Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
32d82067 | 35 | #include <linux/uaccess.h> |
54cf91dc | 36 | |
a415d355 CW |
37 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
38 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 39 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
40 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
41 | ||
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
125 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
126 | list_add_tail(&obj->obj_exec_link, &objects); |
127 | } | |
128 | spin_unlock(&file->table_lock); | |
3b96eff4 | 129 | |
27173f1f | 130 | i = 0; |
9ae9ab52 | 131 | while (!list_empty(&objects)) { |
27173f1f | 132 | struct i915_vma *vma; |
6f65e29a | 133 | |
9ae9ab52 CW |
134 | obj = list_first_entry(&objects, |
135 | struct drm_i915_gem_object, | |
136 | obj_exec_link); | |
137 | ||
e656a6cb DV |
138 | /* |
139 | * NOTE: We can leak any vmas created here when something fails | |
140 | * later on. But that's no issue since vma_unbind can deal with | |
141 | * vmas which are not actually bound. And since only | |
142 | * lookup_or_create exists as an interface to get at the vma | |
143 | * from the (obj, vm) we don't run the risk of creating | |
144 | * duplicated vmas for the same vm. | |
145 | */ | |
da51a1e7 | 146 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 147 | if (IS_ERR(vma)) { |
27173f1f BW |
148 | DRM_DEBUG("Failed to lookup VMA\n"); |
149 | ret = PTR_ERR(vma); | |
9ae9ab52 | 150 | goto err; |
27173f1f BW |
151 | } |
152 | ||
9ae9ab52 | 153 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 154 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 155 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
156 | |
157 | vma->exec_entry = &exec[i]; | |
eef90ccb | 158 | if (eb->and < 0) { |
27173f1f | 159 | eb->lut[i] = vma; |
eef90ccb CW |
160 | } else { |
161 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
162 | vma->exec_handle = handle; |
163 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
164 | &eb->buckets[handle & eb->and]); |
165 | } | |
27173f1f | 166 | ++i; |
3b96eff4 | 167 | } |
3b96eff4 | 168 | |
9ae9ab52 | 169 | return 0; |
27173f1f | 170 | |
27173f1f | 171 | |
9ae9ab52 | 172 | err: |
27173f1f BW |
173 | while (!list_empty(&objects)) { |
174 | obj = list_first_entry(&objects, | |
175 | struct drm_i915_gem_object, | |
176 | obj_exec_link); | |
177 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 178 | drm_gem_object_unreference(&obj->base); |
27173f1f | 179 | } |
9ae9ab52 CW |
180 | /* |
181 | * Objects already transfered to the vmas list will be unreferenced by | |
182 | * eb_destroy. | |
183 | */ | |
184 | ||
27173f1f | 185 | return ret; |
3b96eff4 CW |
186 | } |
187 | ||
27173f1f | 188 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 189 | { |
eef90ccb CW |
190 | if (eb->and < 0) { |
191 | if (handle >= -eb->and) | |
192 | return NULL; | |
193 | return eb->lut[handle]; | |
194 | } else { | |
195 | struct hlist_head *head; | |
196 | struct hlist_node *node; | |
67731b87 | 197 | |
eef90ccb CW |
198 | head = &eb->buckets[handle & eb->and]; |
199 | hlist_for_each(node, head) { | |
27173f1f | 200 | struct i915_vma *vma; |
67731b87 | 201 | |
27173f1f BW |
202 | vma = hlist_entry(node, struct i915_vma, exec_node); |
203 | if (vma->exec_handle == handle) | |
204 | return vma; | |
eef90ccb CW |
205 | } |
206 | return NULL; | |
207 | } | |
67731b87 CW |
208 | } |
209 | ||
a415d355 CW |
210 | static void |
211 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
212 | { | |
213 | struct drm_i915_gem_exec_object2 *entry; | |
214 | struct drm_i915_gem_object *obj = vma->obj; | |
215 | ||
216 | if (!drm_mm_node_allocated(&vma->node)) | |
217 | return; | |
218 | ||
219 | entry = vma->exec_entry; | |
220 | ||
221 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
222 | i915_gem_object_unpin_fence(obj); | |
223 | ||
224 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 225 | vma->pin_count--; |
a415d355 | 226 | |
de4e783a | 227 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); |
a415d355 CW |
228 | } |
229 | ||
230 | static void eb_destroy(struct eb_vmas *eb) | |
231 | { | |
27173f1f BW |
232 | while (!list_empty(&eb->vmas)) { |
233 | struct i915_vma *vma; | |
bcffc3fa | 234 | |
27173f1f BW |
235 | vma = list_first_entry(&eb->vmas, |
236 | struct i915_vma, | |
bcffc3fa | 237 | exec_list); |
27173f1f | 238 | list_del_init(&vma->exec_list); |
a415d355 | 239 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 240 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 241 | } |
67731b87 CW |
242 | kfree(eb); |
243 | } | |
244 | ||
dabdfe02 CW |
245 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
246 | { | |
2cc86b82 CW |
247 | return (HAS_LLC(obj->base.dev) || |
248 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
dabdfe02 CW |
249 | obj->cache_level != I915_CACHE_NONE); |
250 | } | |
251 | ||
5032d871 RB |
252 | static int |
253 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
254 | struct drm_i915_gem_relocation_entry *reloc, |
255 | uint64_t target_offset) | |
5032d871 | 256 | { |
3c94ceee | 257 | struct drm_device *dev = obj->base.dev; |
5032d871 | 258 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 259 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 260 | char *vaddr; |
8b78f0e5 | 261 | int ret; |
5032d871 | 262 | |
2cc86b82 | 263 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
264 | if (ret) |
265 | return ret; | |
266 | ||
267 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
268 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 269 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
270 | |
271 | if (INTEL_INFO(dev)->gen >= 8) { | |
272 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
273 | ||
274 | if (page_offset == 0) { | |
275 | kunmap_atomic(vaddr); | |
276 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
277 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
278 | } | |
279 | ||
d9ceb957 | 280 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
281 | } |
282 | ||
5032d871 RB |
283 | kunmap_atomic(vaddr); |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | static int | |
289 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
290 | struct drm_i915_gem_relocation_entry *reloc, |
291 | uint64_t target_offset) | |
5032d871 RB |
292 | { |
293 | struct drm_device *dev = obj->base.dev; | |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 295 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 296 | uint64_t offset; |
5032d871 | 297 | void __iomem *reloc_page; |
8b78f0e5 | 298 | int ret; |
5032d871 RB |
299 | |
300 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
301 | if (ret) | |
302 | return ret; | |
303 | ||
304 | ret = i915_gem_object_put_fence(obj); | |
305 | if (ret) | |
306 | return ret; | |
307 | ||
308 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
309 | offset = i915_gem_obj_ggtt_offset(obj); |
310 | offset += reloc->offset; | |
5032d871 | 311 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
312 | offset & PAGE_MASK); |
313 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
314 | |
315 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 316 | offset += sizeof(uint32_t); |
3c94ceee | 317 | |
906843c3 | 318 | if (offset_in_page(offset) == 0) { |
3c94ceee | 319 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
320 | reloc_page = |
321 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
322 | offset); | |
3c94ceee BW |
323 | } |
324 | ||
906843c3 CW |
325 | iowrite32(upper_32_bits(delta), |
326 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
327 | } |
328 | ||
5032d871 RB |
329 | io_mapping_unmap_atomic(reloc_page); |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
edf4427b CW |
334 | static void |
335 | clflush_write32(void *addr, uint32_t value) | |
336 | { | |
337 | /* This is not a fast path, so KISS. */ | |
338 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
339 | *(uint32_t *)addr = value; | |
340 | drm_clflush_virt_range(addr, sizeof(uint32_t)); | |
341 | } | |
342 | ||
343 | static int | |
344 | relocate_entry_clflush(struct drm_i915_gem_object *obj, | |
345 | struct drm_i915_gem_relocation_entry *reloc, | |
346 | uint64_t target_offset) | |
347 | { | |
348 | struct drm_device *dev = obj->base.dev; | |
349 | uint32_t page_offset = offset_in_page(reloc->offset); | |
350 | uint64_t delta = (int)reloc->delta + target_offset; | |
351 | char *vaddr; | |
352 | int ret; | |
353 | ||
354 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
355 | if (ret) | |
356 | return ret; | |
357 | ||
358 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
359 | reloc->offset >> PAGE_SHIFT)); | |
360 | clflush_write32(vaddr + page_offset, lower_32_bits(delta)); | |
361 | ||
362 | if (INTEL_INFO(dev)->gen >= 8) { | |
363 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
364 | ||
365 | if (page_offset == 0) { | |
366 | kunmap_atomic(vaddr); | |
367 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
368 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
369 | } | |
370 | ||
371 | clflush_write32(vaddr + page_offset, upper_32_bits(delta)); | |
372 | } | |
373 | ||
374 | kunmap_atomic(vaddr); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
54cf91dc CW |
379 | static int |
380 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 381 | struct eb_vmas *eb, |
3e7a0322 | 382 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
383 | { |
384 | struct drm_device *dev = obj->base.dev; | |
385 | struct drm_gem_object *target_obj; | |
149c8407 | 386 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 387 | struct i915_vma *target_vma; |
d9ceb957 | 388 | uint64_t target_offset; |
8b78f0e5 | 389 | int ret; |
54cf91dc | 390 | |
67731b87 | 391 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
392 | target_vma = eb_get_vma(eb, reloc->target_handle); |
393 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 394 | return -ENOENT; |
27173f1f BW |
395 | target_i915_obj = target_vma->obj; |
396 | target_obj = &target_vma->obj->base; | |
54cf91dc | 397 | |
5ce09725 | 398 | target_offset = target_vma->node.start; |
54cf91dc | 399 | |
e844b990 EA |
400 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
401 | * pipe_control writes because the gpu doesn't properly redirect them | |
402 | * through the ppgtt for non_secure batchbuffers. */ | |
403 | if (unlikely(IS_GEN6(dev) && | |
0875546c | 404 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { |
fe14d5f4 | 405 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, |
0875546c | 406 | PIN_GLOBAL); |
fe14d5f4 TU |
407 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) |
408 | return ret; | |
409 | } | |
e844b990 | 410 | |
54cf91dc | 411 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 412 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 413 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
414 | "obj %p target %d offset %d " |
415 | "read %08x write %08x", | |
416 | obj, reloc->target_handle, | |
417 | (int) reloc->offset, | |
418 | reloc->read_domains, | |
419 | reloc->write_domain); | |
8b78f0e5 | 420 | return -EINVAL; |
54cf91dc | 421 | } |
4ca4a250 DV |
422 | if (unlikely((reloc->write_domain | reloc->read_domains) |
423 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 424 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
425 | "obj %p target %d offset %d " |
426 | "read %08x write %08x", | |
427 | obj, reloc->target_handle, | |
428 | (int) reloc->offset, | |
429 | reloc->read_domains, | |
430 | reloc->write_domain); | |
8b78f0e5 | 431 | return -EINVAL; |
54cf91dc | 432 | } |
54cf91dc CW |
433 | |
434 | target_obj->pending_read_domains |= reloc->read_domains; | |
435 | target_obj->pending_write_domain |= reloc->write_domain; | |
436 | ||
437 | /* If the relocation already has the right value in it, no | |
438 | * more work needs to be done. | |
439 | */ | |
440 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 441 | return 0; |
54cf91dc CW |
442 | |
443 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
444 | if (unlikely(reloc->offset > |
445 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 446 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
447 | "obj %p target %d offset %d size %d.\n", |
448 | obj, reloc->target_handle, | |
449 | (int) reloc->offset, | |
450 | (int) obj->base.size); | |
8b78f0e5 | 451 | return -EINVAL; |
54cf91dc | 452 | } |
b8f7ab17 | 453 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 454 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
455 | "obj %p target %d offset %d.\n", |
456 | obj, reloc->target_handle, | |
457 | (int) reloc->offset); | |
8b78f0e5 | 458 | return -EINVAL; |
54cf91dc CW |
459 | } |
460 | ||
dabdfe02 | 461 | /* We can't wait for rendering with pagefaults disabled */ |
32d82067 | 462 | if (obj->active && pagefault_disabled()) |
dabdfe02 CW |
463 | return -EFAULT; |
464 | ||
5032d871 | 465 | if (use_cpu_reloc(obj)) |
d9ceb957 | 466 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
edf4427b | 467 | else if (obj->map_and_fenceable) |
d9ceb957 | 468 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
edf4427b CW |
469 | else if (cpu_has_clflush) |
470 | ret = relocate_entry_clflush(obj, reloc, target_offset); | |
471 | else { | |
472 | WARN_ONCE(1, "Impossible case in relocation handling\n"); | |
473 | ret = -ENODEV; | |
474 | } | |
54cf91dc | 475 | |
d4d36014 DV |
476 | if (ret) |
477 | return ret; | |
478 | ||
54cf91dc CW |
479 | /* and update the user's relocation entry */ |
480 | reloc->presumed_offset = target_offset; | |
481 | ||
67731b87 | 482 | return 0; |
54cf91dc CW |
483 | } |
484 | ||
485 | static int | |
27173f1f BW |
486 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
487 | struct eb_vmas *eb) | |
54cf91dc | 488 | { |
1d83f442 CW |
489 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
490 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 491 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 492 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 493 | int remain, ret; |
54cf91dc | 494 | |
2bb4629a | 495 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 496 | |
1d83f442 CW |
497 | remain = entry->relocation_count; |
498 | while (remain) { | |
499 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
500 | int count = remain; | |
501 | if (count > ARRAY_SIZE(stack_reloc)) | |
502 | count = ARRAY_SIZE(stack_reloc); | |
503 | remain -= count; | |
504 | ||
505 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
506 | return -EFAULT; |
507 | ||
1d83f442 CW |
508 | do { |
509 | u64 offset = r->presumed_offset; | |
54cf91dc | 510 | |
3e7a0322 | 511 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
512 | if (ret) |
513 | return ret; | |
514 | ||
515 | if (r->presumed_offset != offset && | |
516 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
517 | &r->presumed_offset, | |
518 | sizeof(r->presumed_offset))) { | |
519 | return -EFAULT; | |
520 | } | |
521 | ||
522 | user_relocs++; | |
523 | r++; | |
524 | } while (--count); | |
54cf91dc CW |
525 | } |
526 | ||
527 | return 0; | |
1d83f442 | 528 | #undef N_RELOC |
54cf91dc CW |
529 | } |
530 | ||
531 | static int | |
27173f1f BW |
532 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
533 | struct eb_vmas *eb, | |
534 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 535 | { |
27173f1f | 536 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
537 | int i, ret; |
538 | ||
539 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 540 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
541 | if (ret) |
542 | return ret; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | static int | |
17601cbc | 549 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 550 | { |
27173f1f | 551 | struct i915_vma *vma; |
d4aeee77 CW |
552 | int ret = 0; |
553 | ||
554 | /* This is the fast path and we cannot handle a pagefault whilst | |
555 | * holding the struct mutex lest the user pass in the relocations | |
556 | * contained within a mmaped bo. For in such a case we, the page | |
557 | * fault handler would call i915_gem_fault() and we would try to | |
558 | * acquire the struct mutex again. Obviously this is bad and so | |
559 | * lockdep complains vehemently. | |
560 | */ | |
561 | pagefault_disable(); | |
27173f1f BW |
562 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
563 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 564 | if (ret) |
d4aeee77 | 565 | break; |
54cf91dc | 566 | } |
d4aeee77 | 567 | pagefault_enable(); |
54cf91dc | 568 | |
d4aeee77 | 569 | return ret; |
54cf91dc CW |
570 | } |
571 | ||
edf4427b CW |
572 | static bool only_mappable_for_reloc(unsigned int flags) |
573 | { | |
574 | return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == | |
575 | __EXEC_OBJECT_NEEDS_MAP; | |
576 | } | |
577 | ||
1690e1eb | 578 | static int |
27173f1f | 579 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 580 | struct intel_engine_cs *ring, |
27173f1f | 581 | bool *need_reloc) |
1690e1eb | 582 | { |
6f65e29a | 583 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 584 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 585 | uint64_t flags; |
1690e1eb CW |
586 | int ret; |
587 | ||
0875546c | 588 | flags = PIN_USER; |
0229da32 DV |
589 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
590 | flags |= PIN_GLOBAL; | |
591 | ||
edf4427b CW |
592 | if (!drm_mm_node_allocated(&vma->node)) { |
593 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) | |
594 | flags |= PIN_GLOBAL | PIN_MAPPABLE; | |
edf4427b CW |
595 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
596 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
597 | } | |
1ec9e26d DV |
598 | |
599 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
edf4427b CW |
600 | if ((ret == -ENOSPC || ret == -E2BIG) && |
601 | only_mappable_for_reloc(entry->flags)) | |
602 | ret = i915_gem_object_pin(obj, vma->vm, | |
603 | entry->alignment, | |
0229da32 | 604 | flags & ~PIN_MAPPABLE); |
1690e1eb CW |
605 | if (ret) |
606 | return ret; | |
607 | ||
7788a765 CW |
608 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
609 | ||
82b6b6d7 CW |
610 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
611 | ret = i915_gem_object_get_fence(obj); | |
612 | if (ret) | |
613 | return ret; | |
9a5a53b3 | 614 | |
82b6b6d7 CW |
615 | if (i915_gem_object_pin_fence(obj)) |
616 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
617 | } |
618 | ||
27173f1f BW |
619 | if (entry->offset != vma->node.start) { |
620 | entry->offset = vma->node.start; | |
ed5982e6 DV |
621 | *need_reloc = true; |
622 | } | |
623 | ||
624 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
625 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
626 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
627 | } | |
628 | ||
1690e1eb | 629 | return 0; |
7788a765 | 630 | } |
1690e1eb | 631 | |
d23db88c | 632 | static bool |
e6a84468 | 633 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
634 | { |
635 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 636 | |
e6a84468 CW |
637 | if (entry->relocation_count == 0) |
638 | return false; | |
639 | ||
640 | if (!i915_is_ggtt(vma->vm)) | |
641 | return false; | |
642 | ||
643 | /* See also use_cpu_reloc() */ | |
644 | if (HAS_LLC(vma->obj->base.dev)) | |
645 | return false; | |
646 | ||
647 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
648 | return false; | |
649 | ||
650 | return true; | |
651 | } | |
652 | ||
653 | static bool | |
654 | eb_vma_misplaced(struct i915_vma *vma) | |
655 | { | |
656 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
657 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 658 | |
e6a84468 | 659 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
660 | !i915_is_ggtt(vma->vm)); |
661 | ||
662 | if (entry->alignment && | |
663 | vma->node.start & (entry->alignment - 1)) | |
664 | return true; | |
665 | ||
d23db88c CW |
666 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && |
667 | vma->node.start < BATCH_OFFSET_BIAS) | |
668 | return true; | |
669 | ||
edf4427b CW |
670 | /* avoid costly ping-pong once a batch bo ended up non-mappable */ |
671 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) | |
672 | return !only_mappable_for_reloc(entry->flags); | |
673 | ||
d23db88c CW |
674 | return false; |
675 | } | |
676 | ||
54cf91dc | 677 | static int |
a4872ba6 | 678 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 679 | struct list_head *vmas, |
b1b38278 | 680 | struct intel_context *ctx, |
ed5982e6 | 681 | bool *need_relocs) |
54cf91dc | 682 | { |
432e58ed | 683 | struct drm_i915_gem_object *obj; |
27173f1f | 684 | struct i915_vma *vma; |
68c8c17f | 685 | struct i915_address_space *vm; |
27173f1f | 686 | struct list_head ordered_vmas; |
7788a765 CW |
687 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
688 | int retry; | |
6fe4f140 | 689 | |
227f782e CW |
690 | i915_gem_retire_requests_ring(ring); |
691 | ||
68c8c17f BW |
692 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
693 | ||
27173f1f BW |
694 | INIT_LIST_HEAD(&ordered_vmas); |
695 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
696 | struct drm_i915_gem_exec_object2 *entry; |
697 | bool need_fence, need_mappable; | |
698 | ||
27173f1f BW |
699 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
700 | obj = vma->obj; | |
701 | entry = vma->exec_entry; | |
6fe4f140 | 702 | |
b1b38278 DW |
703 | if (ctx->flags & CONTEXT_NO_ZEROMAP) |
704 | entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
705 | ||
82b6b6d7 CW |
706 | if (!has_fenced_gpu_access) |
707 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 708 | need_fence = |
6fe4f140 CW |
709 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
710 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 711 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 712 | |
e6a84468 CW |
713 | if (need_mappable) { |
714 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; | |
27173f1f | 715 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 716 | } else |
27173f1f | 717 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 718 | |
ed5982e6 | 719 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 720 | obj->base.pending_write_domain = 0; |
6fe4f140 | 721 | } |
27173f1f | 722 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
723 | |
724 | /* Attempt to pin all of the buffers into the GTT. | |
725 | * This is done in 3 phases: | |
726 | * | |
727 | * 1a. Unbind all objects that do not match the GTT constraints for | |
728 | * the execbuffer (fenceable, mappable, alignment etc). | |
729 | * 1b. Increment pin count for already bound objects. | |
730 | * 2. Bind new objects. | |
731 | * 3. Decrement pin count. | |
732 | * | |
7788a765 | 733 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
734 | * room for the earlier objects *unless* we need to defragment. |
735 | */ | |
736 | retry = 0; | |
737 | do { | |
7788a765 | 738 | int ret = 0; |
54cf91dc CW |
739 | |
740 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 741 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 742 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
743 | continue; |
744 | ||
e6a84468 | 745 | if (eb_vma_misplaced(vma)) |
27173f1f | 746 | ret = i915_vma_unbind(vma); |
54cf91dc | 747 | else |
27173f1f | 748 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 749 | if (ret) |
54cf91dc | 750 | goto err; |
54cf91dc CW |
751 | } |
752 | ||
753 | /* Bind fresh objects */ | |
27173f1f BW |
754 | list_for_each_entry(vma, vmas, exec_list) { |
755 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 756 | continue; |
54cf91dc | 757 | |
27173f1f | 758 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
759 | if (ret) |
760 | goto err; | |
54cf91dc CW |
761 | } |
762 | ||
a415d355 | 763 | err: |
6c085a72 | 764 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
765 | return ret; |
766 | ||
a415d355 CW |
767 | /* Decrement pin count for bound objects */ |
768 | list_for_each_entry(vma, vmas, exec_list) | |
769 | i915_gem_execbuffer_unreserve_vma(vma); | |
770 | ||
68c8c17f | 771 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
772 | if (ret) |
773 | return ret; | |
54cf91dc CW |
774 | } while (1); |
775 | } | |
776 | ||
777 | static int | |
778 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 779 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 780 | struct drm_file *file, |
a4872ba6 | 781 | struct intel_engine_cs *ring, |
27173f1f | 782 | struct eb_vmas *eb, |
b1b38278 DW |
783 | struct drm_i915_gem_exec_object2 *exec, |
784 | struct intel_context *ctx) | |
54cf91dc CW |
785 | { |
786 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
787 | struct i915_address_space *vm; |
788 | struct i915_vma *vma; | |
ed5982e6 | 789 | bool need_relocs; |
dd6864a4 | 790 | int *reloc_offset; |
54cf91dc | 791 | int i, total, ret; |
b205ca57 | 792 | unsigned count = args->buffer_count; |
54cf91dc | 793 | |
27173f1f BW |
794 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
795 | ||
67731b87 | 796 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
797 | while (!list_empty(&eb->vmas)) { |
798 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
799 | list_del_init(&vma->exec_list); | |
a415d355 | 800 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 801 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
802 | } |
803 | ||
54cf91dc CW |
804 | mutex_unlock(&dev->struct_mutex); |
805 | ||
806 | total = 0; | |
807 | for (i = 0; i < count; i++) | |
432e58ed | 808 | total += exec[i].relocation_count; |
54cf91dc | 809 | |
dd6864a4 | 810 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 811 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
812 | if (reloc == NULL || reloc_offset == NULL) { |
813 | drm_free_large(reloc); | |
814 | drm_free_large(reloc_offset); | |
54cf91dc CW |
815 | mutex_lock(&dev->struct_mutex); |
816 | return -ENOMEM; | |
817 | } | |
818 | ||
819 | total = 0; | |
820 | for (i = 0; i < count; i++) { | |
821 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
822 | u64 invalid_offset = (u64)-1; |
823 | int j; | |
54cf91dc | 824 | |
2bb4629a | 825 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
826 | |
827 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 828 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
829 | ret = -EFAULT; |
830 | mutex_lock(&dev->struct_mutex); | |
831 | goto err; | |
832 | } | |
833 | ||
262b6d36 CW |
834 | /* As we do not update the known relocation offsets after |
835 | * relocating (due to the complexities in lock handling), | |
836 | * we need to mark them as invalid now so that we force the | |
837 | * relocation processing next time. Just in case the target | |
838 | * object is evicted and then rebound into its old | |
839 | * presumed_offset before the next execbuffer - if that | |
840 | * happened we would make the mistake of assuming that the | |
841 | * relocations were valid. | |
842 | */ | |
843 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
844 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
845 | &invalid_offset, | |
846 | sizeof(invalid_offset))) { | |
262b6d36 CW |
847 | ret = -EFAULT; |
848 | mutex_lock(&dev->struct_mutex); | |
849 | goto err; | |
850 | } | |
851 | } | |
852 | ||
dd6864a4 | 853 | reloc_offset[i] = total; |
432e58ed | 854 | total += exec[i].relocation_count; |
54cf91dc CW |
855 | } |
856 | ||
857 | ret = i915_mutex_lock_interruptible(dev); | |
858 | if (ret) { | |
859 | mutex_lock(&dev->struct_mutex); | |
860 | goto err; | |
861 | } | |
862 | ||
67731b87 | 863 | /* reacquire the objects */ |
67731b87 | 864 | eb_reset(eb); |
27173f1f | 865 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
866 | if (ret) |
867 | goto err; | |
67731b87 | 868 | |
ed5982e6 | 869 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 870 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
871 | if (ret) |
872 | goto err; | |
873 | ||
27173f1f BW |
874 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
875 | int offset = vma->exec_entry - exec; | |
876 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
877 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
878 | if (ret) |
879 | goto err; | |
54cf91dc CW |
880 | } |
881 | ||
882 | /* Leave the user relocations as are, this is the painfully slow path, | |
883 | * and we want to avoid the complication of dropping the lock whilst | |
884 | * having buffers reserved in the aperture and so causing spurious | |
885 | * ENOSPC for random operations. | |
886 | */ | |
887 | ||
888 | err: | |
889 | drm_free_large(reloc); | |
dd6864a4 | 890 | drm_free_large(reloc_offset); |
54cf91dc CW |
891 | return ret; |
892 | } | |
893 | ||
54cf91dc | 894 | static int |
535fbe82 | 895 | i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, |
27173f1f | 896 | struct list_head *vmas) |
54cf91dc | 897 | { |
535fbe82 | 898 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
27173f1f | 899 | struct i915_vma *vma; |
6ac42f41 | 900 | uint32_t flush_domains = 0; |
000433b6 | 901 | bool flush_chipset = false; |
432e58ed | 902 | int ret; |
54cf91dc | 903 | |
27173f1f BW |
904 | list_for_each_entry(vma, vmas, exec_list) { |
905 | struct drm_i915_gem_object *obj = vma->obj; | |
03ade511 CW |
906 | |
907 | if (obj->active & other_rings) { | |
91af127f | 908 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
909 | if (ret) |
910 | return ret; | |
911 | } | |
6ac42f41 DV |
912 | |
913 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 914 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 915 | |
6ac42f41 | 916 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
917 | } |
918 | ||
000433b6 | 919 | if (flush_chipset) |
535fbe82 | 920 | i915_gem_chipset_flush(req->ring->dev); |
6ac42f41 DV |
921 | |
922 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
923 | wmb(); | |
924 | ||
09cf7c9a CW |
925 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
926 | * any residual writes from the previous batch. | |
927 | */ | |
2f20055d | 928 | return intel_ring_invalidate_all_caches(req); |
54cf91dc CW |
929 | } |
930 | ||
432e58ed CW |
931 | static bool |
932 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 933 | { |
ed5982e6 DV |
934 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
935 | return false; | |
936 | ||
432e58ed | 937 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
938 | } |
939 | ||
940 | static int | |
ad19f10b CW |
941 | validate_exec_list(struct drm_device *dev, |
942 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
943 | int count) |
944 | { | |
b205ca57 DV |
945 | unsigned relocs_total = 0; |
946 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
947 | unsigned invalid_flags; |
948 | int i; | |
949 | ||
950 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
951 | if (USES_FULL_PPGTT(dev)) | |
952 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
953 | |
954 | for (i = 0; i < count; i++) { | |
2bb4629a | 955 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
956 | int length; /* limited by fault_in_pages_readable() */ |
957 | ||
ad19f10b | 958 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
959 | return -EINVAL; |
960 | ||
55a9785d CW |
961 | if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) |
962 | return -EINVAL; | |
963 | ||
3118a4f6 KC |
964 | /* First check for malicious input causing overflow in |
965 | * the worst case where we need to allocate the entire | |
966 | * relocation tree as a single array. | |
967 | */ | |
968 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 969 | return -EINVAL; |
3118a4f6 | 970 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
971 | |
972 | length = exec[i].relocation_count * | |
973 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
974 | /* |
975 | * We must check that the entire relocation array is safe | |
976 | * to read, but since we may need to update the presumed | |
977 | * offsets during execution, check for full write access. | |
978 | */ | |
54cf91dc CW |
979 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
980 | return -EFAULT; | |
981 | ||
d330a953 | 982 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
983 | if (fault_in_multipages_readable(ptr, length)) |
984 | return -EFAULT; | |
985 | } | |
54cf91dc CW |
986 | } |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
273497e5 | 991 | static struct intel_context * |
d299cce7 | 992 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 993 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 994 | { |
273497e5 | 995 | struct intel_context *ctx = NULL; |
d299cce7 MK |
996 | struct i915_ctx_hang_stats *hs; |
997 | ||
821d66dd | 998 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
999 | return ERR_PTR(-EINVAL); |
1000 | ||
41bde553 | 1001 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 1002 | if (IS_ERR(ctx)) |
41bde553 | 1003 | return ctx; |
d299cce7 | 1004 | |
41bde553 | 1005 | hs = &ctx->hang_stats; |
d299cce7 MK |
1006 | if (hs->banned) { |
1007 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 1008 | return ERR_PTR(-EIO); |
d299cce7 MK |
1009 | } |
1010 | ||
ec3e9963 OM |
1011 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
1012 | int ret = intel_lr_context_deferred_create(ctx, ring); | |
1013 | if (ret) { | |
1014 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
1015 | return ERR_PTR(ret); | |
1016 | } | |
1017 | } | |
1018 | ||
41bde553 | 1019 | return ctx; |
d299cce7 MK |
1020 | } |
1021 | ||
ba8b7ccb | 1022 | void |
27173f1f | 1023 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 1024 | struct drm_i915_gem_request *req) |
432e58ed | 1025 | { |
8a8edb59 | 1026 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
27173f1f | 1027 | struct i915_vma *vma; |
432e58ed | 1028 | |
27173f1f | 1029 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 1030 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 1031 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
1032 | u32 old_read = obj->base.read_domains; |
1033 | u32 old_write = obj->base.write_domain; | |
db53a302 | 1034 | |
432e58ed | 1035 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
1036 | if (obj->base.write_domain == 0) |
1037 | obj->base.pending_read_domains |= obj->base.read_domains; | |
1038 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 1039 | |
b2af0376 | 1040 | i915_vma_move_to_active(vma, req); |
432e58ed CW |
1041 | if (obj->base.write_domain) { |
1042 | obj->dirty = 1; | |
97b2a6a1 | 1043 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 | 1044 | |
77a0d1ca | 1045 | intel_fb_obj_invalidate(obj, ORIGIN_CS); |
c8725f3d CW |
1046 | |
1047 | /* update for the implicit flush after a batch */ | |
1048 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 1049 | } |
82b6b6d7 | 1050 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 1051 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
1052 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
1053 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1054 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
1055 | &dev_priv->mm.fence_list); | |
1056 | } | |
1057 | } | |
432e58ed | 1058 | |
db53a302 | 1059 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
1060 | } |
1061 | } | |
1062 | ||
ba8b7ccb | 1063 | void |
adeca76d | 1064 | i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) |
54cf91dc | 1065 | { |
cc889e0f | 1066 | /* Unconditionally force add_request to emit a full flush. */ |
adeca76d | 1067 | params->ring->gpu_caches_dirty = true; |
54cf91dc | 1068 | |
432e58ed | 1069 | /* Add a breadcrumb for the completion of the batch buffer */ |
fcfa423c | 1070 | __i915_add_request(params->request, params->batch_obj, true); |
432e58ed | 1071 | } |
54cf91dc | 1072 | |
ae662d31 EA |
1073 | static int |
1074 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
2f20055d | 1075 | struct drm_i915_gem_request *req) |
ae662d31 | 1076 | { |
2f20055d | 1077 | struct intel_engine_cs *ring = req->ring; |
50227e1c | 1078 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1079 | int ret, i; |
1080 | ||
9d662da8 DV |
1081 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1082 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1083 | return -EINVAL; | |
1084 | } | |
ae662d31 | 1085 | |
5fb9de1a | 1086 | ret = intel_ring_begin(req, 4 * 3); |
ae662d31 EA |
1087 | if (ret) |
1088 | return ret; | |
1089 | ||
1090 | for (i = 0; i < 4; i++) { | |
1091 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1092 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1093 | intel_ring_emit(ring, 0); | |
1094 | } | |
1095 | ||
1096 | intel_ring_advance(ring); | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
5c6c6003 | 1101 | static int |
2f20055d | 1102 | i915_emit_box(struct drm_i915_gem_request *req, |
5c6c6003 CW |
1103 | struct drm_clip_rect *box, |
1104 | int DR1, int DR4) | |
1105 | { | |
2f20055d | 1106 | struct intel_engine_cs *ring = req->ring; |
5c6c6003 CW |
1107 | int ret; |
1108 | ||
1109 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || | |
1110 | box->y2 <= 0 || box->x2 <= 0) { | |
1111 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
1112 | box->x1, box->y1, box->x2, box->y2); | |
1113 | return -EINVAL; | |
1114 | } | |
1115 | ||
1116 | if (INTEL_INFO(ring->dev)->gen >= 4) { | |
5fb9de1a | 1117 | ret = intel_ring_begin(req, 4); |
5c6c6003 CW |
1118 | if (ret) |
1119 | return ret; | |
1120 | ||
1121 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); | |
1122 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1123 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1124 | intel_ring_emit(ring, DR4); | |
1125 | } else { | |
5fb9de1a | 1126 | ret = intel_ring_begin(req, 6); |
5c6c6003 CW |
1127 | if (ret) |
1128 | return ret; | |
1129 | ||
1130 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); | |
1131 | intel_ring_emit(ring, DR1); | |
1132 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1133 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1134 | intel_ring_emit(ring, DR4); | |
1135 | intel_ring_emit(ring, 0); | |
1136 | } | |
1137 | intel_ring_advance(ring); | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
71745376 BV |
1142 | static struct drm_i915_gem_object* |
1143 | i915_gem_execbuffer_parse(struct intel_engine_cs *ring, | |
1144 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, | |
1145 | struct eb_vmas *eb, | |
1146 | struct drm_i915_gem_object *batch_obj, | |
1147 | u32 batch_start_offset, | |
1148 | u32 batch_len, | |
17cabf57 | 1149 | bool is_master) |
71745376 | 1150 | { |
71745376 | 1151 | struct drm_i915_gem_object *shadow_batch_obj; |
17cabf57 | 1152 | struct i915_vma *vma; |
71745376 BV |
1153 | int ret; |
1154 | ||
06fbca71 | 1155 | shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, |
17cabf57 | 1156 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1157 | if (IS_ERR(shadow_batch_obj)) |
1158 | return shadow_batch_obj; | |
1159 | ||
1160 | ret = i915_parse_cmds(ring, | |
1161 | batch_obj, | |
1162 | shadow_batch_obj, | |
1163 | batch_start_offset, | |
1164 | batch_len, | |
1165 | is_master); | |
17cabf57 CW |
1166 | if (ret) |
1167 | goto err; | |
71745376 | 1168 | |
17cabf57 CW |
1169 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1170 | if (ret) | |
1171 | goto err; | |
71745376 | 1172 | |
de4e783a CW |
1173 | i915_gem_object_unpin_pages(shadow_batch_obj); |
1174 | ||
17cabf57 | 1175 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1176 | |
17cabf57 CW |
1177 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1178 | vma->exec_entry = shadow_exec_entry; | |
de4e783a | 1179 | vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; |
17cabf57 CW |
1180 | drm_gem_object_reference(&shadow_batch_obj->base); |
1181 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1182 | |
17cabf57 CW |
1183 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1184 | ||
1185 | return shadow_batch_obj; | |
71745376 | 1186 | |
17cabf57 | 1187 | err: |
de4e783a | 1188 | i915_gem_object_unpin_pages(shadow_batch_obj); |
17cabf57 CW |
1189 | if (ret == -EACCES) /* unhandled chained batch */ |
1190 | return batch_obj; | |
1191 | else | |
1192 | return ERR_PTR(ret); | |
71745376 | 1193 | } |
5c6c6003 | 1194 | |
a83014d3 | 1195 | int |
5f19e2bf | 1196 | i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 1197 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1198 | struct list_head *vmas) |
78382593 OM |
1199 | { |
1200 | struct drm_clip_rect *cliprects = NULL; | |
5f19e2bf JH |
1201 | struct drm_device *dev = params->dev; |
1202 | struct intel_engine_cs *ring = params->ring; | |
78382593 | 1203 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf | 1204 | u64 exec_start, exec_len; |
78382593 OM |
1205 | int instp_mode; |
1206 | u32 instp_mask; | |
1207 | int i, ret = 0; | |
1208 | ||
1209 | if (args->num_cliprects != 0) { | |
1210 | if (ring != &dev_priv->ring[RCS]) { | |
1211 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); | |
1212 | return -EINVAL; | |
1213 | } | |
1214 | ||
1215 | if (INTEL_INFO(dev)->gen >= 5) { | |
1216 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1217 | return -EINVAL; | |
1218 | } | |
1219 | ||
1220 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { | |
1221 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1222 | args->num_cliprects); | |
1223 | return -EINVAL; | |
1224 | } | |
1225 | ||
1226 | cliprects = kcalloc(args->num_cliprects, | |
1227 | sizeof(*cliprects), | |
1228 | GFP_KERNEL); | |
1229 | if (cliprects == NULL) { | |
1230 | ret = -ENOMEM; | |
1231 | goto error; | |
1232 | } | |
1233 | ||
1234 | if (copy_from_user(cliprects, | |
1235 | to_user_ptr(args->cliprects_ptr), | |
1236 | sizeof(*cliprects)*args->num_cliprects)) { | |
1237 | ret = -EFAULT; | |
1238 | goto error; | |
1239 | } | |
1240 | } else { | |
1241 | if (args->DR4 == 0xffffffff) { | |
1242 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1243 | args->DR4 = 0; | |
1244 | } | |
1245 | ||
1246 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
1247 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | } | |
1251 | ||
535fbe82 | 1252 | ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); |
78382593 OM |
1253 | if (ret) |
1254 | goto error; | |
1255 | ||
ba01cc93 | 1256 | ret = i915_switch_context(params->request); |
78382593 OM |
1257 | if (ret) |
1258 | goto error; | |
1259 | ||
5f19e2bf | 1260 | WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id), |
9258811c | 1261 | "%s didn't clear reload\n", ring->name); |
563222a7 | 1262 | |
78382593 OM |
1263 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; |
1264 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1265 | switch (instp_mode) { | |
1266 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1267 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1268 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1269 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1270 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1271 | ret = -EINVAL; | |
1272 | goto error; | |
1273 | } | |
1274 | ||
1275 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1276 | if (INTEL_INFO(dev)->gen < 4) { | |
1277 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
1278 | ret = -EINVAL; | |
1279 | goto error; | |
1280 | } | |
1281 | ||
1282 | if (INTEL_INFO(dev)->gen > 5 && | |
1283 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1284 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
1285 | ret = -EINVAL; | |
1286 | goto error; | |
1287 | } | |
1288 | ||
1289 | /* The HW changed the meaning on this bit on gen6 */ | |
1290 | if (INTEL_INFO(dev)->gen >= 6) | |
1291 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1292 | } | |
1293 | break; | |
1294 | default: | |
1295 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
1296 | ret = -EINVAL; | |
1297 | goto error; | |
1298 | } | |
1299 | ||
1300 | if (ring == &dev_priv->ring[RCS] && | |
1301 | instp_mode != dev_priv->relative_constants_mode) { | |
5fb9de1a | 1302 | ret = intel_ring_begin(params->request, 4); |
78382593 OM |
1303 | if (ret) |
1304 | goto error; | |
1305 | ||
1306 | intel_ring_emit(ring, MI_NOOP); | |
1307 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1308 | intel_ring_emit(ring, INSTPM); | |
1309 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1310 | intel_ring_advance(ring); | |
1311 | ||
1312 | dev_priv->relative_constants_mode = instp_mode; | |
1313 | } | |
1314 | ||
1315 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
2f20055d | 1316 | ret = i915_reset_gen7_sol_offsets(dev, params->request); |
78382593 OM |
1317 | if (ret) |
1318 | goto error; | |
1319 | } | |
1320 | ||
5f19e2bf JH |
1321 | exec_len = args->batch_len; |
1322 | exec_start = params->batch_obj_vm_offset + | |
1323 | params->args_batch_start_offset; | |
1324 | ||
78382593 OM |
1325 | if (cliprects) { |
1326 | for (i = 0; i < args->num_cliprects; i++) { | |
2f20055d | 1327 | ret = i915_emit_box(params->request, &cliprects[i], |
78382593 OM |
1328 | args->DR1, args->DR4); |
1329 | if (ret) | |
1330 | goto error; | |
1331 | ||
53fddaf7 | 1332 | ret = ring->dispatch_execbuffer(params->request, |
78382593 | 1333 | exec_start, exec_len, |
5f19e2bf | 1334 | params->dispatch_flags); |
78382593 OM |
1335 | if (ret) |
1336 | goto error; | |
1337 | } | |
1338 | } else { | |
53fddaf7 | 1339 | ret = ring->dispatch_execbuffer(params->request, |
78382593 | 1340 | exec_start, exec_len, |
5f19e2bf | 1341 | params->dispatch_flags); |
78382593 OM |
1342 | if (ret) |
1343 | return ret; | |
1344 | } | |
1345 | ||
95c24161 | 1346 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
78382593 | 1347 | |
8a8edb59 | 1348 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1349 | i915_gem_execbuffer_retire_commands(params); |
78382593 OM |
1350 | |
1351 | error: | |
1352 | kfree(cliprects); | |
1353 | return ret; | |
1354 | } | |
1355 | ||
a8ebba75 ZY |
1356 | /** |
1357 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1358 | * The Ring ID is returned. | |
1359 | */ | |
1360 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1361 | struct drm_file *file) | |
1362 | { | |
1363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1364 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1365 | ||
1366 | /* Check whether the file_priv is using one ring */ | |
1367 | if (file_priv->bsd_ring) | |
1368 | return file_priv->bsd_ring->id; | |
1369 | else { | |
1370 | /* If no, use the ping-pong mechanism to select one ring */ | |
1371 | int ring_id; | |
1372 | ||
1373 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1374 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1375 | ring_id = VCS; |
bdf1e7e3 | 1376 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1377 | } else { |
1378 | ring_id = VCS2; | |
bdf1e7e3 | 1379 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1380 | } |
1381 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1382 | mutex_unlock(&dev->struct_mutex); | |
1383 | return ring_id; | |
1384 | } | |
1385 | } | |
1386 | ||
d23db88c CW |
1387 | static struct drm_i915_gem_object * |
1388 | eb_get_batch(struct eb_vmas *eb) | |
1389 | { | |
1390 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1391 | ||
1392 | /* | |
1393 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1394 | * to negative relocation deltas. Usually that works out ok since the | |
1395 | * relocate address is still positive, except when the batch is placed | |
1396 | * very low in the GTT. Ensure this doesn't happen. | |
1397 | * | |
1398 | * Note that actual hangs have only been observed on gen7, but for | |
1399 | * paranoia do it everywhere. | |
1400 | */ | |
1401 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1402 | ||
1403 | return vma->obj; | |
1404 | } | |
1405 | ||
54cf91dc CW |
1406 | static int |
1407 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1408 | struct drm_file *file, | |
1409 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1410 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1411 | { |
50227e1c | 1412 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1413 | struct eb_vmas *eb; |
54cf91dc | 1414 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1415 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
a4872ba6 | 1416 | struct intel_engine_cs *ring; |
273497e5 | 1417 | struct intel_context *ctx; |
41bde553 | 1418 | struct i915_address_space *vm; |
5f19e2bf JH |
1419 | struct i915_execbuffer_params params_master; /* XXX: will be removed later */ |
1420 | struct i915_execbuffer_params *params = ¶ms_master; | |
d299cce7 | 1421 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
8e004efc | 1422 | u32 dispatch_flags; |
78382593 | 1423 | int ret; |
ed5982e6 | 1424 | bool need_relocs; |
54cf91dc | 1425 | |
ed5982e6 | 1426 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1427 | return -EINVAL; |
432e58ed | 1428 | |
ad19f10b | 1429 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1430 | if (ret) |
1431 | return ret; | |
1432 | ||
8e004efc | 1433 | dispatch_flags = 0; |
d7d4eedd CW |
1434 | if (args->flags & I915_EXEC_SECURE) { |
1435 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1436 | return -EPERM; | |
1437 | ||
8e004efc | 1438 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1439 | } |
b45305fc | 1440 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1441 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1442 | |
b1a93306 | 1443 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1444 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1445 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1446 | return -EINVAL; | |
1447 | } | |
ca01b12b | 1448 | |
8d360dff ZG |
1449 | if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) && |
1450 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1451 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1452 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1453 | return -EINVAL; | |
1454 | } | |
1455 | ||
ca01b12b BW |
1456 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) |
1457 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1458 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1459 | if (HAS_BSD2(dev)) { | |
1460 | int ring_id; | |
8d360dff ZG |
1461 | |
1462 | switch (args->flags & I915_EXEC_BSD_MASK) { | |
1463 | case I915_EXEC_BSD_DEFAULT: | |
1464 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1465 | ring = &dev_priv->ring[ring_id]; | |
1466 | break; | |
1467 | case I915_EXEC_BSD_RING1: | |
1468 | ring = &dev_priv->ring[VCS]; | |
1469 | break; | |
1470 | case I915_EXEC_BSD_RING2: | |
1471 | ring = &dev_priv->ring[VCS2]; | |
1472 | break; | |
1473 | default: | |
1474 | DRM_DEBUG("execbuf with unknown bsd ring: %d\n", | |
1475 | (int)(args->flags & I915_EXEC_BSD_MASK)); | |
1476 | return -EINVAL; | |
1477 | } | |
a8ebba75 ZY |
1478 | } else |
1479 | ring = &dev_priv->ring[VCS]; | |
1480 | } else | |
ca01b12b BW |
1481 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1482 | ||
a15817cf CW |
1483 | if (!intel_ring_initialized(ring)) { |
1484 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1485 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1486 | return -EINVAL; | |
1487 | } | |
54cf91dc CW |
1488 | |
1489 | if (args->buffer_count < 1) { | |
ff240199 | 1490 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1491 | return -EINVAL; |
1492 | } | |
54cf91dc | 1493 | |
a9ed33ca AJ |
1494 | if (args->flags & I915_EXEC_RESOURCE_STREAMER) { |
1495 | if (!HAS_RESOURCE_STREAMER(dev)) { | |
1496 | DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); | |
1497 | return -EINVAL; | |
1498 | } | |
1499 | if (ring->id != RCS) { | |
1500 | DRM_DEBUG("RS is not available on %s\n", | |
1501 | ring->name); | |
1502 | return -EINVAL; | |
1503 | } | |
1504 | ||
1505 | dispatch_flags |= I915_DISPATCH_RS; | |
1506 | } | |
1507 | ||
f65c9168 PZ |
1508 | intel_runtime_pm_get(dev_priv); |
1509 | ||
54cf91dc CW |
1510 | ret = i915_mutex_lock_interruptible(dev); |
1511 | if (ret) | |
1512 | goto pre_mutex_err; | |
1513 | ||
7c9c4b8f | 1514 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1515 | if (IS_ERR(ctx)) { |
d299cce7 | 1516 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1517 | ret = PTR_ERR(ctx); |
d299cce7 | 1518 | goto pre_mutex_err; |
935f38d6 | 1519 | } |
41bde553 BW |
1520 | |
1521 | i915_gem_context_reference(ctx); | |
1522 | ||
ae6c4806 DV |
1523 | if (ctx->ppgtt) |
1524 | vm = &ctx->ppgtt->base; | |
1525 | else | |
7e0d96bc | 1526 | vm = &dev_priv->gtt.base; |
d299cce7 | 1527 | |
5f19e2bf JH |
1528 | memset(¶ms_master, 0x00, sizeof(params_master)); |
1529 | ||
17601cbc | 1530 | eb = eb_create(args); |
67731b87 | 1531 | if (eb == NULL) { |
935f38d6 | 1532 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1533 | mutex_unlock(&dev->struct_mutex); |
1534 | ret = -ENOMEM; | |
1535 | goto pre_mutex_err; | |
1536 | } | |
1537 | ||
54cf91dc | 1538 | /* Look up object handles */ |
27173f1f | 1539 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1540 | if (ret) |
1541 | goto err; | |
54cf91dc | 1542 | |
6fe4f140 | 1543 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1544 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1545 | |
54cf91dc | 1546 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1547 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
b1b38278 | 1548 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); |
54cf91dc CW |
1549 | if (ret) |
1550 | goto err; | |
1551 | ||
1552 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1553 | if (need_relocs) |
17601cbc | 1554 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1555 | if (ret) { |
1556 | if (ret == -EFAULT) { | |
ed5982e6 | 1557 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
b1b38278 | 1558 | eb, exec, ctx); |
54cf91dc CW |
1559 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1560 | } | |
1561 | if (ret) | |
1562 | goto err; | |
1563 | } | |
1564 | ||
1565 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1566 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1567 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1568 | ret = -EINVAL; |
1569 | goto err; | |
1570 | } | |
54cf91dc | 1571 | |
5f19e2bf | 1572 | params->args_batch_start_offset = args->batch_start_offset; |
743e78c1 | 1573 | if (i915_needs_cmd_parser(ring) && args->batch_len) { |
c7c7372e RP |
1574 | struct drm_i915_gem_object *parsed_batch_obj; |
1575 | ||
1576 | parsed_batch_obj = i915_gem_execbuffer_parse(ring, | |
71745376 BV |
1577 | &shadow_exec_entry, |
1578 | eb, | |
1579 | batch_obj, | |
1580 | args->batch_start_offset, | |
1581 | args->batch_len, | |
17cabf57 | 1582 | file->is_master); |
c7c7372e RP |
1583 | if (IS_ERR(parsed_batch_obj)) { |
1584 | ret = PTR_ERR(parsed_batch_obj); | |
78a42377 BV |
1585 | goto err; |
1586 | } | |
17cabf57 CW |
1587 | |
1588 | /* | |
c7c7372e RP |
1589 | * parsed_batch_obj == batch_obj means batch not fully parsed: |
1590 | * Accept, but don't promote to secure. | |
17cabf57 | 1591 | */ |
17cabf57 | 1592 | |
c7c7372e RP |
1593 | if (parsed_batch_obj != batch_obj) { |
1594 | /* | |
1595 | * Batch parsed and accepted: | |
1596 | * | |
1597 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1598 | * bit from MI_BATCH_BUFFER_START commands issued in | |
1599 | * the dispatch_execbuffer implementations. We | |
1600 | * specifically don't want that set on batches the | |
1601 | * command parser has accepted. | |
1602 | */ | |
1603 | dispatch_flags |= I915_DISPATCH_SECURE; | |
5f19e2bf | 1604 | params->args_batch_start_offset = 0; |
c7c7372e RP |
1605 | batch_obj = parsed_batch_obj; |
1606 | } | |
351e3db2 BV |
1607 | } |
1608 | ||
78a42377 BV |
1609 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1610 | ||
d7d4eedd CW |
1611 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1612 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1613 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1614 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1615 | /* |
1616 | * So on first glance it looks freaky that we pin the batch here | |
1617 | * outside of the reservation loop. But: | |
1618 | * - The batch is already pinned into the relevant ppgtt, so we | |
1619 | * already have the backing storage fully allocated. | |
1620 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1621 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1622 | * fitting due to fragmentation. |
1623 | * So this is actually safe. | |
1624 | */ | |
1625 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1626 | if (ret) | |
1627 | goto err; | |
d7d4eedd | 1628 | |
5f19e2bf | 1629 | params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1630 | } else |
5f19e2bf | 1631 | params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1632 | |
0c8dac88 | 1633 | /* Allocate a request for this batch buffer nice and early. */ |
6a6ae79a | 1634 | ret = i915_gem_request_alloc(ring, ctx, ¶ms->request); |
0c8dac88 JH |
1635 | if (ret) |
1636 | goto err_batch_unpin; | |
1637 | ||
fcfa423c JH |
1638 | ret = i915_gem_request_add_to_client(params->request, file); |
1639 | if (ret) | |
1640 | goto err_batch_unpin; | |
1641 | ||
5f19e2bf JH |
1642 | /* |
1643 | * Save assorted stuff away to pass through to *_submission(). | |
1644 | * NB: This data should be 'persistent' and not local as it will | |
1645 | * kept around beyond the duration of the IOCTL once the GPU | |
1646 | * scheduler arrives. | |
1647 | */ | |
1648 | params->dev = dev; | |
1649 | params->file = file; | |
1650 | params->ring = ring; | |
1651 | params->dispatch_flags = dispatch_flags; | |
1652 | params->batch_obj = batch_obj; | |
1653 | params->ctx = ctx; | |
1654 | ||
1655 | ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); | |
54cf91dc | 1656 | |
0c8dac88 | 1657 | err_batch_unpin: |
da51a1e7 DV |
1658 | /* |
1659 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1660 | * batch vma for correctness. For less ugly and less fragility this | |
1661 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1662 | * active. | |
1663 | */ | |
8e004efc | 1664 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1665 | i915_gem_object_ggtt_unpin(batch_obj); |
0c8dac88 | 1666 | |
54cf91dc | 1667 | err: |
41bde553 BW |
1668 | /* the request owns the ref now */ |
1669 | i915_gem_context_unreference(ctx); | |
67731b87 | 1670 | eb_destroy(eb); |
54cf91dc | 1671 | |
6a6ae79a JH |
1672 | /* |
1673 | * If the request was created but not successfully submitted then it | |
1674 | * must be freed again. If it was submitted then it is being tracked | |
1675 | * on the active request list and no clean up is required here. | |
1676 | */ | |
bccca494 | 1677 | if (ret && params->request) |
6a6ae79a | 1678 | i915_gem_request_cancel(params->request); |
6a6ae79a | 1679 | |
54cf91dc CW |
1680 | mutex_unlock(&dev->struct_mutex); |
1681 | ||
1682 | pre_mutex_err: | |
f65c9168 PZ |
1683 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1684 | * is really idle. */ | |
1685 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1686 | return ret; |
1687 | } | |
1688 | ||
1689 | /* | |
1690 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1691 | * list array and passes it to the real function. | |
1692 | */ | |
1693 | int | |
1694 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1695 | struct drm_file *file) | |
1696 | { | |
1697 | struct drm_i915_gem_execbuffer *args = data; | |
1698 | struct drm_i915_gem_execbuffer2 exec2; | |
1699 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1700 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1701 | int ret, i; | |
1702 | ||
54cf91dc | 1703 | if (args->buffer_count < 1) { |
ff240199 | 1704 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1705 | return -EINVAL; |
1706 | } | |
1707 | ||
1708 | /* Copy in the exec list from userland */ | |
1709 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1710 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1711 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1712 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1713 | args->buffer_count); |
1714 | drm_free_large(exec_list); | |
1715 | drm_free_large(exec2_list); | |
1716 | return -ENOMEM; | |
1717 | } | |
1718 | ret = copy_from_user(exec_list, | |
2bb4629a | 1719 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1720 | sizeof(*exec_list) * args->buffer_count); |
1721 | if (ret != 0) { | |
ff240199 | 1722 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1723 | args->buffer_count, ret); |
1724 | drm_free_large(exec_list); | |
1725 | drm_free_large(exec2_list); | |
1726 | return -EFAULT; | |
1727 | } | |
1728 | ||
1729 | for (i = 0; i < args->buffer_count; i++) { | |
1730 | exec2_list[i].handle = exec_list[i].handle; | |
1731 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1732 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1733 | exec2_list[i].alignment = exec_list[i].alignment; | |
1734 | exec2_list[i].offset = exec_list[i].offset; | |
1735 | if (INTEL_INFO(dev)->gen < 4) | |
1736 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1737 | else | |
1738 | exec2_list[i].flags = 0; | |
1739 | } | |
1740 | ||
1741 | exec2.buffers_ptr = args->buffers_ptr; | |
1742 | exec2.buffer_count = args->buffer_count; | |
1743 | exec2.batch_start_offset = args->batch_start_offset; | |
1744 | exec2.batch_len = args->batch_len; | |
1745 | exec2.DR1 = args->DR1; | |
1746 | exec2.DR4 = args->DR4; | |
1747 | exec2.num_cliprects = args->num_cliprects; | |
1748 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1749 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1750 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1751 | |
41bde553 | 1752 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1753 | if (!ret) { |
9aab8bff CW |
1754 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1755 | to_user_ptr(args->buffers_ptr); | |
1756 | ||
54cf91dc | 1757 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1758 | for (i = 0; i < args->buffer_count; i++) { |
1759 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1760 | &exec2_list[i].offset, | |
1761 | sizeof(user_exec_list[i].offset)); | |
1762 | if (ret) { | |
1763 | ret = -EFAULT; | |
1764 | DRM_DEBUG("failed to copy %d exec entries " | |
1765 | "back to user (%d)\n", | |
1766 | args->buffer_count, ret); | |
1767 | break; | |
1768 | } | |
54cf91dc CW |
1769 | } |
1770 | } | |
1771 | ||
1772 | drm_free_large(exec_list); | |
1773 | drm_free_large(exec2_list); | |
1774 | return ret; | |
1775 | } | |
1776 | ||
1777 | int | |
1778 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1779 | struct drm_file *file) | |
1780 | { | |
1781 | struct drm_i915_gem_execbuffer2 *args = data; | |
1782 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1783 | int ret; | |
1784 | ||
ed8cd3b2 XW |
1785 | if (args->buffer_count < 1 || |
1786 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1787 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1788 | return -EINVAL; |
1789 | } | |
1790 | ||
9cb34664 DV |
1791 | if (args->rsvd2 != 0) { |
1792 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1793 | return -EINVAL; | |
1794 | } | |
1795 | ||
8408c282 | 1796 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1797 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1798 | if (exec2_list == NULL) |
1799 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1800 | args->buffer_count); | |
54cf91dc | 1801 | if (exec2_list == NULL) { |
ff240199 | 1802 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1803 | args->buffer_count); |
1804 | return -ENOMEM; | |
1805 | } | |
1806 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1807 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1808 | sizeof(*exec2_list) * args->buffer_count); |
1809 | if (ret != 0) { | |
ff240199 | 1810 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1811 | args->buffer_count, ret); |
1812 | drm_free_large(exec2_list); | |
1813 | return -EFAULT; | |
1814 | } | |
1815 | ||
41bde553 | 1816 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1817 | if (!ret) { |
1818 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1819 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1820 | to_user_ptr(args->buffers_ptr); |
1821 | int i; | |
1822 | ||
1823 | for (i = 0; i < args->buffer_count; i++) { | |
1824 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1825 | &exec2_list[i].offset, | |
1826 | sizeof(user_exec_list[i].offset)); | |
1827 | if (ret) { | |
1828 | ret = -EFAULT; | |
1829 | DRM_DEBUG("failed to copy %d exec entries " | |
1830 | "back to user\n", | |
1831 | args->buffer_count); | |
1832 | break; | |
1833 | } | |
54cf91dc CW |
1834 | } |
1835 | } | |
1836 | ||
1837 | drm_free_large(exec2_list); | |
1838 | return ret; | |
1839 | } |