Commit | Line | Data |
---|---|---|
54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 38 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c | 39 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
0079a7df | 40 | #define __EXEC_OBJECT_PURGEABLE (1<<27) |
d23db88c CW |
41 | |
42 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 43 | |
27173f1f BW |
44 | struct eb_vmas { |
45 | struct list_head vmas; | |
67731b87 | 46 | int and; |
eef90ccb | 47 | union { |
27173f1f | 48 | struct i915_vma *lut[0]; |
eef90ccb CW |
49 | struct hlist_head buckets[0]; |
50 | }; | |
67731b87 CW |
51 | }; |
52 | ||
27173f1f | 53 | static struct eb_vmas * |
17601cbc | 54 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 55 | { |
27173f1f | 56 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
57 | |
58 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 59 | unsigned size = args->buffer_count; |
27173f1f BW |
60 | size *= sizeof(struct i915_vma *); |
61 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
62 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
63 | } | |
64 | ||
65 | if (eb == NULL) { | |
b205ca57 DV |
66 | unsigned size = args->buffer_count; |
67 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 68 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
69 | while (count > 2*size) |
70 | count >>= 1; | |
71 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 72 | sizeof(struct eb_vmas), |
eef90ccb CW |
73 | GFP_TEMPORARY); |
74 | if (eb == NULL) | |
75 | return eb; | |
76 | ||
77 | eb->and = count - 1; | |
78 | } else | |
79 | eb->and = -args->buffer_count; | |
80 | ||
27173f1f | 81 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
82 | return eb; |
83 | } | |
84 | ||
85 | static void | |
27173f1f | 86 | eb_reset(struct eb_vmas *eb) |
67731b87 | 87 | { |
eef90ccb CW |
88 | if (eb->and >= 0) |
89 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
90 | } |
91 | ||
3b96eff4 | 92 | static int |
27173f1f BW |
93 | eb_lookup_vmas(struct eb_vmas *eb, |
94 | struct drm_i915_gem_exec_object2 *exec, | |
95 | const struct drm_i915_gem_execbuffer2 *args, | |
96 | struct i915_address_space *vm, | |
97 | struct drm_file *file) | |
3b96eff4 | 98 | { |
27173f1f BW |
99 | struct drm_i915_gem_object *obj; |
100 | struct list_head objects; | |
9ae9ab52 | 101 | int i, ret; |
3b96eff4 | 102 | |
27173f1f | 103 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 104 | spin_lock(&file->table_lock); |
27173f1f BW |
105 | /* Grab a reference to the object and release the lock so we can lookup |
106 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 107 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
108 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
109 | if (obj == NULL) { | |
110 | spin_unlock(&file->table_lock); | |
111 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
112 | exec[i].handle, i); | |
27173f1f | 113 | ret = -ENOENT; |
9ae9ab52 | 114 | goto err; |
3b96eff4 CW |
115 | } |
116 | ||
27173f1f | 117 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
118 | spin_unlock(&file->table_lock); |
119 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
120 | obj, exec[i].handle, i); | |
27173f1f | 121 | ret = -EINVAL; |
9ae9ab52 | 122 | goto err; |
3b96eff4 CW |
123 | } |
124 | ||
125 | drm_gem_object_reference(&obj->base); | |
27173f1f BW |
126 | list_add_tail(&obj->obj_exec_link, &objects); |
127 | } | |
128 | spin_unlock(&file->table_lock); | |
3b96eff4 | 129 | |
27173f1f | 130 | i = 0; |
9ae9ab52 | 131 | while (!list_empty(&objects)) { |
27173f1f | 132 | struct i915_vma *vma; |
6f65e29a | 133 | |
9ae9ab52 CW |
134 | obj = list_first_entry(&objects, |
135 | struct drm_i915_gem_object, | |
136 | obj_exec_link); | |
137 | ||
e656a6cb DV |
138 | /* |
139 | * NOTE: We can leak any vmas created here when something fails | |
140 | * later on. But that's no issue since vma_unbind can deal with | |
141 | * vmas which are not actually bound. And since only | |
142 | * lookup_or_create exists as an interface to get at the vma | |
143 | * from the (obj, vm) we don't run the risk of creating | |
144 | * duplicated vmas for the same vm. | |
145 | */ | |
da51a1e7 | 146 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 147 | if (IS_ERR(vma)) { |
27173f1f BW |
148 | DRM_DEBUG("Failed to lookup VMA\n"); |
149 | ret = PTR_ERR(vma); | |
9ae9ab52 | 150 | goto err; |
27173f1f BW |
151 | } |
152 | ||
9ae9ab52 | 153 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 154 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 155 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
156 | |
157 | vma->exec_entry = &exec[i]; | |
eef90ccb | 158 | if (eb->and < 0) { |
27173f1f | 159 | eb->lut[i] = vma; |
eef90ccb CW |
160 | } else { |
161 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
162 | vma->exec_handle = handle; |
163 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
164 | &eb->buckets[handle & eb->and]); |
165 | } | |
27173f1f | 166 | ++i; |
3b96eff4 | 167 | } |
3b96eff4 | 168 | |
9ae9ab52 | 169 | return 0; |
27173f1f | 170 | |
27173f1f | 171 | |
9ae9ab52 | 172 | err: |
27173f1f BW |
173 | while (!list_empty(&objects)) { |
174 | obj = list_first_entry(&objects, | |
175 | struct drm_i915_gem_object, | |
176 | obj_exec_link); | |
177 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 178 | drm_gem_object_unreference(&obj->base); |
27173f1f | 179 | } |
9ae9ab52 CW |
180 | /* |
181 | * Objects already transfered to the vmas list will be unreferenced by | |
182 | * eb_destroy. | |
183 | */ | |
184 | ||
27173f1f | 185 | return ret; |
3b96eff4 CW |
186 | } |
187 | ||
27173f1f | 188 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 189 | { |
eef90ccb CW |
190 | if (eb->and < 0) { |
191 | if (handle >= -eb->and) | |
192 | return NULL; | |
193 | return eb->lut[handle]; | |
194 | } else { | |
195 | struct hlist_head *head; | |
196 | struct hlist_node *node; | |
67731b87 | 197 | |
eef90ccb CW |
198 | head = &eb->buckets[handle & eb->and]; |
199 | hlist_for_each(node, head) { | |
27173f1f | 200 | struct i915_vma *vma; |
67731b87 | 201 | |
27173f1f BW |
202 | vma = hlist_entry(node, struct i915_vma, exec_node); |
203 | if (vma->exec_handle == handle) | |
204 | return vma; | |
eef90ccb CW |
205 | } |
206 | return NULL; | |
207 | } | |
67731b87 CW |
208 | } |
209 | ||
a415d355 CW |
210 | static void |
211 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
212 | { | |
213 | struct drm_i915_gem_exec_object2 *entry; | |
214 | struct drm_i915_gem_object *obj = vma->obj; | |
215 | ||
216 | if (!drm_mm_node_allocated(&vma->node)) | |
217 | return; | |
218 | ||
219 | entry = vma->exec_entry; | |
220 | ||
221 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
222 | i915_gem_object_unpin_fence(obj); | |
223 | ||
224 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 225 | vma->pin_count--; |
a415d355 | 226 | |
0079a7df BV |
227 | if (entry->flags & __EXEC_OBJECT_PURGEABLE) |
228 | obj->madv = I915_MADV_DONTNEED; | |
229 | ||
230 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | | |
231 | __EXEC_OBJECT_HAS_PIN | | |
232 | __EXEC_OBJECT_PURGEABLE); | |
a415d355 CW |
233 | } |
234 | ||
235 | static void eb_destroy(struct eb_vmas *eb) | |
236 | { | |
27173f1f BW |
237 | while (!list_empty(&eb->vmas)) { |
238 | struct i915_vma *vma; | |
bcffc3fa | 239 | |
27173f1f BW |
240 | vma = list_first_entry(&eb->vmas, |
241 | struct i915_vma, | |
bcffc3fa | 242 | exec_list); |
27173f1f | 243 | list_del_init(&vma->exec_list); |
a415d355 | 244 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 245 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 246 | } |
67731b87 CW |
247 | kfree(eb); |
248 | } | |
249 | ||
dabdfe02 CW |
250 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
251 | { | |
2cc86b82 CW |
252 | return (HAS_LLC(obj->base.dev) || |
253 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 254 | !obj->map_and_fenceable || |
dabdfe02 CW |
255 | obj->cache_level != I915_CACHE_NONE); |
256 | } | |
257 | ||
5032d871 RB |
258 | static int |
259 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
260 | struct drm_i915_gem_relocation_entry *reloc, |
261 | uint64_t target_offset) | |
5032d871 | 262 | { |
3c94ceee | 263 | struct drm_device *dev = obj->base.dev; |
5032d871 | 264 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 265 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 266 | char *vaddr; |
8b78f0e5 | 267 | int ret; |
5032d871 | 268 | |
2cc86b82 | 269 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
270 | if (ret) |
271 | return ret; | |
272 | ||
273 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
274 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 275 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
276 | |
277 | if (INTEL_INFO(dev)->gen >= 8) { | |
278 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
279 | ||
280 | if (page_offset == 0) { | |
281 | kunmap_atomic(vaddr); | |
282 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
283 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
284 | } | |
285 | ||
d9ceb957 | 286 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
287 | } |
288 | ||
5032d871 RB |
289 | kunmap_atomic(vaddr); |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | static int | |
295 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
296 | struct drm_i915_gem_relocation_entry *reloc, |
297 | uint64_t target_offset) | |
5032d871 RB |
298 | { |
299 | struct drm_device *dev = obj->base.dev; | |
300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 301 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 302 | uint64_t offset; |
5032d871 | 303 | void __iomem *reloc_page; |
8b78f0e5 | 304 | int ret; |
5032d871 RB |
305 | |
306 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | ret = i915_gem_object_put_fence(obj); | |
311 | if (ret) | |
312 | return ret; | |
313 | ||
314 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
315 | offset = i915_gem_obj_ggtt_offset(obj); |
316 | offset += reloc->offset; | |
5032d871 | 317 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
318 | offset & PAGE_MASK); |
319 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
320 | |
321 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 322 | offset += sizeof(uint32_t); |
3c94ceee | 323 | |
906843c3 | 324 | if (offset_in_page(offset) == 0) { |
3c94ceee | 325 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
326 | reloc_page = |
327 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
328 | offset); | |
3c94ceee BW |
329 | } |
330 | ||
906843c3 CW |
331 | iowrite32(upper_32_bits(delta), |
332 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
333 | } |
334 | ||
5032d871 RB |
335 | io_mapping_unmap_atomic(reloc_page); |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
54cf91dc CW |
340 | static int |
341 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 342 | struct eb_vmas *eb, |
3e7a0322 | 343 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
344 | { |
345 | struct drm_device *dev = obj->base.dev; | |
346 | struct drm_gem_object *target_obj; | |
149c8407 | 347 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 348 | struct i915_vma *target_vma; |
d9ceb957 | 349 | uint64_t target_offset; |
8b78f0e5 | 350 | int ret; |
54cf91dc | 351 | |
67731b87 | 352 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
353 | target_vma = eb_get_vma(eb, reloc->target_handle); |
354 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 355 | return -ENOENT; |
27173f1f BW |
356 | target_i915_obj = target_vma->obj; |
357 | target_obj = &target_vma->obj->base; | |
54cf91dc | 358 | |
5ce09725 | 359 | target_offset = target_vma->node.start; |
54cf91dc | 360 | |
e844b990 EA |
361 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
362 | * pipe_control writes because the gpu doesn't properly redirect them | |
363 | * through the ppgtt for non_secure batchbuffers. */ | |
364 | if (unlikely(IS_GEN6(dev) && | |
365 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
fe14d5f4 TU |
366 | !(target_vma->bound & GLOBAL_BIND))) { |
367 | ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, | |
368 | GLOBAL_BIND); | |
369 | if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) | |
370 | return ret; | |
371 | } | |
e844b990 | 372 | |
54cf91dc | 373 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 374 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 375 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
376 | "obj %p target %d offset %d " |
377 | "read %08x write %08x", | |
378 | obj, reloc->target_handle, | |
379 | (int) reloc->offset, | |
380 | reloc->read_domains, | |
381 | reloc->write_domain); | |
8b78f0e5 | 382 | return -EINVAL; |
54cf91dc | 383 | } |
4ca4a250 DV |
384 | if (unlikely((reloc->write_domain | reloc->read_domains) |
385 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 386 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
387 | "obj %p target %d offset %d " |
388 | "read %08x write %08x", | |
389 | obj, reloc->target_handle, | |
390 | (int) reloc->offset, | |
391 | reloc->read_domains, | |
392 | reloc->write_domain); | |
8b78f0e5 | 393 | return -EINVAL; |
54cf91dc | 394 | } |
54cf91dc CW |
395 | |
396 | target_obj->pending_read_domains |= reloc->read_domains; | |
397 | target_obj->pending_write_domain |= reloc->write_domain; | |
398 | ||
399 | /* If the relocation already has the right value in it, no | |
400 | * more work needs to be done. | |
401 | */ | |
402 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 403 | return 0; |
54cf91dc CW |
404 | |
405 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
406 | if (unlikely(reloc->offset > |
407 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 408 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
409 | "obj %p target %d offset %d size %d.\n", |
410 | obj, reloc->target_handle, | |
411 | (int) reloc->offset, | |
412 | (int) obj->base.size); | |
8b78f0e5 | 413 | return -EINVAL; |
54cf91dc | 414 | } |
b8f7ab17 | 415 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 416 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
417 | "obj %p target %d offset %d.\n", |
418 | obj, reloc->target_handle, | |
419 | (int) reloc->offset); | |
8b78f0e5 | 420 | return -EINVAL; |
54cf91dc CW |
421 | } |
422 | ||
dabdfe02 CW |
423 | /* We can't wait for rendering with pagefaults disabled */ |
424 | if (obj->active && in_atomic()) | |
425 | return -EFAULT; | |
426 | ||
5032d871 | 427 | if (use_cpu_reloc(obj)) |
d9ceb957 | 428 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
5032d871 | 429 | else |
d9ceb957 | 430 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
54cf91dc | 431 | |
d4d36014 DV |
432 | if (ret) |
433 | return ret; | |
434 | ||
54cf91dc CW |
435 | /* and update the user's relocation entry */ |
436 | reloc->presumed_offset = target_offset; | |
437 | ||
67731b87 | 438 | return 0; |
54cf91dc CW |
439 | } |
440 | ||
441 | static int | |
27173f1f BW |
442 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
443 | struct eb_vmas *eb) | |
54cf91dc | 444 | { |
1d83f442 CW |
445 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
446 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 447 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 448 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 449 | int remain, ret; |
54cf91dc | 450 | |
2bb4629a | 451 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 452 | |
1d83f442 CW |
453 | remain = entry->relocation_count; |
454 | while (remain) { | |
455 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
456 | int count = remain; | |
457 | if (count > ARRAY_SIZE(stack_reloc)) | |
458 | count = ARRAY_SIZE(stack_reloc); | |
459 | remain -= count; | |
460 | ||
461 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
462 | return -EFAULT; |
463 | ||
1d83f442 CW |
464 | do { |
465 | u64 offset = r->presumed_offset; | |
54cf91dc | 466 | |
3e7a0322 | 467 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
468 | if (ret) |
469 | return ret; | |
470 | ||
471 | if (r->presumed_offset != offset && | |
472 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
473 | &r->presumed_offset, | |
474 | sizeof(r->presumed_offset))) { | |
475 | return -EFAULT; | |
476 | } | |
477 | ||
478 | user_relocs++; | |
479 | r++; | |
480 | } while (--count); | |
54cf91dc CW |
481 | } |
482 | ||
483 | return 0; | |
1d83f442 | 484 | #undef N_RELOC |
54cf91dc CW |
485 | } |
486 | ||
487 | static int | |
27173f1f BW |
488 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
489 | struct eb_vmas *eb, | |
490 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 491 | { |
27173f1f | 492 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
493 | int i, ret; |
494 | ||
495 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 496 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
497 | if (ret) |
498 | return ret; | |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static int | |
17601cbc | 505 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 506 | { |
27173f1f | 507 | struct i915_vma *vma; |
d4aeee77 CW |
508 | int ret = 0; |
509 | ||
510 | /* This is the fast path and we cannot handle a pagefault whilst | |
511 | * holding the struct mutex lest the user pass in the relocations | |
512 | * contained within a mmaped bo. For in such a case we, the page | |
513 | * fault handler would call i915_gem_fault() and we would try to | |
514 | * acquire the struct mutex again. Obviously this is bad and so | |
515 | * lockdep complains vehemently. | |
516 | */ | |
517 | pagefault_disable(); | |
27173f1f BW |
518 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
519 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 520 | if (ret) |
d4aeee77 | 521 | break; |
54cf91dc | 522 | } |
d4aeee77 | 523 | pagefault_enable(); |
54cf91dc | 524 | |
d4aeee77 | 525 | return ret; |
54cf91dc CW |
526 | } |
527 | ||
1690e1eb | 528 | static int |
27173f1f | 529 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 530 | struct intel_engine_cs *ring, |
27173f1f | 531 | bool *need_reloc) |
1690e1eb | 532 | { |
6f65e29a | 533 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 534 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 535 | uint64_t flags; |
1690e1eb CW |
536 | int ret; |
537 | ||
1ec9e26d | 538 | flags = 0; |
e6a84468 | 539 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
c826c449 | 540 | flags |= PIN_GLOBAL | PIN_MAPPABLE; |
1ec9e26d | 541 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
bf3d149b | 542 | flags |= PIN_GLOBAL; |
d23db88c CW |
543 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
544 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
1ec9e26d DV |
545 | |
546 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
1690e1eb CW |
547 | if (ret) |
548 | return ret; | |
549 | ||
7788a765 CW |
550 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
551 | ||
82b6b6d7 CW |
552 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
553 | ret = i915_gem_object_get_fence(obj); | |
554 | if (ret) | |
555 | return ret; | |
9a5a53b3 | 556 | |
82b6b6d7 CW |
557 | if (i915_gem_object_pin_fence(obj)) |
558 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
559 | } |
560 | ||
27173f1f BW |
561 | if (entry->offset != vma->node.start) { |
562 | entry->offset = vma->node.start; | |
ed5982e6 DV |
563 | *need_reloc = true; |
564 | } | |
565 | ||
566 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
567 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
568 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
569 | } | |
570 | ||
1690e1eb | 571 | return 0; |
7788a765 | 572 | } |
1690e1eb | 573 | |
d23db88c | 574 | static bool |
e6a84468 | 575 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
576 | { |
577 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 578 | |
e6a84468 CW |
579 | if (entry->relocation_count == 0) |
580 | return false; | |
581 | ||
582 | if (!i915_is_ggtt(vma->vm)) | |
583 | return false; | |
584 | ||
585 | /* See also use_cpu_reloc() */ | |
586 | if (HAS_LLC(vma->obj->base.dev)) | |
587 | return false; | |
588 | ||
589 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
590 | return false; | |
591 | ||
592 | return true; | |
593 | } | |
594 | ||
595 | static bool | |
596 | eb_vma_misplaced(struct i915_vma *vma) | |
597 | { | |
598 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
599 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 600 | |
e6a84468 | 601 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
602 | !i915_is_ggtt(vma->vm)); |
603 | ||
604 | if (entry->alignment && | |
605 | vma->node.start & (entry->alignment - 1)) | |
606 | return true; | |
607 | ||
e6a84468 | 608 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) |
d23db88c CW |
609 | return true; |
610 | ||
611 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && | |
612 | vma->node.start < BATCH_OFFSET_BIAS) | |
613 | return true; | |
614 | ||
615 | return false; | |
616 | } | |
617 | ||
54cf91dc | 618 | static int |
a4872ba6 | 619 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 620 | struct list_head *vmas, |
ed5982e6 | 621 | bool *need_relocs) |
54cf91dc | 622 | { |
432e58ed | 623 | struct drm_i915_gem_object *obj; |
27173f1f | 624 | struct i915_vma *vma; |
68c8c17f | 625 | struct i915_address_space *vm; |
27173f1f | 626 | struct list_head ordered_vmas; |
7788a765 CW |
627 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
628 | int retry; | |
6fe4f140 | 629 | |
227f782e CW |
630 | i915_gem_retire_requests_ring(ring); |
631 | ||
68c8c17f BW |
632 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
633 | ||
27173f1f BW |
634 | INIT_LIST_HEAD(&ordered_vmas); |
635 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
636 | struct drm_i915_gem_exec_object2 *entry; |
637 | bool need_fence, need_mappable; | |
638 | ||
27173f1f BW |
639 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
640 | obj = vma->obj; | |
641 | entry = vma->exec_entry; | |
6fe4f140 | 642 | |
82b6b6d7 CW |
643 | if (!has_fenced_gpu_access) |
644 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 645 | need_fence = |
6fe4f140 CW |
646 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
647 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 648 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 649 | |
e6a84468 CW |
650 | if (need_mappable) { |
651 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; | |
27173f1f | 652 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 653 | } else |
27173f1f | 654 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 655 | |
ed5982e6 | 656 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 657 | obj->base.pending_write_domain = 0; |
6fe4f140 | 658 | } |
27173f1f | 659 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
660 | |
661 | /* Attempt to pin all of the buffers into the GTT. | |
662 | * This is done in 3 phases: | |
663 | * | |
664 | * 1a. Unbind all objects that do not match the GTT constraints for | |
665 | * the execbuffer (fenceable, mappable, alignment etc). | |
666 | * 1b. Increment pin count for already bound objects. | |
667 | * 2. Bind new objects. | |
668 | * 3. Decrement pin count. | |
669 | * | |
7788a765 | 670 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
671 | * room for the earlier objects *unless* we need to defragment. |
672 | */ | |
673 | retry = 0; | |
674 | do { | |
7788a765 | 675 | int ret = 0; |
54cf91dc CW |
676 | |
677 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 678 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 679 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
680 | continue; |
681 | ||
e6a84468 | 682 | if (eb_vma_misplaced(vma)) |
27173f1f | 683 | ret = i915_vma_unbind(vma); |
54cf91dc | 684 | else |
27173f1f | 685 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 686 | if (ret) |
54cf91dc | 687 | goto err; |
54cf91dc CW |
688 | } |
689 | ||
690 | /* Bind fresh objects */ | |
27173f1f BW |
691 | list_for_each_entry(vma, vmas, exec_list) { |
692 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 693 | continue; |
54cf91dc | 694 | |
27173f1f | 695 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
696 | if (ret) |
697 | goto err; | |
54cf91dc CW |
698 | } |
699 | ||
a415d355 | 700 | err: |
6c085a72 | 701 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
702 | return ret; |
703 | ||
a415d355 CW |
704 | /* Decrement pin count for bound objects */ |
705 | list_for_each_entry(vma, vmas, exec_list) | |
706 | i915_gem_execbuffer_unreserve_vma(vma); | |
707 | ||
68c8c17f | 708 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
709 | if (ret) |
710 | return ret; | |
54cf91dc CW |
711 | } while (1); |
712 | } | |
713 | ||
714 | static int | |
715 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 716 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 717 | struct drm_file *file, |
a4872ba6 | 718 | struct intel_engine_cs *ring, |
27173f1f BW |
719 | struct eb_vmas *eb, |
720 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
721 | { |
722 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
723 | struct i915_address_space *vm; |
724 | struct i915_vma *vma; | |
ed5982e6 | 725 | bool need_relocs; |
dd6864a4 | 726 | int *reloc_offset; |
54cf91dc | 727 | int i, total, ret; |
b205ca57 | 728 | unsigned count = args->buffer_count; |
54cf91dc | 729 | |
27173f1f BW |
730 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
731 | ||
67731b87 | 732 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
733 | while (!list_empty(&eb->vmas)) { |
734 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
735 | list_del_init(&vma->exec_list); | |
a415d355 | 736 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 737 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
738 | } |
739 | ||
54cf91dc CW |
740 | mutex_unlock(&dev->struct_mutex); |
741 | ||
742 | total = 0; | |
743 | for (i = 0; i < count; i++) | |
432e58ed | 744 | total += exec[i].relocation_count; |
54cf91dc | 745 | |
dd6864a4 | 746 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 747 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
748 | if (reloc == NULL || reloc_offset == NULL) { |
749 | drm_free_large(reloc); | |
750 | drm_free_large(reloc_offset); | |
54cf91dc CW |
751 | mutex_lock(&dev->struct_mutex); |
752 | return -ENOMEM; | |
753 | } | |
754 | ||
755 | total = 0; | |
756 | for (i = 0; i < count; i++) { | |
757 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
758 | u64 invalid_offset = (u64)-1; |
759 | int j; | |
54cf91dc | 760 | |
2bb4629a | 761 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
762 | |
763 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 764 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
765 | ret = -EFAULT; |
766 | mutex_lock(&dev->struct_mutex); | |
767 | goto err; | |
768 | } | |
769 | ||
262b6d36 CW |
770 | /* As we do not update the known relocation offsets after |
771 | * relocating (due to the complexities in lock handling), | |
772 | * we need to mark them as invalid now so that we force the | |
773 | * relocation processing next time. Just in case the target | |
774 | * object is evicted and then rebound into its old | |
775 | * presumed_offset before the next execbuffer - if that | |
776 | * happened we would make the mistake of assuming that the | |
777 | * relocations were valid. | |
778 | */ | |
779 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
780 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
781 | &invalid_offset, | |
782 | sizeof(invalid_offset))) { | |
262b6d36 CW |
783 | ret = -EFAULT; |
784 | mutex_lock(&dev->struct_mutex); | |
785 | goto err; | |
786 | } | |
787 | } | |
788 | ||
dd6864a4 | 789 | reloc_offset[i] = total; |
432e58ed | 790 | total += exec[i].relocation_count; |
54cf91dc CW |
791 | } |
792 | ||
793 | ret = i915_mutex_lock_interruptible(dev); | |
794 | if (ret) { | |
795 | mutex_lock(&dev->struct_mutex); | |
796 | goto err; | |
797 | } | |
798 | ||
67731b87 | 799 | /* reacquire the objects */ |
67731b87 | 800 | eb_reset(eb); |
27173f1f | 801 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
802 | if (ret) |
803 | goto err; | |
67731b87 | 804 | |
ed5982e6 | 805 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 806 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
807 | if (ret) |
808 | goto err; | |
809 | ||
27173f1f BW |
810 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
811 | int offset = vma->exec_entry - exec; | |
812 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
813 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
814 | if (ret) |
815 | goto err; | |
54cf91dc CW |
816 | } |
817 | ||
818 | /* Leave the user relocations as are, this is the painfully slow path, | |
819 | * and we want to avoid the complication of dropping the lock whilst | |
820 | * having buffers reserved in the aperture and so causing spurious | |
821 | * ENOSPC for random operations. | |
822 | */ | |
823 | ||
824 | err: | |
825 | drm_free_large(reloc); | |
dd6864a4 | 826 | drm_free_large(reloc_offset); |
54cf91dc CW |
827 | return ret; |
828 | } | |
829 | ||
54cf91dc | 830 | static int |
a4872ba6 | 831 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 832 | struct list_head *vmas) |
54cf91dc | 833 | { |
27173f1f | 834 | struct i915_vma *vma; |
6ac42f41 | 835 | uint32_t flush_domains = 0; |
000433b6 | 836 | bool flush_chipset = false; |
432e58ed | 837 | int ret; |
54cf91dc | 838 | |
27173f1f BW |
839 | list_for_each_entry(vma, vmas, exec_list) { |
840 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 841 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
842 | if (ret) |
843 | return ret; | |
6ac42f41 DV |
844 | |
845 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 846 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 847 | |
6ac42f41 | 848 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
849 | } |
850 | ||
000433b6 | 851 | if (flush_chipset) |
e76e9aeb | 852 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
853 | |
854 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
855 | wmb(); | |
856 | ||
09cf7c9a CW |
857 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
858 | * any residual writes from the previous batch. | |
859 | */ | |
a7b9761d | 860 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
861 | } |
862 | ||
432e58ed CW |
863 | static bool |
864 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 865 | { |
ed5982e6 DV |
866 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
867 | return false; | |
868 | ||
432e58ed | 869 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
870 | } |
871 | ||
872 | static int | |
ad19f10b CW |
873 | validate_exec_list(struct drm_device *dev, |
874 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
875 | int count) |
876 | { | |
b205ca57 DV |
877 | unsigned relocs_total = 0; |
878 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
879 | unsigned invalid_flags; |
880 | int i; | |
881 | ||
882 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
883 | if (USES_FULL_PPGTT(dev)) | |
884 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
885 | |
886 | for (i = 0; i < count; i++) { | |
2bb4629a | 887 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
888 | int length; /* limited by fault_in_pages_readable() */ |
889 | ||
ad19f10b | 890 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
891 | return -EINVAL; |
892 | ||
3118a4f6 KC |
893 | /* First check for malicious input causing overflow in |
894 | * the worst case where we need to allocate the entire | |
895 | * relocation tree as a single array. | |
896 | */ | |
897 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 898 | return -EINVAL; |
3118a4f6 | 899 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
900 | |
901 | length = exec[i].relocation_count * | |
902 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
903 | /* |
904 | * We must check that the entire relocation array is safe | |
905 | * to read, but since we may need to update the presumed | |
906 | * offsets during execution, check for full write access. | |
907 | */ | |
54cf91dc CW |
908 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
909 | return -EFAULT; | |
910 | ||
d330a953 | 911 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
912 | if (fault_in_multipages_readable(ptr, length)) |
913 | return -EFAULT; | |
914 | } | |
54cf91dc CW |
915 | } |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
273497e5 | 920 | static struct intel_context * |
d299cce7 | 921 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 922 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 923 | { |
273497e5 | 924 | struct intel_context *ctx = NULL; |
d299cce7 MK |
925 | struct i915_ctx_hang_stats *hs; |
926 | ||
821d66dd | 927 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
928 | return ERR_PTR(-EINVAL); |
929 | ||
41bde553 | 930 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 931 | if (IS_ERR(ctx)) |
41bde553 | 932 | return ctx; |
d299cce7 | 933 | |
41bde553 | 934 | hs = &ctx->hang_stats; |
d299cce7 MK |
935 | if (hs->banned) { |
936 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 937 | return ERR_PTR(-EIO); |
d299cce7 MK |
938 | } |
939 | ||
ec3e9963 OM |
940 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
941 | int ret = intel_lr_context_deferred_create(ctx, ring); | |
942 | if (ret) { | |
943 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
944 | return ERR_PTR(ret); | |
945 | } | |
946 | } | |
947 | ||
41bde553 | 948 | return ctx; |
d299cce7 MK |
949 | } |
950 | ||
ba8b7ccb | 951 | void |
27173f1f | 952 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 953 | struct intel_engine_cs *ring) |
432e58ed | 954 | { |
97b2a6a1 | 955 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
27173f1f | 956 | struct i915_vma *vma; |
432e58ed | 957 | |
27173f1f | 958 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 959 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 960 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
961 | u32 old_read = obj->base.read_domains; |
962 | u32 old_write = obj->base.write_domain; | |
db53a302 | 963 | |
432e58ed | 964 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
965 | if (obj->base.write_domain == 0) |
966 | obj->base.pending_read_domains |= obj->base.read_domains; | |
967 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 968 | |
e2d05a8b | 969 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
970 | if (obj->base.write_domain) { |
971 | obj->dirty = 1; | |
97b2a6a1 | 972 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 DV |
973 | |
974 | intel_fb_obj_invalidate(obj, ring); | |
c8725f3d CW |
975 | |
976 | /* update for the implicit flush after a batch */ | |
977 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 978 | } |
82b6b6d7 | 979 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 980 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
981 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
982 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
983 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
984 | &dev_priv->mm.fence_list); | |
985 | } | |
986 | } | |
432e58ed | 987 | |
db53a302 | 988 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
989 | } |
990 | } | |
991 | ||
ba8b7ccb | 992 | void |
54cf91dc | 993 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
432e58ed | 994 | struct drm_file *file, |
a4872ba6 | 995 | struct intel_engine_cs *ring, |
7d736f4f | 996 | struct drm_i915_gem_object *obj) |
54cf91dc | 997 | { |
cc889e0f DV |
998 | /* Unconditionally force add_request to emit a full flush. */ |
999 | ring->gpu_caches_dirty = true; | |
54cf91dc | 1000 | |
432e58ed | 1001 | /* Add a breadcrumb for the completion of the batch buffer */ |
9400ae5c | 1002 | (void)__i915_add_request(ring, file, obj); |
432e58ed | 1003 | } |
54cf91dc | 1004 | |
ae662d31 EA |
1005 | static int |
1006 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 1007 | struct intel_engine_cs *ring) |
ae662d31 | 1008 | { |
50227e1c | 1009 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1010 | int ret, i; |
1011 | ||
9d662da8 DV |
1012 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1013 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1014 | return -EINVAL; | |
1015 | } | |
ae662d31 EA |
1016 | |
1017 | ret = intel_ring_begin(ring, 4 * 3); | |
1018 | if (ret) | |
1019 | return ret; | |
1020 | ||
1021 | for (i = 0; i < 4; i++) { | |
1022 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1023 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1024 | intel_ring_emit(ring, 0); | |
1025 | } | |
1026 | ||
1027 | intel_ring_advance(ring); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
5c6c6003 CW |
1032 | static int |
1033 | i915_emit_box(struct intel_engine_cs *ring, | |
1034 | struct drm_clip_rect *box, | |
1035 | int DR1, int DR4) | |
1036 | { | |
1037 | int ret; | |
1038 | ||
1039 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || | |
1040 | box->y2 <= 0 || box->x2 <= 0) { | |
1041 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
1042 | box->x1, box->y1, box->x2, box->y2); | |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | if (INTEL_INFO(ring->dev)->gen >= 4) { | |
1047 | ret = intel_ring_begin(ring, 4); | |
1048 | if (ret) | |
1049 | return ret; | |
1050 | ||
1051 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); | |
1052 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1053 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1054 | intel_ring_emit(ring, DR4); | |
1055 | } else { | |
1056 | ret = intel_ring_begin(ring, 6); | |
1057 | if (ret) | |
1058 | return ret; | |
1059 | ||
1060 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); | |
1061 | intel_ring_emit(ring, DR1); | |
1062 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1063 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1064 | intel_ring_emit(ring, DR4); | |
1065 | intel_ring_emit(ring, 0); | |
1066 | } | |
1067 | intel_ring_advance(ring); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
71745376 BV |
1072 | static struct drm_i915_gem_object* |
1073 | i915_gem_execbuffer_parse(struct intel_engine_cs *ring, | |
1074 | struct drm_i915_gem_exec_object2 *shadow_exec_entry, | |
1075 | struct eb_vmas *eb, | |
1076 | struct drm_i915_gem_object *batch_obj, | |
1077 | u32 batch_start_offset, | |
1078 | u32 batch_len, | |
17cabf57 | 1079 | bool is_master) |
71745376 BV |
1080 | { |
1081 | struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev); | |
1082 | struct drm_i915_gem_object *shadow_batch_obj; | |
17cabf57 | 1083 | struct i915_vma *vma; |
71745376 BV |
1084 | int ret; |
1085 | ||
1086 | shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv->mm.batch_pool, | |
17cabf57 | 1087 | PAGE_ALIGN(batch_len)); |
71745376 BV |
1088 | if (IS_ERR(shadow_batch_obj)) |
1089 | return shadow_batch_obj; | |
1090 | ||
1091 | ret = i915_parse_cmds(ring, | |
1092 | batch_obj, | |
1093 | shadow_batch_obj, | |
1094 | batch_start_offset, | |
1095 | batch_len, | |
1096 | is_master); | |
17cabf57 CW |
1097 | if (ret) |
1098 | goto err; | |
71745376 | 1099 | |
17cabf57 CW |
1100 | ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); |
1101 | if (ret) | |
1102 | goto err; | |
71745376 | 1103 | |
17cabf57 | 1104 | memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); |
71745376 | 1105 | |
17cabf57 CW |
1106 | vma = i915_gem_obj_to_ggtt(shadow_batch_obj); |
1107 | vma->exec_entry = shadow_exec_entry; | |
1108 | vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE | __EXEC_OBJECT_HAS_PIN; | |
1109 | drm_gem_object_reference(&shadow_batch_obj->base); | |
1110 | list_add_tail(&vma->exec_list, &eb->vmas); | |
71745376 | 1111 | |
17cabf57 CW |
1112 | shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; |
1113 | ||
1114 | return shadow_batch_obj; | |
71745376 | 1115 | |
17cabf57 CW |
1116 | err: |
1117 | if (ret == -EACCES) /* unhandled chained batch */ | |
1118 | return batch_obj; | |
1119 | else | |
1120 | return ERR_PTR(ret); | |
71745376 | 1121 | } |
5c6c6003 | 1122 | |
a83014d3 OM |
1123 | int |
1124 | i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, | |
1125 | struct intel_engine_cs *ring, | |
1126 | struct intel_context *ctx, | |
1127 | struct drm_i915_gem_execbuffer2 *args, | |
1128 | struct list_head *vmas, | |
1129 | struct drm_i915_gem_object *batch_obj, | |
8e004efc | 1130 | u64 exec_start, u32 dispatch_flags) |
78382593 OM |
1131 | { |
1132 | struct drm_clip_rect *cliprects = NULL; | |
1133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1134 | u64 exec_len; | |
1135 | int instp_mode; | |
1136 | u32 instp_mask; | |
1137 | int i, ret = 0; | |
1138 | ||
1139 | if (args->num_cliprects != 0) { | |
1140 | if (ring != &dev_priv->ring[RCS]) { | |
1141 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); | |
1142 | return -EINVAL; | |
1143 | } | |
1144 | ||
1145 | if (INTEL_INFO(dev)->gen >= 5) { | |
1146 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1147 | return -EINVAL; | |
1148 | } | |
1149 | ||
1150 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { | |
1151 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1152 | args->num_cliprects); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
1156 | cliprects = kcalloc(args->num_cliprects, | |
1157 | sizeof(*cliprects), | |
1158 | GFP_KERNEL); | |
1159 | if (cliprects == NULL) { | |
1160 | ret = -ENOMEM; | |
1161 | goto error; | |
1162 | } | |
1163 | ||
1164 | if (copy_from_user(cliprects, | |
1165 | to_user_ptr(args->cliprects_ptr), | |
1166 | sizeof(*cliprects)*args->num_cliprects)) { | |
1167 | ret = -EFAULT; | |
1168 | goto error; | |
1169 | } | |
1170 | } else { | |
1171 | if (args->DR4 == 0xffffffff) { | |
1172 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1173 | args->DR4 = 0; | |
1174 | } | |
1175 | ||
1176 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
1177 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | ret = i915_gem_execbuffer_move_to_gpu(ring, vmas); | |
1183 | if (ret) | |
1184 | goto error; | |
1185 | ||
1186 | ret = i915_switch_context(ring, ctx); | |
1187 | if (ret) | |
1188 | goto error; | |
1189 | ||
1190 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1191 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1192 | switch (instp_mode) { | |
1193 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1194 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1195 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1196 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1197 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1198 | ret = -EINVAL; | |
1199 | goto error; | |
1200 | } | |
1201 | ||
1202 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1203 | if (INTEL_INFO(dev)->gen < 4) { | |
1204 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
1205 | ret = -EINVAL; | |
1206 | goto error; | |
1207 | } | |
1208 | ||
1209 | if (INTEL_INFO(dev)->gen > 5 && | |
1210 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1211 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
1212 | ret = -EINVAL; | |
1213 | goto error; | |
1214 | } | |
1215 | ||
1216 | /* The HW changed the meaning on this bit on gen6 */ | |
1217 | if (INTEL_INFO(dev)->gen >= 6) | |
1218 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1219 | } | |
1220 | break; | |
1221 | default: | |
1222 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
1223 | ret = -EINVAL; | |
1224 | goto error; | |
1225 | } | |
1226 | ||
1227 | if (ring == &dev_priv->ring[RCS] && | |
1228 | instp_mode != dev_priv->relative_constants_mode) { | |
1229 | ret = intel_ring_begin(ring, 4); | |
1230 | if (ret) | |
1231 | goto error; | |
1232 | ||
1233 | intel_ring_emit(ring, MI_NOOP); | |
1234 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1235 | intel_ring_emit(ring, INSTPM); | |
1236 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1237 | intel_ring_advance(ring); | |
1238 | ||
1239 | dev_priv->relative_constants_mode = instp_mode; | |
1240 | } | |
1241 | ||
1242 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
1243 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1244 | if (ret) | |
1245 | goto error; | |
1246 | } | |
1247 | ||
1248 | exec_len = args->batch_len; | |
1249 | if (cliprects) { | |
1250 | for (i = 0; i < args->num_cliprects; i++) { | |
5c6c6003 | 1251 | ret = i915_emit_box(ring, &cliprects[i], |
78382593 OM |
1252 | args->DR1, args->DR4); |
1253 | if (ret) | |
1254 | goto error; | |
1255 | ||
1256 | ret = ring->dispatch_execbuffer(ring, | |
1257 | exec_start, exec_len, | |
8e004efc | 1258 | dispatch_flags); |
78382593 OM |
1259 | if (ret) |
1260 | goto error; | |
1261 | } | |
1262 | } else { | |
1263 | ret = ring->dispatch_execbuffer(ring, | |
1264 | exec_start, exec_len, | |
8e004efc | 1265 | dispatch_flags); |
78382593 OM |
1266 | if (ret) |
1267 | return ret; | |
1268 | } | |
1269 | ||
8e004efc | 1270 | trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags); |
78382593 OM |
1271 | |
1272 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
1273 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
1274 | ||
1275 | error: | |
1276 | kfree(cliprects); | |
1277 | return ret; | |
1278 | } | |
1279 | ||
a8ebba75 ZY |
1280 | /** |
1281 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1282 | * The Ring ID is returned. | |
1283 | */ | |
1284 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1285 | struct drm_file *file) | |
1286 | { | |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1288 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1289 | ||
1290 | /* Check whether the file_priv is using one ring */ | |
1291 | if (file_priv->bsd_ring) | |
1292 | return file_priv->bsd_ring->id; | |
1293 | else { | |
1294 | /* If no, use the ping-pong mechanism to select one ring */ | |
1295 | int ring_id; | |
1296 | ||
1297 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1298 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1299 | ring_id = VCS; |
bdf1e7e3 | 1300 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1301 | } else { |
1302 | ring_id = VCS2; | |
bdf1e7e3 | 1303 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1304 | } |
1305 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1306 | mutex_unlock(&dev->struct_mutex); | |
1307 | return ring_id; | |
1308 | } | |
1309 | } | |
1310 | ||
d23db88c CW |
1311 | static struct drm_i915_gem_object * |
1312 | eb_get_batch(struct eb_vmas *eb) | |
1313 | { | |
1314 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1315 | ||
1316 | /* | |
1317 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1318 | * to negative relocation deltas. Usually that works out ok since the | |
1319 | * relocate address is still positive, except when the batch is placed | |
1320 | * very low in the GTT. Ensure this doesn't happen. | |
1321 | * | |
1322 | * Note that actual hangs have only been observed on gen7, but for | |
1323 | * paranoia do it everywhere. | |
1324 | */ | |
1325 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1326 | ||
1327 | return vma->obj; | |
1328 | } | |
1329 | ||
54cf91dc CW |
1330 | static int |
1331 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1332 | struct drm_file *file, | |
1333 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1334 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1335 | { |
50227e1c | 1336 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1337 | struct eb_vmas *eb; |
54cf91dc | 1338 | struct drm_i915_gem_object *batch_obj; |
78a42377 | 1339 | struct drm_i915_gem_exec_object2 shadow_exec_entry; |
a4872ba6 | 1340 | struct intel_engine_cs *ring; |
273497e5 | 1341 | struct intel_context *ctx; |
41bde553 | 1342 | struct i915_address_space *vm; |
d299cce7 | 1343 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
78382593 | 1344 | u64 exec_start = args->batch_start_offset; |
8e004efc | 1345 | u32 dispatch_flags; |
78382593 | 1346 | int ret; |
ed5982e6 | 1347 | bool need_relocs; |
54cf91dc | 1348 | |
ed5982e6 | 1349 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1350 | return -EINVAL; |
432e58ed | 1351 | |
ad19f10b | 1352 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1353 | if (ret) |
1354 | return ret; | |
1355 | ||
8e004efc | 1356 | dispatch_flags = 0; |
d7d4eedd CW |
1357 | if (args->flags & I915_EXEC_SECURE) { |
1358 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1359 | return -EPERM; | |
1360 | ||
8e004efc | 1361 | dispatch_flags |= I915_DISPATCH_SECURE; |
d7d4eedd | 1362 | } |
b45305fc | 1363 | if (args->flags & I915_EXEC_IS_PINNED) |
8e004efc | 1364 | dispatch_flags |= I915_DISPATCH_PINNED; |
d7d4eedd | 1365 | |
b1a93306 | 1366 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1367 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1368 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1369 | return -EINVAL; | |
1370 | } | |
ca01b12b | 1371 | |
8d360dff ZG |
1372 | if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) && |
1373 | ((args->flags & I915_EXEC_BSD_MASK) != 0)) { | |
1374 | DRM_DEBUG("execbuf with non bsd ring but with invalid " | |
1375 | "bsd dispatch flags: %d\n", (int)(args->flags)); | |
1376 | return -EINVAL; | |
1377 | } | |
1378 | ||
ca01b12b BW |
1379 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) |
1380 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1381 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1382 | if (HAS_BSD2(dev)) { | |
1383 | int ring_id; | |
8d360dff ZG |
1384 | |
1385 | switch (args->flags & I915_EXEC_BSD_MASK) { | |
1386 | case I915_EXEC_BSD_DEFAULT: | |
1387 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1388 | ring = &dev_priv->ring[ring_id]; | |
1389 | break; | |
1390 | case I915_EXEC_BSD_RING1: | |
1391 | ring = &dev_priv->ring[VCS]; | |
1392 | break; | |
1393 | case I915_EXEC_BSD_RING2: | |
1394 | ring = &dev_priv->ring[VCS2]; | |
1395 | break; | |
1396 | default: | |
1397 | DRM_DEBUG("execbuf with unknown bsd ring: %d\n", | |
1398 | (int)(args->flags & I915_EXEC_BSD_MASK)); | |
1399 | return -EINVAL; | |
1400 | } | |
a8ebba75 ZY |
1401 | } else |
1402 | ring = &dev_priv->ring[VCS]; | |
1403 | } else | |
ca01b12b BW |
1404 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1405 | ||
a15817cf CW |
1406 | if (!intel_ring_initialized(ring)) { |
1407 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1408 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1409 | return -EINVAL; | |
1410 | } | |
54cf91dc CW |
1411 | |
1412 | if (args->buffer_count < 1) { | |
ff240199 | 1413 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1414 | return -EINVAL; |
1415 | } | |
54cf91dc | 1416 | |
f65c9168 PZ |
1417 | intel_runtime_pm_get(dev_priv); |
1418 | ||
54cf91dc CW |
1419 | ret = i915_mutex_lock_interruptible(dev); |
1420 | if (ret) | |
1421 | goto pre_mutex_err; | |
1422 | ||
7c9c4b8f | 1423 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1424 | if (IS_ERR(ctx)) { |
d299cce7 | 1425 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1426 | ret = PTR_ERR(ctx); |
d299cce7 | 1427 | goto pre_mutex_err; |
935f38d6 | 1428 | } |
41bde553 BW |
1429 | |
1430 | i915_gem_context_reference(ctx); | |
1431 | ||
ae6c4806 DV |
1432 | if (ctx->ppgtt) |
1433 | vm = &ctx->ppgtt->base; | |
1434 | else | |
7e0d96bc | 1435 | vm = &dev_priv->gtt.base; |
d299cce7 | 1436 | |
17601cbc | 1437 | eb = eb_create(args); |
67731b87 | 1438 | if (eb == NULL) { |
935f38d6 | 1439 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1440 | mutex_unlock(&dev->struct_mutex); |
1441 | ret = -ENOMEM; | |
1442 | goto pre_mutex_err; | |
1443 | } | |
1444 | ||
54cf91dc | 1445 | /* Look up object handles */ |
27173f1f | 1446 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1447 | if (ret) |
1448 | goto err; | |
54cf91dc | 1449 | |
6fe4f140 | 1450 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1451 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1452 | |
54cf91dc | 1453 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1454 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1455 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1456 | if (ret) |
1457 | goto err; | |
1458 | ||
1459 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1460 | if (need_relocs) |
17601cbc | 1461 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1462 | if (ret) { |
1463 | if (ret == -EFAULT) { | |
ed5982e6 | 1464 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1465 | eb, exec); |
54cf91dc CW |
1466 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1467 | } | |
1468 | if (ret) | |
1469 | goto err; | |
1470 | } | |
1471 | ||
1472 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1473 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1474 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1475 | ret = -EINVAL; |
1476 | goto err; | |
1477 | } | |
54cf91dc | 1478 | |
351e3db2 | 1479 | if (i915_needs_cmd_parser(ring)) { |
71745376 BV |
1480 | batch_obj = i915_gem_execbuffer_parse(ring, |
1481 | &shadow_exec_entry, | |
1482 | eb, | |
1483 | batch_obj, | |
1484 | args->batch_start_offset, | |
1485 | args->batch_len, | |
17cabf57 | 1486 | file->is_master); |
71745376 BV |
1487 | if (IS_ERR(batch_obj)) { |
1488 | ret = PTR_ERR(batch_obj); | |
78a42377 BV |
1489 | goto err; |
1490 | } | |
17cabf57 CW |
1491 | |
1492 | /* | |
1493 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE | |
1494 | * bit from MI_BATCH_BUFFER_START commands issued in the | |
1495 | * dispatch_execbuffer implementations. We specifically | |
1496 | * don't want that set when the command parser is | |
1497 | * enabled. | |
1498 | * | |
1499 | * FIXME: with aliasing ppgtt, buffers that should only | |
1500 | * be in ggtt still end up in the aliasing ppgtt. remove | |
1501 | * this check when that is fixed. | |
1502 | */ | |
1503 | if (USES_FULL_PPGTT(dev)) | |
8e004efc | 1504 | dispatch_flags |= I915_DISPATCH_SECURE; |
17cabf57 CW |
1505 | |
1506 | exec_start = 0; | |
351e3db2 BV |
1507 | } |
1508 | ||
78a42377 BV |
1509 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
1510 | ||
d7d4eedd CW |
1511 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1512 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1513 | * hsw should have this fixed, but bdw mucks it up again. */ |
8e004efc | 1514 | if (dispatch_flags & I915_DISPATCH_SECURE) { |
da51a1e7 DV |
1515 | /* |
1516 | * So on first glance it looks freaky that we pin the batch here | |
1517 | * outside of the reservation loop. But: | |
1518 | * - The batch is already pinned into the relevant ppgtt, so we | |
1519 | * already have the backing storage fully allocated. | |
1520 | * - No other BO uses the global gtt (well contexts, but meh), | |
fd0753cf | 1521 | * so we don't really have issues with multiple objects not |
da51a1e7 DV |
1522 | * fitting due to fragmentation. |
1523 | * So this is actually safe. | |
1524 | */ | |
1525 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1526 | if (ret) | |
1527 | goto err; | |
d7d4eedd | 1528 | |
7e0d96bc | 1529 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1530 | } else |
7e0d96bc | 1531 | exec_start += i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1532 | |
a83014d3 | 1533 | ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args, |
8e004efc JH |
1534 | &eb->vmas, batch_obj, exec_start, |
1535 | dispatch_flags); | |
54cf91dc | 1536 | |
da51a1e7 DV |
1537 | /* |
1538 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1539 | * batch vma for correctness. For less ugly and less fragility this | |
1540 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1541 | * active. | |
1542 | */ | |
8e004efc | 1543 | if (dispatch_flags & I915_DISPATCH_SECURE) |
da51a1e7 | 1544 | i915_gem_object_ggtt_unpin(batch_obj); |
54cf91dc | 1545 | err: |
41bde553 BW |
1546 | /* the request owns the ref now */ |
1547 | i915_gem_context_unreference(ctx); | |
67731b87 | 1548 | eb_destroy(eb); |
54cf91dc CW |
1549 | |
1550 | mutex_unlock(&dev->struct_mutex); | |
1551 | ||
1552 | pre_mutex_err: | |
f65c9168 PZ |
1553 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1554 | * is really idle. */ | |
1555 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1556 | return ret; |
1557 | } | |
1558 | ||
1559 | /* | |
1560 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1561 | * list array and passes it to the real function. | |
1562 | */ | |
1563 | int | |
1564 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1565 | struct drm_file *file) | |
1566 | { | |
1567 | struct drm_i915_gem_execbuffer *args = data; | |
1568 | struct drm_i915_gem_execbuffer2 exec2; | |
1569 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1570 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1571 | int ret, i; | |
1572 | ||
54cf91dc | 1573 | if (args->buffer_count < 1) { |
ff240199 | 1574 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1575 | return -EINVAL; |
1576 | } | |
1577 | ||
1578 | /* Copy in the exec list from userland */ | |
1579 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1580 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1581 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1582 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1583 | args->buffer_count); |
1584 | drm_free_large(exec_list); | |
1585 | drm_free_large(exec2_list); | |
1586 | return -ENOMEM; | |
1587 | } | |
1588 | ret = copy_from_user(exec_list, | |
2bb4629a | 1589 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1590 | sizeof(*exec_list) * args->buffer_count); |
1591 | if (ret != 0) { | |
ff240199 | 1592 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1593 | args->buffer_count, ret); |
1594 | drm_free_large(exec_list); | |
1595 | drm_free_large(exec2_list); | |
1596 | return -EFAULT; | |
1597 | } | |
1598 | ||
1599 | for (i = 0; i < args->buffer_count; i++) { | |
1600 | exec2_list[i].handle = exec_list[i].handle; | |
1601 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1602 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1603 | exec2_list[i].alignment = exec_list[i].alignment; | |
1604 | exec2_list[i].offset = exec_list[i].offset; | |
1605 | if (INTEL_INFO(dev)->gen < 4) | |
1606 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1607 | else | |
1608 | exec2_list[i].flags = 0; | |
1609 | } | |
1610 | ||
1611 | exec2.buffers_ptr = args->buffers_ptr; | |
1612 | exec2.buffer_count = args->buffer_count; | |
1613 | exec2.batch_start_offset = args->batch_start_offset; | |
1614 | exec2.batch_len = args->batch_len; | |
1615 | exec2.DR1 = args->DR1; | |
1616 | exec2.DR4 = args->DR4; | |
1617 | exec2.num_cliprects = args->num_cliprects; | |
1618 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1619 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1620 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1621 | |
41bde553 | 1622 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1623 | if (!ret) { |
9aab8bff CW |
1624 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1625 | to_user_ptr(args->buffers_ptr); | |
1626 | ||
54cf91dc | 1627 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1628 | for (i = 0; i < args->buffer_count; i++) { |
1629 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1630 | &exec2_list[i].offset, | |
1631 | sizeof(user_exec_list[i].offset)); | |
1632 | if (ret) { | |
1633 | ret = -EFAULT; | |
1634 | DRM_DEBUG("failed to copy %d exec entries " | |
1635 | "back to user (%d)\n", | |
1636 | args->buffer_count, ret); | |
1637 | break; | |
1638 | } | |
54cf91dc CW |
1639 | } |
1640 | } | |
1641 | ||
1642 | drm_free_large(exec_list); | |
1643 | drm_free_large(exec2_list); | |
1644 | return ret; | |
1645 | } | |
1646 | ||
1647 | int | |
1648 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1649 | struct drm_file *file) | |
1650 | { | |
1651 | struct drm_i915_gem_execbuffer2 *args = data; | |
1652 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1653 | int ret; | |
1654 | ||
ed8cd3b2 XW |
1655 | if (args->buffer_count < 1 || |
1656 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1657 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1658 | return -EINVAL; |
1659 | } | |
1660 | ||
9cb34664 DV |
1661 | if (args->rsvd2 != 0) { |
1662 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | ||
8408c282 | 1666 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1667 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1668 | if (exec2_list == NULL) |
1669 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1670 | args->buffer_count); | |
54cf91dc | 1671 | if (exec2_list == NULL) { |
ff240199 | 1672 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1673 | args->buffer_count); |
1674 | return -ENOMEM; | |
1675 | } | |
1676 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1677 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1678 | sizeof(*exec2_list) * args->buffer_count); |
1679 | if (ret != 0) { | |
ff240199 | 1680 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1681 | args->buffer_count, ret); |
1682 | drm_free_large(exec2_list); | |
1683 | return -EFAULT; | |
1684 | } | |
1685 | ||
41bde553 | 1686 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1687 | if (!ret) { |
1688 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1689 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1690 | to_user_ptr(args->buffers_ptr); |
1691 | int i; | |
1692 | ||
1693 | for (i = 0; i < args->buffer_count; i++) { | |
1694 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1695 | &exec2_list[i].offset, | |
1696 | sizeof(user_exec_list[i].offset)); | |
1697 | if (ret) { | |
1698 | ret = -EFAULT; | |
1699 | DRM_DEBUG("failed to copy %d exec entries " | |
1700 | "back to user\n", | |
1701 | args->buffer_count); | |
1702 | break; | |
1703 | } | |
54cf91dc CW |
1704 | } |
1705 | } | |
1706 | ||
1707 | drm_free_large(exec2_list); | |
1708 | return ret; | |
1709 | } |