Commit | Line | Data |
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54cf91dc CW |
1 | /* |
2 | * Copyright © 2008,2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Chris Wilson <chris@chris-wilson.co.uk> | |
26 | * | |
27 | */ | |
28 | ||
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
54cf91dc CW |
31 | #include "i915_drv.h" |
32 | #include "i915_trace.h" | |
33 | #include "intel_drv.h" | |
f45b5557 | 34 | #include <linux/dma_remapping.h> |
54cf91dc | 35 | |
a415d355 CW |
36 | #define __EXEC_OBJECT_HAS_PIN (1<<31) |
37 | #define __EXEC_OBJECT_HAS_FENCE (1<<30) | |
e6a84468 | 38 | #define __EXEC_OBJECT_NEEDS_MAP (1<<29) |
d23db88c CW |
39 | #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) |
40 | ||
41 | #define BATCH_OFFSET_BIAS (256*1024) | |
a415d355 | 42 | |
27173f1f BW |
43 | struct eb_vmas { |
44 | struct list_head vmas; | |
67731b87 | 45 | int and; |
eef90ccb | 46 | union { |
27173f1f | 47 | struct i915_vma *lut[0]; |
eef90ccb CW |
48 | struct hlist_head buckets[0]; |
49 | }; | |
67731b87 CW |
50 | }; |
51 | ||
27173f1f | 52 | static struct eb_vmas * |
17601cbc | 53 | eb_create(struct drm_i915_gem_execbuffer2 *args) |
67731b87 | 54 | { |
27173f1f | 55 | struct eb_vmas *eb = NULL; |
eef90ccb CW |
56 | |
57 | if (args->flags & I915_EXEC_HANDLE_LUT) { | |
b205ca57 | 58 | unsigned size = args->buffer_count; |
27173f1f BW |
59 | size *= sizeof(struct i915_vma *); |
60 | size += sizeof(struct eb_vmas); | |
eef90ccb CW |
61 | eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
62 | } | |
63 | ||
64 | if (eb == NULL) { | |
b205ca57 DV |
65 | unsigned size = args->buffer_count; |
66 | unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; | |
27b7c63a | 67 | BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); |
eef90ccb CW |
68 | while (count > 2*size) |
69 | count >>= 1; | |
70 | eb = kzalloc(count*sizeof(struct hlist_head) + | |
27173f1f | 71 | sizeof(struct eb_vmas), |
eef90ccb CW |
72 | GFP_TEMPORARY); |
73 | if (eb == NULL) | |
74 | return eb; | |
75 | ||
76 | eb->and = count - 1; | |
77 | } else | |
78 | eb->and = -args->buffer_count; | |
79 | ||
27173f1f | 80 | INIT_LIST_HEAD(&eb->vmas); |
67731b87 CW |
81 | return eb; |
82 | } | |
83 | ||
84 | static void | |
27173f1f | 85 | eb_reset(struct eb_vmas *eb) |
67731b87 | 86 | { |
eef90ccb CW |
87 | if (eb->and >= 0) |
88 | memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); | |
67731b87 CW |
89 | } |
90 | ||
3b96eff4 | 91 | static int |
27173f1f BW |
92 | eb_lookup_vmas(struct eb_vmas *eb, |
93 | struct drm_i915_gem_exec_object2 *exec, | |
94 | const struct drm_i915_gem_execbuffer2 *args, | |
95 | struct i915_address_space *vm, | |
96 | struct drm_file *file) | |
3b96eff4 | 97 | { |
27173f1f BW |
98 | struct drm_i915_gem_object *obj; |
99 | struct list_head objects; | |
9ae9ab52 | 100 | int i, ret; |
3b96eff4 | 101 | |
27173f1f | 102 | INIT_LIST_HEAD(&objects); |
3b96eff4 | 103 | spin_lock(&file->table_lock); |
27173f1f BW |
104 | /* Grab a reference to the object and release the lock so we can lookup |
105 | * or create the VMA without using GFP_ATOMIC */ | |
eef90ccb | 106 | for (i = 0; i < args->buffer_count; i++) { |
3b96eff4 CW |
107 | obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); |
108 | if (obj == NULL) { | |
109 | spin_unlock(&file->table_lock); | |
110 | DRM_DEBUG("Invalid object handle %d at index %d\n", | |
111 | exec[i].handle, i); | |
27173f1f | 112 | ret = -ENOENT; |
9ae9ab52 | 113 | goto err; |
3b96eff4 CW |
114 | } |
115 | ||
27173f1f | 116 | if (!list_empty(&obj->obj_exec_link)) { |
3b96eff4 CW |
117 | spin_unlock(&file->table_lock); |
118 | DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", | |
119 | obj, exec[i].handle, i); | |
27173f1f | 120 | ret = -EINVAL; |
9ae9ab52 | 121 | goto err; |
3b96eff4 CW |
122 | } |
123 | ||
355a7018 TH |
124 | WARN_ONCE(obj->base.dumb, |
125 | "GPU use of dumb buffer is illegal.\n"); | |
126 | ||
3b96eff4 | 127 | drm_gem_object_reference(&obj->base); |
27173f1f BW |
128 | list_add_tail(&obj->obj_exec_link, &objects); |
129 | } | |
130 | spin_unlock(&file->table_lock); | |
3b96eff4 | 131 | |
27173f1f | 132 | i = 0; |
9ae9ab52 | 133 | while (!list_empty(&objects)) { |
27173f1f | 134 | struct i915_vma *vma; |
6f65e29a | 135 | |
9ae9ab52 CW |
136 | obj = list_first_entry(&objects, |
137 | struct drm_i915_gem_object, | |
138 | obj_exec_link); | |
139 | ||
e656a6cb DV |
140 | /* |
141 | * NOTE: We can leak any vmas created here when something fails | |
142 | * later on. But that's no issue since vma_unbind can deal with | |
143 | * vmas which are not actually bound. And since only | |
144 | * lookup_or_create exists as an interface to get at the vma | |
145 | * from the (obj, vm) we don't run the risk of creating | |
146 | * duplicated vmas for the same vm. | |
147 | */ | |
da51a1e7 | 148 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
27173f1f | 149 | if (IS_ERR(vma)) { |
27173f1f BW |
150 | DRM_DEBUG("Failed to lookup VMA\n"); |
151 | ret = PTR_ERR(vma); | |
9ae9ab52 | 152 | goto err; |
27173f1f BW |
153 | } |
154 | ||
9ae9ab52 | 155 | /* Transfer ownership from the objects list to the vmas list. */ |
27173f1f | 156 | list_add_tail(&vma->exec_list, &eb->vmas); |
9ae9ab52 | 157 | list_del_init(&obj->obj_exec_link); |
27173f1f BW |
158 | |
159 | vma->exec_entry = &exec[i]; | |
eef90ccb | 160 | if (eb->and < 0) { |
27173f1f | 161 | eb->lut[i] = vma; |
eef90ccb CW |
162 | } else { |
163 | uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; | |
27173f1f BW |
164 | vma->exec_handle = handle; |
165 | hlist_add_head(&vma->exec_node, | |
eef90ccb CW |
166 | &eb->buckets[handle & eb->and]); |
167 | } | |
27173f1f | 168 | ++i; |
3b96eff4 | 169 | } |
3b96eff4 | 170 | |
9ae9ab52 | 171 | return 0; |
27173f1f | 172 | |
27173f1f | 173 | |
9ae9ab52 | 174 | err: |
27173f1f BW |
175 | while (!list_empty(&objects)) { |
176 | obj = list_first_entry(&objects, | |
177 | struct drm_i915_gem_object, | |
178 | obj_exec_link); | |
179 | list_del_init(&obj->obj_exec_link); | |
9ae9ab52 | 180 | drm_gem_object_unreference(&obj->base); |
27173f1f | 181 | } |
9ae9ab52 CW |
182 | /* |
183 | * Objects already transfered to the vmas list will be unreferenced by | |
184 | * eb_destroy. | |
185 | */ | |
186 | ||
27173f1f | 187 | return ret; |
3b96eff4 CW |
188 | } |
189 | ||
27173f1f | 190 | static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) |
67731b87 | 191 | { |
eef90ccb CW |
192 | if (eb->and < 0) { |
193 | if (handle >= -eb->and) | |
194 | return NULL; | |
195 | return eb->lut[handle]; | |
196 | } else { | |
197 | struct hlist_head *head; | |
198 | struct hlist_node *node; | |
67731b87 | 199 | |
eef90ccb CW |
200 | head = &eb->buckets[handle & eb->and]; |
201 | hlist_for_each(node, head) { | |
27173f1f | 202 | struct i915_vma *vma; |
67731b87 | 203 | |
27173f1f BW |
204 | vma = hlist_entry(node, struct i915_vma, exec_node); |
205 | if (vma->exec_handle == handle) | |
206 | return vma; | |
eef90ccb CW |
207 | } |
208 | return NULL; | |
209 | } | |
67731b87 CW |
210 | } |
211 | ||
a415d355 CW |
212 | static void |
213 | i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) | |
214 | { | |
215 | struct drm_i915_gem_exec_object2 *entry; | |
216 | struct drm_i915_gem_object *obj = vma->obj; | |
217 | ||
218 | if (!drm_mm_node_allocated(&vma->node)) | |
219 | return; | |
220 | ||
221 | entry = vma->exec_entry; | |
222 | ||
223 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) | |
224 | i915_gem_object_unpin_fence(obj); | |
225 | ||
226 | if (entry->flags & __EXEC_OBJECT_HAS_PIN) | |
3d7f0f9d | 227 | vma->pin_count--; |
a415d355 CW |
228 | |
229 | entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); | |
230 | } | |
231 | ||
232 | static void eb_destroy(struct eb_vmas *eb) | |
233 | { | |
27173f1f BW |
234 | while (!list_empty(&eb->vmas)) { |
235 | struct i915_vma *vma; | |
bcffc3fa | 236 | |
27173f1f BW |
237 | vma = list_first_entry(&eb->vmas, |
238 | struct i915_vma, | |
bcffc3fa | 239 | exec_list); |
27173f1f | 240 | list_del_init(&vma->exec_list); |
a415d355 | 241 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 242 | drm_gem_object_unreference(&vma->obj->base); |
bcffc3fa | 243 | } |
67731b87 CW |
244 | kfree(eb); |
245 | } | |
246 | ||
dabdfe02 CW |
247 | static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) |
248 | { | |
2cc86b82 CW |
249 | return (HAS_LLC(obj->base.dev) || |
250 | obj->base.write_domain == I915_GEM_DOMAIN_CPU || | |
504c7267 | 251 | !obj->map_and_fenceable || |
dabdfe02 CW |
252 | obj->cache_level != I915_CACHE_NONE); |
253 | } | |
254 | ||
5032d871 RB |
255 | static int |
256 | relocate_entry_cpu(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
257 | struct drm_i915_gem_relocation_entry *reloc, |
258 | uint64_t target_offset) | |
5032d871 | 259 | { |
3c94ceee | 260 | struct drm_device *dev = obj->base.dev; |
5032d871 | 261 | uint32_t page_offset = offset_in_page(reloc->offset); |
d9ceb957 | 262 | uint64_t delta = reloc->delta + target_offset; |
5032d871 | 263 | char *vaddr; |
8b78f0e5 | 264 | int ret; |
5032d871 | 265 | |
2cc86b82 | 266 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
5032d871 RB |
267 | if (ret) |
268 | return ret; | |
269 | ||
270 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
271 | reloc->offset >> PAGE_SHIFT)); | |
d9ceb957 | 272 | *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); |
3c94ceee BW |
273 | |
274 | if (INTEL_INFO(dev)->gen >= 8) { | |
275 | page_offset = offset_in_page(page_offset + sizeof(uint32_t)); | |
276 | ||
277 | if (page_offset == 0) { | |
278 | kunmap_atomic(vaddr); | |
279 | vaddr = kmap_atomic(i915_gem_object_get_page(obj, | |
280 | (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); | |
281 | } | |
282 | ||
d9ceb957 | 283 | *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); |
3c94ceee BW |
284 | } |
285 | ||
5032d871 RB |
286 | kunmap_atomic(vaddr); |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static int | |
292 | relocate_entry_gtt(struct drm_i915_gem_object *obj, | |
d9ceb957 BW |
293 | struct drm_i915_gem_relocation_entry *reloc, |
294 | uint64_t target_offset) | |
5032d871 RB |
295 | { |
296 | struct drm_device *dev = obj->base.dev; | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d9ceb957 | 298 | uint64_t delta = reloc->delta + target_offset; |
906843c3 | 299 | uint64_t offset; |
5032d871 | 300 | void __iomem *reloc_page; |
8b78f0e5 | 301 | int ret; |
5032d871 RB |
302 | |
303 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
304 | if (ret) | |
305 | return ret; | |
306 | ||
307 | ret = i915_gem_object_put_fence(obj); | |
308 | if (ret) | |
309 | return ret; | |
310 | ||
311 | /* Map the page containing the relocation we're going to perform. */ | |
906843c3 CW |
312 | offset = i915_gem_obj_ggtt_offset(obj); |
313 | offset += reloc->offset; | |
5032d871 | 314 | reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
906843c3 CW |
315 | offset & PAGE_MASK); |
316 | iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
317 | |
318 | if (INTEL_INFO(dev)->gen >= 8) { | |
906843c3 | 319 | offset += sizeof(uint32_t); |
3c94ceee | 320 | |
906843c3 | 321 | if (offset_in_page(offset) == 0) { |
3c94ceee | 322 | io_mapping_unmap_atomic(reloc_page); |
906843c3 CW |
323 | reloc_page = |
324 | io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
325 | offset); | |
3c94ceee BW |
326 | } |
327 | ||
906843c3 CW |
328 | iowrite32(upper_32_bits(delta), |
329 | reloc_page + offset_in_page(offset)); | |
3c94ceee BW |
330 | } |
331 | ||
5032d871 RB |
332 | io_mapping_unmap_atomic(reloc_page); |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
54cf91dc CW |
337 | static int |
338 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, | |
27173f1f | 339 | struct eb_vmas *eb, |
3e7a0322 | 340 | struct drm_i915_gem_relocation_entry *reloc) |
54cf91dc CW |
341 | { |
342 | struct drm_device *dev = obj->base.dev; | |
343 | struct drm_gem_object *target_obj; | |
149c8407 | 344 | struct drm_i915_gem_object *target_i915_obj; |
27173f1f | 345 | struct i915_vma *target_vma; |
d9ceb957 | 346 | uint64_t target_offset; |
8b78f0e5 | 347 | int ret; |
54cf91dc | 348 | |
67731b87 | 349 | /* we've already hold a reference to all valid objects */ |
27173f1f BW |
350 | target_vma = eb_get_vma(eb, reloc->target_handle); |
351 | if (unlikely(target_vma == NULL)) | |
54cf91dc | 352 | return -ENOENT; |
27173f1f BW |
353 | target_i915_obj = target_vma->obj; |
354 | target_obj = &target_vma->obj->base; | |
54cf91dc | 355 | |
5ce09725 | 356 | target_offset = target_vma->node.start; |
54cf91dc | 357 | |
e844b990 EA |
358 | /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and |
359 | * pipe_control writes because the gpu doesn't properly redirect them | |
360 | * through the ppgtt for non_secure batchbuffers. */ | |
361 | if (unlikely(IS_GEN6(dev) && | |
362 | reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && | |
aff43766 TU |
363 | !(target_vma->bound & GLOBAL_BIND))) |
364 | target_vma->bind_vma(target_vma, target_i915_obj->cache_level, | |
365 | GLOBAL_BIND); | |
e844b990 | 366 | |
54cf91dc | 367 | /* Validate that the target is in a valid r/w GPU domain */ |
b8f7ab17 | 368 | if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { |
ff240199 | 369 | DRM_DEBUG("reloc with multiple write domains: " |
54cf91dc CW |
370 | "obj %p target %d offset %d " |
371 | "read %08x write %08x", | |
372 | obj, reloc->target_handle, | |
373 | (int) reloc->offset, | |
374 | reloc->read_domains, | |
375 | reloc->write_domain); | |
8b78f0e5 | 376 | return -EINVAL; |
54cf91dc | 377 | } |
4ca4a250 DV |
378 | if (unlikely((reloc->write_domain | reloc->read_domains) |
379 | & ~I915_GEM_GPU_DOMAINS)) { | |
ff240199 | 380 | DRM_DEBUG("reloc with read/write non-GPU domains: " |
54cf91dc CW |
381 | "obj %p target %d offset %d " |
382 | "read %08x write %08x", | |
383 | obj, reloc->target_handle, | |
384 | (int) reloc->offset, | |
385 | reloc->read_domains, | |
386 | reloc->write_domain); | |
8b78f0e5 | 387 | return -EINVAL; |
54cf91dc | 388 | } |
54cf91dc CW |
389 | |
390 | target_obj->pending_read_domains |= reloc->read_domains; | |
391 | target_obj->pending_write_domain |= reloc->write_domain; | |
392 | ||
393 | /* If the relocation already has the right value in it, no | |
394 | * more work needs to be done. | |
395 | */ | |
396 | if (target_offset == reloc->presumed_offset) | |
67731b87 | 397 | return 0; |
54cf91dc CW |
398 | |
399 | /* Check that the relocation address is valid... */ | |
3c94ceee BW |
400 | if (unlikely(reloc->offset > |
401 | obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { | |
ff240199 | 402 | DRM_DEBUG("Relocation beyond object bounds: " |
54cf91dc CW |
403 | "obj %p target %d offset %d size %d.\n", |
404 | obj, reloc->target_handle, | |
405 | (int) reloc->offset, | |
406 | (int) obj->base.size); | |
8b78f0e5 | 407 | return -EINVAL; |
54cf91dc | 408 | } |
b8f7ab17 | 409 | if (unlikely(reloc->offset & 3)) { |
ff240199 | 410 | DRM_DEBUG("Relocation not 4-byte aligned: " |
54cf91dc CW |
411 | "obj %p target %d offset %d.\n", |
412 | obj, reloc->target_handle, | |
413 | (int) reloc->offset); | |
8b78f0e5 | 414 | return -EINVAL; |
54cf91dc CW |
415 | } |
416 | ||
dabdfe02 CW |
417 | /* We can't wait for rendering with pagefaults disabled */ |
418 | if (obj->active && in_atomic()) | |
419 | return -EFAULT; | |
420 | ||
5032d871 | 421 | if (use_cpu_reloc(obj)) |
d9ceb957 | 422 | ret = relocate_entry_cpu(obj, reloc, target_offset); |
5032d871 | 423 | else |
d9ceb957 | 424 | ret = relocate_entry_gtt(obj, reloc, target_offset); |
54cf91dc | 425 | |
d4d36014 DV |
426 | if (ret) |
427 | return ret; | |
428 | ||
54cf91dc CW |
429 | /* and update the user's relocation entry */ |
430 | reloc->presumed_offset = target_offset; | |
431 | ||
67731b87 | 432 | return 0; |
54cf91dc CW |
433 | } |
434 | ||
435 | static int | |
27173f1f BW |
436 | i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, |
437 | struct eb_vmas *eb) | |
54cf91dc | 438 | { |
1d83f442 CW |
439 | #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) |
440 | struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; | |
54cf91dc | 441 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
27173f1f | 442 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
1d83f442 | 443 | int remain, ret; |
54cf91dc | 444 | |
2bb4629a | 445 | user_relocs = to_user_ptr(entry->relocs_ptr); |
54cf91dc | 446 | |
1d83f442 CW |
447 | remain = entry->relocation_count; |
448 | while (remain) { | |
449 | struct drm_i915_gem_relocation_entry *r = stack_reloc; | |
450 | int count = remain; | |
451 | if (count > ARRAY_SIZE(stack_reloc)) | |
452 | count = ARRAY_SIZE(stack_reloc); | |
453 | remain -= count; | |
454 | ||
455 | if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) | |
54cf91dc CW |
456 | return -EFAULT; |
457 | ||
1d83f442 CW |
458 | do { |
459 | u64 offset = r->presumed_offset; | |
54cf91dc | 460 | |
3e7a0322 | 461 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); |
1d83f442 CW |
462 | if (ret) |
463 | return ret; | |
464 | ||
465 | if (r->presumed_offset != offset && | |
466 | __copy_to_user_inatomic(&user_relocs->presumed_offset, | |
467 | &r->presumed_offset, | |
468 | sizeof(r->presumed_offset))) { | |
469 | return -EFAULT; | |
470 | } | |
471 | ||
472 | user_relocs++; | |
473 | r++; | |
474 | } while (--count); | |
54cf91dc CW |
475 | } |
476 | ||
477 | return 0; | |
1d83f442 | 478 | #undef N_RELOC |
54cf91dc CW |
479 | } |
480 | ||
481 | static int | |
27173f1f BW |
482 | i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, |
483 | struct eb_vmas *eb, | |
484 | struct drm_i915_gem_relocation_entry *relocs) | |
54cf91dc | 485 | { |
27173f1f | 486 | const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
54cf91dc CW |
487 | int i, ret; |
488 | ||
489 | for (i = 0; i < entry->relocation_count; i++) { | |
3e7a0322 | 490 | ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); |
54cf91dc CW |
491 | if (ret) |
492 | return ret; | |
493 | } | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | static int | |
17601cbc | 499 | i915_gem_execbuffer_relocate(struct eb_vmas *eb) |
54cf91dc | 500 | { |
27173f1f | 501 | struct i915_vma *vma; |
d4aeee77 CW |
502 | int ret = 0; |
503 | ||
504 | /* This is the fast path and we cannot handle a pagefault whilst | |
505 | * holding the struct mutex lest the user pass in the relocations | |
506 | * contained within a mmaped bo. For in such a case we, the page | |
507 | * fault handler would call i915_gem_fault() and we would try to | |
508 | * acquire the struct mutex again. Obviously this is bad and so | |
509 | * lockdep complains vehemently. | |
510 | */ | |
511 | pagefault_disable(); | |
27173f1f BW |
512 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
513 | ret = i915_gem_execbuffer_relocate_vma(vma, eb); | |
54cf91dc | 514 | if (ret) |
d4aeee77 | 515 | break; |
54cf91dc | 516 | } |
d4aeee77 | 517 | pagefault_enable(); |
54cf91dc | 518 | |
d4aeee77 | 519 | return ret; |
54cf91dc CW |
520 | } |
521 | ||
1690e1eb | 522 | static int |
27173f1f | 523 | i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, |
a4872ba6 | 524 | struct intel_engine_cs *ring, |
27173f1f | 525 | bool *need_reloc) |
1690e1eb | 526 | { |
6f65e29a | 527 | struct drm_i915_gem_object *obj = vma->obj; |
27173f1f | 528 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
d23db88c | 529 | uint64_t flags; |
1690e1eb CW |
530 | int ret; |
531 | ||
1ec9e26d | 532 | flags = 0; |
e6a84468 | 533 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) |
c826c449 | 534 | flags |= PIN_GLOBAL | PIN_MAPPABLE; |
1ec9e26d | 535 | if (entry->flags & EXEC_OBJECT_NEEDS_GTT) |
bf3d149b | 536 | flags |= PIN_GLOBAL; |
d23db88c CW |
537 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) |
538 | flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; | |
1ec9e26d DV |
539 | |
540 | ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); | |
1690e1eb CW |
541 | if (ret) |
542 | return ret; | |
543 | ||
7788a765 CW |
544 | entry->flags |= __EXEC_OBJECT_HAS_PIN; |
545 | ||
82b6b6d7 CW |
546 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
547 | ret = i915_gem_object_get_fence(obj); | |
548 | if (ret) | |
549 | return ret; | |
9a5a53b3 | 550 | |
82b6b6d7 CW |
551 | if (i915_gem_object_pin_fence(obj)) |
552 | entry->flags |= __EXEC_OBJECT_HAS_FENCE; | |
1690e1eb CW |
553 | } |
554 | ||
27173f1f BW |
555 | if (entry->offset != vma->node.start) { |
556 | entry->offset = vma->node.start; | |
ed5982e6 DV |
557 | *need_reloc = true; |
558 | } | |
559 | ||
560 | if (entry->flags & EXEC_OBJECT_WRITE) { | |
561 | obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; | |
562 | obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; | |
563 | } | |
564 | ||
1690e1eb | 565 | return 0; |
7788a765 | 566 | } |
1690e1eb | 567 | |
d23db88c | 568 | static bool |
e6a84468 | 569 | need_reloc_mappable(struct i915_vma *vma) |
d23db88c CW |
570 | { |
571 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
d23db88c | 572 | |
e6a84468 CW |
573 | if (entry->relocation_count == 0) |
574 | return false; | |
575 | ||
576 | if (!i915_is_ggtt(vma->vm)) | |
577 | return false; | |
578 | ||
579 | /* See also use_cpu_reloc() */ | |
580 | if (HAS_LLC(vma->obj->base.dev)) | |
581 | return false; | |
582 | ||
583 | if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) | |
584 | return false; | |
585 | ||
586 | return true; | |
587 | } | |
588 | ||
589 | static bool | |
590 | eb_vma_misplaced(struct i915_vma *vma) | |
591 | { | |
592 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; | |
593 | struct drm_i915_gem_object *obj = vma->obj; | |
d23db88c | 594 | |
e6a84468 | 595 | WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && |
d23db88c CW |
596 | !i915_is_ggtt(vma->vm)); |
597 | ||
598 | if (entry->alignment && | |
599 | vma->node.start & (entry->alignment - 1)) | |
600 | return true; | |
601 | ||
e6a84468 | 602 | if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) |
d23db88c CW |
603 | return true; |
604 | ||
605 | if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && | |
606 | vma->node.start < BATCH_OFFSET_BIAS) | |
607 | return true; | |
608 | ||
609 | return false; | |
610 | } | |
611 | ||
54cf91dc | 612 | static int |
a4872ba6 | 613 | i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, |
27173f1f | 614 | struct list_head *vmas, |
ed5982e6 | 615 | bool *need_relocs) |
54cf91dc | 616 | { |
432e58ed | 617 | struct drm_i915_gem_object *obj; |
27173f1f | 618 | struct i915_vma *vma; |
68c8c17f | 619 | struct i915_address_space *vm; |
27173f1f | 620 | struct list_head ordered_vmas; |
7788a765 CW |
621 | bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; |
622 | int retry; | |
6fe4f140 | 623 | |
227f782e CW |
624 | i915_gem_retire_requests_ring(ring); |
625 | ||
68c8c17f BW |
626 | vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; |
627 | ||
27173f1f BW |
628 | INIT_LIST_HEAD(&ordered_vmas); |
629 | while (!list_empty(vmas)) { | |
6fe4f140 CW |
630 | struct drm_i915_gem_exec_object2 *entry; |
631 | bool need_fence, need_mappable; | |
632 | ||
27173f1f BW |
633 | vma = list_first_entry(vmas, struct i915_vma, exec_list); |
634 | obj = vma->obj; | |
635 | entry = vma->exec_entry; | |
6fe4f140 | 636 | |
82b6b6d7 CW |
637 | if (!has_fenced_gpu_access) |
638 | entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; | |
6fe4f140 | 639 | need_fence = |
6fe4f140 CW |
640 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
641 | obj->tiling_mode != I915_TILING_NONE; | |
27173f1f | 642 | need_mappable = need_fence || need_reloc_mappable(vma); |
6fe4f140 | 643 | |
e6a84468 CW |
644 | if (need_mappable) { |
645 | entry->flags |= __EXEC_OBJECT_NEEDS_MAP; | |
27173f1f | 646 | list_move(&vma->exec_list, &ordered_vmas); |
e6a84468 | 647 | } else |
27173f1f | 648 | list_move_tail(&vma->exec_list, &ordered_vmas); |
595dad76 | 649 | |
ed5982e6 | 650 | obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; |
595dad76 | 651 | obj->base.pending_write_domain = 0; |
6fe4f140 | 652 | } |
27173f1f | 653 | list_splice(&ordered_vmas, vmas); |
54cf91dc CW |
654 | |
655 | /* Attempt to pin all of the buffers into the GTT. | |
656 | * This is done in 3 phases: | |
657 | * | |
658 | * 1a. Unbind all objects that do not match the GTT constraints for | |
659 | * the execbuffer (fenceable, mappable, alignment etc). | |
660 | * 1b. Increment pin count for already bound objects. | |
661 | * 2. Bind new objects. | |
662 | * 3. Decrement pin count. | |
663 | * | |
7788a765 | 664 | * This avoid unnecessary unbinding of later objects in order to make |
54cf91dc CW |
665 | * room for the earlier objects *unless* we need to defragment. |
666 | */ | |
667 | retry = 0; | |
668 | do { | |
7788a765 | 669 | int ret = 0; |
54cf91dc CW |
670 | |
671 | /* Unbind any ill-fitting objects or pin. */ | |
27173f1f | 672 | list_for_each_entry(vma, vmas, exec_list) { |
27173f1f | 673 | if (!drm_mm_node_allocated(&vma->node)) |
54cf91dc CW |
674 | continue; |
675 | ||
e6a84468 | 676 | if (eb_vma_misplaced(vma)) |
27173f1f | 677 | ret = i915_vma_unbind(vma); |
54cf91dc | 678 | else |
27173f1f | 679 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
432e58ed | 680 | if (ret) |
54cf91dc | 681 | goto err; |
54cf91dc CW |
682 | } |
683 | ||
684 | /* Bind fresh objects */ | |
27173f1f BW |
685 | list_for_each_entry(vma, vmas, exec_list) { |
686 | if (drm_mm_node_allocated(&vma->node)) | |
1690e1eb | 687 | continue; |
54cf91dc | 688 | |
27173f1f | 689 | ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); |
7788a765 CW |
690 | if (ret) |
691 | goto err; | |
54cf91dc CW |
692 | } |
693 | ||
a415d355 | 694 | err: |
6c085a72 | 695 | if (ret != -ENOSPC || retry++) |
54cf91dc CW |
696 | return ret; |
697 | ||
a415d355 CW |
698 | /* Decrement pin count for bound objects */ |
699 | list_for_each_entry(vma, vmas, exec_list) | |
700 | i915_gem_execbuffer_unreserve_vma(vma); | |
701 | ||
68c8c17f | 702 | ret = i915_gem_evict_vm(vm, true); |
54cf91dc CW |
703 | if (ret) |
704 | return ret; | |
54cf91dc CW |
705 | } while (1); |
706 | } | |
707 | ||
708 | static int | |
709 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
ed5982e6 | 710 | struct drm_i915_gem_execbuffer2 *args, |
54cf91dc | 711 | struct drm_file *file, |
a4872ba6 | 712 | struct intel_engine_cs *ring, |
27173f1f BW |
713 | struct eb_vmas *eb, |
714 | struct drm_i915_gem_exec_object2 *exec) | |
54cf91dc CW |
715 | { |
716 | struct drm_i915_gem_relocation_entry *reloc; | |
27173f1f BW |
717 | struct i915_address_space *vm; |
718 | struct i915_vma *vma; | |
ed5982e6 | 719 | bool need_relocs; |
dd6864a4 | 720 | int *reloc_offset; |
54cf91dc | 721 | int i, total, ret; |
b205ca57 | 722 | unsigned count = args->buffer_count; |
54cf91dc | 723 | |
27173f1f BW |
724 | vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; |
725 | ||
67731b87 | 726 | /* We may process another execbuffer during the unlock... */ |
27173f1f BW |
727 | while (!list_empty(&eb->vmas)) { |
728 | vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); | |
729 | list_del_init(&vma->exec_list); | |
a415d355 | 730 | i915_gem_execbuffer_unreserve_vma(vma); |
27173f1f | 731 | drm_gem_object_unreference(&vma->obj->base); |
67731b87 CW |
732 | } |
733 | ||
54cf91dc CW |
734 | mutex_unlock(&dev->struct_mutex); |
735 | ||
736 | total = 0; | |
737 | for (i = 0; i < count; i++) | |
432e58ed | 738 | total += exec[i].relocation_count; |
54cf91dc | 739 | |
dd6864a4 | 740 | reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); |
54cf91dc | 741 | reloc = drm_malloc_ab(total, sizeof(*reloc)); |
dd6864a4 CW |
742 | if (reloc == NULL || reloc_offset == NULL) { |
743 | drm_free_large(reloc); | |
744 | drm_free_large(reloc_offset); | |
54cf91dc CW |
745 | mutex_lock(&dev->struct_mutex); |
746 | return -ENOMEM; | |
747 | } | |
748 | ||
749 | total = 0; | |
750 | for (i = 0; i < count; i++) { | |
751 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
262b6d36 CW |
752 | u64 invalid_offset = (u64)-1; |
753 | int j; | |
54cf91dc | 754 | |
2bb4629a | 755 | user_relocs = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
756 | |
757 | if (copy_from_user(reloc+total, user_relocs, | |
432e58ed | 758 | exec[i].relocation_count * sizeof(*reloc))) { |
54cf91dc CW |
759 | ret = -EFAULT; |
760 | mutex_lock(&dev->struct_mutex); | |
761 | goto err; | |
762 | } | |
763 | ||
262b6d36 CW |
764 | /* As we do not update the known relocation offsets after |
765 | * relocating (due to the complexities in lock handling), | |
766 | * we need to mark them as invalid now so that we force the | |
767 | * relocation processing next time. Just in case the target | |
768 | * object is evicted and then rebound into its old | |
769 | * presumed_offset before the next execbuffer - if that | |
770 | * happened we would make the mistake of assuming that the | |
771 | * relocations were valid. | |
772 | */ | |
773 | for (j = 0; j < exec[i].relocation_count; j++) { | |
9aab8bff CW |
774 | if (__copy_to_user(&user_relocs[j].presumed_offset, |
775 | &invalid_offset, | |
776 | sizeof(invalid_offset))) { | |
262b6d36 CW |
777 | ret = -EFAULT; |
778 | mutex_lock(&dev->struct_mutex); | |
779 | goto err; | |
780 | } | |
781 | } | |
782 | ||
dd6864a4 | 783 | reloc_offset[i] = total; |
432e58ed | 784 | total += exec[i].relocation_count; |
54cf91dc CW |
785 | } |
786 | ||
787 | ret = i915_mutex_lock_interruptible(dev); | |
788 | if (ret) { | |
789 | mutex_lock(&dev->struct_mutex); | |
790 | goto err; | |
791 | } | |
792 | ||
67731b87 | 793 | /* reacquire the objects */ |
67731b87 | 794 | eb_reset(eb); |
27173f1f | 795 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
796 | if (ret) |
797 | goto err; | |
67731b87 | 798 | |
ed5982e6 | 799 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 800 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
801 | if (ret) |
802 | goto err; | |
803 | ||
27173f1f BW |
804 | list_for_each_entry(vma, &eb->vmas, exec_list) { |
805 | int offset = vma->exec_entry - exec; | |
806 | ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, | |
807 | reloc + reloc_offset[offset]); | |
54cf91dc CW |
808 | if (ret) |
809 | goto err; | |
54cf91dc CW |
810 | } |
811 | ||
812 | /* Leave the user relocations as are, this is the painfully slow path, | |
813 | * and we want to avoid the complication of dropping the lock whilst | |
814 | * having buffers reserved in the aperture and so causing spurious | |
815 | * ENOSPC for random operations. | |
816 | */ | |
817 | ||
818 | err: | |
819 | drm_free_large(reloc); | |
dd6864a4 | 820 | drm_free_large(reloc_offset); |
54cf91dc CW |
821 | return ret; |
822 | } | |
823 | ||
54cf91dc | 824 | static int |
a4872ba6 | 825 | i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring, |
27173f1f | 826 | struct list_head *vmas) |
54cf91dc | 827 | { |
27173f1f | 828 | struct i915_vma *vma; |
6ac42f41 | 829 | uint32_t flush_domains = 0; |
000433b6 | 830 | bool flush_chipset = false; |
432e58ed | 831 | int ret; |
54cf91dc | 832 | |
27173f1f BW |
833 | list_for_each_entry(vma, vmas, exec_list) { |
834 | struct drm_i915_gem_object *obj = vma->obj; | |
6ac42f41 | 835 | ret = i915_gem_object_sync(obj, ring); |
c59a333f CW |
836 | if (ret) |
837 | return ret; | |
6ac42f41 DV |
838 | |
839 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
000433b6 | 840 | flush_chipset |= i915_gem_clflush_object(obj, false); |
6ac42f41 | 841 | |
6ac42f41 | 842 | flush_domains |= obj->base.write_domain; |
c59a333f CW |
843 | } |
844 | ||
000433b6 | 845 | if (flush_chipset) |
e76e9aeb | 846 | i915_gem_chipset_flush(ring->dev); |
6ac42f41 DV |
847 | |
848 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
849 | wmb(); | |
850 | ||
09cf7c9a CW |
851 | /* Unconditionally invalidate gpu caches and ensure that we do flush |
852 | * any residual writes from the previous batch. | |
853 | */ | |
a7b9761d | 854 | return intel_ring_invalidate_all_caches(ring); |
54cf91dc CW |
855 | } |
856 | ||
432e58ed CW |
857 | static bool |
858 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) | |
54cf91dc | 859 | { |
ed5982e6 DV |
860 | if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) |
861 | return false; | |
862 | ||
432e58ed | 863 | return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; |
54cf91dc CW |
864 | } |
865 | ||
866 | static int | |
ad19f10b CW |
867 | validate_exec_list(struct drm_device *dev, |
868 | struct drm_i915_gem_exec_object2 *exec, | |
54cf91dc CW |
869 | int count) |
870 | { | |
b205ca57 DV |
871 | unsigned relocs_total = 0; |
872 | unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); | |
ad19f10b CW |
873 | unsigned invalid_flags; |
874 | int i; | |
875 | ||
876 | invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; | |
877 | if (USES_FULL_PPGTT(dev)) | |
878 | invalid_flags |= EXEC_OBJECT_NEEDS_GTT; | |
54cf91dc CW |
879 | |
880 | for (i = 0; i < count; i++) { | |
2bb4629a | 881 | char __user *ptr = to_user_ptr(exec[i].relocs_ptr); |
54cf91dc CW |
882 | int length; /* limited by fault_in_pages_readable() */ |
883 | ||
ad19f10b | 884 | if (exec[i].flags & invalid_flags) |
ed5982e6 DV |
885 | return -EINVAL; |
886 | ||
3118a4f6 KC |
887 | /* First check for malicious input causing overflow in |
888 | * the worst case where we need to allocate the entire | |
889 | * relocation tree as a single array. | |
890 | */ | |
891 | if (exec[i].relocation_count > relocs_max - relocs_total) | |
54cf91dc | 892 | return -EINVAL; |
3118a4f6 | 893 | relocs_total += exec[i].relocation_count; |
54cf91dc CW |
894 | |
895 | length = exec[i].relocation_count * | |
896 | sizeof(struct drm_i915_gem_relocation_entry); | |
30587535 KC |
897 | /* |
898 | * We must check that the entire relocation array is safe | |
899 | * to read, but since we may need to update the presumed | |
900 | * offsets during execution, check for full write access. | |
901 | */ | |
54cf91dc CW |
902 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
903 | return -EFAULT; | |
904 | ||
d330a953 | 905 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
906 | if (fault_in_multipages_readable(ptr, length)) |
907 | return -EFAULT; | |
908 | } | |
54cf91dc CW |
909 | } |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
273497e5 | 914 | static struct intel_context * |
d299cce7 | 915 | i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, |
a4872ba6 | 916 | struct intel_engine_cs *ring, const u32 ctx_id) |
d299cce7 | 917 | { |
273497e5 | 918 | struct intel_context *ctx = NULL; |
d299cce7 MK |
919 | struct i915_ctx_hang_stats *hs; |
920 | ||
821d66dd | 921 | if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) |
7c9c4b8f DV |
922 | return ERR_PTR(-EINVAL); |
923 | ||
41bde553 | 924 | ctx = i915_gem_context_get(file->driver_priv, ctx_id); |
72ad5c45 | 925 | if (IS_ERR(ctx)) |
41bde553 | 926 | return ctx; |
d299cce7 | 927 | |
41bde553 | 928 | hs = &ctx->hang_stats; |
d299cce7 MK |
929 | if (hs->banned) { |
930 | DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); | |
41bde553 | 931 | return ERR_PTR(-EIO); |
d299cce7 MK |
932 | } |
933 | ||
ec3e9963 OM |
934 | if (i915.enable_execlists && !ctx->engine[ring->id].state) { |
935 | int ret = intel_lr_context_deferred_create(ctx, ring); | |
936 | if (ret) { | |
937 | DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); | |
938 | return ERR_PTR(ret); | |
939 | } | |
940 | } | |
941 | ||
41bde553 | 942 | return ctx; |
d299cce7 MK |
943 | } |
944 | ||
ba8b7ccb | 945 | void |
27173f1f | 946 | i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
a4872ba6 | 947 | struct intel_engine_cs *ring) |
432e58ed | 948 | { |
97b2a6a1 | 949 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
27173f1f | 950 | struct i915_vma *vma; |
432e58ed | 951 | |
27173f1f | 952 | list_for_each_entry(vma, vmas, exec_list) { |
82b6b6d7 | 953 | struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; |
27173f1f | 954 | struct drm_i915_gem_object *obj = vma->obj; |
69c2fc89 CW |
955 | u32 old_read = obj->base.read_domains; |
956 | u32 old_write = obj->base.write_domain; | |
db53a302 | 957 | |
432e58ed | 958 | obj->base.write_domain = obj->base.pending_write_domain; |
ed5982e6 DV |
959 | if (obj->base.write_domain == 0) |
960 | obj->base.pending_read_domains |= obj->base.read_domains; | |
961 | obj->base.read_domains = obj->base.pending_read_domains; | |
432e58ed | 962 | |
e2d05a8b | 963 | i915_vma_move_to_active(vma, ring); |
432e58ed CW |
964 | if (obj->base.write_domain) { |
965 | obj->dirty = 1; | |
97b2a6a1 | 966 | i915_gem_request_assign(&obj->last_write_req, req); |
f99d7069 DV |
967 | |
968 | intel_fb_obj_invalidate(obj, ring); | |
c8725f3d CW |
969 | |
970 | /* update for the implicit flush after a batch */ | |
971 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
432e58ed | 972 | } |
82b6b6d7 | 973 | if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { |
97b2a6a1 | 974 | i915_gem_request_assign(&obj->last_fenced_req, req); |
82b6b6d7 CW |
975 | if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { |
976 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
977 | list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, | |
978 | &dev_priv->mm.fence_list); | |
979 | } | |
980 | } | |
432e58ed | 981 | |
db53a302 | 982 | trace_i915_gem_object_change_domain(obj, old_read, old_write); |
432e58ed CW |
983 | } |
984 | } | |
985 | ||
ba8b7ccb | 986 | void |
54cf91dc | 987 | i915_gem_execbuffer_retire_commands(struct drm_device *dev, |
432e58ed | 988 | struct drm_file *file, |
a4872ba6 | 989 | struct intel_engine_cs *ring, |
7d736f4f | 990 | struct drm_i915_gem_object *obj) |
54cf91dc | 991 | { |
cc889e0f DV |
992 | /* Unconditionally force add_request to emit a full flush. */ |
993 | ring->gpu_caches_dirty = true; | |
54cf91dc | 994 | |
432e58ed | 995 | /* Add a breadcrumb for the completion of the batch buffer */ |
7d736f4f | 996 | (void)__i915_add_request(ring, file, obj, NULL); |
432e58ed | 997 | } |
54cf91dc | 998 | |
ae662d31 EA |
999 | static int |
1000 | i915_reset_gen7_sol_offsets(struct drm_device *dev, | |
a4872ba6 | 1001 | struct intel_engine_cs *ring) |
ae662d31 | 1002 | { |
50227e1c | 1003 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae662d31 EA |
1004 | int ret, i; |
1005 | ||
9d662da8 DV |
1006 | if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { |
1007 | DRM_DEBUG("sol reset is gen7/rcs only\n"); | |
1008 | return -EINVAL; | |
1009 | } | |
ae662d31 EA |
1010 | |
1011 | ret = intel_ring_begin(ring, 4 * 3); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
1015 | for (i = 0; i < 4; i++) { | |
1016 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1017 | intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); | |
1018 | intel_ring_emit(ring, 0); | |
1019 | } | |
1020 | ||
1021 | intel_ring_advance(ring); | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
5c6c6003 CW |
1026 | static int |
1027 | i915_emit_box(struct intel_engine_cs *ring, | |
1028 | struct drm_clip_rect *box, | |
1029 | int DR1, int DR4) | |
1030 | { | |
1031 | int ret; | |
1032 | ||
1033 | if (box->y2 <= box->y1 || box->x2 <= box->x1 || | |
1034 | box->y2 <= 0 || box->x2 <= 0) { | |
1035 | DRM_ERROR("Bad box %d,%d..%d,%d\n", | |
1036 | box->x1, box->y1, box->x2, box->y2); | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | if (INTEL_INFO(ring->dev)->gen >= 4) { | |
1041 | ret = intel_ring_begin(ring, 4); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | ||
1045 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); | |
1046 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1047 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1048 | intel_ring_emit(ring, DR4); | |
1049 | } else { | |
1050 | ret = intel_ring_begin(ring, 6); | |
1051 | if (ret) | |
1052 | return ret; | |
1053 | ||
1054 | intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); | |
1055 | intel_ring_emit(ring, DR1); | |
1056 | intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); | |
1057 | intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); | |
1058 | intel_ring_emit(ring, DR4); | |
1059 | intel_ring_emit(ring, 0); | |
1060 | } | |
1061 | intel_ring_advance(ring); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | ||
a83014d3 OM |
1067 | int |
1068 | i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, | |
1069 | struct intel_engine_cs *ring, | |
1070 | struct intel_context *ctx, | |
1071 | struct drm_i915_gem_execbuffer2 *args, | |
1072 | struct list_head *vmas, | |
1073 | struct drm_i915_gem_object *batch_obj, | |
1074 | u64 exec_start, u32 flags) | |
78382593 OM |
1075 | { |
1076 | struct drm_clip_rect *cliprects = NULL; | |
1077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1078 | u64 exec_len; | |
1079 | int instp_mode; | |
1080 | u32 instp_mask; | |
1081 | int i, ret = 0; | |
1082 | ||
1083 | if (args->num_cliprects != 0) { | |
1084 | if (ring != &dev_priv->ring[RCS]) { | |
1085 | DRM_DEBUG("clip rectangles are only valid with the render ring\n"); | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | ||
1089 | if (INTEL_INFO(dev)->gen >= 5) { | |
1090 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
1094 | if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { | |
1095 | DRM_DEBUG("execbuf with %u cliprects\n", | |
1096 | args->num_cliprects); | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
1100 | cliprects = kcalloc(args->num_cliprects, | |
1101 | sizeof(*cliprects), | |
1102 | GFP_KERNEL); | |
1103 | if (cliprects == NULL) { | |
1104 | ret = -ENOMEM; | |
1105 | goto error; | |
1106 | } | |
1107 | ||
1108 | if (copy_from_user(cliprects, | |
1109 | to_user_ptr(args->cliprects_ptr), | |
1110 | sizeof(*cliprects)*args->num_cliprects)) { | |
1111 | ret = -EFAULT; | |
1112 | goto error; | |
1113 | } | |
1114 | } else { | |
1115 | if (args->DR4 == 0xffffffff) { | |
1116 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
1117 | args->DR4 = 0; | |
1118 | } | |
1119 | ||
1120 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
1121 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | ret = i915_gem_execbuffer_move_to_gpu(ring, vmas); | |
1127 | if (ret) | |
1128 | goto error; | |
1129 | ||
1130 | ret = i915_switch_context(ring, ctx); | |
1131 | if (ret) | |
1132 | goto error; | |
1133 | ||
1134 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
1135 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
1136 | switch (instp_mode) { | |
1137 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
1138 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
1139 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
1140 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
1141 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
1142 | ret = -EINVAL; | |
1143 | goto error; | |
1144 | } | |
1145 | ||
1146 | if (instp_mode != dev_priv->relative_constants_mode) { | |
1147 | if (INTEL_INFO(dev)->gen < 4) { | |
1148 | DRM_DEBUG("no rel constants on pre-gen4\n"); | |
1149 | ret = -EINVAL; | |
1150 | goto error; | |
1151 | } | |
1152 | ||
1153 | if (INTEL_INFO(dev)->gen > 5 && | |
1154 | instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
1155 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
1156 | ret = -EINVAL; | |
1157 | goto error; | |
1158 | } | |
1159 | ||
1160 | /* The HW changed the meaning on this bit on gen6 */ | |
1161 | if (INTEL_INFO(dev)->gen >= 6) | |
1162 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
1163 | } | |
1164 | break; | |
1165 | default: | |
1166 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
1167 | ret = -EINVAL; | |
1168 | goto error; | |
1169 | } | |
1170 | ||
1171 | if (ring == &dev_priv->ring[RCS] && | |
1172 | instp_mode != dev_priv->relative_constants_mode) { | |
1173 | ret = intel_ring_begin(ring, 4); | |
1174 | if (ret) | |
1175 | goto error; | |
1176 | ||
1177 | intel_ring_emit(ring, MI_NOOP); | |
1178 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
1179 | intel_ring_emit(ring, INSTPM); | |
1180 | intel_ring_emit(ring, instp_mask << 16 | instp_mode); | |
1181 | intel_ring_advance(ring); | |
1182 | ||
1183 | dev_priv->relative_constants_mode = instp_mode; | |
1184 | } | |
1185 | ||
1186 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
1187 | ret = i915_reset_gen7_sol_offsets(dev, ring); | |
1188 | if (ret) | |
1189 | goto error; | |
1190 | } | |
1191 | ||
1192 | exec_len = args->batch_len; | |
1193 | if (cliprects) { | |
1194 | for (i = 0; i < args->num_cliprects; i++) { | |
5c6c6003 | 1195 | ret = i915_emit_box(ring, &cliprects[i], |
78382593 OM |
1196 | args->DR1, args->DR4); |
1197 | if (ret) | |
1198 | goto error; | |
1199 | ||
1200 | ret = ring->dispatch_execbuffer(ring, | |
1201 | exec_start, exec_len, | |
1202 | flags); | |
1203 | if (ret) | |
1204 | goto error; | |
1205 | } | |
1206 | } else { | |
1207 | ret = ring->dispatch_execbuffer(ring, | |
1208 | exec_start, exec_len, | |
1209 | flags); | |
1210 | if (ret) | |
1211 | return ret; | |
1212 | } | |
1213 | ||
1214 | trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags); | |
1215 | ||
1216 | i915_gem_execbuffer_move_to_active(vmas, ring); | |
1217 | i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); | |
1218 | ||
1219 | error: | |
1220 | kfree(cliprects); | |
1221 | return ret; | |
1222 | } | |
1223 | ||
a8ebba75 ZY |
1224 | /** |
1225 | * Find one BSD ring to dispatch the corresponding BSD command. | |
1226 | * The Ring ID is returned. | |
1227 | */ | |
1228 | static int gen8_dispatch_bsd_ring(struct drm_device *dev, | |
1229 | struct drm_file *file) | |
1230 | { | |
1231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1232 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1233 | ||
1234 | /* Check whether the file_priv is using one ring */ | |
1235 | if (file_priv->bsd_ring) | |
1236 | return file_priv->bsd_ring->id; | |
1237 | else { | |
1238 | /* If no, use the ping-pong mechanism to select one ring */ | |
1239 | int ring_id; | |
1240 | ||
1241 | mutex_lock(&dev->struct_mutex); | |
bdf1e7e3 | 1242 | if (dev_priv->mm.bsd_ring_dispatch_index == 0) { |
a8ebba75 | 1243 | ring_id = VCS; |
bdf1e7e3 | 1244 | dev_priv->mm.bsd_ring_dispatch_index = 1; |
a8ebba75 ZY |
1245 | } else { |
1246 | ring_id = VCS2; | |
bdf1e7e3 | 1247 | dev_priv->mm.bsd_ring_dispatch_index = 0; |
a8ebba75 ZY |
1248 | } |
1249 | file_priv->bsd_ring = &dev_priv->ring[ring_id]; | |
1250 | mutex_unlock(&dev->struct_mutex); | |
1251 | return ring_id; | |
1252 | } | |
1253 | } | |
1254 | ||
d23db88c CW |
1255 | static struct drm_i915_gem_object * |
1256 | eb_get_batch(struct eb_vmas *eb) | |
1257 | { | |
1258 | struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); | |
1259 | ||
1260 | /* | |
1261 | * SNA is doing fancy tricks with compressing batch buffers, which leads | |
1262 | * to negative relocation deltas. Usually that works out ok since the | |
1263 | * relocate address is still positive, except when the batch is placed | |
1264 | * very low in the GTT. Ensure this doesn't happen. | |
1265 | * | |
1266 | * Note that actual hangs have only been observed on gen7, but for | |
1267 | * paranoia do it everywhere. | |
1268 | */ | |
1269 | vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; | |
1270 | ||
1271 | return vma->obj; | |
1272 | } | |
1273 | ||
54cf91dc CW |
1274 | static int |
1275 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |
1276 | struct drm_file *file, | |
1277 | struct drm_i915_gem_execbuffer2 *args, | |
41bde553 | 1278 | struct drm_i915_gem_exec_object2 *exec) |
54cf91dc | 1279 | { |
50227e1c | 1280 | struct drm_i915_private *dev_priv = dev->dev_private; |
27173f1f | 1281 | struct eb_vmas *eb; |
54cf91dc | 1282 | struct drm_i915_gem_object *batch_obj; |
a4872ba6 | 1283 | struct intel_engine_cs *ring; |
273497e5 | 1284 | struct intel_context *ctx; |
41bde553 | 1285 | struct i915_address_space *vm; |
d299cce7 | 1286 | const u32 ctx_id = i915_execbuffer2_get_context_id(*args); |
78382593 OM |
1287 | u64 exec_start = args->batch_start_offset; |
1288 | u32 flags; | |
1289 | int ret; | |
ed5982e6 | 1290 | bool need_relocs; |
54cf91dc | 1291 | |
ed5982e6 | 1292 | if (!i915_gem_check_execbuffer(args)) |
432e58ed | 1293 | return -EINVAL; |
432e58ed | 1294 | |
ad19f10b | 1295 | ret = validate_exec_list(dev, exec, args->buffer_count); |
54cf91dc CW |
1296 | if (ret) |
1297 | return ret; | |
1298 | ||
d7d4eedd CW |
1299 | flags = 0; |
1300 | if (args->flags & I915_EXEC_SECURE) { | |
1301 | if (!file->is_master || !capable(CAP_SYS_ADMIN)) | |
1302 | return -EPERM; | |
1303 | ||
1304 | flags |= I915_DISPATCH_SECURE; | |
1305 | } | |
b45305fc DV |
1306 | if (args->flags & I915_EXEC_IS_PINNED) |
1307 | flags |= I915_DISPATCH_PINNED; | |
d7d4eedd | 1308 | |
b1a93306 | 1309 | if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { |
ff240199 | 1310 | DRM_DEBUG("execbuf with unknown ring: %d\n", |
54cf91dc CW |
1311 | (int)(args->flags & I915_EXEC_RING_MASK)); |
1312 | return -EINVAL; | |
1313 | } | |
ca01b12b BW |
1314 | |
1315 | if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) | |
1316 | ring = &dev_priv->ring[RCS]; | |
a8ebba75 ZY |
1317 | else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { |
1318 | if (HAS_BSD2(dev)) { | |
1319 | int ring_id; | |
1320 | ring_id = gen8_dispatch_bsd_ring(dev, file); | |
1321 | ring = &dev_priv->ring[ring_id]; | |
1322 | } else | |
1323 | ring = &dev_priv->ring[VCS]; | |
1324 | } else | |
ca01b12b BW |
1325 | ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; |
1326 | ||
a15817cf CW |
1327 | if (!intel_ring_initialized(ring)) { |
1328 | DRM_DEBUG("execbuf with invalid ring: %d\n", | |
1329 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
1330 | return -EINVAL; | |
1331 | } | |
54cf91dc CW |
1332 | |
1333 | if (args->buffer_count < 1) { | |
ff240199 | 1334 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1335 | return -EINVAL; |
1336 | } | |
54cf91dc | 1337 | |
f65c9168 PZ |
1338 | intel_runtime_pm_get(dev_priv); |
1339 | ||
54cf91dc CW |
1340 | ret = i915_mutex_lock_interruptible(dev); |
1341 | if (ret) | |
1342 | goto pre_mutex_err; | |
1343 | ||
7c9c4b8f | 1344 | ctx = i915_gem_validate_context(dev, file, ring, ctx_id); |
72ad5c45 | 1345 | if (IS_ERR(ctx)) { |
d299cce7 | 1346 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1347 | ret = PTR_ERR(ctx); |
d299cce7 | 1348 | goto pre_mutex_err; |
935f38d6 | 1349 | } |
41bde553 BW |
1350 | |
1351 | i915_gem_context_reference(ctx); | |
1352 | ||
ae6c4806 DV |
1353 | if (ctx->ppgtt) |
1354 | vm = &ctx->ppgtt->base; | |
1355 | else | |
7e0d96bc | 1356 | vm = &dev_priv->gtt.base; |
d299cce7 | 1357 | |
17601cbc | 1358 | eb = eb_create(args); |
67731b87 | 1359 | if (eb == NULL) { |
935f38d6 | 1360 | i915_gem_context_unreference(ctx); |
67731b87 CW |
1361 | mutex_unlock(&dev->struct_mutex); |
1362 | ret = -ENOMEM; | |
1363 | goto pre_mutex_err; | |
1364 | } | |
1365 | ||
54cf91dc | 1366 | /* Look up object handles */ |
27173f1f | 1367 | ret = eb_lookup_vmas(eb, exec, args, vm, file); |
3b96eff4 CW |
1368 | if (ret) |
1369 | goto err; | |
54cf91dc | 1370 | |
6fe4f140 | 1371 | /* take note of the batch buffer before we might reorder the lists */ |
d23db88c | 1372 | batch_obj = eb_get_batch(eb); |
6fe4f140 | 1373 | |
54cf91dc | 1374 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
ed5982e6 | 1375 | need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; |
27173f1f | 1376 | ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs); |
54cf91dc CW |
1377 | if (ret) |
1378 | goto err; | |
1379 | ||
1380 | /* The objects are in their final locations, apply the relocations. */ | |
ed5982e6 | 1381 | if (need_relocs) |
17601cbc | 1382 | ret = i915_gem_execbuffer_relocate(eb); |
54cf91dc CW |
1383 | if (ret) { |
1384 | if (ret == -EFAULT) { | |
ed5982e6 | 1385 | ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, |
27173f1f | 1386 | eb, exec); |
54cf91dc CW |
1387 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
1388 | } | |
1389 | if (ret) | |
1390 | goto err; | |
1391 | } | |
1392 | ||
1393 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
54cf91dc | 1394 | if (batch_obj->base.pending_write_domain) { |
ff240199 | 1395 | DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); |
54cf91dc CW |
1396 | ret = -EINVAL; |
1397 | goto err; | |
1398 | } | |
1399 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
1400 | ||
351e3db2 BV |
1401 | if (i915_needs_cmd_parser(ring)) { |
1402 | ret = i915_parse_cmds(ring, | |
1403 | batch_obj, | |
1404 | args->batch_start_offset, | |
1405 | file->is_master); | |
42c7156a BV |
1406 | if (ret) { |
1407 | if (ret != -EACCES) | |
1408 | goto err; | |
1409 | } else { | |
1410 | /* | |
1411 | * XXX: Actually do this when enabling batch copy... | |
1412 | * | |
1413 | * Set the DISPATCH_SECURE bit to remove the NON_SECURE bit | |
1414 | * from MI_BATCH_BUFFER_START commands issued in the | |
1415 | * dispatch_execbuffer implementations. We specifically don't | |
1416 | * want that set when the command parser is enabled. | |
1417 | */ | |
1418 | } | |
351e3db2 BV |
1419 | } |
1420 | ||
d7d4eedd CW |
1421 | /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure |
1422 | * batch" bit. Hence we need to pin secure batches into the global gtt. | |
28cf5415 | 1423 | * hsw should have this fixed, but bdw mucks it up again. */ |
da51a1e7 DV |
1424 | if (flags & I915_DISPATCH_SECURE) { |
1425 | /* | |
1426 | * So on first glance it looks freaky that we pin the batch here | |
1427 | * outside of the reservation loop. But: | |
1428 | * - The batch is already pinned into the relevant ppgtt, so we | |
1429 | * already have the backing storage fully allocated. | |
1430 | * - No other BO uses the global gtt (well contexts, but meh), | |
1431 | * so we don't really have issues with mutliple objects not | |
1432 | * fitting due to fragmentation. | |
1433 | * So this is actually safe. | |
1434 | */ | |
1435 | ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); | |
1436 | if (ret) | |
1437 | goto err; | |
d7d4eedd | 1438 | |
7e0d96bc | 1439 | exec_start += i915_gem_obj_ggtt_offset(batch_obj); |
da51a1e7 | 1440 | } else |
7e0d96bc | 1441 | exec_start += i915_gem_obj_offset(batch_obj, vm); |
d7d4eedd | 1442 | |
a83014d3 OM |
1443 | ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args, |
1444 | &eb->vmas, batch_obj, exec_start, flags); | |
54cf91dc | 1445 | |
da51a1e7 DV |
1446 | /* |
1447 | * FIXME: We crucially rely upon the active tracking for the (ppgtt) | |
1448 | * batch vma for correctness. For less ugly and less fragility this | |
1449 | * needs to be adjusted to also track the ggtt batch vma properly as | |
1450 | * active. | |
1451 | */ | |
1452 | if (flags & I915_DISPATCH_SECURE) | |
1453 | i915_gem_object_ggtt_unpin(batch_obj); | |
54cf91dc | 1454 | err: |
41bde553 BW |
1455 | /* the request owns the ref now */ |
1456 | i915_gem_context_unreference(ctx); | |
67731b87 | 1457 | eb_destroy(eb); |
54cf91dc CW |
1458 | |
1459 | mutex_unlock(&dev->struct_mutex); | |
1460 | ||
1461 | pre_mutex_err: | |
f65c9168 PZ |
1462 | /* intel_gpu_busy should also get a ref, so it will free when the device |
1463 | * is really idle. */ | |
1464 | intel_runtime_pm_put(dev_priv); | |
54cf91dc CW |
1465 | return ret; |
1466 | } | |
1467 | ||
1468 | /* | |
1469 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
1470 | * list array and passes it to the real function. | |
1471 | */ | |
1472 | int | |
1473 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1474 | struct drm_file *file) | |
1475 | { | |
1476 | struct drm_i915_gem_execbuffer *args = data; | |
1477 | struct drm_i915_gem_execbuffer2 exec2; | |
1478 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1479 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1480 | int ret, i; | |
1481 | ||
54cf91dc | 1482 | if (args->buffer_count < 1) { |
ff240199 | 1483 | DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1484 | return -EINVAL; |
1485 | } | |
1486 | ||
1487 | /* Copy in the exec list from userland */ | |
1488 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
1489 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
1490 | if (exec_list == NULL || exec2_list == NULL) { | |
ff240199 | 1491 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1492 | args->buffer_count); |
1493 | drm_free_large(exec_list); | |
1494 | drm_free_large(exec2_list); | |
1495 | return -ENOMEM; | |
1496 | } | |
1497 | ret = copy_from_user(exec_list, | |
2bb4629a | 1498 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1499 | sizeof(*exec_list) * args->buffer_count); |
1500 | if (ret != 0) { | |
ff240199 | 1501 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1502 | args->buffer_count, ret); |
1503 | drm_free_large(exec_list); | |
1504 | drm_free_large(exec2_list); | |
1505 | return -EFAULT; | |
1506 | } | |
1507 | ||
1508 | for (i = 0; i < args->buffer_count; i++) { | |
1509 | exec2_list[i].handle = exec_list[i].handle; | |
1510 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
1511 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
1512 | exec2_list[i].alignment = exec_list[i].alignment; | |
1513 | exec2_list[i].offset = exec_list[i].offset; | |
1514 | if (INTEL_INFO(dev)->gen < 4) | |
1515 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
1516 | else | |
1517 | exec2_list[i].flags = 0; | |
1518 | } | |
1519 | ||
1520 | exec2.buffers_ptr = args->buffers_ptr; | |
1521 | exec2.buffer_count = args->buffer_count; | |
1522 | exec2.batch_start_offset = args->batch_start_offset; | |
1523 | exec2.batch_len = args->batch_len; | |
1524 | exec2.DR1 = args->DR1; | |
1525 | exec2.DR4 = args->DR4; | |
1526 | exec2.num_cliprects = args->num_cliprects; | |
1527 | exec2.cliprects_ptr = args->cliprects_ptr; | |
1528 | exec2.flags = I915_EXEC_RENDER; | |
6e0a69db | 1529 | i915_execbuffer2_set_context_id(exec2, 0); |
54cf91dc | 1530 | |
41bde553 | 1531 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
54cf91dc | 1532 | if (!ret) { |
9aab8bff CW |
1533 | struct drm_i915_gem_exec_object __user *user_exec_list = |
1534 | to_user_ptr(args->buffers_ptr); | |
1535 | ||
54cf91dc | 1536 | /* Copy the new buffer offsets back to the user's exec list. */ |
9aab8bff CW |
1537 | for (i = 0; i < args->buffer_count; i++) { |
1538 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1539 | &exec2_list[i].offset, | |
1540 | sizeof(user_exec_list[i].offset)); | |
1541 | if (ret) { | |
1542 | ret = -EFAULT; | |
1543 | DRM_DEBUG("failed to copy %d exec entries " | |
1544 | "back to user (%d)\n", | |
1545 | args->buffer_count, ret); | |
1546 | break; | |
1547 | } | |
54cf91dc CW |
1548 | } |
1549 | } | |
1550 | ||
1551 | drm_free_large(exec_list); | |
1552 | drm_free_large(exec2_list); | |
1553 | return ret; | |
1554 | } | |
1555 | ||
1556 | int | |
1557 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
1558 | struct drm_file *file) | |
1559 | { | |
1560 | struct drm_i915_gem_execbuffer2 *args = data; | |
1561 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
1562 | int ret; | |
1563 | ||
ed8cd3b2 XW |
1564 | if (args->buffer_count < 1 || |
1565 | args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { | |
ff240199 | 1566 | DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); |
54cf91dc CW |
1567 | return -EINVAL; |
1568 | } | |
1569 | ||
9cb34664 DV |
1570 | if (args->rsvd2 != 0) { |
1571 | DRM_DEBUG("dirty rvsd2 field\n"); | |
1572 | return -EINVAL; | |
1573 | } | |
1574 | ||
8408c282 | 1575 | exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, |
419fa72a | 1576 | GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY); |
8408c282 CW |
1577 | if (exec2_list == NULL) |
1578 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), | |
1579 | args->buffer_count); | |
54cf91dc | 1580 | if (exec2_list == NULL) { |
ff240199 | 1581 | DRM_DEBUG("Failed to allocate exec list for %d buffers\n", |
54cf91dc CW |
1582 | args->buffer_count); |
1583 | return -ENOMEM; | |
1584 | } | |
1585 | ret = copy_from_user(exec2_list, | |
2bb4629a | 1586 | to_user_ptr(args->buffers_ptr), |
54cf91dc CW |
1587 | sizeof(*exec2_list) * args->buffer_count); |
1588 | if (ret != 0) { | |
ff240199 | 1589 | DRM_DEBUG("copy %d exec entries failed %d\n", |
54cf91dc CW |
1590 | args->buffer_count, ret); |
1591 | drm_free_large(exec2_list); | |
1592 | return -EFAULT; | |
1593 | } | |
1594 | ||
41bde553 | 1595 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
54cf91dc CW |
1596 | if (!ret) { |
1597 | /* Copy the new buffer offsets back to the user's exec list. */ | |
d593d992 | 1598 | struct drm_i915_gem_exec_object2 __user *user_exec_list = |
9aab8bff CW |
1599 | to_user_ptr(args->buffers_ptr); |
1600 | int i; | |
1601 | ||
1602 | for (i = 0; i < args->buffer_count; i++) { | |
1603 | ret = __copy_to_user(&user_exec_list[i].offset, | |
1604 | &exec2_list[i].offset, | |
1605 | sizeof(user_exec_list[i].offset)); | |
1606 | if (ret) { | |
1607 | ret = -EFAULT; | |
1608 | DRM_DEBUG("failed to copy %d exec entries " | |
1609 | "back to user\n", | |
1610 | args->buffer_count); | |
1611 | break; | |
1612 | } | |
54cf91dc CW |
1613 | } |
1614 | } | |
1615 | ||
1616 | drm_free_large(exec2_list); | |
1617 | return ret; | |
1618 | } |