Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
cfa7c862 DV |
36 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
37 | { | |
1893a71b CW |
38 | bool has_aliasing_ppgtt; |
39 | bool has_full_ppgtt; | |
40 | ||
41 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
42 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
43 | if (IS_GEN8(dev)) | |
44 | has_full_ppgtt = false; /* XXX why? */ | |
45 | ||
70ee45e1 DL |
46 | /* |
47 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
48 | * execlists, the sole mechanism available to submit work. | |
49 | */ | |
50 | if (INTEL_INFO(dev)->gen < 9 && | |
51 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
52 | return 0; |
53 | ||
54 | if (enable_ppgtt == 1) | |
55 | return 1; | |
56 | ||
1893a71b | 57 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
58 | return 2; |
59 | ||
93a25a9e DV |
60 | #ifdef CONFIG_INTEL_IOMMU |
61 | /* Disable ppgtt on SNB if VT-d is on. */ | |
62 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
63 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 64 | return 0; |
93a25a9e DV |
65 | } |
66 | #endif | |
67 | ||
62942ed7 | 68 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
69 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
70 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
71 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
72 | return 0; | |
73 | } | |
74 | ||
cacc6c83 | 75 | return has_aliasing_ppgtt ? 1 : 0; |
93a25a9e DV |
76 | } |
77 | ||
fbe5d36e | 78 | |
6f65e29a BW |
79 | static void ppgtt_bind_vma(struct i915_vma *vma, |
80 | enum i915_cache_level cache_level, | |
81 | u32 flags); | |
82 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
83 | ||
94ec8f61 BW |
84 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
85 | enum i915_cache_level level, | |
86 | bool valid) | |
87 | { | |
88 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
89 | pte |= addr; | |
63c42e56 BW |
90 | |
91 | switch (level) { | |
92 | case I915_CACHE_NONE: | |
fbe5d36e | 93 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
94 | break; |
95 | case I915_CACHE_WT: | |
96 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
97 | break; | |
98 | default: | |
99 | pte |= PPAT_CACHED_INDEX; | |
100 | break; | |
101 | } | |
102 | ||
94ec8f61 BW |
103 | return pte; |
104 | } | |
105 | ||
b1fe6673 BW |
106 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
107 | dma_addr_t addr, | |
108 | enum i915_cache_level level) | |
109 | { | |
110 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
111 | pde |= addr; | |
112 | if (level != I915_CACHE_NONE) | |
113 | pde |= PPAT_CACHED_PDE_INDEX; | |
114 | else | |
115 | pde |= PPAT_UNCACHED_INDEX; | |
116 | return pde; | |
117 | } | |
118 | ||
350ec881 | 119 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 120 | enum i915_cache_level level, |
24f3a8cf | 121 | bool valid, u32 unused) |
54d12527 | 122 | { |
b35b380e | 123 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 124 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
125 | |
126 | switch (level) { | |
350ec881 CW |
127 | case I915_CACHE_L3_LLC: |
128 | case I915_CACHE_LLC: | |
129 | pte |= GEN6_PTE_CACHE_LLC; | |
130 | break; | |
131 | case I915_CACHE_NONE: | |
132 | pte |= GEN6_PTE_UNCACHED; | |
133 | break; | |
134 | default: | |
135 | WARN_ON(1); | |
136 | } | |
137 | ||
138 | return pte; | |
139 | } | |
140 | ||
141 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 142 | enum i915_cache_level level, |
24f3a8cf | 143 | bool valid, u32 unused) |
350ec881 | 144 | { |
b35b380e | 145 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
146 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
147 | ||
148 | switch (level) { | |
149 | case I915_CACHE_L3_LLC: | |
150 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
151 | break; |
152 | case I915_CACHE_LLC: | |
153 | pte |= GEN6_PTE_CACHE_LLC; | |
154 | break; | |
155 | case I915_CACHE_NONE: | |
9119708c | 156 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
157 | break; |
158 | default: | |
350ec881 | 159 | WARN_ON(1); |
e7210c3c BW |
160 | } |
161 | ||
54d12527 BW |
162 | return pte; |
163 | } | |
164 | ||
80a74f7f | 165 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 166 | enum i915_cache_level level, |
24f3a8cf | 167 | bool valid, u32 flags) |
93c34e70 | 168 | { |
b35b380e | 169 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
170 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
171 | ||
24f3a8cf AG |
172 | if (!(flags & PTE_READ_ONLY)) |
173 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
174 | |
175 | if (level != I915_CACHE_NONE) | |
176 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
177 | ||
178 | return pte; | |
179 | } | |
180 | ||
80a74f7f | 181 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 182 | enum i915_cache_level level, |
24f3a8cf | 183 | bool valid, u32 unused) |
9119708c | 184 | { |
b35b380e | 185 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 186 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
187 | |
188 | if (level != I915_CACHE_NONE) | |
87a6b688 | 189 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
190 | |
191 | return pte; | |
192 | } | |
193 | ||
4d15c145 | 194 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 195 | enum i915_cache_level level, |
24f3a8cf | 196 | bool valid, u32 unused) |
4d15c145 | 197 | { |
b35b380e | 198 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
199 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
200 | ||
651d794f CW |
201 | switch (level) { |
202 | case I915_CACHE_NONE: | |
203 | break; | |
204 | case I915_CACHE_WT: | |
c51e9701 | 205 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
206 | break; |
207 | default: | |
c51e9701 | 208 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
209 | break; |
210 | } | |
4d15c145 BW |
211 | |
212 | return pte; | |
213 | } | |
214 | ||
94e409c1 | 215 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 216 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 217 | uint64_t val) |
94e409c1 BW |
218 | { |
219 | int ret; | |
220 | ||
221 | BUG_ON(entry >= 4); | |
222 | ||
223 | ret = intel_ring_begin(ring, 6); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
227 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
228 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
229 | intel_ring_emit(ring, (u32)(val >> 32)); | |
230 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
231 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
232 | intel_ring_emit(ring, (u32)(val)); | |
233 | intel_ring_advance(ring); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
eeb9488e | 238 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 239 | struct intel_engine_cs *ring) |
94e409c1 | 240 | { |
eeb9488e | 241 | int i, ret; |
94e409c1 BW |
242 | |
243 | /* bit of a hack to find the actual last used pd */ | |
244 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
245 | ||
94e409c1 BW |
246 | for (i = used_pd - 1; i >= 0; i--) { |
247 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
6689c167 | 248 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
249 | if (ret) |
250 | return ret; | |
94e409c1 | 251 | } |
d595bd4b | 252 | |
eeb9488e | 253 | return 0; |
94e409c1 BW |
254 | } |
255 | ||
459108b8 | 256 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
257 | uint64_t start, |
258 | uint64_t length, | |
459108b8 BW |
259 | bool use_scratch) |
260 | { | |
261 | struct i915_hw_ppgtt *ppgtt = | |
262 | container_of(vm, struct i915_hw_ppgtt, base); | |
263 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
264 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
265 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
266 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 267 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
268 | unsigned last_pte, i; |
269 | ||
270 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
271 | I915_CACHE_LLC, use_scratch); | |
272 | ||
273 | while (num_entries) { | |
7ad47cf2 | 274 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 275 | |
7ad47cf2 | 276 | last_pte = pte + num_entries; |
459108b8 BW |
277 | if (last_pte > GEN8_PTES_PER_PAGE) |
278 | last_pte = GEN8_PTES_PER_PAGE; | |
279 | ||
280 | pt_vaddr = kmap_atomic(page_table); | |
281 | ||
7ad47cf2 | 282 | for (i = pte; i < last_pte; i++) { |
459108b8 | 283 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
284 | num_entries--; |
285 | } | |
459108b8 | 286 | |
fd1ab8f4 RB |
287 | if (!HAS_LLC(ppgtt->base.dev)) |
288 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
289 | kunmap_atomic(pt_vaddr); |
290 | ||
7ad47cf2 BW |
291 | pte = 0; |
292 | if (++pde == GEN8_PDES_PER_PAGE) { | |
293 | pdpe++; | |
294 | pde = 0; | |
295 | } | |
459108b8 BW |
296 | } |
297 | } | |
298 | ||
9df15b49 BW |
299 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
300 | struct sg_table *pages, | |
782f1495 | 301 | uint64_t start, |
24f3a8cf | 302 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
303 | { |
304 | struct i915_hw_ppgtt *ppgtt = | |
305 | container_of(vm, struct i915_hw_ppgtt, base); | |
306 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
307 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
308 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
309 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
310 | struct sg_page_iter sg_iter; |
311 | ||
6f1cc993 | 312 | pt_vaddr = NULL; |
7ad47cf2 | 313 | |
9df15b49 | 314 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
315 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
316 | break; | |
317 | ||
6f1cc993 | 318 | if (pt_vaddr == NULL) |
7ad47cf2 | 319 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 320 | |
7ad47cf2 | 321 | pt_vaddr[pte] = |
6f1cc993 CW |
322 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
323 | cache_level, true); | |
7ad47cf2 | 324 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
325 | if (!HAS_LLC(ppgtt->base.dev)) |
326 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 327 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 328 | pt_vaddr = NULL; |
7ad47cf2 BW |
329 | if (++pde == GEN8_PDES_PER_PAGE) { |
330 | pdpe++; | |
331 | pde = 0; | |
332 | } | |
333 | pte = 0; | |
9df15b49 BW |
334 | } |
335 | } | |
fd1ab8f4 RB |
336 | if (pt_vaddr) { |
337 | if (!HAS_LLC(ppgtt->base.dev)) | |
338 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 339 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 340 | } |
9df15b49 BW |
341 | } |
342 | ||
7ad47cf2 BW |
343 | static void gen8_free_page_tables(struct page **pt_pages) |
344 | { | |
345 | int i; | |
346 | ||
347 | if (pt_pages == NULL) | |
348 | return; | |
349 | ||
350 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
351 | if (pt_pages[i]) | |
352 | __free_pages(pt_pages[i], 0); | |
353 | } | |
354 | ||
355 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
356 | { |
357 | int i; | |
358 | ||
7ad47cf2 BW |
359 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
360 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
361 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 362 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 363 | } |
b45a6715 | 364 | |
b45a6715 BW |
365 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
366 | } | |
367 | ||
368 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
369 | { | |
f3a964b9 | 370 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
371 | int i, j; |
372 | ||
373 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
374 | /* TODO: In the future we'll support sparse mappings, so this | |
375 | * will have to change. */ | |
376 | if (!ppgtt->pd_dma_addr[i]) | |
377 | continue; | |
378 | ||
f3a964b9 BW |
379 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
380 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
381 | |
382 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
383 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
384 | if (addr) | |
f3a964b9 BW |
385 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
386 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
387 | } |
388 | } | |
389 | } | |
390 | ||
37aca44a BW |
391 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
392 | { | |
393 | struct i915_hw_ppgtt *ppgtt = | |
394 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 395 | |
b45a6715 BW |
396 | gen8_ppgtt_unmap_pages(ppgtt); |
397 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
398 | } |
399 | ||
7ad47cf2 BW |
400 | static struct page **__gen8_alloc_page_tables(void) |
401 | { | |
402 | struct page **pt_pages; | |
403 | int i; | |
404 | ||
405 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
406 | if (!pt_pages) | |
407 | return ERR_PTR(-ENOMEM); | |
408 | ||
409 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
410 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
411 | if (!pt_pages[i]) | |
412 | goto bail; | |
413 | } | |
414 | ||
415 | return pt_pages; | |
416 | ||
417 | bail: | |
418 | gen8_free_page_tables(pt_pages); | |
419 | kfree(pt_pages); | |
420 | return ERR_PTR(-ENOMEM); | |
421 | } | |
422 | ||
bf2b4ed2 BW |
423 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
424 | const int max_pdp) | |
425 | { | |
7ad47cf2 | 426 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 427 | int i, ret; |
bf2b4ed2 | 428 | |
7ad47cf2 BW |
429 | for (i = 0; i < max_pdp; i++) { |
430 | pt_pages[i] = __gen8_alloc_page_tables(); | |
431 | if (IS_ERR(pt_pages[i])) { | |
432 | ret = PTR_ERR(pt_pages[i]); | |
433 | goto unwind_out; | |
434 | } | |
435 | } | |
436 | ||
437 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
438 | * "atomic" - for cleanup purposes. | |
439 | */ | |
440 | for (i = 0; i < max_pdp; i++) | |
441 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 442 | |
bf2b4ed2 | 443 | return 0; |
7ad47cf2 BW |
444 | |
445 | unwind_out: | |
446 | while (i--) { | |
447 | gen8_free_page_tables(pt_pages[i]); | |
448 | kfree(pt_pages[i]); | |
449 | } | |
450 | ||
451 | return ret; | |
bf2b4ed2 BW |
452 | } |
453 | ||
454 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
455 | { | |
456 | int i; | |
457 | ||
458 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
459 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
460 | sizeof(dma_addr_t), | |
461 | GFP_KERNEL); | |
462 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
463 | return -ENOMEM; | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
470 | const int max_pdp) | |
471 | { | |
472 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
473 | if (!ppgtt->pd_pages) | |
474 | return -ENOMEM; | |
475 | ||
476 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
477 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
483 | const int max_pdp) | |
484 | { | |
485 | int ret; | |
486 | ||
487 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
488 | if (ret) | |
489 | return ret; | |
490 | ||
491 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
492 | if (ret) { | |
493 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
494 | return ret; | |
495 | } | |
496 | ||
497 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
498 | ||
499 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
500 | if (ret) | |
501 | gen8_ppgtt_free(ppgtt); | |
502 | ||
503 | return ret; | |
504 | } | |
505 | ||
506 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
507 | const int pd) | |
508 | { | |
509 | dma_addr_t pd_addr; | |
510 | int ret; | |
511 | ||
512 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
513 | &ppgtt->pd_pages[pd], 0, | |
514 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
515 | ||
516 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
517 | if (ret) | |
518 | return ret; | |
519 | ||
520 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
526 | const int pd, | |
527 | const int pt) | |
528 | { | |
529 | dma_addr_t pt_addr; | |
530 | struct page *p; | |
531 | int ret; | |
532 | ||
7ad47cf2 | 533 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
534 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
535 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
536 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
537 | if (ret) | |
538 | return ret; | |
539 | ||
540 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
37aca44a | 545 | /** |
f3a964b9 BW |
546 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
547 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
548 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
549 | * space. | |
37aca44a | 550 | * |
f3a964b9 BW |
551 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
552 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 553 | * TODO: Do something with the size parameter |
f3a964b9 | 554 | */ |
37aca44a BW |
555 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
556 | { | |
37aca44a | 557 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 558 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 559 | int i, j, ret; |
37aca44a BW |
560 | |
561 | if (size % (1<<30)) | |
562 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
563 | ||
bf2b4ed2 BW |
564 | /* 1. Do all our allocations for page directories and page tables. */ |
565 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
566 | if (ret) | |
567 | return ret; | |
f3a964b9 | 568 | |
37aca44a | 569 | /* |
bf2b4ed2 | 570 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
571 | */ |
572 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 573 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
574 | if (ret) |
575 | goto bail; | |
37aca44a | 576 | |
37aca44a | 577 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 578 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
579 | if (ret) |
580 | goto bail; | |
37aca44a BW |
581 | } |
582 | } | |
583 | ||
f3a964b9 BW |
584 | /* |
585 | * 3. Map all the page directory entires to point to the page tables | |
586 | * we've allocated. | |
587 | * | |
588 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 589 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
590 | * will never need to touch the PDEs again. |
591 | */ | |
b1fe6673 BW |
592 | for (i = 0; i < max_pdp; i++) { |
593 | gen8_ppgtt_pde_t *pd_vaddr; | |
594 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
595 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
596 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
597 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
598 | I915_CACHE_LLC); | |
599 | } | |
fd1ab8f4 RB |
600 | if (!HAS_LLC(ppgtt->base.dev)) |
601 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
602 | kunmap_atomic(pd_vaddr); |
603 | } | |
604 | ||
f3a964b9 BW |
605 | ppgtt->switch_mm = gen8_mm_switch; |
606 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
607 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
608 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
609 | ppgtt->base.start = 0; | |
5abbcca3 | 610 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 611 | |
5abbcca3 | 612 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 613 | |
37aca44a BW |
614 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
615 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
616 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
617 | ppgtt->num_pd_entries, |
618 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 619 | return 0; |
37aca44a | 620 | |
f3a964b9 BW |
621 | bail: |
622 | gen8_ppgtt_unmap_pages(ppgtt); | |
623 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
624 | return ret; |
625 | } | |
626 | ||
87d60b63 BW |
627 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
628 | { | |
629 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
630 | struct i915_address_space *vm = &ppgtt->base; | |
631 | gen6_gtt_pte_t __iomem *pd_addr; | |
632 | gen6_gtt_pte_t scratch_pte; | |
633 | uint32_t pd_entry; | |
634 | int pte, pde; | |
635 | ||
24f3a8cf | 636 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
637 | |
638 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
639 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
640 | ||
641 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
642 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
643 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
644 | u32 expected; | |
645 | gen6_gtt_pte_t *pt_vaddr; | |
646 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
647 | pd_entry = readl(pd_addr + pde); | |
648 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
649 | ||
650 | if (pd_entry != expected) | |
651 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
652 | pde, | |
653 | pd_entry, | |
654 | expected); | |
655 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
656 | ||
657 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
658 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
659 | unsigned long va = | |
660 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
661 | (pte * PAGE_SIZE); | |
662 | int i; | |
663 | bool found = false; | |
664 | for (i = 0; i < 4; i++) | |
665 | if (pt_vaddr[pte + i] != scratch_pte) | |
666 | found = true; | |
667 | if (!found) | |
668 | continue; | |
669 | ||
670 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
671 | for (i = 0; i < 4; i++) { | |
672 | if (pt_vaddr[pte + i] != scratch_pte) | |
673 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
674 | else | |
675 | seq_puts(m, " SCRATCH "); | |
676 | } | |
677 | seq_puts(m, "\n"); | |
678 | } | |
679 | kunmap_atomic(pt_vaddr); | |
680 | } | |
681 | } | |
682 | ||
3e302542 | 683 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 684 | { |
853ba5d2 | 685 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
686 | gen6_gtt_pte_t __iomem *pd_addr; |
687 | uint32_t pd_entry; | |
688 | int i; | |
689 | ||
0a732870 | 690 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
691 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
692 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
693 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
694 | dma_addr_t pt_addr; | |
695 | ||
696 | pt_addr = ppgtt->pt_dma_addr[i]; | |
697 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
698 | pd_entry |= GEN6_PDE_VALID; | |
699 | ||
700 | writel(pd_entry, pd_addr + i); | |
701 | } | |
702 | readl(pd_addr); | |
3e302542 BW |
703 | } |
704 | ||
b4a74e3a | 705 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 706 | { |
b4a74e3a BW |
707 | BUG_ON(ppgtt->pd_offset & 0x3f); |
708 | ||
709 | return (ppgtt->pd_offset / 64) << 16; | |
710 | } | |
711 | ||
90252e5c | 712 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 713 | struct intel_engine_cs *ring) |
90252e5c | 714 | { |
90252e5c BW |
715 | int ret; |
716 | ||
90252e5c BW |
717 | /* NB: TLBs must be flushed and invalidated before a switch */ |
718 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
719 | if (ret) | |
720 | return ret; | |
721 | ||
722 | ret = intel_ring_begin(ring, 6); | |
723 | if (ret) | |
724 | return ret; | |
725 | ||
726 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
727 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
728 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
729 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
730 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
731 | intel_ring_emit(ring, MI_NOOP); | |
732 | intel_ring_advance(ring); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
48a10389 | 737 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 738 | struct intel_engine_cs *ring) |
48a10389 | 739 | { |
48a10389 BW |
740 | int ret; |
741 | ||
48a10389 BW |
742 | /* NB: TLBs must be flushed and invalidated before a switch */ |
743 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
744 | if (ret) | |
745 | return ret; | |
746 | ||
747 | ret = intel_ring_begin(ring, 6); | |
748 | if (ret) | |
749 | return ret; | |
750 | ||
751 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
752 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
753 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
754 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
755 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
756 | intel_ring_emit(ring, MI_NOOP); | |
757 | intel_ring_advance(ring); | |
758 | ||
90252e5c BW |
759 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
760 | if (ring->id != RCS) { | |
761 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
762 | if (ret) | |
763 | return ret; | |
764 | } | |
765 | ||
48a10389 BW |
766 | return 0; |
767 | } | |
768 | ||
eeb9488e | 769 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 770 | struct intel_engine_cs *ring) |
eeb9488e BW |
771 | { |
772 | struct drm_device *dev = ppgtt->base.dev; | |
773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
774 | ||
48a10389 | 775 | |
eeb9488e BW |
776 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
777 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
778 | ||
779 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
82460d97 | 784 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 785 | { |
eeb9488e | 786 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 787 | struct intel_engine_cs *ring; |
82460d97 | 788 | int j; |
3e302542 | 789 | |
eeb9488e BW |
790 | for_each_ring(ring, dev_priv, j) { |
791 | I915_WRITE(RING_MODE_GEN7(ring), | |
792 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 793 | } |
eeb9488e | 794 | } |
6197349b | 795 | |
82460d97 | 796 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 797 | { |
50227e1c | 798 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 799 | struct intel_engine_cs *ring; |
b4a74e3a | 800 | uint32_t ecochk, ecobits; |
3e302542 | 801 | int i; |
6197349b | 802 | |
b4a74e3a BW |
803 | ecobits = I915_READ(GAC_ECO_BITS); |
804 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 805 | |
b4a74e3a BW |
806 | ecochk = I915_READ(GAM_ECOCHK); |
807 | if (IS_HASWELL(dev)) { | |
808 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
809 | } else { | |
810 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
811 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
812 | } | |
813 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 814 | |
b4a74e3a | 815 | for_each_ring(ring, dev_priv, i) { |
6197349b | 816 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
817 | I915_WRITE(RING_MODE_GEN7(ring), |
818 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 819 | } |
b4a74e3a | 820 | } |
6197349b | 821 | |
82460d97 | 822 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 823 | { |
50227e1c | 824 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 825 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 826 | |
b4a74e3a BW |
827 | ecobits = I915_READ(GAC_ECO_BITS); |
828 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
829 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 830 | |
b4a74e3a BW |
831 | gab_ctl = I915_READ(GAB_CTL); |
832 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
833 | ||
834 | ecochk = I915_READ(GAM_ECOCHK); | |
835 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
836 | ||
837 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
838 | } |
839 | ||
1d2a314c | 840 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 841 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
842 | uint64_t start, |
843 | uint64_t length, | |
828c7908 | 844 | bool use_scratch) |
1d2a314c | 845 | { |
853ba5d2 BW |
846 | struct i915_hw_ppgtt *ppgtt = |
847 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 848 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
849 | unsigned first_entry = start >> PAGE_SHIFT; |
850 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 851 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
852 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
853 | unsigned last_pte, i; | |
1d2a314c | 854 | |
24f3a8cf | 855 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 856 | |
7bddb01f DV |
857 | while (num_entries) { |
858 | last_pte = first_pte + num_entries; | |
859 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
860 | last_pte = I915_PPGTT_PT_ENTRIES; | |
861 | ||
a15326a5 | 862 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 863 | |
7bddb01f DV |
864 | for (i = first_pte; i < last_pte; i++) |
865 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
866 | |
867 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 868 | |
7bddb01f DV |
869 | num_entries -= last_pte - first_pte; |
870 | first_pte = 0; | |
a15326a5 | 871 | act_pt++; |
7bddb01f | 872 | } |
1d2a314c DV |
873 | } |
874 | ||
853ba5d2 | 875 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 876 | struct sg_table *pages, |
782f1495 | 877 | uint64_t start, |
24f3a8cf | 878 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 879 | { |
853ba5d2 BW |
880 | struct i915_hw_ppgtt *ppgtt = |
881 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 882 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 883 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 884 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
885 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
886 | struct sg_page_iter sg_iter; | |
887 | ||
cc79714f | 888 | pt_vaddr = NULL; |
6e995e23 | 889 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
890 | if (pt_vaddr == NULL) |
891 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 892 | |
cc79714f CW |
893 | pt_vaddr[act_pte] = |
894 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
895 | cache_level, true, flags); |
896 | ||
6e995e23 ID |
897 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
898 | kunmap_atomic(pt_vaddr); | |
cc79714f | 899 | pt_vaddr = NULL; |
a15326a5 | 900 | act_pt++; |
6e995e23 | 901 | act_pte = 0; |
def886c3 | 902 | } |
def886c3 | 903 | } |
cc79714f CW |
904 | if (pt_vaddr) |
905 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
906 | } |
907 | ||
a00d825d | 908 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 909 | { |
3440d265 DV |
910 | int i; |
911 | ||
912 | if (ppgtt->pt_dma_addr) { | |
913 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 914 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
915 | ppgtt->pt_dma_addr[i], |
916 | 4096, PCI_DMA_BIDIRECTIONAL); | |
917 | } | |
a00d825d BW |
918 | } |
919 | ||
920 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
921 | { | |
922 | int i; | |
3440d265 DV |
923 | |
924 | kfree(ppgtt->pt_dma_addr); | |
925 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
926 | __free_page(ppgtt->pt_pages[i]); | |
927 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
928 | } |
929 | ||
a00d825d BW |
930 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
931 | { | |
932 | struct i915_hw_ppgtt *ppgtt = | |
933 | container_of(vm, struct i915_hw_ppgtt, base); | |
934 | ||
a00d825d BW |
935 | drm_mm_remove_node(&ppgtt->node); |
936 | ||
937 | gen6_ppgtt_unmap_pages(ppgtt); | |
938 | gen6_ppgtt_free(ppgtt); | |
939 | } | |
940 | ||
b146520f | 941 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 942 | { |
853ba5d2 | 943 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 944 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 945 | bool retried = false; |
b146520f | 946 | int ret; |
1d2a314c | 947 | |
c8d4c0d6 BW |
948 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
949 | * allocator works in address space sizes, so it's multiplied by page | |
950 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
951 | */ | |
952 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 953 | alloc: |
c8d4c0d6 BW |
954 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
955 | &ppgtt->node, GEN6_PD_SIZE, | |
956 | GEN6_PD_ALIGN, 0, | |
957 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 958 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
959 | if (ret == -ENOSPC && !retried) { |
960 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
961 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
962 | I915_CACHE_NONE, |
963 | 0, dev_priv->gtt.base.total, | |
964 | 0); | |
e3cc1995 BW |
965 | if (ret) |
966 | return ret; | |
967 | ||
968 | retried = true; | |
969 | goto alloc; | |
970 | } | |
c8d4c0d6 BW |
971 | |
972 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
973 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 974 | |
6670a5a5 | 975 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
976 | return ret; |
977 | } | |
978 | ||
979 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
980 | { | |
981 | int i; | |
982 | ||
a1e22653 | 983 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 984 | GFP_KERNEL); |
b146520f BW |
985 | |
986 | if (!ppgtt->pt_pages) | |
3440d265 | 987 | return -ENOMEM; |
1d2a314c DV |
988 | |
989 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
990 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
991 | if (!ppgtt->pt_pages[i]) { |
992 | gen6_ppgtt_free(ppgtt); | |
993 | return -ENOMEM; | |
994 | } | |
995 | } | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1001 | { | |
1002 | int ret; | |
1003 | ||
1004 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1005 | if (ret) | |
1006 | return ret; | |
1007 | ||
1008 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1009 | if (ret) { | |
1010 | drm_mm_remove_node(&ppgtt->node); | |
1011 | return ret; | |
1d2a314c DV |
1012 | } |
1013 | ||
a1e22653 | 1014 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1015 | GFP_KERNEL); |
b146520f BW |
1016 | if (!ppgtt->pt_dma_addr) { |
1017 | drm_mm_remove_node(&ppgtt->node); | |
1018 | gen6_ppgtt_free(ppgtt); | |
1019 | return -ENOMEM; | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1026 | { | |
1027 | struct drm_device *dev = ppgtt->base.dev; | |
1028 | int i; | |
1d2a314c | 1029 | |
8d2e6308 BW |
1030 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1031 | dma_addr_t pt_addr; | |
211c568b | 1032 | |
8d2e6308 BW |
1033 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1034 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1035 | |
8d2e6308 | 1036 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1037 | gen6_ppgtt_unmap_pages(ppgtt); |
1038 | return -EIO; | |
211c568b | 1039 | } |
b146520f | 1040 | |
8d2e6308 | 1041 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1042 | } |
1d2a314c | 1043 | |
b146520f BW |
1044 | return 0; |
1045 | } | |
1046 | ||
1047 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1048 | { | |
1049 | struct drm_device *dev = ppgtt->base.dev; | |
1050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1051 | int ret; | |
1052 | ||
1053 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1054 | if (IS_GEN6(dev)) { | |
b146520f BW |
1055 | ppgtt->switch_mm = gen6_mm_switch; |
1056 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1057 | ppgtt->switch_mm = hsw_mm_switch; |
1058 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1059 | ppgtt->switch_mm = gen7_mm_switch; |
1060 | } else | |
1061 | BUG(); | |
1062 | ||
1063 | ret = gen6_ppgtt_alloc(ppgtt); | |
1064 | if (ret) | |
1065 | return ret; | |
1066 | ||
1067 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1068 | if (ret) { | |
1069 | gen6_ppgtt_free(ppgtt); | |
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1074 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1075 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1076 | ppgtt->base.start = 0; |
5a6c93fe | 1077 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1078 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1079 | |
c8d4c0d6 BW |
1080 | ppgtt->pd_offset = |
1081 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1082 | |
b146520f | 1083 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1084 | |
b146520f BW |
1085 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1086 | ppgtt->node.size >> 20, | |
1087 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1088 | |
fa76da34 DV |
1089 | gen6_write_pdes(ppgtt); |
1090 | DRM_DEBUG("Adding PPGTT at offset %x\n", | |
1091 | ppgtt->pd_offset << 10); | |
1092 | ||
b146520f | 1093 | return 0; |
3440d265 DV |
1094 | } |
1095 | ||
fa76da34 | 1096 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1097 | { |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1099 | |
853ba5d2 | 1100 | ppgtt->base.dev = dev; |
8407bb91 | 1101 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1102 | |
3ed124b2 | 1103 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1104 | return gen6_ppgtt_init(ppgtt); |
3fdcf80f | 1105 | else if (IS_GEN8(dev) || IS_GEN9(dev)) |
fa76da34 | 1106 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1107 | else |
1108 | BUG(); | |
fa76da34 DV |
1109 | } |
1110 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1111 | { | |
1112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1113 | int ret = 0; | |
3ed124b2 | 1114 | |
fa76da34 DV |
1115 | ret = __hw_ppgtt_init(dev, ppgtt); |
1116 | if (ret == 0) { | |
c7c48dfd | 1117 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1118 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1119 | ppgtt->base.total); | |
7e0d96bc | 1120 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1121 | } |
1d2a314c DV |
1122 | |
1123 | return ret; | |
1124 | } | |
1125 | ||
82460d97 DV |
1126 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1127 | { | |
1128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1129 | struct intel_engine_cs *ring; | |
1130 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1131 | int i, ret = 0; | |
1132 | ||
671b5013 TD |
1133 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1134 | * and the PDPs are contained within the context itself. We don't | |
1135 | * need to do anything here. */ | |
1136 | if (i915.enable_execlists) | |
1137 | return 0; | |
1138 | ||
82460d97 DV |
1139 | if (!USES_PPGTT(dev)) |
1140 | return 0; | |
1141 | ||
1142 | if (IS_GEN6(dev)) | |
1143 | gen6_ppgtt_enable(dev); | |
1144 | else if (IS_GEN7(dev)) | |
1145 | gen7_ppgtt_enable(dev); | |
1146 | else if (INTEL_INFO(dev)->gen >= 8) | |
1147 | gen8_ppgtt_enable(dev); | |
1148 | else | |
1149 | WARN_ON(1); | |
1150 | ||
1151 | if (ppgtt) { | |
1152 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1153 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1154 | if (ret != 0) |
1155 | return ret; | |
7e0d96bc | 1156 | } |
93bd8649 | 1157 | } |
1d2a314c DV |
1158 | |
1159 | return ret; | |
1160 | } | |
4d884705 DV |
1161 | struct i915_hw_ppgtt * |
1162 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1163 | { | |
1164 | struct i915_hw_ppgtt *ppgtt; | |
1165 | int ret; | |
1166 | ||
1167 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1168 | if (!ppgtt) | |
1169 | return ERR_PTR(-ENOMEM); | |
1170 | ||
1171 | ret = i915_ppgtt_init(dev, ppgtt); | |
1172 | if (ret) { | |
1173 | kfree(ppgtt); | |
1174 | return ERR_PTR(ret); | |
1175 | } | |
1176 | ||
1177 | ppgtt->file_priv = fpriv; | |
1178 | ||
198c974d DCS |
1179 | trace_i915_ppgtt_create(&ppgtt->base); |
1180 | ||
4d884705 DV |
1181 | return ppgtt; |
1182 | } | |
1183 | ||
ee960be7 DV |
1184 | void i915_ppgtt_release(struct kref *kref) |
1185 | { | |
1186 | struct i915_hw_ppgtt *ppgtt = | |
1187 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1188 | ||
198c974d DCS |
1189 | trace_i915_ppgtt_release(&ppgtt->base); |
1190 | ||
ee960be7 DV |
1191 | /* vmas should already be unbound */ |
1192 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1193 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1194 | ||
19dd120c DV |
1195 | list_del(&ppgtt->base.global_link); |
1196 | drm_mm_takedown(&ppgtt->base.mm); | |
1197 | ||
ee960be7 DV |
1198 | ppgtt->base.cleanup(&ppgtt->base); |
1199 | kfree(ppgtt); | |
1200 | } | |
1d2a314c | 1201 | |
7e0d96bc | 1202 | static void |
6f65e29a BW |
1203 | ppgtt_bind_vma(struct i915_vma *vma, |
1204 | enum i915_cache_level cache_level, | |
1205 | u32 flags) | |
1d2a314c | 1206 | { |
24f3a8cf AG |
1207 | /* Currently applicable only to VLV */ |
1208 | if (vma->obj->gt_ro) | |
1209 | flags |= PTE_READ_ONLY; | |
1210 | ||
782f1495 | 1211 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1212 | cache_level, flags); |
1d2a314c DV |
1213 | } |
1214 | ||
7e0d96bc | 1215 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1216 | { |
6f65e29a | 1217 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1218 | vma->node.start, |
1219 | vma->obj->base.size, | |
6f65e29a | 1220 | true); |
7bddb01f DV |
1221 | } |
1222 | ||
a81cc00c BW |
1223 | extern int intel_iommu_gfx_mapped; |
1224 | /* Certain Gen5 chipsets require require idling the GPU before | |
1225 | * unmapping anything from the GTT when VT-d is enabled. | |
1226 | */ | |
1227 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1228 | { | |
1229 | #ifdef CONFIG_INTEL_IOMMU | |
1230 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1231 | * was loaded first. | |
1232 | */ | |
1233 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1234 | return true; | |
1235 | #endif | |
1236 | return false; | |
1237 | } | |
1238 | ||
5c042287 BW |
1239 | static bool do_idling(struct drm_i915_private *dev_priv) |
1240 | { | |
1241 | bool ret = dev_priv->mm.interruptible; | |
1242 | ||
a81cc00c | 1243 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1244 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1245 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1246 | DRM_ERROR("Couldn't idle GPU\n"); |
1247 | /* Wait a bit, in hopes it avoids the hang */ | |
1248 | udelay(10); | |
1249 | } | |
1250 | } | |
1251 | ||
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1256 | { | |
a81cc00c | 1257 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1258 | dev_priv->mm.interruptible = interruptible; |
1259 | } | |
1260 | ||
828c7908 BW |
1261 | void i915_check_and_clear_faults(struct drm_device *dev) |
1262 | { | |
1263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1264 | struct intel_engine_cs *ring; |
828c7908 BW |
1265 | int i; |
1266 | ||
1267 | if (INTEL_INFO(dev)->gen < 6) | |
1268 | return; | |
1269 | ||
1270 | for_each_ring(ring, dev_priv, i) { | |
1271 | u32 fault_reg; | |
1272 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1273 | if (fault_reg & RING_FAULT_VALID) { | |
1274 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1275 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1276 | "\tAddress space: %s\n" |
1277 | "\tSource ID: %d\n" | |
1278 | "\tType: %d\n", | |
1279 | fault_reg & PAGE_MASK, | |
1280 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1281 | RING_FAULT_SRCID(fault_reg), | |
1282 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1283 | I915_WRITE(RING_FAULT_REG(ring), | |
1284 | fault_reg & ~RING_FAULT_VALID); | |
1285 | } | |
1286 | } | |
1287 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1288 | } | |
1289 | ||
91e56499 CW |
1290 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1291 | { | |
1292 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1293 | intel_gtt_chipset_flush(); | |
1294 | } else { | |
1295 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1296 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1297 | } | |
1298 | } | |
1299 | ||
828c7908 BW |
1300 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1301 | { | |
1302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1303 | ||
1304 | /* Don't bother messing with faults pre GEN6 as we have little | |
1305 | * documentation supporting that it's a good idea. | |
1306 | */ | |
1307 | if (INTEL_INFO(dev)->gen < 6) | |
1308 | return; | |
1309 | ||
1310 | i915_check_and_clear_faults(dev); | |
1311 | ||
1312 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1313 | dev_priv->gtt.base.start, |
1314 | dev_priv->gtt.base.total, | |
e568af1c | 1315 | true); |
91e56499 CW |
1316 | |
1317 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1318 | } |
1319 | ||
76aaf220 DV |
1320 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1321 | { | |
1322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1323 | struct drm_i915_gem_object *obj; |
80da2161 | 1324 | struct i915_address_space *vm; |
76aaf220 | 1325 | |
828c7908 BW |
1326 | i915_check_and_clear_faults(dev); |
1327 | ||
bee4a186 | 1328 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1329 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1330 | dev_priv->gtt.base.start, |
1331 | dev_priv->gtt.base.total, | |
828c7908 | 1332 | true); |
bee4a186 | 1333 | |
35c20a60 | 1334 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1335 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1336 | &dev_priv->gtt.base); | |
1337 | if (!vma) | |
1338 | continue; | |
1339 | ||
2c22569b | 1340 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1341 | /* The bind_vma code tries to be smart about tracking mappings. |
1342 | * Unfortunately above, we've just wiped out the mappings | |
1343 | * without telling our object about it. So we need to fake it. | |
1344 | */ | |
aff43766 | 1345 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1346 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
76aaf220 DV |
1347 | } |
1348 | ||
80da2161 | 1349 | |
a2319c08 | 1350 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1351 | if (IS_CHERRYVIEW(dev)) |
1352 | chv_setup_private_ppat(dev_priv); | |
1353 | else | |
1354 | bdw_setup_private_ppat(dev_priv); | |
1355 | ||
80da2161 | 1356 | return; |
a2319c08 | 1357 | } |
80da2161 BW |
1358 | |
1359 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1360 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1361 | if (i915_is_ggtt(vm)) { | |
1362 | if (dev_priv->mm.aliasing_ppgtt) | |
1363 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1364 | continue; | |
1365 | } | |
1366 | ||
1367 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1368 | } |
1369 | ||
91e56499 | 1370 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1371 | } |
7c2e6fdf | 1372 | |
74163907 | 1373 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1374 | { |
9da3da66 | 1375 | if (obj->has_dma_mapping) |
74163907 | 1376 | return 0; |
9da3da66 CW |
1377 | |
1378 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1379 | obj->pages->sgl, obj->pages->nents, | |
1380 | PCI_DMA_BIDIRECTIONAL)) | |
1381 | return -ENOSPC; | |
1382 | ||
1383 | return 0; | |
7c2e6fdf DV |
1384 | } |
1385 | ||
94ec8f61 BW |
1386 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1387 | { | |
1388 | #ifdef writeq | |
1389 | writeq(pte, addr); | |
1390 | #else | |
1391 | iowrite32((u32)pte, addr); | |
1392 | iowrite32(pte >> 32, addr + 4); | |
1393 | #endif | |
1394 | } | |
1395 | ||
1396 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1397 | struct sg_table *st, | |
782f1495 | 1398 | uint64_t start, |
24f3a8cf | 1399 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1400 | { |
1401 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1402 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1403 | gen8_gtt_pte_t __iomem *gtt_entries = |
1404 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1405 | int i = 0; | |
1406 | struct sg_page_iter sg_iter; | |
57007df7 | 1407 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1408 | |
1409 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1410 | addr = sg_dma_address(sg_iter.sg) + | |
1411 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1412 | gen8_set_pte(>t_entries[i], | |
1413 | gen8_pte_encode(addr, level, true)); | |
1414 | i++; | |
1415 | } | |
1416 | ||
1417 | /* | |
1418 | * XXX: This serves as a posting read to make sure that the PTE has | |
1419 | * actually been updated. There is some concern that even though | |
1420 | * registers and PTEs are within the same BAR that they are potentially | |
1421 | * of NUMA access patterns. Therefore, even with the way we assume | |
1422 | * hardware should work, we must keep this posting read for paranoia. | |
1423 | */ | |
1424 | if (i != 0) | |
1425 | WARN_ON(readq(>t_entries[i-1]) | |
1426 | != gen8_pte_encode(addr, level, true)); | |
1427 | ||
94ec8f61 BW |
1428 | /* This next bit makes the above posting read even more important. We |
1429 | * want to flush the TLBs only after we're certain all the PTE updates | |
1430 | * have finished. | |
1431 | */ | |
1432 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1433 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1434 | } |
1435 | ||
e76e9aeb BW |
1436 | /* |
1437 | * Binds an object into the global gtt with the specified cache level. The object | |
1438 | * will be accessible to the GPU via commands whose operands reference offsets | |
1439 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1440 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1441 | */ | |
853ba5d2 | 1442 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1443 | struct sg_table *st, |
782f1495 | 1444 | uint64_t start, |
24f3a8cf | 1445 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1446 | { |
853ba5d2 | 1447 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1448 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1449 | gen6_gtt_pte_t __iomem *gtt_entries = |
1450 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1451 | int i = 0; |
1452 | struct sg_page_iter sg_iter; | |
57007df7 | 1453 | dma_addr_t addr = 0; |
e76e9aeb | 1454 | |
6e995e23 | 1455 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1456 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1457 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1458 | i++; |
e76e9aeb BW |
1459 | } |
1460 | ||
e76e9aeb BW |
1461 | /* XXX: This serves as a posting read to make sure that the PTE has |
1462 | * actually been updated. There is some concern that even though | |
1463 | * registers and PTEs are within the same BAR that they are potentially | |
1464 | * of NUMA access patterns. Therefore, even with the way we assume | |
1465 | * hardware should work, we must keep this posting read for paranoia. | |
1466 | */ | |
57007df7 PM |
1467 | if (i != 0) { |
1468 | unsigned long gtt = readl(>t_entries[i-1]); | |
1469 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1470 | } | |
0f9b91c7 BW |
1471 | |
1472 | /* This next bit makes the above posting read even more important. We | |
1473 | * want to flush the TLBs only after we're certain all the PTE updates | |
1474 | * have finished. | |
1475 | */ | |
1476 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1477 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1478 | } |
1479 | ||
94ec8f61 | 1480 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1481 | uint64_t start, |
1482 | uint64_t length, | |
94ec8f61 BW |
1483 | bool use_scratch) |
1484 | { | |
1485 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1486 | unsigned first_entry = start >> PAGE_SHIFT; |
1487 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1488 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1489 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1490 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1491 | int i; | |
1492 | ||
1493 | if (WARN(num_entries > max_entries, | |
1494 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1495 | first_entry, num_entries, max_entries)) | |
1496 | num_entries = max_entries; | |
1497 | ||
1498 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1499 | I915_CACHE_LLC, | |
1500 | use_scratch); | |
1501 | for (i = 0; i < num_entries; i++) | |
1502 | gen8_set_pte(>t_base[i], scratch_pte); | |
1503 | readl(gtt_base); | |
1504 | } | |
1505 | ||
853ba5d2 | 1506 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1507 | uint64_t start, |
1508 | uint64_t length, | |
828c7908 | 1509 | bool use_scratch) |
7faf1ab2 | 1510 | { |
853ba5d2 | 1511 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1512 | unsigned first_entry = start >> PAGE_SHIFT; |
1513 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1514 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1515 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1516 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1517 | int i; |
1518 | ||
1519 | if (WARN(num_entries > max_entries, | |
1520 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1521 | first_entry, num_entries, max_entries)) | |
1522 | num_entries = max_entries; | |
1523 | ||
24f3a8cf | 1524 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1525 | |
7faf1ab2 DV |
1526 | for (i = 0; i < num_entries; i++) |
1527 | iowrite32(scratch_pte, >t_base[i]); | |
1528 | readl(gtt_base); | |
1529 | } | |
1530 | ||
6f65e29a BW |
1531 | |
1532 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1533 | enum i915_cache_level cache_level, | |
1534 | u32 unused) | |
7faf1ab2 | 1535 | { |
6f65e29a | 1536 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1537 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1538 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1539 | ||
6f65e29a BW |
1540 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1541 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
aff43766 | 1542 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1543 | } |
1544 | ||
853ba5d2 | 1545 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1546 | uint64_t start, |
1547 | uint64_t length, | |
828c7908 | 1548 | bool unused) |
7faf1ab2 | 1549 | { |
782f1495 BW |
1550 | unsigned first_entry = start >> PAGE_SHIFT; |
1551 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1552 | intel_gtt_clear_range(first_entry, num_entries); |
1553 | } | |
1554 | ||
6f65e29a BW |
1555 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1556 | { | |
1557 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1558 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1559 | |
6f65e29a | 1560 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1561 | vma->bound = 0; |
6f65e29a BW |
1562 | intel_gtt_clear_range(first, size); |
1563 | } | |
7faf1ab2 | 1564 | |
6f65e29a BW |
1565 | static void ggtt_bind_vma(struct i915_vma *vma, |
1566 | enum i915_cache_level cache_level, | |
1567 | u32 flags) | |
d5bd1449 | 1568 | { |
6f65e29a | 1569 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1570 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1571 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1572 | |
24f3a8cf AG |
1573 | /* Currently applicable only to VLV */ |
1574 | if (obj->gt_ro) | |
1575 | flags |= PTE_READ_ONLY; | |
1576 | ||
6f65e29a BW |
1577 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1578 | * or we have a global mapping already but the cacheability flags have | |
1579 | * changed, set the global PTEs. | |
1580 | * | |
1581 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1582 | * instead if none of the above hold true. | |
1583 | * | |
1584 | * NB: A global mapping should only be needed for special regions like | |
1585 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1586 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1587 | */ | |
1588 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1589 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1590 | (cache_level != obj->cache_level)) { |
782f1495 BW |
1591 | vma->vm->insert_entries(vma->vm, obj->pages, |
1592 | vma->node.start, | |
24f3a8cf | 1593 | cache_level, flags); |
aff43766 | 1594 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1595 | } |
1596 | } | |
d5bd1449 | 1597 | |
6f65e29a | 1598 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1599 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1600 | (cache_level != obj->cache_level))) { |
1601 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1602 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1603 | vma->obj->pages, |
1604 | vma->node.start, | |
24f3a8cf | 1605 | cache_level, flags); |
aff43766 | 1606 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1607 | } |
d5bd1449 CW |
1608 | } |
1609 | ||
6f65e29a | 1610 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1611 | { |
6f65e29a | 1612 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1613 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1614 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1615 | |
aff43766 | 1616 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1617 | vma->vm->clear_range(vma->vm, |
1618 | vma->node.start, | |
1619 | obj->base.size, | |
6f65e29a | 1620 | true); |
aff43766 | 1621 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1622 | } |
74898d7e | 1623 | |
aff43766 | 1624 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1625 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1626 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1627 | vma->node.start, |
1628 | obj->base.size, | |
6f65e29a | 1629 | true); |
aff43766 | 1630 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1631 | } |
74163907 DV |
1632 | } |
1633 | ||
1634 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1635 | { |
5c042287 BW |
1636 | struct drm_device *dev = obj->base.dev; |
1637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1638 | bool interruptible; | |
1639 | ||
1640 | interruptible = do_idling(dev_priv); | |
1641 | ||
9da3da66 CW |
1642 | if (!obj->has_dma_mapping) |
1643 | dma_unmap_sg(&dev->pdev->dev, | |
1644 | obj->pages->sgl, obj->pages->nents, | |
1645 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1646 | |
1647 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1648 | } |
644ec02b | 1649 | |
42d6ab48 CW |
1650 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1651 | unsigned long color, | |
1652 | unsigned long *start, | |
1653 | unsigned long *end) | |
1654 | { | |
1655 | if (node->color != color) | |
1656 | *start += 4096; | |
1657 | ||
1658 | if (!list_empty(&node->node_list)) { | |
1659 | node = list_entry(node->node_list.next, | |
1660 | struct drm_mm_node, | |
1661 | node_list); | |
1662 | if (node->allocated && node->color != color) | |
1663 | *end -= 4096; | |
1664 | } | |
1665 | } | |
fbe5d36e | 1666 | |
f548c0e9 DV |
1667 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1668 | unsigned long start, | |
1669 | unsigned long mappable_end, | |
1670 | unsigned long end) | |
644ec02b | 1671 | { |
e78891ca BW |
1672 | /* Let GEM Manage all of the aperture. |
1673 | * | |
1674 | * However, leave one page at the end still bound to the scratch page. | |
1675 | * There are a number of places where the hardware apparently prefetches | |
1676 | * past the end of the object, and we've seen multiple hangs with the | |
1677 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1678 | * aperture. One page should be enough to keep any prefetching inside | |
1679 | * of the aperture. | |
1680 | */ | |
40d74980 BW |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; |
1682 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1683 | struct drm_mm_node *entry; |
1684 | struct drm_i915_gem_object *obj; | |
1685 | unsigned long hole_start, hole_end; | |
fa76da34 | 1686 | int ret; |
644ec02b | 1687 | |
35451cb6 BW |
1688 | BUG_ON(mappable_end > end); |
1689 | ||
ed2f3452 | 1690 | /* Subtract the guard page ... */ |
40d74980 | 1691 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1692 | if (!HAS_LLC(dev)) |
93bd8649 | 1693 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1694 | |
ed2f3452 | 1695 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1696 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1697 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1698 | |
edd41a87 | 1699 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1700 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1701 | ||
1702 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1703 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1704 | if (ret) { |
1705 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1706 | return ret; | |
1707 | } | |
aff43766 | 1708 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
1709 | } |
1710 | ||
853ba5d2 BW |
1711 | dev_priv->gtt.base.start = start; |
1712 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1713 | |
ed2f3452 | 1714 | /* Clear any non-preallocated blocks */ |
40d74980 | 1715 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1716 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1717 | hole_start, hole_end); | |
782f1495 BW |
1718 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1719 | hole_end - hole_start, true); | |
ed2f3452 CW |
1720 | } |
1721 | ||
1722 | /* And finally clear the reserved guard page */ | |
782f1495 | 1723 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1724 | |
fa76da34 DV |
1725 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1726 | struct i915_hw_ppgtt *ppgtt; | |
1727 | ||
1728 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1729 | if (!ppgtt) | |
1730 | return -ENOMEM; | |
1731 | ||
1732 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1733 | if (ret != 0) | |
1734 | return ret; | |
1735 | ||
1736 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1737 | } | |
1738 | ||
6c5566a8 | 1739 | return 0; |
e76e9aeb BW |
1740 | } |
1741 | ||
d7e5008f BW |
1742 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1743 | { | |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1746 | |
853ba5d2 | 1747 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1748 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1749 | |
e78891ca | 1750 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1751 | } |
1752 | ||
90d0a0e8 DV |
1753 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1754 | { | |
1755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1756 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
1757 | ||
70e32544 DV |
1758 | if (dev_priv->mm.aliasing_ppgtt) { |
1759 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1760 | ||
1761 | ppgtt->base.cleanup(&ppgtt->base); | |
1762 | } | |
1763 | ||
90d0a0e8 DV |
1764 | if (drm_mm_initialized(&vm->mm)) { |
1765 | drm_mm_takedown(&vm->mm); | |
1766 | list_del(&vm->global_link); | |
1767 | } | |
1768 | ||
1769 | vm->cleanup(vm); | |
1770 | } | |
70e32544 | 1771 | |
e76e9aeb BW |
1772 | static int setup_scratch_page(struct drm_device *dev) |
1773 | { | |
1774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1775 | struct page *page; | |
1776 | dma_addr_t dma_addr; | |
1777 | ||
1778 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1779 | if (page == NULL) | |
1780 | return -ENOMEM; | |
e76e9aeb BW |
1781 | set_pages_uc(page, 1); |
1782 | ||
1783 | #ifdef CONFIG_INTEL_IOMMU | |
1784 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1785 | PCI_DMA_BIDIRECTIONAL); | |
1786 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1787 | return -EINVAL; | |
1788 | #else | |
1789 | dma_addr = page_to_phys(page); | |
1790 | #endif | |
853ba5d2 BW |
1791 | dev_priv->gtt.base.scratch.page = page; |
1792 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1793 | |
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | static void teardown_scratch_page(struct drm_device *dev) | |
1798 | { | |
1799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1800 | struct page *page = dev_priv->gtt.base.scratch.page; |
1801 | ||
1802 | set_pages_wb(page, 1); | |
1803 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1804 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 1805 | __free_page(page); |
e76e9aeb BW |
1806 | } |
1807 | ||
1808 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1809 | { | |
1810 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1811 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1812 | return snb_gmch_ctl << 20; | |
1813 | } | |
1814 | ||
9459d252 BW |
1815 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1816 | { | |
1817 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1818 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1819 | if (bdw_gmch_ctl) | |
1820 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1821 | |
1822 | #ifdef CONFIG_X86_32 | |
1823 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1824 | if (bdw_gmch_ctl > 4) | |
1825 | bdw_gmch_ctl = 4; | |
1826 | #endif | |
1827 | ||
9459d252 BW |
1828 | return bdw_gmch_ctl << 20; |
1829 | } | |
1830 | ||
d7f25f23 DL |
1831 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1832 | { | |
1833 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1834 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1835 | ||
1836 | if (gmch_ctrl) | |
1837 | return 1 << (20 + gmch_ctrl); | |
1838 | ||
1839 | return 0; | |
1840 | } | |
1841 | ||
baa09f5f | 1842 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1843 | { |
1844 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1845 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1846 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1847 | } | |
1848 | ||
9459d252 BW |
1849 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1850 | { | |
1851 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1852 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1853 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1854 | } | |
1855 | ||
d7f25f23 DL |
1856 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1857 | { | |
1858 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1859 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1860 | ||
1861 | /* | |
1862 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1863 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1864 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1865 | */ | |
1866 | if (gmch_ctrl < 0x11) | |
1867 | return gmch_ctrl << 25; | |
1868 | else if (gmch_ctrl < 0x17) | |
1869 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1870 | else | |
1871 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1872 | } | |
1873 | ||
66375014 DL |
1874 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
1875 | { | |
1876 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1877 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1878 | ||
1879 | if (gen9_gmch_ctl < 0xf0) | |
1880 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
1881 | else | |
1882 | /* 4MB increments starting at 0xf0 for 4MB */ | |
1883 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
1884 | } | |
1885 | ||
63340133 BW |
1886 | static int ggtt_probe_common(struct drm_device *dev, |
1887 | size_t gtt_size) | |
1888 | { | |
1889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1890 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1891 | int ret; |
1892 | ||
1893 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1894 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1895 | (pci_resource_len(dev->pdev, 0) / 2); |
1896 | ||
21c34607 | 1897 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1898 | if (!dev_priv->gtt.gsm) { |
1899 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1900 | return -ENOMEM; | |
1901 | } | |
1902 | ||
1903 | ret = setup_scratch_page(dev); | |
1904 | if (ret) { | |
1905 | DRM_ERROR("Scratch setup failed\n"); | |
1906 | /* iounmap will also get called at remove, but meh */ | |
1907 | iounmap(dev_priv->gtt.gsm); | |
1908 | } | |
1909 | ||
1910 | return ret; | |
1911 | } | |
1912 | ||
fbe5d36e BW |
1913 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1914 | * bits. When using advanced contexts each context stores its own PAT, but | |
1915 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1916 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1917 | { |
fbe5d36e BW |
1918 | uint64_t pat; |
1919 | ||
1920 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1921 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1922 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1923 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1924 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1925 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1926 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1927 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1928 | ||
d6a8b72e RV |
1929 | if (!USES_PPGTT(dev_priv->dev)) |
1930 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
1931 | * so RTL will always use the value corresponding to | |
1932 | * pat_sel = 000". | |
1933 | * So let's disable cache for GGTT to avoid screen corruptions. | |
1934 | * MOCS still can be used though. | |
1935 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
1936 | * before this patch, i.e. the same uncached + snooping access | |
1937 | * like on gen6/7 seems to be in effect. | |
1938 | * - So this just fixes blitter/render access. Again it looks | |
1939 | * like it's not just uncached access, but uncached + snooping. | |
1940 | * So we can still hold onto all our assumptions wrt cpu | |
1941 | * clflushing on LLC machines. | |
1942 | */ | |
1943 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
1944 | ||
fbe5d36e BW |
1945 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
1946 | * write would work. */ | |
1947 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1948 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1949 | } | |
1950 | ||
ee0ce478 VS |
1951 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1952 | { | |
1953 | uint64_t pat; | |
1954 | ||
1955 | /* | |
1956 | * Map WB on BDW to snooped on CHV. | |
1957 | * | |
1958 | * Only the snoop bit has meaning for CHV, the rest is | |
1959 | * ignored. | |
1960 | * | |
cf3d262e VS |
1961 | * The hardware will never snoop for certain types of accesses: |
1962 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
1963 | * - PPGTT page tables | |
1964 | * - some other special cycles | |
1965 | * | |
1966 | * As with BDW, we also need to consider the following for GT accesses: | |
1967 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
1968 | * so RTL will always use the value corresponding to | |
1969 | * pat_sel = 000". | |
1970 | * Which means we must set the snoop bit in PAT entry 0 | |
1971 | * in order to keep the global status page working. | |
ee0ce478 VS |
1972 | */ |
1973 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1974 | GEN8_PPAT(1, 0) | | |
1975 | GEN8_PPAT(2, 0) | | |
1976 | GEN8_PPAT(3, 0) | | |
1977 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1978 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1979 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1980 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1981 | ||
1982 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1983 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1984 | } | |
1985 | ||
63340133 BW |
1986 | static int gen8_gmch_probe(struct drm_device *dev, |
1987 | size_t *gtt_total, | |
1988 | size_t *stolen, | |
1989 | phys_addr_t *mappable_base, | |
1990 | unsigned long *mappable_end) | |
1991 | { | |
1992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1993 | unsigned int gtt_size; | |
1994 | u16 snb_gmch_ctl; | |
1995 | int ret; | |
1996 | ||
1997 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1998 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1999 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2000 | ||
2001 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2002 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2003 | ||
2004 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2005 | ||
66375014 DL |
2006 | if (INTEL_INFO(dev)->gen >= 9) { |
2007 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2008 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2009 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2010 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2011 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2012 | } else { | |
2013 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2014 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2015 | } | |
63340133 | 2016 | |
d31eb10e | 2017 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 2018 | |
ee0ce478 VS |
2019 | if (IS_CHERRYVIEW(dev)) |
2020 | chv_setup_private_ppat(dev_priv); | |
2021 | else | |
2022 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2023 | |
63340133 BW |
2024 | ret = ggtt_probe_common(dev, gtt_size); |
2025 | ||
94ec8f61 BW |
2026 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2027 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2028 | |
2029 | return ret; | |
2030 | } | |
2031 | ||
baa09f5f BW |
2032 | static int gen6_gmch_probe(struct drm_device *dev, |
2033 | size_t *gtt_total, | |
41907ddc BW |
2034 | size_t *stolen, |
2035 | phys_addr_t *mappable_base, | |
2036 | unsigned long *mappable_end) | |
e76e9aeb BW |
2037 | { |
2038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2039 | unsigned int gtt_size; |
e76e9aeb | 2040 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2041 | int ret; |
2042 | ||
41907ddc BW |
2043 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2044 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2045 | ||
baa09f5f BW |
2046 | /* 64/512MB is the current min/max we actually know of, but this is just |
2047 | * a coarse sanity check. | |
e76e9aeb | 2048 | */ |
41907ddc | 2049 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2050 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2051 | dev_priv->gtt.mappable_end); | |
2052 | return -ENXIO; | |
e76e9aeb BW |
2053 | } |
2054 | ||
e76e9aeb BW |
2055 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2056 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2057 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2058 | |
c4ae25ec | 2059 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2060 | |
63340133 BW |
2061 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2062 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2063 | |
63340133 | 2064 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2065 | |
853ba5d2 BW |
2066 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2067 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2068 | |
e76e9aeb BW |
2069 | return ret; |
2070 | } | |
2071 | ||
853ba5d2 | 2072 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2073 | { |
853ba5d2 BW |
2074 | |
2075 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2076 | |
853ba5d2 BW |
2077 | iounmap(gtt->gsm); |
2078 | teardown_scratch_page(vm->dev); | |
644ec02b | 2079 | } |
baa09f5f BW |
2080 | |
2081 | static int i915_gmch_probe(struct drm_device *dev, | |
2082 | size_t *gtt_total, | |
41907ddc BW |
2083 | size_t *stolen, |
2084 | phys_addr_t *mappable_base, | |
2085 | unsigned long *mappable_end) | |
baa09f5f BW |
2086 | { |
2087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2088 | int ret; | |
2089 | ||
baa09f5f BW |
2090 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2091 | if (!ret) { | |
2092 | DRM_ERROR("failed to set up gmch\n"); | |
2093 | return -EIO; | |
2094 | } | |
2095 | ||
41907ddc | 2096 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2097 | |
2098 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2099 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2100 | |
c0a7f818 CW |
2101 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2102 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2103 | ||
baa09f5f BW |
2104 | return 0; |
2105 | } | |
2106 | ||
853ba5d2 | 2107 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2108 | { |
2109 | intel_gmch_remove(); | |
2110 | } | |
2111 | ||
2112 | int i915_gem_gtt_init(struct drm_device *dev) | |
2113 | { | |
2114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2115 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2116 | int ret; |
2117 | ||
baa09f5f | 2118 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2119 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2120 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2121 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2122 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2123 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2124 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2125 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2126 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2127 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2128 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2129 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2130 | else if (INTEL_INFO(dev)->gen >= 7) |
2131 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2132 | else |
350ec881 | 2133 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2134 | } else { |
2135 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2136 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2137 | } |
2138 | ||
853ba5d2 | 2139 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2140 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2141 | if (ret) |
baa09f5f | 2142 | return ret; |
baa09f5f | 2143 | |
853ba5d2 BW |
2144 | gtt->base.dev = dev; |
2145 | ||
baa09f5f | 2146 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2147 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2148 | gtt->base.total >> 20); | |
b2f21b4d BW |
2149 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2150 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2151 | #ifdef CONFIG_INTEL_IOMMU |
2152 | if (intel_iommu_gfx_mapped) | |
2153 | DRM_INFO("VT-d active for gfx access\n"); | |
2154 | #endif | |
cfa7c862 DV |
2155 | /* |
2156 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2157 | * user's requested state against the hardware/driver capabilities. We | |
2158 | * do this now so that we can print out any log messages once rather | |
2159 | * than every time we check intel_enable_ppgtt(). | |
2160 | */ | |
2161 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2162 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2163 | |
2164 | return 0; | |
2165 | } | |
6f65e29a BW |
2166 | |
2167 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2168 | struct i915_address_space *vm) | |
2169 | { | |
2170 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2171 | if (vma == NULL) | |
2172 | return ERR_PTR(-ENOMEM); | |
2173 | ||
2174 | INIT_LIST_HEAD(&vma->vma_link); | |
2175 | INIT_LIST_HEAD(&vma->mm_list); | |
2176 | INIT_LIST_HEAD(&vma->exec_list); | |
2177 | vma->vm = vm; | |
2178 | vma->obj = obj; | |
2179 | ||
2180 | switch (INTEL_INFO(vm->dev)->gen) { | |
fb8aad4b | 2181 | case 9: |
6f65e29a BW |
2182 | case 8: |
2183 | case 7: | |
2184 | case 6: | |
7e0d96bc BW |
2185 | if (i915_is_ggtt(vm)) { |
2186 | vma->unbind_vma = ggtt_unbind_vma; | |
2187 | vma->bind_vma = ggtt_bind_vma; | |
2188 | } else { | |
2189 | vma->unbind_vma = ppgtt_unbind_vma; | |
2190 | vma->bind_vma = ppgtt_bind_vma; | |
2191 | } | |
6f65e29a BW |
2192 | break; |
2193 | case 5: | |
2194 | case 4: | |
2195 | case 3: | |
2196 | case 2: | |
2197 | BUG_ON(!i915_is_ggtt(vm)); | |
2198 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2199 | vma->bind_vma = i915_ggtt_bind_vma; | |
2200 | break; | |
2201 | default: | |
2202 | BUG(); | |
2203 | } | |
2204 | ||
2205 | /* Keep GGTT vmas first to make debug easier */ | |
2206 | if (i915_is_ggtt(vm)) | |
2207 | list_add(&vma->vma_link, &obj->vma_list); | |
e07f0552 | 2208 | else { |
6f65e29a | 2209 | list_add_tail(&vma->vma_link, &obj->vma_list); |
e07f0552 MT |
2210 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
2211 | } | |
6f65e29a BW |
2212 | |
2213 | return vma; | |
2214 | } | |
2215 | ||
2216 | struct i915_vma * | |
2217 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2218 | struct i915_address_space *vm) | |
2219 | { | |
2220 | struct i915_vma *vma; | |
2221 | ||
2222 | vma = i915_gem_obj_to_vma(obj, vm); | |
2223 | if (!vma) | |
2224 | vma = __i915_gem_vma_create(obj, vm); | |
2225 | ||
2226 | return vma; | |
2227 | } |