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drm/i915: Store number of active engines in device info
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
5bab6f60 27#include <linux/stop_machine.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
76aaf220 30#include "i915_drv.h"
5dda8fa3 31#include "i915_vgpu.h"
76aaf220
DV		 32#include "i915_trace.h"
33#include "intel_drv.h"
34
45f8f69a
TU		 35/**
36 * DOC: Global GTT views
37 *
38 * Background and previous state
39 *
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
43 *
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
47 *
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
50 * (2x2 pages):
51 *
52 * 12
53 * 34
54 *
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
58 *
59 * 1212
60 * 3434
61 *
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
64 *
65 * Implementation and usage
66 *
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
69 *
70 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 74 *
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
79 *
80 * Code wanting to add or use a new GGTT view needs to:
81 *
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
85 *
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
89 *
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
93 *
94 */
95
ce7fda2e
CW		 96static inline struct i915_ggtt *
97i915_vm_to_ggtt(struct i915_address_space *vm)
98{
99 GEM_BUG_ON(!i915_is_ggtt(vm));
100 return container_of(vm, struct i915_ggtt, base);
101}
102
70b9f6f8
DV		 103static int
104i915_get_ggtt_vma_pages(struct i915_vma *vma);
105
b5e16987
VS		 106const struct i915_ggtt_view i915_ggtt_view_normal = {
107 .type = I915_GGTT_VIEW_NORMAL,
108};
9abc4648 109const struct i915_ggtt_view i915_ggtt_view_rotated = {
b5e16987 110 .type = I915_GGTT_VIEW_ROTATED,
9abc4648 111};
fe14d5f4 112
c033666a
CW		 113int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
114 int enable_ppgtt)
cfa7c862 115{
1893a71b
CW		 116 bool has_aliasing_ppgtt;
117 bool has_full_ppgtt;
1f9a99e0 118 bool has_full_48bit_ppgtt;
1893a71b 119
c033666a
CW		 120 has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
121 has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
122 has_full_48bit_ppgtt =
123 IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
1893a71b 124
c033666a 125 if (intel_vgpu_active(dev_priv))
71ba2d64
YZ		 126 has_full_ppgtt = false; /* emulation is too hard */
127
0e4ca100
CW		 128 if (!has_aliasing_ppgtt)
129 return 0;
130
70ee45e1
DL		 131 /*
132 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
133 * execlists, the sole mechanism available to submit work.
134 */
c033666a 135 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
cfa7c862
DV		 136 return 0;
137
138 if (enable_ppgtt == 1)
139 return 1;
140
1893a71b 141 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 142 return 2;
143
1f9a99e0
MT		 144 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
145 return 3;
146
93a25a9e
DV		 147#ifdef CONFIG_INTEL_IOMMU
148 /* Disable ppgtt on SNB if VT-d is on. */
c033666a 149 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
93a25a9e 150 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 151 return 0;
93a25a9e
DV		 152 }
153#endif
154
62942ed7 155 /* Early VLV doesn't have this */
91c8a326 156 if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
62942ed7
JB		 157 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
158 return 0;
159 }
160
c033666a 161 if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
1f9a99e0 162 return has_full_48bit_ppgtt ? 3 : 2;
2f82bbdf
MT		 163 else
164 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 165}
166
70b9f6f8
DV		 167static int ppgtt_bind_vma(struct i915_vma *vma,
168 enum i915_cache_level cache_level,
169 u32 unused)
47552659
DV		 170{
171 u32 pte_flags = 0;
172
173 /* Currently applicable only to VLV */
174 if (vma->obj->gt_ro)
175 pte_flags |= PTE_READ_ONLY;
176
177 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
178 cache_level, pte_flags);
70b9f6f8
DV		 179
180 return 0;
47552659
DV		 181}
182
183static void ppgtt_unbind_vma(struct i915_vma *vma)
184{
185 vma->vm->clear_range(vma->vm,
186 vma->node.start,
de180033 187 vma->size,
47552659
DV		 188 true);
189}
6f65e29a 190
2c642b07
DV		 191static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
192 enum i915_cache_level level,
193 bool valid)
94ec8f61 194{
07749ef3 195 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 196 pte |= addr;
63c42e56
BW		 197
198 switch (level) {
199 case I915_CACHE_NONE:
fbe5d36e 200 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 201 break;
202 case I915_CACHE_WT:
203 pte |= PPAT_DISPLAY_ELLC_INDEX;
204 break;
205 default:
206 pte |= PPAT_CACHED_INDEX;
207 break;
208 }
209
94ec8f61
BW		 210 return pte;
211}
212
fe36f55d
MK		 213static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
214 const enum i915_cache_level level)
b1fe6673 215{
07749ef3 216 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 217 pde |= addr;
218 if (level != I915_CACHE_NONE)
219 pde |= PPAT_CACHED_PDE_INDEX;
220 else
221 pde |= PPAT_UNCACHED_INDEX;
222 return pde;
223}
224
762d9936
MT		 225#define gen8_pdpe_encode gen8_pde_encode
226#define gen8_pml4e_encode gen8_pde_encode
227
07749ef3
MT		 228static gen6_pte_t snb_pte_encode(dma_addr_t addr,
229 enum i915_cache_level level,
230 bool valid, u32 unused)
54d12527 231{
07749ef3 232 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 233 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 234
235 switch (level) {
350ec881
CW		 236 case I915_CACHE_L3_LLC:
237 case I915_CACHE_LLC:
238 pte |= GEN6_PTE_CACHE_LLC;
239 break;
240 case I915_CACHE_NONE:
241 pte |= GEN6_PTE_UNCACHED;
242 break;
243 default:
5f77eeb0 244 MISSING_CASE(level);
350ec881
CW		 245 }
246
247 return pte;
248}
249
07749ef3
MT		 250static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
251 enum i915_cache_level level,
252 bool valid, u32 unused)
350ec881 253{
07749ef3 254 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 255 pte |= GEN6_PTE_ADDR_ENCODE(addr);
256
257 switch (level) {
258 case I915_CACHE_L3_LLC:
259 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 260 break;
261 case I915_CACHE_LLC:
262 pte |= GEN6_PTE_CACHE_LLC;
263 break;
264 case I915_CACHE_NONE:
9119708c 265 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 266 break;
267 default:
5f77eeb0 268 MISSING_CASE(level);
e7210c3c
BW		 269 }
270
54d12527
BW		 271 return pte;
272}
273
07749ef3
MT		 274static gen6_pte_t byt_pte_encode(dma_addr_t addr,
275 enum i915_cache_level level,
276 bool valid, u32 flags)
93c34e70 277{
07749ef3 278 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 279 pte |= GEN6_PTE_ADDR_ENCODE(addr);
280
24f3a8cf
AG		 281 if (!(flags & PTE_READ_ONLY))
282 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 283
284 if (level != I915_CACHE_NONE)
285 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
286
287 return pte;
288}
289
07749ef3
MT		 290static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
291 enum i915_cache_level level,
292 bool valid, u32 unused)
9119708c 293{
07749ef3 294 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 295 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 296
297 if (level != I915_CACHE_NONE)
87a6b688 298 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 299
300 return pte;
301}
302
07749ef3
MT		 303static gen6_pte_t iris_pte_encode(dma_addr_t addr,
304 enum i915_cache_level level,
305 bool valid, u32 unused)
4d15c145 306{
07749ef3 307 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 308 pte |= HSW_PTE_ADDR_ENCODE(addr);
309
651d794f
CW		 310 switch (level) {
311 case I915_CACHE_NONE:
312 break;
313 case I915_CACHE_WT:
c51e9701 314 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 315 break;
316 default:
c51e9701 317 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 318 break;
319 }
4d15c145
BW		 320
321 return pte;
322}
323
c114f76a
MK		 324static int __setup_page_dma(struct drm_device *dev,
325 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 326{
327 struct device *device = &dev->pdev->dev;
328
c114f76a 329 p->page = alloc_page(flags);
44159ddb
MK		 330 if (!p->page)
331 return -ENOMEM;
678d96fb 332
44159ddb
MK		 333 p->daddr = dma_map_page(device,
334 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 335
44159ddb
MK		 336 if (dma_mapping_error(device, p->daddr)) {
337 __free_page(p->page);
338 return -EINVAL;
339 }
1266cdb1
MT		 340
341 return 0;
678d96fb
BW		 342}
343
c114f76a
MK		 344static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
345{
346 return __setup_page_dma(dev, p, GFP_KERNEL);
347}
348
44159ddb 349static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 350{
44159ddb 351 if (WARN_ON(!p->page))
06fda602 352 return;
678d96fb 353
44159ddb
MK		 354 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
355 __free_page(p->page);
356 memset(p, 0, sizeof(*p));
357}
358
d1c54acd 359static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 360{
d1c54acd
MK		 361 return kmap_atomic(p->page);
362}
73eeea53 363
d1c54acd
MK		 364/* We use the flushing unmap only with ppgtt structures:
365 * page directories, page tables and scratch pages.
366 */
367static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
368{
73eeea53
MK		 369 /* There are only few exceptions for gen >=6. chv and bxt.
370 * And we are not sure about the latter so play safe for now.
371 */
372 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
373 drm_clflush_virt_range(vaddr, PAGE_SIZE);
374
375 kunmap_atomic(vaddr);
376}
377
567047be 378#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 379#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
380
567047be
MK		 381#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
382#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
383#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
384#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
385
d1c54acd
MK		 386static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
387 const uint64_t val)
388{
389 int i;
390 uint64_t * const vaddr = kmap_page_dma(p);
391
392 for (i = 0; i < 512; i++)
393 vaddr[i] = val;
394
395 kunmap_page_dma(dev, vaddr);
396}
397
73eeea53
MK		 398static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
399 const uint32_t val32)
400{
401 uint64_t v = val32;
402
403 v = v << 32 | val32;
404
405 fill_page_dma(dev, p, v);
406}
407
4ad2af1e
MK		 408static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
409{
410 struct i915_page_scratch *sp;
411 int ret;
412
413 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
414 if (sp == NULL)
415 return ERR_PTR(-ENOMEM);
416
417 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
418 if (ret) {
419 kfree(sp);
420 return ERR_PTR(ret);
421 }
422
423 set_pages_uc(px_page(sp), 1);
424
425 return sp;
426}
427
428static void free_scratch_page(struct drm_device *dev,
429 struct i915_page_scratch *sp)
430{
431 set_pages_wb(px_page(sp), 1);
432
433 cleanup_px(dev, sp);
434 kfree(sp);
435}
436
8a1ebd74 437static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 438{
ec565b3c 439 struct i915_page_table *pt;
678d96fb
BW		 440 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
441 GEN8_PTES : GEN6_PTES;
442 int ret = -ENOMEM;
06fda602
BW		 443
444 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
445 if (!pt)
446 return ERR_PTR(-ENOMEM);
447
678d96fb
BW		 448 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
449 GFP_KERNEL);
450
451 if (!pt->used_ptes)
452 goto fail_bitmap;
453
567047be 454 ret = setup_px(dev, pt);
678d96fb 455 if (ret)
44159ddb 456 goto fail_page_m;
06fda602
BW		 457
458 return pt;
678d96fb 459
44159ddb 460fail_page_m:
678d96fb
BW		 461 kfree(pt->used_ptes);
462fail_bitmap:
463 kfree(pt);
464
465 return ERR_PTR(ret);
06fda602
BW		 466}
467
2e906bea 468static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 469{
2e906bea
MK		 470 cleanup_px(dev, pt);
471 kfree(pt->used_ptes);
472 kfree(pt);
473}
474
475static void gen8_initialize_pt(struct i915_address_space *vm,
476 struct i915_page_table *pt)
477{
478 gen8_pte_t scratch_pte;
479
480 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
481 I915_CACHE_LLC, true);
482
483 fill_px(vm->dev, pt, scratch_pte);
484}
485
486static void gen6_initialize_pt(struct i915_address_space *vm,
487 struct i915_page_table *pt)
488{
489 gen6_pte_t scratch_pte;
490
491 WARN_ON(px_dma(vm->scratch_page) == 0);
492
493 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
494 I915_CACHE_LLC, true, 0);
495
496 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 497}
498
8a1ebd74 499static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 500{
ec565b3c 501 struct i915_page_directory *pd;
33c8819f 502 int ret = -ENOMEM;
06fda602
BW		 503
504 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
505 if (!pd)
506 return ERR_PTR(-ENOMEM);
507
33c8819f
MT		 508 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
509 sizeof(*pd->used_pdes), GFP_KERNEL);
510 if (!pd->used_pdes)
a08e111a 511 goto fail_bitmap;
33c8819f 512
567047be 513 ret = setup_px(dev, pd);
33c8819f 514 if (ret)
a08e111a 515 goto fail_page_m;
e5815a2e 516
06fda602 517 return pd;
33c8819f 518
a08e111a 519fail_page_m:
33c8819f 520 kfree(pd->used_pdes);
a08e111a 521fail_bitmap:
33c8819f
MT		 522 kfree(pd);
523
524 return ERR_PTR(ret);
06fda602
BW		 525}
526
2e906bea
MK		 527static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
528{
529 if (px_page(pd)) {
530 cleanup_px(dev, pd);
531 kfree(pd->used_pdes);
532 kfree(pd);
533 }
534}
535
536static void gen8_initialize_pd(struct i915_address_space *vm,
537 struct i915_page_directory *pd)
538{
539 gen8_pde_t scratch_pde;
540
541 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
542
543 fill_px(vm->dev, pd, scratch_pde);
544}
545
6ac18502
MT		 546static int __pdp_init(struct drm_device *dev,
547 struct i915_page_directory_pointer *pdp)
548{
549 size_t pdpes = I915_PDPES_PER_PDP(dev);
550
551 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
552 sizeof(unsigned long),
553 GFP_KERNEL);
554 if (!pdp->used_pdpes)
555 return -ENOMEM;
556
557 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
558 GFP_KERNEL);
559 if (!pdp->page_directory) {
560 kfree(pdp->used_pdpes);
561 /* the PDP might be the statically allocated top level. Keep it
562 * as clean as possible */
563 pdp->used_pdpes = NULL;
564 return -ENOMEM;
565 }
566
567 return 0;
568}
569
570static void __pdp_fini(struct i915_page_directory_pointer *pdp)
571{
572 kfree(pdp->used_pdpes);
573 kfree(pdp->page_directory);
574 pdp->page_directory = NULL;
575}
576
762d9936
MT		 577static struct
578i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
579{
580 struct i915_page_directory_pointer *pdp;
581 int ret = -ENOMEM;
582
583 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
584
585 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
586 if (!pdp)
587 return ERR_PTR(-ENOMEM);
588
589 ret = __pdp_init(dev, pdp);
590 if (ret)
591 goto fail_bitmap;
592
593 ret = setup_px(dev, pdp);
594 if (ret)
595 goto fail_page_m;
596
597 return pdp;
598
599fail_page_m:
600 __pdp_fini(pdp);
601fail_bitmap:
602 kfree(pdp);
603
604 return ERR_PTR(ret);
605}
606
6ac18502
MT		 607static void free_pdp(struct drm_device *dev,
608 struct i915_page_directory_pointer *pdp)
609{
610 __pdp_fini(pdp);
762d9936
MT		 611 if (USES_FULL_48BIT_PPGTT(dev)) {
612 cleanup_px(dev, pdp);
613 kfree(pdp);
614 }
615}
616
69ab76fd
MT		 617static void gen8_initialize_pdp(struct i915_address_space *vm,
618 struct i915_page_directory_pointer *pdp)
619{
620 gen8_ppgtt_pdpe_t scratch_pdpe;
621
622 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
623
624 fill_px(vm->dev, pdp, scratch_pdpe);
625}
626
627static void gen8_initialize_pml4(struct i915_address_space *vm,
628 struct i915_pml4 *pml4)
629{
630 gen8_ppgtt_pml4e_t scratch_pml4e;
631
632 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
633 I915_CACHE_LLC);
634
635 fill_px(vm->dev, pml4, scratch_pml4e);
636}
637
762d9936
MT		 638static void
639gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
640 struct i915_page_directory_pointer *pdp,
641 struct i915_page_directory *pd,
642 int index)
643{
644 gen8_ppgtt_pdpe_t *page_directorypo;
645
646 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
647 return;
648
649 page_directorypo = kmap_px(pdp);
650 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
651 kunmap_px(ppgtt, page_directorypo);
652}
653
654static void
655gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
656 struct i915_pml4 *pml4,
657 struct i915_page_directory_pointer *pdp,
658 int index)
659{
660 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
661
662 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
663 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
664 kunmap_px(ppgtt, pagemap);
6ac18502
MT		 665}
666
94e409c1 667/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 668static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 669 unsigned entry,
670 dma_addr_t addr)
94e409c1 671{
7e37f889 672 struct intel_ring *ring = req->ring;
4a570db5 673 struct intel_engine_cs *engine = req->engine;
94e409c1
BW		 674 int ret;
675
676 BUG_ON(entry >= 4);
677
5fb9de1a 678 ret = intel_ring_begin(req, 6);
94e409c1
BW		 679 if (ret)
680 return ret;
681
b5321f30
CW		 682 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
683 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry));
684 intel_ring_emit(ring, upper_32_bits(addr));
685 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
686 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry));
687 intel_ring_emit(ring, lower_32_bits(addr));
688 intel_ring_advance(ring);
94e409c1
BW		 689
690 return 0;
691}
692
2dba3239
MT		 693static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
694 struct drm_i915_gem_request *req)
94e409c1 695{
eeb9488e 696 int i, ret;
94e409c1 697
7cb6d7ac 698 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 699 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
700
e85b26dc 701 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 702 if (ret)
703 return ret;
94e409c1 704 }
d595bd4b 705
eeb9488e 706 return 0;
94e409c1
BW		 707}
708
2dba3239
MT		 709static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
710 struct drm_i915_gem_request *req)
711{
712 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
713}
714
f9b5b782
MT		 715static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
716 struct i915_page_directory_pointer *pdp,
717 uint64_t start,
718 uint64_t length,
719 gen8_pte_t scratch_pte)
459108b8 720{
e5716f55 721 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782 722 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 723 unsigned pdpe = gen8_pdpe_index(start);
724 unsigned pde = gen8_pde_index(start);
725 unsigned pte = gen8_pte_index(start);
782f1495 726 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 727 unsigned last_pte, i;
728
f9b5b782
MT		 729 if (WARN_ON(!pdp))
730 return;
459108b8
BW		 731
732 while (num_entries) {
ec565b3c
MT		 733 struct i915_page_directory *pd;
734 struct i915_page_table *pt;
06fda602 735
d4ec9da0 736 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 737 break;
06fda602 738
d4ec9da0 739 pd = pdp->page_directory[pdpe];
06fda602
BW		 740
741 if (WARN_ON(!pd->page_table[pde]))
00245266 742 break;
06fda602
BW		 743
744 pt = pd->page_table[pde];
745
567047be 746 if (WARN_ON(!px_page(pt)))
00245266 747 break;
06fda602 748
7ad47cf2 749 last_pte = pte + num_entries;
07749ef3
MT		 750 if (last_pte > GEN8_PTES)
751 last_pte = GEN8_PTES;
459108b8 752
d1c54acd 753 pt_vaddr = kmap_px(pt);
459108b8 754
7ad47cf2 755 for (i = pte; i < last_pte; i++) {
459108b8 756 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 757 num_entries--;
758 }
459108b8 759
44a71024 760 kunmap_px(ppgtt, pt_vaddr);
459108b8 761
7ad47cf2 762 pte = 0;
07749ef3 763 if (++pde == I915_PDES) {
de5ba8eb
MT		 764 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
765 break;
7ad47cf2
BW		 766 pde = 0;
767 }
459108b8
BW		 768 }
769}
770
f9b5b782
MT		 771static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
772 uint64_t start,
773 uint64_t length,
774 bool use_scratch)
9df15b49 775{
e5716f55 776 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782
MT		 777 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
778 I915_CACHE_LLC, use_scratch);
779
de5ba8eb
MT		 780 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
781 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
782 scratch_pte);
783 } else {
e8ebd8e2 784 uint64_t pml4e;
de5ba8eb
MT		 785 struct i915_page_directory_pointer *pdp;
786
e8ebd8e2 787 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 788 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
789 scratch_pte);
790 }
791 }
f9b5b782
MT		 792}
793
794static void
795gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
796 struct i915_page_directory_pointer *pdp,
3387d433 797 struct sg_page_iter *sg_iter,
f9b5b782
MT		 798 uint64_t start,
799 enum i915_cache_level cache_level)
800{
e5716f55 801 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 802 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 803 unsigned pdpe = gen8_pdpe_index(start);
804 unsigned pde = gen8_pde_index(start);
805 unsigned pte = gen8_pte_index(start);
9df15b49 806
6f1cc993 807 pt_vaddr = NULL;
7ad47cf2 808
3387d433 809 while (__sg_page_iter_next(sg_iter)) {
d7b3de91 810 if (pt_vaddr == NULL) {
d4ec9da0 811 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 812 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 813 pt_vaddr = kmap_px(pt);
d7b3de91 814 }
9df15b49 815
7ad47cf2 816 pt_vaddr[pte] =
3387d433 817 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
6f1cc993 818 cache_level, true);
07749ef3 819 if (++pte == GEN8_PTES) {
d1c54acd 820 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 821 pt_vaddr = NULL;
07749ef3 822 if (++pde == I915_PDES) {
de5ba8eb
MT		 823 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
824 break;
7ad47cf2
BW		 825 pde = 0;
826 }
827 pte = 0;
9df15b49
BW		 828 }
829 }
d1c54acd
MK		 830
831 if (pt_vaddr)
832 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 833}
834
f9b5b782
MT		 835static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
836 struct sg_table *pages,
837 uint64_t start,
838 enum i915_cache_level cache_level,
839 u32 unused)
840{
e5716f55 841 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3387d433 842 struct sg_page_iter sg_iter;
f9b5b782 843
3387d433 844 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
de5ba8eb
MT		 845
846 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
847 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
848 cache_level);
849 } else {
850 struct i915_page_directory_pointer *pdp;
e8ebd8e2 851 uint64_t pml4e;
de5ba8eb
MT		 852 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
853
e8ebd8e2 854 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 855 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
856 start, cache_level);
857 }
858 }
f9b5b782
MT		 859}
860
f37c0505
MT		 861static void gen8_free_page_tables(struct drm_device *dev,
862 struct i915_page_directory *pd)
7ad47cf2
BW		 863{
864 int i;
865
567047be 866 if (!px_page(pd))
7ad47cf2
BW		 867 return;
868
33c8819f 869 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 870 if (WARN_ON(!pd->page_table[i]))
871 continue;
7ad47cf2 872
a08e111a 873 free_pt(dev, pd->page_table[i]);
06fda602
BW		 874 pd->page_table[i] = NULL;
875 }
d7b3de91
BW		 876}
877
8776f02b
MK		 878static int gen8_init_scratch(struct i915_address_space *vm)
879{
880 struct drm_device *dev = vm->dev;
64c050db 881 int ret;
8776f02b
MK		 882
883 vm->scratch_page = alloc_scratch_page(dev);
884 if (IS_ERR(vm->scratch_page))
885 return PTR_ERR(vm->scratch_page);
886
887 vm->scratch_pt = alloc_pt(dev);
888 if (IS_ERR(vm->scratch_pt)) {
64c050db
MA		 889 ret = PTR_ERR(vm->scratch_pt);
890 goto free_scratch_page;
8776f02b
MK		 891 }
892
893 vm->scratch_pd = alloc_pd(dev);
894 if (IS_ERR(vm->scratch_pd)) {
64c050db
MA		 895 ret = PTR_ERR(vm->scratch_pd);
896 goto free_pt;
8776f02b
MK		 897 }
898
69ab76fd
MT		 899 if (USES_FULL_48BIT_PPGTT(dev)) {
900 vm->scratch_pdp = alloc_pdp(dev);
901 if (IS_ERR(vm->scratch_pdp)) {
64c050db
MA		 902 ret = PTR_ERR(vm->scratch_pdp);
903 goto free_pd;
69ab76fd
MT		 904 }
905 }
906
8776f02b
MK		 907 gen8_initialize_pt(vm, vm->scratch_pt);
908 gen8_initialize_pd(vm, vm->scratch_pd);
69ab76fd
MT		 909 if (USES_FULL_48BIT_PPGTT(dev))
910 gen8_initialize_pdp(vm, vm->scratch_pdp);
8776f02b
MK		 911
912 return 0;
64c050db
MA		 913
914free_pd:
915 free_pd(dev, vm->scratch_pd);
916free_pt:
917 free_pt(dev, vm->scratch_pt);
918free_scratch_page:
919 free_scratch_page(dev, vm->scratch_page);
920
921 return ret;
8776f02b
MK		 922}
923
650da34c
ZL		 924static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
925{
926 enum vgt_g2v_type msg;
df28564d 927 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
650da34c
ZL		 928 int i;
929
df28564d 930 if (USES_FULL_48BIT_PPGTT(dev_priv)) {
650da34c
ZL		 931 u64 daddr = px_dma(&ppgtt->pml4);
932
ab75bb5d
VS		 933 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
934 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
650da34c
ZL		 935
936 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
937 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
938 } else {
939 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
940 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
941
ab75bb5d
VS		 942 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
943 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
650da34c
ZL		 944 }
945
946 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
947 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
948 }
949
950 I915_WRITE(vgtif_reg(g2v_notify), msg);
951
952 return 0;
953}
954
8776f02b
MK		 955static void gen8_free_scratch(struct i915_address_space *vm)
956{
957 struct drm_device *dev = vm->dev;
958
69ab76fd
MT		 959 if (USES_FULL_48BIT_PPGTT(dev))
960 free_pdp(dev, vm->scratch_pdp);
8776f02b
MK		 961 free_pd(dev, vm->scratch_pd);
962 free_pt(dev, vm->scratch_pt);
963 free_scratch_page(dev, vm->scratch_page);
964}
965
762d9936
MT		 966static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
967 struct i915_page_directory_pointer *pdp)
b45a6715
BW		 968{
969 int i;
970
d4ec9da0
MT		 971 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
972 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 973 continue;
974
d4ec9da0
MT		 975 gen8_free_page_tables(dev, pdp->page_directory[i]);
976 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 977 }
69876bed 978
d4ec9da0 979 free_pdp(dev, pdp);
762d9936
MT		 980}
981
982static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
983{
984 int i;
985
986 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
987 if (WARN_ON(!ppgtt->pml4.pdps[i]))
988 continue;
989
990 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
991 }
992
993 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
994}
995
996static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
997{
e5716f55 998 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 999
c033666a 1000 if (intel_vgpu_active(to_i915(vm->dev)))
650da34c
ZL		 1001 gen8_ppgtt_notify_vgt(ppgtt, false);
1002
762d9936
MT		 1003 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
1004 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
1005 else
1006 gen8_ppgtt_cleanup_4lvl(ppgtt);
d4ec9da0 1007
8776f02b 1008 gen8_free_scratch(vm);
b45a6715
BW		 1009}
1010
d7b2633d
MT		 1011/**
1012 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 1013 * @vm: Master vm structure.
1014 * @pd: Page directory for this address range.
d7b2633d 1015 * @start: Starting virtual address to begin allocations.
d4ec9da0 1016 * @length: Size of the allocations.
d7b2633d
MT		 1017 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1018 * caller to free on error.
1019 *
1020 * Allocate the required number of page tables. Extremely similar to
1021 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1022 * the page directory boundary (instead of the page directory pointer). That
1023 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1024 * possible, and likely that the caller will need to use multiple calls of this
1025 * function to achieve the appropriate allocation.
1026 *
1027 * Return: 0 if success; negative error code otherwise.
1028 */
d4ec9da0 1029static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 1030 struct i915_page_directory *pd,
5441f0cb 1031 uint64_t start,
d7b2633d
MT		 1032 uint64_t length,
1033 unsigned long *new_pts)
bf2b4ed2 1034{
d4ec9da0 1035 struct drm_device *dev = vm->dev;
d7b2633d 1036 struct i915_page_table *pt;
5441f0cb 1037 uint32_t pde;
bf2b4ed2 1038
e8ebd8e2 1039 gen8_for_each_pde(pt, pd, start, length, pde) {
d7b2633d 1040 /* Don't reallocate page tables */
6ac18502 1041 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 1042 /* Scratch is never allocated this way */
d4ec9da0 1043 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 1044 continue;
1045 }
1046
8a1ebd74 1047 pt = alloc_pt(dev);
d7b2633d 1048 if (IS_ERR(pt))
5441f0cb
MT		 1049 goto unwind_out;
1050
d4ec9da0 1051 gen8_initialize_pt(vm, pt);
d7b2633d 1052 pd->page_table[pde] = pt;
966082c9 1053 __set_bit(pde, new_pts);
4c06ec8d 1054 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 1055 }
1056
bf2b4ed2 1057 return 0;
7ad47cf2
BW		 1058
1059unwind_out:
d7b2633d 1060 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 1061 free_pt(dev, pd->page_table[pde]);
7ad47cf2 1062
d7b3de91 1063 return -ENOMEM;
bf2b4ed2
BW		 1064}
1065
d7b2633d
MT		 1066/**
1067 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 1068 * @vm: Master vm structure.
d7b2633d
MT		 1069 * @pdp: Page directory pointer for this address range.
1070 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 1071 * @length: Size of the allocations.
1072 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 1073 * caller to free on error.
1074 *
1075 * Allocate the required number of page directories starting at the pde index of
1076 * @start, and ending at the pde index @start + @length. This function will skip
1077 * over already allocated page directories within the range, and only allocate
1078 * new ones, setting the appropriate pointer within the pdp as well as the
1079 * correct position in the bitmap @new_pds.
1080 *
1081 * The function will only allocate the pages within the range for a give page
1082 * directory pointer. In other words, if @start + @length straddles a virtually
1083 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1084 * required by the caller, This is not currently possible, and the BUG in the
1085 * code will prevent it.
1086 *
1087 * Return: 0 if success; negative error code otherwise.
1088 */
d4ec9da0
MT		 1089static int
1090gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1091 struct i915_page_directory_pointer *pdp,
1092 uint64_t start,
1093 uint64_t length,
1094 unsigned long *new_pds)
bf2b4ed2 1095{
d4ec9da0 1096 struct drm_device *dev = vm->dev;
d7b2633d 1097 struct i915_page_directory *pd;
69876bed 1098 uint32_t pdpe;
6ac18502 1099 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 1100
6ac18502 1101 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 1102
e8ebd8e2 1103 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
6ac18502 1104 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 1105 continue;
33c8819f 1106
8a1ebd74 1107 pd = alloc_pd(dev);
d7b2633d 1108 if (IS_ERR(pd))
d7b3de91 1109 goto unwind_out;
69876bed 1110
d4ec9da0 1111 gen8_initialize_pd(vm, pd);
d7b2633d 1112 pdp->page_directory[pdpe] = pd;
966082c9 1113 __set_bit(pdpe, new_pds);
4c06ec8d 1114 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 1115 }
1116
bf2b4ed2 1117 return 0;
d7b3de91
BW		 1118
1119unwind_out:
6ac18502 1120 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 1121 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 1122
1123 return -ENOMEM;
bf2b4ed2
BW		 1124}
1125
762d9936
MT		 1126/**
1127 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1128 * @vm: Master vm structure.
1129 * @pml4: Page map level 4 for this address range.
1130 * @start: Starting virtual address to begin allocations.
1131 * @length: Size of the allocations.
1132 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1133 * caller to free on error.
1134 *
1135 * Allocate the required number of page directory pointers. Extremely similar to
1136 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1137 * The main difference is here we are limited by the pml4 boundary (instead of
1138 * the page directory pointer).
1139 *
1140 * Return: 0 if success; negative error code otherwise.
1141 */
1142static int
1143gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1144 struct i915_pml4 *pml4,
1145 uint64_t start,
1146 uint64_t length,
1147 unsigned long *new_pdps)
1148{
1149 struct drm_device *dev = vm->dev;
1150 struct i915_page_directory_pointer *pdp;
762d9936
MT		 1151 uint32_t pml4e;
1152
1153 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1154
e8ebd8e2 1155 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1156 if (!test_bit(pml4e, pml4->used_pml4es)) {
1157 pdp = alloc_pdp(dev);
1158 if (IS_ERR(pdp))
1159 goto unwind_out;
1160
69ab76fd 1161 gen8_initialize_pdp(vm, pdp);
762d9936
MT		 1162 pml4->pdps[pml4e] = pdp;
1163 __set_bit(pml4e, new_pdps);
1164 trace_i915_page_directory_pointer_entry_alloc(vm,
1165 pml4e,
1166 start,
1167 GEN8_PML4E_SHIFT);
1168 }
1169 }
1170
1171 return 0;
1172
1173unwind_out:
1174 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1175 free_pdp(dev, pml4->pdps[pml4e]);
1176
1177 return -ENOMEM;
1178}
1179
d7b2633d 1180static void
3a41a05d 1181free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
d7b2633d 1182{
d7b2633d
MT		 1183 kfree(new_pts);
1184 kfree(new_pds);
1185}
1186
1187/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1188 * of these are based on the number of PDPEs in the system.
1189 */
1190static
1191int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
3a41a05d 1192 unsigned long **new_pts,
6ac18502 1193 uint32_t pdpes)
d7b2633d 1194{
d7b2633d 1195 unsigned long *pds;
3a41a05d 1196 unsigned long *pts;
d7b2633d 1197
3a41a05d 1198 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
d7b2633d
MT		 1199 if (!pds)
1200 return -ENOMEM;
1201
3a41a05d
MW		 1202 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1203 GFP_TEMPORARY);
1204 if (!pts)
1205 goto err_out;
d7b2633d
MT		 1206
1207 *new_pds = pds;
1208 *new_pts = pts;
1209
1210 return 0;
1211
1212err_out:
3a41a05d 1213 free_gen8_temp_bitmaps(pds, pts);
d7b2633d
MT		 1214 return -ENOMEM;
1215}
1216
5b7e4c9c
MK		 1217/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1218 * the page table structures, we mark them dirty so that
1219 * context switching/execlist queuing code takes extra steps
1220 * to ensure that tlbs are flushed.
1221 */
1222static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1223{
1224 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1225}
1226
762d9936
MT		 1227static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1228 struct i915_page_directory_pointer *pdp,
1229 uint64_t start,
1230 uint64_t length)
bf2b4ed2 1231{
e5716f55 1232 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3a41a05d 1233 unsigned long *new_page_dirs, *new_page_tables;
d4ec9da0 1234 struct drm_device *dev = vm->dev;
5441f0cb 1235 struct i915_page_directory *pd;
33c8819f
MT		 1236 const uint64_t orig_start = start;
1237 const uint64_t orig_length = length;
5441f0cb 1238 uint32_t pdpe;
d4ec9da0 1239 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 1240 int ret;
1241
d7b2633d
MT		 1242 /* Wrap is never okay since we can only represent 48b, and we don't
1243 * actually use the other side of the canonical address space.
1244 */
1245 if (WARN_ON(start + length < start))
a05d80ee
MK		 1246 return -ENODEV;
1247
d4ec9da0 1248 if (WARN_ON(start + length > vm->total))
a05d80ee 1249 return -ENODEV;
d7b2633d 1250
6ac18502 1251 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1252 if (ret)
1253 return ret;
1254
d7b2633d 1255 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1256 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1257 new_page_dirs);
d7b2633d 1258 if (ret) {
3a41a05d 1259 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
d7b2633d
MT		 1260 return ret;
1261 }
1262
1263 /* For every page directory referenced, allocate page tables */
e8ebd8e2 1264 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d4ec9da0 1265 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
3a41a05d 1266 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
5441f0cb
MT		 1267 if (ret)
1268 goto err_out;
5441f0cb
MT		 1269 }
1270
33c8819f
MT		 1271 start = orig_start;
1272 length = orig_length;
1273
d7b2633d
MT		 1274 /* Allocations have completed successfully, so set the bitmaps, and do
1275 * the mappings. */
e8ebd8e2 1276 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d1c54acd 1277 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1278 struct i915_page_table *pt;
09120d4e 1279 uint64_t pd_len = length;
33c8819f
MT		 1280 uint64_t pd_start = start;
1281 uint32_t pde;
1282
d7b2633d
MT		 1283 /* Every pd should be allocated, we just did that above. */
1284 WARN_ON(!pd);
1285
e8ebd8e2 1286 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
d7b2633d
MT		 1287 /* Same reasoning as pd */
1288 WARN_ON(!pt);
1289 WARN_ON(!pd_len);
1290 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1291
1292 /* Set our used ptes within the page table */
1293 bitmap_set(pt->used_ptes,
1294 gen8_pte_index(pd_start),
1295 gen8_pte_count(pd_start, pd_len));
1296
1297 /* Our pde is now pointing to the pagetable, pt */
966082c9 1298 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1299
1300 /* Map the PDE to the page table */
fe36f55d
MK		 1301 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1302 I915_CACHE_LLC);
4c06ec8d
MT		 1303 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1304 gen8_pte_index(start),
1305 gen8_pte_count(start, length),
1306 GEN8_PTES);
d7b2633d
MT		 1307
1308 /* NB: We haven't yet mapped ptes to pages. At this
1309 * point we're still relying on insert_entries() */
33c8819f 1310 }
d7b2633d 1311
d1c54acd 1312 kunmap_px(ppgtt, page_directory);
d4ec9da0 1313 __set_bit(pdpe, pdp->used_pdpes);
762d9936 1314 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
33c8819f
MT		 1315 }
1316
3a41a05d 1317 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1318 mark_tlbs_dirty(ppgtt);
d7b3de91 1319 return 0;
bf2b4ed2 1320
d7b3de91 1321err_out:
d7b2633d 1322 while (pdpe--) {
e8ebd8e2
DG		 1323 unsigned long temp;
1324
3a41a05d
MW		 1325 for_each_set_bit(temp, new_page_tables + pdpe *
1326 BITS_TO_LONGS(I915_PDES), I915_PDES)
d4ec9da0 1327 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1328 }
1329
6ac18502 1330 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1331 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1332
3a41a05d 1333 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1334 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1335 return ret;
1336}
1337
762d9936
MT		 1338static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1339 struct i915_pml4 *pml4,
1340 uint64_t start,
1341 uint64_t length)
1342{
1343 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
e5716f55 1344 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 1345 struct i915_page_directory_pointer *pdp;
e8ebd8e2 1346 uint64_t pml4e;
762d9936
MT		 1347 int ret = 0;
1348
1349 /* Do the pml4 allocations first, so we don't need to track the newly
1350 * allocated tables below the pdp */
1351 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1352
1353 /* The pagedirectory and pagetable allocations are done in the shared 3
1354 * and 4 level code. Just allocate the pdps.
1355 */
1356 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1357 new_pdps);
1358 if (ret)
1359 return ret;
1360
1361 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1362 "The allocation has spanned more than 512GB. "
1363 "It is highly likely this is incorrect.");
1364
e8ebd8e2 1365 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1366 WARN_ON(!pdp);
1367
1368 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1369 if (ret)
1370 goto err_out;
1371
1372 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1373 }
1374
1375 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1376 GEN8_PML4ES_PER_PML4);
1377
1378 return 0;
1379
1380err_out:
1381 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1382 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1383
1384 return ret;
1385}
1386
1387static int gen8_alloc_va_range(struct i915_address_space *vm,
1388 uint64_t start, uint64_t length)
1389{
e5716f55 1390 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936
MT		 1391
1392 if (USES_FULL_48BIT_PPGTT(vm->dev))
1393 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1394 else
1395 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1396}
1397
ea91e401
MT		 1398static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1399 uint64_t start, uint64_t length,
1400 gen8_pte_t scratch_pte,
1401 struct seq_file *m)
1402{
1403 struct i915_page_directory *pd;
ea91e401
MT		 1404 uint32_t pdpe;
1405
e8ebd8e2 1406 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
ea91e401
MT		 1407 struct i915_page_table *pt;
1408 uint64_t pd_len = length;
1409 uint64_t pd_start = start;
1410 uint32_t pde;
1411
1412 if (!test_bit(pdpe, pdp->used_pdpes))
1413 continue;
1414
1415 seq_printf(m, "\tPDPE #%d\n", pdpe);
e8ebd8e2 1416 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
ea91e401
MT		 1417 uint32_t pte;
1418 gen8_pte_t *pt_vaddr;
1419
1420 if (!test_bit(pde, pd->used_pdes))
1421 continue;
1422
1423 pt_vaddr = kmap_px(pt);
1424 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1425 uint64_t va =
1426 (pdpe << GEN8_PDPE_SHIFT) |
1427 (pde << GEN8_PDE_SHIFT) |
1428 (pte << GEN8_PTE_SHIFT);
1429 int i;
1430 bool found = false;
1431
1432 for (i = 0; i < 4; i++)
1433 if (pt_vaddr[pte + i] != scratch_pte)
1434 found = true;
1435 if (!found)
1436 continue;
1437
1438 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1439 for (i = 0; i < 4; i++) {
1440 if (pt_vaddr[pte + i] != scratch_pte)
1441 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1442 else
1443 seq_puts(m, " SCRATCH ");
1444 }
1445 seq_puts(m, "\n");
1446 }
1447 /* don't use kunmap_px, it could trigger
1448 * an unnecessary flush.
1449 */
1450 kunmap_atomic(pt_vaddr);
1451 }
1452 }
1453}
1454
1455static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1456{
1457 struct i915_address_space *vm = &ppgtt->base;
1458 uint64_t start = ppgtt->base.start;
1459 uint64_t length = ppgtt->base.total;
1460 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1461 I915_CACHE_LLC, true);
1462
1463 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1464 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1465 } else {
e8ebd8e2 1466 uint64_t pml4e;
ea91e401
MT		 1467 struct i915_pml4 *pml4 = &ppgtt->pml4;
1468 struct i915_page_directory_pointer *pdp;
1469
e8ebd8e2 1470 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
ea91e401
MT		 1471 if (!test_bit(pml4e, pml4->used_pml4es))
1472 continue;
1473
1474 seq_printf(m, " PML4E #%llu\n", pml4e);
1475 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1476 }
1477 }
1478}
1479
331f38e7
ZL		 1480static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1481{
3a41a05d 1482 unsigned long *new_page_dirs, *new_page_tables;
331f38e7
ZL		 1483 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1484 int ret;
1485
1486 /* We allocate temp bitmap for page tables for no gain
1487 * but as this is for init only, lets keep the things simple
1488 */
1489 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1490 if (ret)
1491 return ret;
1492
1493 /* Allocate for all pdps regardless of how the ppgtt
1494 * was defined.
1495 */
1496 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1497 0, 1ULL << 32,
1498 new_page_dirs);
1499 if (!ret)
1500 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1501
3a41a05d 1502 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
331f38e7
ZL		 1503
1504 return ret;
1505}
1506
eb0b44ad 1507/*
f3a964b9
BW		 1508 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1509 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1510 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1511 * space.
37aca44a 1512 *
f3a964b9 1513 */
5c5f6457 1514static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1515{
8776f02b 1516 int ret;
7cb6d7ac 1517
8776f02b
MK		 1518 ret = gen8_init_scratch(&ppgtt->base);
1519 if (ret)
1520 return ret;
69876bed 1521
d7b2633d 1522 ppgtt->base.start = 0;
d7b2633d 1523 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1524 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1525 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1526 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1527 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1528 ppgtt->base.bind_vma = ppgtt_bind_vma;
ea91e401 1529 ppgtt->debug_dump = gen8_dump_ppgtt;
d7b2633d 1530
762d9936
MT		 1531 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1532 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1533 if (ret)
1534 goto free_scratch;
6ac18502 1535
69ab76fd
MT		 1536 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1537
762d9936 1538 ppgtt->base.total = 1ULL << 48;
2dba3239 1539 ppgtt->switch_mm = gen8_48b_mm_switch;
762d9936 1540 } else {
25f50337 1541 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
81ba8aef
MT		 1542 if (ret)
1543 goto free_scratch;
1544
1545 ppgtt->base.total = 1ULL << 32;
2dba3239 1546 ppgtt->switch_mm = gen8_legacy_mm_switch;
762d9936
MT		 1547 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1548 0, 0,
1549 GEN8_PML4E_SHIFT);
331f38e7 1550
c033666a 1551 if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
331f38e7
ZL		 1552 ret = gen8_preallocate_top_level_pdps(ppgtt);
1553 if (ret)
1554 goto free_scratch;
1555 }
81ba8aef 1556 }
6ac18502 1557
c033666a 1558 if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
650da34c
ZL		 1559 gen8_ppgtt_notify_vgt(ppgtt, true);
1560
d7b2633d 1561 return 0;
6ac18502
MT		 1562
1563free_scratch:
1564 gen8_free_scratch(&ppgtt->base);
1565 return ret;
d7b2633d
MT		 1566}
1567
87d60b63
BW		 1568static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1569{
87d60b63 1570 struct i915_address_space *vm = &ppgtt->base;
09942c65 1571 struct i915_page_table *unused;
07749ef3 1572 gen6_pte_t scratch_pte;
87d60b63 1573 uint32_t pd_entry;
731f74c5 1574 uint32_t pte, pde;
09942c65 1575 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1576
79ab9370
MK		 1577 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1578 I915_CACHE_LLC, true, 0);
87d60b63 1579
731f74c5 1580 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
87d60b63 1581 u32 expected;
07749ef3 1582 gen6_pte_t *pt_vaddr;
567047be 1583 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1584 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1585 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1586
1587 if (pd_entry != expected)
1588 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1589 pde,
1590 pd_entry,
1591 expected);
1592 seq_printf(m, "\tPDE: %x\n", pd_entry);
1593
d1c54acd
MK		 1594 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1595
07749ef3 1596 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1597 unsigned long va =
07749ef3 1598 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1599 (pte * PAGE_SIZE);
1600 int i;
1601 bool found = false;
1602 for (i = 0; i < 4; i++)
1603 if (pt_vaddr[pte + i] != scratch_pte)
1604 found = true;
1605 if (!found)
1606 continue;
1607
1608 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1609 for (i = 0; i < 4; i++) {
1610 if (pt_vaddr[pte + i] != scratch_pte)
1611 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1612 else
1613 seq_puts(m, " SCRATCH ");
1614 }
1615 seq_puts(m, "\n");
1616 }
d1c54acd 1617 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1618 }
1619}
1620
678d96fb 1621/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1622static void gen6_write_pde(struct i915_page_directory *pd,
1623 const int pde, struct i915_page_table *pt)
6197349b 1624{
678d96fb
BW		 1625 /* Caller needs to make sure the write completes if necessary */
1626 struct i915_hw_ppgtt *ppgtt =
1627 container_of(pd, struct i915_hw_ppgtt, pd);
1628 u32 pd_entry;
6197349b 1629
567047be 1630 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1631 pd_entry |= GEN6_PDE_VALID;
6197349b 1632
678d96fb
BW		 1633 writel(pd_entry, ppgtt->pd_addr + pde);
1634}
6197349b 1635
678d96fb
BW		 1636/* Write all the page tables found in the ppgtt structure to incrementing page
1637 * directories. */
1638static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1639 struct i915_page_directory *pd,
678d96fb
BW		 1640 uint32_t start, uint32_t length)
1641{
72e96d64 1642 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ec565b3c 1643 struct i915_page_table *pt;
731f74c5 1644 uint32_t pde;
678d96fb 1645
731f74c5 1646 gen6_for_each_pde(pt, pd, start, length, pde)
678d96fb
BW		 1647 gen6_write_pde(pd, pde, pt);
1648
1649 /* Make sure write is complete before other code can use this page
1650 * table. Also require for WC mapped PTEs */
72e96d64 1651 readl(ggtt->gsm);
3e302542
BW		 1652}
1653
b4a74e3a 1654static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1655{
44159ddb 1656 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1657
44159ddb 1658 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1659}
1660
90252e5c 1661static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1662 struct drm_i915_gem_request *req)
90252e5c 1663{
7e37f889 1664 struct intel_ring *ring = req->ring;
4a570db5 1665 struct intel_engine_cs *engine = req->engine;
90252e5c
BW		 1666 int ret;
1667
90252e5c 1668 /* NB: TLBs must be flushed and invalidated before a switch */
7c9cf4e3 1669 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
90252e5c
BW		 1670 if (ret)
1671 return ret;
1672
5fb9de1a 1673 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1674 if (ret)
1675 return ret;
1676
b5321f30
CW		 1677 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1678 intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
1679 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1680 intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
1681 intel_ring_emit(ring, get_pd_offset(ppgtt));
1682 intel_ring_emit(ring, MI_NOOP);
1683 intel_ring_advance(ring);
90252e5c
BW		 1684
1685 return 0;
1686}
1687
48a10389 1688static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1689 struct drm_i915_gem_request *req)
48a10389 1690{
7e37f889 1691 struct intel_ring *ring = req->ring;
4a570db5 1692 struct intel_engine_cs *engine = req->engine;
48a10389
BW		 1693 int ret;
1694
48a10389 1695 /* NB: TLBs must be flushed and invalidated before a switch */
7c9cf4e3 1696 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
48a10389
BW		 1697 if (ret)
1698 return ret;
1699
5fb9de1a 1700 ret = intel_ring_begin(req, 6);
48a10389
BW		 1701 if (ret)
1702 return ret;
1703
b5321f30
CW		 1704 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1705 intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));
1706 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1707 intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));
1708 intel_ring_emit(ring, get_pd_offset(ppgtt));
1709 intel_ring_emit(ring, MI_NOOP);
1710 intel_ring_advance(ring);
48a10389 1711
90252e5c 1712 /* XXX: RCS is the only one to auto invalidate the TLBs? */
e2f80391 1713 if (engine->id != RCS) {
7c9cf4e3 1714 ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
90252e5c
BW		 1715 if (ret)
1716 return ret;
1717 }
1718
48a10389
BW		 1719 return 0;
1720}
1721
eeb9488e 1722static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1723 struct drm_i915_gem_request *req)
eeb9488e 1724{
4a570db5 1725 struct intel_engine_cs *engine = req->engine;
8eb95204 1726 struct drm_i915_private *dev_priv = req->i915;
48a10389 1727
e2f80391
TU		 1728 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1729 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
eeb9488e
BW		 1730 return 0;
1731}
1732
82460d97 1733static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1734{
fac5e23e 1735 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1736 struct intel_engine_cs *engine;
3e302542 1737
b4ac5afc 1738 for_each_engine(engine, dev_priv) {
2dba3239 1739 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
e2f80391 1740 I915_WRITE(RING_MODE_GEN7(engine),
2dba3239 1741 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
eeb9488e 1742 }
eeb9488e 1743}
6197349b 1744
82460d97 1745static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1746{
fac5e23e 1747 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1748 struct intel_engine_cs *engine;
b4a74e3a 1749 uint32_t ecochk, ecobits;
6197349b 1750
b4a74e3a
BW		 1751 ecobits = I915_READ(GAC_ECO_BITS);
1752 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1753
b4a74e3a
BW		 1754 ecochk = I915_READ(GAM_ECOCHK);
1755 if (IS_HASWELL(dev)) {
1756 ecochk |= ECOCHK_PPGTT_WB_HSW;
1757 } else {
1758 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1759 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1760 }
1761 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1762
b4ac5afc 1763 for_each_engine(engine, dev_priv) {
6197349b 1764 /* GFX_MODE is per-ring on gen7+ */
e2f80391 1765 I915_WRITE(RING_MODE_GEN7(engine),
b4a74e3a 1766 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1767 }
b4a74e3a 1768}
6197349b 1769
82460d97 1770static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1771{
fac5e23e 1772 struct drm_i915_private *dev_priv = to_i915(dev);
b4a74e3a 1773 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1774
b4a74e3a
BW		 1775 ecobits = I915_READ(GAC_ECO_BITS);
1776 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1777 ECOBITS_PPGTT_CACHE64B);
6197349b 1778
b4a74e3a
BW		 1779 gab_ctl = I915_READ(GAB_CTL);
1780 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1781
1782 ecochk = I915_READ(GAM_ECOCHK);
1783 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1784
1785 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1786}
1787
1d2a314c 1788/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1789static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1790 uint64_t start,
1791 uint64_t length,
828c7908 1792 bool use_scratch)
1d2a314c 1793{
e5716f55 1794 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 1795 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1796 unsigned first_entry = start >> PAGE_SHIFT;
1797 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1798 unsigned act_pt = first_entry / GEN6_PTES;
1799 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1800 unsigned last_pte, i;
1d2a314c 1801
c114f76a
MK		 1802 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1803 I915_CACHE_LLC, true, 0);
1d2a314c 1804
7bddb01f
DV		 1805 while (num_entries) {
1806 last_pte = first_pte + num_entries;
07749ef3
MT		 1807 if (last_pte > GEN6_PTES)
1808 last_pte = GEN6_PTES;
7bddb01f 1809
d1c54acd 1810 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1811
7bddb01f
DV		 1812 for (i = first_pte; i < last_pte; i++)
1813 pt_vaddr[i] = scratch_pte;
1d2a314c 1814
d1c54acd 1815 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1816
7bddb01f
DV		 1817 num_entries -= last_pte - first_pte;
1818 first_pte = 0;
a15326a5 1819 act_pt++;
7bddb01f 1820 }
1d2a314c
DV		 1821}
1822
853ba5d2 1823static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1824 struct sg_table *pages,
782f1495 1825 uint64_t start,
24f3a8cf 1826 enum i915_cache_level cache_level, u32 flags)
def886c3 1827{
e5716f55 1828 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
782f1495 1829 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1830 unsigned act_pt = first_entry / GEN6_PTES;
1831 unsigned act_pte = first_entry % GEN6_PTES;
85d1225e
DG		 1832 gen6_pte_t *pt_vaddr = NULL;
1833 struct sgt_iter sgt_iter;
1834 dma_addr_t addr;
6e995e23 1835
85d1225e 1836 for_each_sgt_dma(addr, sgt_iter, pages) {
cc79714f 1837 if (pt_vaddr == NULL)
d1c54acd 1838 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1839
cc79714f 1840 pt_vaddr[act_pte] =
85d1225e 1841 vm->pte_encode(addr, cache_level, true, flags);
24f3a8cf 1842
07749ef3 1843 if (++act_pte == GEN6_PTES) {
d1c54acd 1844 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1845 pt_vaddr = NULL;
a15326a5 1846 act_pt++;
6e995e23 1847 act_pte = 0;
def886c3 1848 }
def886c3 1849 }
85d1225e 1850
cc79714f 1851 if (pt_vaddr)
d1c54acd 1852 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1853}
1854
678d96fb 1855static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1856 uint64_t start_in, uint64_t length_in)
678d96fb 1857{
4933d519
MT		 1858 DECLARE_BITMAP(new_page_tables, I915_PDES);
1859 struct drm_device *dev = vm->dev;
72e96d64
JL		 1860 struct drm_i915_private *dev_priv = to_i915(dev);
1861 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e5716f55 1862 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
ec565b3c 1863 struct i915_page_table *pt;
a05d80ee 1864 uint32_t start, length, start_save, length_save;
731f74c5 1865 uint32_t pde;
4933d519
MT		 1866 int ret;
1867
a05d80ee
MK		 1868 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1869 return -ENODEV;
1870
1871 start = start_save = start_in;
1872 length = length_save = length_in;
4933d519
MT		 1873
1874 bitmap_zero(new_page_tables, I915_PDES);
1875
1876 /* The allocation is done in two stages so that we can bail out with
1877 * minimal amount of pain. The first stage finds new page tables that
1878 * need allocation. The second stage marks use ptes within the page
1879 * tables.
1880 */
731f74c5 1881 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
79ab9370 1882 if (pt != vm->scratch_pt) {
4933d519
MT		 1883 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1884 continue;
1885 }
1886
1887 /* We've already allocated a page table */
1888 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1889
8a1ebd74 1890 pt = alloc_pt(dev);
4933d519
MT		 1891 if (IS_ERR(pt)) {
1892 ret = PTR_ERR(pt);
1893 goto unwind_out;
1894 }
1895
1896 gen6_initialize_pt(vm, pt);
1897
1898 ppgtt->pd.page_table[pde] = pt;
966082c9 1899 __set_bit(pde, new_page_tables);
72744cb1 1900 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1901 }
1902
1903 start = start_save;
1904 length = length_save;
678d96fb 1905
731f74c5 1906 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
678d96fb
BW		 1907 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1908
1909 bitmap_zero(tmp_bitmap, GEN6_PTES);
1910 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1911 gen6_pte_count(start, length));
1912
966082c9 1913 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1914 gen6_write_pde(&ppgtt->pd, pde, pt);
1915
72744cb1
MT		 1916 trace_i915_page_table_entry_map(vm, pde, pt,
1917 gen6_pte_index(start),
1918 gen6_pte_count(start, length),
1919 GEN6_PTES);
4933d519 1920 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1921 GEN6_PTES);
1922 }
1923
4933d519
MT		 1924 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1925
1926 /* Make sure write is complete before other code can use this page
1927 * table. Also require for WC mapped PTEs */
72e96d64 1928 readl(ggtt->gsm);
4933d519 1929
563222a7 1930 mark_tlbs_dirty(ppgtt);
678d96fb 1931 return 0;
4933d519
MT		 1932
1933unwind_out:
1934 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1935 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1936
79ab9370 1937 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1938 free_pt(vm->dev, pt);
4933d519
MT		 1939 }
1940
1941 mark_tlbs_dirty(ppgtt);
1942 return ret;
678d96fb
BW		 1943}
1944
8776f02b
MK		 1945static int gen6_init_scratch(struct i915_address_space *vm)
1946{
1947 struct drm_device *dev = vm->dev;
1948
1949 vm->scratch_page = alloc_scratch_page(dev);
1950 if (IS_ERR(vm->scratch_page))
1951 return PTR_ERR(vm->scratch_page);
1952
1953 vm->scratch_pt = alloc_pt(dev);
1954 if (IS_ERR(vm->scratch_pt)) {
1955 free_scratch_page(dev, vm->scratch_page);
1956 return PTR_ERR(vm->scratch_pt);
1957 }
1958
1959 gen6_initialize_pt(vm, vm->scratch_pt);
1960
1961 return 0;
1962}
1963
1964static void gen6_free_scratch(struct i915_address_space *vm)
1965{
1966 struct drm_device *dev = vm->dev;
1967
1968 free_pt(dev, vm->scratch_pt);
1969 free_scratch_page(dev, vm->scratch_page);
1970}
1971
061dd493 1972static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1973{
e5716f55 1974 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
731f74c5
DG		 1975 struct i915_page_directory *pd = &ppgtt->pd;
1976 struct drm_device *dev = vm->dev;
09942c65
MT		 1977 struct i915_page_table *pt;
1978 uint32_t pde;
4933d519 1979
061dd493
DV		 1980 drm_mm_remove_node(&ppgtt->node);
1981
731f74c5 1982 gen6_for_all_pdes(pt, pd, pde)
79ab9370 1983 if (pt != vm->scratch_pt)
731f74c5 1984 free_pt(dev, pt);
06fda602 1985
8776f02b 1986 gen6_free_scratch(vm);
3440d265
DV		 1987}
1988
b146520f 1989static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1990{
8776f02b 1991 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1992 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 1993 struct drm_i915_private *dev_priv = to_i915(dev);
1994 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e3cc1995 1995 bool retried = false;
b146520f 1996 int ret;
1d2a314c 1997
c8d4c0d6
BW		 1998 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1999 * allocator works in address space sizes, so it's multiplied by page
2000 * size. We allocate at the top of the GTT to avoid fragmentation.
2001 */
72e96d64 2002 BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
4933d519 2003
8776f02b
MK		 2004 ret = gen6_init_scratch(vm);
2005 if (ret)
2006 return ret;
4933d519 2007
e3cc1995 2008alloc:
72e96d64 2009 ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
c8d4c0d6
BW		 2010 &ppgtt->node, GEN6_PD_SIZE,
2011 GEN6_PD_ALIGN, 0,
72e96d64 2012 0, ggtt->base.total,
3e8b5ae9 2013 DRM_MM_TOPDOWN);
e3cc1995 2014 if (ret == -ENOSPC && !retried) {
e522ac23 2015 ret = i915_gem_evict_something(&ggtt->base,
e3cc1995 2016 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c 2017 I915_CACHE_NONE,
72e96d64 2018 0, ggtt->base.total,
d23db88c 2019 0);
e3cc1995 2020 if (ret)
678d96fb 2021 goto err_out;
e3cc1995
BW		 2022
2023 retried = true;
2024 goto alloc;
2025 }
c8d4c0d6 2026
c8c26622 2027 if (ret)
678d96fb
BW		 2028 goto err_out;
2029
c8c26622 2030
72e96d64 2031 if (ppgtt->node.start < ggtt->mappable_end)
c8d4c0d6 2032 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 2033
c8c26622 2034 return 0;
678d96fb
BW		 2035
2036err_out:
8776f02b 2037 gen6_free_scratch(vm);
678d96fb 2038 return ret;
b146520f
BW		 2039}
2040
b146520f
BW		 2041static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2042{
2f2cf682 2043 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 2044}
06dc68d6 2045
4933d519
MT		 2046static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2047 uint64_t start, uint64_t length)
2048{
ec565b3c 2049 struct i915_page_table *unused;
731f74c5 2050 uint32_t pde;
1d2a314c 2051
731f74c5 2052 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
79ab9370 2053 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 2054}
2055
5c5f6457 2056static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 2057{
2058 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 2059 struct drm_i915_private *dev_priv = to_i915(dev);
2060 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b146520f
BW		 2061 int ret;
2062
72e96d64 2063 ppgtt->base.pte_encode = ggtt->base.pte_encode;
8eb95204 2064 if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
b146520f 2065 ppgtt->switch_mm = gen6_mm_switch;
8eb95204 2066 else if (IS_HASWELL(dev))
b146520f 2067 ppgtt->switch_mm = hsw_mm_switch;
8eb95204 2068 else if (IS_GEN7(dev))
b146520f 2069 ppgtt->switch_mm = gen7_mm_switch;
8eb95204 2070 else
b146520f
BW		 2071 BUG();
2072
2073 ret = gen6_ppgtt_alloc(ppgtt);
2074 if (ret)
2075 return ret;
2076
5c5f6457 2077 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 2078 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2079 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 2080 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2081 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 2082 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 2083 ppgtt->base.start = 0;
09942c65 2084 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 2085 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 2086
44159ddb 2087 ppgtt->pd.base.ggtt_offset =
07749ef3 2088 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 2089
72e96d64 2090 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
44159ddb 2091 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 2092
5c5f6457 2093 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 2094
678d96fb
BW		 2095 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2096
440fd528 2097 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 2098 ppgtt->node.size >> 20,
2099 ppgtt->node.start / PAGE_SIZE);
3440d265 2100
fa76da34 2101 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 2102 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 2103
b146520f 2104 return 0;
3440d265
DV		 2105}
2106
2bfa996e
CW		 2107static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
2108 struct drm_i915_private *dev_priv)
3440d265 2109{
2bfa996e 2110 ppgtt->base.dev = &dev_priv->drm;
3440d265 2111
2bfa996e 2112 if (INTEL_INFO(dev_priv)->gen < 8)
5c5f6457 2113 return gen6_ppgtt_init(ppgtt);
3ed124b2 2114 else
d7b2633d 2115 return gen8_ppgtt_init(ppgtt);
fa76da34 2116}
c114f76a 2117
a2cad9df
MW		 2118static void i915_address_space_init(struct i915_address_space *vm,
2119 struct drm_i915_private *dev_priv)
2120{
2121 drm_mm_init(&vm->mm, vm->start, vm->total);
a2cad9df
MW		 2122 INIT_LIST_HEAD(&vm->active_list);
2123 INIT_LIST_HEAD(&vm->inactive_list);
50e046b6 2124 INIT_LIST_HEAD(&vm->unbound_list);
a2cad9df
MW		 2125 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2126}
2127
d5165ebd
TG		 2128static void gtt_write_workarounds(struct drm_device *dev)
2129{
fac5e23e 2130 struct drm_i915_private *dev_priv = to_i915(dev);
d5165ebd
TG		 2131
2132 /* This function is for gtt related workarounds. This function is
2133 * called on driver load and after a GPU reset, so you can place
2134 * workarounds here even if they get overwritten by GPU reset.
2135 */
2136 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2137 if (IS_BROADWELL(dev))
2138 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2139 else if (IS_CHERRYVIEW(dev))
2140 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2141 else if (IS_SKYLAKE(dev))
2142 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2143 else if (IS_BROXTON(dev))
2144 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2145}
2146
2bfa996e
CW		 2147static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
2148 struct drm_i915_private *dev_priv,
2149 struct drm_i915_file_private *file_priv)
fa76da34 2150{
2bfa996e 2151 int ret;
3ed124b2 2152
2bfa996e 2153 ret = __hw_ppgtt_init(ppgtt, dev_priv);
fa76da34 2154 if (ret == 0) {
c7c48dfd 2155 kref_init(&ppgtt->ref);
a2cad9df 2156 i915_address_space_init(&ppgtt->base, dev_priv);
2bfa996e 2157 ppgtt->base.file = file_priv;
93bd8649 2158 }
1d2a314c
DV		 2159
2160 return ret;
2161}
2162
82460d97
DV		 2163int i915_ppgtt_init_hw(struct drm_device *dev)
2164{
d5165ebd
TG		 2165 gtt_write_workarounds(dev);
2166
671b5013
TD		 2167 /* In the case of execlists, PPGTT is enabled by the context descriptor
2168 * and the PDPs are contained within the context itself. We don't
2169 * need to do anything here. */
2170 if (i915.enable_execlists)
2171 return 0;
2172
82460d97
DV		 2173 if (!USES_PPGTT(dev))
2174 return 0;
2175
2176 if (IS_GEN6(dev))
2177 gen6_ppgtt_enable(dev);
2178 else if (IS_GEN7(dev))
2179 gen7_ppgtt_enable(dev);
2180 else if (INTEL_INFO(dev)->gen >= 8)
2181 gen8_ppgtt_enable(dev);
2182 else
5f77eeb0 2183 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 2184
4ad2fd88
JH		 2185 return 0;
2186}
1d2a314c 2187
4d884705 2188struct i915_hw_ppgtt *
2bfa996e
CW		 2189i915_ppgtt_create(struct drm_i915_private *dev_priv,
2190 struct drm_i915_file_private *fpriv)
4d884705
DV		 2191{
2192 struct i915_hw_ppgtt *ppgtt;
2193 int ret;
2194
2195 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2196 if (!ppgtt)
2197 return ERR_PTR(-ENOMEM);
2198
2bfa996e 2199 ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv);
4d884705
DV		 2200 if (ret) {
2201 kfree(ppgtt);
2202 return ERR_PTR(ret);
2203 }
2204
198c974d
DCS		 2205 trace_i915_ppgtt_create(&ppgtt->base);
2206
4d884705
DV		 2207 return ppgtt;
2208}
2209
ee960be7
DV		 2210void i915_ppgtt_release(struct kref *kref)
2211{
2212 struct i915_hw_ppgtt *ppgtt =
2213 container_of(kref, struct i915_hw_ppgtt, ref);
2214
198c974d
DCS		 2215 trace_i915_ppgtt_release(&ppgtt->base);
2216
50e046b6 2217 /* vmas should already be unbound and destroyed */
ee960be7
DV		 2218 WARN_ON(!list_empty(&ppgtt->base.active_list));
2219 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
50e046b6 2220 WARN_ON(!list_empty(&ppgtt->base.unbound_list));
ee960be7 2221
19dd120c
DV		 2222 list_del(&ppgtt->base.global_link);
2223 drm_mm_takedown(&ppgtt->base.mm);
2224
ee960be7
DV		 2225 ppgtt->base.cleanup(&ppgtt->base);
2226 kfree(ppgtt);
2227}
1d2a314c 2228
a81cc00c
BW		 2229/* Certain Gen5 chipsets require require idling the GPU before
2230 * unmapping anything from the GTT when VT-d is enabled.
2231 */
97d6d7ab 2232static bool needs_idle_maps(struct drm_i915_private *dev_priv)
a81cc00c
BW		 2233{
2234#ifdef CONFIG_INTEL_IOMMU
2235 /* Query intel_iommu to see if we need the workaround. Presumably that
2236 * was loaded first.
2237 */
97d6d7ab 2238 if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped)
a81cc00c
BW		 2239 return true;
2240#endif
2241 return false;
2242}
2243
dc97997a 2244void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
828c7908 2245{
e2f80391 2246 struct intel_engine_cs *engine;
828c7908 2247
dc97997a 2248 if (INTEL_INFO(dev_priv)->gen < 6)
828c7908
BW		 2249 return;
2250
b4ac5afc 2251 for_each_engine(engine, dev_priv) {
828c7908 2252 u32 fault_reg;
e2f80391 2253 fault_reg = I915_READ(RING_FAULT_REG(engine));
828c7908
BW		 2254 if (fault_reg & RING_FAULT_VALID) {
2255 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 2256 "\tAddr: 0x%08lx\n"
828c7908
BW		 2257 "\tAddress space: %s\n"
2258 "\tSource ID: %d\n"
2259 "\tType: %d\n",
2260 fault_reg & PAGE_MASK,
2261 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2262 RING_FAULT_SRCID(fault_reg),
2263 RING_FAULT_FAULT_TYPE(fault_reg));
e2f80391 2264 I915_WRITE(RING_FAULT_REG(engine),
828c7908
BW		 2265 fault_reg & ~RING_FAULT_VALID);
2266 }
2267 }
4a570db5 2268 POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
828c7908
BW		 2269}
2270
91e56499
CW		 2271static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2272{
2d1fe073 2273 if (INTEL_INFO(dev_priv)->gen < 6) {
91e56499
CW		 2274 intel_gtt_chipset_flush();
2275 } else {
2276 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2277 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2278 }
2279}
2280
828c7908
BW		 2281void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2282{
72e96d64
JL		 2283 struct drm_i915_private *dev_priv = to_i915(dev);
2284 struct i915_ggtt *ggtt = &dev_priv->ggtt;
828c7908
BW		 2285
2286 /* Don't bother messing with faults pre GEN6 as we have little
2287 * documentation supporting that it's a good idea.
2288 */
2289 if (INTEL_INFO(dev)->gen < 6)
2290 return;
2291
dc97997a 2292 i915_check_and_clear_faults(dev_priv);
828c7908 2293
72e96d64
JL		 2294 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2295 true);
91e56499
CW		 2296
2297 i915_ggtt_flush(dev_priv);
828c7908
BW		 2298}
2299
74163907 2300int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2301{
9da3da66
CW		 2302 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2303 obj->pages->sgl, obj->pages->nents,
2304 PCI_DMA_BIDIRECTIONAL))
2305 return -ENOSPC;
2306
2307 return 0;
7c2e6fdf
DV		 2308}
2309
2c642b07 2310static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 2311{
2312#ifdef writeq
2313 writeq(pte, addr);
2314#else
2315 iowrite32((u32)pte, addr);
2316 iowrite32(pte >> 32, addr + 4);
2317#endif
2318}
2319
d6473f56
CW		 2320static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2321 dma_addr_t addr,
2322 uint64_t offset,
2323 enum i915_cache_level level,
2324 u32 unused)
2325{
2326 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2327 gen8_pte_t __iomem *pte =
2328 (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
2329 (offset >> PAGE_SHIFT);
2330 int rpm_atomic_seq;
2331
2332 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2333
2334 gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
2335
2336 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2337 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2338
2339 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2340}
2341
94ec8f61
BW		 2342static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2343 struct sg_table *st,
782f1495 2344 uint64_t start,
24f3a8cf 2345 enum i915_cache_level level, u32 unused)
94ec8f61 2346{
72e96d64 2347 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2348 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
85d1225e
DG		 2349 struct sgt_iter sgt_iter;
2350 gen8_pte_t __iomem *gtt_entries;
2351 gen8_pte_t gtt_entry;
2352 dma_addr_t addr;
be69459a 2353 int rpm_atomic_seq;
85d1225e 2354 int i = 0;
be69459a
ID		 2355
2356 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61 2357
85d1225e
DG		 2358 gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2359
2360 for_each_sgt_dma(addr, sgt_iter, st) {
2361 gtt_entry = gen8_pte_encode(addr, level, true);
2362 gen8_set_pte(&gtt_entries[i++], gtt_entry);
94ec8f61
BW		 2363 }
2364
2365 /*
2366 * XXX: This serves as a posting read to make sure that the PTE has
2367 * actually been updated. There is some concern that even though
2368 * registers and PTEs are within the same BAR that they are potentially
2369 * of NUMA access patterns. Therefore, even with the way we assume
2370 * hardware should work, we must keep this posting read for paranoia.
2371 */
2372 if (i != 0)
85d1225e 2373 WARN_ON(readq(&gtt_entries[i-1]) != gtt_entry);
94ec8f61 2374
94ec8f61
BW		 2375 /* This next bit makes the above posting read even more important. We
2376 * want to flush the TLBs only after we're certain all the PTE updates
2377 * have finished.
2378 */
2379 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2380 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2381
2382 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2383}
2384
c140330b
CW		 2385struct insert_entries {
2386 struct i915_address_space *vm;
2387 struct sg_table *st;
2388 uint64_t start;
2389 enum i915_cache_level level;
2390 u32 flags;
2391};
2392
2393static int gen8_ggtt_insert_entries__cb(void *_arg)
2394{
2395 struct insert_entries *arg = _arg;
2396 gen8_ggtt_insert_entries(arg->vm, arg->st,
2397 arg->start, arg->level, arg->flags);
2398 return 0;
2399}
2400
2401static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2402 struct sg_table *st,
2403 uint64_t start,
2404 enum i915_cache_level level,
2405 u32 flags)
2406{
2407 struct insert_entries arg = { vm, st, start, level, flags };
2408 stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2409}
2410
d6473f56
CW		 2411static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2412 dma_addr_t addr,
2413 uint64_t offset,
2414 enum i915_cache_level level,
2415 u32 flags)
2416{
2417 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2418 gen6_pte_t __iomem *pte =
2419 (gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
2420 (offset >> PAGE_SHIFT);
2421 int rpm_atomic_seq;
2422
2423 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2424
2425 iowrite32(vm->pte_encode(addr, level, true, flags), pte);
2426
2427 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2428 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2429
2430 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2431}
2432
e76e9aeb
BW		 2433/*
2434 * Binds an object into the global gtt with the specified cache level. The object
2435 * will be accessible to the GPU via commands whose operands reference offsets
2436 * within the global GTT as well as accessible by the GPU through the GMADR
2437 * mapped BAR (dev_priv->mm.gtt->gtt).
2438 */
853ba5d2 2439static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 2440 struct sg_table *st,
782f1495 2441 uint64_t start,
24f3a8cf 2442 enum i915_cache_level level, u32 flags)
e76e9aeb 2443{
72e96d64 2444 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2445 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
85d1225e
DG		 2446 struct sgt_iter sgt_iter;
2447 gen6_pte_t __iomem *gtt_entries;
2448 gen6_pte_t gtt_entry;
2449 dma_addr_t addr;
be69459a 2450 int rpm_atomic_seq;
85d1225e 2451 int i = 0;
be69459a
ID		 2452
2453 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
e76e9aeb 2454
85d1225e
DG		 2455 gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2456
2457 for_each_sgt_dma(addr, sgt_iter, st) {
2458 gtt_entry = vm->pte_encode(addr, level, true, flags);
2459 iowrite32(gtt_entry, &gtt_entries[i++]);
e76e9aeb
BW		 2460 }
2461
e76e9aeb
BW		 2462 /* XXX: This serves as a posting read to make sure that the PTE has
2463 * actually been updated. There is some concern that even though
2464 * registers and PTEs are within the same BAR that they are potentially
2465 * of NUMA access patterns. Therefore, even with the way we assume
2466 * hardware should work, we must keep this posting read for paranoia.
2467 */
85d1225e
DG		 2468 if (i != 0)
2469 WARN_ON(readl(&gtt_entries[i-1]) != gtt_entry);
0f9b91c7
BW		 2470
2471 /* This next bit makes the above posting read even more important. We
2472 * want to flush the TLBs only after we're certain all the PTE updates
2473 * have finished.
2474 */
2475 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2476 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2477
2478 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
e76e9aeb
BW		 2479}
2480
f7770bfd
CW		 2481static void nop_clear_range(struct i915_address_space *vm,
2482 uint64_t start,
2483 uint64_t length,
2484 bool use_scratch)
2485{
2486}
2487
94ec8f61 2488static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2489 uint64_t start,
2490 uint64_t length,
94ec8f61
BW		 2491 bool use_scratch)
2492{
72e96d64 2493 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2494 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
782f1495
BW		 2495 unsigned first_entry = start >> PAGE_SHIFT;
2496 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2497 gen8_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2498 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2499 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
94ec8f61 2500 int i;
be69459a
ID		 2501 int rpm_atomic_seq;
2502
2503 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2504
2505 if (WARN(num_entries > max_entries,
2506 "First entry = %d; Num entries = %d (max=%d)\n",
2507 first_entry, num_entries, max_entries))
2508 num_entries = max_entries;
2509
c114f76a 2510 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2511 I915_CACHE_LLC,
2512 use_scratch);
2513 for (i = 0; i < num_entries; i++)
2514 gen8_set_pte(&gtt_base[i], scratch_pte);
2515 readl(gtt_base);
be69459a
ID		 2516
2517 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2518}
2519
853ba5d2 2520static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2521 uint64_t start,
2522 uint64_t length,
828c7908 2523 bool use_scratch)
7faf1ab2 2524{
72e96d64 2525 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2526 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
782f1495
BW		 2527 unsigned first_entry = start >> PAGE_SHIFT;
2528 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2529 gen6_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2530 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2531 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
7faf1ab2 2532 int i;
be69459a
ID		 2533 int rpm_atomic_seq;
2534
2535 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2
DV		 2536
2537 if (WARN(num_entries > max_entries,
2538 "First entry = %d; Num entries = %d (max=%d)\n",
2539 first_entry, num_entries, max_entries))
2540 num_entries = max_entries;
2541
c114f76a
MK		 2542 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2543 I915_CACHE_LLC, use_scratch, 0);
828c7908 2544
7faf1ab2
DV		 2545 for (i = 0; i < num_entries; i++)
2546 iowrite32(scratch_pte, &gtt_base[i]);
2547 readl(gtt_base);
be69459a
ID		 2548
2549 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2550}
2551
d6473f56
CW		 2552static void i915_ggtt_insert_page(struct i915_address_space *vm,
2553 dma_addr_t addr,
2554 uint64_t offset,
2555 enum i915_cache_level cache_level,
2556 u32 unused)
2557{
2558 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2559 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2560 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2561 int rpm_atomic_seq;
2562
2563 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2564
2565 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2566
2567 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2568}
2569
d369d2d9
DV		 2570static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2571 struct sg_table *pages,
2572 uint64_t start,
2573 enum i915_cache_level cache_level, u32 unused)
7faf1ab2 2574{
fac5e23e 2575 struct drm_i915_private *dev_priv = to_i915(vm->dev);
7faf1ab2
DV		 2576 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2577 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
be69459a
ID		 2578 int rpm_atomic_seq;
2579
2580 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2 2581
d369d2d9 2582 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2583
be69459a
ID		 2584 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2585
7faf1ab2
DV		 2586}
2587
853ba5d2 2588static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2589 uint64_t start,
2590 uint64_t length,
828c7908 2591 bool unused)
7faf1ab2 2592{
fac5e23e 2593 struct drm_i915_private *dev_priv = to_i915(vm->dev);
782f1495
BW		 2594 unsigned first_entry = start >> PAGE_SHIFT;
2595 unsigned num_entries = length >> PAGE_SHIFT;
be69459a
ID		 2596 int rpm_atomic_seq;
2597
2598 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2599
7faf1ab2 2600 intel_gtt_clear_range(first_entry, num_entries);
be69459a
ID		 2601
2602 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2603}
2604
70b9f6f8
DV		 2605static int ggtt_bind_vma(struct i915_vma *vma,
2606 enum i915_cache_level cache_level,
2607 u32 flags)
0a878716
DV		 2608{
2609 struct drm_i915_gem_object *obj = vma->obj;
2610 u32 pte_flags = 0;
2611 int ret;
2612
2613 ret = i915_get_ggtt_vma_pages(vma);
2614 if (ret)
2615 return ret;
2616
2617 /* Currently applicable only to VLV */
2618 if (obj->gt_ro)
2619 pte_flags |= PTE_READ_ONLY;
2620
2621 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2622 vma->node.start,
2623 cache_level, pte_flags);
2624
2625 /*
2626 * Without aliasing PPGTT there's no difference between
2627 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2628 * upgrade to both bound if we bind either to avoid double-binding.
2629 */
3272db53 2630 vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
0a878716
DV		 2631
2632 return 0;
2633}
2634
2635static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2636 enum i915_cache_level cache_level,
2637 u32 flags)
d5bd1449 2638{
321d178e 2639 u32 pte_flags;
70b9f6f8
DV		 2640 int ret;
2641
2642 ret = i915_get_ggtt_vma_pages(vma);
2643 if (ret)
2644 return ret;
7faf1ab2 2645
24f3a8cf 2646 /* Currently applicable only to VLV */
321d178e
CW		 2647 pte_flags = 0;
2648 if (vma->obj->gt_ro)
f329f5f6 2649 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2650
ec7adb6e 2651
3272db53 2652 if (flags & I915_VMA_GLOBAL_BIND) {
321d178e
CW		 2653 vma->vm->insert_entries(vma->vm,
2654 vma->ggtt_view.pages,
0875546c
DV		 2655 vma->node.start,
2656 cache_level, pte_flags);
6f65e29a 2657 }
d5bd1449 2658
3272db53 2659 if (flags & I915_VMA_LOCAL_BIND) {
321d178e
CW		 2660 struct i915_hw_ppgtt *appgtt =
2661 to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2662 appgtt->base.insert_entries(&appgtt->base,
2663 vma->ggtt_view.pages,
782f1495 2664 vma->node.start,
f329f5f6 2665 cache_level, pte_flags);
6f65e29a 2666 }
70b9f6f8
DV		 2667
2668 return 0;
d5bd1449
CW		 2669}
2670
6f65e29a 2671static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2672{
de180033
CW		 2673 struct i915_hw_ppgtt *appgtt = to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2674 const u64 size = min(vma->size, vma->node.size);
6f65e29a 2675
3272db53 2676 if (vma->flags & I915_VMA_GLOBAL_BIND)
782f1495 2677 vma->vm->clear_range(vma->vm,
de180033 2678 vma->node.start, size,
6f65e29a 2679 true);
06615ee5 2680
3272db53 2681 if (vma->flags & I915_VMA_LOCAL_BIND && appgtt)
6f65e29a 2682 appgtt->base.clear_range(&appgtt->base,
de180033 2683 vma->node.start, size,
6f65e29a 2684 true);
74163907
DV		 2685}
2686
2687void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2688{
5c042287 2689 struct drm_device *dev = obj->base.dev;
fac5e23e 2690 struct drm_i915_private *dev_priv = to_i915(dev);
307dc25b 2691 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5c042287 2692
307dc25b
CW		 2693 if (unlikely(ggtt->do_idle_maps)) {
2694 if (i915_gem_wait_for_idle(dev_priv, false)) {
2695 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2696 /* Wait a bit, in hopes it avoids the hang */
2697 udelay(10);
2698 }
2699 }
5c042287 2700
5ec5b516
ID		 2701 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2702 PCI_DMA_BIDIRECTIONAL);
7c2e6fdf 2703}
644ec02b 2704
42d6ab48
CW		 2705static void i915_gtt_color_adjust(struct drm_mm_node *node,
2706 unsigned long color,
440fd528
TR		 2707 u64 *start,
2708 u64 *end)
42d6ab48
CW		 2709{
2710 if (node->color != color)
2711 *start += 4096;
2712
2a1d7752
CW		 2713 node = list_first_entry_or_null(&node->node_list,
2714 struct drm_mm_node,
2715 node_list);
2716 if (node && node->allocated && node->color != color)
2717 *end -= 4096;
42d6ab48 2718}
fbe5d36e 2719
f6b9d5ca 2720int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
644ec02b 2721{
e78891ca
BW		 2722 /* Let GEM Manage all of the aperture.
2723 *
2724 * However, leave one page at the end still bound to the scratch page.
2725 * There are a number of places where the hardware apparently prefetches
2726 * past the end of the object, and we've seen multiple hangs with the
2727 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2728 * aperture. One page should be enough to keep any prefetching inside
2729 * of the aperture.
2730 */
72e96d64 2731 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ed2f3452 2732 unsigned long hole_start, hole_end;
f6b9d5ca 2733 struct drm_mm_node *entry;
fa76da34 2734 int ret;
644ec02b 2735
b02d22a3
ZW		 2736 ret = intel_vgt_balloon(dev_priv);
2737 if (ret)
2738 return ret;
5dda8fa3 2739
ed2f3452 2740 /* Clear any non-preallocated blocks */
72e96d64 2741 drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
ed2f3452
CW		 2742 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2743 hole_start, hole_end);
72e96d64 2744 ggtt->base.clear_range(&ggtt->base, hole_start,
782f1495 2745 hole_end - hole_start, true);
ed2f3452
CW		 2746 }
2747
2748 /* And finally clear the reserved guard page */
f6b9d5ca
CW		 2749 ggtt->base.clear_range(&ggtt->base,
2750 ggtt->base.total - PAGE_SIZE, PAGE_SIZE,
2751 true);
6c5566a8 2752
97d6d7ab 2753 if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
fa76da34
DV		 2754 struct i915_hw_ppgtt *ppgtt;
2755
2756 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2757 if (!ppgtt)
2758 return -ENOMEM;
2759
2bfa996e 2760 ret = __hw_ppgtt_init(ppgtt, dev_priv);
5c5f6457 2761 if (ret) {
5c5f6457
DV		 2762 kfree(ppgtt);
2763 return ret;
2764 }
2765
2766 if (ppgtt->base.allocate_va_range)
2767 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2768 ppgtt->base.total);
4933d519 2769 if (ret) {
061dd493 2770 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2771 kfree(ppgtt);
fa76da34 2772 return ret;
4933d519 2773 }
fa76da34 2774
5c5f6457
DV		 2775 ppgtt->base.clear_range(&ppgtt->base,
2776 ppgtt->base.start,
2777 ppgtt->base.total,
2778 true);
2779
fa76da34 2780 dev_priv->mm.aliasing_ppgtt = ppgtt;
72e96d64
JL		 2781 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2782 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
fa76da34
DV		 2783 }
2784
6c5566a8 2785 return 0;
e76e9aeb
BW		 2786}
2787
d85489d3
JL		 2788/**
2789 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
97d6d7ab 2790 * @dev_priv: i915 device
d85489d3 2791 */
97d6d7ab 2792void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
90d0a0e8 2793{
72e96d64 2794 struct i915_ggtt *ggtt = &dev_priv->ggtt;
90d0a0e8 2795
70e32544
DV		 2796 if (dev_priv->mm.aliasing_ppgtt) {
2797 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2798
2799 ppgtt->base.cleanup(&ppgtt->base);
cb7f2760 2800 kfree(ppgtt);
70e32544
DV		 2801 }
2802
97d6d7ab 2803 i915_gem_cleanup_stolen(&dev_priv->drm);
a4eba47b 2804
72e96d64 2805 if (drm_mm_initialized(&ggtt->base.mm)) {
b02d22a3 2806 intel_vgt_deballoon(dev_priv);
5dda8fa3 2807
72e96d64
JL		 2808 drm_mm_takedown(&ggtt->base.mm);
2809 list_del(&ggtt->base.global_link);
90d0a0e8
DV		 2810 }
2811
72e96d64 2812 ggtt->base.cleanup(&ggtt->base);
f6b9d5ca
CW		 2813
2814 arch_phys_wc_del(ggtt->mtrr);
2815 io_mapping_free(ggtt->mappable);
90d0a0e8 2816}
70e32544 2817
2c642b07 2818static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2819{
2820 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2821 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2822 return snb_gmch_ctl << 20;
2823}
2824
2c642b07 2825static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2826{
2827 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2828 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2829 if (bdw_gmch_ctl)
2830 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2831
2832#ifdef CONFIG_X86_32
2833 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2834 if (bdw_gmch_ctl > 4)
2835 bdw_gmch_ctl = 4;
2836#endif
2837
9459d252
BW		 2838 return bdw_gmch_ctl << 20;
2839}
2840
2c642b07 2841static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2842{
2843 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2844 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2845
2846 if (gmch_ctrl)
2847 return 1 << (20 + gmch_ctrl);
2848
2849 return 0;
2850}
2851
2c642b07 2852static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2853{
2854 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2855 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2856 return snb_gmch_ctl << 25; /* 32 MB units */
2857}
2858
2c642b07 2859static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2860{
2861 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2862 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2863 return bdw_gmch_ctl << 25; /* 32 MB units */
2864}
2865
d7f25f23
DL		 2866static size_t chv_get_stolen_size(u16 gmch_ctrl)
2867{
2868 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2869 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2870
2871 /*
2872 * 0x0 to 0x10: 32MB increments starting at 0MB
2873 * 0x11 to 0x16: 4MB increments starting at 8MB
2874 * 0x17 to 0x1d: 4MB increments start at 36MB
2875 */
2876 if (gmch_ctrl < 0x11)
2877 return gmch_ctrl << 25;
2878 else if (gmch_ctrl < 0x17)
2879 return (gmch_ctrl - 0x11 + 2) << 22;
2880 else
2881 return (gmch_ctrl - 0x17 + 9) << 22;
2882}
2883
66375014
DL		 2884static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2885{
2886 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2887 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2888
2889 if (gen9_gmch_ctl < 0xf0)
2890 return gen9_gmch_ctl << 25; /* 32 MB units */
2891 else
2892 /* 4MB increments starting at 0xf0 for 4MB */
2893 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2894}
2895
34c998b4 2896static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
63340133 2897{
34c998b4 2898 struct pci_dev *pdev = ggtt->base.dev->pdev;
4ad2af1e 2899 struct i915_page_scratch *scratch_page;
34c998b4 2900 phys_addr_t phys_addr;
63340133
BW		 2901
2902 /* For Modern GENs the PTEs and register space are split in the BAR */
34c998b4 2903 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
63340133 2904
2a073f89
ID		 2905 /*
2906 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2907 * dropped. For WC mappings in general we have 64 byte burst writes
2908 * when the WC buffer is flushed, so we can't use it, but have to
2909 * resort to an uncached mapping. The WC issue is easily caught by the
2910 * readback check when writing GTT PTE entries.
2911 */
34c998b4
CW		 2912 if (IS_BROXTON(ggtt->base.dev))
2913 ggtt->gsm = ioremap_nocache(phys_addr, size);
2a073f89 2914 else
34c998b4 2915 ggtt->gsm = ioremap_wc(phys_addr, size);
72e96d64 2916 if (!ggtt->gsm) {
34c998b4 2917 DRM_ERROR("Failed to map the ggtt page table\n");
63340133
BW		 2918 return -ENOMEM;
2919 }
2920
34c998b4 2921 scratch_page = alloc_scratch_page(ggtt->base.dev);
4ad2af1e 2922 if (IS_ERR(scratch_page)) {
63340133
BW		 2923 DRM_ERROR("Scratch setup failed\n");
2924 /* iounmap will also get called at remove, but meh */
72e96d64 2925 iounmap(ggtt->gsm);
4ad2af1e 2926 return PTR_ERR(scratch_page);
63340133
BW		 2927 }
2928
72e96d64 2929 ggtt->base.scratch_page = scratch_page;
4ad2af1e
MK		 2930
2931 return 0;
63340133
BW		 2932}
2933
fbe5d36e
BW		 2934/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2935 * bits. When using advanced contexts each context stores its own PAT, but
2936 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2937static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2938{
fbe5d36e
BW		 2939 uint64_t pat;
2940
2941 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2942 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2943 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2944 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2945 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2946 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2947 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2948 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2949
2d1fe073 2950 if (!USES_PPGTT(dev_priv))
d6a8b72e
RV		 2951 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2952 * so RTL will always use the value corresponding to
2953 * pat_sel = 000".
2954 * So let's disable cache for GGTT to avoid screen corruptions.
2955 * MOCS still can be used though.
2956 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2957 * before this patch, i.e. the same uncached + snooping access
2958 * like on gen6/7 seems to be in effect.
2959 * - So this just fixes blitter/render access. Again it looks
2960 * like it's not just uncached access, but uncached + snooping.
2961 * So we can still hold onto all our assumptions wrt cpu
2962 * clflushing on LLC machines.
2963 */
2964 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2965
fbe5d36e
BW		 2966 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2967 * write would work. */
7e435ad2
VS		 2968 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2969 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
fbe5d36e
BW		 2970}
2971
ee0ce478
VS		 2972static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2973{
2974 uint64_t pat;
2975
2976 /*
2977 * Map WB on BDW to snooped on CHV.
2978 *
2979 * Only the snoop bit has meaning for CHV, the rest is
2980 * ignored.
2981 *
cf3d262e
VS		 2982 * The hardware will never snoop for certain types of accesses:
2983 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2984 * - PPGTT page tables
2985 * - some other special cycles
2986 *
2987 * As with BDW, we also need to consider the following for GT accesses:
2988 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2989 * so RTL will always use the value corresponding to
2990 * pat_sel = 000".
2991 * Which means we must set the snoop bit in PAT entry 0
2992 * in order to keep the global status page working.
ee0ce478
VS		 2993 */
2994 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2995 GEN8_PPAT(1, 0) |
2996 GEN8_PPAT(2, 0) |
2997 GEN8_PPAT(3, 0) |
2998 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2999 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3000 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3001 GEN8_PPAT(7, CHV_PPAT_SNOOP);
3002
7e435ad2
VS		 3003 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3004 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
ee0ce478
VS		 3005}
3006
34c998b4
CW		 3007static void gen6_gmch_remove(struct i915_address_space *vm)
3008{
3009 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
3010
3011 iounmap(ggtt->gsm);
3012 free_scratch_page(vm->dev, vm->scratch_page);
3013}
3014
d507d735 3015static int gen8_gmch_probe(struct i915_ggtt *ggtt)
63340133 3016{
97d6d7ab
CW		 3017 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
3018 struct pci_dev *pdev = dev_priv->drm.pdev;
34c998b4 3019 unsigned int size;
63340133 3020 u16 snb_gmch_ctl;
63340133
BW		 3021
3022 /* TODO: We're not aware of mappable constraints on gen8 yet */
97d6d7ab
CW		 3023 ggtt->mappable_base = pci_resource_start(pdev, 2);
3024 ggtt->mappable_end = pci_resource_len(pdev, 2);
63340133 3025
97d6d7ab
CW		 3026 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39)))
3027 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
63340133 3028
97d6d7ab 3029 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
63340133 3030
97d6d7ab 3031 if (INTEL_GEN(dev_priv) >= 9) {
d507d735 3032 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
34c998b4 3033 size = gen8_get_total_gtt_size(snb_gmch_ctl);
97d6d7ab 3034 } else if (IS_CHERRYVIEW(dev_priv)) {
d507d735 3035 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
34c998b4 3036 size = chv_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3037 } else {
d507d735 3038 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
34c998b4 3039 size = gen8_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3040 }
63340133 3041
34c998b4 3042 ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 3043
97d6d7ab 3044 if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
ee0ce478
VS		 3045 chv_setup_private_ppat(dev_priv);
3046 else
3047 bdw_setup_private_ppat(dev_priv);
fbe5d36e 3048
34c998b4 3049 ggtt->base.cleanup = gen6_gmch_remove;
d507d735
JL		 3050 ggtt->base.bind_vma = ggtt_bind_vma;
3051 ggtt->base.unbind_vma = ggtt_unbind_vma;
d6473f56 3052 ggtt->base.insert_page = gen8_ggtt_insert_page;
f7770bfd 3053 ggtt->base.clear_range = nop_clear_range;
48f112fe 3054 if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
f7770bfd
CW		 3055 ggtt->base.clear_range = gen8_ggtt_clear_range;
3056
3057 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3058 if (IS_CHERRYVIEW(dev_priv))
3059 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3060
34c998b4 3061 return ggtt_probe_common(ggtt, size);
63340133
BW		 3062}
3063
d507d735 3064static int gen6_gmch_probe(struct i915_ggtt *ggtt)
e76e9aeb 3065{
97d6d7ab
CW		 3066 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
3067 struct pci_dev *pdev = dev_priv->drm.pdev;
34c998b4 3068 unsigned int size;
e76e9aeb 3069 u16 snb_gmch_ctl;
e76e9aeb 3070
97d6d7ab
CW		 3071 ggtt->mappable_base = pci_resource_start(pdev, 2);
3072 ggtt->mappable_end = pci_resource_len(pdev, 2);
41907ddc 3073
baa09f5f
BW		 3074 /* 64/512MB is the current min/max we actually know of, but this is just
3075 * a coarse sanity check.
e76e9aeb 3076 */
34c998b4 3077 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
d507d735 3078 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
baa09f5f 3079 return -ENXIO;
e76e9aeb
BW		 3080 }
3081
97d6d7ab
CW		 3082 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
3083 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
3084 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 3085
d507d735 3086 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
e76e9aeb 3087
34c998b4
CW		 3088 size = gen6_get_total_gtt_size(snb_gmch_ctl);
3089 ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 3090
d507d735 3091 ggtt->base.clear_range = gen6_ggtt_clear_range;
d6473f56 3092 ggtt->base.insert_page = gen6_ggtt_insert_page;
d507d735
JL		 3093 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3094 ggtt->base.bind_vma = ggtt_bind_vma;
3095 ggtt->base.unbind_vma = ggtt_unbind_vma;
34c998b4
CW		 3096 ggtt->base.cleanup = gen6_gmch_remove;
3097
3098 if (HAS_EDRAM(dev_priv))
3099 ggtt->base.pte_encode = iris_pte_encode;
3100 else if (IS_HASWELL(dev_priv))
3101 ggtt->base.pte_encode = hsw_pte_encode;
3102 else if (IS_VALLEYVIEW(dev_priv))
3103 ggtt->base.pte_encode = byt_pte_encode;
3104 else if (INTEL_GEN(dev_priv) >= 7)
3105 ggtt->base.pte_encode = ivb_pte_encode;
3106 else
3107 ggtt->base.pte_encode = snb_pte_encode;
7faf1ab2 3108
34c998b4 3109 return ggtt_probe_common(ggtt, size);
e76e9aeb
BW		 3110}
3111
34c998b4 3112static void i915_gmch_remove(struct i915_address_space *vm)
e76e9aeb 3113{
34c998b4 3114 intel_gmch_remove();
644ec02b 3115}
baa09f5f 3116
d507d735 3117static int i915_gmch_probe(struct i915_ggtt *ggtt)
baa09f5f 3118{
97d6d7ab 3119 struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev);
baa09f5f
BW		 3120 int ret;
3121
91c8a326 3122 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL);
baa09f5f
BW		 3123 if (!ret) {
3124 DRM_ERROR("failed to set up gmch\n");
3125 return -EIO;
3126 }
3127
d507d735
JL		 3128 intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3129 &ggtt->mappable_base, &ggtt->mappable_end);
baa09f5f 3130
97d6d7ab 3131 ggtt->do_idle_maps = needs_idle_maps(dev_priv);
d6473f56 3132 ggtt->base.insert_page = i915_ggtt_insert_page;
d507d735
JL		 3133 ggtt->base.insert_entries = i915_ggtt_insert_entries;
3134 ggtt->base.clear_range = i915_ggtt_clear_range;
3135 ggtt->base.bind_vma = ggtt_bind_vma;
3136 ggtt->base.unbind_vma = ggtt_unbind_vma;
34c998b4 3137 ggtt->base.cleanup = i915_gmch_remove;
baa09f5f 3138
d507d735 3139 if (unlikely(ggtt->do_idle_maps))
c0a7f818
CW		 3140 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3141
baa09f5f
BW		 3142 return 0;
3143}
3144
d85489d3 3145/**
0088e522 3146 * i915_ggtt_probe_hw - Probe GGTT hardware location
97d6d7ab 3147 * @dev_priv: i915 device
d85489d3 3148 */
97d6d7ab 3149int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
baa09f5f 3150{
62106b4f 3151 struct i915_ggtt *ggtt = &dev_priv->ggtt;
baa09f5f
BW		 3152 int ret;
3153
97d6d7ab 3154 ggtt->base.dev = &dev_priv->drm;
c114f76a 3155
34c998b4
CW		 3156 if (INTEL_GEN(dev_priv) <= 5)
3157 ret = i915_gmch_probe(ggtt);
3158 else if (INTEL_GEN(dev_priv) < 8)
3159 ret = gen6_gmch_probe(ggtt);
3160 else
3161 ret = gen8_gmch_probe(ggtt);
a54c0c27 3162 if (ret)
baa09f5f 3163 return ret;
baa09f5f 3164
c890e2d5
CW		 3165 if ((ggtt->base.total - 1) >> 32) {
3166 DRM_ERROR("We never expected a Global GTT with more than 32bits"
f6b9d5ca 3167 " of address space! Found %lldM!\n",
c890e2d5
CW		 3168 ggtt->base.total >> 20);
3169 ggtt->base.total = 1ULL << 32;
3170 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3171 }
3172
f6b9d5ca
CW		 3173 if (ggtt->mappable_end > ggtt->base.total) {
3174 DRM_ERROR("mappable aperture extends past end of GGTT,"
3175 " aperture=%llx, total=%llx\n",
3176 ggtt->mappable_end, ggtt->base.total);
3177 ggtt->mappable_end = ggtt->base.total;
3178 }
3179
baa09f5f 3180 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 3181 DRM_INFO("Memory usable by graphics device = %lluM\n",
62106b4f
JL		 3182 ggtt->base.total >> 20);
3183 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3184 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
5db6c735
DV		 3185#ifdef CONFIG_INTEL_IOMMU
3186 if (intel_iommu_gfx_mapped)
3187 DRM_INFO("VT-d active for gfx access\n");
3188#endif
baa09f5f
BW		 3189
3190 return 0;
0088e522
CW		 3191}
3192
3193/**
3194 * i915_ggtt_init_hw - Initialize GGTT hardware
97d6d7ab 3195 * @dev_priv: i915 device
0088e522 3196 */
97d6d7ab 3197int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
0088e522 3198{
0088e522
CW		 3199 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3200 int ret;
3201
f6b9d5ca
CW		 3202 INIT_LIST_HEAD(&dev_priv->vm_list);
3203
3204 /* Subtract the guard page before address space initialization to
3205 * shrink the range used by drm_mm.
3206 */
3207 ggtt->base.total -= PAGE_SIZE;
3208 i915_address_space_init(&ggtt->base, dev_priv);
3209 ggtt->base.total += PAGE_SIZE;
3210 if (!HAS_LLC(dev_priv))
3211 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
3212
3213 ggtt->mappable =
3214 io_mapping_create_wc(ggtt->mappable_base, ggtt->mappable_end);
3215 if (!ggtt->mappable) {
3216 ret = -EIO;
3217 goto out_gtt_cleanup;
3218 }
3219
3220 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
3221
0088e522
CW		 3222 /*
3223 * Initialise stolen early so that we may reserve preallocated
3224 * objects for the BIOS to KMS transition.
3225 */
97d6d7ab 3226 ret = i915_gem_init_stolen(&dev_priv->drm);
0088e522
CW		 3227 if (ret)
3228 goto out_gtt_cleanup;
3229
3230 return 0;
a4eba47b
ID		 3231
3232out_gtt_cleanup:
72e96d64 3233 ggtt->base.cleanup(&ggtt->base);
a4eba47b 3234 return ret;
baa09f5f 3235}
6f65e29a 3236
97d6d7ab 3237int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
ac840ae5 3238{
97d6d7ab 3239 if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
ac840ae5
VS		 3240 return -EIO;
3241
3242 return 0;
3243}
3244
fa42331b
DV		 3245void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3246{
72e96d64
JL		 3247 struct drm_i915_private *dev_priv = to_i915(dev);
3248 struct i915_ggtt *ggtt = &dev_priv->ggtt;
fa42331b 3249 struct drm_i915_gem_object *obj;
2c3d9984 3250 struct i915_vma *vma;
fa42331b 3251
dc97997a 3252 i915_check_and_clear_faults(dev_priv);
fa42331b
DV		 3253
3254 /* First fill our portion of the GTT with scratch pages */
72e96d64
JL		 3255 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3256 true);
fa42331b 3257
2c3d9984 3258 /* Cache flush objects bound into GGTT and rebind them. */
fa42331b 3259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1c7f4bca 3260 list_for_each_entry(vma, &obj->vma_list, obj_link) {
72e96d64 3261 if (vma->vm != &ggtt->base)
2c3d9984 3262 continue;
fa42331b 3263
2c3d9984
TU		 3264 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3265 PIN_UPDATE));
2c3d9984
TU		 3266 }
3267
975f7ff4
CW		 3268 if (obj->pin_display)
3269 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
2c3d9984 3270 }
fa42331b
DV		 3271
3272 if (INTEL_INFO(dev)->gen >= 8) {
3273 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3274 chv_setup_private_ppat(dev_priv);
3275 else
3276 bdw_setup_private_ppat(dev_priv);
3277
3278 return;
3279 }
3280
3281 if (USES_PPGTT(dev)) {
72e96d64
JL		 3282 struct i915_address_space *vm;
3283
fa42331b
DV		 3284 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3285 /* TODO: Perhaps it shouldn't be gen6 specific */
3286
e5716f55 3287 struct i915_hw_ppgtt *ppgtt;
fa42331b 3288
2bfa996e 3289 if (i915_is_ggtt(vm))
fa42331b 3290 ppgtt = dev_priv->mm.aliasing_ppgtt;
e5716f55
JL		 3291 else
3292 ppgtt = i915_vm_to_ppgtt(vm);
fa42331b
DV		 3293
3294 gen6_write_page_range(dev_priv, &ppgtt->pd,
3295 0, ppgtt->base.total);
3296 }
3297 }
3298
3299 i915_ggtt_flush(dev_priv);
3300}
3301
b0decaf7
CW		 3302static void
3303i915_vma_retire(struct i915_gem_active *active,
3304 struct drm_i915_gem_request *rq)
3305{
3306 const unsigned int idx = rq->engine->id;
3307 struct i915_vma *vma =
3308 container_of(active, struct i915_vma, last_read[idx]);
3309
3310 GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx));
3311
3312 i915_vma_clear_active(vma, idx);
3313 if (i915_vma_is_active(vma))
3314 return;
3315
3316 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3272db53 3317 if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma)))
b1f788c6
CW		 3318 WARN_ON(i915_vma_unbind(vma));
3319}
3320
3321void i915_vma_destroy(struct i915_vma *vma)
3322{
3323 GEM_BUG_ON(vma->node.allocated);
3324 GEM_BUG_ON(i915_vma_is_active(vma));
3272db53 3325 GEM_BUG_ON(!i915_vma_is_closed(vma));
b1f788c6
CW		 3326
3327 list_del(&vma->vm_link);
3272db53 3328 if (!i915_vma_is_ggtt(vma))
b1f788c6
CW		 3329 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
3330
3331 kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
3332}
3333
3334void i915_vma_close(struct i915_vma *vma)
3335{
3272db53
CW		 3336 GEM_BUG_ON(i915_vma_is_closed(vma));
3337 vma->flags |= I915_VMA_CLOSED;
b1f788c6
CW		 3338
3339 list_del_init(&vma->obj_link);
20dfbde4 3340 if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma))
df0e9a28 3341 WARN_ON(i915_vma_unbind(vma));
b0decaf7
CW		 3342}
3343
ec7adb6e
JL		 3344static struct i915_vma *
3345__i915_gem_vma_create(struct drm_i915_gem_object *obj,
3346 struct i915_address_space *vm,
de180033 3347 const struct i915_ggtt_view *view)
6f65e29a 3348{
dabde5c7 3349 struct i915_vma *vma;
b0decaf7 3350 int i;
6f65e29a 3351
50e046b6
CW		 3352 GEM_BUG_ON(vm->closed);
3353
de180033 3354 if (WARN_ON(i915_is_ggtt(vm) != !!view))
ec7adb6e 3355 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 3356
3357 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 3358 if (vma == NULL)
3359 return ERR_PTR(-ENOMEM);
ec7adb6e 3360
1c7f4bca 3361 INIT_LIST_HEAD(&vma->obj_link);
6f65e29a 3362 INIT_LIST_HEAD(&vma->exec_list);
b0decaf7
CW		 3363 for (i = 0; i < ARRAY_SIZE(vma->last_read); i++)
3364 init_request_active(&vma->last_read[i], i915_vma_retire);
50e046b6 3365 list_add(&vma->vm_link, &vm->unbound_list);
6f65e29a
BW		 3366 vma->vm = vm;
3367 vma->obj = obj;
de180033 3368 vma->size = obj->base.size;
6f65e29a 3369
de180033 3370 if (i915_is_ggtt(vm)) {
3272db53 3371 vma->flags |= I915_VMA_GGTT;
de180033
CW		 3372 vma->ggtt_view = *view;
3373 if (view->type == I915_GGTT_VIEW_PARTIAL) {
3374 vma->size = view->params.partial.size;
3375 vma->size <<= PAGE_SHIFT;
3376 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3377 vma->size =
3378 intel_rotation_info_size(&view->params.rotated);
3379 vma->size <<= PAGE_SHIFT;
3380 }
3381 } else {
596c5923 3382 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
de180033 3383 }
6f65e29a 3384
1c7f4bca 3385 list_add_tail(&vma->obj_link, &obj->vma_list);
6f65e29a
BW		 3386
3387 return vma;
3388}
3389
3390struct i915_vma *
ec7adb6e
JL		 3391i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3392 struct i915_address_space *vm)
3393{
3394 struct i915_vma *vma;
3395
3396 vma = i915_gem_obj_to_vma(obj, vm);
3397 if (!vma)
3398 vma = __i915_gem_vma_create(obj, vm,
3399 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3400
3401 return vma;
3402}
3403
3404struct i915_vma *
3405i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 3406 const struct i915_ggtt_view *view)
6f65e29a 3407{
72e96d64
JL		 3408 struct drm_device *dev = obj->base.dev;
3409 struct drm_i915_private *dev_priv = to_i915(dev);
3410 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ade7daa1 3411 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
ec7adb6e 3412
de895082
CW		 3413 GEM_BUG_ON(!view);
3414
6f65e29a 3415 if (!vma)
72e96d64 3416 vma = __i915_gem_vma_create(obj, &ggtt->base, view);
6f65e29a 3417
3272db53 3418 GEM_BUG_ON(i915_vma_is_closed(vma));
6f65e29a 3419 return vma;
ec7adb6e 3420
6f65e29a 3421}
fe14d5f4 3422
804beb4b 3423static struct scatterlist *
2d7f3bdb 3424rotate_pages(const dma_addr_t *in, unsigned int offset,
804beb4b 3425 unsigned int width, unsigned int height,
87130255 3426 unsigned int stride,
804beb4b 3427 struct sg_table *st, struct scatterlist *sg)
50470bb0
TU		 3428{
3429 unsigned int column, row;
3430 unsigned int src_idx;
50470bb0 3431
50470bb0 3432 for (column = 0; column < width; column++) {
87130255 3433 src_idx = stride * (height - 1) + column;
50470bb0
TU		 3434 for (row = 0; row < height; row++) {
3435 st->nents++;
3436 /* We don't need the pages, but need to initialize
3437 * the entries so the sg list can be happily traversed.
3438 * The only thing we need are DMA addresses.
3439 */
3440 sg_set_page(sg, NULL, PAGE_SIZE, 0);
804beb4b 3441 sg_dma_address(sg) = in[offset + src_idx];
50470bb0
TU		 3442 sg_dma_len(sg) = PAGE_SIZE;
3443 sg = sg_next(sg);
87130255 3444 src_idx -= stride;
50470bb0
TU		 3445 }
3446 }
804beb4b
TU		 3447
3448 return sg;
50470bb0
TU		 3449}
3450
3451static struct sg_table *
11d23e6f 3452intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
50470bb0
TU		 3453 struct drm_i915_gem_object *obj)
3454{
85d1225e 3455 const size_t n_pages = obj->base.size / PAGE_SIZE;
1663b9d6 3456 unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
89e3e142 3457 unsigned int size_pages_uv;
85d1225e
DG		 3458 struct sgt_iter sgt_iter;
3459 dma_addr_t dma_addr;
50470bb0
TU		 3460 unsigned long i;
3461 dma_addr_t *page_addr_list;
3462 struct sg_table *st;
89e3e142
TU		 3463 unsigned int uv_start_page;
3464 struct scatterlist *sg;
1d00dad5 3465 int ret = -ENOMEM;
50470bb0 3466
50470bb0 3467 /* Allocate a temporary list of source pages for random access. */
85d1225e 3468 page_addr_list = drm_malloc_gfp(n_pages,
f2a85e19
CW		 3469 sizeof(dma_addr_t),
3470 GFP_TEMPORARY);
50470bb0
TU		 3471 if (!page_addr_list)
3472 return ERR_PTR(ret);
3473
89e3e142
TU		 3474 /* Account for UV plane with NV12. */
3475 if (rot_info->pixel_format == DRM_FORMAT_NV12)
1663b9d6 3476 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
89e3e142
TU		 3477 else
3478 size_pages_uv = 0;
3479
50470bb0
TU		 3480 /* Allocate target SG list. */
3481 st = kmalloc(sizeof(*st), GFP_KERNEL);
3482 if (!st)
3483 goto err_st_alloc;
3484
89e3e142 3485 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
50470bb0
TU		 3486 if (ret)
3487 goto err_sg_alloc;
3488
3489 /* Populate source page list from the object. */
3490 i = 0;
85d1225e
DG		 3491 for_each_sgt_dma(dma_addr, sgt_iter, obj->pages)
3492 page_addr_list[i++] = dma_addr;
50470bb0 3493
85d1225e 3494 GEM_BUG_ON(i != n_pages);
11f20322
VS		 3495 st->nents = 0;
3496 sg = st->sgl;
3497
50470bb0 3498 /* Rotate the pages. */
89e3e142 3499 sg = rotate_pages(page_addr_list, 0,
1663b9d6
VS		 3500 rot_info->plane[0].width, rot_info->plane[0].height,
3501 rot_info->plane[0].width,
11f20322 3502 st, sg);
50470bb0 3503
89e3e142
TU		 3504 /* Append the UV plane if NV12. */
3505 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3506 uv_start_page = size_pages;
3507
3508 /* Check for tile-row un-alignment. */
3509 if (offset_in_page(rot_info->uv_offset))
3510 uv_start_page--;
3511
dedf278c
TU		 3512 rot_info->uv_start_page = uv_start_page;
3513
11f20322
VS		 3514 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3515 rot_info->plane[1].width, rot_info->plane[1].height,
3516 rot_info->plane[1].width,
3517 st, sg);
89e3e142
TU		 3518 }
3519
1663b9d6
VS		 3520 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3521 obj->base.size, rot_info->plane[0].width,
3522 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3523 size_pages);
50470bb0
TU		 3524
3525 drm_free_large(page_addr_list);
3526
3527 return st;
3528
3529err_sg_alloc:
3530 kfree(st);
3531err_st_alloc:
3532 drm_free_large(page_addr_list);
3533
1663b9d6
VS		 3534 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3535 obj->base.size, ret, rot_info->plane[0].width,
3536 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3537 size_pages);
50470bb0
TU		 3538 return ERR_PTR(ret);
3539}
ec7adb6e 3540
8bd7ef16
JL		 3541static struct sg_table *
3542intel_partial_pages(const struct i915_ggtt_view *view,
3543 struct drm_i915_gem_object *obj)
3544{
3545 struct sg_table *st;
3546 struct scatterlist *sg;
3547 struct sg_page_iter obj_sg_iter;
3548 int ret = -ENOMEM;
3549
3550 st = kmalloc(sizeof(*st), GFP_KERNEL);
3551 if (!st)
3552 goto err_st_alloc;
3553
3554 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3555 if (ret)
3556 goto err_sg_alloc;
3557
3558 sg = st->sgl;
3559 st->nents = 0;
3560 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3561 view->params.partial.offset)
3562 {
3563 if (st->nents >= view->params.partial.size)
3564 break;
3565
3566 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3567 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3568 sg_dma_len(sg) = PAGE_SIZE;
3569
3570 sg = sg_next(sg);
3571 st->nents++;
3572 }
3573
3574 return st;
3575
3576err_sg_alloc:
3577 kfree(st);
3578err_st_alloc:
3579 return ERR_PTR(ret);
3580}
3581
70b9f6f8 3582static int
50470bb0 3583i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 3584{
50470bb0
TU		 3585 int ret = 0;
3586
fe14d5f4
TU		 3587 if (vma->ggtt_view.pages)
3588 return 0;
3589
3590 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3591 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 3592 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3593 vma->ggtt_view.pages =
11d23e6f 3594 intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
8bd7ef16
JL		 3595 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3596 vma->ggtt_view.pages =
3597 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 3598 else
3599 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3600 vma->ggtt_view.type);
3601
3602 if (!vma->ggtt_view.pages) {
ec7adb6e 3603 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 3604 vma->ggtt_view.type);
50470bb0
TU		 3605 ret = -EINVAL;
3606 } else if (IS_ERR(vma->ggtt_view.pages)) {
3607 ret = PTR_ERR(vma->ggtt_view.pages);
3608 vma->ggtt_view.pages = NULL;
3609 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3610 vma->ggtt_view.type, ret);
fe14d5f4
TU		 3611 }
3612
50470bb0 3613 return ret;
fe14d5f4
TU		 3614}
3615
3616/**
3617 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3618 * @vma: VMA to map
3619 * @cache_level: mapping cache level
3620 * @flags: flags like global or local mapping
3621 *
3622 * DMA addresses are taken from the scatter-gather table of this object (or of
3623 * this VMA in case of non-default GGTT views) and PTE entries set up.
3624 * Note that DMA addresses are also the only part of the SG table we care about.
3625 */
3626int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3627 u32 flags)
3628{
75d04a37 3629 u32 bind_flags;
3272db53
CW		 3630 u32 vma_flags;
3631 int ret;
1d335d1b 3632
75d04a37
MK		 3633 if (WARN_ON(flags == 0))
3634 return -EINVAL;
1d335d1b 3635
75d04a37 3636 bind_flags = 0;
0875546c 3637 if (flags & PIN_GLOBAL)
3272db53 3638 bind_flags |= I915_VMA_GLOBAL_BIND;
0875546c 3639 if (flags & PIN_USER)
3272db53 3640 bind_flags |= I915_VMA_LOCAL_BIND;
0875546c 3641
3272db53 3642 vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND);
0875546c 3643 if (flags & PIN_UPDATE)
3272db53 3644 bind_flags |= vma_flags;
0875546c 3645 else
3272db53 3646 bind_flags &= ~vma_flags;
75d04a37
MK		 3647 if (bind_flags == 0)
3648 return 0;
3649
3272db53 3650 if (vma_flags == 0 && vma->vm->allocate_va_range) {
596c5923 3651 trace_i915_va_alloc(vma);
75d04a37
MK		 3652 ret = vma->vm->allocate_va_range(vma->vm,
3653 vma->node.start,
3654 vma->node.size);
3655 if (ret)
3656 return ret;
3657 }
3658
3659 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3660 if (ret)
3661 return ret;
0875546c 3662
3272db53 3663 vma->flags |= bind_flags;
fe14d5f4
TU		 3664 return 0;
3665}
91e6711e 3666
8ef8561f
CW		 3667void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
3668{
3669 void __iomem *ptr;
3670
3671 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3672 if (WARN_ON(!vma->obj->map_and_fenceable))
406ea8d2 3673 return IO_ERR_PTR(-ENODEV);
8ef8561f 3674
3272db53
CW		 3675 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
3676 GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0);
8ef8561f
CW		 3677
3678 ptr = vma->iomap;
3679 if (ptr == NULL) {
3680 ptr = io_mapping_map_wc(i915_vm_to_ggtt(vma->vm)->mappable,
3681 vma->node.start,
3682 vma->node.size);
3683 if (ptr == NULL)
406ea8d2 3684 return IO_ERR_PTR(-ENOMEM);
8ef8561f
CW		 3685
3686 vma->iomap = ptr;
3687 }
3688
20dfbde4 3689 __i915_vma_pin(vma);
8ef8561f
CW		 3690 return ptr;
3691}
Linux kernel - Deliverables
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