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drm/i915: Add locking to pll updates, v3.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
5bab6f60 27#include <linux/stop_machine.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
76aaf220 30#include "i915_drv.h"
5dda8fa3 31#include "i915_vgpu.h"
76aaf220
DV		 32#include "i915_trace.h"
33#include "intel_drv.h"
34
45f8f69a
TU		 35/**
36 * DOC: Global GTT views
37 *
38 * Background and previous state
39 *
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
43 *
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
47 *
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
50 * (2x2 pages):
51 *
52 * 12
53 * 34
54 *
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
58 *
59 * 1212
60 * 3434
61 *
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
64 *
65 * Implementation and usage
66 *
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
69 *
70 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 74 *
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
79 *
80 * Code wanting to add or use a new GGTT view needs to:
81 *
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
85 *
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
89 *
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
93 *
94 */
95
70b9f6f8
DV		 96static int
97i915_get_ggtt_vma_pages(struct i915_vma *vma);
98
b5e16987
VS		 99const struct i915_ggtt_view i915_ggtt_view_normal = {
100 .type = I915_GGTT_VIEW_NORMAL,
101};
9abc4648 102const struct i915_ggtt_view i915_ggtt_view_rotated = {
b5e16987 103 .type = I915_GGTT_VIEW_ROTATED,
9abc4648 104};
fe14d5f4 105
cfa7c862
DV		 106static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
107{
1893a71b
CW		 108 bool has_aliasing_ppgtt;
109 bool has_full_ppgtt;
1f9a99e0 110 bool has_full_48bit_ppgtt;
1893a71b
CW		 111
112 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
113 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1f9a99e0 114 has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
1893a71b 115
71ba2d64
YZ		 116 if (intel_vgpu_active(dev))
117 has_full_ppgtt = false; /* emulation is too hard */
118
70ee45e1
DL		 119 /*
120 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
121 * execlists, the sole mechanism available to submit work.
122 */
123 if (INTEL_INFO(dev)->gen < 9 &&
124 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 125 return 0;
126
127 if (enable_ppgtt == 1)
128 return 1;
129
1893a71b 130 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 131 return 2;
132
1f9a99e0
MT		 133 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
134 return 3;
135
93a25a9e
DV		 136#ifdef CONFIG_INTEL_IOMMU
137 /* Disable ppgtt on SNB if VT-d is on. */
138 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
139 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 140 return 0;
93a25a9e
DV		 141 }
142#endif
143
62942ed7 144 /* Early VLV doesn't have this */
666a4537 145 if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
62942ed7
JB		 146 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
147 return 0;
148 }
149
2f82bbdf 150 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
1f9a99e0 151 return has_full_48bit_ppgtt ? 3 : 2;
2f82bbdf
MT		 152 else
153 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 154}
155
70b9f6f8
DV		 156static int ppgtt_bind_vma(struct i915_vma *vma,
157 enum i915_cache_level cache_level,
158 u32 unused)
47552659
DV		 159{
160 u32 pte_flags = 0;
161
162 /* Currently applicable only to VLV */
163 if (vma->obj->gt_ro)
164 pte_flags |= PTE_READ_ONLY;
165
166 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
167 cache_level, pte_flags);
70b9f6f8
DV		 168
169 return 0;
47552659
DV		 170}
171
172static void ppgtt_unbind_vma(struct i915_vma *vma)
173{
174 vma->vm->clear_range(vma->vm,
175 vma->node.start,
176 vma->obj->base.size,
177 true);
178}
6f65e29a 179
2c642b07
DV		 180static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
181 enum i915_cache_level level,
182 bool valid)
94ec8f61 183{
07749ef3 184 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 185 pte |= addr;
63c42e56
BW		 186
187 switch (level) {
188 case I915_CACHE_NONE:
fbe5d36e 189 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 190 break;
191 case I915_CACHE_WT:
192 pte |= PPAT_DISPLAY_ELLC_INDEX;
193 break;
194 default:
195 pte |= PPAT_CACHED_INDEX;
196 break;
197 }
198
94ec8f61
BW		 199 return pte;
200}
201
fe36f55d
MK		 202static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
203 const enum i915_cache_level level)
b1fe6673 204{
07749ef3 205 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 206 pde |= addr;
207 if (level != I915_CACHE_NONE)
208 pde |= PPAT_CACHED_PDE_INDEX;
209 else
210 pde |= PPAT_UNCACHED_INDEX;
211 return pde;
212}
213
762d9936
MT		 214#define gen8_pdpe_encode gen8_pde_encode
215#define gen8_pml4e_encode gen8_pde_encode
216
07749ef3
MT		 217static gen6_pte_t snb_pte_encode(dma_addr_t addr,
218 enum i915_cache_level level,
219 bool valid, u32 unused)
54d12527 220{
07749ef3 221 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 222 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 223
224 switch (level) {
350ec881
CW		 225 case I915_CACHE_L3_LLC:
226 case I915_CACHE_LLC:
227 pte |= GEN6_PTE_CACHE_LLC;
228 break;
229 case I915_CACHE_NONE:
230 pte |= GEN6_PTE_UNCACHED;
231 break;
232 default:
5f77eeb0 233 MISSING_CASE(level);
350ec881
CW		 234 }
235
236 return pte;
237}
238
07749ef3
MT		 239static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
240 enum i915_cache_level level,
241 bool valid, u32 unused)
350ec881 242{
07749ef3 243 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 244 pte |= GEN6_PTE_ADDR_ENCODE(addr);
245
246 switch (level) {
247 case I915_CACHE_L3_LLC:
248 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 249 break;
250 case I915_CACHE_LLC:
251 pte |= GEN6_PTE_CACHE_LLC;
252 break;
253 case I915_CACHE_NONE:
9119708c 254 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 255 break;
256 default:
5f77eeb0 257 MISSING_CASE(level);
e7210c3c
BW		 258 }
259
54d12527
BW		 260 return pte;
261}
262
07749ef3
MT		 263static gen6_pte_t byt_pte_encode(dma_addr_t addr,
264 enum i915_cache_level level,
265 bool valid, u32 flags)
93c34e70 266{
07749ef3 267 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 268 pte |= GEN6_PTE_ADDR_ENCODE(addr);
269
24f3a8cf
AG		 270 if (!(flags & PTE_READ_ONLY))
271 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 272
273 if (level != I915_CACHE_NONE)
274 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
275
276 return pte;
277}
278
07749ef3
MT		 279static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
280 enum i915_cache_level level,
281 bool valid, u32 unused)
9119708c 282{
07749ef3 283 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 284 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 285
286 if (level != I915_CACHE_NONE)
87a6b688 287 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 288
289 return pte;
290}
291
07749ef3
MT		 292static gen6_pte_t iris_pte_encode(dma_addr_t addr,
293 enum i915_cache_level level,
294 bool valid, u32 unused)
4d15c145 295{
07749ef3 296 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 297 pte |= HSW_PTE_ADDR_ENCODE(addr);
298
651d794f
CW		 299 switch (level) {
300 case I915_CACHE_NONE:
301 break;
302 case I915_CACHE_WT:
c51e9701 303 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 304 break;
305 default:
c51e9701 306 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 307 break;
308 }
4d15c145
BW		 309
310 return pte;
311}
312
c114f76a
MK		 313static int __setup_page_dma(struct drm_device *dev,
314 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 315{
316 struct device *device = &dev->pdev->dev;
317
c114f76a 318 p->page = alloc_page(flags);
44159ddb
MK		 319 if (!p->page)
320 return -ENOMEM;
678d96fb 321
44159ddb
MK		 322 p->daddr = dma_map_page(device,
323 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 324
44159ddb
MK		 325 if (dma_mapping_error(device, p->daddr)) {
326 __free_page(p->page);
327 return -EINVAL;
328 }
1266cdb1
MT		 329
330 return 0;
678d96fb
BW		 331}
332
c114f76a
MK		 333static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
334{
335 return __setup_page_dma(dev, p, GFP_KERNEL);
336}
337
44159ddb 338static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 339{
44159ddb 340 if (WARN_ON(!p->page))
06fda602 341 return;
678d96fb 342
44159ddb
MK		 343 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
344 __free_page(p->page);
345 memset(p, 0, sizeof(*p));
346}
347
d1c54acd 348static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 349{
d1c54acd
MK		 350 return kmap_atomic(p->page);
351}
73eeea53 352
d1c54acd
MK		 353/* We use the flushing unmap only with ppgtt structures:
354 * page directories, page tables and scratch pages.
355 */
356static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
357{
73eeea53
MK		 358 /* There are only few exceptions for gen >=6. chv and bxt.
359 * And we are not sure about the latter so play safe for now.
360 */
361 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
362 drm_clflush_virt_range(vaddr, PAGE_SIZE);
363
364 kunmap_atomic(vaddr);
365}
366
567047be 367#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 368#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
369
567047be
MK		 370#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
371#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
372#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
373#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
374
d1c54acd
MK		 375static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
376 const uint64_t val)
377{
378 int i;
379 uint64_t * const vaddr = kmap_page_dma(p);
380
381 for (i = 0; i < 512; i++)
382 vaddr[i] = val;
383
384 kunmap_page_dma(dev, vaddr);
385}
386
73eeea53
MK		 387static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
388 const uint32_t val32)
389{
390 uint64_t v = val32;
391
392 v = v << 32 | val32;
393
394 fill_page_dma(dev, p, v);
395}
396
4ad2af1e
MK		 397static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
398{
399 struct i915_page_scratch *sp;
400 int ret;
401
402 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
403 if (sp == NULL)
404 return ERR_PTR(-ENOMEM);
405
406 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
407 if (ret) {
408 kfree(sp);
409 return ERR_PTR(ret);
410 }
411
412 set_pages_uc(px_page(sp), 1);
413
414 return sp;
415}
416
417static void free_scratch_page(struct drm_device *dev,
418 struct i915_page_scratch *sp)
419{
420 set_pages_wb(px_page(sp), 1);
421
422 cleanup_px(dev, sp);
423 kfree(sp);
424}
425
8a1ebd74 426static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 427{
ec565b3c 428 struct i915_page_table *pt;
678d96fb
BW		 429 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
430 GEN8_PTES : GEN6_PTES;
431 int ret = -ENOMEM;
06fda602
BW		 432
433 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
434 if (!pt)
435 return ERR_PTR(-ENOMEM);
436
678d96fb
BW		 437 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
438 GFP_KERNEL);
439
440 if (!pt->used_ptes)
441 goto fail_bitmap;
442
567047be 443 ret = setup_px(dev, pt);
678d96fb 444 if (ret)
44159ddb 445 goto fail_page_m;
06fda602
BW		 446
447 return pt;
678d96fb 448
44159ddb 449fail_page_m:
678d96fb
BW		 450 kfree(pt->used_ptes);
451fail_bitmap:
452 kfree(pt);
453
454 return ERR_PTR(ret);
06fda602
BW		 455}
456
2e906bea 457static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 458{
2e906bea
MK		 459 cleanup_px(dev, pt);
460 kfree(pt->used_ptes);
461 kfree(pt);
462}
463
464static void gen8_initialize_pt(struct i915_address_space *vm,
465 struct i915_page_table *pt)
466{
467 gen8_pte_t scratch_pte;
468
469 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
470 I915_CACHE_LLC, true);
471
472 fill_px(vm->dev, pt, scratch_pte);
473}
474
475static void gen6_initialize_pt(struct i915_address_space *vm,
476 struct i915_page_table *pt)
477{
478 gen6_pte_t scratch_pte;
479
480 WARN_ON(px_dma(vm->scratch_page) == 0);
481
482 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
483 I915_CACHE_LLC, true, 0);
484
485 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 486}
487
8a1ebd74 488static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 489{
ec565b3c 490 struct i915_page_directory *pd;
33c8819f 491 int ret = -ENOMEM;
06fda602
BW		 492
493 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
494 if (!pd)
495 return ERR_PTR(-ENOMEM);
496
33c8819f
MT		 497 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
498 sizeof(*pd->used_pdes), GFP_KERNEL);
499 if (!pd->used_pdes)
a08e111a 500 goto fail_bitmap;
33c8819f 501
567047be 502 ret = setup_px(dev, pd);
33c8819f 503 if (ret)
a08e111a 504 goto fail_page_m;
e5815a2e 505
06fda602 506 return pd;
33c8819f 507
a08e111a 508fail_page_m:
33c8819f 509 kfree(pd->used_pdes);
a08e111a 510fail_bitmap:
33c8819f
MT		 511 kfree(pd);
512
513 return ERR_PTR(ret);
06fda602
BW		 514}
515
2e906bea
MK		 516static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
517{
518 if (px_page(pd)) {
519 cleanup_px(dev, pd);
520 kfree(pd->used_pdes);
521 kfree(pd);
522 }
523}
524
525static void gen8_initialize_pd(struct i915_address_space *vm,
526 struct i915_page_directory *pd)
527{
528 gen8_pde_t scratch_pde;
529
530 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
531
532 fill_px(vm->dev, pd, scratch_pde);
533}
534
6ac18502
MT		 535static int __pdp_init(struct drm_device *dev,
536 struct i915_page_directory_pointer *pdp)
537{
538 size_t pdpes = I915_PDPES_PER_PDP(dev);
539
540 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
541 sizeof(unsigned long),
542 GFP_KERNEL);
543 if (!pdp->used_pdpes)
544 return -ENOMEM;
545
546 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
547 GFP_KERNEL);
548 if (!pdp->page_directory) {
549 kfree(pdp->used_pdpes);
550 /* the PDP might be the statically allocated top level. Keep it
551 * as clean as possible */
552 pdp->used_pdpes = NULL;
553 return -ENOMEM;
554 }
555
556 return 0;
557}
558
559static void __pdp_fini(struct i915_page_directory_pointer *pdp)
560{
561 kfree(pdp->used_pdpes);
562 kfree(pdp->page_directory);
563 pdp->page_directory = NULL;
564}
565
762d9936
MT		 566static struct
567i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
568{
569 struct i915_page_directory_pointer *pdp;
570 int ret = -ENOMEM;
571
572 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
573
574 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
575 if (!pdp)
576 return ERR_PTR(-ENOMEM);
577
578 ret = __pdp_init(dev, pdp);
579 if (ret)
580 goto fail_bitmap;
581
582 ret = setup_px(dev, pdp);
583 if (ret)
584 goto fail_page_m;
585
586 return pdp;
587
588fail_page_m:
589 __pdp_fini(pdp);
590fail_bitmap:
591 kfree(pdp);
592
593 return ERR_PTR(ret);
594}
595
6ac18502
MT		 596static void free_pdp(struct drm_device *dev,
597 struct i915_page_directory_pointer *pdp)
598{
599 __pdp_fini(pdp);
762d9936
MT		 600 if (USES_FULL_48BIT_PPGTT(dev)) {
601 cleanup_px(dev, pdp);
602 kfree(pdp);
603 }
604}
605
69ab76fd
MT		 606static void gen8_initialize_pdp(struct i915_address_space *vm,
607 struct i915_page_directory_pointer *pdp)
608{
609 gen8_ppgtt_pdpe_t scratch_pdpe;
610
611 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
612
613 fill_px(vm->dev, pdp, scratch_pdpe);
614}
615
616static void gen8_initialize_pml4(struct i915_address_space *vm,
617 struct i915_pml4 *pml4)
618{
619 gen8_ppgtt_pml4e_t scratch_pml4e;
620
621 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
622 I915_CACHE_LLC);
623
624 fill_px(vm->dev, pml4, scratch_pml4e);
625}
626
762d9936
MT		 627static void
628gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
629 struct i915_page_directory_pointer *pdp,
630 struct i915_page_directory *pd,
631 int index)
632{
633 gen8_ppgtt_pdpe_t *page_directorypo;
634
635 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
636 return;
637
638 page_directorypo = kmap_px(pdp);
639 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
640 kunmap_px(ppgtt, page_directorypo);
641}
642
643static void
644gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
645 struct i915_pml4 *pml4,
646 struct i915_page_directory_pointer *pdp,
647 int index)
648{
649 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
650
651 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
652 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
653 kunmap_px(ppgtt, pagemap);
6ac18502
MT		 654}
655
94e409c1 656/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 657static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 658 unsigned entry,
659 dma_addr_t addr)
94e409c1 660{
4a570db5 661 struct intel_engine_cs *engine = req->engine;
94e409c1
BW		 662 int ret;
663
664 BUG_ON(entry >= 4);
665
5fb9de1a 666 ret = intel_ring_begin(req, 6);
94e409c1
BW		 667 if (ret)
668 return ret;
669
e2f80391
TU		 670 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
671 intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
672 intel_ring_emit(engine, upper_32_bits(addr));
673 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
674 intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
675 intel_ring_emit(engine, lower_32_bits(addr));
676 intel_ring_advance(engine);
94e409c1
BW		 677
678 return 0;
679}
680
2dba3239
MT		 681static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
682 struct drm_i915_gem_request *req)
94e409c1 683{
eeb9488e 684 int i, ret;
94e409c1 685
7cb6d7ac 686 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 687 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
688
e85b26dc 689 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 690 if (ret)
691 return ret;
94e409c1 692 }
d595bd4b 693
eeb9488e 694 return 0;
94e409c1
BW		 695}
696
2dba3239
MT		 697static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
698 struct drm_i915_gem_request *req)
699{
700 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
701}
702
f9b5b782
MT		 703static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
704 struct i915_page_directory_pointer *pdp,
705 uint64_t start,
706 uint64_t length,
707 gen8_pte_t scratch_pte)
459108b8
BW		 708{
709 struct i915_hw_ppgtt *ppgtt =
710 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782 711 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 712 unsigned pdpe = gen8_pdpe_index(start);
713 unsigned pde = gen8_pde_index(start);
714 unsigned pte = gen8_pte_index(start);
782f1495 715 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 716 unsigned last_pte, i;
717
f9b5b782
MT		 718 if (WARN_ON(!pdp))
719 return;
459108b8
BW		 720
721 while (num_entries) {
ec565b3c
MT		 722 struct i915_page_directory *pd;
723 struct i915_page_table *pt;
06fda602 724
d4ec9da0 725 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 726 break;
06fda602 727
d4ec9da0 728 pd = pdp->page_directory[pdpe];
06fda602
BW		 729
730 if (WARN_ON(!pd->page_table[pde]))
00245266 731 break;
06fda602
BW		 732
733 pt = pd->page_table[pde];
734
567047be 735 if (WARN_ON(!px_page(pt)))
00245266 736 break;
06fda602 737
7ad47cf2 738 last_pte = pte + num_entries;
07749ef3
MT		 739 if (last_pte > GEN8_PTES)
740 last_pte = GEN8_PTES;
459108b8 741
d1c54acd 742 pt_vaddr = kmap_px(pt);
459108b8 743
7ad47cf2 744 for (i = pte; i < last_pte; i++) {
459108b8 745 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 746 num_entries--;
747 }
459108b8 748
d1c54acd 749 kunmap_px(ppgtt, pt);
459108b8 750
7ad47cf2 751 pte = 0;
07749ef3 752 if (++pde == I915_PDES) {
de5ba8eb
MT		 753 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
754 break;
7ad47cf2
BW		 755 pde = 0;
756 }
459108b8
BW		 757 }
758}
759
f9b5b782
MT		 760static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
761 uint64_t start,
762 uint64_t length,
763 bool use_scratch)
9df15b49
BW		 764{
765 struct i915_hw_ppgtt *ppgtt =
766 container_of(vm, struct i915_hw_ppgtt, base);
f9b5b782
MT		 767 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
768 I915_CACHE_LLC, use_scratch);
769
de5ba8eb
MT		 770 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
771 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
772 scratch_pte);
773 } else {
e8ebd8e2 774 uint64_t pml4e;
de5ba8eb
MT		 775 struct i915_page_directory_pointer *pdp;
776
e8ebd8e2 777 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 778 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
779 scratch_pte);
780 }
781 }
f9b5b782
MT		 782}
783
784static void
785gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
786 struct i915_page_directory_pointer *pdp,
3387d433 787 struct sg_page_iter *sg_iter,
f9b5b782
MT		 788 uint64_t start,
789 enum i915_cache_level cache_level)
790{
791 struct i915_hw_ppgtt *ppgtt =
792 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 793 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 794 unsigned pdpe = gen8_pdpe_index(start);
795 unsigned pde = gen8_pde_index(start);
796 unsigned pte = gen8_pte_index(start);
9df15b49 797
6f1cc993 798 pt_vaddr = NULL;
7ad47cf2 799
3387d433 800 while (__sg_page_iter_next(sg_iter)) {
d7b3de91 801 if (pt_vaddr == NULL) {
d4ec9da0 802 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 803 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 804 pt_vaddr = kmap_px(pt);
d7b3de91 805 }
9df15b49 806
7ad47cf2 807 pt_vaddr[pte] =
3387d433 808 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
6f1cc993 809 cache_level, true);
07749ef3 810 if (++pte == GEN8_PTES) {
d1c54acd 811 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 812 pt_vaddr = NULL;
07749ef3 813 if (++pde == I915_PDES) {
de5ba8eb
MT		 814 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
815 break;
7ad47cf2
BW		 816 pde = 0;
817 }
818 pte = 0;
9df15b49
BW		 819 }
820 }
d1c54acd
MK		 821
822 if (pt_vaddr)
823 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 824}
825
f9b5b782
MT		 826static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
827 struct sg_table *pages,
828 uint64_t start,
829 enum i915_cache_level cache_level,
830 u32 unused)
831{
832 struct i915_hw_ppgtt *ppgtt =
833 container_of(vm, struct i915_hw_ppgtt, base);
3387d433 834 struct sg_page_iter sg_iter;
f9b5b782 835
3387d433 836 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
de5ba8eb
MT		 837
838 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
839 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
840 cache_level);
841 } else {
842 struct i915_page_directory_pointer *pdp;
e8ebd8e2 843 uint64_t pml4e;
de5ba8eb
MT		 844 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
845
e8ebd8e2 846 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 847 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
848 start, cache_level);
849 }
850 }
f9b5b782
MT		 851}
852
f37c0505
MT		 853static void gen8_free_page_tables(struct drm_device *dev,
854 struct i915_page_directory *pd)
7ad47cf2
BW		 855{
856 int i;
857
567047be 858 if (!px_page(pd))
7ad47cf2
BW		 859 return;
860
33c8819f 861 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 862 if (WARN_ON(!pd->page_table[i]))
863 continue;
7ad47cf2 864
a08e111a 865 free_pt(dev, pd->page_table[i]);
06fda602
BW		 866 pd->page_table[i] = NULL;
867 }
d7b3de91
BW		 868}
869
8776f02b
MK		 870static int gen8_init_scratch(struct i915_address_space *vm)
871{
872 struct drm_device *dev = vm->dev;
873
874 vm->scratch_page = alloc_scratch_page(dev);
875 if (IS_ERR(vm->scratch_page))
876 return PTR_ERR(vm->scratch_page);
877
878 vm->scratch_pt = alloc_pt(dev);
879 if (IS_ERR(vm->scratch_pt)) {
880 free_scratch_page(dev, vm->scratch_page);
881 return PTR_ERR(vm->scratch_pt);
882 }
883
884 vm->scratch_pd = alloc_pd(dev);
885 if (IS_ERR(vm->scratch_pd)) {
886 free_pt(dev, vm->scratch_pt);
887 free_scratch_page(dev, vm->scratch_page);
888 return PTR_ERR(vm->scratch_pd);
889 }
890
69ab76fd
MT		 891 if (USES_FULL_48BIT_PPGTT(dev)) {
892 vm->scratch_pdp = alloc_pdp(dev);
893 if (IS_ERR(vm->scratch_pdp)) {
894 free_pd(dev, vm->scratch_pd);
895 free_pt(dev, vm->scratch_pt);
896 free_scratch_page(dev, vm->scratch_page);
897 return PTR_ERR(vm->scratch_pdp);
898 }
899 }
900
8776f02b
MK		 901 gen8_initialize_pt(vm, vm->scratch_pt);
902 gen8_initialize_pd(vm, vm->scratch_pd);
69ab76fd
MT		 903 if (USES_FULL_48BIT_PPGTT(dev))
904 gen8_initialize_pdp(vm, vm->scratch_pdp);
8776f02b
MK		 905
906 return 0;
907}
908
650da34c
ZL		 909static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
910{
911 enum vgt_g2v_type msg;
912 struct drm_device *dev = ppgtt->base.dev;
913 struct drm_i915_private *dev_priv = dev->dev_private;
650da34c
ZL		 914 int i;
915
916 if (USES_FULL_48BIT_PPGTT(dev)) {
917 u64 daddr = px_dma(&ppgtt->pml4);
918
ab75bb5d
VS		 919 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
920 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
650da34c
ZL		 921
922 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
923 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
924 } else {
925 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
926 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
927
ab75bb5d
VS		 928 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
929 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
650da34c
ZL		 930 }
931
932 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
933 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
934 }
935
936 I915_WRITE(vgtif_reg(g2v_notify), msg);
937
938 return 0;
939}
940
8776f02b
MK		 941static void gen8_free_scratch(struct i915_address_space *vm)
942{
943 struct drm_device *dev = vm->dev;
944
69ab76fd
MT		 945 if (USES_FULL_48BIT_PPGTT(dev))
946 free_pdp(dev, vm->scratch_pdp);
8776f02b
MK		 947 free_pd(dev, vm->scratch_pd);
948 free_pt(dev, vm->scratch_pt);
949 free_scratch_page(dev, vm->scratch_page);
950}
951
762d9936
MT		 952static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
953 struct i915_page_directory_pointer *pdp)
b45a6715
BW		 954{
955 int i;
956
d4ec9da0
MT		 957 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
958 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 959 continue;
960
d4ec9da0
MT		 961 gen8_free_page_tables(dev, pdp->page_directory[i]);
962 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 963 }
69876bed 964
d4ec9da0 965 free_pdp(dev, pdp);
762d9936
MT		 966}
967
968static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
969{
970 int i;
971
972 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
973 if (WARN_ON(!ppgtt->pml4.pdps[i]))
974 continue;
975
976 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
977 }
978
979 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
980}
981
982static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
983{
984 struct i915_hw_ppgtt *ppgtt =
985 container_of(vm, struct i915_hw_ppgtt, base);
986
650da34c
ZL		 987 if (intel_vgpu_active(vm->dev))
988 gen8_ppgtt_notify_vgt(ppgtt, false);
989
762d9936
MT		 990 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
991 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
992 else
993 gen8_ppgtt_cleanup_4lvl(ppgtt);
d4ec9da0 994
8776f02b 995 gen8_free_scratch(vm);
b45a6715
BW		 996}
997
d7b2633d
MT		 998/**
999 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 1000 * @vm: Master vm structure.
1001 * @pd: Page directory for this address range.
d7b2633d 1002 * @start: Starting virtual address to begin allocations.
d4ec9da0 1003 * @length: Size of the allocations.
d7b2633d
MT		 1004 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1005 * caller to free on error.
1006 *
1007 * Allocate the required number of page tables. Extremely similar to
1008 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1009 * the page directory boundary (instead of the page directory pointer). That
1010 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1011 * possible, and likely that the caller will need to use multiple calls of this
1012 * function to achieve the appropriate allocation.
1013 *
1014 * Return: 0 if success; negative error code otherwise.
1015 */
d4ec9da0 1016static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 1017 struct i915_page_directory *pd,
5441f0cb 1018 uint64_t start,
d7b2633d
MT		 1019 uint64_t length,
1020 unsigned long *new_pts)
bf2b4ed2 1021{
d4ec9da0 1022 struct drm_device *dev = vm->dev;
d7b2633d 1023 struct i915_page_table *pt;
5441f0cb 1024 uint32_t pde;
bf2b4ed2 1025
e8ebd8e2 1026 gen8_for_each_pde(pt, pd, start, length, pde) {
d7b2633d 1027 /* Don't reallocate page tables */
6ac18502 1028 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 1029 /* Scratch is never allocated this way */
d4ec9da0 1030 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 1031 continue;
1032 }
1033
8a1ebd74 1034 pt = alloc_pt(dev);
d7b2633d 1035 if (IS_ERR(pt))
5441f0cb
MT		 1036 goto unwind_out;
1037
d4ec9da0 1038 gen8_initialize_pt(vm, pt);
d7b2633d 1039 pd->page_table[pde] = pt;
966082c9 1040 __set_bit(pde, new_pts);
4c06ec8d 1041 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 1042 }
1043
bf2b4ed2 1044 return 0;
7ad47cf2
BW		 1045
1046unwind_out:
d7b2633d 1047 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 1048 free_pt(dev, pd->page_table[pde]);
7ad47cf2 1049
d7b3de91 1050 return -ENOMEM;
bf2b4ed2
BW		 1051}
1052
d7b2633d
MT		 1053/**
1054 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 1055 * @vm: Master vm structure.
d7b2633d
MT		 1056 * @pdp: Page directory pointer for this address range.
1057 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 1058 * @length: Size of the allocations.
1059 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 1060 * caller to free on error.
1061 *
1062 * Allocate the required number of page directories starting at the pde index of
1063 * @start, and ending at the pde index @start + @length. This function will skip
1064 * over already allocated page directories within the range, and only allocate
1065 * new ones, setting the appropriate pointer within the pdp as well as the
1066 * correct position in the bitmap @new_pds.
1067 *
1068 * The function will only allocate the pages within the range for a give page
1069 * directory pointer. In other words, if @start + @length straddles a virtually
1070 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1071 * required by the caller, This is not currently possible, and the BUG in the
1072 * code will prevent it.
1073 *
1074 * Return: 0 if success; negative error code otherwise.
1075 */
d4ec9da0
MT		 1076static int
1077gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1078 struct i915_page_directory_pointer *pdp,
1079 uint64_t start,
1080 uint64_t length,
1081 unsigned long *new_pds)
bf2b4ed2 1082{
d4ec9da0 1083 struct drm_device *dev = vm->dev;
d7b2633d 1084 struct i915_page_directory *pd;
69876bed 1085 uint32_t pdpe;
6ac18502 1086 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 1087
6ac18502 1088 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 1089
e8ebd8e2 1090 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
6ac18502 1091 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 1092 continue;
33c8819f 1093
8a1ebd74 1094 pd = alloc_pd(dev);
d7b2633d 1095 if (IS_ERR(pd))
d7b3de91 1096 goto unwind_out;
69876bed 1097
d4ec9da0 1098 gen8_initialize_pd(vm, pd);
d7b2633d 1099 pdp->page_directory[pdpe] = pd;
966082c9 1100 __set_bit(pdpe, new_pds);
4c06ec8d 1101 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 1102 }
1103
bf2b4ed2 1104 return 0;
d7b3de91
BW		 1105
1106unwind_out:
6ac18502 1107 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 1108 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 1109
1110 return -ENOMEM;
bf2b4ed2
BW		 1111}
1112
762d9936
MT		 1113/**
1114 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1115 * @vm: Master vm structure.
1116 * @pml4: Page map level 4 for this address range.
1117 * @start: Starting virtual address to begin allocations.
1118 * @length: Size of the allocations.
1119 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1120 * caller to free on error.
1121 *
1122 * Allocate the required number of page directory pointers. Extremely similar to
1123 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1124 * The main difference is here we are limited by the pml4 boundary (instead of
1125 * the page directory pointer).
1126 *
1127 * Return: 0 if success; negative error code otherwise.
1128 */
1129static int
1130gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1131 struct i915_pml4 *pml4,
1132 uint64_t start,
1133 uint64_t length,
1134 unsigned long *new_pdps)
1135{
1136 struct drm_device *dev = vm->dev;
1137 struct i915_page_directory_pointer *pdp;
762d9936
MT		 1138 uint32_t pml4e;
1139
1140 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1141
e8ebd8e2 1142 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1143 if (!test_bit(pml4e, pml4->used_pml4es)) {
1144 pdp = alloc_pdp(dev);
1145 if (IS_ERR(pdp))
1146 goto unwind_out;
1147
69ab76fd 1148 gen8_initialize_pdp(vm, pdp);
762d9936
MT		 1149 pml4->pdps[pml4e] = pdp;
1150 __set_bit(pml4e, new_pdps);
1151 trace_i915_page_directory_pointer_entry_alloc(vm,
1152 pml4e,
1153 start,
1154 GEN8_PML4E_SHIFT);
1155 }
1156 }
1157
1158 return 0;
1159
1160unwind_out:
1161 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1162 free_pdp(dev, pml4->pdps[pml4e]);
1163
1164 return -ENOMEM;
1165}
1166
d7b2633d 1167static void
3a41a05d 1168free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
d7b2633d 1169{
d7b2633d
MT		 1170 kfree(new_pts);
1171 kfree(new_pds);
1172}
1173
1174/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1175 * of these are based on the number of PDPEs in the system.
1176 */
1177static
1178int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
3a41a05d 1179 unsigned long **new_pts,
6ac18502 1180 uint32_t pdpes)
d7b2633d 1181{
d7b2633d 1182 unsigned long *pds;
3a41a05d 1183 unsigned long *pts;
d7b2633d 1184
3a41a05d 1185 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
d7b2633d
MT		 1186 if (!pds)
1187 return -ENOMEM;
1188
3a41a05d
MW		 1189 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1190 GFP_TEMPORARY);
1191 if (!pts)
1192 goto err_out;
d7b2633d
MT		 1193
1194 *new_pds = pds;
1195 *new_pts = pts;
1196
1197 return 0;
1198
1199err_out:
3a41a05d 1200 free_gen8_temp_bitmaps(pds, pts);
d7b2633d
MT		 1201 return -ENOMEM;
1202}
1203
5b7e4c9c
MK		 1204/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1205 * the page table structures, we mark them dirty so that
1206 * context switching/execlist queuing code takes extra steps
1207 * to ensure that tlbs are flushed.
1208 */
1209static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1210{
1211 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1212}
1213
762d9936
MT		 1214static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1215 struct i915_page_directory_pointer *pdp,
1216 uint64_t start,
1217 uint64_t length)
bf2b4ed2 1218{
e5815a2e
MT		 1219 struct i915_hw_ppgtt *ppgtt =
1220 container_of(vm, struct i915_hw_ppgtt, base);
3a41a05d 1221 unsigned long *new_page_dirs, *new_page_tables;
d4ec9da0 1222 struct drm_device *dev = vm->dev;
5441f0cb 1223 struct i915_page_directory *pd;
33c8819f
MT		 1224 const uint64_t orig_start = start;
1225 const uint64_t orig_length = length;
5441f0cb 1226 uint32_t pdpe;
d4ec9da0 1227 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 1228 int ret;
1229
d7b2633d
MT		 1230 /* Wrap is never okay since we can only represent 48b, and we don't
1231 * actually use the other side of the canonical address space.
1232 */
1233 if (WARN_ON(start + length < start))
a05d80ee
MK		 1234 return -ENODEV;
1235
d4ec9da0 1236 if (WARN_ON(start + length > vm->total))
a05d80ee 1237 return -ENODEV;
d7b2633d 1238
6ac18502 1239 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1240 if (ret)
1241 return ret;
1242
d7b2633d 1243 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1244 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1245 new_page_dirs);
d7b2633d 1246 if (ret) {
3a41a05d 1247 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
d7b2633d
MT		 1248 return ret;
1249 }
1250
1251 /* For every page directory referenced, allocate page tables */
e8ebd8e2 1252 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d4ec9da0 1253 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
3a41a05d 1254 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
5441f0cb
MT		 1255 if (ret)
1256 goto err_out;
5441f0cb
MT		 1257 }
1258
33c8819f
MT		 1259 start = orig_start;
1260 length = orig_length;
1261
d7b2633d
MT		 1262 /* Allocations have completed successfully, so set the bitmaps, and do
1263 * the mappings. */
e8ebd8e2 1264 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d1c54acd 1265 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1266 struct i915_page_table *pt;
09120d4e 1267 uint64_t pd_len = length;
33c8819f
MT		 1268 uint64_t pd_start = start;
1269 uint32_t pde;
1270
d7b2633d
MT		 1271 /* Every pd should be allocated, we just did that above. */
1272 WARN_ON(!pd);
1273
e8ebd8e2 1274 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
d7b2633d
MT		 1275 /* Same reasoning as pd */
1276 WARN_ON(!pt);
1277 WARN_ON(!pd_len);
1278 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1279
1280 /* Set our used ptes within the page table */
1281 bitmap_set(pt->used_ptes,
1282 gen8_pte_index(pd_start),
1283 gen8_pte_count(pd_start, pd_len));
1284
1285 /* Our pde is now pointing to the pagetable, pt */
966082c9 1286 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1287
1288 /* Map the PDE to the page table */
fe36f55d
MK		 1289 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1290 I915_CACHE_LLC);
4c06ec8d
MT		 1291 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1292 gen8_pte_index(start),
1293 gen8_pte_count(start, length),
1294 GEN8_PTES);
d7b2633d
MT		 1295
1296 /* NB: We haven't yet mapped ptes to pages. At this
1297 * point we're still relying on insert_entries() */
33c8819f 1298 }
d7b2633d 1299
d1c54acd 1300 kunmap_px(ppgtt, page_directory);
d4ec9da0 1301 __set_bit(pdpe, pdp->used_pdpes);
762d9936 1302 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
33c8819f
MT		 1303 }
1304
3a41a05d 1305 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1306 mark_tlbs_dirty(ppgtt);
d7b3de91 1307 return 0;
bf2b4ed2 1308
d7b3de91 1309err_out:
d7b2633d 1310 while (pdpe--) {
e8ebd8e2
DG		 1311 unsigned long temp;
1312
3a41a05d
MW		 1313 for_each_set_bit(temp, new_page_tables + pdpe *
1314 BITS_TO_LONGS(I915_PDES), I915_PDES)
d4ec9da0 1315 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1316 }
1317
6ac18502 1318 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1319 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1320
3a41a05d 1321 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1322 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1323 return ret;
1324}
1325
762d9936
MT		 1326static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1327 struct i915_pml4 *pml4,
1328 uint64_t start,
1329 uint64_t length)
1330{
1331 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1332 struct i915_hw_ppgtt *ppgtt =
1333 container_of(vm, struct i915_hw_ppgtt, base);
1334 struct i915_page_directory_pointer *pdp;
e8ebd8e2 1335 uint64_t pml4e;
762d9936
MT		 1336 int ret = 0;
1337
1338 /* Do the pml4 allocations first, so we don't need to track the newly
1339 * allocated tables below the pdp */
1340 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1341
1342 /* The pagedirectory and pagetable allocations are done in the shared 3
1343 * and 4 level code. Just allocate the pdps.
1344 */
1345 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1346 new_pdps);
1347 if (ret)
1348 return ret;
1349
1350 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1351 "The allocation has spanned more than 512GB. "
1352 "It is highly likely this is incorrect.");
1353
e8ebd8e2 1354 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1355 WARN_ON(!pdp);
1356
1357 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1358 if (ret)
1359 goto err_out;
1360
1361 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1362 }
1363
1364 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1365 GEN8_PML4ES_PER_PML4);
1366
1367 return 0;
1368
1369err_out:
1370 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1371 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1372
1373 return ret;
1374}
1375
1376static int gen8_alloc_va_range(struct i915_address_space *vm,
1377 uint64_t start, uint64_t length)
1378{
1379 struct i915_hw_ppgtt *ppgtt =
1380 container_of(vm, struct i915_hw_ppgtt, base);
1381
1382 if (USES_FULL_48BIT_PPGTT(vm->dev))
1383 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1384 else
1385 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1386}
1387
ea91e401
MT		 1388static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1389 uint64_t start, uint64_t length,
1390 gen8_pte_t scratch_pte,
1391 struct seq_file *m)
1392{
1393 struct i915_page_directory *pd;
ea91e401
MT		 1394 uint32_t pdpe;
1395
e8ebd8e2 1396 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
ea91e401
MT		 1397 struct i915_page_table *pt;
1398 uint64_t pd_len = length;
1399 uint64_t pd_start = start;
1400 uint32_t pde;
1401
1402 if (!test_bit(pdpe, pdp->used_pdpes))
1403 continue;
1404
1405 seq_printf(m, "\tPDPE #%d\n", pdpe);
e8ebd8e2 1406 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
ea91e401
MT		 1407 uint32_t pte;
1408 gen8_pte_t *pt_vaddr;
1409
1410 if (!test_bit(pde, pd->used_pdes))
1411 continue;
1412
1413 pt_vaddr = kmap_px(pt);
1414 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1415 uint64_t va =
1416 (pdpe << GEN8_PDPE_SHIFT) |
1417 (pde << GEN8_PDE_SHIFT) |
1418 (pte << GEN8_PTE_SHIFT);
1419 int i;
1420 bool found = false;
1421
1422 for (i = 0; i < 4; i++)
1423 if (pt_vaddr[pte + i] != scratch_pte)
1424 found = true;
1425 if (!found)
1426 continue;
1427
1428 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1429 for (i = 0; i < 4; i++) {
1430 if (pt_vaddr[pte + i] != scratch_pte)
1431 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1432 else
1433 seq_puts(m, " SCRATCH ");
1434 }
1435 seq_puts(m, "\n");
1436 }
1437 /* don't use kunmap_px, it could trigger
1438 * an unnecessary flush.
1439 */
1440 kunmap_atomic(pt_vaddr);
1441 }
1442 }
1443}
1444
1445static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1446{
1447 struct i915_address_space *vm = &ppgtt->base;
1448 uint64_t start = ppgtt->base.start;
1449 uint64_t length = ppgtt->base.total;
1450 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1451 I915_CACHE_LLC, true);
1452
1453 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1454 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1455 } else {
e8ebd8e2 1456 uint64_t pml4e;
ea91e401
MT		 1457 struct i915_pml4 *pml4 = &ppgtt->pml4;
1458 struct i915_page_directory_pointer *pdp;
1459
e8ebd8e2 1460 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
ea91e401
MT		 1461 if (!test_bit(pml4e, pml4->used_pml4es))
1462 continue;
1463
1464 seq_printf(m, " PML4E #%llu\n", pml4e);
1465 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1466 }
1467 }
1468}
1469
331f38e7
ZL		 1470static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1471{
3a41a05d 1472 unsigned long *new_page_dirs, *new_page_tables;
331f38e7
ZL		 1473 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1474 int ret;
1475
1476 /* We allocate temp bitmap for page tables for no gain
1477 * but as this is for init only, lets keep the things simple
1478 */
1479 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1480 if (ret)
1481 return ret;
1482
1483 /* Allocate for all pdps regardless of how the ppgtt
1484 * was defined.
1485 */
1486 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1487 0, 1ULL << 32,
1488 new_page_dirs);
1489 if (!ret)
1490 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1491
3a41a05d 1492 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
331f38e7
ZL		 1493
1494 return ret;
1495}
1496
eb0b44ad 1497/*
f3a964b9
BW		 1498 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1499 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1500 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1501 * space.
37aca44a 1502 *
f3a964b9 1503 */
5c5f6457 1504static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1505{
8776f02b 1506 int ret;
7cb6d7ac 1507
8776f02b
MK		 1508 ret = gen8_init_scratch(&ppgtt->base);
1509 if (ret)
1510 return ret;
69876bed 1511
d7b2633d 1512 ppgtt->base.start = 0;
d7b2633d 1513 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1514 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1515 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1516 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1517 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1518 ppgtt->base.bind_vma = ppgtt_bind_vma;
ea91e401 1519 ppgtt->debug_dump = gen8_dump_ppgtt;
d7b2633d 1520
762d9936
MT		 1521 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1522 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1523 if (ret)
1524 goto free_scratch;
6ac18502 1525
69ab76fd
MT		 1526 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1527
762d9936 1528 ppgtt->base.total = 1ULL << 48;
2dba3239 1529 ppgtt->switch_mm = gen8_48b_mm_switch;
762d9936 1530 } else {
25f50337 1531 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
81ba8aef
MT		 1532 if (ret)
1533 goto free_scratch;
1534
1535 ppgtt->base.total = 1ULL << 32;
2dba3239 1536 ppgtt->switch_mm = gen8_legacy_mm_switch;
762d9936
MT		 1537 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1538 0, 0,
1539 GEN8_PML4E_SHIFT);
331f38e7
ZL		 1540
1541 if (intel_vgpu_active(ppgtt->base.dev)) {
1542 ret = gen8_preallocate_top_level_pdps(ppgtt);
1543 if (ret)
1544 goto free_scratch;
1545 }
81ba8aef 1546 }
6ac18502 1547
650da34c
ZL		 1548 if (intel_vgpu_active(ppgtt->base.dev))
1549 gen8_ppgtt_notify_vgt(ppgtt, true);
1550
d7b2633d 1551 return 0;
6ac18502
MT		 1552
1553free_scratch:
1554 gen8_free_scratch(&ppgtt->base);
1555 return ret;
d7b2633d
MT		 1556}
1557
87d60b63
BW		 1558static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1559{
87d60b63 1560 struct i915_address_space *vm = &ppgtt->base;
09942c65 1561 struct i915_page_table *unused;
07749ef3 1562 gen6_pte_t scratch_pte;
87d60b63 1563 uint32_t pd_entry;
09942c65
MT		 1564 uint32_t pte, pde, temp;
1565 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1566
79ab9370
MK		 1567 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1568 I915_CACHE_LLC, true, 0);
87d60b63 1569
09942c65 1570 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1571 u32 expected;
07749ef3 1572 gen6_pte_t *pt_vaddr;
567047be 1573 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1574 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1575 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1576
1577 if (pd_entry != expected)
1578 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1579 pde,
1580 pd_entry,
1581 expected);
1582 seq_printf(m, "\tPDE: %x\n", pd_entry);
1583
d1c54acd
MK		 1584 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1585
07749ef3 1586 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1587 unsigned long va =
07749ef3 1588 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1589 (pte * PAGE_SIZE);
1590 int i;
1591 bool found = false;
1592 for (i = 0; i < 4; i++)
1593 if (pt_vaddr[pte + i] != scratch_pte)
1594 found = true;
1595 if (!found)
1596 continue;
1597
1598 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1599 for (i = 0; i < 4; i++) {
1600 if (pt_vaddr[pte + i] != scratch_pte)
1601 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1602 else
1603 seq_puts(m, " SCRATCH ");
1604 }
1605 seq_puts(m, "\n");
1606 }
d1c54acd 1607 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1608 }
1609}
1610
678d96fb 1611/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1612static void gen6_write_pde(struct i915_page_directory *pd,
1613 const int pde, struct i915_page_table *pt)
6197349b 1614{
678d96fb
BW		 1615 /* Caller needs to make sure the write completes if necessary */
1616 struct i915_hw_ppgtt *ppgtt =
1617 container_of(pd, struct i915_hw_ppgtt, pd);
1618 u32 pd_entry;
6197349b 1619
567047be 1620 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1621 pd_entry |= GEN6_PDE_VALID;
6197349b 1622
678d96fb
BW		 1623 writel(pd_entry, ppgtt->pd_addr + pde);
1624}
6197349b 1625
678d96fb
BW		 1626/* Write all the page tables found in the ppgtt structure to incrementing page
1627 * directories. */
1628static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1629 struct i915_page_directory *pd,
678d96fb
BW		 1630 uint32_t start, uint32_t length)
1631{
ec565b3c 1632 struct i915_page_table *pt;
678d96fb
BW		 1633 uint32_t pde, temp;
1634
1635 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1636 gen6_write_pde(pd, pde, pt);
1637
1638 /* Make sure write is complete before other code can use this page
1639 * table. Also require for WC mapped PTEs */
62106b4f 1640 readl(dev_priv->ggtt.gsm);
3e302542
BW		 1641}
1642
b4a74e3a 1643static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1644{
44159ddb 1645 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1646
44159ddb 1647 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1648}
1649
90252e5c 1650static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1651 struct drm_i915_gem_request *req)
90252e5c 1652{
4a570db5 1653 struct intel_engine_cs *engine = req->engine;
90252e5c
BW		 1654 int ret;
1655
90252e5c 1656 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1657 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1658 if (ret)
1659 return ret;
1660
5fb9de1a 1661 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1662 if (ret)
1663 return ret;
1664
e2f80391
TU		 1665 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1666 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1667 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1668 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1669 intel_ring_emit(engine, get_pd_offset(ppgtt));
1670 intel_ring_emit(engine, MI_NOOP);
1671 intel_ring_advance(engine);
90252e5c
BW		 1672
1673 return 0;
1674}
1675
71ba2d64 1676static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1677 struct drm_i915_gem_request *req)
71ba2d64 1678{
4a570db5 1679 struct intel_engine_cs *engine = req->engine;
71ba2d64
YZ		 1680 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1681
e2f80391
TU		 1682 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1683 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
71ba2d64
YZ		 1684 return 0;
1685}
1686
48a10389 1687static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1688 struct drm_i915_gem_request *req)
48a10389 1689{
4a570db5 1690 struct intel_engine_cs *engine = req->engine;
48a10389
BW		 1691 int ret;
1692
48a10389 1693 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1694 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1695 if (ret)
1696 return ret;
1697
5fb9de1a 1698 ret = intel_ring_begin(req, 6);
48a10389
BW		 1699 if (ret)
1700 return ret;
1701
e2f80391
TU		 1702 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1703 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1704 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1705 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1706 intel_ring_emit(engine, get_pd_offset(ppgtt));
1707 intel_ring_emit(engine, MI_NOOP);
1708 intel_ring_advance(engine);
48a10389 1709
90252e5c 1710 /* XXX: RCS is the only one to auto invalidate the TLBs? */
e2f80391
TU		 1711 if (engine->id != RCS) {
1712 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1713 if (ret)
1714 return ret;
1715 }
1716
48a10389
BW		 1717 return 0;
1718}
1719
eeb9488e 1720static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1721 struct drm_i915_gem_request *req)
eeb9488e 1722{
4a570db5 1723 struct intel_engine_cs *engine = req->engine;
eeb9488e
BW		 1724 struct drm_device *dev = ppgtt->base.dev;
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
48a10389 1727
e2f80391
TU		 1728 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1729 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
eeb9488e 1730
e2f80391 1731 POSTING_READ(RING_PP_DIR_DCLV(engine));
eeb9488e
BW		 1732
1733 return 0;
1734}
1735
82460d97 1736static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1737{
eeb9488e 1738 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1739 struct intel_engine_cs *engine;
3e302542 1740
b4ac5afc 1741 for_each_engine(engine, dev_priv) {
2dba3239 1742 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
e2f80391 1743 I915_WRITE(RING_MODE_GEN7(engine),
2dba3239 1744 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
eeb9488e 1745 }
eeb9488e 1746}
6197349b 1747
82460d97 1748static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1749{
50227e1c 1750 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1751 struct intel_engine_cs *engine;
b4a74e3a 1752 uint32_t ecochk, ecobits;
6197349b 1753
b4a74e3a
BW		 1754 ecobits = I915_READ(GAC_ECO_BITS);
1755 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1756
b4a74e3a
BW		 1757 ecochk = I915_READ(GAM_ECOCHK);
1758 if (IS_HASWELL(dev)) {
1759 ecochk |= ECOCHK_PPGTT_WB_HSW;
1760 } else {
1761 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1762 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1763 }
1764 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1765
b4ac5afc 1766 for_each_engine(engine, dev_priv) {
6197349b 1767 /* GFX_MODE is per-ring on gen7+ */
e2f80391 1768 I915_WRITE(RING_MODE_GEN7(engine),
b4a74e3a 1769 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1770 }
b4a74e3a 1771}
6197349b 1772
82460d97 1773static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1774{
50227e1c 1775 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1776 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1777
b4a74e3a
BW		 1778 ecobits = I915_READ(GAC_ECO_BITS);
1779 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1780 ECOBITS_PPGTT_CACHE64B);
6197349b 1781
b4a74e3a
BW		 1782 gab_ctl = I915_READ(GAB_CTL);
1783 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1784
1785 ecochk = I915_READ(GAM_ECOCHK);
1786 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1787
1788 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1789}
1790
1d2a314c 1791/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1792static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1793 uint64_t start,
1794 uint64_t length,
828c7908 1795 bool use_scratch)
1d2a314c 1796{
853ba5d2
BW		 1797 struct i915_hw_ppgtt *ppgtt =
1798 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1799 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1800 unsigned first_entry = start >> PAGE_SHIFT;
1801 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1802 unsigned act_pt = first_entry / GEN6_PTES;
1803 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1804 unsigned last_pte, i;
1d2a314c 1805
c114f76a
MK		 1806 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1807 I915_CACHE_LLC, true, 0);
1d2a314c 1808
7bddb01f
DV		 1809 while (num_entries) {
1810 last_pte = first_pte + num_entries;
07749ef3
MT		 1811 if (last_pte > GEN6_PTES)
1812 last_pte = GEN6_PTES;
7bddb01f 1813
d1c54acd 1814 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1815
7bddb01f
DV		 1816 for (i = first_pte; i < last_pte; i++)
1817 pt_vaddr[i] = scratch_pte;
1d2a314c 1818
d1c54acd 1819 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1820
7bddb01f
DV		 1821 num_entries -= last_pte - first_pte;
1822 first_pte = 0;
a15326a5 1823 act_pt++;
7bddb01f 1824 }
1d2a314c
DV		 1825}
1826
853ba5d2 1827static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1828 struct sg_table *pages,
782f1495 1829 uint64_t start,
24f3a8cf 1830 enum i915_cache_level cache_level, u32 flags)
def886c3 1831{
853ba5d2
BW		 1832 struct i915_hw_ppgtt *ppgtt =
1833 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1834 gen6_pte_t *pt_vaddr;
782f1495 1835 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1836 unsigned act_pt = first_entry / GEN6_PTES;
1837 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1838 struct sg_page_iter sg_iter;
1839
cc79714f 1840 pt_vaddr = NULL;
6e995e23 1841 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1842 if (pt_vaddr == NULL)
d1c54acd 1843 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1844
cc79714f
CW		 1845 pt_vaddr[act_pte] =
1846 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1847 cache_level, true, flags);
1848
07749ef3 1849 if (++act_pte == GEN6_PTES) {
d1c54acd 1850 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1851 pt_vaddr = NULL;
a15326a5 1852 act_pt++;
6e995e23 1853 act_pte = 0;
def886c3 1854 }
def886c3 1855 }
cc79714f 1856 if (pt_vaddr)
d1c54acd 1857 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1858}
1859
678d96fb 1860static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1861 uint64_t start_in, uint64_t length_in)
678d96fb 1862{
4933d519
MT		 1863 DECLARE_BITMAP(new_page_tables, I915_PDES);
1864 struct drm_device *dev = vm->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1866 struct i915_hw_ppgtt *ppgtt =
1867 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1868 struct i915_page_table *pt;
a05d80ee 1869 uint32_t start, length, start_save, length_save;
678d96fb 1870 uint32_t pde, temp;
4933d519
MT		 1871 int ret;
1872
a05d80ee
MK		 1873 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1874 return -ENODEV;
1875
1876 start = start_save = start_in;
1877 length = length_save = length_in;
4933d519
MT		 1878
1879 bitmap_zero(new_page_tables, I915_PDES);
1880
1881 /* The allocation is done in two stages so that we can bail out with
1882 * minimal amount of pain. The first stage finds new page tables that
1883 * need allocation. The second stage marks use ptes within the page
1884 * tables.
1885 */
1886 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1887 if (pt != vm->scratch_pt) {
4933d519
MT		 1888 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1889 continue;
1890 }
1891
1892 /* We've already allocated a page table */
1893 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1894
8a1ebd74 1895 pt = alloc_pt(dev);
4933d519
MT		 1896 if (IS_ERR(pt)) {
1897 ret = PTR_ERR(pt);
1898 goto unwind_out;
1899 }
1900
1901 gen6_initialize_pt(vm, pt);
1902
1903 ppgtt->pd.page_table[pde] = pt;
966082c9 1904 __set_bit(pde, new_page_tables);
72744cb1 1905 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1906 }
1907
1908 start = start_save;
1909 length = length_save;
678d96fb
BW		 1910
1911 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1912 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1913
1914 bitmap_zero(tmp_bitmap, GEN6_PTES);
1915 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1916 gen6_pte_count(start, length));
1917
966082c9 1918 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1919 gen6_write_pde(&ppgtt->pd, pde, pt);
1920
72744cb1
MT		 1921 trace_i915_page_table_entry_map(vm, pde, pt,
1922 gen6_pte_index(start),
1923 gen6_pte_count(start, length),
1924 GEN6_PTES);
4933d519 1925 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1926 GEN6_PTES);
1927 }
1928
4933d519
MT		 1929 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1930
1931 /* Make sure write is complete before other code can use this page
1932 * table. Also require for WC mapped PTEs */
62106b4f 1933 readl(dev_priv->ggtt.gsm);
4933d519 1934
563222a7 1935 mark_tlbs_dirty(ppgtt);
678d96fb 1936 return 0;
4933d519
MT		 1937
1938unwind_out:
1939 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1940 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1941
79ab9370 1942 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1943 free_pt(vm->dev, pt);
4933d519
MT		 1944 }
1945
1946 mark_tlbs_dirty(ppgtt);
1947 return ret;
678d96fb
BW		 1948}
1949
8776f02b
MK		 1950static int gen6_init_scratch(struct i915_address_space *vm)
1951{
1952 struct drm_device *dev = vm->dev;
1953
1954 vm->scratch_page = alloc_scratch_page(dev);
1955 if (IS_ERR(vm->scratch_page))
1956 return PTR_ERR(vm->scratch_page);
1957
1958 vm->scratch_pt = alloc_pt(dev);
1959 if (IS_ERR(vm->scratch_pt)) {
1960 free_scratch_page(dev, vm->scratch_page);
1961 return PTR_ERR(vm->scratch_pt);
1962 }
1963
1964 gen6_initialize_pt(vm, vm->scratch_pt);
1965
1966 return 0;
1967}
1968
1969static void gen6_free_scratch(struct i915_address_space *vm)
1970{
1971 struct drm_device *dev = vm->dev;
1972
1973 free_pt(dev, vm->scratch_pt);
1974 free_scratch_page(dev, vm->scratch_page);
1975}
1976
061dd493 1977static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1978{
061dd493
DV		 1979 struct i915_hw_ppgtt *ppgtt =
1980 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT		 1981 struct i915_page_table *pt;
1982 uint32_t pde;
4933d519 1983
061dd493
DV		 1984 drm_mm_remove_node(&ppgtt->node);
1985
09942c65 1986 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1987 if (pt != vm->scratch_pt)
a08e111a 1988 free_pt(ppgtt->base.dev, pt);
4933d519 1989 }
06fda602 1990
8776f02b 1991 gen6_free_scratch(vm);
3440d265
DV		 1992}
1993
b146520f 1994static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1995{
8776f02b 1996 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1997 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1998 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1999 bool retried = false;
b146520f 2000 int ret;
1d2a314c 2001
c8d4c0d6
BW		 2002 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2003 * allocator works in address space sizes, so it's multiplied by page
2004 * size. We allocate at the top of the GTT to avoid fragmentation.
2005 */
62106b4f 2006 BUG_ON(!drm_mm_initialized(&dev_priv->ggtt.base.mm));
4933d519 2007
8776f02b
MK		 2008 ret = gen6_init_scratch(vm);
2009 if (ret)
2010 return ret;
4933d519 2011
e3cc1995 2012alloc:
62106b4f 2013 ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,
c8d4c0d6
BW		 2014 &ppgtt->node, GEN6_PD_SIZE,
2015 GEN6_PD_ALIGN, 0,
62106b4f 2016 0, dev_priv->ggtt.base.total,
3e8b5ae9 2017 DRM_MM_TOPDOWN);
e3cc1995 2018 if (ret == -ENOSPC && !retried) {
62106b4f 2019 ret = i915_gem_evict_something(dev, &dev_priv->ggtt.base,
e3cc1995 2020 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c 2021 I915_CACHE_NONE,
62106b4f 2022 0, dev_priv->ggtt.base.total,
d23db88c 2023 0);
e3cc1995 2024 if (ret)
678d96fb 2025 goto err_out;
e3cc1995
BW		 2026
2027 retried = true;
2028 goto alloc;
2029 }
c8d4c0d6 2030
c8c26622 2031 if (ret)
678d96fb
BW		 2032 goto err_out;
2033
c8c26622 2034
62106b4f 2035 if (ppgtt->node.start < dev_priv->ggtt.mappable_end)
c8d4c0d6 2036 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 2037
c8c26622 2038 return 0;
678d96fb
BW		 2039
2040err_out:
8776f02b 2041 gen6_free_scratch(vm);
678d96fb 2042 return ret;
b146520f
BW		 2043}
2044
b146520f
BW		 2045static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2046{
2f2cf682 2047 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 2048}
06dc68d6 2049
4933d519
MT		 2050static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2051 uint64_t start, uint64_t length)
2052{
ec565b3c 2053 struct i915_page_table *unused;
4933d519 2054 uint32_t pde, temp;
1d2a314c 2055
4933d519 2056 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 2057 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 2058}
2059
5c5f6457 2060static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 2061{
2062 struct drm_device *dev = ppgtt->base.dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 int ret;
2065
62106b4f 2066 ppgtt->base.pte_encode = dev_priv->ggtt.base.pte_encode;
b146520f 2067 if (IS_GEN6(dev)) {
b146520f
BW		 2068 ppgtt->switch_mm = gen6_mm_switch;
2069 } else if (IS_HASWELL(dev)) {
b146520f
BW		 2070 ppgtt->switch_mm = hsw_mm_switch;
2071 } else if (IS_GEN7(dev)) {
b146520f
BW		 2072 ppgtt->switch_mm = gen7_mm_switch;
2073 } else
2074 BUG();
2075
71ba2d64
YZ		 2076 if (intel_vgpu_active(dev))
2077 ppgtt->switch_mm = vgpu_mm_switch;
2078
b146520f
BW		 2079 ret = gen6_ppgtt_alloc(ppgtt);
2080 if (ret)
2081 return ret;
2082
5c5f6457 2083 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 2084 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2085 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 2086 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2087 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 2088 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 2089 ppgtt->base.start = 0;
09942c65 2090 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 2091 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 2092
44159ddb 2093 ppgtt->pd.base.ggtt_offset =
07749ef3 2094 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 2095
62106b4f 2096 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
44159ddb 2097 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 2098
5c5f6457 2099 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 2100
678d96fb
BW		 2101 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2102
440fd528 2103 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 2104 ppgtt->node.size >> 20,
2105 ppgtt->node.start / PAGE_SIZE);
3440d265 2106
fa76da34 2107 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 2108 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 2109
b146520f 2110 return 0;
3440d265
DV		 2111}
2112
5c5f6457 2113static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 2114{
853ba5d2 2115 ppgtt->base.dev = dev;
3440d265 2116
3ed124b2 2117 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 2118 return gen6_ppgtt_init(ppgtt);
3ed124b2 2119 else
d7b2633d 2120 return gen8_ppgtt_init(ppgtt);
fa76da34 2121}
c114f76a 2122
a2cad9df
MW		 2123static void i915_address_space_init(struct i915_address_space *vm,
2124 struct drm_i915_private *dev_priv)
2125{
2126 drm_mm_init(&vm->mm, vm->start, vm->total);
2127 vm->dev = dev_priv->dev;
2128 INIT_LIST_HEAD(&vm->active_list);
2129 INIT_LIST_HEAD(&vm->inactive_list);
2130 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2131}
2132
d5165ebd
TG		 2133static void gtt_write_workarounds(struct drm_device *dev)
2134{
2135 struct drm_i915_private *dev_priv = dev->dev_private;
2136
2137 /* This function is for gtt related workarounds. This function is
2138 * called on driver load and after a GPU reset, so you can place
2139 * workarounds here even if they get overwritten by GPU reset.
2140 */
2141 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2142 if (IS_BROADWELL(dev))
2143 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2144 else if (IS_CHERRYVIEW(dev))
2145 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2146 else if (IS_SKYLAKE(dev))
2147 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2148 else if (IS_BROXTON(dev))
2149 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2150}
2151
fa76da34
DV		 2152int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2153{
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 int ret = 0;
3ed124b2 2156
5c5f6457 2157 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 2158 if (ret == 0) {
c7c48dfd 2159 kref_init(&ppgtt->ref);
a2cad9df 2160 i915_address_space_init(&ppgtt->base, dev_priv);
93bd8649 2161 }
1d2a314c
DV		 2162
2163 return ret;
2164}
2165
82460d97
DV		 2166int i915_ppgtt_init_hw(struct drm_device *dev)
2167{
d5165ebd
TG		 2168 gtt_write_workarounds(dev);
2169
671b5013
TD		 2170 /* In the case of execlists, PPGTT is enabled by the context descriptor
2171 * and the PDPs are contained within the context itself. We don't
2172 * need to do anything here. */
2173 if (i915.enable_execlists)
2174 return 0;
2175
82460d97
DV		 2176 if (!USES_PPGTT(dev))
2177 return 0;
2178
2179 if (IS_GEN6(dev))
2180 gen6_ppgtt_enable(dev);
2181 else if (IS_GEN7(dev))
2182 gen7_ppgtt_enable(dev);
2183 else if (INTEL_INFO(dev)->gen >= 8)
2184 gen8_ppgtt_enable(dev);
2185 else
5f77eeb0 2186 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 2187
4ad2fd88
JH		 2188 return 0;
2189}
1d2a314c 2190
b3dd6b96 2191int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 2192{
39dabecd 2193 struct drm_i915_private *dev_priv = req->i915;
4ad2fd88
JH		 2194 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2195
2196 if (i915.enable_execlists)
2197 return 0;
2198
2199 if (!ppgtt)
2200 return 0;
2201
e85b26dc 2202 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 2203}
4ad2fd88 2204
4d884705
DV		 2205struct i915_hw_ppgtt *
2206i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2207{
2208 struct i915_hw_ppgtt *ppgtt;
2209 int ret;
2210
2211 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2212 if (!ppgtt)
2213 return ERR_PTR(-ENOMEM);
2214
2215 ret = i915_ppgtt_init(dev, ppgtt);
2216 if (ret) {
2217 kfree(ppgtt);
2218 return ERR_PTR(ret);
2219 }
2220
2221 ppgtt->file_priv = fpriv;
2222
198c974d
DCS		 2223 trace_i915_ppgtt_create(&ppgtt->base);
2224
4d884705
DV		 2225 return ppgtt;
2226}
2227
ee960be7
DV		 2228void i915_ppgtt_release(struct kref *kref)
2229{
2230 struct i915_hw_ppgtt *ppgtt =
2231 container_of(kref, struct i915_hw_ppgtt, ref);
2232
198c974d
DCS		 2233 trace_i915_ppgtt_release(&ppgtt->base);
2234
ee960be7
DV		 2235 /* vmas should already be unbound */
2236 WARN_ON(!list_empty(&ppgtt->base.active_list));
2237 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2238
19dd120c
DV		 2239 list_del(&ppgtt->base.global_link);
2240 drm_mm_takedown(&ppgtt->base.mm);
2241
ee960be7
DV		 2242 ppgtt->base.cleanup(&ppgtt->base);
2243 kfree(ppgtt);
2244}
1d2a314c 2245
a81cc00c
BW		 2246extern int intel_iommu_gfx_mapped;
2247/* Certain Gen5 chipsets require require idling the GPU before
2248 * unmapping anything from the GTT when VT-d is enabled.
2249 */
2c642b07 2250static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 2251{
2252#ifdef CONFIG_INTEL_IOMMU
2253 /* Query intel_iommu to see if we need the workaround. Presumably that
2254 * was loaded first.
2255 */
2256 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2257 return true;
2258#endif
2259 return false;
2260}
2261
5c042287
BW		 2262static bool do_idling(struct drm_i915_private *dev_priv)
2263{
2264 bool ret = dev_priv->mm.interruptible;
2265
62106b4f 2266 if (unlikely(dev_priv->ggtt.do_idle_maps)) {
5c042287 2267 dev_priv->mm.interruptible = false;
b2da9fe5 2268 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 2269 DRM_ERROR("Couldn't idle GPU\n");
2270 /* Wait a bit, in hopes it avoids the hang */
2271 udelay(10);
2272 }
2273 }
2274
2275 return ret;
2276}
2277
2278static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2279{
62106b4f 2280 if (unlikely(dev_priv->ggtt.do_idle_maps))
5c042287
BW		 2281 dev_priv->mm.interruptible = interruptible;
2282}
2283
828c7908
BW		 2284void i915_check_and_clear_faults(struct drm_device *dev)
2285{
2286 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2287 struct intel_engine_cs *engine;
828c7908
BW		 2288
2289 if (INTEL_INFO(dev)->gen < 6)
2290 return;
2291
b4ac5afc 2292 for_each_engine(engine, dev_priv) {
828c7908 2293 u32 fault_reg;
e2f80391 2294 fault_reg = I915_READ(RING_FAULT_REG(engine));
828c7908
BW		 2295 if (fault_reg & RING_FAULT_VALID) {
2296 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 2297 "\tAddr: 0x%08lx\n"
828c7908
BW		 2298 "\tAddress space: %s\n"
2299 "\tSource ID: %d\n"
2300 "\tType: %d\n",
2301 fault_reg & PAGE_MASK,
2302 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2303 RING_FAULT_SRCID(fault_reg),
2304 RING_FAULT_FAULT_TYPE(fault_reg));
e2f80391 2305 I915_WRITE(RING_FAULT_REG(engine),
828c7908
BW		 2306 fault_reg & ~RING_FAULT_VALID);
2307 }
2308 }
4a570db5 2309 POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
828c7908
BW		 2310}
2311
91e56499
CW		 2312static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2313{
2314 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2315 intel_gtt_chipset_flush();
2316 } else {
2317 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2318 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2319 }
2320}
2321
828c7908
BW		 2322void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2323{
2324 struct drm_i915_private *dev_priv = dev->dev_private;
2325
2326 /* Don't bother messing with faults pre GEN6 as we have little
2327 * documentation supporting that it's a good idea.
2328 */
2329 if (INTEL_INFO(dev)->gen < 6)
2330 return;
2331
2332 i915_check_and_clear_faults(dev);
2333
62106b4f
JL		 2334 dev_priv->ggtt.base.clear_range(&dev_priv->ggtt.base,
2335 dev_priv->ggtt.base.start,
2336 dev_priv->ggtt.base.total,
e568af1c 2337 true);
91e56499
CW		 2338
2339 i915_ggtt_flush(dev_priv);
828c7908
BW		 2340}
2341
74163907 2342int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2343{
9da3da66
CW		 2344 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2345 obj->pages->sgl, obj->pages->nents,
2346 PCI_DMA_BIDIRECTIONAL))
2347 return -ENOSPC;
2348
2349 return 0;
7c2e6fdf
DV		 2350}
2351
2c642b07 2352static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 2353{
2354#ifdef writeq
2355 writeq(pte, addr);
2356#else
2357 iowrite32((u32)pte, addr);
2358 iowrite32(pte >> 32, addr + 4);
2359#endif
2360}
2361
2362static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2363 struct sg_table *st,
782f1495 2364 uint64_t start,
24f3a8cf 2365 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 2366{
2367 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 2368 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3 2369 gen8_pte_t __iomem *gtt_entries =
62106b4f 2370 (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + first_entry;
94ec8f61
BW		 2371 int i = 0;
2372 struct sg_page_iter sg_iter;
57007df7 2373 dma_addr_t addr = 0; /* shut up gcc */
be69459a
ID		 2374 int rpm_atomic_seq;
2375
2376 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2377
2378 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2379 addr = sg_dma_address(sg_iter.sg) +
2380 (sg_iter.sg_pgoffset << PAGE_SHIFT);
2381 gen8_set_pte(&gtt_entries[i],
2382 gen8_pte_encode(addr, level, true));
2383 i++;
2384 }
2385
2386 /*
2387 * XXX: This serves as a posting read to make sure that the PTE has
2388 * actually been updated. There is some concern that even though
2389 * registers and PTEs are within the same BAR that they are potentially
2390 * of NUMA access patterns. Therefore, even with the way we assume
2391 * hardware should work, we must keep this posting read for paranoia.
2392 */
2393 if (i != 0)
2394 WARN_ON(readq(&gtt_entries[i-1])
2395 != gen8_pte_encode(addr, level, true));
2396
94ec8f61
BW		 2397 /* This next bit makes the above posting read even more important. We
2398 * want to flush the TLBs only after we're certain all the PTE updates
2399 * have finished.
2400 */
2401 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2402 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2403
2404 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2405}
2406
c140330b
CW		 2407struct insert_entries {
2408 struct i915_address_space *vm;
2409 struct sg_table *st;
2410 uint64_t start;
2411 enum i915_cache_level level;
2412 u32 flags;
2413};
2414
2415static int gen8_ggtt_insert_entries__cb(void *_arg)
2416{
2417 struct insert_entries *arg = _arg;
2418 gen8_ggtt_insert_entries(arg->vm, arg->st,
2419 arg->start, arg->level, arg->flags);
2420 return 0;
2421}
2422
2423static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2424 struct sg_table *st,
2425 uint64_t start,
2426 enum i915_cache_level level,
2427 u32 flags)
2428{
2429 struct insert_entries arg = { vm, st, start, level, flags };
2430 stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2431}
2432
e76e9aeb
BW		 2433/*
2434 * Binds an object into the global gtt with the specified cache level. The object
2435 * will be accessible to the GPU via commands whose operands reference offsets
2436 * within the global GTT as well as accessible by the GPU through the GMADR
2437 * mapped BAR (dev_priv->mm.gtt->gtt).
2438 */
853ba5d2 2439static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 2440 struct sg_table *st,
782f1495 2441 uint64_t start,
24f3a8cf 2442 enum i915_cache_level level, u32 flags)
e76e9aeb 2443{
853ba5d2 2444 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 2445 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3 2446 gen6_pte_t __iomem *gtt_entries =
62106b4f 2447 (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + first_entry;
6e995e23
ID		 2448 int i = 0;
2449 struct sg_page_iter sg_iter;
57007df7 2450 dma_addr_t addr = 0;
be69459a
ID		 2451 int rpm_atomic_seq;
2452
2453 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
e76e9aeb 2454
6e995e23 2455 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 2456 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 2457 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 2458 i++;
e76e9aeb
BW		 2459 }
2460
e76e9aeb
BW		 2461 /* XXX: This serves as a posting read to make sure that the PTE has
2462 * actually been updated. There is some concern that even though
2463 * registers and PTEs are within the same BAR that they are potentially
2464 * of NUMA access patterns. Therefore, even with the way we assume
2465 * hardware should work, we must keep this posting read for paranoia.
2466 */
57007df7
PM		 2467 if (i != 0) {
2468 unsigned long gtt = readl(&gtt_entries[i-1]);
2469 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2470 }
0f9b91c7
BW		 2471
2472 /* This next bit makes the above posting read even more important. We
2473 * want to flush the TLBs only after we're certain all the PTE updates
2474 * have finished.
2475 */
2476 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2477 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2478
2479 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
e76e9aeb
BW		 2480}
2481
94ec8f61 2482static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2483 uint64_t start,
2484 uint64_t length,
94ec8f61
BW		 2485 bool use_scratch)
2486{
2487 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2488 unsigned first_entry = start >> PAGE_SHIFT;
2489 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2490 gen8_pte_t scratch_pte, __iomem *gtt_base =
62106b4f
JL		 2491 (gen8_pte_t __iomem *) dev_priv->ggtt.gsm + first_entry;
2492 const int max_entries = gtt_total_entries(dev_priv->ggtt) - first_entry;
94ec8f61 2493 int i;
be69459a
ID		 2494 int rpm_atomic_seq;
2495
2496 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2497
2498 if (WARN(num_entries > max_entries,
2499 "First entry = %d; Num entries = %d (max=%d)\n",
2500 first_entry, num_entries, max_entries))
2501 num_entries = max_entries;
2502
c114f76a 2503 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2504 I915_CACHE_LLC,
2505 use_scratch);
2506 for (i = 0; i < num_entries; i++)
2507 gen8_set_pte(&gtt_base[i], scratch_pte);
2508 readl(gtt_base);
be69459a
ID		 2509
2510 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2511}
2512
853ba5d2 2513static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2514 uint64_t start,
2515 uint64_t length,
828c7908 2516 bool use_scratch)
7faf1ab2 2517{
853ba5d2 2518 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2519 unsigned first_entry = start >> PAGE_SHIFT;
2520 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2521 gen6_pte_t scratch_pte, __iomem *gtt_base =
62106b4f
JL		 2522 (gen6_pte_t __iomem *) dev_priv->ggtt.gsm + first_entry;
2523 const int max_entries = gtt_total_entries(dev_priv->ggtt) - first_entry;
7faf1ab2 2524 int i;
be69459a
ID		 2525 int rpm_atomic_seq;
2526
2527 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2
DV		 2528
2529 if (WARN(num_entries > max_entries,
2530 "First entry = %d; Num entries = %d (max=%d)\n",
2531 first_entry, num_entries, max_entries))
2532 num_entries = max_entries;
2533
c114f76a
MK		 2534 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2535 I915_CACHE_LLC, use_scratch, 0);
828c7908 2536
7faf1ab2
DV		 2537 for (i = 0; i < num_entries; i++)
2538 iowrite32(scratch_pte, &gtt_base[i]);
2539 readl(gtt_base);
be69459a
ID		 2540
2541 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2542}
2543
d369d2d9
DV		 2544static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2545 struct sg_table *pages,
2546 uint64_t start,
2547 enum i915_cache_level cache_level, u32 unused)
7faf1ab2 2548{
be69459a 2549 struct drm_i915_private *dev_priv = vm->dev->dev_private;
7faf1ab2
DV		 2550 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2551 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
be69459a
ID		 2552 int rpm_atomic_seq;
2553
2554 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2 2555
d369d2d9 2556 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2557
be69459a
ID		 2558 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2559
7faf1ab2
DV		 2560}
2561
853ba5d2 2562static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2563 uint64_t start,
2564 uint64_t length,
828c7908 2565 bool unused)
7faf1ab2 2566{
be69459a 2567 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 2568 unsigned first_entry = start >> PAGE_SHIFT;
2569 unsigned num_entries = length >> PAGE_SHIFT;
be69459a
ID		 2570 int rpm_atomic_seq;
2571
2572 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2573
7faf1ab2 2574 intel_gtt_clear_range(first_entry, num_entries);
be69459a
ID		 2575
2576 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2577}
2578
70b9f6f8
DV		 2579static int ggtt_bind_vma(struct i915_vma *vma,
2580 enum i915_cache_level cache_level,
2581 u32 flags)
0a878716
DV		 2582{
2583 struct drm_i915_gem_object *obj = vma->obj;
2584 u32 pte_flags = 0;
2585 int ret;
2586
2587 ret = i915_get_ggtt_vma_pages(vma);
2588 if (ret)
2589 return ret;
2590
2591 /* Currently applicable only to VLV */
2592 if (obj->gt_ro)
2593 pte_flags |= PTE_READ_ONLY;
2594
2595 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2596 vma->node.start,
2597 cache_level, pte_flags);
2598
2599 /*
2600 * Without aliasing PPGTT there's no difference between
2601 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2602 * upgrade to both bound if we bind either to avoid double-binding.
2603 */
2604 vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2605
2606 return 0;
2607}
2608
2609static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2610 enum i915_cache_level cache_level,
2611 u32 flags)
d5bd1449 2612{
321d178e 2613 u32 pte_flags;
70b9f6f8
DV		 2614 int ret;
2615
2616 ret = i915_get_ggtt_vma_pages(vma);
2617 if (ret)
2618 return ret;
7faf1ab2 2619
24f3a8cf 2620 /* Currently applicable only to VLV */
321d178e
CW		 2621 pte_flags = 0;
2622 if (vma->obj->gt_ro)
f329f5f6 2623 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2624
ec7adb6e 2625
0a878716 2626 if (flags & GLOBAL_BIND) {
321d178e
CW		 2627 vma->vm->insert_entries(vma->vm,
2628 vma->ggtt_view.pages,
0875546c
DV		 2629 vma->node.start,
2630 cache_level, pte_flags);
6f65e29a 2631 }
d5bd1449 2632
0a878716 2633 if (flags & LOCAL_BIND) {
321d178e
CW		 2634 struct i915_hw_ppgtt *appgtt =
2635 to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2636 appgtt->base.insert_entries(&appgtt->base,
2637 vma->ggtt_view.pages,
782f1495 2638 vma->node.start,
f329f5f6 2639 cache_level, pte_flags);
6f65e29a 2640 }
70b9f6f8
DV		 2641
2642 return 0;
d5bd1449
CW		 2643}
2644
6f65e29a 2645static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2646{
6f65e29a 2647 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2648 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2649 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2650 const uint64_t size = min_t(uint64_t,
2651 obj->base.size,
2652 vma->node.size);
6f65e29a 2653
aff43766 2654 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2655 vma->vm->clear_range(vma->vm,
2656 vma->node.start,
06615ee5 2657 size,
6f65e29a 2658 true);
6f65e29a 2659 }
74898d7e 2660
0875546c 2661 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2662 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2663
6f65e29a 2664 appgtt->base.clear_range(&appgtt->base,
782f1495 2665 vma->node.start,
06615ee5 2666 size,
6f65e29a 2667 true);
6f65e29a 2668 }
74163907
DV		 2669}
2670
2671void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2672{
5c042287
BW		 2673 struct drm_device *dev = obj->base.dev;
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 bool interruptible;
2676
2677 interruptible = do_idling(dev_priv);
2678
5ec5b516
ID		 2679 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2680 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2681
2682 undo_idling(dev_priv, interruptible);
7c2e6fdf 2683}
644ec02b 2684
42d6ab48
CW		 2685static void i915_gtt_color_adjust(struct drm_mm_node *node,
2686 unsigned long color,
440fd528
TR		 2687 u64 *start,
2688 u64 *end)
42d6ab48
CW		 2689{
2690 if (node->color != color)
2691 *start += 4096;
2692
2693 if (!list_empty(&node->node_list)) {
2694 node = list_entry(node->node_list.next,
2695 struct drm_mm_node,
2696 node_list);
2697 if (node->allocated && node->color != color)
2698 *end -= 4096;
2699 }
2700}
fbe5d36e 2701
f548c0e9 2702static int i915_gem_setup_global_gtt(struct drm_device *dev,
088e0df4
MT		 2703 u64 start,
2704 u64 mappable_end,
2705 u64 end)
644ec02b 2706{
e78891ca
BW		 2707 /* Let GEM Manage all of the aperture.
2708 *
2709 * However, leave one page at the end still bound to the scratch page.
2710 * There are a number of places where the hardware apparently prefetches
2711 * past the end of the object, and we've seen multiple hangs with the
2712 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2713 * aperture. One page should be enough to keep any prefetching inside
2714 * of the aperture.
2715 */
40d74980 2716 struct drm_i915_private *dev_priv = dev->dev_private;
62106b4f 2717 struct i915_address_space *ggtt_vm = &dev_priv->ggtt.base;
ed2f3452
CW		 2718 struct drm_mm_node *entry;
2719 struct drm_i915_gem_object *obj;
2720 unsigned long hole_start, hole_end;
fa76da34 2721 int ret;
644ec02b 2722
35451cb6
BW		 2723 BUG_ON(mappable_end > end);
2724
a2cad9df 2725 ggtt_vm->start = start;
5dda8fa3 2726
a2cad9df
MW		 2727 /* Subtract the guard page before address space initialization to
2728 * shrink the range used by drm_mm */
2729 ggtt_vm->total = end - start - PAGE_SIZE;
2730 i915_address_space_init(ggtt_vm, dev_priv);
2731 ggtt_vm->total += PAGE_SIZE;
5dda8fa3
YZ		 2732
2733 if (intel_vgpu_active(dev)) {
2734 ret = intel_vgt_balloon(dev);
2735 if (ret)
2736 return ret;
2737 }
2738
42d6ab48 2739 if (!HAS_LLC(dev))
a2cad9df 2740 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2741
ed2f3452 2742 /* Mark any preallocated objects as occupied */
35c20a60 2743 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2744 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2745
088e0df4 2746 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
c6cfb325
BW		 2747 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2748
2749 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2750 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2751 if (ret) {
2752 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2753 return ret;
2754 }
aff43766 2755 vma->bound |= GLOBAL_BIND;
d0710abb 2756 __i915_vma_set_map_and_fenceable(vma);
1c7f4bca 2757 list_add_tail(&vma->vm_link, &ggtt_vm->inactive_list);
ed2f3452
CW		 2758 }
2759
ed2f3452 2760 /* Clear any non-preallocated blocks */
40d74980 2761 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2762 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2763 hole_start, hole_end);
782f1495
BW		 2764 ggtt_vm->clear_range(ggtt_vm, hole_start,
2765 hole_end - hole_start, true);
ed2f3452
CW		 2766 }
2767
2768 /* And finally clear the reserved guard page */
782f1495 2769 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2770
fa76da34
DV		 2771 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2772 struct i915_hw_ppgtt *ppgtt;
2773
2774 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2775 if (!ppgtt)
2776 return -ENOMEM;
2777
5c5f6457
DV		 2778 ret = __hw_ppgtt_init(dev, ppgtt);
2779 if (ret) {
2780 ppgtt->base.cleanup(&ppgtt->base);
2781 kfree(ppgtt);
2782 return ret;
2783 }
2784
2785 if (ppgtt->base.allocate_va_range)
2786 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2787 ppgtt->base.total);
4933d519 2788 if (ret) {
061dd493 2789 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2790 kfree(ppgtt);
fa76da34 2791 return ret;
4933d519 2792 }
fa76da34 2793
5c5f6457
DV		 2794 ppgtt->base.clear_range(&ppgtt->base,
2795 ppgtt->base.start,
2796 ppgtt->base.total,
2797 true);
2798
fa76da34 2799 dev_priv->mm.aliasing_ppgtt = ppgtt;
62106b4f
JL		 2800 WARN_ON(dev_priv->ggtt.base.bind_vma != ggtt_bind_vma);
2801 dev_priv->ggtt.base.bind_vma = aliasing_gtt_bind_vma;
fa76da34
DV		 2802 }
2803
6c5566a8 2804 return 0;
e76e9aeb
BW		 2805}
2806
d85489d3
JL		 2807/**
2808 * i915_gem_init_ggtt - Initialize GEM for Global GTT
2809 * @dev: DRM device
2810 */
2811void i915_gem_init_ggtt(struct drm_device *dev)
d7e5008f
BW		 2812{
2813 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2814 u64 gtt_size, mappable_size;
d7e5008f 2815
62106b4f
JL		 2816 gtt_size = dev_priv->ggtt.base.total;
2817 mappable_size = dev_priv->ggtt.mappable_end;
d7e5008f 2818
e78891ca 2819 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2820}
2821
d85489d3
JL		 2822/**
2823 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2824 * @dev: DRM device
2825 */
2826void i915_ggtt_cleanup_hw(struct drm_device *dev)
90d0a0e8
DV		 2827{
2828 struct drm_i915_private *dev_priv = dev->dev_private;
62106b4f 2829 struct i915_address_space *vm = &dev_priv->ggtt.base;
90d0a0e8 2830
70e32544
DV		 2831 if (dev_priv->mm.aliasing_ppgtt) {
2832 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2833
2834 ppgtt->base.cleanup(&ppgtt->base);
2835 }
2836
a4eba47b
ID		 2837 i915_gem_cleanup_stolen(dev);
2838
90d0a0e8 2839 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2840 if (intel_vgpu_active(dev))
2841 intel_vgt_deballoon();
2842
90d0a0e8
DV		 2843 drm_mm_takedown(&vm->mm);
2844 list_del(&vm->global_link);
2845 }
2846
2847 vm->cleanup(vm);
2848}
70e32544 2849
2c642b07 2850static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2851{
2852 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2853 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2854 return snb_gmch_ctl << 20;
2855}
2856
2c642b07 2857static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2858{
2859 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2860 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2861 if (bdw_gmch_ctl)
2862 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2863
2864#ifdef CONFIG_X86_32
2865 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2866 if (bdw_gmch_ctl > 4)
2867 bdw_gmch_ctl = 4;
2868#endif
2869
9459d252
BW		 2870 return bdw_gmch_ctl << 20;
2871}
2872
2c642b07 2873static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2874{
2875 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2876 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2877
2878 if (gmch_ctrl)
2879 return 1 << (20 + gmch_ctrl);
2880
2881 return 0;
2882}
2883
2c642b07 2884static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2885{
2886 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2887 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2888 return snb_gmch_ctl << 25; /* 32 MB units */
2889}
2890
2c642b07 2891static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2892{
2893 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2894 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2895 return bdw_gmch_ctl << 25; /* 32 MB units */
2896}
2897
d7f25f23
DL		 2898static size_t chv_get_stolen_size(u16 gmch_ctrl)
2899{
2900 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2901 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2902
2903 /*
2904 * 0x0 to 0x10: 32MB increments starting at 0MB
2905 * 0x11 to 0x16: 4MB increments starting at 8MB
2906 * 0x17 to 0x1d: 4MB increments start at 36MB
2907 */
2908 if (gmch_ctrl < 0x11)
2909 return gmch_ctrl << 25;
2910 else if (gmch_ctrl < 0x17)
2911 return (gmch_ctrl - 0x11 + 2) << 22;
2912 else
2913 return (gmch_ctrl - 0x17 + 9) << 22;
2914}
2915
66375014
DL		 2916static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2917{
2918 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2919 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2920
2921 if (gen9_gmch_ctl < 0xf0)
2922 return gen9_gmch_ctl << 25; /* 32 MB units */
2923 else
2924 /* 4MB increments starting at 0xf0 for 4MB */
2925 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2926}
2927
63340133
BW		 2928static int ggtt_probe_common(struct drm_device *dev,
2929 size_t gtt_size)
2930{
2931 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2932 struct i915_page_scratch *scratch_page;
21c34607 2933 phys_addr_t gtt_phys_addr;
63340133
BW		 2934
2935 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2936 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2937 (pci_resource_len(dev->pdev, 0) / 2);
2938
2a073f89
ID		 2939 /*
2940 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2941 * dropped. For WC mappings in general we have 64 byte burst writes
2942 * when the WC buffer is flushed, so we can't use it, but have to
2943 * resort to an uncached mapping. The WC issue is easily caught by the
2944 * readback check when writing GTT PTE entries.
2945 */
2946 if (IS_BROXTON(dev))
62106b4f 2947 dev_priv->ggtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2a073f89 2948 else
62106b4f
JL		 2949 dev_priv->ggtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2950 if (!dev_priv->ggtt.gsm) {
63340133
BW		 2951 DRM_ERROR("Failed to map the gtt page table\n");
2952 return -ENOMEM;
2953 }
2954
4ad2af1e
MK		 2955 scratch_page = alloc_scratch_page(dev);
2956 if (IS_ERR(scratch_page)) {
63340133
BW		 2957 DRM_ERROR("Scratch setup failed\n");
2958 /* iounmap will also get called at remove, but meh */
62106b4f 2959 iounmap(dev_priv->ggtt.gsm);
4ad2af1e 2960 return PTR_ERR(scratch_page);
63340133
BW		 2961 }
2962
62106b4f 2963 dev_priv->ggtt.base.scratch_page = scratch_page;
4ad2af1e
MK		 2964
2965 return 0;
63340133
BW		 2966}
2967
fbe5d36e
BW		 2968/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2969 * bits. When using advanced contexts each context stores its own PAT, but
2970 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2971static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2972{
fbe5d36e
BW		 2973 uint64_t pat;
2974
2975 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2976 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2977 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2978 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2979 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2980 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2981 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2982 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2983
d6a8b72e
RV		 2984 if (!USES_PPGTT(dev_priv->dev))
2985 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2986 * so RTL will always use the value corresponding to
2987 * pat_sel = 000".
2988 * So let's disable cache for GGTT to avoid screen corruptions.
2989 * MOCS still can be used though.
2990 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2991 * before this patch, i.e. the same uncached + snooping access
2992 * like on gen6/7 seems to be in effect.
2993 * - So this just fixes blitter/render access. Again it looks
2994 * like it's not just uncached access, but uncached + snooping.
2995 * So we can still hold onto all our assumptions wrt cpu
2996 * clflushing on LLC machines.
2997 */
2998 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2999
fbe5d36e
BW		 3000 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
3001 * write would work. */
7e435ad2
VS		 3002 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3003 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
fbe5d36e
BW		 3004}
3005
ee0ce478
VS		 3006static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3007{
3008 uint64_t pat;
3009
3010 /*
3011 * Map WB on BDW to snooped on CHV.
3012 *
3013 * Only the snoop bit has meaning for CHV, the rest is
3014 * ignored.
3015 *
cf3d262e
VS		 3016 * The hardware will never snoop for certain types of accesses:
3017 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3018 * - PPGTT page tables
3019 * - some other special cycles
3020 *
3021 * As with BDW, we also need to consider the following for GT accesses:
3022 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3023 * so RTL will always use the value corresponding to
3024 * pat_sel = 000".
3025 * Which means we must set the snoop bit in PAT entry 0
3026 * in order to keep the global status page working.
ee0ce478
VS		 3027 */
3028 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3029 GEN8_PPAT(1, 0) |
3030 GEN8_PPAT(2, 0) |
3031 GEN8_PPAT(3, 0) |
3032 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3033 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3034 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3035 GEN8_PPAT(7, CHV_PPAT_SNOOP);
3036
7e435ad2
VS		 3037 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3038 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
ee0ce478
VS		 3039}
3040
d507d735 3041static int gen8_gmch_probe(struct i915_ggtt *ggtt)
63340133 3042{
d507d735 3043 struct drm_device *dev = ggtt->base.dev;
63340133 3044 struct drm_i915_private *dev_priv = dev->dev_private;
63340133
BW		 3045 u16 snb_gmch_ctl;
3046 int ret;
3047
3048 /* TODO: We're not aware of mappable constraints on gen8 yet */
d507d735
JL		 3049 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3050 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
63340133
BW		 3051
3052 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3053 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3054
3055 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3056
66375014 3057 if (INTEL_INFO(dev)->gen >= 9) {
d507d735
JL		 3058 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3059 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
66375014 3060 } else if (IS_CHERRYVIEW(dev)) {
d507d735
JL		 3061 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3062 ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3063 } else {
d507d735
JL		 3064 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3065 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3066 }
63340133 3067
d507d735 3068 ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 3069
5a4e33a3 3070 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 3071 chv_setup_private_ppat(dev_priv);
3072 else
3073 bdw_setup_private_ppat(dev_priv);
fbe5d36e 3074
d507d735 3075 ret = ggtt_probe_common(dev, ggtt->size);
63340133 3076
d507d735 3077 ggtt->base.clear_range = gen8_ggtt_clear_range;
c140330b 3078 if (IS_CHERRYVIEW(dev_priv))
d507d735
JL		 3079 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3080 else
3081 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3082 ggtt->base.bind_vma = ggtt_bind_vma;
3083 ggtt->base.unbind_vma = ggtt_unbind_vma;
3084
5bab6f60 3085
63340133
BW		 3086 return ret;
3087}
3088
d507d735 3089static int gen6_gmch_probe(struct i915_ggtt *ggtt)
e76e9aeb 3090{
d507d735 3091 struct drm_device *dev = ggtt->base.dev;
e76e9aeb 3092 u16 snb_gmch_ctl;
e76e9aeb
BW		 3093 int ret;
3094
d507d735
JL		 3095 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3096 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
41907ddc 3097
baa09f5f
BW		 3098 /* 64/512MB is the current min/max we actually know of, but this is just
3099 * a coarse sanity check.
e76e9aeb 3100 */
d507d735
JL		 3101 if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
3102 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
baa09f5f 3103 return -ENXIO;
e76e9aeb
BW		 3104 }
3105
e76e9aeb
BW		 3106 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3107 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 3108 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 3109
d507d735
JL		 3110 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3111 ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
3112 ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 3113
d507d735 3114 ret = ggtt_probe_common(dev, ggtt->size);
e76e9aeb 3115
d507d735
JL		 3116 ggtt->base.clear_range = gen6_ggtt_clear_range;
3117 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3118 ggtt->base.bind_vma = ggtt_bind_vma;
3119 ggtt->base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 3120
e76e9aeb
BW		 3121 return ret;
3122}
3123
853ba5d2 3124static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 3125{
62106b4f 3126 struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
853ba5d2 3127
62106b4f 3128 iounmap(ggtt->gsm);
4ad2af1e 3129 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 3130}
baa09f5f 3131
d507d735 3132static int i915_gmch_probe(struct i915_ggtt *ggtt)
baa09f5f 3133{
d507d735 3134 struct drm_device *dev = ggtt->base.dev;
baa09f5f
BW		 3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136 int ret;
3137
baa09f5f
BW		 3138 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3139 if (!ret) {
3140 DRM_ERROR("failed to set up gmch\n");
3141 return -EIO;
3142 }
3143
d507d735
JL		 3144 intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3145 &ggtt->mappable_base, &ggtt->mappable_end);
baa09f5f 3146
d507d735
JL		 3147 ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
3148 ggtt->base.insert_entries = i915_ggtt_insert_entries;
3149 ggtt->base.clear_range = i915_ggtt_clear_range;
3150 ggtt->base.bind_vma = ggtt_bind_vma;
3151 ggtt->base.unbind_vma = ggtt_unbind_vma;
baa09f5f 3152
d507d735 3153 if (unlikely(ggtt->do_idle_maps))
c0a7f818
CW		 3154 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3155
baa09f5f
BW		 3156 return 0;
3157}
3158
853ba5d2 3159static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 3160{
3161 intel_gmch_remove();
3162}
3163
d85489d3
JL		 3164/**
3165 * i915_ggtt_init_hw - Initialize GGTT hardware
3166 * @dev: DRM device
3167 */
3168int i915_ggtt_init_hw(struct drm_device *dev)
baa09f5f
BW		 3169{
3170 struct drm_i915_private *dev_priv = dev->dev_private;
62106b4f 3171 struct i915_ggtt *ggtt = &dev_priv->ggtt;
baa09f5f
BW		 3172 int ret;
3173
baa09f5f 3174 if (INTEL_INFO(dev)->gen <= 5) {
62106b4f
JL		 3175 ggtt->probe = i915_gmch_probe;
3176 ggtt->base.cleanup = i915_gmch_remove;
63340133 3177 } else if (INTEL_INFO(dev)->gen < 8) {
62106b4f
JL		 3178 ggtt->probe = gen6_gmch_probe;
3179 ggtt->base.cleanup = gen6_gmch_remove;
4d15c145 3180 if (IS_HASWELL(dev) && dev_priv->ellc_size)
62106b4f 3181 ggtt->base.pte_encode = iris_pte_encode;
4d15c145 3182 else if (IS_HASWELL(dev))
62106b4f 3183 ggtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 3184 else if (IS_VALLEYVIEW(dev))
62106b4f 3185 ggtt->base.pte_encode = byt_pte_encode;
350ec881 3186 else if (INTEL_INFO(dev)->gen >= 7)
62106b4f 3187 ggtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 3188 else
62106b4f 3189 ggtt->base.pte_encode = snb_pte_encode;
63340133 3190 } else {
62106b4f
JL		 3191 ggtt->probe = gen8_gmch_probe;
3192 ggtt->base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 3193 }
3194
62106b4f
JL		 3195 ggtt->base.dev = dev;
3196 ggtt->base.is_ggtt = true;
c114f76a 3197
d507d735 3198 ret = ggtt->probe(ggtt);
a54c0c27 3199 if (ret)
baa09f5f 3200 return ret;
baa09f5f 3201
c890e2d5
CW		 3202 if ((ggtt->base.total - 1) >> 32) {
3203 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3204 "of address space! Found %lldM!\n",
3205 ggtt->base.total >> 20);
3206 ggtt->base.total = 1ULL << 32;
3207 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3208 }
3209
a4eba47b
ID		 3210 /*
3211 * Initialise stolen early so that we may reserve preallocated
3212 * objects for the BIOS to KMS transition.
3213 */
3214 ret = i915_gem_init_stolen(dev);
3215 if (ret)
3216 goto out_gtt_cleanup;
3217
baa09f5f 3218 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 3219 DRM_INFO("Memory usable by graphics device = %lluM\n",
62106b4f
JL		 3220 ggtt->base.total >> 20);
3221 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3222 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
5db6c735
DV		 3223#ifdef CONFIG_INTEL_IOMMU
3224 if (intel_iommu_gfx_mapped)
3225 DRM_INFO("VT-d active for gfx access\n");
3226#endif
cfa7c862
DV		 3227 /*
3228 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3229 * user's requested state against the hardware/driver capabilities. We
3230 * do this now so that we can print out any log messages once rather
3231 * than every time we check intel_enable_ppgtt().
3232 */
3233 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3234 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 3235
3236 return 0;
a4eba47b
ID		 3237
3238out_gtt_cleanup:
62106b4f 3239 ggtt->base.cleanup(&dev_priv->ggtt.base);
a4eba47b
ID		 3240
3241 return ret;
baa09f5f 3242}
6f65e29a 3243
fa42331b
DV		 3244void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3245{
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct drm_i915_gem_object *obj;
3248 struct i915_address_space *vm;
2c3d9984
TU		 3249 struct i915_vma *vma;
3250 bool flush;
fa42331b
DV		 3251
3252 i915_check_and_clear_faults(dev);
3253
3254 /* First fill our portion of the GTT with scratch pages */
62106b4f
JL		 3255 dev_priv->ggtt.base.clear_range(&dev_priv->ggtt.base,
3256 dev_priv->ggtt.base.start,
3257 dev_priv->ggtt.base.total,
fa42331b
DV		 3258 true);
3259
2c3d9984 3260 /* Cache flush objects bound into GGTT and rebind them. */
62106b4f 3261 vm = &dev_priv->ggtt.base;
fa42331b 3262 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984 3263 flush = false;
1c7f4bca 3264 list_for_each_entry(vma, &obj->vma_list, obj_link) {
2c3d9984
TU		 3265 if (vma->vm != vm)
3266 continue;
fa42331b 3267
2c3d9984
TU		 3268 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3269 PIN_UPDATE));
fa42331b 3270
2c3d9984
TU		 3271 flush = true;
3272 }
3273
3274 if (flush)
3275 i915_gem_clflush_object(obj, obj->pin_display);
3276 }
fa42331b
DV		 3277
3278 if (INTEL_INFO(dev)->gen >= 8) {
3279 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3280 chv_setup_private_ppat(dev_priv);
3281 else
3282 bdw_setup_private_ppat(dev_priv);
3283
3284 return;
3285 }
3286
3287 if (USES_PPGTT(dev)) {
3288 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3289 /* TODO: Perhaps it shouldn't be gen6 specific */
3290
3291 struct i915_hw_ppgtt *ppgtt =
3292 container_of(vm, struct i915_hw_ppgtt,
3293 base);
3294
3295 if (i915_is_ggtt(vm))
3296 ppgtt = dev_priv->mm.aliasing_ppgtt;
3297
3298 gen6_write_page_range(dev_priv, &ppgtt->pd,
3299 0, ppgtt->base.total);
3300 }
3301 }
3302
3303 i915_ggtt_flush(dev_priv);
3304}
3305
ec7adb6e
JL		 3306static struct i915_vma *
3307__i915_gem_vma_create(struct drm_i915_gem_object *obj,
3308 struct i915_address_space *vm,
3309 const struct i915_ggtt_view *ggtt_view)
6f65e29a 3310{
dabde5c7 3311 struct i915_vma *vma;
6f65e29a 3312
ec7adb6e
JL		 3313 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3314 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 3315
3316 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 3317 if (vma == NULL)
3318 return ERR_PTR(-ENOMEM);
ec7adb6e 3319
1c7f4bca
CW		 3320 INIT_LIST_HEAD(&vma->vm_link);
3321 INIT_LIST_HEAD(&vma->obj_link);
6f65e29a
BW		 3322 INIT_LIST_HEAD(&vma->exec_list);
3323 vma->vm = vm;
3324 vma->obj = obj;
596c5923 3325 vma->is_ggtt = i915_is_ggtt(vm);
6f65e29a 3326
777dc5bb 3327 if (i915_is_ggtt(vm))
ec7adb6e 3328 vma->ggtt_view = *ggtt_view;
596c5923
CW		 3329 else
3330 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a 3331
1c7f4bca 3332 list_add_tail(&vma->obj_link, &obj->vma_list);
6f65e29a
BW		 3333
3334 return vma;
3335}
3336
3337struct i915_vma *
ec7adb6e
JL		 3338i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3339 struct i915_address_space *vm)
3340{
3341 struct i915_vma *vma;
3342
3343 vma = i915_gem_obj_to_vma(obj, vm);
3344 if (!vma)
3345 vma = __i915_gem_vma_create(obj, vm,
3346 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3347
3348 return vma;
3349}
3350
3351struct i915_vma *
3352i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 3353 const struct i915_ggtt_view *view)
6f65e29a 3354{
ec7adb6e 3355 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
ade7daa1 3356 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
ec7adb6e 3357
6f65e29a 3358 if (!vma)
ec7adb6e 3359 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 3360
3361 return vma;
ec7adb6e 3362
6f65e29a 3363}
fe14d5f4 3364
804beb4b 3365static struct scatterlist *
2d7f3bdb 3366rotate_pages(const dma_addr_t *in, unsigned int offset,
804beb4b 3367 unsigned int width, unsigned int height,
87130255 3368 unsigned int stride,
804beb4b 3369 struct sg_table *st, struct scatterlist *sg)
50470bb0
TU		 3370{
3371 unsigned int column, row;
3372 unsigned int src_idx;
50470bb0 3373
50470bb0 3374 for (column = 0; column < width; column++) {
87130255 3375 src_idx = stride * (height - 1) + column;
50470bb0
TU		 3376 for (row = 0; row < height; row++) {
3377 st->nents++;
3378 /* We don't need the pages, but need to initialize
3379 * the entries so the sg list can be happily traversed.
3380 * The only thing we need are DMA addresses.
3381 */
3382 sg_set_page(sg, NULL, PAGE_SIZE, 0);
804beb4b 3383 sg_dma_address(sg) = in[offset + src_idx];
50470bb0
TU		 3384 sg_dma_len(sg) = PAGE_SIZE;
3385 sg = sg_next(sg);
87130255 3386 src_idx -= stride;
50470bb0
TU		 3387 }
3388 }
804beb4b
TU		 3389
3390 return sg;
50470bb0
TU		 3391}
3392
3393static struct sg_table *
11d23e6f 3394intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
50470bb0
TU		 3395 struct drm_i915_gem_object *obj)
3396{
1663b9d6 3397 unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
89e3e142 3398 unsigned int size_pages_uv;
50470bb0
TU		 3399 struct sg_page_iter sg_iter;
3400 unsigned long i;
3401 dma_addr_t *page_addr_list;
3402 struct sg_table *st;
89e3e142
TU		 3403 unsigned int uv_start_page;
3404 struct scatterlist *sg;
1d00dad5 3405 int ret = -ENOMEM;
50470bb0 3406
50470bb0 3407 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU		 3408 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3409 sizeof(dma_addr_t));
50470bb0
TU		 3410 if (!page_addr_list)
3411 return ERR_PTR(ret);
3412
89e3e142
TU		 3413 /* Account for UV plane with NV12. */
3414 if (rot_info->pixel_format == DRM_FORMAT_NV12)
1663b9d6 3415 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
89e3e142
TU		 3416 else
3417 size_pages_uv = 0;
3418
50470bb0
TU		 3419 /* Allocate target SG list. */
3420 st = kmalloc(sizeof(*st), GFP_KERNEL);
3421 if (!st)
3422 goto err_st_alloc;
3423
89e3e142 3424 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
50470bb0
TU		 3425 if (ret)
3426 goto err_sg_alloc;
3427
3428 /* Populate source page list from the object. */
3429 i = 0;
3430 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3431 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3432 i++;
3433 }
3434
11f20322
VS		 3435 st->nents = 0;
3436 sg = st->sgl;
3437
50470bb0 3438 /* Rotate the pages. */
89e3e142 3439 sg = rotate_pages(page_addr_list, 0,
1663b9d6
VS		 3440 rot_info->plane[0].width, rot_info->plane[0].height,
3441 rot_info->plane[0].width,
11f20322 3442 st, sg);
50470bb0 3443
89e3e142
TU		 3444 /* Append the UV plane if NV12. */
3445 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3446 uv_start_page = size_pages;
3447
3448 /* Check for tile-row un-alignment. */
3449 if (offset_in_page(rot_info->uv_offset))
3450 uv_start_page--;
3451
dedf278c
TU		 3452 rot_info->uv_start_page = uv_start_page;
3453
11f20322
VS		 3454 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3455 rot_info->plane[1].width, rot_info->plane[1].height,
3456 rot_info->plane[1].width,
3457 st, sg);
89e3e142
TU		 3458 }
3459
1663b9d6
VS		 3460 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3461 obj->base.size, rot_info->plane[0].width,
3462 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3463 size_pages);
50470bb0
TU		 3464
3465 drm_free_large(page_addr_list);
3466
3467 return st;
3468
3469err_sg_alloc:
3470 kfree(st);
3471err_st_alloc:
3472 drm_free_large(page_addr_list);
3473
1663b9d6
VS		 3474 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3475 obj->base.size, ret, rot_info->plane[0].width,
3476 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3477 size_pages);
50470bb0
TU		 3478 return ERR_PTR(ret);
3479}
ec7adb6e 3480
8bd7ef16
JL		 3481static struct sg_table *
3482intel_partial_pages(const struct i915_ggtt_view *view,
3483 struct drm_i915_gem_object *obj)
3484{
3485 struct sg_table *st;
3486 struct scatterlist *sg;
3487 struct sg_page_iter obj_sg_iter;
3488 int ret = -ENOMEM;
3489
3490 st = kmalloc(sizeof(*st), GFP_KERNEL);
3491 if (!st)
3492 goto err_st_alloc;
3493
3494 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3495 if (ret)
3496 goto err_sg_alloc;
3497
3498 sg = st->sgl;
3499 st->nents = 0;
3500 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3501 view->params.partial.offset)
3502 {
3503 if (st->nents >= view->params.partial.size)
3504 break;
3505
3506 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3507 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3508 sg_dma_len(sg) = PAGE_SIZE;
3509
3510 sg = sg_next(sg);
3511 st->nents++;
3512 }
3513
3514 return st;
3515
3516err_sg_alloc:
3517 kfree(st);
3518err_st_alloc:
3519 return ERR_PTR(ret);
3520}
3521
70b9f6f8 3522static int
50470bb0 3523i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 3524{
50470bb0
TU		 3525 int ret = 0;
3526
fe14d5f4
TU		 3527 if (vma->ggtt_view.pages)
3528 return 0;
3529
3530 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3531 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 3532 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3533 vma->ggtt_view.pages =
11d23e6f 3534 intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
8bd7ef16
JL		 3535 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3536 vma->ggtt_view.pages =
3537 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 3538 else
3539 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3540 vma->ggtt_view.type);
3541
3542 if (!vma->ggtt_view.pages) {
ec7adb6e 3543 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 3544 vma->ggtt_view.type);
50470bb0
TU		 3545 ret = -EINVAL;
3546 } else if (IS_ERR(vma->ggtt_view.pages)) {
3547 ret = PTR_ERR(vma->ggtt_view.pages);
3548 vma->ggtt_view.pages = NULL;
3549 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3550 vma->ggtt_view.type, ret);
fe14d5f4
TU		 3551 }
3552
50470bb0 3553 return ret;
fe14d5f4
TU		 3554}
3555
3556/**
3557 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3558 * @vma: VMA to map
3559 * @cache_level: mapping cache level
3560 * @flags: flags like global or local mapping
3561 *
3562 * DMA addresses are taken from the scatter-gather table of this object (or of
3563 * this VMA in case of non-default GGTT views) and PTE entries set up.
3564 * Note that DMA addresses are also the only part of the SG table we care about.
3565 */
3566int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3567 u32 flags)
3568{
75d04a37
MK		 3569 int ret;
3570 u32 bind_flags;
1d335d1b 3571
75d04a37
MK		 3572 if (WARN_ON(flags == 0))
3573 return -EINVAL;
1d335d1b 3574
75d04a37 3575 bind_flags = 0;
0875546c
DV		 3576 if (flags & PIN_GLOBAL)
3577 bind_flags |= GLOBAL_BIND;
3578 if (flags & PIN_USER)
3579 bind_flags |= LOCAL_BIND;
3580
3581 if (flags & PIN_UPDATE)
3582 bind_flags |= vma->bound;
3583 else
3584 bind_flags &= ~vma->bound;
3585
75d04a37
MK		 3586 if (bind_flags == 0)
3587 return 0;
3588
3589 if (vma->bound == 0 && vma->vm->allocate_va_range) {
b2dd4511
MK		 3590 /* XXX: i915_vma_pin() will fix this +- hack */
3591 vma->pin_count++;
596c5923 3592 trace_i915_va_alloc(vma);
75d04a37
MK		 3593 ret = vma->vm->allocate_va_range(vma->vm,
3594 vma->node.start,
3595 vma->node.size);
b2dd4511 3596 vma->pin_count--;
75d04a37
MK		 3597 if (ret)
3598 return ret;
3599 }
3600
3601 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3602 if (ret)
3603 return ret;
0875546c
DV		 3604
3605 vma->bound |= bind_flags;
fe14d5f4
TU		 3606
3607 return 0;
3608}
91e6711e
JL		 3609
3610/**
3611 * i915_ggtt_view_size - Get the size of a GGTT view.
3612 * @obj: Object the view is of.
3613 * @view: The view in question.
3614 *
3615 * @return The size of the GGTT view in bytes.
3616 */
3617size_t
3618i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3619 const struct i915_ggtt_view *view)
3620{
9e759ff1 3621 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3622 return obj->base.size;
9e759ff1 3623 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
1663b9d6 3624 return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
8bd7ef16
JL		 3625 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3626 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3627 } else {
3628 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3629 return obj->base.size;
3630 }
3631}
Linux kernel - Deliverables
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