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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
a2319c08 BW |
33 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | ||
93a25a9e DV |
35 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) |
36 | { | |
37 | if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
38 | return false; | |
39 | ||
40 | if (i915.enable_ppgtt == 1 && full) | |
41 | return false; | |
42 | ||
43 | #ifdef CONFIG_INTEL_IOMMU | |
44 | /* Disable ppgtt on SNB if VT-d is on. */ | |
45 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
46 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
47 | return false; | |
48 | } | |
49 | #endif | |
50 | ||
51 | /* Full ppgtt disabled by default for now due to issues. */ | |
52 | if (full) | |
53 | return false; /* HAS_PPGTT(dev) */ | |
54 | else | |
55 | return HAS_ALIASING_PPGTT(dev); | |
56 | } | |
57 | ||
6670a5a5 BW |
58 | #define GEN6_PPGTT_PD_ENTRIES 512 |
59 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 60 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 61 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 62 | |
26b1ff35 BW |
63 | /* PPGTT stuff */ |
64 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 65 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
66 | |
67 | #define GEN6_PDE_VALID (1 << 0) | |
68 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
69 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
70 | ||
71 | #define GEN6_PTE_VALID (1 << 0) | |
72 | #define GEN6_PTE_UNCACHED (1 << 1) | |
73 | #define HSW_PTE_UNCACHED (0) | |
74 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 75 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 76 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
77 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
78 | ||
79 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
80 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
81 | */ | |
82 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
83 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 84 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 85 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 86 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
c51e9701 | 87 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
651d794f | 88 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
c51e9701 | 89 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
26b1ff35 | 90 | |
459108b8 | 91 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a | 92 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
7ad47cf2 BW |
93 | |
94 | /* GEN8 legacy style addressis defined as a 3 level page table: | |
95 | * 31:30 | 29:21 | 20:12 | 11:0 | |
96 | * PDPE | PDE | PTE | offset | |
97 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
98 | * programmed via register. | |
99 | */ | |
100 | #define GEN8_PDPE_SHIFT 30 | |
101 | #define GEN8_PDPE_MASK 0x3 | |
102 | #define GEN8_PDE_SHIFT 21 | |
103 | #define GEN8_PDE_MASK 0x1ff | |
104 | #define GEN8_PTE_SHIFT 12 | |
105 | #define GEN8_PTE_MASK 0x1ff | |
37aca44a | 106 | |
fbe5d36e BW |
107 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
108 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
109 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
110 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
111 | ||
6f65e29a BW |
112 | static void ppgtt_bind_vma(struct i915_vma *vma, |
113 | enum i915_cache_level cache_level, | |
114 | u32 flags); | |
115 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 116 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 117 | |
94ec8f61 BW |
118 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
119 | enum i915_cache_level level, | |
120 | bool valid) | |
121 | { | |
122 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
123 | pte |= addr; | |
fbe5d36e BW |
124 | if (level != I915_CACHE_NONE) |
125 | pte |= PPAT_CACHED_INDEX; | |
126 | else | |
127 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
128 | return pte; |
129 | } | |
130 | ||
b1fe6673 BW |
131 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
132 | dma_addr_t addr, | |
133 | enum i915_cache_level level) | |
134 | { | |
135 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
136 | pde |= addr; | |
137 | if (level != I915_CACHE_NONE) | |
138 | pde |= PPAT_CACHED_PDE_INDEX; | |
139 | else | |
140 | pde |= PPAT_UNCACHED_INDEX; | |
141 | return pde; | |
142 | } | |
143 | ||
350ec881 | 144 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
145 | enum i915_cache_level level, |
146 | bool valid) | |
54d12527 | 147 | { |
b35b380e | 148 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 149 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
150 | |
151 | switch (level) { | |
350ec881 CW |
152 | case I915_CACHE_L3_LLC: |
153 | case I915_CACHE_LLC: | |
154 | pte |= GEN6_PTE_CACHE_LLC; | |
155 | break; | |
156 | case I915_CACHE_NONE: | |
157 | pte |= GEN6_PTE_UNCACHED; | |
158 | break; | |
159 | default: | |
160 | WARN_ON(1); | |
161 | } | |
162 | ||
163 | return pte; | |
164 | } | |
165 | ||
166 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
167 | enum i915_cache_level level, |
168 | bool valid) | |
350ec881 | 169 | { |
b35b380e | 170 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
171 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
172 | ||
173 | switch (level) { | |
174 | case I915_CACHE_L3_LLC: | |
175 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
176 | break; |
177 | case I915_CACHE_LLC: | |
178 | pte |= GEN6_PTE_CACHE_LLC; | |
179 | break; | |
180 | case I915_CACHE_NONE: | |
9119708c | 181 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
182 | break; |
183 | default: | |
350ec881 | 184 | WARN_ON(1); |
e7210c3c BW |
185 | } |
186 | ||
54d12527 BW |
187 | return pte; |
188 | } | |
189 | ||
93c34e70 KG |
190 | #define BYT_PTE_WRITEABLE (1 << 1) |
191 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
192 | ||
80a74f7f | 193 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
194 | enum i915_cache_level level, |
195 | bool valid) | |
93c34e70 | 196 | { |
b35b380e | 197 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
198 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
199 | ||
200 | /* Mark the page as writeable. Other platforms don't have a | |
201 | * setting for read-only/writable, so this matches that behavior. | |
202 | */ | |
203 | pte |= BYT_PTE_WRITEABLE; | |
204 | ||
205 | if (level != I915_CACHE_NONE) | |
206 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
207 | ||
208 | return pte; | |
209 | } | |
210 | ||
80a74f7f | 211 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
212 | enum i915_cache_level level, |
213 | bool valid) | |
9119708c | 214 | { |
b35b380e | 215 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 216 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
217 | |
218 | if (level != I915_CACHE_NONE) | |
87a6b688 | 219 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
220 | |
221 | return pte; | |
222 | } | |
223 | ||
4d15c145 | 224 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
225 | enum i915_cache_level level, |
226 | bool valid) | |
4d15c145 | 227 | { |
b35b380e | 228 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
229 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
230 | ||
651d794f CW |
231 | switch (level) { |
232 | case I915_CACHE_NONE: | |
233 | break; | |
234 | case I915_CACHE_WT: | |
c51e9701 | 235 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
236 | break; |
237 | default: | |
c51e9701 | 238 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
239 | break; |
240 | } | |
4d15c145 BW |
241 | |
242 | return pte; | |
243 | } | |
244 | ||
94e409c1 BW |
245 | /* Broadwell Page Directory Pointer Descriptors */ |
246 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 247 | uint64_t val, bool synchronous) |
94e409c1 | 248 | { |
e178f705 | 249 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
250 | int ret; |
251 | ||
252 | BUG_ON(entry >= 4); | |
253 | ||
e178f705 BW |
254 | if (synchronous) { |
255 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
256 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
257 | return 0; | |
258 | } | |
259 | ||
94e409c1 BW |
260 | ret = intel_ring_begin(ring, 6); |
261 | if (ret) | |
262 | return ret; | |
263 | ||
264 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
265 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
266 | intel_ring_emit(ring, (u32)(val >> 32)); | |
267 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
268 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
269 | intel_ring_emit(ring, (u32)(val)); | |
270 | intel_ring_advance(ring); | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
eeb9488e BW |
275 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
276 | struct intel_ring_buffer *ring, | |
277 | bool synchronous) | |
94e409c1 | 278 | { |
eeb9488e | 279 | int i, ret; |
94e409c1 BW |
280 | |
281 | /* bit of a hack to find the actual last used pd */ | |
282 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
283 | ||
94e409c1 BW |
284 | for (i = used_pd - 1; i >= 0; i--) { |
285 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
286 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
287 | if (ret) | |
288 | return ret; | |
94e409c1 | 289 | } |
d595bd4b | 290 | |
eeb9488e | 291 | return 0; |
94e409c1 BW |
292 | } |
293 | ||
459108b8 | 294 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
295 | uint64_t start, |
296 | uint64_t length, | |
459108b8 BW |
297 | bool use_scratch) |
298 | { | |
299 | struct i915_hw_ppgtt *ppgtt = | |
300 | container_of(vm, struct i915_hw_ppgtt, base); | |
301 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
302 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
303 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
304 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 305 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
306 | unsigned last_pte, i; |
307 | ||
308 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
309 | I915_CACHE_LLC, use_scratch); | |
310 | ||
311 | while (num_entries) { | |
7ad47cf2 | 312 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 313 | |
7ad47cf2 | 314 | last_pte = pte + num_entries; |
459108b8 BW |
315 | if (last_pte > GEN8_PTES_PER_PAGE) |
316 | last_pte = GEN8_PTES_PER_PAGE; | |
317 | ||
318 | pt_vaddr = kmap_atomic(page_table); | |
319 | ||
7ad47cf2 | 320 | for (i = pte; i < last_pte; i++) { |
459108b8 | 321 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
322 | num_entries--; |
323 | } | |
459108b8 BW |
324 | |
325 | kunmap_atomic(pt_vaddr); | |
326 | ||
7ad47cf2 BW |
327 | pte = 0; |
328 | if (++pde == GEN8_PDES_PER_PAGE) { | |
329 | pdpe++; | |
330 | pde = 0; | |
331 | } | |
459108b8 BW |
332 | } |
333 | } | |
334 | ||
9df15b49 BW |
335 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
336 | struct sg_table *pages, | |
782f1495 | 337 | uint64_t start, |
9df15b49 BW |
338 | enum i915_cache_level cache_level) |
339 | { | |
340 | struct i915_hw_ppgtt *ppgtt = | |
341 | container_of(vm, struct i915_hw_ppgtt, base); | |
342 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
343 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
344 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
345 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
346 | struct sg_page_iter sg_iter; |
347 | ||
6f1cc993 | 348 | pt_vaddr = NULL; |
7ad47cf2 | 349 | |
9df15b49 | 350 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
351 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
352 | break; | |
353 | ||
6f1cc993 | 354 | if (pt_vaddr == NULL) |
7ad47cf2 | 355 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 356 | |
7ad47cf2 | 357 | pt_vaddr[pte] = |
6f1cc993 CW |
358 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
359 | cache_level, true); | |
7ad47cf2 | 360 | if (++pte == GEN8_PTES_PER_PAGE) { |
9df15b49 | 361 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 362 | pt_vaddr = NULL; |
7ad47cf2 BW |
363 | if (++pde == GEN8_PDES_PER_PAGE) { |
364 | pdpe++; | |
365 | pde = 0; | |
366 | } | |
367 | pte = 0; | |
9df15b49 BW |
368 | } |
369 | } | |
6f1cc993 CW |
370 | if (pt_vaddr) |
371 | kunmap_atomic(pt_vaddr); | |
9df15b49 BW |
372 | } |
373 | ||
7ad47cf2 BW |
374 | static void gen8_free_page_tables(struct page **pt_pages) |
375 | { | |
376 | int i; | |
377 | ||
378 | if (pt_pages == NULL) | |
379 | return; | |
380 | ||
381 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
382 | if (pt_pages[i]) | |
383 | __free_pages(pt_pages[i], 0); | |
384 | } | |
385 | ||
386 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
387 | { |
388 | int i; | |
389 | ||
7ad47cf2 BW |
390 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
391 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
392 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 393 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 394 | } |
b45a6715 | 395 | |
b45a6715 BW |
396 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
397 | } | |
398 | ||
399 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
400 | { | |
f3a964b9 | 401 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
402 | int i, j; |
403 | ||
404 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
405 | /* TODO: In the future we'll support sparse mappings, so this | |
406 | * will have to change. */ | |
407 | if (!ppgtt->pd_dma_addr[i]) | |
408 | continue; | |
409 | ||
f3a964b9 BW |
410 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
411 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
412 | |
413 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
414 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
415 | if (addr) | |
f3a964b9 BW |
416 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
417 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
418 | } |
419 | } | |
420 | } | |
421 | ||
37aca44a BW |
422 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
423 | { | |
424 | struct i915_hw_ppgtt *ppgtt = | |
425 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 426 | |
7e0d96bc | 427 | list_del(&vm->global_link); |
686e1f6f BW |
428 | drm_mm_takedown(&vm->mm); |
429 | ||
b45a6715 BW |
430 | gen8_ppgtt_unmap_pages(ppgtt); |
431 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
432 | } |
433 | ||
7ad47cf2 BW |
434 | static struct page **__gen8_alloc_page_tables(void) |
435 | { | |
436 | struct page **pt_pages; | |
437 | int i; | |
438 | ||
439 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
440 | if (!pt_pages) | |
441 | return ERR_PTR(-ENOMEM); | |
442 | ||
443 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
444 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
445 | if (!pt_pages[i]) | |
446 | goto bail; | |
447 | } | |
448 | ||
449 | return pt_pages; | |
450 | ||
451 | bail: | |
452 | gen8_free_page_tables(pt_pages); | |
453 | kfree(pt_pages); | |
454 | return ERR_PTR(-ENOMEM); | |
455 | } | |
456 | ||
bf2b4ed2 BW |
457 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
458 | const int max_pdp) | |
459 | { | |
7ad47cf2 | 460 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 461 | int i, ret; |
bf2b4ed2 | 462 | |
7ad47cf2 BW |
463 | for (i = 0; i < max_pdp; i++) { |
464 | pt_pages[i] = __gen8_alloc_page_tables(); | |
465 | if (IS_ERR(pt_pages[i])) { | |
466 | ret = PTR_ERR(pt_pages[i]); | |
467 | goto unwind_out; | |
468 | } | |
469 | } | |
470 | ||
471 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
472 | * "atomic" - for cleanup purposes. | |
473 | */ | |
474 | for (i = 0; i < max_pdp; i++) | |
475 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 476 | |
bf2b4ed2 | 477 | return 0; |
7ad47cf2 BW |
478 | |
479 | unwind_out: | |
480 | while (i--) { | |
481 | gen8_free_page_tables(pt_pages[i]); | |
482 | kfree(pt_pages[i]); | |
483 | } | |
484 | ||
485 | return ret; | |
bf2b4ed2 BW |
486 | } |
487 | ||
488 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
489 | { | |
490 | int i; | |
491 | ||
492 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
493 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
494 | sizeof(dma_addr_t), | |
495 | GFP_KERNEL); | |
496 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
497 | return -ENOMEM; | |
498 | } | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
504 | const int max_pdp) | |
505 | { | |
506 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
507 | if (!ppgtt->pd_pages) | |
508 | return -ENOMEM; | |
509 | ||
510 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
511 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
517 | const int max_pdp) | |
518 | { | |
519 | int ret; | |
520 | ||
521 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
522 | if (ret) | |
523 | return ret; | |
524 | ||
525 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
526 | if (ret) { | |
527 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
528 | return ret; | |
529 | } | |
530 | ||
531 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
532 | ||
533 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
534 | if (ret) | |
535 | gen8_ppgtt_free(ppgtt); | |
536 | ||
537 | return ret; | |
538 | } | |
539 | ||
540 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
541 | const int pd) | |
542 | { | |
543 | dma_addr_t pd_addr; | |
544 | int ret; | |
545 | ||
546 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
547 | &ppgtt->pd_pages[pd], 0, | |
548 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
549 | ||
550 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
551 | if (ret) | |
552 | return ret; | |
553 | ||
554 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
559 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
560 | const int pd, | |
561 | const int pt) | |
562 | { | |
563 | dma_addr_t pt_addr; | |
564 | struct page *p; | |
565 | int ret; | |
566 | ||
7ad47cf2 | 567 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
568 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
569 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
570 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
571 | if (ret) | |
572 | return ret; | |
573 | ||
574 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
37aca44a | 579 | /** |
f3a964b9 BW |
580 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
581 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
582 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
583 | * space. | |
37aca44a | 584 | * |
f3a964b9 BW |
585 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
586 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 587 | * TODO: Do something with the size parameter |
f3a964b9 | 588 | */ |
37aca44a BW |
589 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
590 | { | |
37aca44a | 591 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 592 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 593 | int i, j, ret; |
37aca44a BW |
594 | |
595 | if (size % (1<<30)) | |
596 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
597 | ||
bf2b4ed2 BW |
598 | /* 1. Do all our allocations for page directories and page tables. */ |
599 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
600 | if (ret) | |
601 | return ret; | |
f3a964b9 | 602 | |
37aca44a | 603 | /* |
bf2b4ed2 | 604 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
605 | */ |
606 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 607 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
608 | if (ret) |
609 | goto bail; | |
37aca44a | 610 | |
37aca44a | 611 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 612 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
613 | if (ret) |
614 | goto bail; | |
37aca44a BW |
615 | } |
616 | } | |
617 | ||
f3a964b9 BW |
618 | /* |
619 | * 3. Map all the page directory entires to point to the page tables | |
620 | * we've allocated. | |
621 | * | |
622 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 623 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
624 | * will never need to touch the PDEs again. |
625 | */ | |
b1fe6673 BW |
626 | for (i = 0; i < max_pdp; i++) { |
627 | gen8_ppgtt_pde_t *pd_vaddr; | |
628 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
629 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
630 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
631 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
632 | I915_CACHE_LLC); | |
633 | } | |
634 | kunmap_atomic(pd_vaddr); | |
635 | } | |
636 | ||
f3a964b9 BW |
637 | ppgtt->enable = gen8_ppgtt_enable; |
638 | ppgtt->switch_mm = gen8_mm_switch; | |
639 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
640 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
641 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
642 | ppgtt->base.start = 0; | |
5abbcca3 | 643 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 644 | |
5abbcca3 | 645 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 646 | |
37aca44a BW |
647 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
648 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
649 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
650 | ppgtt->num_pd_entries, |
651 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 652 | return 0; |
37aca44a | 653 | |
f3a964b9 BW |
654 | bail: |
655 | gen8_ppgtt_unmap_pages(ppgtt); | |
656 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
657 | return ret; |
658 | } | |
659 | ||
87d60b63 BW |
660 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
661 | { | |
662 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
663 | struct i915_address_space *vm = &ppgtt->base; | |
664 | gen6_gtt_pte_t __iomem *pd_addr; | |
665 | gen6_gtt_pte_t scratch_pte; | |
666 | uint32_t pd_entry; | |
667 | int pte, pde; | |
668 | ||
669 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
670 | ||
671 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
672 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
673 | ||
674 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
675 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
676 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
677 | u32 expected; | |
678 | gen6_gtt_pte_t *pt_vaddr; | |
679 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
680 | pd_entry = readl(pd_addr + pde); | |
681 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
682 | ||
683 | if (pd_entry != expected) | |
684 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
685 | pde, | |
686 | pd_entry, | |
687 | expected); | |
688 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
689 | ||
690 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
691 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
692 | unsigned long va = | |
693 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
694 | (pte * PAGE_SIZE); | |
695 | int i; | |
696 | bool found = false; | |
697 | for (i = 0; i < 4; i++) | |
698 | if (pt_vaddr[pte + i] != scratch_pte) | |
699 | found = true; | |
700 | if (!found) | |
701 | continue; | |
702 | ||
703 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
704 | for (i = 0; i < 4; i++) { | |
705 | if (pt_vaddr[pte + i] != scratch_pte) | |
706 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
707 | else | |
708 | seq_puts(m, " SCRATCH "); | |
709 | } | |
710 | seq_puts(m, "\n"); | |
711 | } | |
712 | kunmap_atomic(pt_vaddr); | |
713 | } | |
714 | } | |
715 | ||
3e302542 | 716 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 717 | { |
853ba5d2 | 718 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
719 | gen6_gtt_pte_t __iomem *pd_addr; |
720 | uint32_t pd_entry; | |
721 | int i; | |
722 | ||
0a732870 | 723 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
724 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
725 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
726 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
727 | dma_addr_t pt_addr; | |
728 | ||
729 | pt_addr = ppgtt->pt_dma_addr[i]; | |
730 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
731 | pd_entry |= GEN6_PDE_VALID; | |
732 | ||
733 | writel(pd_entry, pd_addr + i); | |
734 | } | |
735 | readl(pd_addr); | |
3e302542 BW |
736 | } |
737 | ||
b4a74e3a | 738 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 739 | { |
b4a74e3a BW |
740 | BUG_ON(ppgtt->pd_offset & 0x3f); |
741 | ||
742 | return (ppgtt->pd_offset / 64) << 16; | |
743 | } | |
744 | ||
90252e5c BW |
745 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
746 | struct intel_ring_buffer *ring, | |
747 | bool synchronous) | |
748 | { | |
749 | struct drm_device *dev = ppgtt->base.dev; | |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
751 | int ret; | |
752 | ||
753 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
754 | * manually frob these bits. Ideally we could use the ring functions, | |
755 | * except our error handling makes it quite difficult (can't use | |
756 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
757 | * | |
758 | * FIXME: We should try not to special case reset | |
759 | */ | |
760 | if (synchronous || | |
761 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
762 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
763 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
764 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
765 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
770 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
771 | if (ret) | |
772 | return ret; | |
773 | ||
774 | ret = intel_ring_begin(ring, 6); | |
775 | if (ret) | |
776 | return ret; | |
777 | ||
778 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
779 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
780 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
781 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
782 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
783 | intel_ring_emit(ring, MI_NOOP); | |
784 | intel_ring_advance(ring); | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
48a10389 BW |
789 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
790 | struct intel_ring_buffer *ring, | |
791 | bool synchronous) | |
792 | { | |
793 | struct drm_device *dev = ppgtt->base.dev; | |
794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
795 | int ret; | |
796 | ||
797 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
798 | * manually frob these bits. Ideally we could use the ring functions, | |
799 | * except our error handling makes it quite difficult (can't use | |
800 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
801 | * | |
802 | * FIXME: We should try not to special case reset | |
803 | */ | |
804 | if (synchronous || | |
805 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
806 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
807 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
808 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
809 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
810 | return 0; | |
811 | } | |
812 | ||
813 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
814 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
815 | if (ret) | |
816 | return ret; | |
817 | ||
818 | ret = intel_ring_begin(ring, 6); | |
819 | if (ret) | |
820 | return ret; | |
821 | ||
822 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
823 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
824 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
825 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
826 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
827 | intel_ring_emit(ring, MI_NOOP); | |
828 | intel_ring_advance(ring); | |
829 | ||
90252e5c BW |
830 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
831 | if (ring->id != RCS) { | |
832 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
833 | if (ret) | |
834 | return ret; | |
835 | } | |
836 | ||
48a10389 BW |
837 | return 0; |
838 | } | |
839 | ||
eeb9488e BW |
840 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
841 | struct intel_ring_buffer *ring, | |
842 | bool synchronous) | |
843 | { | |
844 | struct drm_device *dev = ppgtt->base.dev; | |
845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
846 | ||
48a10389 BW |
847 | if (!synchronous) |
848 | return 0; | |
849 | ||
eeb9488e BW |
850 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
851 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
852 | ||
853 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
858 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
859 | { | |
860 | struct drm_device *dev = ppgtt->base.dev; | |
861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3e302542 | 862 | struct intel_ring_buffer *ring; |
eeb9488e | 863 | int j, ret; |
3e302542 | 864 | |
eeb9488e BW |
865 | for_each_ring(ring, dev_priv, j) { |
866 | I915_WRITE(RING_MODE_GEN7(ring), | |
867 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 868 | |
d2ff7192 BW |
869 | /* We promise to do a switch later with FULL PPGTT. If this is |
870 | * aliasing, this is the one and only switch we'll do */ | |
871 | if (USES_FULL_PPGTT(dev)) | |
872 | continue; | |
6197349b | 873 | |
eeb9488e BW |
874 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
875 | if (ret) | |
876 | goto err_out; | |
877 | } | |
6197349b | 878 | |
eeb9488e | 879 | return 0; |
6197349b | 880 | |
eeb9488e BW |
881 | err_out: |
882 | for_each_ring(ring, dev_priv, j) | |
883 | I915_WRITE(RING_MODE_GEN7(ring), | |
884 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
885 | return ret; | |
886 | } | |
6197349b | 887 | |
b4a74e3a | 888 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 889 | { |
a3d67d23 | 890 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 891 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 892 | struct intel_ring_buffer *ring; |
b4a74e3a | 893 | uint32_t ecochk, ecobits; |
3e302542 | 894 | int i; |
6197349b | 895 | |
b4a74e3a BW |
896 | ecobits = I915_READ(GAC_ECO_BITS); |
897 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 898 | |
b4a74e3a BW |
899 | ecochk = I915_READ(GAM_ECOCHK); |
900 | if (IS_HASWELL(dev)) { | |
901 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
902 | } else { | |
903 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
904 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
905 | } | |
906 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 907 | |
b4a74e3a | 908 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 909 | int ret; |
6197349b | 910 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
911 | I915_WRITE(RING_MODE_GEN7(ring), |
912 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
913 | |
914 | /* We promise to do a switch later with FULL PPGTT. If this is | |
915 | * aliasing, this is the one and only switch we'll do */ | |
916 | if (USES_FULL_PPGTT(dev)) | |
917 | continue; | |
918 | ||
eeb9488e BW |
919 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
920 | if (ret) | |
921 | return ret; | |
6197349b BW |
922 | } |
923 | ||
b4a74e3a BW |
924 | return 0; |
925 | } | |
6197349b | 926 | |
b4a74e3a BW |
927 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
928 | { | |
929 | struct drm_device *dev = ppgtt->base.dev; | |
930 | drm_i915_private_t *dev_priv = dev->dev_private; | |
931 | struct intel_ring_buffer *ring; | |
932 | uint32_t ecochk, gab_ctl, ecobits; | |
933 | int i; | |
a65c2fcd | 934 | |
b4a74e3a BW |
935 | ecobits = I915_READ(GAC_ECO_BITS); |
936 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
937 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 938 | |
b4a74e3a BW |
939 | gab_ctl = I915_READ(GAB_CTL); |
940 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
941 | ||
942 | ecochk = I915_READ(GAM_ECOCHK); | |
943 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
944 | ||
945 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 946 | |
b4a74e3a | 947 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
948 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
949 | if (ret) | |
950 | return ret; | |
6197349b | 951 | } |
b4a74e3a | 952 | |
b7c36d25 | 953 | return 0; |
6197349b BW |
954 | } |
955 | ||
1d2a314c | 956 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 957 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
958 | uint64_t start, |
959 | uint64_t length, | |
828c7908 | 960 | bool use_scratch) |
1d2a314c | 961 | { |
853ba5d2 BW |
962 | struct i915_hw_ppgtt *ppgtt = |
963 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 964 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
965 | unsigned first_entry = start >> PAGE_SHIFT; |
966 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 967 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
968 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
969 | unsigned last_pte, i; | |
1d2a314c | 970 | |
b35b380e | 971 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 972 | |
7bddb01f DV |
973 | while (num_entries) { |
974 | last_pte = first_pte + num_entries; | |
975 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
976 | last_pte = I915_PPGTT_PT_ENTRIES; | |
977 | ||
a15326a5 | 978 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 979 | |
7bddb01f DV |
980 | for (i = first_pte; i < last_pte; i++) |
981 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
982 | |
983 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 984 | |
7bddb01f DV |
985 | num_entries -= last_pte - first_pte; |
986 | first_pte = 0; | |
a15326a5 | 987 | act_pt++; |
7bddb01f | 988 | } |
1d2a314c DV |
989 | } |
990 | ||
853ba5d2 | 991 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 992 | struct sg_table *pages, |
782f1495 | 993 | uint64_t start, |
def886c3 DV |
994 | enum i915_cache_level cache_level) |
995 | { | |
853ba5d2 BW |
996 | struct i915_hw_ppgtt *ppgtt = |
997 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 998 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 999 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 1000 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
1001 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
1002 | struct sg_page_iter sg_iter; | |
1003 | ||
cc79714f | 1004 | pt_vaddr = NULL; |
6e995e23 | 1005 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
1006 | if (pt_vaddr == NULL) |
1007 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 1008 | |
cc79714f CW |
1009 | pt_vaddr[act_pte] = |
1010 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
1011 | cache_level, true); | |
6e995e23 ID |
1012 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
1013 | kunmap_atomic(pt_vaddr); | |
cc79714f | 1014 | pt_vaddr = NULL; |
a15326a5 | 1015 | act_pt++; |
6e995e23 | 1016 | act_pte = 0; |
def886c3 | 1017 | } |
def886c3 | 1018 | } |
cc79714f CW |
1019 | if (pt_vaddr) |
1020 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1021 | } |
1022 | ||
a00d825d | 1023 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 1024 | { |
3440d265 DV |
1025 | int i; |
1026 | ||
1027 | if (ppgtt->pt_dma_addr) { | |
1028 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 1029 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
1030 | ppgtt->pt_dma_addr[i], |
1031 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1032 | } | |
a00d825d BW |
1033 | } |
1034 | ||
1035 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
1036 | { | |
1037 | int i; | |
3440d265 DV |
1038 | |
1039 | kfree(ppgtt->pt_dma_addr); | |
1040 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1041 | __free_page(ppgtt->pt_pages[i]); | |
1042 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1043 | } |
1044 | ||
a00d825d BW |
1045 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1046 | { | |
1047 | struct i915_hw_ppgtt *ppgtt = | |
1048 | container_of(vm, struct i915_hw_ppgtt, base); | |
1049 | ||
1050 | list_del(&vm->global_link); | |
1051 | drm_mm_takedown(&ppgtt->base.mm); | |
1052 | drm_mm_remove_node(&ppgtt->node); | |
1053 | ||
1054 | gen6_ppgtt_unmap_pages(ppgtt); | |
1055 | gen6_ppgtt_free(ppgtt); | |
1056 | } | |
1057 | ||
b146520f | 1058 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1059 | { |
c8d4c0d6 BW |
1060 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
1061 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 1062 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1063 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1064 | bool retried = false; |
b146520f | 1065 | int ret; |
1d2a314c | 1066 | |
c8d4c0d6 BW |
1067 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1068 | * allocator works in address space sizes, so it's multiplied by page | |
1069 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1070 | */ | |
1071 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1072 | alloc: |
c8d4c0d6 BW |
1073 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1074 | &ppgtt->node, GEN6_PD_SIZE, | |
1075 | GEN6_PD_ALIGN, 0, | |
1076 | 0, dev_priv->gtt.base.total, | |
1077 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
1078 | if (ret == -ENOSPC && !retried) { |
1079 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1080 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d47c3ea2 | 1081 | I915_CACHE_NONE, 0); |
e3cc1995 BW |
1082 | if (ret) |
1083 | return ret; | |
1084 | ||
1085 | retried = true; | |
1086 | goto alloc; | |
1087 | } | |
c8d4c0d6 BW |
1088 | |
1089 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1090 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1091 | |
6670a5a5 | 1092 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1093 | return ret; |
1094 | } | |
1095 | ||
1096 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1097 | { | |
1098 | int i; | |
1099 | ||
a1e22653 | 1100 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1101 | GFP_KERNEL); |
b146520f BW |
1102 | |
1103 | if (!ppgtt->pt_pages) | |
3440d265 | 1104 | return -ENOMEM; |
1d2a314c DV |
1105 | |
1106 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1107 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1108 | if (!ppgtt->pt_pages[i]) { |
1109 | gen6_ppgtt_free(ppgtt); | |
1110 | return -ENOMEM; | |
1111 | } | |
1112 | } | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1118 | { | |
1119 | int ret; | |
1120 | ||
1121 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
1125 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1126 | if (ret) { | |
1127 | drm_mm_remove_node(&ppgtt->node); | |
1128 | return ret; | |
1d2a314c DV |
1129 | } |
1130 | ||
a1e22653 | 1131 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1132 | GFP_KERNEL); |
b146520f BW |
1133 | if (!ppgtt->pt_dma_addr) { |
1134 | drm_mm_remove_node(&ppgtt->node); | |
1135 | gen6_ppgtt_free(ppgtt); | |
1136 | return -ENOMEM; | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1143 | { | |
1144 | struct drm_device *dev = ppgtt->base.dev; | |
1145 | int i; | |
1d2a314c | 1146 | |
8d2e6308 BW |
1147 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1148 | dma_addr_t pt_addr; | |
211c568b | 1149 | |
8d2e6308 BW |
1150 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1151 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1152 | |
8d2e6308 | 1153 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1154 | gen6_ppgtt_unmap_pages(ppgtt); |
1155 | return -EIO; | |
211c568b | 1156 | } |
b146520f | 1157 | |
8d2e6308 | 1158 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1159 | } |
1d2a314c | 1160 | |
b146520f BW |
1161 | return 0; |
1162 | } | |
1163 | ||
1164 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1165 | { | |
1166 | struct drm_device *dev = ppgtt->base.dev; | |
1167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1168 | int ret; | |
1169 | ||
1170 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1171 | if (IS_GEN6(dev)) { | |
1172 | ppgtt->enable = gen6_ppgtt_enable; | |
1173 | ppgtt->switch_mm = gen6_mm_switch; | |
1174 | } else if (IS_HASWELL(dev)) { | |
1175 | ppgtt->enable = gen7_ppgtt_enable; | |
1176 | ppgtt->switch_mm = hsw_mm_switch; | |
1177 | } else if (IS_GEN7(dev)) { | |
1178 | ppgtt->enable = gen7_ppgtt_enable; | |
1179 | ppgtt->switch_mm = gen7_mm_switch; | |
1180 | } else | |
1181 | BUG(); | |
1182 | ||
1183 | ret = gen6_ppgtt_alloc(ppgtt); | |
1184 | if (ret) | |
1185 | return ret; | |
1186 | ||
1187 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1188 | if (ret) { | |
1189 | gen6_ppgtt_free(ppgtt); | |
1190 | return ret; | |
1191 | } | |
1192 | ||
1193 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1194 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1195 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1196 | ppgtt->base.start = 0; |
5a6c93fe | 1197 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1198 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1199 | |
c8d4c0d6 BW |
1200 | ppgtt->pd_offset = |
1201 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1202 | |
b146520f | 1203 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1204 | |
b146520f BW |
1205 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1206 | ppgtt->node.size >> 20, | |
1207 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1208 | |
b146520f | 1209 | return 0; |
3440d265 DV |
1210 | } |
1211 | ||
246cbfb5 | 1212 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1213 | { |
1214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1215 | int ret = 0; |
3440d265 | 1216 | |
853ba5d2 | 1217 | ppgtt->base.dev = dev; |
8407bb91 | 1218 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1219 | |
3ed124b2 BW |
1220 | if (INTEL_INFO(dev)->gen < 8) |
1221 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1222 | else if (IS_GEN8(dev)) |
37aca44a | 1223 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1224 | else |
1225 | BUG(); | |
1226 | ||
c7c48dfd | 1227 | if (!ret) { |
7e0d96bc | 1228 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1229 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1230 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1231 | ppgtt->base.total); | |
7e0d96bc BW |
1232 | i915_init_vm(dev_priv, &ppgtt->base); |
1233 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1234 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1235 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1236 | ppgtt->pd_offset << 10); | |
1237 | } | |
93bd8649 | 1238 | } |
1d2a314c DV |
1239 | |
1240 | return ret; | |
1241 | } | |
1242 | ||
7e0d96bc | 1243 | static void |
6f65e29a BW |
1244 | ppgtt_bind_vma(struct i915_vma *vma, |
1245 | enum i915_cache_level cache_level, | |
1246 | u32 flags) | |
1d2a314c | 1247 | { |
782f1495 BW |
1248 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1249 | cache_level); | |
1d2a314c DV |
1250 | } |
1251 | ||
7e0d96bc | 1252 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1253 | { |
6f65e29a | 1254 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1255 | vma->node.start, |
1256 | vma->obj->base.size, | |
6f65e29a | 1257 | true); |
7bddb01f DV |
1258 | } |
1259 | ||
a81cc00c BW |
1260 | extern int intel_iommu_gfx_mapped; |
1261 | /* Certain Gen5 chipsets require require idling the GPU before | |
1262 | * unmapping anything from the GTT when VT-d is enabled. | |
1263 | */ | |
1264 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1265 | { | |
1266 | #ifdef CONFIG_INTEL_IOMMU | |
1267 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1268 | * was loaded first. | |
1269 | */ | |
1270 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1271 | return true; | |
1272 | #endif | |
1273 | return false; | |
1274 | } | |
1275 | ||
5c042287 BW |
1276 | static bool do_idling(struct drm_i915_private *dev_priv) |
1277 | { | |
1278 | bool ret = dev_priv->mm.interruptible; | |
1279 | ||
a81cc00c | 1280 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1281 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1282 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1283 | DRM_ERROR("Couldn't idle GPU\n"); |
1284 | /* Wait a bit, in hopes it avoids the hang */ | |
1285 | udelay(10); | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | return ret; | |
1290 | } | |
1291 | ||
1292 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1293 | { | |
a81cc00c | 1294 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1295 | dev_priv->mm.interruptible = interruptible; |
1296 | } | |
1297 | ||
828c7908 BW |
1298 | void i915_check_and_clear_faults(struct drm_device *dev) |
1299 | { | |
1300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1301 | struct intel_ring_buffer *ring; | |
1302 | int i; | |
1303 | ||
1304 | if (INTEL_INFO(dev)->gen < 6) | |
1305 | return; | |
1306 | ||
1307 | for_each_ring(ring, dev_priv, i) { | |
1308 | u32 fault_reg; | |
1309 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1310 | if (fault_reg & RING_FAULT_VALID) { | |
1311 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1312 | "\tAddr: 0x%08lx\\n" | |
1313 | "\tAddress space: %s\n" | |
1314 | "\tSource ID: %d\n" | |
1315 | "\tType: %d\n", | |
1316 | fault_reg & PAGE_MASK, | |
1317 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1318 | RING_FAULT_SRCID(fault_reg), | |
1319 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1320 | I915_WRITE(RING_FAULT_REG(ring), | |
1321 | fault_reg & ~RING_FAULT_VALID); | |
1322 | } | |
1323 | } | |
1324 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1325 | } | |
1326 | ||
1327 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1328 | { | |
1329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1330 | ||
1331 | /* Don't bother messing with faults pre GEN6 as we have little | |
1332 | * documentation supporting that it's a good idea. | |
1333 | */ | |
1334 | if (INTEL_INFO(dev)->gen < 6) | |
1335 | return; | |
1336 | ||
1337 | i915_check_and_clear_faults(dev); | |
1338 | ||
1339 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1340 | dev_priv->gtt.base.start, |
1341 | dev_priv->gtt.base.total, | |
e568af1c | 1342 | true); |
828c7908 BW |
1343 | } |
1344 | ||
76aaf220 DV |
1345 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1346 | { | |
1347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1348 | struct drm_i915_gem_object *obj; |
80da2161 | 1349 | struct i915_address_space *vm; |
76aaf220 | 1350 | |
828c7908 BW |
1351 | i915_check_and_clear_faults(dev); |
1352 | ||
bee4a186 | 1353 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1354 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1355 | dev_priv->gtt.base.start, |
1356 | dev_priv->gtt.base.total, | |
828c7908 | 1357 | true); |
bee4a186 | 1358 | |
35c20a60 | 1359 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1360 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1361 | &dev_priv->gtt.base); | |
1362 | if (!vma) | |
1363 | continue; | |
1364 | ||
2c22569b | 1365 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1366 | /* The bind_vma code tries to be smart about tracking mappings. |
1367 | * Unfortunately above, we've just wiped out the mappings | |
1368 | * without telling our object about it. So we need to fake it. | |
1369 | */ | |
1370 | obj->has_global_gtt_mapping = 0; | |
1371 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1372 | } |
1373 | ||
80da2161 | 1374 | |
a2319c08 BW |
1375 | if (INTEL_INFO(dev)->gen >= 8) { |
1376 | gen8_setup_private_ppat(dev_priv); | |
80da2161 | 1377 | return; |
a2319c08 | 1378 | } |
80da2161 BW |
1379 | |
1380 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1381 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1382 | if (i915_is_ggtt(vm)) { | |
1383 | if (dev_priv->mm.aliasing_ppgtt) | |
1384 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1385 | continue; | |
1386 | } | |
1387 | ||
1388 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1389 | } |
1390 | ||
e76e9aeb | 1391 | i915_gem_chipset_flush(dev); |
76aaf220 | 1392 | } |
7c2e6fdf | 1393 | |
74163907 | 1394 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1395 | { |
9da3da66 | 1396 | if (obj->has_dma_mapping) |
74163907 | 1397 | return 0; |
9da3da66 CW |
1398 | |
1399 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1400 | obj->pages->sgl, obj->pages->nents, | |
1401 | PCI_DMA_BIDIRECTIONAL)) | |
1402 | return -ENOSPC; | |
1403 | ||
1404 | return 0; | |
7c2e6fdf DV |
1405 | } |
1406 | ||
94ec8f61 BW |
1407 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1408 | { | |
1409 | #ifdef writeq | |
1410 | writeq(pte, addr); | |
1411 | #else | |
1412 | iowrite32((u32)pte, addr); | |
1413 | iowrite32(pte >> 32, addr + 4); | |
1414 | #endif | |
1415 | } | |
1416 | ||
1417 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1418 | struct sg_table *st, | |
782f1495 | 1419 | uint64_t start, |
94ec8f61 BW |
1420 | enum i915_cache_level level) |
1421 | { | |
1422 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1423 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1424 | gen8_gtt_pte_t __iomem *gtt_entries = |
1425 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1426 | int i = 0; | |
1427 | struct sg_page_iter sg_iter; | |
1428 | dma_addr_t addr; | |
1429 | ||
1430 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1431 | addr = sg_dma_address(sg_iter.sg) + | |
1432 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1433 | gen8_set_pte(>t_entries[i], | |
1434 | gen8_pte_encode(addr, level, true)); | |
1435 | i++; | |
1436 | } | |
1437 | ||
1438 | /* | |
1439 | * XXX: This serves as a posting read to make sure that the PTE has | |
1440 | * actually been updated. There is some concern that even though | |
1441 | * registers and PTEs are within the same BAR that they are potentially | |
1442 | * of NUMA access patterns. Therefore, even with the way we assume | |
1443 | * hardware should work, we must keep this posting read for paranoia. | |
1444 | */ | |
1445 | if (i != 0) | |
1446 | WARN_ON(readq(>t_entries[i-1]) | |
1447 | != gen8_pte_encode(addr, level, true)); | |
1448 | ||
94ec8f61 BW |
1449 | /* This next bit makes the above posting read even more important. We |
1450 | * want to flush the TLBs only after we're certain all the PTE updates | |
1451 | * have finished. | |
1452 | */ | |
1453 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1454 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1455 | } |
1456 | ||
e76e9aeb BW |
1457 | /* |
1458 | * Binds an object into the global gtt with the specified cache level. The object | |
1459 | * will be accessible to the GPU via commands whose operands reference offsets | |
1460 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1461 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1462 | */ | |
853ba5d2 | 1463 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1464 | struct sg_table *st, |
782f1495 | 1465 | uint64_t start, |
7faf1ab2 | 1466 | enum i915_cache_level level) |
e76e9aeb | 1467 | { |
853ba5d2 | 1468 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1469 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1470 | gen6_gtt_pte_t __iomem *gtt_entries = |
1471 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1472 | int i = 0; |
1473 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1474 | dma_addr_t addr; |
1475 | ||
6e995e23 | 1476 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1477 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1478 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1479 | i++; |
e76e9aeb BW |
1480 | } |
1481 | ||
e76e9aeb BW |
1482 | /* XXX: This serves as a posting read to make sure that the PTE has |
1483 | * actually been updated. There is some concern that even though | |
1484 | * registers and PTEs are within the same BAR that they are potentially | |
1485 | * of NUMA access patterns. Therefore, even with the way we assume | |
1486 | * hardware should work, we must keep this posting read for paranoia. | |
1487 | */ | |
1488 | if (i != 0) | |
853ba5d2 | 1489 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1490 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1491 | |
1492 | /* This next bit makes the above posting read even more important. We | |
1493 | * want to flush the TLBs only after we're certain all the PTE updates | |
1494 | * have finished. | |
1495 | */ | |
1496 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1497 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1498 | } |
1499 | ||
94ec8f61 | 1500 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1501 | uint64_t start, |
1502 | uint64_t length, | |
94ec8f61 BW |
1503 | bool use_scratch) |
1504 | { | |
1505 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1506 | unsigned first_entry = start >> PAGE_SHIFT; |
1507 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1508 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1509 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1510 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1511 | int i; | |
1512 | ||
1513 | if (WARN(num_entries > max_entries, | |
1514 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1515 | first_entry, num_entries, max_entries)) | |
1516 | num_entries = max_entries; | |
1517 | ||
1518 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1519 | I915_CACHE_LLC, | |
1520 | use_scratch); | |
1521 | for (i = 0; i < num_entries; i++) | |
1522 | gen8_set_pte(>t_base[i], scratch_pte); | |
1523 | readl(gtt_base); | |
1524 | } | |
1525 | ||
853ba5d2 | 1526 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1527 | uint64_t start, |
1528 | uint64_t length, | |
828c7908 | 1529 | bool use_scratch) |
7faf1ab2 | 1530 | { |
853ba5d2 | 1531 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1532 | unsigned first_entry = start >> PAGE_SHIFT; |
1533 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1534 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1535 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1536 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1537 | int i; |
1538 | ||
1539 | if (WARN(num_entries > max_entries, | |
1540 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1541 | first_entry, num_entries, max_entries)) | |
1542 | num_entries = max_entries; | |
1543 | ||
828c7908 BW |
1544 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1545 | ||
7faf1ab2 DV |
1546 | for (i = 0; i < num_entries; i++) |
1547 | iowrite32(scratch_pte, >t_base[i]); | |
1548 | readl(gtt_base); | |
1549 | } | |
1550 | ||
6f65e29a BW |
1551 | |
1552 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1553 | enum i915_cache_level cache_level, | |
1554 | u32 unused) | |
7faf1ab2 | 1555 | { |
6f65e29a | 1556 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1557 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1558 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1559 | ||
6f65e29a BW |
1560 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1561 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1562 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1563 | } |
1564 | ||
853ba5d2 | 1565 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1566 | uint64_t start, |
1567 | uint64_t length, | |
828c7908 | 1568 | bool unused) |
7faf1ab2 | 1569 | { |
782f1495 BW |
1570 | unsigned first_entry = start >> PAGE_SHIFT; |
1571 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1572 | intel_gtt_clear_range(first_entry, num_entries); |
1573 | } | |
1574 | ||
6f65e29a BW |
1575 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1576 | { | |
1577 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1578 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1579 | |
6f65e29a BW |
1580 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1581 | vma->obj->has_global_gtt_mapping = 0; | |
1582 | intel_gtt_clear_range(first, size); | |
1583 | } | |
7faf1ab2 | 1584 | |
6f65e29a BW |
1585 | static void ggtt_bind_vma(struct i915_vma *vma, |
1586 | enum i915_cache_level cache_level, | |
1587 | u32 flags) | |
d5bd1449 | 1588 | { |
6f65e29a | 1589 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1590 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1591 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1592 | |
6f65e29a BW |
1593 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1594 | * or we have a global mapping already but the cacheability flags have | |
1595 | * changed, set the global PTEs. | |
1596 | * | |
1597 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1598 | * instead if none of the above hold true. | |
1599 | * | |
1600 | * NB: A global mapping should only be needed for special regions like | |
1601 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1602 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1603 | */ | |
1604 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1605 | if (!obj->has_global_gtt_mapping || | |
1606 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1607 | vma->vm->insert_entries(vma->vm, obj->pages, |
1608 | vma->node.start, | |
6f65e29a BW |
1609 | cache_level); |
1610 | obj->has_global_gtt_mapping = 1; | |
1611 | } | |
1612 | } | |
d5bd1449 | 1613 | |
6f65e29a BW |
1614 | if (dev_priv->mm.aliasing_ppgtt && |
1615 | (!obj->has_aliasing_ppgtt_mapping || | |
1616 | (cache_level != obj->cache_level))) { | |
1617 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1618 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1619 | vma->obj->pages, |
1620 | vma->node.start, | |
1621 | cache_level); | |
6f65e29a BW |
1622 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1623 | } | |
d5bd1449 CW |
1624 | } |
1625 | ||
6f65e29a | 1626 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1627 | { |
6f65e29a | 1628 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1629 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1630 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1631 | |
1632 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1633 | vma->vm->clear_range(vma->vm, |
1634 | vma->node.start, | |
1635 | obj->base.size, | |
6f65e29a BW |
1636 | true); |
1637 | obj->has_global_gtt_mapping = 0; | |
1638 | } | |
74898d7e | 1639 | |
6f65e29a BW |
1640 | if (obj->has_aliasing_ppgtt_mapping) { |
1641 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1642 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1643 | vma->node.start, |
1644 | obj->base.size, | |
6f65e29a BW |
1645 | true); |
1646 | obj->has_aliasing_ppgtt_mapping = 0; | |
1647 | } | |
74163907 DV |
1648 | } |
1649 | ||
1650 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1651 | { |
5c042287 BW |
1652 | struct drm_device *dev = obj->base.dev; |
1653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1654 | bool interruptible; | |
1655 | ||
1656 | interruptible = do_idling(dev_priv); | |
1657 | ||
9da3da66 CW |
1658 | if (!obj->has_dma_mapping) |
1659 | dma_unmap_sg(&dev->pdev->dev, | |
1660 | obj->pages->sgl, obj->pages->nents, | |
1661 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1662 | |
1663 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1664 | } |
644ec02b | 1665 | |
42d6ab48 CW |
1666 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1667 | unsigned long color, | |
1668 | unsigned long *start, | |
1669 | unsigned long *end) | |
1670 | { | |
1671 | if (node->color != color) | |
1672 | *start += 4096; | |
1673 | ||
1674 | if (!list_empty(&node->node_list)) { | |
1675 | node = list_entry(node->node_list.next, | |
1676 | struct drm_mm_node, | |
1677 | node_list); | |
1678 | if (node->allocated && node->color != color) | |
1679 | *end -= 4096; | |
1680 | } | |
1681 | } | |
fbe5d36e | 1682 | |
d7e5008f BW |
1683 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1684 | unsigned long start, | |
1685 | unsigned long mappable_end, | |
1686 | unsigned long end) | |
644ec02b | 1687 | { |
e78891ca BW |
1688 | /* Let GEM Manage all of the aperture. |
1689 | * | |
1690 | * However, leave one page at the end still bound to the scratch page. | |
1691 | * There are a number of places where the hardware apparently prefetches | |
1692 | * past the end of the object, and we've seen multiple hangs with the | |
1693 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1694 | * aperture. One page should be enough to keep any prefetching inside | |
1695 | * of the aperture. | |
1696 | */ | |
40d74980 BW |
1697 | struct drm_i915_private *dev_priv = dev->dev_private; |
1698 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1699 | struct drm_mm_node *entry; |
1700 | struct drm_i915_gem_object *obj; | |
1701 | unsigned long hole_start, hole_end; | |
644ec02b | 1702 | |
35451cb6 BW |
1703 | BUG_ON(mappable_end > end); |
1704 | ||
ed2f3452 | 1705 | /* Subtract the guard page ... */ |
40d74980 | 1706 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1707 | if (!HAS_LLC(dev)) |
93bd8649 | 1708 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1709 | |
ed2f3452 | 1710 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1711 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1712 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1713 | int ret; |
edd41a87 | 1714 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1715 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1716 | ||
1717 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1718 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1719 | if (ret) |
b3a070cc | 1720 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1721 | obj->has_global_gtt_mapping = 1; |
1722 | } | |
1723 | ||
853ba5d2 BW |
1724 | dev_priv->gtt.base.start = start; |
1725 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1726 | |
ed2f3452 | 1727 | /* Clear any non-preallocated blocks */ |
40d74980 | 1728 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1729 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1730 | hole_start, hole_end); | |
782f1495 BW |
1731 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1732 | hole_end - hole_start, true); | |
ed2f3452 CW |
1733 | } |
1734 | ||
1735 | /* And finally clear the reserved guard page */ | |
782f1495 | 1736 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1737 | } |
1738 | ||
d7e5008f BW |
1739 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1740 | { | |
1741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1742 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1743 | |
853ba5d2 | 1744 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1745 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1746 | |
e78891ca | 1747 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1748 | } |
1749 | ||
1750 | static int setup_scratch_page(struct drm_device *dev) | |
1751 | { | |
1752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1753 | struct page *page; | |
1754 | dma_addr_t dma_addr; | |
1755 | ||
1756 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1757 | if (page == NULL) | |
1758 | return -ENOMEM; | |
1759 | get_page(page); | |
1760 | set_pages_uc(page, 1); | |
1761 | ||
1762 | #ifdef CONFIG_INTEL_IOMMU | |
1763 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1764 | PCI_DMA_BIDIRECTIONAL); | |
1765 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1766 | return -EINVAL; | |
1767 | #else | |
1768 | dma_addr = page_to_phys(page); | |
1769 | #endif | |
853ba5d2 BW |
1770 | dev_priv->gtt.base.scratch.page = page; |
1771 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1772 | |
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | static void teardown_scratch_page(struct drm_device *dev) | |
1777 | { | |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1779 | struct page *page = dev_priv->gtt.base.scratch.page; |
1780 | ||
1781 | set_pages_wb(page, 1); | |
1782 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1783 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1784 | put_page(page); |
1785 | __free_page(page); | |
e76e9aeb BW |
1786 | } |
1787 | ||
1788 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1789 | { | |
1790 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1791 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1792 | return snb_gmch_ctl << 20; | |
1793 | } | |
1794 | ||
9459d252 BW |
1795 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1796 | { | |
1797 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1798 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1799 | if (bdw_gmch_ctl) | |
1800 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1801 | return bdw_gmch_ctl << 20; | |
1802 | } | |
1803 | ||
baa09f5f | 1804 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1805 | { |
1806 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1807 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1808 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1809 | } | |
1810 | ||
9459d252 BW |
1811 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1812 | { | |
1813 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1814 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1815 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1816 | } | |
1817 | ||
63340133 BW |
1818 | static int ggtt_probe_common(struct drm_device *dev, |
1819 | size_t gtt_size) | |
1820 | { | |
1821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1822 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1823 | int ret; |
1824 | ||
1825 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1826 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1827 | (pci_resource_len(dev->pdev, 0) / 2); |
1828 | ||
21c34607 | 1829 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1830 | if (!dev_priv->gtt.gsm) { |
1831 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1832 | return -ENOMEM; | |
1833 | } | |
1834 | ||
1835 | ret = setup_scratch_page(dev); | |
1836 | if (ret) { | |
1837 | DRM_ERROR("Scratch setup failed\n"); | |
1838 | /* iounmap will also get called at remove, but meh */ | |
1839 | iounmap(dev_priv->gtt.gsm); | |
1840 | } | |
1841 | ||
1842 | return ret; | |
1843 | } | |
1844 | ||
fbe5d36e BW |
1845 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1846 | * bits. When using advanced contexts each context stores its own PAT, but | |
1847 | * writing this data shouldn't be harmful even in those cases. */ | |
1848 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1849 | { | |
1850 | #define GEN8_PPAT_UC (0<<0) | |
1851 | #define GEN8_PPAT_WC (1<<0) | |
1852 | #define GEN8_PPAT_WT (2<<0) | |
1853 | #define GEN8_PPAT_WB (3<<0) | |
1854 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1855 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1856 | #define GEN8_PPAT_LLC (1<<2) | |
1857 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1858 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1859 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1860 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1861 | uint64_t pat; | |
1862 | ||
1863 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1864 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1865 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1866 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1867 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1868 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1869 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1870 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1871 | ||
1872 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1873 | * write would work. */ | |
1874 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1875 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1876 | } | |
1877 | ||
63340133 BW |
1878 | static int gen8_gmch_probe(struct drm_device *dev, |
1879 | size_t *gtt_total, | |
1880 | size_t *stolen, | |
1881 | phys_addr_t *mappable_base, | |
1882 | unsigned long *mappable_end) | |
1883 | { | |
1884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1885 | unsigned int gtt_size; | |
1886 | u16 snb_gmch_ctl; | |
1887 | int ret; | |
1888 | ||
1889 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1890 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1891 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1892 | ||
1893 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1894 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1895 | ||
1896 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1897 | ||
1898 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1899 | ||
1900 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1901 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1902 | |
fbe5d36e BW |
1903 | gen8_setup_private_ppat(dev_priv); |
1904 | ||
63340133 BW |
1905 | ret = ggtt_probe_common(dev, gtt_size); |
1906 | ||
94ec8f61 BW |
1907 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1908 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1909 | |
1910 | return ret; | |
1911 | } | |
1912 | ||
baa09f5f BW |
1913 | static int gen6_gmch_probe(struct drm_device *dev, |
1914 | size_t *gtt_total, | |
41907ddc BW |
1915 | size_t *stolen, |
1916 | phys_addr_t *mappable_base, | |
1917 | unsigned long *mappable_end) | |
e76e9aeb BW |
1918 | { |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1920 | unsigned int gtt_size; |
e76e9aeb | 1921 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1922 | int ret; |
1923 | ||
41907ddc BW |
1924 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1925 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1926 | ||
baa09f5f BW |
1927 | /* 64/512MB is the current min/max we actually know of, but this is just |
1928 | * a coarse sanity check. | |
e76e9aeb | 1929 | */ |
41907ddc | 1930 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1931 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1932 | dev_priv->gtt.mappable_end); | |
1933 | return -ENXIO; | |
e76e9aeb BW |
1934 | } |
1935 | ||
e76e9aeb BW |
1936 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1937 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1938 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1939 | |
c4ae25ec | 1940 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1941 | |
63340133 BW |
1942 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1943 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1944 | |
63340133 | 1945 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1946 | |
853ba5d2 BW |
1947 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1948 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1949 | |
e76e9aeb BW |
1950 | return ret; |
1951 | } | |
1952 | ||
853ba5d2 | 1953 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1954 | { |
853ba5d2 BW |
1955 | |
1956 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1957 | |
1958 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1959 | iounmap(gtt->gsm); |
1960 | teardown_scratch_page(vm->dev); | |
644ec02b | 1961 | } |
baa09f5f BW |
1962 | |
1963 | static int i915_gmch_probe(struct drm_device *dev, | |
1964 | size_t *gtt_total, | |
41907ddc BW |
1965 | size_t *stolen, |
1966 | phys_addr_t *mappable_base, | |
1967 | unsigned long *mappable_end) | |
baa09f5f BW |
1968 | { |
1969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1970 | int ret; | |
1971 | ||
baa09f5f BW |
1972 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1973 | if (!ret) { | |
1974 | DRM_ERROR("failed to set up gmch\n"); | |
1975 | return -EIO; | |
1976 | } | |
1977 | ||
41907ddc | 1978 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1979 | |
1980 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1981 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 1982 | |
c0a7f818 CW |
1983 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
1984 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
1985 | ||
baa09f5f BW |
1986 | return 0; |
1987 | } | |
1988 | ||
853ba5d2 | 1989 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1990 | { |
1991 | intel_gmch_remove(); | |
1992 | } | |
1993 | ||
1994 | int i915_gem_gtt_init(struct drm_device *dev) | |
1995 | { | |
1996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1997 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1998 | int ret; |
1999 | ||
baa09f5f | 2000 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2001 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2002 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2003 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2004 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2005 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2006 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2007 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2008 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2009 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2010 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2011 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2012 | else if (INTEL_INFO(dev)->gen >= 7) |
2013 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2014 | else |
350ec881 | 2015 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2016 | } else { |
2017 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2018 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2019 | } |
2020 | ||
853ba5d2 | 2021 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2022 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2023 | if (ret) |
baa09f5f | 2024 | return ret; |
baa09f5f | 2025 | |
853ba5d2 BW |
2026 | gtt->base.dev = dev; |
2027 | ||
baa09f5f | 2028 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2029 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2030 | gtt->base.total >> 20); | |
b2f21b4d BW |
2031 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2032 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
2033 | |
2034 | return 0; | |
2035 | } | |
6f65e29a BW |
2036 | |
2037 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2038 | struct i915_address_space *vm) | |
2039 | { | |
2040 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2041 | if (vma == NULL) | |
2042 | return ERR_PTR(-ENOMEM); | |
2043 | ||
2044 | INIT_LIST_HEAD(&vma->vma_link); | |
2045 | INIT_LIST_HEAD(&vma->mm_list); | |
2046 | INIT_LIST_HEAD(&vma->exec_list); | |
2047 | vma->vm = vm; | |
2048 | vma->obj = obj; | |
2049 | ||
2050 | switch (INTEL_INFO(vm->dev)->gen) { | |
2051 | case 8: | |
2052 | case 7: | |
2053 | case 6: | |
7e0d96bc BW |
2054 | if (i915_is_ggtt(vm)) { |
2055 | vma->unbind_vma = ggtt_unbind_vma; | |
2056 | vma->bind_vma = ggtt_bind_vma; | |
2057 | } else { | |
2058 | vma->unbind_vma = ppgtt_unbind_vma; | |
2059 | vma->bind_vma = ppgtt_bind_vma; | |
2060 | } | |
6f65e29a BW |
2061 | break; |
2062 | case 5: | |
2063 | case 4: | |
2064 | case 3: | |
2065 | case 2: | |
2066 | BUG_ON(!i915_is_ggtt(vm)); | |
2067 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2068 | vma->bind_vma = i915_ggtt_bind_vma; | |
2069 | break; | |
2070 | default: | |
2071 | BUG(); | |
2072 | } | |
2073 | ||
2074 | /* Keep GGTT vmas first to make debug easier */ | |
2075 | if (i915_is_ggtt(vm)) | |
2076 | list_add(&vma->vma_link, &obj->vma_list); | |
2077 | else | |
2078 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2079 | ||
2080 | return vma; | |
2081 | } | |
2082 | ||
2083 | struct i915_vma * | |
2084 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2085 | struct i915_address_space *vm) | |
2086 | { | |
2087 | struct i915_vma *vma; | |
2088 | ||
2089 | vma = i915_gem_obj_to_vma(obj, vm); | |
2090 | if (!vma) | |
2091 | vma = __i915_gem_vma_create(obj, vm); | |
2092 | ||
2093 | return vma; | |
2094 | } |