Commit | Line | Data |
---|---|---|
76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
fe14d5f4 | 95 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
96 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
97 | .type = I915_GGTT_VIEW_ROTATED | |
98 | }; | |
fe14d5f4 | 99 | |
cfa7c862 DV |
100 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
101 | { | |
1893a71b CW |
102 | bool has_aliasing_ppgtt; |
103 | bool has_full_ppgtt; | |
104 | ||
105 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
106 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 107 | |
71ba2d64 YZ |
108 | if (intel_vgpu_active(dev)) |
109 | has_full_ppgtt = false; /* emulation is too hard */ | |
110 | ||
70ee45e1 DL |
111 | /* |
112 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
113 | * execlists, the sole mechanism available to submit work. | |
114 | */ | |
115 | if (INTEL_INFO(dev)->gen < 9 && | |
116 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
117 | return 0; |
118 | ||
119 | if (enable_ppgtt == 1) | |
120 | return 1; | |
121 | ||
1893a71b | 122 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
123 | return 2; |
124 | ||
93a25a9e DV |
125 | #ifdef CONFIG_INTEL_IOMMU |
126 | /* Disable ppgtt on SNB if VT-d is on. */ | |
127 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
128 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 129 | return 0; |
93a25a9e DV |
130 | } |
131 | #endif | |
132 | ||
62942ed7 | 133 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
134 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
135 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
136 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
137 | return 0; | |
138 | } | |
139 | ||
2f82bbdf MT |
140 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
141 | return 2; | |
142 | else | |
143 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
144 | } |
145 | ||
6f65e29a BW |
146 | static void ppgtt_bind_vma(struct i915_vma *vma, |
147 | enum i915_cache_level cache_level, | |
47552659 DV |
148 | u32 unused) |
149 | { | |
150 | u32 pte_flags = 0; | |
151 | ||
152 | /* Currently applicable only to VLV */ | |
153 | if (vma->obj->gt_ro) | |
154 | pte_flags |= PTE_READ_ONLY; | |
155 | ||
156 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
157 | cache_level, pte_flags); | |
158 | } | |
159 | ||
160 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
161 | { | |
162 | vma->vm->clear_range(vma->vm, | |
163 | vma->node.start, | |
164 | vma->obj->base.size, | |
165 | true); | |
166 | } | |
6f65e29a | 167 | |
07749ef3 MT |
168 | static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
169 | enum i915_cache_level level, | |
170 | bool valid) | |
94ec8f61 | 171 | { |
07749ef3 | 172 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 173 | pte |= addr; |
63c42e56 BW |
174 | |
175 | switch (level) { | |
176 | case I915_CACHE_NONE: | |
fbe5d36e | 177 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
178 | break; |
179 | case I915_CACHE_WT: | |
180 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
181 | break; | |
182 | default: | |
183 | pte |= PPAT_CACHED_INDEX; | |
184 | break; | |
185 | } | |
186 | ||
94ec8f61 BW |
187 | return pte; |
188 | } | |
189 | ||
07749ef3 MT |
190 | static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
191 | dma_addr_t addr, | |
192 | enum i915_cache_level level) | |
b1fe6673 | 193 | { |
07749ef3 | 194 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
195 | pde |= addr; |
196 | if (level != I915_CACHE_NONE) | |
197 | pde |= PPAT_CACHED_PDE_INDEX; | |
198 | else | |
199 | pde |= PPAT_UNCACHED_INDEX; | |
200 | return pde; | |
201 | } | |
202 | ||
07749ef3 MT |
203 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
204 | enum i915_cache_level level, | |
205 | bool valid, u32 unused) | |
54d12527 | 206 | { |
07749ef3 | 207 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 208 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
209 | |
210 | switch (level) { | |
350ec881 CW |
211 | case I915_CACHE_L3_LLC: |
212 | case I915_CACHE_LLC: | |
213 | pte |= GEN6_PTE_CACHE_LLC; | |
214 | break; | |
215 | case I915_CACHE_NONE: | |
216 | pte |= GEN6_PTE_UNCACHED; | |
217 | break; | |
218 | default: | |
5f77eeb0 | 219 | MISSING_CASE(level); |
350ec881 CW |
220 | } |
221 | ||
222 | return pte; | |
223 | } | |
224 | ||
07749ef3 MT |
225 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
226 | enum i915_cache_level level, | |
227 | bool valid, u32 unused) | |
350ec881 | 228 | { |
07749ef3 | 229 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
230 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
231 | ||
232 | switch (level) { | |
233 | case I915_CACHE_L3_LLC: | |
234 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
235 | break; |
236 | case I915_CACHE_LLC: | |
237 | pte |= GEN6_PTE_CACHE_LLC; | |
238 | break; | |
239 | case I915_CACHE_NONE: | |
9119708c | 240 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
241 | break; |
242 | default: | |
5f77eeb0 | 243 | MISSING_CASE(level); |
e7210c3c BW |
244 | } |
245 | ||
54d12527 BW |
246 | return pte; |
247 | } | |
248 | ||
07749ef3 MT |
249 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
250 | enum i915_cache_level level, | |
251 | bool valid, u32 flags) | |
93c34e70 | 252 | { |
07749ef3 | 253 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
254 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
255 | ||
24f3a8cf AG |
256 | if (!(flags & PTE_READ_ONLY)) |
257 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
258 | |
259 | if (level != I915_CACHE_NONE) | |
260 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
261 | ||
262 | return pte; | |
263 | } | |
264 | ||
07749ef3 MT |
265 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
266 | enum i915_cache_level level, | |
267 | bool valid, u32 unused) | |
9119708c | 268 | { |
07749ef3 | 269 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 270 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
271 | |
272 | if (level != I915_CACHE_NONE) | |
87a6b688 | 273 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
274 | |
275 | return pte; | |
276 | } | |
277 | ||
07749ef3 MT |
278 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
279 | enum i915_cache_level level, | |
280 | bool valid, u32 unused) | |
4d15c145 | 281 | { |
07749ef3 | 282 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
283 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
284 | ||
651d794f CW |
285 | switch (level) { |
286 | case I915_CACHE_NONE: | |
287 | break; | |
288 | case I915_CACHE_WT: | |
c51e9701 | 289 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
290 | break; |
291 | default: | |
c51e9701 | 292 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
293 | break; |
294 | } | |
4d15c145 BW |
295 | |
296 | return pte; | |
297 | } | |
298 | ||
678d96fb BW |
299 | #define i915_dma_unmap_single(px, dev) \ |
300 | __i915_dma_unmap_single((px)->daddr, dev) | |
301 | ||
302 | static inline void __i915_dma_unmap_single(dma_addr_t daddr, | |
303 | struct drm_device *dev) | |
304 | { | |
305 | struct device *device = &dev->pdev->dev; | |
306 | ||
307 | dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); | |
308 | } | |
309 | ||
310 | /** | |
311 | * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. | |
312 | * @px: Page table/dir/etc to get a DMA map for | |
313 | * @dev: drm device | |
314 | * | |
315 | * Page table allocations are unified across all gens. They always require a | |
316 | * single 4k allocation, as well as a DMA mapping. If we keep the structs | |
317 | * symmetric here, the simple macro covers us for every page table type. | |
318 | * | |
319 | * Return: 0 if success. | |
320 | */ | |
321 | #define i915_dma_map_single(px, dev) \ | |
322 | i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) | |
323 | ||
324 | static inline int i915_dma_map_page_single(struct page *page, | |
325 | struct drm_device *dev, | |
326 | dma_addr_t *daddr) | |
327 | { | |
328 | struct device *device = &dev->pdev->dev; | |
329 | ||
330 | *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
1266cdb1 MT |
331 | if (dma_mapping_error(device, *daddr)) |
332 | return -ENOMEM; | |
333 | ||
334 | return 0; | |
678d96fb BW |
335 | } |
336 | ||
ec565b3c | 337 | static void unmap_and_free_pt(struct i915_page_table *pt, |
678d96fb | 338 | struct drm_device *dev) |
06fda602 BW |
339 | { |
340 | if (WARN_ON(!pt->page)) | |
341 | return; | |
678d96fb BW |
342 | |
343 | i915_dma_unmap_single(pt, dev); | |
06fda602 | 344 | __free_page(pt->page); |
678d96fb | 345 | kfree(pt->used_ptes); |
06fda602 BW |
346 | kfree(pt); |
347 | } | |
348 | ||
5a8e9943 | 349 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 350 | struct i915_page_table *pt) |
5a8e9943 MT |
351 | { |
352 | gen8_pte_t *pt_vaddr, scratch_pte; | |
353 | int i; | |
354 | ||
355 | pt_vaddr = kmap_atomic(pt->page); | |
356 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
357 | I915_CACHE_LLC, true); | |
358 | ||
359 | for (i = 0; i < GEN8_PTES; i++) | |
360 | pt_vaddr[i] = scratch_pte; | |
361 | ||
362 | if (!HAS_LLC(vm->dev)) | |
363 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
364 | kunmap_atomic(pt_vaddr); | |
365 | } | |
366 | ||
ec565b3c | 367 | static struct i915_page_table *alloc_pt_single(struct drm_device *dev) |
06fda602 | 368 | { |
ec565b3c | 369 | struct i915_page_table *pt; |
678d96fb BW |
370 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
371 | GEN8_PTES : GEN6_PTES; | |
372 | int ret = -ENOMEM; | |
06fda602 BW |
373 | |
374 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
375 | if (!pt) | |
376 | return ERR_PTR(-ENOMEM); | |
377 | ||
678d96fb BW |
378 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
379 | GFP_KERNEL); | |
380 | ||
381 | if (!pt->used_ptes) | |
382 | goto fail_bitmap; | |
383 | ||
4933d519 | 384 | pt->page = alloc_page(GFP_KERNEL); |
678d96fb BW |
385 | if (!pt->page) |
386 | goto fail_page; | |
387 | ||
388 | ret = i915_dma_map_single(pt, dev); | |
389 | if (ret) | |
390 | goto fail_dma; | |
06fda602 BW |
391 | |
392 | return pt; | |
678d96fb BW |
393 | |
394 | fail_dma: | |
395 | __free_page(pt->page); | |
396 | fail_page: | |
397 | kfree(pt->used_ptes); | |
398 | fail_bitmap: | |
399 | kfree(pt); | |
400 | ||
401 | return ERR_PTR(ret); | |
06fda602 BW |
402 | } |
403 | ||
e5815a2e MT |
404 | static void unmap_and_free_pd(struct i915_page_directory *pd, |
405 | struct drm_device *dev) | |
06fda602 BW |
406 | { |
407 | if (pd->page) { | |
e5815a2e | 408 | i915_dma_unmap_single(pd, dev); |
06fda602 | 409 | __free_page(pd->page); |
33c8819f | 410 | kfree(pd->used_pdes); |
06fda602 BW |
411 | kfree(pd); |
412 | } | |
413 | } | |
414 | ||
e5815a2e | 415 | static struct i915_page_directory *alloc_pd_single(struct drm_device *dev) |
06fda602 | 416 | { |
ec565b3c | 417 | struct i915_page_directory *pd; |
33c8819f | 418 | int ret = -ENOMEM; |
06fda602 BW |
419 | |
420 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
421 | if (!pd) | |
422 | return ERR_PTR(-ENOMEM); | |
423 | ||
33c8819f MT |
424 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
425 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
426 | if (!pd->used_pdes) | |
427 | goto free_pd; | |
428 | ||
5a8e9943 | 429 | pd->page = alloc_page(GFP_KERNEL); |
33c8819f MT |
430 | if (!pd->page) |
431 | goto free_bitmap; | |
06fda602 | 432 | |
e5815a2e | 433 | ret = i915_dma_map_single(pd, dev); |
33c8819f MT |
434 | if (ret) |
435 | goto free_page; | |
e5815a2e | 436 | |
06fda602 | 437 | return pd; |
33c8819f MT |
438 | |
439 | free_page: | |
440 | __free_page(pd->page); | |
441 | free_bitmap: | |
442 | kfree(pd->used_pdes); | |
443 | free_pd: | |
444 | kfree(pd); | |
445 | ||
446 | return ERR_PTR(ret); | |
06fda602 BW |
447 | } |
448 | ||
94e409c1 | 449 | /* Broadwell Page Directory Pointer Descriptors */ |
7cb6d7ac MT |
450 | static int gen8_write_pdp(struct intel_engine_cs *ring, |
451 | unsigned entry, | |
452 | dma_addr_t addr) | |
94e409c1 BW |
453 | { |
454 | int ret; | |
455 | ||
456 | BUG_ON(entry >= 4); | |
457 | ||
458 | ret = intel_ring_begin(ring, 6); | |
459 | if (ret) | |
460 | return ret; | |
461 | ||
462 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
463 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 464 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
465 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
466 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 467 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
468 | intel_ring_advance(ring); |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
eeb9488e | 473 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 474 | struct intel_engine_cs *ring) |
94e409c1 | 475 | { |
eeb9488e | 476 | int i, ret; |
94e409c1 | 477 | |
7cb6d7ac MT |
478 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
479 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[i]; | |
480 | dma_addr_t pd_daddr = pd ? pd->daddr : ppgtt->scratch_pd->daddr; | |
481 | /* The page directory might be NULL, but we need to clear out | |
482 | * whatever the previous context might have used. */ | |
483 | ret = gen8_write_pdp(ring, i, pd_daddr); | |
eeb9488e BW |
484 | if (ret) |
485 | return ret; | |
94e409c1 | 486 | } |
d595bd4b | 487 | |
eeb9488e | 488 | return 0; |
94e409c1 BW |
489 | } |
490 | ||
459108b8 | 491 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
492 | uint64_t start, |
493 | uint64_t length, | |
459108b8 BW |
494 | bool use_scratch) |
495 | { | |
496 | struct i915_hw_ppgtt *ppgtt = | |
497 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 498 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
499 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
500 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
501 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 502 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
503 | unsigned last_pte, i; |
504 | ||
505 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
506 | I915_CACHE_LLC, use_scratch); | |
507 | ||
508 | while (num_entries) { | |
ec565b3c MT |
509 | struct i915_page_directory *pd; |
510 | struct i915_page_table *pt; | |
06fda602 BW |
511 | struct page *page_table; |
512 | ||
513 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
514 | continue; | |
515 | ||
516 | pd = ppgtt->pdp.page_directory[pdpe]; | |
517 | ||
518 | if (WARN_ON(!pd->page_table[pde])) | |
519 | continue; | |
520 | ||
521 | pt = pd->page_table[pde]; | |
522 | ||
523 | if (WARN_ON(!pt->page)) | |
524 | continue; | |
525 | ||
526 | page_table = pt->page; | |
459108b8 | 527 | |
7ad47cf2 | 528 | last_pte = pte + num_entries; |
07749ef3 MT |
529 | if (last_pte > GEN8_PTES) |
530 | last_pte = GEN8_PTES; | |
459108b8 BW |
531 | |
532 | pt_vaddr = kmap_atomic(page_table); | |
533 | ||
7ad47cf2 | 534 | for (i = pte; i < last_pte; i++) { |
459108b8 | 535 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
536 | num_entries--; |
537 | } | |
459108b8 | 538 | |
fd1ab8f4 RB |
539 | if (!HAS_LLC(ppgtt->base.dev)) |
540 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
541 | kunmap_atomic(pt_vaddr); |
542 | ||
7ad47cf2 | 543 | pte = 0; |
07749ef3 | 544 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
545 | pdpe++; |
546 | pde = 0; | |
547 | } | |
459108b8 BW |
548 | } |
549 | } | |
550 | ||
9df15b49 BW |
551 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
552 | struct sg_table *pages, | |
782f1495 | 553 | uint64_t start, |
24f3a8cf | 554 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
555 | { |
556 | struct i915_hw_ppgtt *ppgtt = | |
557 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 558 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
559 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
560 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
561 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
562 | struct sg_page_iter sg_iter; |
563 | ||
6f1cc993 | 564 | pt_vaddr = NULL; |
7ad47cf2 | 565 | |
9df15b49 | 566 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 567 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
568 | break; |
569 | ||
d7b3de91 | 570 | if (pt_vaddr == NULL) { |
ec565b3c MT |
571 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
572 | struct i915_page_table *pt = pd->page_table[pde]; | |
06fda602 | 573 | struct page *page_table = pt->page; |
d7b3de91 BW |
574 | |
575 | pt_vaddr = kmap_atomic(page_table); | |
576 | } | |
9df15b49 | 577 | |
7ad47cf2 | 578 | pt_vaddr[pte] = |
6f1cc993 CW |
579 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
580 | cache_level, true); | |
07749ef3 | 581 | if (++pte == GEN8_PTES) { |
fd1ab8f4 RB |
582 | if (!HAS_LLC(ppgtt->base.dev)) |
583 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 584 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 585 | pt_vaddr = NULL; |
07749ef3 | 586 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
587 | pdpe++; |
588 | pde = 0; | |
589 | } | |
590 | pte = 0; | |
9df15b49 BW |
591 | } |
592 | } | |
fd1ab8f4 RB |
593 | if (pt_vaddr) { |
594 | if (!HAS_LLC(ppgtt->base.dev)) | |
595 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 596 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 597 | } |
9df15b49 BW |
598 | } |
599 | ||
69876bed MT |
600 | static void __gen8_do_map_pt(gen8_pde_t * const pde, |
601 | struct i915_page_table *pt, | |
602 | struct drm_device *dev) | |
603 | { | |
604 | gen8_pde_t entry = | |
605 | gen8_pde_encode(dev, pt->daddr, I915_CACHE_LLC); | |
606 | *pde = entry; | |
607 | } | |
608 | ||
609 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
610 | struct i915_page_directory *pd) | |
611 | { | |
612 | struct i915_hw_ppgtt *ppgtt = | |
613 | container_of(vm, struct i915_hw_ppgtt, base); | |
614 | gen8_pde_t *page_directory; | |
615 | struct i915_page_table *pt; | |
616 | int i; | |
617 | ||
618 | page_directory = kmap_atomic(pd->page); | |
619 | pt = ppgtt->scratch_pt; | |
620 | for (i = 0; i < I915_PDES; i++) | |
621 | /* Map the PDE to the page table */ | |
622 | __gen8_do_map_pt(page_directory + i, pt, vm->dev); | |
623 | ||
624 | if (!HAS_LLC(vm->dev)) | |
625 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
e5815a2e MT |
626 | kunmap_atomic(page_directory); |
627 | } | |
628 | ||
ec565b3c | 629 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
630 | { |
631 | int i; | |
632 | ||
06fda602 | 633 | if (!pd->page) |
7ad47cf2 BW |
634 | return; |
635 | ||
33c8819f | 636 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
637 | if (WARN_ON(!pd->page_table[i])) |
638 | continue; | |
7ad47cf2 | 639 | |
06dc68d6 | 640 | unmap_and_free_pt(pd->page_table[i], dev); |
06fda602 BW |
641 | pd->page_table[i] = NULL; |
642 | } | |
d7b3de91 BW |
643 | } |
644 | ||
061dd493 | 645 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 646 | { |
061dd493 DV |
647 | struct i915_hw_ppgtt *ppgtt = |
648 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
649 | int i; |
650 | ||
33c8819f | 651 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
652 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
653 | continue; | |
654 | ||
06dc68d6 | 655 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
e5815a2e | 656 | unmap_and_free_pd(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
7ad47cf2 | 657 | } |
69876bed | 658 | |
e5815a2e | 659 | unmap_and_free_pd(ppgtt->scratch_pd, ppgtt->base.dev); |
69876bed | 660 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
b45a6715 BW |
661 | } |
662 | ||
d7b2633d MT |
663 | /** |
664 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
665 | * @ppgtt: Master ppgtt structure. | |
666 | * @pd: Page directory for this address range. | |
667 | * @start: Starting virtual address to begin allocations. | |
668 | * @length Size of the allocations. | |
669 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
670 | * caller to free on error. | |
671 | * | |
672 | * Allocate the required number of page tables. Extremely similar to | |
673 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
674 | * the page directory boundary (instead of the page directory pointer). That | |
675 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
676 | * possible, and likely that the caller will need to use multiple calls of this | |
677 | * function to achieve the appropriate allocation. | |
678 | * | |
679 | * Return: 0 if success; negative error code otherwise. | |
680 | */ | |
e5815a2e MT |
681 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
682 | struct i915_page_directory *pd, | |
5441f0cb | 683 | uint64_t start, |
d7b2633d MT |
684 | uint64_t length, |
685 | unsigned long *new_pts) | |
bf2b4ed2 | 686 | { |
e5815a2e | 687 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 688 | struct i915_page_table *pt; |
5441f0cb MT |
689 | uint64_t temp; |
690 | uint32_t pde; | |
bf2b4ed2 | 691 | |
d7b2633d MT |
692 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
693 | /* Don't reallocate page tables */ | |
694 | if (pt) { | |
695 | /* Scratch is never allocated this way */ | |
696 | WARN_ON(pt == ppgtt->scratch_pt); | |
697 | continue; | |
698 | } | |
699 | ||
700 | pt = alloc_pt_single(dev); | |
701 | if (IS_ERR(pt)) | |
5441f0cb MT |
702 | goto unwind_out; |
703 | ||
d7b2633d MT |
704 | gen8_initialize_pt(&ppgtt->base, pt); |
705 | pd->page_table[pde] = pt; | |
706 | set_bit(pde, new_pts); | |
7ad47cf2 BW |
707 | } |
708 | ||
bf2b4ed2 | 709 | return 0; |
7ad47cf2 BW |
710 | |
711 | unwind_out: | |
d7b2633d | 712 | for_each_set_bit(pde, new_pts, I915_PDES) |
e5815a2e | 713 | unmap_and_free_pt(pd->page_table[pde], dev); |
7ad47cf2 | 714 | |
d7b3de91 | 715 | return -ENOMEM; |
bf2b4ed2 BW |
716 | } |
717 | ||
d7b2633d MT |
718 | /** |
719 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
720 | * @ppgtt: Master ppgtt structure. | |
721 | * @pdp: Page directory pointer for this address range. | |
722 | * @start: Starting virtual address to begin allocations. | |
723 | * @length Size of the allocations. | |
724 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
725 | * caller to free on error. | |
726 | * | |
727 | * Allocate the required number of page directories starting at the pde index of | |
728 | * @start, and ending at the pde index @start + @length. This function will skip | |
729 | * over already allocated page directories within the range, and only allocate | |
730 | * new ones, setting the appropriate pointer within the pdp as well as the | |
731 | * correct position in the bitmap @new_pds. | |
732 | * | |
733 | * The function will only allocate the pages within the range for a give page | |
734 | * directory pointer. In other words, if @start + @length straddles a virtually | |
735 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
736 | * required by the caller, This is not currently possible, and the BUG in the | |
737 | * code will prevent it. | |
738 | * | |
739 | * Return: 0 if success; negative error code otherwise. | |
740 | */ | |
c488dbba MT |
741 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
742 | struct i915_page_directory_pointer *pdp, | |
69876bed | 743 | uint64_t start, |
d7b2633d MT |
744 | uint64_t length, |
745 | unsigned long *new_pds) | |
bf2b4ed2 | 746 | { |
e5815a2e | 747 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 748 | struct i915_page_directory *pd; |
69876bed MT |
749 | uint64_t temp; |
750 | uint32_t pdpe; | |
751 | ||
d7b2633d MT |
752 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
753 | ||
69876bed MT |
754 | /* FIXME: PPGTT container_of won't work for 64b */ |
755 | WARN_ON((start + length) > 0x800000000ULL); | |
756 | ||
d7b2633d MT |
757 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
758 | if (pd) | |
759 | continue; | |
33c8819f | 760 | |
d7b2633d MT |
761 | pd = alloc_pd_single(dev); |
762 | if (IS_ERR(pd)) | |
d7b3de91 | 763 | goto unwind_out; |
69876bed | 764 | |
d7b2633d MT |
765 | gen8_initialize_pd(&ppgtt->base, pd); |
766 | pdp->page_directory[pdpe] = pd; | |
767 | set_bit(pdpe, new_pds); | |
d7b3de91 BW |
768 | } |
769 | ||
bf2b4ed2 | 770 | return 0; |
d7b3de91 BW |
771 | |
772 | unwind_out: | |
d7b2633d | 773 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
e5815a2e | 774 | unmap_and_free_pd(pdp->page_directory[pdpe], dev); |
d7b3de91 BW |
775 | |
776 | return -ENOMEM; | |
bf2b4ed2 BW |
777 | } |
778 | ||
d7b2633d MT |
779 | static void |
780 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
781 | { | |
782 | int i; | |
783 | ||
784 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
785 | kfree(new_pts[i]); | |
786 | kfree(new_pts); | |
787 | kfree(new_pds); | |
788 | } | |
789 | ||
790 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
791 | * of these are based on the number of PDPEs in the system. | |
792 | */ | |
793 | static | |
794 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
795 | unsigned long ***new_pts) | |
796 | { | |
797 | int i; | |
798 | unsigned long *pds; | |
799 | unsigned long **pts; | |
800 | ||
801 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
802 | if (!pds) | |
803 | return -ENOMEM; | |
804 | ||
805 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
806 | if (!pts) { | |
807 | kfree(pds); | |
808 | return -ENOMEM; | |
809 | } | |
810 | ||
811 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
812 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
813 | sizeof(unsigned long), GFP_KERNEL); | |
814 | if (!pts[i]) | |
815 | goto err_out; | |
816 | } | |
817 | ||
818 | *new_pds = pds; | |
819 | *new_pts = pts; | |
820 | ||
821 | return 0; | |
822 | ||
823 | err_out: | |
824 | free_gen8_temp_bitmaps(pds, pts); | |
825 | return -ENOMEM; | |
826 | } | |
827 | ||
e5815a2e MT |
828 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
829 | uint64_t start, | |
830 | uint64_t length) | |
bf2b4ed2 | 831 | { |
e5815a2e MT |
832 | struct i915_hw_ppgtt *ppgtt = |
833 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 834 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 835 | struct i915_page_directory *pd; |
33c8819f MT |
836 | const uint64_t orig_start = start; |
837 | const uint64_t orig_length = length; | |
5441f0cb MT |
838 | uint64_t temp; |
839 | uint32_t pdpe; | |
bf2b4ed2 BW |
840 | int ret; |
841 | ||
d7b2633d MT |
842 | #ifndef CONFIG_64BIT |
843 | /* Disallow 64b address on 32b platforms. Nothing is wrong with doing | |
844 | * this in hardware, but a lot of the drm code is not prepared to handle | |
845 | * 64b offset on 32b platforms. | |
846 | * This will be addressed when 48b PPGTT is added */ | |
847 | if (start + length > 0x100000000ULL) | |
848 | return -E2BIG; | |
849 | #endif | |
850 | ||
851 | /* Wrap is never okay since we can only represent 48b, and we don't | |
852 | * actually use the other side of the canonical address space. | |
853 | */ | |
854 | if (WARN_ON(start + length < start)) | |
855 | return -ERANGE; | |
856 | ||
857 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
858 | if (ret) |
859 | return ret; | |
860 | ||
d7b2633d MT |
861 | /* Do the allocations first so we can easily bail out */ |
862 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
863 | new_page_dirs); | |
864 | if (ret) { | |
865 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
866 | return ret; | |
867 | } | |
868 | ||
869 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 870 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
871 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
872 | new_page_tables[pdpe]); | |
5441f0cb MT |
873 | if (ret) |
874 | goto err_out; | |
5441f0cb MT |
875 | } |
876 | ||
33c8819f MT |
877 | start = orig_start; |
878 | length = orig_length; | |
879 | ||
d7b2633d MT |
880 | /* Allocations have completed successfully, so set the bitmaps, and do |
881 | * the mappings. */ | |
33c8819f | 882 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d | 883 | gen8_pde_t *const page_directory = kmap_atomic(pd->page); |
33c8819f MT |
884 | struct i915_page_table *pt; |
885 | uint64_t pd_len = gen8_clamp_pd(start, length); | |
886 | uint64_t pd_start = start; | |
887 | uint32_t pde; | |
888 | ||
d7b2633d MT |
889 | /* Every pd should be allocated, we just did that above. */ |
890 | WARN_ON(!pd); | |
891 | ||
892 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
893 | /* Same reasoning as pd */ | |
894 | WARN_ON(!pt); | |
895 | WARN_ON(!pd_len); | |
896 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
897 | ||
898 | /* Set our used ptes within the page table */ | |
899 | bitmap_set(pt->used_ptes, | |
900 | gen8_pte_index(pd_start), | |
901 | gen8_pte_count(pd_start, pd_len)); | |
902 | ||
903 | /* Our pde is now pointing to the pagetable, pt */ | |
33c8819f | 904 | set_bit(pde, pd->used_pdes); |
d7b2633d MT |
905 | |
906 | /* Map the PDE to the page table */ | |
907 | __gen8_do_map_pt(page_directory + pde, pt, vm->dev); | |
908 | ||
909 | /* NB: We haven't yet mapped ptes to pages. At this | |
910 | * point we're still relying on insert_entries() */ | |
33c8819f | 911 | } |
d7b2633d MT |
912 | |
913 | if (!HAS_LLC(vm->dev)) | |
914 | drm_clflush_virt_range(page_directory, PAGE_SIZE); | |
915 | ||
916 | kunmap_atomic(page_directory); | |
917 | ||
33c8819f MT |
918 | set_bit(pdpe, ppgtt->pdp.used_pdpes); |
919 | } | |
920 | ||
d7b2633d | 921 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b3de91 | 922 | return 0; |
bf2b4ed2 | 923 | |
d7b3de91 | 924 | err_out: |
d7b2633d MT |
925 | while (pdpe--) { |
926 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
927 | unmap_and_free_pt(ppgtt->pdp.page_directory[pdpe]->page_table[temp], vm->dev); | |
928 | } | |
929 | ||
930 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
931 | unmap_and_free_pd(ppgtt->pdp.page_directory[pdpe], vm->dev); | |
932 | ||
933 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
bf2b4ed2 BW |
934 | return ret; |
935 | } | |
936 | ||
eb0b44ad | 937 | /* |
f3a964b9 BW |
938 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
939 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
940 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
941 | * space. | |
37aca44a | 942 | * |
f3a964b9 | 943 | */ |
5c5f6457 | 944 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 945 | { |
69876bed MT |
946 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
947 | if (IS_ERR(ppgtt->scratch_pt)) | |
948 | return PTR_ERR(ppgtt->scratch_pt); | |
949 | ||
e5815a2e | 950 | ppgtt->scratch_pd = alloc_pd_single(ppgtt->base.dev); |
7cb6d7ac MT |
951 | if (IS_ERR(ppgtt->scratch_pd)) |
952 | return PTR_ERR(ppgtt->scratch_pd); | |
953 | ||
69876bed | 954 | gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); |
7cb6d7ac | 955 | gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); |
69876bed | 956 | |
d7b2633d | 957 | ppgtt->base.start = 0; |
5c5f6457 | 958 | ppgtt->base.total = 1ULL << 32; |
d7b2633d | 959 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 960 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 961 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 962 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
963 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
964 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
965 | |
966 | ppgtt->switch_mm = gen8_mm_switch; | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
87d60b63 BW |
971 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
972 | { | |
87d60b63 | 973 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 974 | struct i915_page_table *unused; |
07749ef3 | 975 | gen6_pte_t scratch_pte; |
87d60b63 | 976 | uint32_t pd_entry; |
09942c65 MT |
977 | uint32_t pte, pde, temp; |
978 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 979 | |
24f3a8cf | 980 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 981 | |
09942c65 | 982 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 983 | u32 expected; |
07749ef3 | 984 | gen6_pte_t *pt_vaddr; |
06fda602 | 985 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; |
09942c65 | 986 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
987 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
988 | ||
989 | if (pd_entry != expected) | |
990 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
991 | pde, | |
992 | pd_entry, | |
993 | expected); | |
994 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
995 | ||
06fda602 | 996 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); |
07749ef3 | 997 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 998 | unsigned long va = |
07749ef3 | 999 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1000 | (pte * PAGE_SIZE); |
1001 | int i; | |
1002 | bool found = false; | |
1003 | for (i = 0; i < 4; i++) | |
1004 | if (pt_vaddr[pte + i] != scratch_pte) | |
1005 | found = true; | |
1006 | if (!found) | |
1007 | continue; | |
1008 | ||
1009 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1010 | for (i = 0; i < 4; i++) { | |
1011 | if (pt_vaddr[pte + i] != scratch_pte) | |
1012 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1013 | else | |
1014 | seq_puts(m, " SCRATCH "); | |
1015 | } | |
1016 | seq_puts(m, "\n"); | |
1017 | } | |
1018 | kunmap_atomic(pt_vaddr); | |
1019 | } | |
1020 | } | |
1021 | ||
678d96fb | 1022 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1023 | static void gen6_write_pde(struct i915_page_directory *pd, |
1024 | const int pde, struct i915_page_table *pt) | |
6197349b | 1025 | { |
678d96fb BW |
1026 | /* Caller needs to make sure the write completes if necessary */ |
1027 | struct i915_hw_ppgtt *ppgtt = | |
1028 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1029 | u32 pd_entry; | |
6197349b | 1030 | |
678d96fb BW |
1031 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); |
1032 | pd_entry |= GEN6_PDE_VALID; | |
6197349b | 1033 | |
678d96fb BW |
1034 | writel(pd_entry, ppgtt->pd_addr + pde); |
1035 | } | |
6197349b | 1036 | |
678d96fb BW |
1037 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1038 | * directories. */ | |
1039 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1040 | struct i915_page_directory *pd, |
678d96fb BW |
1041 | uint32_t start, uint32_t length) |
1042 | { | |
ec565b3c | 1043 | struct i915_page_table *pt; |
678d96fb BW |
1044 | uint32_t pde, temp; |
1045 | ||
1046 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1047 | gen6_write_pde(pd, pde, pt); | |
1048 | ||
1049 | /* Make sure write is complete before other code can use this page | |
1050 | * table. Also require for WC mapped PTEs */ | |
1051 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1052 | } |
1053 | ||
b4a74e3a | 1054 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1055 | { |
7324cc04 | 1056 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 1057 | |
7324cc04 | 1058 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
1059 | } |
1060 | ||
90252e5c | 1061 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1062 | struct intel_engine_cs *ring) |
90252e5c | 1063 | { |
90252e5c BW |
1064 | int ret; |
1065 | ||
90252e5c BW |
1066 | /* NB: TLBs must be flushed and invalidated before a switch */ |
1067 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1068 | if (ret) | |
1069 | return ret; | |
1070 | ||
1071 | ret = intel_ring_begin(ring, 6); | |
1072 | if (ret) | |
1073 | return ret; | |
1074 | ||
1075 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1076 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1077 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1078 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1079 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1080 | intel_ring_emit(ring, MI_NOOP); | |
1081 | intel_ring_advance(ring); | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
71ba2d64 YZ |
1086 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
1087 | struct intel_engine_cs *ring) | |
1088 | { | |
1089 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
1090 | ||
1091 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1092 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
48a10389 | 1096 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1097 | struct intel_engine_cs *ring) |
48a10389 | 1098 | { |
48a10389 BW |
1099 | int ret; |
1100 | ||
48a10389 BW |
1101 | /* NB: TLBs must be flushed and invalidated before a switch */ |
1102 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1103 | if (ret) | |
1104 | return ret; | |
1105 | ||
1106 | ret = intel_ring_begin(ring, 6); | |
1107 | if (ret) | |
1108 | return ret; | |
1109 | ||
1110 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1111 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1112 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1113 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1114 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1115 | intel_ring_emit(ring, MI_NOOP); | |
1116 | intel_ring_advance(ring); | |
1117 | ||
90252e5c BW |
1118 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1119 | if (ring->id != RCS) { | |
1120 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
1121 | if (ret) | |
1122 | return ret; | |
1123 | } | |
1124 | ||
48a10389 BW |
1125 | return 0; |
1126 | } | |
1127 | ||
eeb9488e | 1128 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 1129 | struct intel_engine_cs *ring) |
eeb9488e BW |
1130 | { |
1131 | struct drm_device *dev = ppgtt->base.dev; | |
1132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1133 | ||
48a10389 | 1134 | |
eeb9488e BW |
1135 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1136 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1137 | ||
1138 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
82460d97 | 1143 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1144 | { |
eeb9488e | 1145 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1146 | struct intel_engine_cs *ring; |
82460d97 | 1147 | int j; |
3e302542 | 1148 | |
eeb9488e BW |
1149 | for_each_ring(ring, dev_priv, j) { |
1150 | I915_WRITE(RING_MODE_GEN7(ring), | |
1151 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1152 | } |
eeb9488e | 1153 | } |
6197349b | 1154 | |
82460d97 | 1155 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1156 | { |
50227e1c | 1157 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1158 | struct intel_engine_cs *ring; |
b4a74e3a | 1159 | uint32_t ecochk, ecobits; |
3e302542 | 1160 | int i; |
6197349b | 1161 | |
b4a74e3a BW |
1162 | ecobits = I915_READ(GAC_ECO_BITS); |
1163 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1164 | |
b4a74e3a BW |
1165 | ecochk = I915_READ(GAM_ECOCHK); |
1166 | if (IS_HASWELL(dev)) { | |
1167 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1168 | } else { | |
1169 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1170 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1171 | } | |
1172 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1173 | |
b4a74e3a | 1174 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1175 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1176 | I915_WRITE(RING_MODE_GEN7(ring), |
1177 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1178 | } |
b4a74e3a | 1179 | } |
6197349b | 1180 | |
82460d97 | 1181 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1182 | { |
50227e1c | 1183 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1184 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1185 | |
b4a74e3a BW |
1186 | ecobits = I915_READ(GAC_ECO_BITS); |
1187 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1188 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1189 | |
b4a74e3a BW |
1190 | gab_ctl = I915_READ(GAB_CTL); |
1191 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1192 | ||
1193 | ecochk = I915_READ(GAM_ECOCHK); | |
1194 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1195 | ||
1196 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1197 | } |
1198 | ||
1d2a314c | 1199 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1200 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1201 | uint64_t start, |
1202 | uint64_t length, | |
828c7908 | 1203 | bool use_scratch) |
1d2a314c | 1204 | { |
853ba5d2 BW |
1205 | struct i915_hw_ppgtt *ppgtt = |
1206 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1207 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1208 | unsigned first_entry = start >> PAGE_SHIFT; |
1209 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1210 | unsigned act_pt = first_entry / GEN6_PTES; |
1211 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1212 | unsigned last_pte, i; |
1d2a314c | 1213 | |
24f3a8cf | 1214 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1215 | |
7bddb01f DV |
1216 | while (num_entries) { |
1217 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1218 | if (last_pte > GEN6_PTES) |
1219 | last_pte = GEN6_PTES; | |
7bddb01f | 1220 | |
06fda602 | 1221 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
1d2a314c | 1222 | |
7bddb01f DV |
1223 | for (i = first_pte; i < last_pte; i++) |
1224 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
1225 | |
1226 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 1227 | |
7bddb01f DV |
1228 | num_entries -= last_pte - first_pte; |
1229 | first_pte = 0; | |
a15326a5 | 1230 | act_pt++; |
7bddb01f | 1231 | } |
1d2a314c DV |
1232 | } |
1233 | ||
853ba5d2 | 1234 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1235 | struct sg_table *pages, |
782f1495 | 1236 | uint64_t start, |
24f3a8cf | 1237 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1238 | { |
853ba5d2 BW |
1239 | struct i915_hw_ppgtt *ppgtt = |
1240 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1241 | gen6_pte_t *pt_vaddr; |
782f1495 | 1242 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1243 | unsigned act_pt = first_entry / GEN6_PTES; |
1244 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1245 | struct sg_page_iter sg_iter; |
1246 | ||
cc79714f | 1247 | pt_vaddr = NULL; |
6e995e23 | 1248 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1249 | if (pt_vaddr == NULL) |
06fda602 | 1250 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); |
6e995e23 | 1251 | |
cc79714f CW |
1252 | pt_vaddr[act_pte] = |
1253 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1254 | cache_level, true, flags); |
1255 | ||
07749ef3 | 1256 | if (++act_pte == GEN6_PTES) { |
6e995e23 | 1257 | kunmap_atomic(pt_vaddr); |
cc79714f | 1258 | pt_vaddr = NULL; |
a15326a5 | 1259 | act_pt++; |
6e995e23 | 1260 | act_pte = 0; |
def886c3 | 1261 | } |
def886c3 | 1262 | } |
cc79714f CW |
1263 | if (pt_vaddr) |
1264 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1265 | } |
1266 | ||
563222a7 BW |
1267 | /* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we |
1268 | * are switching between contexts with the same LRCA, we also must do a force | |
1269 | * restore. | |
1270 | */ | |
1271 | static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1272 | { | |
1273 | /* If current vm != vm, */ | |
1274 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1275 | } | |
1276 | ||
4933d519 | 1277 | static void gen6_initialize_pt(struct i915_address_space *vm, |
ec565b3c | 1278 | struct i915_page_table *pt) |
4933d519 MT |
1279 | { |
1280 | gen6_pte_t *pt_vaddr, scratch_pte; | |
1281 | int i; | |
1282 | ||
1283 | WARN_ON(vm->scratch.addr == 0); | |
1284 | ||
1285 | scratch_pte = vm->pte_encode(vm->scratch.addr, | |
1286 | I915_CACHE_LLC, true, 0); | |
1287 | ||
1288 | pt_vaddr = kmap_atomic(pt->page); | |
1289 | ||
1290 | for (i = 0; i < GEN6_PTES; i++) | |
1291 | pt_vaddr[i] = scratch_pte; | |
1292 | ||
1293 | kunmap_atomic(pt_vaddr); | |
1294 | } | |
1295 | ||
678d96fb BW |
1296 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
1297 | uint64_t start, uint64_t length) | |
1298 | { | |
4933d519 MT |
1299 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1300 | struct drm_device *dev = vm->dev; | |
1301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1302 | struct i915_hw_ppgtt *ppgtt = |
1303 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1304 | struct i915_page_table *pt; |
4933d519 | 1305 | const uint32_t start_save = start, length_save = length; |
678d96fb | 1306 | uint32_t pde, temp; |
4933d519 MT |
1307 | int ret; |
1308 | ||
1309 | WARN_ON(upper_32_bits(start)); | |
1310 | ||
1311 | bitmap_zero(new_page_tables, I915_PDES); | |
1312 | ||
1313 | /* The allocation is done in two stages so that we can bail out with | |
1314 | * minimal amount of pain. The first stage finds new page tables that | |
1315 | * need allocation. The second stage marks use ptes within the page | |
1316 | * tables. | |
1317 | */ | |
1318 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1319 | if (pt != ppgtt->scratch_pt) { | |
1320 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1321 | continue; | |
1322 | } | |
1323 | ||
1324 | /* We've already allocated a page table */ | |
1325 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1326 | ||
1327 | pt = alloc_pt_single(dev); | |
1328 | if (IS_ERR(pt)) { | |
1329 | ret = PTR_ERR(pt); | |
1330 | goto unwind_out; | |
1331 | } | |
1332 | ||
1333 | gen6_initialize_pt(vm, pt); | |
1334 | ||
1335 | ppgtt->pd.page_table[pde] = pt; | |
1336 | set_bit(pde, new_page_tables); | |
72744cb1 | 1337 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1338 | } |
1339 | ||
1340 | start = start_save; | |
1341 | length = length_save; | |
678d96fb BW |
1342 | |
1343 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1344 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1345 | ||
1346 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1347 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1348 | gen6_pte_count(start, length)); | |
1349 | ||
4933d519 MT |
1350 | if (test_and_clear_bit(pde, new_page_tables)) |
1351 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1352 | ||
72744cb1 MT |
1353 | trace_i915_page_table_entry_map(vm, pde, pt, |
1354 | gen6_pte_index(start), | |
1355 | gen6_pte_count(start, length), | |
1356 | GEN6_PTES); | |
4933d519 | 1357 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1358 | GEN6_PTES); |
1359 | } | |
1360 | ||
4933d519 MT |
1361 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1362 | ||
1363 | /* Make sure write is complete before other code can use this page | |
1364 | * table. Also require for WC mapped PTEs */ | |
1365 | readl(dev_priv->gtt.gsm); | |
1366 | ||
563222a7 | 1367 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1368 | return 0; |
4933d519 MT |
1369 | |
1370 | unwind_out: | |
1371 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1372 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 MT |
1373 | |
1374 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
1375 | unmap_and_free_pt(pt, vm->dev); | |
1376 | } | |
1377 | ||
1378 | mark_tlbs_dirty(ppgtt); | |
1379 | return ret; | |
678d96fb BW |
1380 | } |
1381 | ||
061dd493 | 1382 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1383 | { |
061dd493 DV |
1384 | struct i915_hw_ppgtt *ppgtt = |
1385 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1386 | struct i915_page_table *pt; |
1387 | uint32_t pde; | |
4933d519 | 1388 | |
061dd493 DV |
1389 | |
1390 | drm_mm_remove_node(&ppgtt->node); | |
1391 | ||
09942c65 | 1392 | gen6_for_all_pdes(pt, ppgtt, pde) { |
4933d519 | 1393 | if (pt != ppgtt->scratch_pt) |
09942c65 | 1394 | unmap_and_free_pt(pt, ppgtt->base.dev); |
4933d519 | 1395 | } |
06fda602 | 1396 | |
4933d519 | 1397 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
e5815a2e | 1398 | unmap_and_free_pd(&ppgtt->pd, ppgtt->base.dev); |
3440d265 DV |
1399 | } |
1400 | ||
b146520f | 1401 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1402 | { |
853ba5d2 | 1403 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1404 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1405 | bool retried = false; |
b146520f | 1406 | int ret; |
1d2a314c | 1407 | |
c8d4c0d6 BW |
1408 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1409 | * allocator works in address space sizes, so it's multiplied by page | |
1410 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1411 | */ | |
1412 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 MT |
1413 | ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); |
1414 | if (IS_ERR(ppgtt->scratch_pt)) | |
1415 | return PTR_ERR(ppgtt->scratch_pt); | |
1416 | ||
1417 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1418 | ||
e3cc1995 | 1419 | alloc: |
c8d4c0d6 BW |
1420 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1421 | &ppgtt->node, GEN6_PD_SIZE, | |
1422 | GEN6_PD_ALIGN, 0, | |
1423 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1424 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1425 | if (ret == -ENOSPC && !retried) { |
1426 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1427 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1428 | I915_CACHE_NONE, |
1429 | 0, dev_priv->gtt.base.total, | |
1430 | 0); | |
e3cc1995 | 1431 | if (ret) |
678d96fb | 1432 | goto err_out; |
e3cc1995 BW |
1433 | |
1434 | retried = true; | |
1435 | goto alloc; | |
1436 | } | |
c8d4c0d6 | 1437 | |
c8c26622 | 1438 | if (ret) |
678d96fb BW |
1439 | goto err_out; |
1440 | ||
c8c26622 | 1441 | |
c8d4c0d6 BW |
1442 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1443 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1444 | |
c8c26622 | 1445 | return 0; |
678d96fb BW |
1446 | |
1447 | err_out: | |
4933d519 | 1448 | unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); |
678d96fb | 1449 | return ret; |
b146520f BW |
1450 | } |
1451 | ||
b146520f BW |
1452 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1453 | { | |
2f2cf682 | 1454 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1455 | } |
06dc68d6 | 1456 | |
4933d519 MT |
1457 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1458 | uint64_t start, uint64_t length) | |
1459 | { | |
ec565b3c | 1460 | struct i915_page_table *unused; |
4933d519 | 1461 | uint32_t pde, temp; |
1d2a314c | 1462 | |
4933d519 MT |
1463 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1464 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1465 | } |
1466 | ||
5c5f6457 | 1467 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1468 | { |
1469 | struct drm_device *dev = ppgtt->base.dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1471 | int ret; | |
1472 | ||
1473 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1474 | if (IS_GEN6(dev)) { | |
b146520f BW |
1475 | ppgtt->switch_mm = gen6_mm_switch; |
1476 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1477 | ppgtt->switch_mm = hsw_mm_switch; |
1478 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1479 | ppgtt->switch_mm = gen7_mm_switch; |
1480 | } else | |
1481 | BUG(); | |
1482 | ||
71ba2d64 YZ |
1483 | if (intel_vgpu_active(dev)) |
1484 | ppgtt->switch_mm = vgpu_mm_switch; | |
1485 | ||
b146520f BW |
1486 | ret = gen6_ppgtt_alloc(ppgtt); |
1487 | if (ret) | |
1488 | return ret; | |
1489 | ||
5c5f6457 | 1490 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1491 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1492 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1493 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1494 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1495 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1496 | ppgtt->base.start = 0; |
09942c65 | 1497 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1498 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1499 | |
7324cc04 | 1500 | ppgtt->pd.pd_offset = |
07749ef3 | 1501 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1502 | |
678d96fb BW |
1503 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
1504 | ppgtt->pd.pd_offset / sizeof(gen6_pte_t); | |
1505 | ||
5c5f6457 | 1506 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1507 | |
678d96fb BW |
1508 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1509 | ||
440fd528 | 1510 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1511 | ppgtt->node.size >> 20, |
1512 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1513 | |
fa76da34 | 1514 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
7324cc04 | 1515 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1516 | |
b146520f | 1517 | return 0; |
3440d265 DV |
1518 | } |
1519 | ||
5c5f6457 | 1520 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1521 | { |
1522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1523 | |
853ba5d2 | 1524 | ppgtt->base.dev = dev; |
8407bb91 | 1525 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1526 | |
3ed124b2 | 1527 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1528 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1529 | else |
d7b2633d | 1530 | return gen8_ppgtt_init(ppgtt); |
fa76da34 DV |
1531 | } |
1532 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1533 | { | |
1534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1535 | int ret = 0; | |
3ed124b2 | 1536 | |
5c5f6457 | 1537 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1538 | if (ret == 0) { |
c7c48dfd | 1539 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1540 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1541 | ppgtt->base.total); | |
7e0d96bc | 1542 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1543 | } |
1d2a314c DV |
1544 | |
1545 | return ret; | |
1546 | } | |
1547 | ||
82460d97 DV |
1548 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1549 | { | |
1550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1551 | struct intel_engine_cs *ring; | |
1552 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1553 | int i, ret = 0; | |
1554 | ||
671b5013 TD |
1555 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1556 | * and the PDPs are contained within the context itself. We don't | |
1557 | * need to do anything here. */ | |
1558 | if (i915.enable_execlists) | |
1559 | return 0; | |
1560 | ||
82460d97 DV |
1561 | if (!USES_PPGTT(dev)) |
1562 | return 0; | |
1563 | ||
1564 | if (IS_GEN6(dev)) | |
1565 | gen6_ppgtt_enable(dev); | |
1566 | else if (IS_GEN7(dev)) | |
1567 | gen7_ppgtt_enable(dev); | |
1568 | else if (INTEL_INFO(dev)->gen >= 8) | |
1569 | gen8_ppgtt_enable(dev); | |
1570 | else | |
5f77eeb0 | 1571 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1572 | |
1573 | if (ppgtt) { | |
1574 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1575 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1576 | if (ret != 0) |
1577 | return ret; | |
7e0d96bc | 1578 | } |
93bd8649 | 1579 | } |
1d2a314c DV |
1580 | |
1581 | return ret; | |
1582 | } | |
4d884705 DV |
1583 | struct i915_hw_ppgtt * |
1584 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1585 | { | |
1586 | struct i915_hw_ppgtt *ppgtt; | |
1587 | int ret; | |
1588 | ||
1589 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1590 | if (!ppgtt) | |
1591 | return ERR_PTR(-ENOMEM); | |
1592 | ||
1593 | ret = i915_ppgtt_init(dev, ppgtt); | |
1594 | if (ret) { | |
1595 | kfree(ppgtt); | |
1596 | return ERR_PTR(ret); | |
1597 | } | |
1598 | ||
1599 | ppgtt->file_priv = fpriv; | |
1600 | ||
198c974d DCS |
1601 | trace_i915_ppgtt_create(&ppgtt->base); |
1602 | ||
4d884705 DV |
1603 | return ppgtt; |
1604 | } | |
1605 | ||
ee960be7 DV |
1606 | void i915_ppgtt_release(struct kref *kref) |
1607 | { | |
1608 | struct i915_hw_ppgtt *ppgtt = | |
1609 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1610 | ||
198c974d DCS |
1611 | trace_i915_ppgtt_release(&ppgtt->base); |
1612 | ||
ee960be7 DV |
1613 | /* vmas should already be unbound */ |
1614 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1615 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1616 | ||
19dd120c DV |
1617 | list_del(&ppgtt->base.global_link); |
1618 | drm_mm_takedown(&ppgtt->base.mm); | |
1619 | ||
ee960be7 DV |
1620 | ppgtt->base.cleanup(&ppgtt->base); |
1621 | kfree(ppgtt); | |
1622 | } | |
1d2a314c | 1623 | |
a81cc00c BW |
1624 | extern int intel_iommu_gfx_mapped; |
1625 | /* Certain Gen5 chipsets require require idling the GPU before | |
1626 | * unmapping anything from the GTT when VT-d is enabled. | |
1627 | */ | |
1628 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1629 | { | |
1630 | #ifdef CONFIG_INTEL_IOMMU | |
1631 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1632 | * was loaded first. | |
1633 | */ | |
1634 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1635 | return true; | |
1636 | #endif | |
1637 | return false; | |
1638 | } | |
1639 | ||
5c042287 BW |
1640 | static bool do_idling(struct drm_i915_private *dev_priv) |
1641 | { | |
1642 | bool ret = dev_priv->mm.interruptible; | |
1643 | ||
a81cc00c | 1644 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1645 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1646 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1647 | DRM_ERROR("Couldn't idle GPU\n"); |
1648 | /* Wait a bit, in hopes it avoids the hang */ | |
1649 | udelay(10); | |
1650 | } | |
1651 | } | |
1652 | ||
1653 | return ret; | |
1654 | } | |
1655 | ||
1656 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1657 | { | |
a81cc00c | 1658 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1659 | dev_priv->mm.interruptible = interruptible; |
1660 | } | |
1661 | ||
828c7908 BW |
1662 | void i915_check_and_clear_faults(struct drm_device *dev) |
1663 | { | |
1664 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1665 | struct intel_engine_cs *ring; |
828c7908 BW |
1666 | int i; |
1667 | ||
1668 | if (INTEL_INFO(dev)->gen < 6) | |
1669 | return; | |
1670 | ||
1671 | for_each_ring(ring, dev_priv, i) { | |
1672 | u32 fault_reg; | |
1673 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1674 | if (fault_reg & RING_FAULT_VALID) { | |
1675 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1676 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1677 | "\tAddress space: %s\n" |
1678 | "\tSource ID: %d\n" | |
1679 | "\tType: %d\n", | |
1680 | fault_reg & PAGE_MASK, | |
1681 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1682 | RING_FAULT_SRCID(fault_reg), | |
1683 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1684 | I915_WRITE(RING_FAULT_REG(ring), | |
1685 | fault_reg & ~RING_FAULT_VALID); | |
1686 | } | |
1687 | } | |
1688 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1689 | } | |
1690 | ||
91e56499 CW |
1691 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1692 | { | |
1693 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1694 | intel_gtt_chipset_flush(); | |
1695 | } else { | |
1696 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1697 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1698 | } | |
1699 | } | |
1700 | ||
828c7908 BW |
1701 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1702 | { | |
1703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1704 | ||
1705 | /* Don't bother messing with faults pre GEN6 as we have little | |
1706 | * documentation supporting that it's a good idea. | |
1707 | */ | |
1708 | if (INTEL_INFO(dev)->gen < 6) | |
1709 | return; | |
1710 | ||
1711 | i915_check_and_clear_faults(dev); | |
1712 | ||
1713 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1714 | dev_priv->gtt.base.start, |
1715 | dev_priv->gtt.base.total, | |
e568af1c | 1716 | true); |
91e56499 CW |
1717 | |
1718 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1719 | } |
1720 | ||
74163907 | 1721 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1722 | { |
9da3da66 | 1723 | if (obj->has_dma_mapping) |
74163907 | 1724 | return 0; |
9da3da66 CW |
1725 | |
1726 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1727 | obj->pages->sgl, obj->pages->nents, | |
1728 | PCI_DMA_BIDIRECTIONAL)) | |
1729 | return -ENOSPC; | |
1730 | ||
1731 | return 0; | |
7c2e6fdf DV |
1732 | } |
1733 | ||
07749ef3 | 1734 | static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1735 | { |
1736 | #ifdef writeq | |
1737 | writeq(pte, addr); | |
1738 | #else | |
1739 | iowrite32((u32)pte, addr); | |
1740 | iowrite32(pte >> 32, addr + 4); | |
1741 | #endif | |
1742 | } | |
1743 | ||
1744 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1745 | struct sg_table *st, | |
782f1495 | 1746 | uint64_t start, |
24f3a8cf | 1747 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1748 | { |
1749 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1750 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1751 | gen8_pte_t __iomem *gtt_entries = |
1752 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1753 | int i = 0; |
1754 | struct sg_page_iter sg_iter; | |
57007df7 | 1755 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1756 | |
1757 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1758 | addr = sg_dma_address(sg_iter.sg) + | |
1759 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1760 | gen8_set_pte(>t_entries[i], | |
1761 | gen8_pte_encode(addr, level, true)); | |
1762 | i++; | |
1763 | } | |
1764 | ||
1765 | /* | |
1766 | * XXX: This serves as a posting read to make sure that the PTE has | |
1767 | * actually been updated. There is some concern that even though | |
1768 | * registers and PTEs are within the same BAR that they are potentially | |
1769 | * of NUMA access patterns. Therefore, even with the way we assume | |
1770 | * hardware should work, we must keep this posting read for paranoia. | |
1771 | */ | |
1772 | if (i != 0) | |
1773 | WARN_ON(readq(>t_entries[i-1]) | |
1774 | != gen8_pte_encode(addr, level, true)); | |
1775 | ||
94ec8f61 BW |
1776 | /* This next bit makes the above posting read even more important. We |
1777 | * want to flush the TLBs only after we're certain all the PTE updates | |
1778 | * have finished. | |
1779 | */ | |
1780 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1781 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1782 | } |
1783 | ||
e76e9aeb BW |
1784 | /* |
1785 | * Binds an object into the global gtt with the specified cache level. The object | |
1786 | * will be accessible to the GPU via commands whose operands reference offsets | |
1787 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1788 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1789 | */ | |
853ba5d2 | 1790 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1791 | struct sg_table *st, |
782f1495 | 1792 | uint64_t start, |
24f3a8cf | 1793 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1794 | { |
853ba5d2 | 1795 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1796 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1797 | gen6_pte_t __iomem *gtt_entries = |
1798 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1799 | int i = 0; |
1800 | struct sg_page_iter sg_iter; | |
57007df7 | 1801 | dma_addr_t addr = 0; |
e76e9aeb | 1802 | |
6e995e23 | 1803 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1804 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1805 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1806 | i++; |
e76e9aeb BW |
1807 | } |
1808 | ||
e76e9aeb BW |
1809 | /* XXX: This serves as a posting read to make sure that the PTE has |
1810 | * actually been updated. There is some concern that even though | |
1811 | * registers and PTEs are within the same BAR that they are potentially | |
1812 | * of NUMA access patterns. Therefore, even with the way we assume | |
1813 | * hardware should work, we must keep this posting read for paranoia. | |
1814 | */ | |
57007df7 PM |
1815 | if (i != 0) { |
1816 | unsigned long gtt = readl(>t_entries[i-1]); | |
1817 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1818 | } | |
0f9b91c7 BW |
1819 | |
1820 | /* This next bit makes the above posting read even more important. We | |
1821 | * want to flush the TLBs only after we're certain all the PTE updates | |
1822 | * have finished. | |
1823 | */ | |
1824 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1825 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1826 | } |
1827 | ||
94ec8f61 | 1828 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1829 | uint64_t start, |
1830 | uint64_t length, | |
94ec8f61 BW |
1831 | bool use_scratch) |
1832 | { | |
1833 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1834 | unsigned first_entry = start >> PAGE_SHIFT; |
1835 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1836 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1837 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1838 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1839 | int i; | |
1840 | ||
1841 | if (WARN(num_entries > max_entries, | |
1842 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1843 | first_entry, num_entries, max_entries)) | |
1844 | num_entries = max_entries; | |
1845 | ||
1846 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1847 | I915_CACHE_LLC, | |
1848 | use_scratch); | |
1849 | for (i = 0; i < num_entries; i++) | |
1850 | gen8_set_pte(>t_base[i], scratch_pte); | |
1851 | readl(gtt_base); | |
1852 | } | |
1853 | ||
853ba5d2 | 1854 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1855 | uint64_t start, |
1856 | uint64_t length, | |
828c7908 | 1857 | bool use_scratch) |
7faf1ab2 | 1858 | { |
853ba5d2 | 1859 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1860 | unsigned first_entry = start >> PAGE_SHIFT; |
1861 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1862 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1863 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1864 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1865 | int i; |
1866 | ||
1867 | if (WARN(num_entries > max_entries, | |
1868 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1869 | first_entry, num_entries, max_entries)) | |
1870 | num_entries = max_entries; | |
1871 | ||
24f3a8cf | 1872 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1873 | |
7faf1ab2 DV |
1874 | for (i = 0; i < num_entries; i++) |
1875 | iowrite32(scratch_pte, >t_base[i]); | |
1876 | readl(gtt_base); | |
1877 | } | |
1878 | ||
6f65e29a BW |
1879 | |
1880 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1881 | enum i915_cache_level cache_level, | |
1882 | u32 unused) | |
7faf1ab2 | 1883 | { |
6f65e29a | 1884 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1885 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1886 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1887 | ||
6f65e29a | 1888 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1889 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
0875546c DV |
1890 | |
1891 | vma->bound |= GLOBAL_BIND; | |
7faf1ab2 DV |
1892 | } |
1893 | ||
853ba5d2 | 1894 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1895 | uint64_t start, |
1896 | uint64_t length, | |
828c7908 | 1897 | bool unused) |
7faf1ab2 | 1898 | { |
782f1495 BW |
1899 | unsigned first_entry = start >> PAGE_SHIFT; |
1900 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1901 | intel_gtt_clear_range(first_entry, num_entries); |
1902 | } | |
1903 | ||
6f65e29a BW |
1904 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1905 | { | |
1906 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1907 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1908 | |
6f65e29a | 1909 | BUG_ON(!i915_is_ggtt(vma->vm)); |
6f65e29a BW |
1910 | intel_gtt_clear_range(first, size); |
1911 | } | |
7faf1ab2 | 1912 | |
6f65e29a BW |
1913 | static void ggtt_bind_vma(struct i915_vma *vma, |
1914 | enum i915_cache_level cache_level, | |
1915 | u32 flags) | |
d5bd1449 | 1916 | { |
6f65e29a | 1917 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1918 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1919 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1920 | struct sg_table *pages = obj->pages; |
f329f5f6 | 1921 | u32 pte_flags = 0; |
7faf1ab2 | 1922 | |
24f3a8cf AG |
1923 | /* Currently applicable only to VLV */ |
1924 | if (obj->gt_ro) | |
f329f5f6 | 1925 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 1926 | |
ec7adb6e JL |
1927 | if (i915_is_ggtt(vma->vm)) |
1928 | pages = vma->ggtt_view.pages; | |
1929 | ||
6f65e29a | 1930 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
1931 | vma->vm->insert_entries(vma->vm, pages, |
1932 | vma->node.start, | |
1933 | cache_level, pte_flags); | |
1934 | ||
1935 | vma->bound |= GLOBAL_BIND; | |
6f65e29a | 1936 | } |
d5bd1449 | 1937 | |
0875546c | 1938 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 1939 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 1940 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1941 | vma->node.start, |
f329f5f6 | 1942 | cache_level, pte_flags); |
6f65e29a | 1943 | } |
d5bd1449 CW |
1944 | } |
1945 | ||
6f65e29a | 1946 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1947 | { |
6f65e29a | 1948 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1949 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1950 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1951 | |
aff43766 | 1952 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1953 | vma->vm->clear_range(vma->vm, |
1954 | vma->node.start, | |
1955 | obj->base.size, | |
6f65e29a | 1956 | true); |
6f65e29a | 1957 | } |
74898d7e | 1958 | |
0875546c | 1959 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1960 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1961 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1962 | vma->node.start, |
1963 | obj->base.size, | |
6f65e29a | 1964 | true); |
6f65e29a | 1965 | } |
74163907 DV |
1966 | } |
1967 | ||
1968 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1969 | { |
5c042287 BW |
1970 | struct drm_device *dev = obj->base.dev; |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1972 | bool interruptible; | |
1973 | ||
1974 | interruptible = do_idling(dev_priv); | |
1975 | ||
9da3da66 CW |
1976 | if (!obj->has_dma_mapping) |
1977 | dma_unmap_sg(&dev->pdev->dev, | |
1978 | obj->pages->sgl, obj->pages->nents, | |
1979 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1980 | |
1981 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1982 | } |
644ec02b | 1983 | |
42d6ab48 CW |
1984 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1985 | unsigned long color, | |
440fd528 TR |
1986 | u64 *start, |
1987 | u64 *end) | |
42d6ab48 CW |
1988 | { |
1989 | if (node->color != color) | |
1990 | *start += 4096; | |
1991 | ||
1992 | if (!list_empty(&node->node_list)) { | |
1993 | node = list_entry(node->node_list.next, | |
1994 | struct drm_mm_node, | |
1995 | node_list); | |
1996 | if (node->allocated && node->color != color) | |
1997 | *end -= 4096; | |
1998 | } | |
1999 | } | |
fbe5d36e | 2000 | |
f548c0e9 DV |
2001 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
2002 | unsigned long start, | |
2003 | unsigned long mappable_end, | |
2004 | unsigned long end) | |
644ec02b | 2005 | { |
e78891ca BW |
2006 | /* Let GEM Manage all of the aperture. |
2007 | * | |
2008 | * However, leave one page at the end still bound to the scratch page. | |
2009 | * There are a number of places where the hardware apparently prefetches | |
2010 | * past the end of the object, and we've seen multiple hangs with the | |
2011 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2012 | * aperture. One page should be enough to keep any prefetching inside | |
2013 | * of the aperture. | |
2014 | */ | |
40d74980 BW |
2015 | struct drm_i915_private *dev_priv = dev->dev_private; |
2016 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2017 | struct drm_mm_node *entry; |
2018 | struct drm_i915_gem_object *obj; | |
2019 | unsigned long hole_start, hole_end; | |
fa76da34 | 2020 | int ret; |
644ec02b | 2021 | |
35451cb6 BW |
2022 | BUG_ON(mappable_end > end); |
2023 | ||
ed2f3452 | 2024 | /* Subtract the guard page ... */ |
40d74980 | 2025 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2026 | |
2027 | dev_priv->gtt.base.start = start; | |
2028 | dev_priv->gtt.base.total = end - start; | |
2029 | ||
2030 | if (intel_vgpu_active(dev)) { | |
2031 | ret = intel_vgt_balloon(dev); | |
2032 | if (ret) | |
2033 | return ret; | |
2034 | } | |
2035 | ||
42d6ab48 | 2036 | if (!HAS_LLC(dev)) |
93bd8649 | 2037 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2038 | |
ed2f3452 | 2039 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2040 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2041 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2042 | |
edd41a87 | 2043 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2044 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2045 | ||
2046 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2047 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2048 | if (ret) { |
2049 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2050 | return ret; | |
2051 | } | |
aff43766 | 2052 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2053 | } |
2054 | ||
ed2f3452 | 2055 | /* Clear any non-preallocated blocks */ |
40d74980 | 2056 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2057 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2058 | hole_start, hole_end); | |
782f1495 BW |
2059 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2060 | hole_end - hole_start, true); | |
ed2f3452 CW |
2061 | } |
2062 | ||
2063 | /* And finally clear the reserved guard page */ | |
782f1495 | 2064 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2065 | |
fa76da34 DV |
2066 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2067 | struct i915_hw_ppgtt *ppgtt; | |
2068 | ||
2069 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2070 | if (!ppgtt) | |
2071 | return -ENOMEM; | |
2072 | ||
5c5f6457 DV |
2073 | ret = __hw_ppgtt_init(dev, ppgtt); |
2074 | if (ret) { | |
2075 | ppgtt->base.cleanup(&ppgtt->base); | |
2076 | kfree(ppgtt); | |
2077 | return ret; | |
2078 | } | |
2079 | ||
2080 | if (ppgtt->base.allocate_va_range) | |
2081 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2082 | ppgtt->base.total); | |
4933d519 | 2083 | if (ret) { |
061dd493 | 2084 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2085 | kfree(ppgtt); |
fa76da34 | 2086 | return ret; |
4933d519 | 2087 | } |
fa76da34 | 2088 | |
5c5f6457 DV |
2089 | ppgtt->base.clear_range(&ppgtt->base, |
2090 | ppgtt->base.start, | |
2091 | ppgtt->base.total, | |
2092 | true); | |
2093 | ||
fa76da34 DV |
2094 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2095 | } | |
2096 | ||
6c5566a8 | 2097 | return 0; |
e76e9aeb BW |
2098 | } |
2099 | ||
d7e5008f BW |
2100 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2101 | { | |
2102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2103 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 2104 | |
853ba5d2 | 2105 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2106 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2107 | |
e78891ca | 2108 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2109 | } |
2110 | ||
90d0a0e8 DV |
2111 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2112 | { | |
2113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2114 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2115 | ||
70e32544 DV |
2116 | if (dev_priv->mm.aliasing_ppgtt) { |
2117 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2118 | ||
2119 | ppgtt->base.cleanup(&ppgtt->base); | |
2120 | } | |
2121 | ||
90d0a0e8 | 2122 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2123 | if (intel_vgpu_active(dev)) |
2124 | intel_vgt_deballoon(); | |
2125 | ||
90d0a0e8 DV |
2126 | drm_mm_takedown(&vm->mm); |
2127 | list_del(&vm->global_link); | |
2128 | } | |
2129 | ||
2130 | vm->cleanup(vm); | |
2131 | } | |
70e32544 | 2132 | |
e76e9aeb BW |
2133 | static int setup_scratch_page(struct drm_device *dev) |
2134 | { | |
2135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2136 | struct page *page; | |
2137 | dma_addr_t dma_addr; | |
2138 | ||
2139 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2140 | if (page == NULL) | |
2141 | return -ENOMEM; | |
e76e9aeb BW |
2142 | set_pages_uc(page, 1); |
2143 | ||
2144 | #ifdef CONFIG_INTEL_IOMMU | |
2145 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2146 | PCI_DMA_BIDIRECTIONAL); | |
2147 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
2148 | return -EINVAL; | |
2149 | #else | |
2150 | dma_addr = page_to_phys(page); | |
2151 | #endif | |
853ba5d2 BW |
2152 | dev_priv->gtt.base.scratch.page = page; |
2153 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2154 | |
2155 | return 0; | |
2156 | } | |
2157 | ||
2158 | static void teardown_scratch_page(struct drm_device *dev) | |
2159 | { | |
2160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2161 | struct page *page = dev_priv->gtt.base.scratch.page; |
2162 | ||
2163 | set_pages_wb(page, 1); | |
2164 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2165 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2166 | __free_page(page); |
e76e9aeb BW |
2167 | } |
2168 | ||
2169 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
2170 | { | |
2171 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2172 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2173 | return snb_gmch_ctl << 20; | |
2174 | } | |
2175 | ||
9459d252 BW |
2176 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
2177 | { | |
2178 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2179 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2180 | if (bdw_gmch_ctl) | |
2181 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2182 | |
2183 | #ifdef CONFIG_X86_32 | |
2184 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2185 | if (bdw_gmch_ctl > 4) | |
2186 | bdw_gmch_ctl = 4; | |
2187 | #endif | |
2188 | ||
9459d252 BW |
2189 | return bdw_gmch_ctl << 20; |
2190 | } | |
2191 | ||
d7f25f23 DL |
2192 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
2193 | { | |
2194 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2195 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2196 | ||
2197 | if (gmch_ctrl) | |
2198 | return 1 << (20 + gmch_ctrl); | |
2199 | ||
2200 | return 0; | |
2201 | } | |
2202 | ||
baa09f5f | 2203 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2204 | { |
2205 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2206 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2207 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2208 | } | |
2209 | ||
9459d252 BW |
2210 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
2211 | { | |
2212 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2213 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2214 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2215 | } | |
2216 | ||
d7f25f23 DL |
2217 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2218 | { | |
2219 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2220 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2221 | ||
2222 | /* | |
2223 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2224 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2225 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2226 | */ | |
2227 | if (gmch_ctrl < 0x11) | |
2228 | return gmch_ctrl << 25; | |
2229 | else if (gmch_ctrl < 0x17) | |
2230 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2231 | else | |
2232 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2233 | } | |
2234 | ||
66375014 DL |
2235 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2236 | { | |
2237 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2238 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2239 | ||
2240 | if (gen9_gmch_ctl < 0xf0) | |
2241 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2242 | else | |
2243 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2244 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2245 | } | |
2246 | ||
63340133 BW |
2247 | static int ggtt_probe_common(struct drm_device *dev, |
2248 | size_t gtt_size) | |
2249 | { | |
2250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2251 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2252 | int ret; |
2253 | ||
2254 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2255 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2256 | (pci_resource_len(dev->pdev, 0) / 2); |
2257 | ||
2a073f89 ID |
2258 | /* |
2259 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2260 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2261 | * when the WC buffer is flushed, so we can't use it, but have to | |
2262 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2263 | * readback check when writing GTT PTE entries. | |
2264 | */ | |
2265 | if (IS_BROXTON(dev)) | |
2266 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2267 | else | |
2268 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2269 | if (!dev_priv->gtt.gsm) { |
2270 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2271 | return -ENOMEM; | |
2272 | } | |
2273 | ||
2274 | ret = setup_scratch_page(dev); | |
2275 | if (ret) { | |
2276 | DRM_ERROR("Scratch setup failed\n"); | |
2277 | /* iounmap will also get called at remove, but meh */ | |
2278 | iounmap(dev_priv->gtt.gsm); | |
2279 | } | |
2280 | ||
2281 | return ret; | |
2282 | } | |
2283 | ||
fbe5d36e BW |
2284 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2285 | * bits. When using advanced contexts each context stores its own PAT, but | |
2286 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2287 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2288 | { |
fbe5d36e BW |
2289 | uint64_t pat; |
2290 | ||
2291 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2292 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2293 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2294 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2295 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2296 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2297 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2298 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2299 | ||
d6a8b72e RV |
2300 | if (!USES_PPGTT(dev_priv->dev)) |
2301 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2302 | * so RTL will always use the value corresponding to | |
2303 | * pat_sel = 000". | |
2304 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2305 | * MOCS still can be used though. | |
2306 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2307 | * before this patch, i.e. the same uncached + snooping access | |
2308 | * like on gen6/7 seems to be in effect. | |
2309 | * - So this just fixes blitter/render access. Again it looks | |
2310 | * like it's not just uncached access, but uncached + snooping. | |
2311 | * So we can still hold onto all our assumptions wrt cpu | |
2312 | * clflushing on LLC machines. | |
2313 | */ | |
2314 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2315 | ||
fbe5d36e BW |
2316 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2317 | * write would work. */ | |
2318 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2319 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2320 | } | |
2321 | ||
ee0ce478 VS |
2322 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2323 | { | |
2324 | uint64_t pat; | |
2325 | ||
2326 | /* | |
2327 | * Map WB on BDW to snooped on CHV. | |
2328 | * | |
2329 | * Only the snoop bit has meaning for CHV, the rest is | |
2330 | * ignored. | |
2331 | * | |
cf3d262e VS |
2332 | * The hardware will never snoop for certain types of accesses: |
2333 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2334 | * - PPGTT page tables | |
2335 | * - some other special cycles | |
2336 | * | |
2337 | * As with BDW, we also need to consider the following for GT accesses: | |
2338 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2339 | * so RTL will always use the value corresponding to | |
2340 | * pat_sel = 000". | |
2341 | * Which means we must set the snoop bit in PAT entry 0 | |
2342 | * in order to keep the global status page working. | |
ee0ce478 VS |
2343 | */ |
2344 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2345 | GEN8_PPAT(1, 0) | | |
2346 | GEN8_PPAT(2, 0) | | |
2347 | GEN8_PPAT(3, 0) | | |
2348 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2349 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2350 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2351 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2352 | ||
2353 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2354 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2355 | } | |
2356 | ||
63340133 BW |
2357 | static int gen8_gmch_probe(struct drm_device *dev, |
2358 | size_t *gtt_total, | |
2359 | size_t *stolen, | |
2360 | phys_addr_t *mappable_base, | |
2361 | unsigned long *mappable_end) | |
2362 | { | |
2363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2364 | unsigned int gtt_size; | |
2365 | u16 snb_gmch_ctl; | |
2366 | int ret; | |
2367 | ||
2368 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2369 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2370 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2371 | ||
2372 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2373 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2374 | ||
2375 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2376 | ||
66375014 DL |
2377 | if (INTEL_INFO(dev)->gen >= 9) { |
2378 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2379 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2380 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2381 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2382 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2383 | } else { | |
2384 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2385 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2386 | } | |
63340133 | 2387 | |
07749ef3 | 2388 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2389 | |
5a4e33a3 | 2390 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2391 | chv_setup_private_ppat(dev_priv); |
2392 | else | |
2393 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2394 | |
63340133 BW |
2395 | ret = ggtt_probe_common(dev, gtt_size); |
2396 | ||
94ec8f61 BW |
2397 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2398 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2399 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2400 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2401 | |
2402 | return ret; | |
2403 | } | |
2404 | ||
baa09f5f BW |
2405 | static int gen6_gmch_probe(struct drm_device *dev, |
2406 | size_t *gtt_total, | |
41907ddc BW |
2407 | size_t *stolen, |
2408 | phys_addr_t *mappable_base, | |
2409 | unsigned long *mappable_end) | |
e76e9aeb BW |
2410 | { |
2411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2412 | unsigned int gtt_size; |
e76e9aeb | 2413 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2414 | int ret; |
2415 | ||
41907ddc BW |
2416 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2417 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2418 | ||
baa09f5f BW |
2419 | /* 64/512MB is the current min/max we actually know of, but this is just |
2420 | * a coarse sanity check. | |
e76e9aeb | 2421 | */ |
41907ddc | 2422 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2423 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2424 | dev_priv->gtt.mappable_end); | |
2425 | return -ENXIO; | |
e76e9aeb BW |
2426 | } |
2427 | ||
e76e9aeb BW |
2428 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2429 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2430 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2431 | |
c4ae25ec | 2432 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2433 | |
63340133 | 2434 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2435 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2436 | |
63340133 | 2437 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2438 | |
853ba5d2 BW |
2439 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2440 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2441 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2442 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2443 | |
e76e9aeb BW |
2444 | return ret; |
2445 | } | |
2446 | ||
853ba5d2 | 2447 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2448 | { |
853ba5d2 BW |
2449 | |
2450 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2451 | |
853ba5d2 BW |
2452 | iounmap(gtt->gsm); |
2453 | teardown_scratch_page(vm->dev); | |
644ec02b | 2454 | } |
baa09f5f BW |
2455 | |
2456 | static int i915_gmch_probe(struct drm_device *dev, | |
2457 | size_t *gtt_total, | |
41907ddc BW |
2458 | size_t *stolen, |
2459 | phys_addr_t *mappable_base, | |
2460 | unsigned long *mappable_end) | |
baa09f5f BW |
2461 | { |
2462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2463 | int ret; | |
2464 | ||
baa09f5f BW |
2465 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2466 | if (!ret) { | |
2467 | DRM_ERROR("failed to set up gmch\n"); | |
2468 | return -EIO; | |
2469 | } | |
2470 | ||
41907ddc | 2471 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2472 | |
2473 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2474 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
777dc5bb DV |
2475 | dev_priv->gtt.base.bind_vma = i915_ggtt_bind_vma; |
2476 | dev_priv->gtt.base.unbind_vma = i915_ggtt_unbind_vma; | |
baa09f5f | 2477 | |
c0a7f818 CW |
2478 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2479 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2480 | ||
baa09f5f BW |
2481 | return 0; |
2482 | } | |
2483 | ||
853ba5d2 | 2484 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2485 | { |
2486 | intel_gmch_remove(); | |
2487 | } | |
2488 | ||
2489 | int i915_gem_gtt_init(struct drm_device *dev) | |
2490 | { | |
2491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2492 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2493 | int ret; |
2494 | ||
baa09f5f | 2495 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2496 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2497 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2498 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2499 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2500 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2501 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2502 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2503 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2504 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2505 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2506 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2507 | else if (INTEL_INFO(dev)->gen >= 7) |
2508 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2509 | else |
350ec881 | 2510 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2511 | } else { |
2512 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2513 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2514 | } |
2515 | ||
853ba5d2 | 2516 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2517 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2518 | if (ret) |
baa09f5f | 2519 | return ret; |
baa09f5f | 2520 | |
853ba5d2 BW |
2521 | gtt->base.dev = dev; |
2522 | ||
baa09f5f | 2523 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2524 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2525 | gtt->base.total >> 20); | |
b2f21b4d BW |
2526 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2527 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2528 | #ifdef CONFIG_INTEL_IOMMU |
2529 | if (intel_iommu_gfx_mapped) | |
2530 | DRM_INFO("VT-d active for gfx access\n"); | |
2531 | #endif | |
cfa7c862 DV |
2532 | /* |
2533 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2534 | * user's requested state against the hardware/driver capabilities. We | |
2535 | * do this now so that we can print out any log messages once rather | |
2536 | * than every time we check intel_enable_ppgtt(). | |
2537 | */ | |
2538 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2539 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2540 | |
2541 | return 0; | |
2542 | } | |
6f65e29a | 2543 | |
fa42331b DV |
2544 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2545 | { | |
2546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2547 | struct drm_i915_gem_object *obj; | |
2548 | struct i915_address_space *vm; | |
2549 | ||
2550 | i915_check_and_clear_faults(dev); | |
2551 | ||
2552 | /* First fill our portion of the GTT with scratch pages */ | |
2553 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2554 | dev_priv->gtt.base.start, | |
2555 | dev_priv->gtt.base.total, | |
2556 | true); | |
2557 | ||
2558 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
2559 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
2560 | &dev_priv->gtt.base); | |
2561 | if (!vma) | |
2562 | continue; | |
2563 | ||
2564 | i915_gem_clflush_object(obj, obj->pin_display); | |
2565 | WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); | |
2566 | } | |
2567 | ||
2568 | ||
2569 | if (INTEL_INFO(dev)->gen >= 8) { | |
2570 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2571 | chv_setup_private_ppat(dev_priv); | |
2572 | else | |
2573 | bdw_setup_private_ppat(dev_priv); | |
2574 | ||
2575 | return; | |
2576 | } | |
2577 | ||
2578 | if (USES_PPGTT(dev)) { | |
2579 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2580 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2581 | ||
2582 | struct i915_hw_ppgtt *ppgtt = | |
2583 | container_of(vm, struct i915_hw_ppgtt, | |
2584 | base); | |
2585 | ||
2586 | if (i915_is_ggtt(vm)) | |
2587 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2588 | ||
2589 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2590 | 0, ppgtt->base.total); | |
2591 | } | |
2592 | } | |
2593 | ||
2594 | i915_ggtt_flush(dev_priv); | |
2595 | } | |
2596 | ||
ec7adb6e JL |
2597 | static struct i915_vma * |
2598 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2599 | struct i915_address_space *vm, | |
2600 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2601 | { |
dabde5c7 | 2602 | struct i915_vma *vma; |
6f65e29a | 2603 | |
ec7adb6e JL |
2604 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2605 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2606 | |
2607 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2608 | if (vma == NULL) |
2609 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2610 | |
6f65e29a BW |
2611 | INIT_LIST_HEAD(&vma->vma_link); |
2612 | INIT_LIST_HEAD(&vma->mm_list); | |
2613 | INIT_LIST_HEAD(&vma->exec_list); | |
2614 | vma->vm = vm; | |
2615 | vma->obj = obj; | |
2616 | ||
777dc5bb | 2617 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2618 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2619 | |
f7635669 TU |
2620 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2621 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2622 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2623 | |
2624 | return vma; | |
2625 | } | |
2626 | ||
2627 | struct i915_vma * | |
ec7adb6e JL |
2628 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2629 | struct i915_address_space *vm) | |
2630 | { | |
2631 | struct i915_vma *vma; | |
2632 | ||
2633 | vma = i915_gem_obj_to_vma(obj, vm); | |
2634 | if (!vma) | |
2635 | vma = __i915_gem_vma_create(obj, vm, | |
2636 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2637 | ||
2638 | return vma; | |
2639 | } | |
2640 | ||
2641 | struct i915_vma * | |
2642 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2643 | const struct i915_ggtt_view *view) |
6f65e29a | 2644 | { |
ec7adb6e | 2645 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2646 | struct i915_vma *vma; |
2647 | ||
ec7adb6e JL |
2648 | if (WARN_ON(!view)) |
2649 | return ERR_PTR(-EINVAL); | |
2650 | ||
2651 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2652 | ||
2653 | if (IS_ERR(vma)) | |
2654 | return vma; | |
2655 | ||
6f65e29a | 2656 | if (!vma) |
ec7adb6e | 2657 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2658 | |
2659 | return vma; | |
ec7adb6e | 2660 | |
6f65e29a | 2661 | } |
fe14d5f4 | 2662 | |
50470bb0 TU |
2663 | static void |
2664 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2665 | struct sg_table *st) | |
2666 | { | |
2667 | unsigned int column, row; | |
2668 | unsigned int src_idx; | |
2669 | struct scatterlist *sg = st->sgl; | |
2670 | ||
2671 | st->nents = 0; | |
2672 | ||
2673 | for (column = 0; column < width; column++) { | |
2674 | src_idx = width * (height - 1) + column; | |
2675 | for (row = 0; row < height; row++) { | |
2676 | st->nents++; | |
2677 | /* We don't need the pages, but need to initialize | |
2678 | * the entries so the sg list can be happily traversed. | |
2679 | * The only thing we need are DMA addresses. | |
2680 | */ | |
2681 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2682 | sg_dma_address(sg) = in[src_idx]; | |
2683 | sg_dma_len(sg) = PAGE_SIZE; | |
2684 | sg = sg_next(sg); | |
2685 | src_idx -= width; | |
2686 | } | |
2687 | } | |
2688 | } | |
2689 | ||
2690 | static struct sg_table * | |
2691 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2692 | struct drm_i915_gem_object *obj) | |
2693 | { | |
2694 | struct drm_device *dev = obj->base.dev; | |
2695 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; | |
2696 | unsigned long size, pages, rot_pages; | |
2697 | struct sg_page_iter sg_iter; | |
2698 | unsigned long i; | |
2699 | dma_addr_t *page_addr_list; | |
2700 | struct sg_table *st; | |
2701 | unsigned int tile_pitch, tile_height; | |
2702 | unsigned int width_pages, height_pages; | |
1d00dad5 | 2703 | int ret = -ENOMEM; |
50470bb0 TU |
2704 | |
2705 | pages = obj->base.size / PAGE_SIZE; | |
2706 | ||
2707 | /* Calculate tiling geometry. */ | |
2708 | tile_height = intel_tile_height(dev, rot_info->pixel_format, | |
2709 | rot_info->fb_modifier); | |
2710 | tile_pitch = PAGE_SIZE / tile_height; | |
2711 | width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); | |
2712 | height_pages = DIV_ROUND_UP(rot_info->height, tile_height); | |
2713 | rot_pages = width_pages * height_pages; | |
2714 | size = rot_pages * PAGE_SIZE; | |
2715 | ||
2716 | /* Allocate a temporary list of source pages for random access. */ | |
2717 | page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); | |
2718 | if (!page_addr_list) | |
2719 | return ERR_PTR(ret); | |
2720 | ||
2721 | /* Allocate target SG list. */ | |
2722 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2723 | if (!st) | |
2724 | goto err_st_alloc; | |
2725 | ||
2726 | ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); | |
2727 | if (ret) | |
2728 | goto err_sg_alloc; | |
2729 | ||
2730 | /* Populate source page list from the object. */ | |
2731 | i = 0; | |
2732 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2733 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2734 | i++; | |
2735 | } | |
2736 | ||
2737 | /* Rotate the pages. */ | |
2738 | rotate_pages(page_addr_list, width_pages, height_pages, st); | |
2739 | ||
2740 | DRM_DEBUG_KMS( | |
2741 | "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", | |
2742 | size, rot_info->pitch, rot_info->height, | |
2743 | rot_info->pixel_format, width_pages, height_pages, | |
2744 | rot_pages); | |
2745 | ||
2746 | drm_free_large(page_addr_list); | |
2747 | ||
2748 | return st; | |
2749 | ||
2750 | err_sg_alloc: | |
2751 | kfree(st); | |
2752 | err_st_alloc: | |
2753 | drm_free_large(page_addr_list); | |
2754 | ||
2755 | DRM_DEBUG_KMS( | |
2756 | "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", | |
2757 | size, ret, rot_info->pitch, rot_info->height, | |
2758 | rot_info->pixel_format, width_pages, height_pages, | |
2759 | rot_pages); | |
2760 | return ERR_PTR(ret); | |
2761 | } | |
ec7adb6e | 2762 | |
50470bb0 TU |
2763 | static inline int |
2764 | i915_get_ggtt_vma_pages(struct i915_vma *vma) | |
fe14d5f4 | 2765 | { |
50470bb0 TU |
2766 | int ret = 0; |
2767 | ||
fe14d5f4 TU |
2768 | if (vma->ggtt_view.pages) |
2769 | return 0; | |
2770 | ||
2771 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2772 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2773 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2774 | vma->ggtt_view.pages = | |
2775 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2776 | else |
2777 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2778 | vma->ggtt_view.type); | |
2779 | ||
2780 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2781 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2782 | vma->ggtt_view.type); |
50470bb0 TU |
2783 | ret = -EINVAL; |
2784 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2785 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2786 | vma->ggtt_view.pages = NULL; | |
2787 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2788 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2789 | } |
2790 | ||
50470bb0 | 2791 | return ret; |
fe14d5f4 TU |
2792 | } |
2793 | ||
2794 | /** | |
2795 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2796 | * @vma: VMA to map | |
2797 | * @cache_level: mapping cache level | |
2798 | * @flags: flags like global or local mapping | |
2799 | * | |
2800 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2801 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2802 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2803 | */ | |
2804 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2805 | u32 flags) | |
2806 | { | |
0875546c | 2807 | u32 bind_flags = 0; |
1d335d1b MK |
2808 | int ret; |
2809 | ||
2810 | if (vma->vm->allocate_va_range) { | |
2811 | trace_i915_va_alloc(vma->vm, vma->node.start, | |
2812 | vma->node.size, | |
2813 | VM_TO_TRACE_NAME(vma->vm)); | |
2814 | ||
2815 | ret = vma->vm->allocate_va_range(vma->vm, | |
2816 | vma->node.start, | |
2817 | vma->node.size); | |
2818 | if (ret) | |
2819 | return ret; | |
2820 | } | |
2821 | ||
ec7adb6e | 2822 | if (i915_is_ggtt(vma->vm)) { |
1d335d1b | 2823 | ret = i915_get_ggtt_vma_pages(vma); |
ec7adb6e | 2824 | if (ret) |
0875546c | 2825 | return 0; |
ec7adb6e | 2826 | } |
fe14d5f4 | 2827 | |
0875546c DV |
2828 | if (flags & PIN_GLOBAL) |
2829 | bind_flags |= GLOBAL_BIND; | |
2830 | if (flags & PIN_USER) | |
2831 | bind_flags |= LOCAL_BIND; | |
2832 | ||
2833 | if (flags & PIN_UPDATE) | |
2834 | bind_flags |= vma->bound; | |
2835 | else | |
2836 | bind_flags &= ~vma->bound; | |
2837 | ||
2838 | if (bind_flags) | |
2839 | vma->vm->bind_vma(vma, cache_level, bind_flags); | |
2840 | ||
2841 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
2842 | |
2843 | return 0; | |
2844 | } |