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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
cfa7c862 DV |
36 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
37 | { | |
38 | if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
39 | return 0; | |
40 | ||
41 | if (enable_ppgtt == 1) | |
42 | return 1; | |
43 | ||
44 | if (enable_ppgtt == 2 && HAS_PPGTT(dev)) | |
45 | return 2; | |
46 | ||
93a25a9e DV |
47 | #ifdef CONFIG_INTEL_IOMMU |
48 | /* Disable ppgtt on SNB if VT-d is on. */ | |
49 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
50 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 51 | return 0; |
93a25a9e DV |
52 | } |
53 | #endif | |
54 | ||
62942ed7 | 55 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
56 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
57 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
58 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
59 | return 0; | |
60 | } | |
61 | ||
cfa7c862 | 62 | return HAS_ALIASING_PPGTT(dev) ? 1 : 0; |
93a25a9e DV |
63 | } |
64 | ||
fbe5d36e | 65 | |
6f65e29a BW |
66 | static void ppgtt_bind_vma(struct i915_vma *vma, |
67 | enum i915_cache_level cache_level, | |
68 | u32 flags); | |
69 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
70 | ||
94ec8f61 BW |
71 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
72 | enum i915_cache_level level, | |
73 | bool valid) | |
74 | { | |
75 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
76 | pte |= addr; | |
63c42e56 BW |
77 | |
78 | switch (level) { | |
79 | case I915_CACHE_NONE: | |
fbe5d36e | 80 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
81 | break; |
82 | case I915_CACHE_WT: | |
83 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
84 | break; | |
85 | default: | |
86 | pte |= PPAT_CACHED_INDEX; | |
87 | break; | |
88 | } | |
89 | ||
94ec8f61 BW |
90 | return pte; |
91 | } | |
92 | ||
b1fe6673 BW |
93 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
94 | dma_addr_t addr, | |
95 | enum i915_cache_level level) | |
96 | { | |
97 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
98 | pde |= addr; | |
99 | if (level != I915_CACHE_NONE) | |
100 | pde |= PPAT_CACHED_PDE_INDEX; | |
101 | else | |
102 | pde |= PPAT_UNCACHED_INDEX; | |
103 | return pde; | |
104 | } | |
105 | ||
350ec881 | 106 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 107 | enum i915_cache_level level, |
24f3a8cf | 108 | bool valid, u32 unused) |
54d12527 | 109 | { |
b35b380e | 110 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 111 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
112 | |
113 | switch (level) { | |
350ec881 CW |
114 | case I915_CACHE_L3_LLC: |
115 | case I915_CACHE_LLC: | |
116 | pte |= GEN6_PTE_CACHE_LLC; | |
117 | break; | |
118 | case I915_CACHE_NONE: | |
119 | pte |= GEN6_PTE_UNCACHED; | |
120 | break; | |
121 | default: | |
122 | WARN_ON(1); | |
123 | } | |
124 | ||
125 | return pte; | |
126 | } | |
127 | ||
128 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 129 | enum i915_cache_level level, |
24f3a8cf | 130 | bool valid, u32 unused) |
350ec881 | 131 | { |
b35b380e | 132 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
133 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
134 | ||
135 | switch (level) { | |
136 | case I915_CACHE_L3_LLC: | |
137 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
138 | break; |
139 | case I915_CACHE_LLC: | |
140 | pte |= GEN6_PTE_CACHE_LLC; | |
141 | break; | |
142 | case I915_CACHE_NONE: | |
9119708c | 143 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
144 | break; |
145 | default: | |
350ec881 | 146 | WARN_ON(1); |
e7210c3c BW |
147 | } |
148 | ||
54d12527 BW |
149 | return pte; |
150 | } | |
151 | ||
80a74f7f | 152 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 153 | enum i915_cache_level level, |
24f3a8cf | 154 | bool valid, u32 flags) |
93c34e70 | 155 | { |
b35b380e | 156 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
157 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
158 | ||
159 | /* Mark the page as writeable. Other platforms don't have a | |
160 | * setting for read-only/writable, so this matches that behavior. | |
161 | */ | |
24f3a8cf AG |
162 | if (!(flags & PTE_READ_ONLY)) |
163 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
164 | |
165 | if (level != I915_CACHE_NONE) | |
166 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
167 | ||
168 | return pte; | |
169 | } | |
170 | ||
80a74f7f | 171 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 172 | enum i915_cache_level level, |
24f3a8cf | 173 | bool valid, u32 unused) |
9119708c | 174 | { |
b35b380e | 175 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 176 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
177 | |
178 | if (level != I915_CACHE_NONE) | |
87a6b688 | 179 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
180 | |
181 | return pte; | |
182 | } | |
183 | ||
4d15c145 | 184 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 185 | enum i915_cache_level level, |
24f3a8cf | 186 | bool valid, u32 unused) |
4d15c145 | 187 | { |
b35b380e | 188 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
189 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
190 | ||
651d794f CW |
191 | switch (level) { |
192 | case I915_CACHE_NONE: | |
193 | break; | |
194 | case I915_CACHE_WT: | |
c51e9701 | 195 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
196 | break; |
197 | default: | |
c51e9701 | 198 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
199 | break; |
200 | } | |
4d15c145 BW |
201 | |
202 | return pte; | |
203 | } | |
204 | ||
94e409c1 | 205 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 206 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
e178f705 | 207 | uint64_t val, bool synchronous) |
94e409c1 | 208 | { |
e178f705 | 209 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
210 | int ret; |
211 | ||
212 | BUG_ON(entry >= 4); | |
213 | ||
e178f705 BW |
214 | if (synchronous) { |
215 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
216 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
217 | return 0; | |
218 | } | |
219 | ||
94e409c1 BW |
220 | ret = intel_ring_begin(ring, 6); |
221 | if (ret) | |
222 | return ret; | |
223 | ||
224 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
225 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
226 | intel_ring_emit(ring, (u32)(val >> 32)); | |
227 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
228 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
229 | intel_ring_emit(ring, (u32)(val)); | |
230 | intel_ring_advance(ring); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
eeb9488e | 235 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 236 | struct intel_engine_cs *ring, |
eeb9488e | 237 | bool synchronous) |
94e409c1 | 238 | { |
eeb9488e | 239 | int i, ret; |
94e409c1 BW |
240 | |
241 | /* bit of a hack to find the actual last used pd */ | |
242 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
243 | ||
94e409c1 BW |
244 | for (i = used_pd - 1; i >= 0; i--) { |
245 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
246 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
247 | if (ret) | |
248 | return ret; | |
94e409c1 | 249 | } |
d595bd4b | 250 | |
eeb9488e | 251 | return 0; |
94e409c1 BW |
252 | } |
253 | ||
459108b8 | 254 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
255 | uint64_t start, |
256 | uint64_t length, | |
459108b8 BW |
257 | bool use_scratch) |
258 | { | |
259 | struct i915_hw_ppgtt *ppgtt = | |
260 | container_of(vm, struct i915_hw_ppgtt, base); | |
261 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
262 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
263 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
264 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 265 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
266 | unsigned last_pte, i; |
267 | ||
268 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
269 | I915_CACHE_LLC, use_scratch); | |
270 | ||
271 | while (num_entries) { | |
7ad47cf2 | 272 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 273 | |
7ad47cf2 | 274 | last_pte = pte + num_entries; |
459108b8 BW |
275 | if (last_pte > GEN8_PTES_PER_PAGE) |
276 | last_pte = GEN8_PTES_PER_PAGE; | |
277 | ||
278 | pt_vaddr = kmap_atomic(page_table); | |
279 | ||
7ad47cf2 | 280 | for (i = pte; i < last_pte; i++) { |
459108b8 | 281 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
282 | num_entries--; |
283 | } | |
459108b8 | 284 | |
fd1ab8f4 RB |
285 | if (!HAS_LLC(ppgtt->base.dev)) |
286 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
287 | kunmap_atomic(pt_vaddr); |
288 | ||
7ad47cf2 BW |
289 | pte = 0; |
290 | if (++pde == GEN8_PDES_PER_PAGE) { | |
291 | pdpe++; | |
292 | pde = 0; | |
293 | } | |
459108b8 BW |
294 | } |
295 | } | |
296 | ||
9df15b49 BW |
297 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
298 | struct sg_table *pages, | |
782f1495 | 299 | uint64_t start, |
24f3a8cf | 300 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
301 | { |
302 | struct i915_hw_ppgtt *ppgtt = | |
303 | container_of(vm, struct i915_hw_ppgtt, base); | |
304 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
305 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
306 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
307 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
308 | struct sg_page_iter sg_iter; |
309 | ||
6f1cc993 | 310 | pt_vaddr = NULL; |
7ad47cf2 | 311 | |
9df15b49 | 312 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
313 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
314 | break; | |
315 | ||
6f1cc993 | 316 | if (pt_vaddr == NULL) |
7ad47cf2 | 317 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 318 | |
7ad47cf2 | 319 | pt_vaddr[pte] = |
6f1cc993 CW |
320 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
321 | cache_level, true); | |
7ad47cf2 | 322 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
323 | if (!HAS_LLC(ppgtt->base.dev)) |
324 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 325 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 326 | pt_vaddr = NULL; |
7ad47cf2 BW |
327 | if (++pde == GEN8_PDES_PER_PAGE) { |
328 | pdpe++; | |
329 | pde = 0; | |
330 | } | |
331 | pte = 0; | |
9df15b49 BW |
332 | } |
333 | } | |
fd1ab8f4 RB |
334 | if (pt_vaddr) { |
335 | if (!HAS_LLC(ppgtt->base.dev)) | |
336 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 337 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 338 | } |
9df15b49 BW |
339 | } |
340 | ||
7ad47cf2 BW |
341 | static void gen8_free_page_tables(struct page **pt_pages) |
342 | { | |
343 | int i; | |
344 | ||
345 | if (pt_pages == NULL) | |
346 | return; | |
347 | ||
348 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
349 | if (pt_pages[i]) | |
350 | __free_pages(pt_pages[i], 0); | |
351 | } | |
352 | ||
353 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
354 | { |
355 | int i; | |
356 | ||
7ad47cf2 BW |
357 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
358 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
359 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 360 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 361 | } |
b45a6715 | 362 | |
b45a6715 BW |
363 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
364 | } | |
365 | ||
366 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
367 | { | |
f3a964b9 | 368 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
369 | int i, j; |
370 | ||
371 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
372 | /* TODO: In the future we'll support sparse mappings, so this | |
373 | * will have to change. */ | |
374 | if (!ppgtt->pd_dma_addr[i]) | |
375 | continue; | |
376 | ||
f3a964b9 BW |
377 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
378 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
379 | |
380 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
381 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
382 | if (addr) | |
f3a964b9 BW |
383 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
384 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
385 | } |
386 | } | |
387 | } | |
388 | ||
37aca44a BW |
389 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
390 | { | |
391 | struct i915_hw_ppgtt *ppgtt = | |
392 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 393 | |
b45a6715 BW |
394 | gen8_ppgtt_unmap_pages(ppgtt); |
395 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
396 | } |
397 | ||
7ad47cf2 BW |
398 | static struct page **__gen8_alloc_page_tables(void) |
399 | { | |
400 | struct page **pt_pages; | |
401 | int i; | |
402 | ||
403 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
404 | if (!pt_pages) | |
405 | return ERR_PTR(-ENOMEM); | |
406 | ||
407 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
408 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
409 | if (!pt_pages[i]) | |
410 | goto bail; | |
411 | } | |
412 | ||
413 | return pt_pages; | |
414 | ||
415 | bail: | |
416 | gen8_free_page_tables(pt_pages); | |
417 | kfree(pt_pages); | |
418 | return ERR_PTR(-ENOMEM); | |
419 | } | |
420 | ||
bf2b4ed2 BW |
421 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
422 | const int max_pdp) | |
423 | { | |
7ad47cf2 | 424 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 425 | int i, ret; |
bf2b4ed2 | 426 | |
7ad47cf2 BW |
427 | for (i = 0; i < max_pdp; i++) { |
428 | pt_pages[i] = __gen8_alloc_page_tables(); | |
429 | if (IS_ERR(pt_pages[i])) { | |
430 | ret = PTR_ERR(pt_pages[i]); | |
431 | goto unwind_out; | |
432 | } | |
433 | } | |
434 | ||
435 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
436 | * "atomic" - for cleanup purposes. | |
437 | */ | |
438 | for (i = 0; i < max_pdp; i++) | |
439 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 440 | |
bf2b4ed2 | 441 | return 0; |
7ad47cf2 BW |
442 | |
443 | unwind_out: | |
444 | while (i--) { | |
445 | gen8_free_page_tables(pt_pages[i]); | |
446 | kfree(pt_pages[i]); | |
447 | } | |
448 | ||
449 | return ret; | |
bf2b4ed2 BW |
450 | } |
451 | ||
452 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
453 | { | |
454 | int i; | |
455 | ||
456 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
457 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
458 | sizeof(dma_addr_t), | |
459 | GFP_KERNEL); | |
460 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
461 | return -ENOMEM; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
468 | const int max_pdp) | |
469 | { | |
470 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
471 | if (!ppgtt->pd_pages) | |
472 | return -ENOMEM; | |
473 | ||
474 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
475 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
481 | const int max_pdp) | |
482 | { | |
483 | int ret; | |
484 | ||
485 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
486 | if (ret) | |
487 | return ret; | |
488 | ||
489 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
490 | if (ret) { | |
491 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
492 | return ret; | |
493 | } | |
494 | ||
495 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
496 | ||
497 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
498 | if (ret) | |
499 | gen8_ppgtt_free(ppgtt); | |
500 | ||
501 | return ret; | |
502 | } | |
503 | ||
504 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
505 | const int pd) | |
506 | { | |
507 | dma_addr_t pd_addr; | |
508 | int ret; | |
509 | ||
510 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
511 | &ppgtt->pd_pages[pd], 0, | |
512 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
513 | ||
514 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
515 | if (ret) | |
516 | return ret; | |
517 | ||
518 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
524 | const int pd, | |
525 | const int pt) | |
526 | { | |
527 | dma_addr_t pt_addr; | |
528 | struct page *p; | |
529 | int ret; | |
530 | ||
7ad47cf2 | 531 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
532 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
533 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
534 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
535 | if (ret) | |
536 | return ret; | |
537 | ||
538 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
37aca44a | 543 | /** |
f3a964b9 BW |
544 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
545 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
546 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
547 | * space. | |
37aca44a | 548 | * |
f3a964b9 BW |
549 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
550 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 551 | * TODO: Do something with the size parameter |
f3a964b9 | 552 | */ |
37aca44a BW |
553 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
554 | { | |
37aca44a | 555 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 556 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 557 | int i, j, ret; |
37aca44a BW |
558 | |
559 | if (size % (1<<30)) | |
560 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
561 | ||
bf2b4ed2 BW |
562 | /* 1. Do all our allocations for page directories and page tables. */ |
563 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
564 | if (ret) | |
565 | return ret; | |
f3a964b9 | 566 | |
37aca44a | 567 | /* |
bf2b4ed2 | 568 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
569 | */ |
570 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 571 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
572 | if (ret) |
573 | goto bail; | |
37aca44a | 574 | |
37aca44a | 575 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 576 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
577 | if (ret) |
578 | goto bail; | |
37aca44a BW |
579 | } |
580 | } | |
581 | ||
f3a964b9 BW |
582 | /* |
583 | * 3. Map all the page directory entires to point to the page tables | |
584 | * we've allocated. | |
585 | * | |
586 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 587 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
588 | * will never need to touch the PDEs again. |
589 | */ | |
b1fe6673 BW |
590 | for (i = 0; i < max_pdp; i++) { |
591 | gen8_ppgtt_pde_t *pd_vaddr; | |
592 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
593 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
594 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
595 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
596 | I915_CACHE_LLC); | |
597 | } | |
fd1ab8f4 RB |
598 | if (!HAS_LLC(ppgtt->base.dev)) |
599 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
600 | kunmap_atomic(pd_vaddr); |
601 | } | |
602 | ||
f3a964b9 BW |
603 | ppgtt->switch_mm = gen8_mm_switch; |
604 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
605 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
606 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
607 | ppgtt->base.start = 0; | |
5abbcca3 | 608 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 609 | |
5abbcca3 | 610 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 611 | |
37aca44a BW |
612 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
613 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
614 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
615 | ppgtt->num_pd_entries, |
616 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 617 | return 0; |
37aca44a | 618 | |
f3a964b9 BW |
619 | bail: |
620 | gen8_ppgtt_unmap_pages(ppgtt); | |
621 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
622 | return ret; |
623 | } | |
624 | ||
87d60b63 BW |
625 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
626 | { | |
627 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
628 | struct i915_address_space *vm = &ppgtt->base; | |
629 | gen6_gtt_pte_t __iomem *pd_addr; | |
630 | gen6_gtt_pte_t scratch_pte; | |
631 | uint32_t pd_entry; | |
632 | int pte, pde; | |
633 | ||
24f3a8cf | 634 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
635 | |
636 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
637 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
638 | ||
639 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
640 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
641 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
642 | u32 expected; | |
643 | gen6_gtt_pte_t *pt_vaddr; | |
644 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
645 | pd_entry = readl(pd_addr + pde); | |
646 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
647 | ||
648 | if (pd_entry != expected) | |
649 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
650 | pde, | |
651 | pd_entry, | |
652 | expected); | |
653 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
654 | ||
655 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
656 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
657 | unsigned long va = | |
658 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
659 | (pte * PAGE_SIZE); | |
660 | int i; | |
661 | bool found = false; | |
662 | for (i = 0; i < 4; i++) | |
663 | if (pt_vaddr[pte + i] != scratch_pte) | |
664 | found = true; | |
665 | if (!found) | |
666 | continue; | |
667 | ||
668 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
669 | for (i = 0; i < 4; i++) { | |
670 | if (pt_vaddr[pte + i] != scratch_pte) | |
671 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
672 | else | |
673 | seq_puts(m, " SCRATCH "); | |
674 | } | |
675 | seq_puts(m, "\n"); | |
676 | } | |
677 | kunmap_atomic(pt_vaddr); | |
678 | } | |
679 | } | |
680 | ||
3e302542 | 681 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 682 | { |
853ba5d2 | 683 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
684 | gen6_gtt_pte_t __iomem *pd_addr; |
685 | uint32_t pd_entry; | |
686 | int i; | |
687 | ||
0a732870 | 688 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
689 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
690 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
691 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
692 | dma_addr_t pt_addr; | |
693 | ||
694 | pt_addr = ppgtt->pt_dma_addr[i]; | |
695 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
696 | pd_entry |= GEN6_PDE_VALID; | |
697 | ||
698 | writel(pd_entry, pd_addr + i); | |
699 | } | |
700 | readl(pd_addr); | |
3e302542 BW |
701 | } |
702 | ||
b4a74e3a | 703 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 704 | { |
b4a74e3a BW |
705 | BUG_ON(ppgtt->pd_offset & 0x3f); |
706 | ||
707 | return (ppgtt->pd_offset / 64) << 16; | |
708 | } | |
709 | ||
90252e5c | 710 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 711 | struct intel_engine_cs *ring, |
90252e5c BW |
712 | bool synchronous) |
713 | { | |
714 | struct drm_device *dev = ppgtt->base.dev; | |
715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
716 | int ret; | |
717 | ||
718 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
719 | * manually frob these bits. Ideally we could use the ring functions, | |
720 | * except our error handling makes it quite difficult (can't use | |
721 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
722 | * | |
723 | * FIXME: We should try not to special case reset | |
724 | */ | |
725 | if (synchronous || | |
726 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
727 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
728 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
729 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
730 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
731 | return 0; | |
732 | } | |
733 | ||
734 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
735 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
736 | if (ret) | |
737 | return ret; | |
738 | ||
739 | ret = intel_ring_begin(ring, 6); | |
740 | if (ret) | |
741 | return ret; | |
742 | ||
743 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
744 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
745 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
746 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
747 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
748 | intel_ring_emit(ring, MI_NOOP); | |
749 | intel_ring_advance(ring); | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
48a10389 | 754 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 755 | struct intel_engine_cs *ring, |
48a10389 BW |
756 | bool synchronous) |
757 | { | |
758 | struct drm_device *dev = ppgtt->base.dev; | |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
760 | int ret; | |
761 | ||
762 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
763 | * manually frob these bits. Ideally we could use the ring functions, | |
764 | * except our error handling makes it quite difficult (can't use | |
765 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
766 | * | |
767 | * FIXME: We should try not to special case reset | |
768 | */ | |
769 | if (synchronous || | |
770 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
771 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
772 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
773 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
774 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
779 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
780 | if (ret) | |
781 | return ret; | |
782 | ||
783 | ret = intel_ring_begin(ring, 6); | |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
788 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
789 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
790 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
791 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
792 | intel_ring_emit(ring, MI_NOOP); | |
793 | intel_ring_advance(ring); | |
794 | ||
90252e5c BW |
795 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
796 | if (ring->id != RCS) { | |
797 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
798 | if (ret) | |
799 | return ret; | |
800 | } | |
801 | ||
48a10389 BW |
802 | return 0; |
803 | } | |
804 | ||
eeb9488e | 805 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 806 | struct intel_engine_cs *ring, |
eeb9488e BW |
807 | bool synchronous) |
808 | { | |
809 | struct drm_device *dev = ppgtt->base.dev; | |
810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
811 | ||
48a10389 BW |
812 | if (!synchronous) |
813 | return 0; | |
814 | ||
eeb9488e BW |
815 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
816 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
817 | ||
818 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
82460d97 | 823 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 824 | { |
eeb9488e | 825 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 826 | struct intel_engine_cs *ring; |
82460d97 | 827 | int j; |
3e302542 | 828 | |
b7c71823 OM |
829 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
830 | * and the PDPs are contained within the context itself. We don't | |
831 | * need to do anything here. */ | |
832 | if (i915.enable_execlists) | |
833 | return; | |
834 | ||
eeb9488e BW |
835 | for_each_ring(ring, dev_priv, j) { |
836 | I915_WRITE(RING_MODE_GEN7(ring), | |
837 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 838 | } |
eeb9488e | 839 | } |
6197349b | 840 | |
82460d97 | 841 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 842 | { |
50227e1c | 843 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 844 | struct intel_engine_cs *ring; |
b4a74e3a | 845 | uint32_t ecochk, ecobits; |
3e302542 | 846 | int i; |
6197349b | 847 | |
b4a74e3a BW |
848 | ecobits = I915_READ(GAC_ECO_BITS); |
849 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 850 | |
b4a74e3a BW |
851 | ecochk = I915_READ(GAM_ECOCHK); |
852 | if (IS_HASWELL(dev)) { | |
853 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
854 | } else { | |
855 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
856 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
857 | } | |
858 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 859 | |
b4a74e3a | 860 | for_each_ring(ring, dev_priv, i) { |
6197349b | 861 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
862 | I915_WRITE(RING_MODE_GEN7(ring), |
863 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 864 | } |
b4a74e3a | 865 | } |
6197349b | 866 | |
82460d97 | 867 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 868 | { |
50227e1c | 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 870 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 871 | |
b4a74e3a BW |
872 | ecobits = I915_READ(GAC_ECO_BITS); |
873 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
874 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 875 | |
b4a74e3a BW |
876 | gab_ctl = I915_READ(GAB_CTL); |
877 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
878 | ||
879 | ecochk = I915_READ(GAM_ECOCHK); | |
880 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
881 | ||
882 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
883 | } |
884 | ||
1d2a314c | 885 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 886 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
887 | uint64_t start, |
888 | uint64_t length, | |
828c7908 | 889 | bool use_scratch) |
1d2a314c | 890 | { |
853ba5d2 BW |
891 | struct i915_hw_ppgtt *ppgtt = |
892 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 893 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
894 | unsigned first_entry = start >> PAGE_SHIFT; |
895 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 896 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
897 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
898 | unsigned last_pte, i; | |
1d2a314c | 899 | |
24f3a8cf | 900 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 901 | |
7bddb01f DV |
902 | while (num_entries) { |
903 | last_pte = first_pte + num_entries; | |
904 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
905 | last_pte = I915_PPGTT_PT_ENTRIES; | |
906 | ||
a15326a5 | 907 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 908 | |
7bddb01f DV |
909 | for (i = first_pte; i < last_pte; i++) |
910 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
911 | |
912 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 913 | |
7bddb01f DV |
914 | num_entries -= last_pte - first_pte; |
915 | first_pte = 0; | |
a15326a5 | 916 | act_pt++; |
7bddb01f | 917 | } |
1d2a314c DV |
918 | } |
919 | ||
853ba5d2 | 920 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 921 | struct sg_table *pages, |
782f1495 | 922 | uint64_t start, |
24f3a8cf | 923 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 924 | { |
853ba5d2 BW |
925 | struct i915_hw_ppgtt *ppgtt = |
926 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 927 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 928 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 929 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
930 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
931 | struct sg_page_iter sg_iter; | |
932 | ||
cc79714f | 933 | pt_vaddr = NULL; |
6e995e23 | 934 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
935 | if (pt_vaddr == NULL) |
936 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 937 | |
cc79714f CW |
938 | pt_vaddr[act_pte] = |
939 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
940 | cache_level, true, flags); |
941 | ||
6e995e23 ID |
942 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
943 | kunmap_atomic(pt_vaddr); | |
cc79714f | 944 | pt_vaddr = NULL; |
a15326a5 | 945 | act_pt++; |
6e995e23 | 946 | act_pte = 0; |
def886c3 | 947 | } |
def886c3 | 948 | } |
cc79714f CW |
949 | if (pt_vaddr) |
950 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
951 | } |
952 | ||
a00d825d | 953 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 954 | { |
3440d265 DV |
955 | int i; |
956 | ||
957 | if (ppgtt->pt_dma_addr) { | |
958 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 959 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
960 | ppgtt->pt_dma_addr[i], |
961 | 4096, PCI_DMA_BIDIRECTIONAL); | |
962 | } | |
a00d825d BW |
963 | } |
964 | ||
965 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
966 | { | |
967 | int i; | |
3440d265 DV |
968 | |
969 | kfree(ppgtt->pt_dma_addr); | |
970 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
971 | __free_page(ppgtt->pt_pages[i]); | |
972 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
973 | } |
974 | ||
a00d825d BW |
975 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
976 | { | |
977 | struct i915_hw_ppgtt *ppgtt = | |
978 | container_of(vm, struct i915_hw_ppgtt, base); | |
979 | ||
a00d825d BW |
980 | drm_mm_remove_node(&ppgtt->node); |
981 | ||
982 | gen6_ppgtt_unmap_pages(ppgtt); | |
983 | gen6_ppgtt_free(ppgtt); | |
984 | } | |
985 | ||
b146520f | 986 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 987 | { |
853ba5d2 | 988 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 989 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 990 | bool retried = false; |
b146520f | 991 | int ret; |
1d2a314c | 992 | |
c8d4c0d6 BW |
993 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
994 | * allocator works in address space sizes, so it's multiplied by page | |
995 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
996 | */ | |
997 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 998 | alloc: |
c8d4c0d6 BW |
999 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1000 | &ppgtt->node, GEN6_PD_SIZE, | |
1001 | GEN6_PD_ALIGN, 0, | |
1002 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1003 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1004 | if (ret == -ENOSPC && !retried) { |
1005 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1006 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1007 | I915_CACHE_NONE, |
1008 | 0, dev_priv->gtt.base.total, | |
1009 | 0); | |
e3cc1995 BW |
1010 | if (ret) |
1011 | return ret; | |
1012 | ||
1013 | retried = true; | |
1014 | goto alloc; | |
1015 | } | |
c8d4c0d6 BW |
1016 | |
1017 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1018 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1019 | |
6670a5a5 | 1020 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1021 | return ret; |
1022 | } | |
1023 | ||
1024 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1025 | { | |
1026 | int i; | |
1027 | ||
a1e22653 | 1028 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1029 | GFP_KERNEL); |
b146520f BW |
1030 | |
1031 | if (!ppgtt->pt_pages) | |
3440d265 | 1032 | return -ENOMEM; |
1d2a314c DV |
1033 | |
1034 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1035 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1036 | if (!ppgtt->pt_pages[i]) { |
1037 | gen6_ppgtt_free(ppgtt); | |
1038 | return -ENOMEM; | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1046 | { | |
1047 | int ret; | |
1048 | ||
1049 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1050 | if (ret) | |
1051 | return ret; | |
1052 | ||
1053 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1054 | if (ret) { | |
1055 | drm_mm_remove_node(&ppgtt->node); | |
1056 | return ret; | |
1d2a314c DV |
1057 | } |
1058 | ||
a1e22653 | 1059 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1060 | GFP_KERNEL); |
b146520f BW |
1061 | if (!ppgtt->pt_dma_addr) { |
1062 | drm_mm_remove_node(&ppgtt->node); | |
1063 | gen6_ppgtt_free(ppgtt); | |
1064 | return -ENOMEM; | |
1065 | } | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1071 | { | |
1072 | struct drm_device *dev = ppgtt->base.dev; | |
1073 | int i; | |
1d2a314c | 1074 | |
8d2e6308 BW |
1075 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1076 | dma_addr_t pt_addr; | |
211c568b | 1077 | |
8d2e6308 BW |
1078 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1079 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1080 | |
8d2e6308 | 1081 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1082 | gen6_ppgtt_unmap_pages(ppgtt); |
1083 | return -EIO; | |
211c568b | 1084 | } |
b146520f | 1085 | |
8d2e6308 | 1086 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1087 | } |
1d2a314c | 1088 | |
b146520f BW |
1089 | return 0; |
1090 | } | |
1091 | ||
1092 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1093 | { | |
1094 | struct drm_device *dev = ppgtt->base.dev; | |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1096 | int ret; | |
1097 | ||
1098 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1099 | if (IS_GEN6(dev)) { | |
b146520f BW |
1100 | ppgtt->switch_mm = gen6_mm_switch; |
1101 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1102 | ppgtt->switch_mm = hsw_mm_switch; |
1103 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1104 | ppgtt->switch_mm = gen7_mm_switch; |
1105 | } else | |
1106 | BUG(); | |
1107 | ||
1108 | ret = gen6_ppgtt_alloc(ppgtt); | |
1109 | if (ret) | |
1110 | return ret; | |
1111 | ||
1112 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1113 | if (ret) { | |
1114 | gen6_ppgtt_free(ppgtt); | |
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1119 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1120 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1121 | ppgtt->base.start = 0; |
5a6c93fe | 1122 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1123 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1124 | |
c8d4c0d6 BW |
1125 | ppgtt->pd_offset = |
1126 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1127 | |
b146520f | 1128 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1129 | |
b146520f BW |
1130 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1131 | ppgtt->node.size >> 20, | |
1132 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1133 | |
fa76da34 DV |
1134 | gen6_write_pdes(ppgtt); |
1135 | DRM_DEBUG("Adding PPGTT at offset %x\n", | |
1136 | ppgtt->pd_offset << 10); | |
1137 | ||
b146520f | 1138 | return 0; |
3440d265 DV |
1139 | } |
1140 | ||
fa76da34 | 1141 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1142 | { |
1143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1144 | |
853ba5d2 | 1145 | ppgtt->base.dev = dev; |
8407bb91 | 1146 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1147 | |
3ed124b2 | 1148 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1149 | return gen6_ppgtt_init(ppgtt); |
8fe6bd23 | 1150 | else if (IS_GEN8(dev)) |
fa76da34 | 1151 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1152 | else |
1153 | BUG(); | |
fa76da34 DV |
1154 | } |
1155 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1156 | { | |
1157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1158 | int ret = 0; | |
3ed124b2 | 1159 | |
fa76da34 DV |
1160 | ret = __hw_ppgtt_init(dev, ppgtt); |
1161 | if (ret == 0) { | |
c7c48dfd | 1162 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1163 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1164 | ppgtt->base.total); | |
7e0d96bc | 1165 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1166 | } |
1d2a314c DV |
1167 | |
1168 | return ret; | |
1169 | } | |
1170 | ||
82460d97 DV |
1171 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1172 | { | |
1173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1174 | struct intel_engine_cs *ring; | |
1175 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1176 | int i, ret = 0; | |
1177 | ||
1178 | if (!USES_PPGTT(dev)) | |
1179 | return 0; | |
1180 | ||
1181 | if (IS_GEN6(dev)) | |
1182 | gen6_ppgtt_enable(dev); | |
1183 | else if (IS_GEN7(dev)) | |
1184 | gen7_ppgtt_enable(dev); | |
1185 | else if (INTEL_INFO(dev)->gen >= 8) | |
1186 | gen8_ppgtt_enable(dev); | |
1187 | else | |
1188 | WARN_ON(1); | |
1189 | ||
1190 | if (ppgtt) { | |
1191 | for_each_ring(ring, dev_priv, i) { | |
1192 | ret = ppgtt->switch_mm(ppgtt, ring, true); | |
1193 | if (ret != 0) | |
1194 | return ret; | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | return ret; | |
1199 | } | |
4d884705 DV |
1200 | struct i915_hw_ppgtt * |
1201 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1202 | { | |
1203 | struct i915_hw_ppgtt *ppgtt; | |
1204 | int ret; | |
1205 | ||
1206 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1207 | if (!ppgtt) | |
1208 | return ERR_PTR(-ENOMEM); | |
1209 | ||
1210 | ret = i915_ppgtt_init(dev, ppgtt); | |
1211 | if (ret) { | |
1212 | kfree(ppgtt); | |
1213 | return ERR_PTR(ret); | |
1214 | } | |
1215 | ||
1216 | ppgtt->file_priv = fpriv; | |
1217 | ||
1218 | return ppgtt; | |
1219 | } | |
1220 | ||
ee960be7 DV |
1221 | void i915_ppgtt_release(struct kref *kref) |
1222 | { | |
1223 | struct i915_hw_ppgtt *ppgtt = | |
1224 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1225 | ||
1226 | /* vmas should already be unbound */ | |
1227 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1228 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1229 | ||
19dd120c DV |
1230 | list_del(&ppgtt->base.global_link); |
1231 | drm_mm_takedown(&ppgtt->base.mm); | |
1232 | ||
ee960be7 DV |
1233 | ppgtt->base.cleanup(&ppgtt->base); |
1234 | kfree(ppgtt); | |
1235 | } | |
1236 | ||
7e0d96bc | 1237 | static void |
6f65e29a BW |
1238 | ppgtt_bind_vma(struct i915_vma *vma, |
1239 | enum i915_cache_level cache_level, | |
1240 | u32 flags) | |
1d2a314c | 1241 | { |
24f3a8cf AG |
1242 | /* Currently applicable only to VLV */ |
1243 | if (vma->obj->gt_ro) | |
1244 | flags |= PTE_READ_ONLY; | |
1245 | ||
782f1495 | 1246 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1247 | cache_level, flags); |
1d2a314c DV |
1248 | } |
1249 | ||
7e0d96bc | 1250 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1251 | { |
6f65e29a | 1252 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1253 | vma->node.start, |
1254 | vma->obj->base.size, | |
6f65e29a | 1255 | true); |
7bddb01f DV |
1256 | } |
1257 | ||
a81cc00c BW |
1258 | extern int intel_iommu_gfx_mapped; |
1259 | /* Certain Gen5 chipsets require require idling the GPU before | |
1260 | * unmapping anything from the GTT when VT-d is enabled. | |
1261 | */ | |
1262 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1263 | { | |
1264 | #ifdef CONFIG_INTEL_IOMMU | |
1265 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1266 | * was loaded first. | |
1267 | */ | |
1268 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1269 | return true; | |
1270 | #endif | |
1271 | return false; | |
1272 | } | |
1273 | ||
5c042287 BW |
1274 | static bool do_idling(struct drm_i915_private *dev_priv) |
1275 | { | |
1276 | bool ret = dev_priv->mm.interruptible; | |
1277 | ||
a81cc00c | 1278 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1279 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1280 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1281 | DRM_ERROR("Couldn't idle GPU\n"); |
1282 | /* Wait a bit, in hopes it avoids the hang */ | |
1283 | udelay(10); | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1291 | { | |
a81cc00c | 1292 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1293 | dev_priv->mm.interruptible = interruptible; |
1294 | } | |
1295 | ||
828c7908 BW |
1296 | void i915_check_and_clear_faults(struct drm_device *dev) |
1297 | { | |
1298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1299 | struct intel_engine_cs *ring; |
828c7908 BW |
1300 | int i; |
1301 | ||
1302 | if (INTEL_INFO(dev)->gen < 6) | |
1303 | return; | |
1304 | ||
1305 | for_each_ring(ring, dev_priv, i) { | |
1306 | u32 fault_reg; | |
1307 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1308 | if (fault_reg & RING_FAULT_VALID) { | |
1309 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1310 | "\tAddr: 0x%08lx\\n" | |
1311 | "\tAddress space: %s\n" | |
1312 | "\tSource ID: %d\n" | |
1313 | "\tType: %d\n", | |
1314 | fault_reg & PAGE_MASK, | |
1315 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1316 | RING_FAULT_SRCID(fault_reg), | |
1317 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1318 | I915_WRITE(RING_FAULT_REG(ring), | |
1319 | fault_reg & ~RING_FAULT_VALID); | |
1320 | } | |
1321 | } | |
1322 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1323 | } | |
1324 | ||
1325 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1326 | { | |
1327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1328 | ||
1329 | /* Don't bother messing with faults pre GEN6 as we have little | |
1330 | * documentation supporting that it's a good idea. | |
1331 | */ | |
1332 | if (INTEL_INFO(dev)->gen < 6) | |
1333 | return; | |
1334 | ||
1335 | i915_check_and_clear_faults(dev); | |
1336 | ||
1337 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1338 | dev_priv->gtt.base.start, |
1339 | dev_priv->gtt.base.total, | |
e568af1c | 1340 | true); |
828c7908 BW |
1341 | } |
1342 | ||
76aaf220 DV |
1343 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1344 | { | |
1345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1346 | struct drm_i915_gem_object *obj; |
80da2161 | 1347 | struct i915_address_space *vm; |
76aaf220 | 1348 | |
828c7908 BW |
1349 | i915_check_and_clear_faults(dev); |
1350 | ||
bee4a186 | 1351 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1352 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1353 | dev_priv->gtt.base.start, |
1354 | dev_priv->gtt.base.total, | |
828c7908 | 1355 | true); |
bee4a186 | 1356 | |
35c20a60 | 1357 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1358 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1359 | &dev_priv->gtt.base); | |
1360 | if (!vma) | |
1361 | continue; | |
1362 | ||
2c22569b | 1363 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1364 | /* The bind_vma code tries to be smart about tracking mappings. |
1365 | * Unfortunately above, we've just wiped out the mappings | |
1366 | * without telling our object about it. So we need to fake it. | |
1367 | */ | |
1368 | obj->has_global_gtt_mapping = 0; | |
1369 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1370 | } |
1371 | ||
80da2161 | 1372 | |
a2319c08 | 1373 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1374 | if (IS_CHERRYVIEW(dev)) |
1375 | chv_setup_private_ppat(dev_priv); | |
1376 | else | |
1377 | bdw_setup_private_ppat(dev_priv); | |
1378 | ||
80da2161 | 1379 | return; |
a2319c08 | 1380 | } |
80da2161 BW |
1381 | |
1382 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1383 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1384 | if (i915_is_ggtt(vm)) { | |
1385 | if (dev_priv->mm.aliasing_ppgtt) | |
1386 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1387 | continue; | |
1388 | } | |
1389 | ||
1390 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1391 | } |
1392 | ||
e76e9aeb | 1393 | i915_gem_chipset_flush(dev); |
76aaf220 | 1394 | } |
7c2e6fdf | 1395 | |
74163907 | 1396 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1397 | { |
9da3da66 | 1398 | if (obj->has_dma_mapping) |
74163907 | 1399 | return 0; |
9da3da66 CW |
1400 | |
1401 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1402 | obj->pages->sgl, obj->pages->nents, | |
1403 | PCI_DMA_BIDIRECTIONAL)) | |
1404 | return -ENOSPC; | |
1405 | ||
1406 | return 0; | |
7c2e6fdf DV |
1407 | } |
1408 | ||
94ec8f61 BW |
1409 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1410 | { | |
1411 | #ifdef writeq | |
1412 | writeq(pte, addr); | |
1413 | #else | |
1414 | iowrite32((u32)pte, addr); | |
1415 | iowrite32(pte >> 32, addr + 4); | |
1416 | #endif | |
1417 | } | |
1418 | ||
1419 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1420 | struct sg_table *st, | |
782f1495 | 1421 | uint64_t start, |
24f3a8cf | 1422 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1423 | { |
1424 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1425 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1426 | gen8_gtt_pte_t __iomem *gtt_entries = |
1427 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1428 | int i = 0; | |
1429 | struct sg_page_iter sg_iter; | |
57007df7 | 1430 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1431 | |
1432 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1433 | addr = sg_dma_address(sg_iter.sg) + | |
1434 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1435 | gen8_set_pte(>t_entries[i], | |
1436 | gen8_pte_encode(addr, level, true)); | |
1437 | i++; | |
1438 | } | |
1439 | ||
1440 | /* | |
1441 | * XXX: This serves as a posting read to make sure that the PTE has | |
1442 | * actually been updated. There is some concern that even though | |
1443 | * registers and PTEs are within the same BAR that they are potentially | |
1444 | * of NUMA access patterns. Therefore, even with the way we assume | |
1445 | * hardware should work, we must keep this posting read for paranoia. | |
1446 | */ | |
1447 | if (i != 0) | |
1448 | WARN_ON(readq(>t_entries[i-1]) | |
1449 | != gen8_pte_encode(addr, level, true)); | |
1450 | ||
94ec8f61 BW |
1451 | /* This next bit makes the above posting read even more important. We |
1452 | * want to flush the TLBs only after we're certain all the PTE updates | |
1453 | * have finished. | |
1454 | */ | |
1455 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1456 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1457 | } |
1458 | ||
e76e9aeb BW |
1459 | /* |
1460 | * Binds an object into the global gtt with the specified cache level. The object | |
1461 | * will be accessible to the GPU via commands whose operands reference offsets | |
1462 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1463 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1464 | */ | |
853ba5d2 | 1465 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1466 | struct sg_table *st, |
782f1495 | 1467 | uint64_t start, |
24f3a8cf | 1468 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1469 | { |
853ba5d2 | 1470 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1471 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1472 | gen6_gtt_pte_t __iomem *gtt_entries = |
1473 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1474 | int i = 0; |
1475 | struct sg_page_iter sg_iter; | |
57007df7 | 1476 | dma_addr_t addr = 0; |
e76e9aeb | 1477 | |
6e995e23 | 1478 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1479 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1480 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1481 | i++; |
e76e9aeb BW |
1482 | } |
1483 | ||
e76e9aeb BW |
1484 | /* XXX: This serves as a posting read to make sure that the PTE has |
1485 | * actually been updated. There is some concern that even though | |
1486 | * registers and PTEs are within the same BAR that they are potentially | |
1487 | * of NUMA access patterns. Therefore, even with the way we assume | |
1488 | * hardware should work, we must keep this posting read for paranoia. | |
1489 | */ | |
57007df7 PM |
1490 | if (i != 0) { |
1491 | unsigned long gtt = readl(>t_entries[i-1]); | |
1492 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1493 | } | |
0f9b91c7 BW |
1494 | |
1495 | /* This next bit makes the above posting read even more important. We | |
1496 | * want to flush the TLBs only after we're certain all the PTE updates | |
1497 | * have finished. | |
1498 | */ | |
1499 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1500 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1501 | } |
1502 | ||
94ec8f61 | 1503 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1504 | uint64_t start, |
1505 | uint64_t length, | |
94ec8f61 BW |
1506 | bool use_scratch) |
1507 | { | |
1508 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1509 | unsigned first_entry = start >> PAGE_SHIFT; |
1510 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1511 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1512 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1513 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1514 | int i; | |
1515 | ||
1516 | if (WARN(num_entries > max_entries, | |
1517 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1518 | first_entry, num_entries, max_entries)) | |
1519 | num_entries = max_entries; | |
1520 | ||
1521 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1522 | I915_CACHE_LLC, | |
1523 | use_scratch); | |
1524 | for (i = 0; i < num_entries; i++) | |
1525 | gen8_set_pte(>t_base[i], scratch_pte); | |
1526 | readl(gtt_base); | |
1527 | } | |
1528 | ||
853ba5d2 | 1529 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1530 | uint64_t start, |
1531 | uint64_t length, | |
828c7908 | 1532 | bool use_scratch) |
7faf1ab2 | 1533 | { |
853ba5d2 | 1534 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1535 | unsigned first_entry = start >> PAGE_SHIFT; |
1536 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1537 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1538 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1539 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1540 | int i; |
1541 | ||
1542 | if (WARN(num_entries > max_entries, | |
1543 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1544 | first_entry, num_entries, max_entries)) | |
1545 | num_entries = max_entries; | |
1546 | ||
24f3a8cf | 1547 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1548 | |
7faf1ab2 DV |
1549 | for (i = 0; i < num_entries; i++) |
1550 | iowrite32(scratch_pte, >t_base[i]); | |
1551 | readl(gtt_base); | |
1552 | } | |
1553 | ||
6f65e29a BW |
1554 | |
1555 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1556 | enum i915_cache_level cache_level, | |
1557 | u32 unused) | |
7faf1ab2 | 1558 | { |
6f65e29a | 1559 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1560 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1561 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1562 | ||
6f65e29a BW |
1563 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1564 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1565 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1566 | } |
1567 | ||
853ba5d2 | 1568 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1569 | uint64_t start, |
1570 | uint64_t length, | |
828c7908 | 1571 | bool unused) |
7faf1ab2 | 1572 | { |
782f1495 BW |
1573 | unsigned first_entry = start >> PAGE_SHIFT; |
1574 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1575 | intel_gtt_clear_range(first_entry, num_entries); |
1576 | } | |
1577 | ||
6f65e29a BW |
1578 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1579 | { | |
1580 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1581 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1582 | |
6f65e29a BW |
1583 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1584 | vma->obj->has_global_gtt_mapping = 0; | |
1585 | intel_gtt_clear_range(first, size); | |
1586 | } | |
7faf1ab2 | 1587 | |
6f65e29a BW |
1588 | static void ggtt_bind_vma(struct i915_vma *vma, |
1589 | enum i915_cache_level cache_level, | |
1590 | u32 flags) | |
d5bd1449 | 1591 | { |
6f65e29a | 1592 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1593 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1594 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1595 | |
24f3a8cf AG |
1596 | /* Currently applicable only to VLV */ |
1597 | if (obj->gt_ro) | |
1598 | flags |= PTE_READ_ONLY; | |
1599 | ||
6f65e29a BW |
1600 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1601 | * or we have a global mapping already but the cacheability flags have | |
1602 | * changed, set the global PTEs. | |
1603 | * | |
1604 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1605 | * instead if none of the above hold true. | |
1606 | * | |
1607 | * NB: A global mapping should only be needed for special regions like | |
1608 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1609 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1610 | */ | |
1611 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1612 | if (!obj->has_global_gtt_mapping || | |
1613 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1614 | vma->vm->insert_entries(vma->vm, obj->pages, |
1615 | vma->node.start, | |
24f3a8cf | 1616 | cache_level, flags); |
6f65e29a BW |
1617 | obj->has_global_gtt_mapping = 1; |
1618 | } | |
1619 | } | |
d5bd1449 | 1620 | |
6f65e29a BW |
1621 | if (dev_priv->mm.aliasing_ppgtt && |
1622 | (!obj->has_aliasing_ppgtt_mapping || | |
1623 | (cache_level != obj->cache_level))) { | |
1624 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1625 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1626 | vma->obj->pages, |
1627 | vma->node.start, | |
24f3a8cf | 1628 | cache_level, flags); |
6f65e29a BW |
1629 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1630 | } | |
d5bd1449 CW |
1631 | } |
1632 | ||
6f65e29a | 1633 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1634 | { |
6f65e29a | 1635 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1636 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1637 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1638 | |
1639 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1640 | vma->vm->clear_range(vma->vm, |
1641 | vma->node.start, | |
1642 | obj->base.size, | |
6f65e29a BW |
1643 | true); |
1644 | obj->has_global_gtt_mapping = 0; | |
1645 | } | |
74898d7e | 1646 | |
6f65e29a BW |
1647 | if (obj->has_aliasing_ppgtt_mapping) { |
1648 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1649 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1650 | vma->node.start, |
1651 | obj->base.size, | |
6f65e29a BW |
1652 | true); |
1653 | obj->has_aliasing_ppgtt_mapping = 0; | |
1654 | } | |
74163907 DV |
1655 | } |
1656 | ||
1657 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1658 | { |
5c042287 BW |
1659 | struct drm_device *dev = obj->base.dev; |
1660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1661 | bool interruptible; | |
1662 | ||
1663 | interruptible = do_idling(dev_priv); | |
1664 | ||
9da3da66 CW |
1665 | if (!obj->has_dma_mapping) |
1666 | dma_unmap_sg(&dev->pdev->dev, | |
1667 | obj->pages->sgl, obj->pages->nents, | |
1668 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1669 | |
1670 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1671 | } |
644ec02b | 1672 | |
42d6ab48 CW |
1673 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1674 | unsigned long color, | |
1675 | unsigned long *start, | |
1676 | unsigned long *end) | |
1677 | { | |
1678 | if (node->color != color) | |
1679 | *start += 4096; | |
1680 | ||
1681 | if (!list_empty(&node->node_list)) { | |
1682 | node = list_entry(node->node_list.next, | |
1683 | struct drm_mm_node, | |
1684 | node_list); | |
1685 | if (node->allocated && node->color != color) | |
1686 | *end -= 4096; | |
1687 | } | |
1688 | } | |
fbe5d36e | 1689 | |
6c5566a8 DV |
1690 | int i915_gem_setup_global_gtt(struct drm_device *dev, |
1691 | unsigned long start, | |
1692 | unsigned long mappable_end, | |
1693 | unsigned long end) | |
644ec02b | 1694 | { |
e78891ca BW |
1695 | /* Let GEM Manage all of the aperture. |
1696 | * | |
1697 | * However, leave one page at the end still bound to the scratch page. | |
1698 | * There are a number of places where the hardware apparently prefetches | |
1699 | * past the end of the object, and we've seen multiple hangs with the | |
1700 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1701 | * aperture. One page should be enough to keep any prefetching inside | |
1702 | * of the aperture. | |
1703 | */ | |
40d74980 BW |
1704 | struct drm_i915_private *dev_priv = dev->dev_private; |
1705 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1706 | struct drm_mm_node *entry; |
1707 | struct drm_i915_gem_object *obj; | |
1708 | unsigned long hole_start, hole_end; | |
fa76da34 | 1709 | int ret; |
644ec02b | 1710 | |
35451cb6 BW |
1711 | BUG_ON(mappable_end > end); |
1712 | ||
ed2f3452 | 1713 | /* Subtract the guard page ... */ |
40d74980 | 1714 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1715 | if (!HAS_LLC(dev)) |
93bd8649 | 1716 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1717 | |
ed2f3452 | 1718 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1719 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1720 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1721 | |
edd41a87 | 1722 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1723 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1724 | ||
1725 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1726 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1727 | if (ret) { |
1728 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1729 | return ret; | |
1730 | } | |
ed2f3452 CW |
1731 | obj->has_global_gtt_mapping = 1; |
1732 | } | |
1733 | ||
853ba5d2 BW |
1734 | dev_priv->gtt.base.start = start; |
1735 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1736 | |
ed2f3452 | 1737 | /* Clear any non-preallocated blocks */ |
40d74980 | 1738 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1739 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1740 | hole_start, hole_end); | |
782f1495 BW |
1741 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1742 | hole_end - hole_start, true); | |
ed2f3452 CW |
1743 | } |
1744 | ||
1745 | /* And finally clear the reserved guard page */ | |
782f1495 | 1746 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1747 | |
fa76da34 DV |
1748 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1749 | struct i915_hw_ppgtt *ppgtt; | |
1750 | ||
1751 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1752 | if (!ppgtt) | |
1753 | return -ENOMEM; | |
1754 | ||
1755 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1756 | if (ret != 0) | |
1757 | return ret; | |
1758 | ||
1759 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1760 | } | |
1761 | ||
6c5566a8 | 1762 | return 0; |
e76e9aeb BW |
1763 | } |
1764 | ||
d7e5008f BW |
1765 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1766 | { | |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1769 | |
853ba5d2 | 1770 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1771 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1772 | |
e78891ca | 1773 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1774 | } |
1775 | ||
90d0a0e8 DV |
1776 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1777 | { | |
1778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1779 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
1780 | ||
70e32544 DV |
1781 | if (dev_priv->mm.aliasing_ppgtt) { |
1782 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1783 | ||
1784 | ppgtt->base.cleanup(&ppgtt->base); | |
1785 | } | |
1786 | ||
90d0a0e8 DV |
1787 | if (drm_mm_initialized(&vm->mm)) { |
1788 | drm_mm_takedown(&vm->mm); | |
1789 | list_del(&vm->global_link); | |
1790 | } | |
1791 | ||
1792 | vm->cleanup(vm); | |
1793 | } | |
70e32544 | 1794 | |
e76e9aeb BW |
1795 | static int setup_scratch_page(struct drm_device *dev) |
1796 | { | |
1797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1798 | struct page *page; | |
1799 | dma_addr_t dma_addr; | |
1800 | ||
1801 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1802 | if (page == NULL) | |
1803 | return -ENOMEM; | |
1804 | get_page(page); | |
1805 | set_pages_uc(page, 1); | |
1806 | ||
1807 | #ifdef CONFIG_INTEL_IOMMU | |
1808 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1809 | PCI_DMA_BIDIRECTIONAL); | |
1810 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1811 | return -EINVAL; | |
1812 | #else | |
1813 | dma_addr = page_to_phys(page); | |
1814 | #endif | |
853ba5d2 BW |
1815 | dev_priv->gtt.base.scratch.page = page; |
1816 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1817 | |
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | static void teardown_scratch_page(struct drm_device *dev) | |
1822 | { | |
1823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1824 | struct page *page = dev_priv->gtt.base.scratch.page; |
1825 | ||
1826 | set_pages_wb(page, 1); | |
1827 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1828 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1829 | put_page(page); |
1830 | __free_page(page); | |
e76e9aeb BW |
1831 | } |
1832 | ||
1833 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1834 | { | |
1835 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1836 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1837 | return snb_gmch_ctl << 20; | |
1838 | } | |
1839 | ||
9459d252 BW |
1840 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1841 | { | |
1842 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1843 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1844 | if (bdw_gmch_ctl) | |
1845 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1846 | |
1847 | #ifdef CONFIG_X86_32 | |
1848 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1849 | if (bdw_gmch_ctl > 4) | |
1850 | bdw_gmch_ctl = 4; | |
1851 | #endif | |
1852 | ||
9459d252 BW |
1853 | return bdw_gmch_ctl << 20; |
1854 | } | |
1855 | ||
d7f25f23 DL |
1856 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1857 | { | |
1858 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1859 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1860 | ||
1861 | if (gmch_ctrl) | |
1862 | return 1 << (20 + gmch_ctrl); | |
1863 | ||
1864 | return 0; | |
1865 | } | |
1866 | ||
baa09f5f | 1867 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1868 | { |
1869 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1870 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1871 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1872 | } | |
1873 | ||
9459d252 BW |
1874 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1875 | { | |
1876 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1877 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1878 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1879 | } | |
1880 | ||
d7f25f23 DL |
1881 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1882 | { | |
1883 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1884 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1885 | ||
1886 | /* | |
1887 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1888 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1889 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1890 | */ | |
1891 | if (gmch_ctrl < 0x11) | |
1892 | return gmch_ctrl << 25; | |
1893 | else if (gmch_ctrl < 0x17) | |
1894 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1895 | else | |
1896 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1897 | } | |
1898 | ||
63340133 BW |
1899 | static int ggtt_probe_common(struct drm_device *dev, |
1900 | size_t gtt_size) | |
1901 | { | |
1902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1903 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1904 | int ret; |
1905 | ||
1906 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1907 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1908 | (pci_resource_len(dev->pdev, 0) / 2); |
1909 | ||
21c34607 | 1910 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1911 | if (!dev_priv->gtt.gsm) { |
1912 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1913 | return -ENOMEM; | |
1914 | } | |
1915 | ||
1916 | ret = setup_scratch_page(dev); | |
1917 | if (ret) { | |
1918 | DRM_ERROR("Scratch setup failed\n"); | |
1919 | /* iounmap will also get called at remove, but meh */ | |
1920 | iounmap(dev_priv->gtt.gsm); | |
1921 | } | |
1922 | ||
1923 | return ret; | |
1924 | } | |
1925 | ||
fbe5d36e BW |
1926 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1927 | * bits. When using advanced contexts each context stores its own PAT, but | |
1928 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1929 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1930 | { |
fbe5d36e BW |
1931 | uint64_t pat; |
1932 | ||
1933 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1934 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1935 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1936 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1937 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1938 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1939 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1940 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1941 | ||
1942 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1943 | * write would work. */ | |
1944 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1945 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1946 | } | |
1947 | ||
ee0ce478 VS |
1948 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1949 | { | |
1950 | uint64_t pat; | |
1951 | ||
1952 | /* | |
1953 | * Map WB on BDW to snooped on CHV. | |
1954 | * | |
1955 | * Only the snoop bit has meaning for CHV, the rest is | |
1956 | * ignored. | |
1957 | * | |
1958 | * Note that the harware enforces snooping for all page | |
1959 | * table accesses. The snoop bit is actually ignored for | |
1960 | * PDEs. | |
1961 | */ | |
1962 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1963 | GEN8_PPAT(1, 0) | | |
1964 | GEN8_PPAT(2, 0) | | |
1965 | GEN8_PPAT(3, 0) | | |
1966 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1967 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1968 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1969 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1970 | ||
1971 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1972 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1973 | } | |
1974 | ||
63340133 BW |
1975 | static int gen8_gmch_probe(struct drm_device *dev, |
1976 | size_t *gtt_total, | |
1977 | size_t *stolen, | |
1978 | phys_addr_t *mappable_base, | |
1979 | unsigned long *mappable_end) | |
1980 | { | |
1981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1982 | unsigned int gtt_size; | |
1983 | u16 snb_gmch_ctl; | |
1984 | int ret; | |
1985 | ||
1986 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1987 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1988 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1989 | ||
1990 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1991 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1992 | ||
1993 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1994 | ||
d7f25f23 DL |
1995 | if (IS_CHERRYVIEW(dev)) { |
1996 | *stolen = chv_get_stolen_size(snb_gmch_ctl); | |
1997 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
1998 | } else { | |
1999 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2000 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2001 | } | |
63340133 | 2002 | |
d31eb10e | 2003 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 2004 | |
ee0ce478 VS |
2005 | if (IS_CHERRYVIEW(dev)) |
2006 | chv_setup_private_ppat(dev_priv); | |
2007 | else | |
2008 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2009 | |
63340133 BW |
2010 | ret = ggtt_probe_common(dev, gtt_size); |
2011 | ||
94ec8f61 BW |
2012 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2013 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2014 | |
2015 | return ret; | |
2016 | } | |
2017 | ||
baa09f5f BW |
2018 | static int gen6_gmch_probe(struct drm_device *dev, |
2019 | size_t *gtt_total, | |
41907ddc BW |
2020 | size_t *stolen, |
2021 | phys_addr_t *mappable_base, | |
2022 | unsigned long *mappable_end) | |
e76e9aeb BW |
2023 | { |
2024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2025 | unsigned int gtt_size; |
e76e9aeb | 2026 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2027 | int ret; |
2028 | ||
41907ddc BW |
2029 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2030 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2031 | ||
baa09f5f BW |
2032 | /* 64/512MB is the current min/max we actually know of, but this is just |
2033 | * a coarse sanity check. | |
e76e9aeb | 2034 | */ |
41907ddc | 2035 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2036 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2037 | dev_priv->gtt.mappable_end); | |
2038 | return -ENXIO; | |
e76e9aeb BW |
2039 | } |
2040 | ||
e76e9aeb BW |
2041 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2042 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2043 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2044 | |
c4ae25ec | 2045 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2046 | |
63340133 BW |
2047 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2048 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2049 | |
63340133 | 2050 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2051 | |
853ba5d2 BW |
2052 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2053 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2054 | |
e76e9aeb BW |
2055 | return ret; |
2056 | } | |
2057 | ||
853ba5d2 | 2058 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2059 | { |
853ba5d2 BW |
2060 | |
2061 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2062 | |
853ba5d2 BW |
2063 | iounmap(gtt->gsm); |
2064 | teardown_scratch_page(vm->dev); | |
644ec02b | 2065 | } |
baa09f5f BW |
2066 | |
2067 | static int i915_gmch_probe(struct drm_device *dev, | |
2068 | size_t *gtt_total, | |
41907ddc BW |
2069 | size_t *stolen, |
2070 | phys_addr_t *mappable_base, | |
2071 | unsigned long *mappable_end) | |
baa09f5f BW |
2072 | { |
2073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2074 | int ret; | |
2075 | ||
baa09f5f BW |
2076 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2077 | if (!ret) { | |
2078 | DRM_ERROR("failed to set up gmch\n"); | |
2079 | return -EIO; | |
2080 | } | |
2081 | ||
41907ddc | 2082 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2083 | |
2084 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2085 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2086 | |
c0a7f818 CW |
2087 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2088 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2089 | ||
baa09f5f BW |
2090 | return 0; |
2091 | } | |
2092 | ||
853ba5d2 | 2093 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2094 | { |
2095 | intel_gmch_remove(); | |
2096 | } | |
2097 | ||
2098 | int i915_gem_gtt_init(struct drm_device *dev) | |
2099 | { | |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2101 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2102 | int ret; |
2103 | ||
baa09f5f | 2104 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2105 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2106 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2107 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2108 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2109 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2110 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2111 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2112 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2113 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2114 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2115 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2116 | else if (INTEL_INFO(dev)->gen >= 7) |
2117 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2118 | else |
350ec881 | 2119 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2120 | } else { |
2121 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2122 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2123 | } |
2124 | ||
853ba5d2 | 2125 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2126 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2127 | if (ret) |
baa09f5f | 2128 | return ret; |
baa09f5f | 2129 | |
853ba5d2 BW |
2130 | gtt->base.dev = dev; |
2131 | ||
baa09f5f | 2132 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2133 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2134 | gtt->base.total >> 20); | |
b2f21b4d BW |
2135 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2136 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2137 | #ifdef CONFIG_INTEL_IOMMU |
2138 | if (intel_iommu_gfx_mapped) | |
2139 | DRM_INFO("VT-d active for gfx access\n"); | |
2140 | #endif | |
cfa7c862 DV |
2141 | /* |
2142 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2143 | * user's requested state against the hardware/driver capabilities. We | |
2144 | * do this now so that we can print out any log messages once rather | |
2145 | * than every time we check intel_enable_ppgtt(). | |
2146 | */ | |
2147 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2148 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2149 | |
2150 | return 0; | |
2151 | } | |
6f65e29a BW |
2152 | |
2153 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2154 | struct i915_address_space *vm) | |
2155 | { | |
2156 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2157 | if (vma == NULL) | |
2158 | return ERR_PTR(-ENOMEM); | |
2159 | ||
2160 | INIT_LIST_HEAD(&vma->vma_link); | |
2161 | INIT_LIST_HEAD(&vma->mm_list); | |
2162 | INIT_LIST_HEAD(&vma->exec_list); | |
2163 | vma->vm = vm; | |
2164 | vma->obj = obj; | |
2165 | ||
2166 | switch (INTEL_INFO(vm->dev)->gen) { | |
2167 | case 8: | |
2168 | case 7: | |
2169 | case 6: | |
7e0d96bc BW |
2170 | if (i915_is_ggtt(vm)) { |
2171 | vma->unbind_vma = ggtt_unbind_vma; | |
2172 | vma->bind_vma = ggtt_bind_vma; | |
2173 | } else { | |
2174 | vma->unbind_vma = ppgtt_unbind_vma; | |
2175 | vma->bind_vma = ppgtt_bind_vma; | |
2176 | } | |
6f65e29a BW |
2177 | break; |
2178 | case 5: | |
2179 | case 4: | |
2180 | case 3: | |
2181 | case 2: | |
2182 | BUG_ON(!i915_is_ggtt(vm)); | |
2183 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2184 | vma->bind_vma = i915_ggtt_bind_vma; | |
2185 | break; | |
2186 | default: | |
2187 | BUG(); | |
2188 | } | |
2189 | ||
2190 | /* Keep GGTT vmas first to make debug easier */ | |
2191 | if (i915_is_ggtt(vm)) | |
2192 | list_add(&vma->vma_link, &obj->vma_list); | |
2193 | else | |
2194 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2195 | ||
2196 | return vma; | |
2197 | } | |
2198 | ||
2199 | struct i915_vma * | |
2200 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2201 | struct i915_address_space *vm) | |
2202 | { | |
2203 | struct i915_vma *vma; | |
2204 | ||
2205 | vma = i915_gem_obj_to_vma(obj, vm); | |
2206 | if (!vma) | |
2207 | vma = __i915_gem_vma_create(obj, vm); | |
2208 | ||
841cd773 DV |
2209 | if (!i915_is_ggtt(vm)) |
2210 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 2211 | |
6f65e29a BW |
2212 | return vma; |
2213 | } |