Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
93a25a9e DV |
36 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) |
37 | { | |
cfa7c862 | 38 | if (i915.enable_ppgtt == 0) |
93a25a9e DV |
39 | return false; |
40 | ||
41 | if (i915.enable_ppgtt == 1 && full) | |
42 | return false; | |
43 | ||
cfa7c862 DV |
44 | return true; |
45 | } | |
46 | ||
47 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) | |
48 | { | |
49 | if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
50 | return 0; | |
51 | ||
52 | if (enable_ppgtt == 1) | |
53 | return 1; | |
54 | ||
55 | if (enable_ppgtt == 2 && HAS_PPGTT(dev)) | |
56 | return 2; | |
57 | ||
93a25a9e DV |
58 | #ifdef CONFIG_INTEL_IOMMU |
59 | /* Disable ppgtt on SNB if VT-d is on. */ | |
60 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
61 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 62 | return 0; |
93a25a9e DV |
63 | } |
64 | #endif | |
65 | ||
62942ed7 JB |
66 | /* Early VLV doesn't have this */ |
67 | if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) { | |
68 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); | |
69 | return 0; | |
70 | } | |
71 | ||
cfa7c862 | 72 | return HAS_ALIASING_PPGTT(dev) ? 1 : 0; |
93a25a9e DV |
73 | } |
74 | ||
fbe5d36e | 75 | |
6f65e29a BW |
76 | static void ppgtt_bind_vma(struct i915_vma *vma, |
77 | enum i915_cache_level cache_level, | |
78 | u32 flags); | |
79 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 80 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 81 | |
94ec8f61 BW |
82 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
83 | enum i915_cache_level level, | |
84 | bool valid) | |
85 | { | |
86 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
87 | pte |= addr; | |
63c42e56 BW |
88 | |
89 | switch (level) { | |
90 | case I915_CACHE_NONE: | |
fbe5d36e | 91 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
92 | break; |
93 | case I915_CACHE_WT: | |
94 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
95 | break; | |
96 | default: | |
97 | pte |= PPAT_CACHED_INDEX; | |
98 | break; | |
99 | } | |
100 | ||
94ec8f61 BW |
101 | return pte; |
102 | } | |
103 | ||
b1fe6673 BW |
104 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
105 | dma_addr_t addr, | |
106 | enum i915_cache_level level) | |
107 | { | |
108 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
109 | pde |= addr; | |
110 | if (level != I915_CACHE_NONE) | |
111 | pde |= PPAT_CACHED_PDE_INDEX; | |
112 | else | |
113 | pde |= PPAT_UNCACHED_INDEX; | |
114 | return pde; | |
115 | } | |
116 | ||
350ec881 | 117 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
118 | enum i915_cache_level level, |
119 | bool valid) | |
54d12527 | 120 | { |
b35b380e | 121 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 122 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
123 | |
124 | switch (level) { | |
350ec881 CW |
125 | case I915_CACHE_L3_LLC: |
126 | case I915_CACHE_LLC: | |
127 | pte |= GEN6_PTE_CACHE_LLC; | |
128 | break; | |
129 | case I915_CACHE_NONE: | |
130 | pte |= GEN6_PTE_UNCACHED; | |
131 | break; | |
132 | default: | |
133 | WARN_ON(1); | |
134 | } | |
135 | ||
136 | return pte; | |
137 | } | |
138 | ||
139 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
140 | enum i915_cache_level level, |
141 | bool valid) | |
350ec881 | 142 | { |
b35b380e | 143 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
144 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
145 | ||
146 | switch (level) { | |
147 | case I915_CACHE_L3_LLC: | |
148 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
149 | break; |
150 | case I915_CACHE_LLC: | |
151 | pte |= GEN6_PTE_CACHE_LLC; | |
152 | break; | |
153 | case I915_CACHE_NONE: | |
9119708c | 154 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
155 | break; |
156 | default: | |
350ec881 | 157 | WARN_ON(1); |
e7210c3c BW |
158 | } |
159 | ||
54d12527 BW |
160 | return pte; |
161 | } | |
162 | ||
80a74f7f | 163 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
164 | enum i915_cache_level level, |
165 | bool valid) | |
93c34e70 | 166 | { |
b35b380e | 167 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
168 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
169 | ||
170 | /* Mark the page as writeable. Other platforms don't have a | |
171 | * setting for read-only/writable, so this matches that behavior. | |
172 | */ | |
173 | pte |= BYT_PTE_WRITEABLE; | |
174 | ||
175 | if (level != I915_CACHE_NONE) | |
176 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
177 | ||
178 | return pte; | |
179 | } | |
180 | ||
80a74f7f | 181 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
182 | enum i915_cache_level level, |
183 | bool valid) | |
9119708c | 184 | { |
b35b380e | 185 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 186 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
187 | |
188 | if (level != I915_CACHE_NONE) | |
87a6b688 | 189 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
190 | |
191 | return pte; | |
192 | } | |
193 | ||
4d15c145 | 194 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
195 | enum i915_cache_level level, |
196 | bool valid) | |
4d15c145 | 197 | { |
b35b380e | 198 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
199 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
200 | ||
651d794f CW |
201 | switch (level) { |
202 | case I915_CACHE_NONE: | |
203 | break; | |
204 | case I915_CACHE_WT: | |
c51e9701 | 205 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
206 | break; |
207 | default: | |
c51e9701 | 208 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
209 | break; |
210 | } | |
4d15c145 BW |
211 | |
212 | return pte; | |
213 | } | |
214 | ||
94e409c1 | 215 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 216 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
e178f705 | 217 | uint64_t val, bool synchronous) |
94e409c1 | 218 | { |
e178f705 | 219 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
220 | int ret; |
221 | ||
222 | BUG_ON(entry >= 4); | |
223 | ||
e178f705 BW |
224 | if (synchronous) { |
225 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
226 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
227 | return 0; | |
228 | } | |
229 | ||
94e409c1 BW |
230 | ret = intel_ring_begin(ring, 6); |
231 | if (ret) | |
232 | return ret; | |
233 | ||
234 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
235 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
236 | intel_ring_emit(ring, (u32)(val >> 32)); | |
237 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
238 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
239 | intel_ring_emit(ring, (u32)(val)); | |
240 | intel_ring_advance(ring); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
eeb9488e | 245 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 246 | struct intel_engine_cs *ring, |
eeb9488e | 247 | bool synchronous) |
94e409c1 | 248 | { |
eeb9488e | 249 | int i, ret; |
94e409c1 BW |
250 | |
251 | /* bit of a hack to find the actual last used pd */ | |
252 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
253 | ||
94e409c1 BW |
254 | for (i = used_pd - 1; i >= 0; i--) { |
255 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
256 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
257 | if (ret) | |
258 | return ret; | |
94e409c1 | 259 | } |
d595bd4b | 260 | |
eeb9488e | 261 | return 0; |
94e409c1 BW |
262 | } |
263 | ||
459108b8 | 264 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
265 | uint64_t start, |
266 | uint64_t length, | |
459108b8 BW |
267 | bool use_scratch) |
268 | { | |
269 | struct i915_hw_ppgtt *ppgtt = | |
270 | container_of(vm, struct i915_hw_ppgtt, base); | |
271 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
272 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
273 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
274 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 275 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
276 | unsigned last_pte, i; |
277 | ||
278 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
279 | I915_CACHE_LLC, use_scratch); | |
280 | ||
281 | while (num_entries) { | |
7ad47cf2 | 282 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 283 | |
7ad47cf2 | 284 | last_pte = pte + num_entries; |
459108b8 BW |
285 | if (last_pte > GEN8_PTES_PER_PAGE) |
286 | last_pte = GEN8_PTES_PER_PAGE; | |
287 | ||
288 | pt_vaddr = kmap_atomic(page_table); | |
289 | ||
7ad47cf2 | 290 | for (i = pte; i < last_pte; i++) { |
459108b8 | 291 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
292 | num_entries--; |
293 | } | |
459108b8 | 294 | |
fd1ab8f4 RB |
295 | if (!HAS_LLC(ppgtt->base.dev)) |
296 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
297 | kunmap_atomic(pt_vaddr); |
298 | ||
7ad47cf2 BW |
299 | pte = 0; |
300 | if (++pde == GEN8_PDES_PER_PAGE) { | |
301 | pdpe++; | |
302 | pde = 0; | |
303 | } | |
459108b8 BW |
304 | } |
305 | } | |
306 | ||
9df15b49 BW |
307 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
308 | struct sg_table *pages, | |
782f1495 | 309 | uint64_t start, |
9df15b49 BW |
310 | enum i915_cache_level cache_level) |
311 | { | |
312 | struct i915_hw_ppgtt *ppgtt = | |
313 | container_of(vm, struct i915_hw_ppgtt, base); | |
314 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
315 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
316 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
317 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
318 | struct sg_page_iter sg_iter; |
319 | ||
6f1cc993 | 320 | pt_vaddr = NULL; |
7ad47cf2 | 321 | |
9df15b49 | 322 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
323 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
324 | break; | |
325 | ||
6f1cc993 | 326 | if (pt_vaddr == NULL) |
7ad47cf2 | 327 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 328 | |
7ad47cf2 | 329 | pt_vaddr[pte] = |
6f1cc993 CW |
330 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
331 | cache_level, true); | |
7ad47cf2 | 332 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
333 | if (!HAS_LLC(ppgtt->base.dev)) |
334 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 335 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 336 | pt_vaddr = NULL; |
7ad47cf2 BW |
337 | if (++pde == GEN8_PDES_PER_PAGE) { |
338 | pdpe++; | |
339 | pde = 0; | |
340 | } | |
341 | pte = 0; | |
9df15b49 BW |
342 | } |
343 | } | |
fd1ab8f4 RB |
344 | if (pt_vaddr) { |
345 | if (!HAS_LLC(ppgtt->base.dev)) | |
346 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 347 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 348 | } |
9df15b49 BW |
349 | } |
350 | ||
7ad47cf2 BW |
351 | static void gen8_free_page_tables(struct page **pt_pages) |
352 | { | |
353 | int i; | |
354 | ||
355 | if (pt_pages == NULL) | |
356 | return; | |
357 | ||
358 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
359 | if (pt_pages[i]) | |
360 | __free_pages(pt_pages[i], 0); | |
361 | } | |
362 | ||
363 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
364 | { |
365 | int i; | |
366 | ||
7ad47cf2 BW |
367 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
368 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
369 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 370 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 371 | } |
b45a6715 | 372 | |
b45a6715 BW |
373 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
374 | } | |
375 | ||
376 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
377 | { | |
f3a964b9 | 378 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
379 | int i, j; |
380 | ||
381 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
382 | /* TODO: In the future we'll support sparse mappings, so this | |
383 | * will have to change. */ | |
384 | if (!ppgtt->pd_dma_addr[i]) | |
385 | continue; | |
386 | ||
f3a964b9 BW |
387 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
388 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
389 | |
390 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
391 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
392 | if (addr) | |
f3a964b9 BW |
393 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
394 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
395 | } |
396 | } | |
397 | } | |
398 | ||
37aca44a BW |
399 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
400 | { | |
401 | struct i915_hw_ppgtt *ppgtt = | |
402 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 403 | |
7e0d96bc | 404 | list_del(&vm->global_link); |
686e1f6f BW |
405 | drm_mm_takedown(&vm->mm); |
406 | ||
b45a6715 BW |
407 | gen8_ppgtt_unmap_pages(ppgtt); |
408 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
409 | } |
410 | ||
7ad47cf2 BW |
411 | static struct page **__gen8_alloc_page_tables(void) |
412 | { | |
413 | struct page **pt_pages; | |
414 | int i; | |
415 | ||
416 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
417 | if (!pt_pages) | |
418 | return ERR_PTR(-ENOMEM); | |
419 | ||
420 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
421 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
422 | if (!pt_pages[i]) | |
423 | goto bail; | |
424 | } | |
425 | ||
426 | return pt_pages; | |
427 | ||
428 | bail: | |
429 | gen8_free_page_tables(pt_pages); | |
430 | kfree(pt_pages); | |
431 | return ERR_PTR(-ENOMEM); | |
432 | } | |
433 | ||
bf2b4ed2 BW |
434 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
435 | const int max_pdp) | |
436 | { | |
7ad47cf2 | 437 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 438 | int i, ret; |
bf2b4ed2 | 439 | |
7ad47cf2 BW |
440 | for (i = 0; i < max_pdp; i++) { |
441 | pt_pages[i] = __gen8_alloc_page_tables(); | |
442 | if (IS_ERR(pt_pages[i])) { | |
443 | ret = PTR_ERR(pt_pages[i]); | |
444 | goto unwind_out; | |
445 | } | |
446 | } | |
447 | ||
448 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
449 | * "atomic" - for cleanup purposes. | |
450 | */ | |
451 | for (i = 0; i < max_pdp; i++) | |
452 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 453 | |
bf2b4ed2 | 454 | return 0; |
7ad47cf2 BW |
455 | |
456 | unwind_out: | |
457 | while (i--) { | |
458 | gen8_free_page_tables(pt_pages[i]); | |
459 | kfree(pt_pages[i]); | |
460 | } | |
461 | ||
462 | return ret; | |
bf2b4ed2 BW |
463 | } |
464 | ||
465 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
466 | { | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
470 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
471 | sizeof(dma_addr_t), | |
472 | GFP_KERNEL); | |
473 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
474 | return -ENOMEM; | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
481 | const int max_pdp) | |
482 | { | |
483 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
484 | if (!ppgtt->pd_pages) | |
485 | return -ENOMEM; | |
486 | ||
487 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
488 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
494 | const int max_pdp) | |
495 | { | |
496 | int ret; | |
497 | ||
498 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
499 | if (ret) | |
500 | return ret; | |
501 | ||
502 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
503 | if (ret) { | |
504 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
505 | return ret; | |
506 | } | |
507 | ||
508 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
509 | ||
510 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
511 | if (ret) | |
512 | gen8_ppgtt_free(ppgtt); | |
513 | ||
514 | return ret; | |
515 | } | |
516 | ||
517 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
518 | const int pd) | |
519 | { | |
520 | dma_addr_t pd_addr; | |
521 | int ret; | |
522 | ||
523 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
524 | &ppgtt->pd_pages[pd], 0, | |
525 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
526 | ||
527 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
528 | if (ret) | |
529 | return ret; | |
530 | ||
531 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
537 | const int pd, | |
538 | const int pt) | |
539 | { | |
540 | dma_addr_t pt_addr; | |
541 | struct page *p; | |
542 | int ret; | |
543 | ||
7ad47cf2 | 544 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
545 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
546 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
547 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
548 | if (ret) | |
549 | return ret; | |
550 | ||
551 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
37aca44a | 556 | /** |
f3a964b9 BW |
557 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
558 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
559 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
560 | * space. | |
37aca44a | 561 | * |
f3a964b9 BW |
562 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
563 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 564 | * TODO: Do something with the size parameter |
f3a964b9 | 565 | */ |
37aca44a BW |
566 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
567 | { | |
37aca44a | 568 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 569 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 570 | int i, j, ret; |
37aca44a BW |
571 | |
572 | if (size % (1<<30)) | |
573 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
574 | ||
bf2b4ed2 BW |
575 | /* 1. Do all our allocations for page directories and page tables. */ |
576 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
577 | if (ret) | |
578 | return ret; | |
f3a964b9 | 579 | |
37aca44a | 580 | /* |
bf2b4ed2 | 581 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
582 | */ |
583 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 584 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
585 | if (ret) |
586 | goto bail; | |
37aca44a | 587 | |
37aca44a | 588 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 589 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
590 | if (ret) |
591 | goto bail; | |
37aca44a BW |
592 | } |
593 | } | |
594 | ||
f3a964b9 BW |
595 | /* |
596 | * 3. Map all the page directory entires to point to the page tables | |
597 | * we've allocated. | |
598 | * | |
599 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 600 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
601 | * will never need to touch the PDEs again. |
602 | */ | |
b1fe6673 BW |
603 | for (i = 0; i < max_pdp; i++) { |
604 | gen8_ppgtt_pde_t *pd_vaddr; | |
605 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
606 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
607 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
608 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
609 | I915_CACHE_LLC); | |
610 | } | |
fd1ab8f4 RB |
611 | if (!HAS_LLC(ppgtt->base.dev)) |
612 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
613 | kunmap_atomic(pd_vaddr); |
614 | } | |
615 | ||
f3a964b9 BW |
616 | ppgtt->enable = gen8_ppgtt_enable; |
617 | ppgtt->switch_mm = gen8_mm_switch; | |
618 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
619 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
620 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
621 | ppgtt->base.start = 0; | |
5abbcca3 | 622 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 623 | |
5abbcca3 | 624 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 625 | |
37aca44a BW |
626 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
627 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
628 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
629 | ppgtt->num_pd_entries, |
630 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 631 | return 0; |
37aca44a | 632 | |
f3a964b9 BW |
633 | bail: |
634 | gen8_ppgtt_unmap_pages(ppgtt); | |
635 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
636 | return ret; |
637 | } | |
638 | ||
87d60b63 BW |
639 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
640 | { | |
641 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
642 | struct i915_address_space *vm = &ppgtt->base; | |
643 | gen6_gtt_pte_t __iomem *pd_addr; | |
644 | gen6_gtt_pte_t scratch_pte; | |
645 | uint32_t pd_entry; | |
646 | int pte, pde; | |
647 | ||
648 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
649 | ||
650 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
651 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
652 | ||
653 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
654 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
655 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
656 | u32 expected; | |
657 | gen6_gtt_pte_t *pt_vaddr; | |
658 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
659 | pd_entry = readl(pd_addr + pde); | |
660 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
661 | ||
662 | if (pd_entry != expected) | |
663 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
664 | pde, | |
665 | pd_entry, | |
666 | expected); | |
667 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
668 | ||
669 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
670 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
671 | unsigned long va = | |
672 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
673 | (pte * PAGE_SIZE); | |
674 | int i; | |
675 | bool found = false; | |
676 | for (i = 0; i < 4; i++) | |
677 | if (pt_vaddr[pte + i] != scratch_pte) | |
678 | found = true; | |
679 | if (!found) | |
680 | continue; | |
681 | ||
682 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
683 | for (i = 0; i < 4; i++) { | |
684 | if (pt_vaddr[pte + i] != scratch_pte) | |
685 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
686 | else | |
687 | seq_puts(m, " SCRATCH "); | |
688 | } | |
689 | seq_puts(m, "\n"); | |
690 | } | |
691 | kunmap_atomic(pt_vaddr); | |
692 | } | |
693 | } | |
694 | ||
3e302542 | 695 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 696 | { |
853ba5d2 | 697 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
698 | gen6_gtt_pte_t __iomem *pd_addr; |
699 | uint32_t pd_entry; | |
700 | int i; | |
701 | ||
0a732870 | 702 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
703 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
704 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
705 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
706 | dma_addr_t pt_addr; | |
707 | ||
708 | pt_addr = ppgtt->pt_dma_addr[i]; | |
709 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
710 | pd_entry |= GEN6_PDE_VALID; | |
711 | ||
712 | writel(pd_entry, pd_addr + i); | |
713 | } | |
714 | readl(pd_addr); | |
3e302542 BW |
715 | } |
716 | ||
b4a74e3a | 717 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 718 | { |
b4a74e3a BW |
719 | BUG_ON(ppgtt->pd_offset & 0x3f); |
720 | ||
721 | return (ppgtt->pd_offset / 64) << 16; | |
722 | } | |
723 | ||
90252e5c | 724 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 725 | struct intel_engine_cs *ring, |
90252e5c BW |
726 | bool synchronous) |
727 | { | |
728 | struct drm_device *dev = ppgtt->base.dev; | |
729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
730 | int ret; | |
731 | ||
732 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
733 | * manually frob these bits. Ideally we could use the ring functions, | |
734 | * except our error handling makes it quite difficult (can't use | |
735 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
736 | * | |
737 | * FIXME: We should try not to special case reset | |
738 | */ | |
739 | if (synchronous || | |
740 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
741 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
742 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
743 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
744 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
745 | return 0; | |
746 | } | |
747 | ||
748 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
749 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
750 | if (ret) | |
751 | return ret; | |
752 | ||
753 | ret = intel_ring_begin(ring, 6); | |
754 | if (ret) | |
755 | return ret; | |
756 | ||
757 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
758 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
759 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
760 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
761 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
762 | intel_ring_emit(ring, MI_NOOP); | |
763 | intel_ring_advance(ring); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
48a10389 | 768 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 769 | struct intel_engine_cs *ring, |
48a10389 BW |
770 | bool synchronous) |
771 | { | |
772 | struct drm_device *dev = ppgtt->base.dev; | |
773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
774 | int ret; | |
775 | ||
776 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
777 | * manually frob these bits. Ideally we could use the ring functions, | |
778 | * except our error handling makes it quite difficult (can't use | |
779 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
780 | * | |
781 | * FIXME: We should try not to special case reset | |
782 | */ | |
783 | if (synchronous || | |
784 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
785 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
786 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
787 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
788 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
789 | return 0; | |
790 | } | |
791 | ||
792 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
793 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
794 | if (ret) | |
795 | return ret; | |
796 | ||
797 | ret = intel_ring_begin(ring, 6); | |
798 | if (ret) | |
799 | return ret; | |
800 | ||
801 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
802 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
803 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
804 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
805 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
806 | intel_ring_emit(ring, MI_NOOP); | |
807 | intel_ring_advance(ring); | |
808 | ||
90252e5c BW |
809 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
810 | if (ring->id != RCS) { | |
811 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
812 | if (ret) | |
813 | return ret; | |
814 | } | |
815 | ||
48a10389 BW |
816 | return 0; |
817 | } | |
818 | ||
eeb9488e | 819 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
a4872ba6 | 820 | struct intel_engine_cs *ring, |
eeb9488e BW |
821 | bool synchronous) |
822 | { | |
823 | struct drm_device *dev = ppgtt->base.dev; | |
824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
825 | ||
48a10389 BW |
826 | if (!synchronous) |
827 | return 0; | |
828 | ||
eeb9488e BW |
829 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
830 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
831 | ||
832 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
838 | { | |
839 | struct drm_device *dev = ppgtt->base.dev; | |
840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 841 | struct intel_engine_cs *ring; |
eeb9488e | 842 | int j, ret; |
3e302542 | 843 | |
eeb9488e BW |
844 | for_each_ring(ring, dev_priv, j) { |
845 | I915_WRITE(RING_MODE_GEN7(ring), | |
846 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 847 | |
d2ff7192 BW |
848 | /* We promise to do a switch later with FULL PPGTT. If this is |
849 | * aliasing, this is the one and only switch we'll do */ | |
850 | if (USES_FULL_PPGTT(dev)) | |
851 | continue; | |
6197349b | 852 | |
eeb9488e BW |
853 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
854 | if (ret) | |
855 | goto err_out; | |
856 | } | |
6197349b | 857 | |
eeb9488e | 858 | return 0; |
6197349b | 859 | |
eeb9488e BW |
860 | err_out: |
861 | for_each_ring(ring, dev_priv, j) | |
862 | I915_WRITE(RING_MODE_GEN7(ring), | |
863 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
864 | return ret; | |
865 | } | |
6197349b | 866 | |
b4a74e3a | 867 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 868 | { |
a3d67d23 | 869 | struct drm_device *dev = ppgtt->base.dev; |
50227e1c | 870 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 871 | struct intel_engine_cs *ring; |
b4a74e3a | 872 | uint32_t ecochk, ecobits; |
3e302542 | 873 | int i; |
6197349b | 874 | |
b4a74e3a BW |
875 | ecobits = I915_READ(GAC_ECO_BITS); |
876 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 877 | |
b4a74e3a BW |
878 | ecochk = I915_READ(GAM_ECOCHK); |
879 | if (IS_HASWELL(dev)) { | |
880 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
881 | } else { | |
882 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
883 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
884 | } | |
885 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 886 | |
b4a74e3a | 887 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 888 | int ret; |
6197349b | 889 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
890 | I915_WRITE(RING_MODE_GEN7(ring), |
891 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
892 | |
893 | /* We promise to do a switch later with FULL PPGTT. If this is | |
894 | * aliasing, this is the one and only switch we'll do */ | |
895 | if (USES_FULL_PPGTT(dev)) | |
896 | continue; | |
897 | ||
eeb9488e BW |
898 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
899 | if (ret) | |
900 | return ret; | |
6197349b BW |
901 | } |
902 | ||
b4a74e3a BW |
903 | return 0; |
904 | } | |
6197349b | 905 | |
b4a74e3a BW |
906 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
907 | { | |
908 | struct drm_device *dev = ppgtt->base.dev; | |
50227e1c | 909 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 910 | struct intel_engine_cs *ring; |
b4a74e3a BW |
911 | uint32_t ecochk, gab_ctl, ecobits; |
912 | int i; | |
a65c2fcd | 913 | |
b4a74e3a BW |
914 | ecobits = I915_READ(GAC_ECO_BITS); |
915 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
916 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 917 | |
b4a74e3a BW |
918 | gab_ctl = I915_READ(GAB_CTL); |
919 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
920 | ||
921 | ecochk = I915_READ(GAM_ECOCHK); | |
922 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
923 | ||
924 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 925 | |
b4a74e3a | 926 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
927 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
928 | if (ret) | |
929 | return ret; | |
6197349b | 930 | } |
b4a74e3a | 931 | |
b7c36d25 | 932 | return 0; |
6197349b BW |
933 | } |
934 | ||
1d2a314c | 935 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 936 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
937 | uint64_t start, |
938 | uint64_t length, | |
828c7908 | 939 | bool use_scratch) |
1d2a314c | 940 | { |
853ba5d2 BW |
941 | struct i915_hw_ppgtt *ppgtt = |
942 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 943 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
944 | unsigned first_entry = start >> PAGE_SHIFT; |
945 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 946 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
947 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
948 | unsigned last_pte, i; | |
1d2a314c | 949 | |
b35b380e | 950 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 951 | |
7bddb01f DV |
952 | while (num_entries) { |
953 | last_pte = first_pte + num_entries; | |
954 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
955 | last_pte = I915_PPGTT_PT_ENTRIES; | |
956 | ||
a15326a5 | 957 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 958 | |
7bddb01f DV |
959 | for (i = first_pte; i < last_pte; i++) |
960 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
961 | |
962 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 963 | |
7bddb01f DV |
964 | num_entries -= last_pte - first_pte; |
965 | first_pte = 0; | |
a15326a5 | 966 | act_pt++; |
7bddb01f | 967 | } |
1d2a314c DV |
968 | } |
969 | ||
853ba5d2 | 970 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 971 | struct sg_table *pages, |
782f1495 | 972 | uint64_t start, |
def886c3 DV |
973 | enum i915_cache_level cache_level) |
974 | { | |
853ba5d2 BW |
975 | struct i915_hw_ppgtt *ppgtt = |
976 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 977 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 978 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 979 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
980 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
981 | struct sg_page_iter sg_iter; | |
982 | ||
cc79714f | 983 | pt_vaddr = NULL; |
6e995e23 | 984 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
985 | if (pt_vaddr == NULL) |
986 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 987 | |
cc79714f CW |
988 | pt_vaddr[act_pte] = |
989 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
990 | cache_level, true); | |
6e995e23 ID |
991 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
992 | kunmap_atomic(pt_vaddr); | |
cc79714f | 993 | pt_vaddr = NULL; |
a15326a5 | 994 | act_pt++; |
6e995e23 | 995 | act_pte = 0; |
def886c3 | 996 | } |
def886c3 | 997 | } |
cc79714f CW |
998 | if (pt_vaddr) |
999 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
1000 | } |
1001 | ||
a00d825d | 1002 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 1003 | { |
3440d265 DV |
1004 | int i; |
1005 | ||
1006 | if (ppgtt->pt_dma_addr) { | |
1007 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 1008 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
1009 | ppgtt->pt_dma_addr[i], |
1010 | 4096, PCI_DMA_BIDIRECTIONAL); | |
1011 | } | |
a00d825d BW |
1012 | } |
1013 | ||
1014 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
1015 | { | |
1016 | int i; | |
3440d265 DV |
1017 | |
1018 | kfree(ppgtt->pt_dma_addr); | |
1019 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1020 | __free_page(ppgtt->pt_pages[i]); | |
1021 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1022 | } |
1023 | ||
a00d825d BW |
1024 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1025 | { | |
1026 | struct i915_hw_ppgtt *ppgtt = | |
1027 | container_of(vm, struct i915_hw_ppgtt, base); | |
1028 | ||
1029 | list_del(&vm->global_link); | |
1030 | drm_mm_takedown(&ppgtt->base.mm); | |
1031 | drm_mm_remove_node(&ppgtt->node); | |
1032 | ||
1033 | gen6_ppgtt_unmap_pages(ppgtt); | |
1034 | gen6_ppgtt_free(ppgtt); | |
1035 | } | |
1036 | ||
b146520f | 1037 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1038 | { |
853ba5d2 | 1039 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1040 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1041 | bool retried = false; |
b146520f | 1042 | int ret; |
1d2a314c | 1043 | |
c8d4c0d6 BW |
1044 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1045 | * allocator works in address space sizes, so it's multiplied by page | |
1046 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1047 | */ | |
1048 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1049 | alloc: |
c8d4c0d6 BW |
1050 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1051 | &ppgtt->node, GEN6_PD_SIZE, | |
1052 | GEN6_PD_ALIGN, 0, | |
1053 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1054 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1055 | if (ret == -ENOSPC && !retried) { |
1056 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1057 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1058 | I915_CACHE_NONE, |
1059 | 0, dev_priv->gtt.base.total, | |
1060 | 0); | |
e3cc1995 BW |
1061 | if (ret) |
1062 | return ret; | |
1063 | ||
1064 | retried = true; | |
1065 | goto alloc; | |
1066 | } | |
c8d4c0d6 BW |
1067 | |
1068 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1069 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1070 | |
6670a5a5 | 1071 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1072 | return ret; |
1073 | } | |
1074 | ||
1075 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1076 | { | |
1077 | int i; | |
1078 | ||
a1e22653 | 1079 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1080 | GFP_KERNEL); |
b146520f BW |
1081 | |
1082 | if (!ppgtt->pt_pages) | |
3440d265 | 1083 | return -ENOMEM; |
1d2a314c DV |
1084 | |
1085 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1086 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1087 | if (!ppgtt->pt_pages[i]) { |
1088 | gen6_ppgtt_free(ppgtt); | |
1089 | return -ENOMEM; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1097 | { | |
1098 | int ret; | |
1099 | ||
1100 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1101 | if (ret) | |
1102 | return ret; | |
1103 | ||
1104 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1105 | if (ret) { | |
1106 | drm_mm_remove_node(&ppgtt->node); | |
1107 | return ret; | |
1d2a314c DV |
1108 | } |
1109 | ||
a1e22653 | 1110 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1111 | GFP_KERNEL); |
b146520f BW |
1112 | if (!ppgtt->pt_dma_addr) { |
1113 | drm_mm_remove_node(&ppgtt->node); | |
1114 | gen6_ppgtt_free(ppgtt); | |
1115 | return -ENOMEM; | |
1116 | } | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
1121 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1122 | { | |
1123 | struct drm_device *dev = ppgtt->base.dev; | |
1124 | int i; | |
1d2a314c | 1125 | |
8d2e6308 BW |
1126 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1127 | dma_addr_t pt_addr; | |
211c568b | 1128 | |
8d2e6308 BW |
1129 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1130 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1131 | |
8d2e6308 | 1132 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1133 | gen6_ppgtt_unmap_pages(ppgtt); |
1134 | return -EIO; | |
211c568b | 1135 | } |
b146520f | 1136 | |
8d2e6308 | 1137 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1138 | } |
1d2a314c | 1139 | |
b146520f BW |
1140 | return 0; |
1141 | } | |
1142 | ||
1143 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1144 | { | |
1145 | struct drm_device *dev = ppgtt->base.dev; | |
1146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1147 | int ret; | |
1148 | ||
1149 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1150 | if (IS_GEN6(dev)) { | |
1151 | ppgtt->enable = gen6_ppgtt_enable; | |
1152 | ppgtt->switch_mm = gen6_mm_switch; | |
1153 | } else if (IS_HASWELL(dev)) { | |
1154 | ppgtt->enable = gen7_ppgtt_enable; | |
1155 | ppgtt->switch_mm = hsw_mm_switch; | |
1156 | } else if (IS_GEN7(dev)) { | |
1157 | ppgtt->enable = gen7_ppgtt_enable; | |
1158 | ppgtt->switch_mm = gen7_mm_switch; | |
1159 | } else | |
1160 | BUG(); | |
1161 | ||
1162 | ret = gen6_ppgtt_alloc(ppgtt); | |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
1166 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1167 | if (ret) { | |
1168 | gen6_ppgtt_free(ppgtt); | |
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1173 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1174 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1175 | ppgtt->base.start = 0; |
5a6c93fe | 1176 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1177 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1178 | |
c8d4c0d6 BW |
1179 | ppgtt->pd_offset = |
1180 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1181 | |
b146520f | 1182 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1183 | |
b146520f BW |
1184 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1185 | ppgtt->node.size >> 20, | |
1186 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1187 | |
b146520f | 1188 | return 0; |
3440d265 DV |
1189 | } |
1190 | ||
246cbfb5 | 1191 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1192 | { |
1193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1194 | int ret = 0; |
3440d265 | 1195 | |
853ba5d2 | 1196 | ppgtt->base.dev = dev; |
8407bb91 | 1197 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1198 | |
3ed124b2 BW |
1199 | if (INTEL_INFO(dev)->gen < 8) |
1200 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1201 | else if (IS_GEN8(dev)) |
37aca44a | 1202 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1203 | else |
1204 | BUG(); | |
1205 | ||
c7c48dfd | 1206 | if (!ret) { |
7e0d96bc | 1207 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1208 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1209 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1210 | ppgtt->base.total); | |
7e0d96bc BW |
1211 | i915_init_vm(dev_priv, &ppgtt->base); |
1212 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1213 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1214 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1215 | ppgtt->pd_offset << 10); | |
1216 | } | |
93bd8649 | 1217 | } |
1d2a314c DV |
1218 | |
1219 | return ret; | |
1220 | } | |
1221 | ||
7e0d96bc | 1222 | static void |
6f65e29a BW |
1223 | ppgtt_bind_vma(struct i915_vma *vma, |
1224 | enum i915_cache_level cache_level, | |
1225 | u32 flags) | |
1d2a314c | 1226 | { |
782f1495 BW |
1227 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1228 | cache_level); | |
1d2a314c DV |
1229 | } |
1230 | ||
7e0d96bc | 1231 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1232 | { |
6f65e29a | 1233 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1234 | vma->node.start, |
1235 | vma->obj->base.size, | |
6f65e29a | 1236 | true); |
7bddb01f DV |
1237 | } |
1238 | ||
a81cc00c BW |
1239 | extern int intel_iommu_gfx_mapped; |
1240 | /* Certain Gen5 chipsets require require idling the GPU before | |
1241 | * unmapping anything from the GTT when VT-d is enabled. | |
1242 | */ | |
1243 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1244 | { | |
1245 | #ifdef CONFIG_INTEL_IOMMU | |
1246 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1247 | * was loaded first. | |
1248 | */ | |
1249 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1250 | return true; | |
1251 | #endif | |
1252 | return false; | |
1253 | } | |
1254 | ||
5c042287 BW |
1255 | static bool do_idling(struct drm_i915_private *dev_priv) |
1256 | { | |
1257 | bool ret = dev_priv->mm.interruptible; | |
1258 | ||
a81cc00c | 1259 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1260 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1261 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1262 | DRM_ERROR("Couldn't idle GPU\n"); |
1263 | /* Wait a bit, in hopes it avoids the hang */ | |
1264 | udelay(10); | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1272 | { | |
a81cc00c | 1273 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1274 | dev_priv->mm.interruptible = interruptible; |
1275 | } | |
1276 | ||
828c7908 BW |
1277 | void i915_check_and_clear_faults(struct drm_device *dev) |
1278 | { | |
1279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1280 | struct intel_engine_cs *ring; |
828c7908 BW |
1281 | int i; |
1282 | ||
1283 | if (INTEL_INFO(dev)->gen < 6) | |
1284 | return; | |
1285 | ||
1286 | for_each_ring(ring, dev_priv, i) { | |
1287 | u32 fault_reg; | |
1288 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1289 | if (fault_reg & RING_FAULT_VALID) { | |
1290 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1291 | "\tAddr: 0x%08lx\\n" | |
1292 | "\tAddress space: %s\n" | |
1293 | "\tSource ID: %d\n" | |
1294 | "\tType: %d\n", | |
1295 | fault_reg & PAGE_MASK, | |
1296 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1297 | RING_FAULT_SRCID(fault_reg), | |
1298 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1299 | I915_WRITE(RING_FAULT_REG(ring), | |
1300 | fault_reg & ~RING_FAULT_VALID); | |
1301 | } | |
1302 | } | |
1303 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1304 | } | |
1305 | ||
1306 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1307 | { | |
1308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1309 | ||
1310 | /* Don't bother messing with faults pre GEN6 as we have little | |
1311 | * documentation supporting that it's a good idea. | |
1312 | */ | |
1313 | if (INTEL_INFO(dev)->gen < 6) | |
1314 | return; | |
1315 | ||
1316 | i915_check_and_clear_faults(dev); | |
1317 | ||
1318 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1319 | dev_priv->gtt.base.start, |
1320 | dev_priv->gtt.base.total, | |
e568af1c | 1321 | true); |
828c7908 BW |
1322 | } |
1323 | ||
76aaf220 DV |
1324 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1325 | { | |
1326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1327 | struct drm_i915_gem_object *obj; |
80da2161 | 1328 | struct i915_address_space *vm; |
76aaf220 | 1329 | |
828c7908 BW |
1330 | i915_check_and_clear_faults(dev); |
1331 | ||
bee4a186 | 1332 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1333 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1334 | dev_priv->gtt.base.start, |
1335 | dev_priv->gtt.base.total, | |
828c7908 | 1336 | true); |
bee4a186 | 1337 | |
35c20a60 | 1338 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1339 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1340 | &dev_priv->gtt.base); | |
1341 | if (!vma) | |
1342 | continue; | |
1343 | ||
2c22569b | 1344 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1345 | /* The bind_vma code tries to be smart about tracking mappings. |
1346 | * Unfortunately above, we've just wiped out the mappings | |
1347 | * without telling our object about it. So we need to fake it. | |
1348 | */ | |
1349 | obj->has_global_gtt_mapping = 0; | |
1350 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1351 | } |
1352 | ||
80da2161 | 1353 | |
a2319c08 | 1354 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1355 | if (IS_CHERRYVIEW(dev)) |
1356 | chv_setup_private_ppat(dev_priv); | |
1357 | else | |
1358 | bdw_setup_private_ppat(dev_priv); | |
1359 | ||
80da2161 | 1360 | return; |
a2319c08 | 1361 | } |
80da2161 BW |
1362 | |
1363 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1364 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1365 | if (i915_is_ggtt(vm)) { | |
1366 | if (dev_priv->mm.aliasing_ppgtt) | |
1367 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1368 | continue; | |
1369 | } | |
1370 | ||
1371 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1372 | } |
1373 | ||
e76e9aeb | 1374 | i915_gem_chipset_flush(dev); |
76aaf220 | 1375 | } |
7c2e6fdf | 1376 | |
74163907 | 1377 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1378 | { |
9da3da66 | 1379 | if (obj->has_dma_mapping) |
74163907 | 1380 | return 0; |
9da3da66 CW |
1381 | |
1382 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1383 | obj->pages->sgl, obj->pages->nents, | |
1384 | PCI_DMA_BIDIRECTIONAL)) | |
1385 | return -ENOSPC; | |
1386 | ||
1387 | return 0; | |
7c2e6fdf DV |
1388 | } |
1389 | ||
94ec8f61 BW |
1390 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1391 | { | |
1392 | #ifdef writeq | |
1393 | writeq(pte, addr); | |
1394 | #else | |
1395 | iowrite32((u32)pte, addr); | |
1396 | iowrite32(pte >> 32, addr + 4); | |
1397 | #endif | |
1398 | } | |
1399 | ||
1400 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1401 | struct sg_table *st, | |
782f1495 | 1402 | uint64_t start, |
94ec8f61 BW |
1403 | enum i915_cache_level level) |
1404 | { | |
1405 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1406 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1407 | gen8_gtt_pte_t __iomem *gtt_entries = |
1408 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1409 | int i = 0; | |
1410 | struct sg_page_iter sg_iter; | |
63c42e56 | 1411 | dma_addr_t addr = 0; |
94ec8f61 BW |
1412 | |
1413 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1414 | addr = sg_dma_address(sg_iter.sg) + | |
1415 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1416 | gen8_set_pte(>t_entries[i], | |
1417 | gen8_pte_encode(addr, level, true)); | |
1418 | i++; | |
1419 | } | |
1420 | ||
1421 | /* | |
1422 | * XXX: This serves as a posting read to make sure that the PTE has | |
1423 | * actually been updated. There is some concern that even though | |
1424 | * registers and PTEs are within the same BAR that they are potentially | |
1425 | * of NUMA access patterns. Therefore, even with the way we assume | |
1426 | * hardware should work, we must keep this posting read for paranoia. | |
1427 | */ | |
1428 | if (i != 0) | |
1429 | WARN_ON(readq(>t_entries[i-1]) | |
1430 | != gen8_pte_encode(addr, level, true)); | |
1431 | ||
94ec8f61 BW |
1432 | /* This next bit makes the above posting read even more important. We |
1433 | * want to flush the TLBs only after we're certain all the PTE updates | |
1434 | * have finished. | |
1435 | */ | |
1436 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1437 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1438 | } |
1439 | ||
e76e9aeb BW |
1440 | /* |
1441 | * Binds an object into the global gtt with the specified cache level. The object | |
1442 | * will be accessible to the GPU via commands whose operands reference offsets | |
1443 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1444 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1445 | */ | |
853ba5d2 | 1446 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1447 | struct sg_table *st, |
782f1495 | 1448 | uint64_t start, |
7faf1ab2 | 1449 | enum i915_cache_level level) |
e76e9aeb | 1450 | { |
853ba5d2 | 1451 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1452 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1453 | gen6_gtt_pte_t __iomem *gtt_entries = |
1454 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1455 | int i = 0; |
1456 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1457 | dma_addr_t addr; |
1458 | ||
6e995e23 | 1459 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1460 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1461 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1462 | i++; |
e76e9aeb BW |
1463 | } |
1464 | ||
e76e9aeb BW |
1465 | /* XXX: This serves as a posting read to make sure that the PTE has |
1466 | * actually been updated. There is some concern that even though | |
1467 | * registers and PTEs are within the same BAR that they are potentially | |
1468 | * of NUMA access patterns. Therefore, even with the way we assume | |
1469 | * hardware should work, we must keep this posting read for paranoia. | |
1470 | */ | |
1471 | if (i != 0) | |
853ba5d2 | 1472 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1473 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1474 | |
1475 | /* This next bit makes the above posting read even more important. We | |
1476 | * want to flush the TLBs only after we're certain all the PTE updates | |
1477 | * have finished. | |
1478 | */ | |
1479 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1480 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1481 | } |
1482 | ||
94ec8f61 | 1483 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1484 | uint64_t start, |
1485 | uint64_t length, | |
94ec8f61 BW |
1486 | bool use_scratch) |
1487 | { | |
1488 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1489 | unsigned first_entry = start >> PAGE_SHIFT; |
1490 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1491 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1492 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1493 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1494 | int i; | |
1495 | ||
1496 | if (WARN(num_entries > max_entries, | |
1497 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1498 | first_entry, num_entries, max_entries)) | |
1499 | num_entries = max_entries; | |
1500 | ||
1501 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1502 | I915_CACHE_LLC, | |
1503 | use_scratch); | |
1504 | for (i = 0; i < num_entries; i++) | |
1505 | gen8_set_pte(>t_base[i], scratch_pte); | |
1506 | readl(gtt_base); | |
1507 | } | |
1508 | ||
853ba5d2 | 1509 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1510 | uint64_t start, |
1511 | uint64_t length, | |
828c7908 | 1512 | bool use_scratch) |
7faf1ab2 | 1513 | { |
853ba5d2 | 1514 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1515 | unsigned first_entry = start >> PAGE_SHIFT; |
1516 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1517 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1518 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1519 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1520 | int i; |
1521 | ||
1522 | if (WARN(num_entries > max_entries, | |
1523 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1524 | first_entry, num_entries, max_entries)) | |
1525 | num_entries = max_entries; | |
1526 | ||
828c7908 BW |
1527 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1528 | ||
7faf1ab2 DV |
1529 | for (i = 0; i < num_entries; i++) |
1530 | iowrite32(scratch_pte, >t_base[i]); | |
1531 | readl(gtt_base); | |
1532 | } | |
1533 | ||
6f65e29a BW |
1534 | |
1535 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1536 | enum i915_cache_level cache_level, | |
1537 | u32 unused) | |
7faf1ab2 | 1538 | { |
6f65e29a | 1539 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1540 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1541 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1542 | ||
6f65e29a BW |
1543 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1544 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1545 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1546 | } |
1547 | ||
853ba5d2 | 1548 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1549 | uint64_t start, |
1550 | uint64_t length, | |
828c7908 | 1551 | bool unused) |
7faf1ab2 | 1552 | { |
782f1495 BW |
1553 | unsigned first_entry = start >> PAGE_SHIFT; |
1554 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1555 | intel_gtt_clear_range(first_entry, num_entries); |
1556 | } | |
1557 | ||
6f65e29a BW |
1558 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1559 | { | |
1560 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1561 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1562 | |
6f65e29a BW |
1563 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1564 | vma->obj->has_global_gtt_mapping = 0; | |
1565 | intel_gtt_clear_range(first, size); | |
1566 | } | |
7faf1ab2 | 1567 | |
6f65e29a BW |
1568 | static void ggtt_bind_vma(struct i915_vma *vma, |
1569 | enum i915_cache_level cache_level, | |
1570 | u32 flags) | |
d5bd1449 | 1571 | { |
6f65e29a | 1572 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1574 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1575 | |
6f65e29a BW |
1576 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1577 | * or we have a global mapping already but the cacheability flags have | |
1578 | * changed, set the global PTEs. | |
1579 | * | |
1580 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1581 | * instead if none of the above hold true. | |
1582 | * | |
1583 | * NB: A global mapping should only be needed for special regions like | |
1584 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1585 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1586 | */ | |
1587 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1588 | if (!obj->has_global_gtt_mapping || | |
1589 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1590 | vma->vm->insert_entries(vma->vm, obj->pages, |
1591 | vma->node.start, | |
6f65e29a BW |
1592 | cache_level); |
1593 | obj->has_global_gtt_mapping = 1; | |
1594 | } | |
1595 | } | |
d5bd1449 | 1596 | |
6f65e29a BW |
1597 | if (dev_priv->mm.aliasing_ppgtt && |
1598 | (!obj->has_aliasing_ppgtt_mapping || | |
1599 | (cache_level != obj->cache_level))) { | |
1600 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1601 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1602 | vma->obj->pages, |
1603 | vma->node.start, | |
1604 | cache_level); | |
6f65e29a BW |
1605 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1606 | } | |
d5bd1449 CW |
1607 | } |
1608 | ||
6f65e29a | 1609 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1610 | { |
6f65e29a | 1611 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1612 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1613 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1614 | |
1615 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1616 | vma->vm->clear_range(vma->vm, |
1617 | vma->node.start, | |
1618 | obj->base.size, | |
6f65e29a BW |
1619 | true); |
1620 | obj->has_global_gtt_mapping = 0; | |
1621 | } | |
74898d7e | 1622 | |
6f65e29a BW |
1623 | if (obj->has_aliasing_ppgtt_mapping) { |
1624 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1625 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1626 | vma->node.start, |
1627 | obj->base.size, | |
6f65e29a BW |
1628 | true); |
1629 | obj->has_aliasing_ppgtt_mapping = 0; | |
1630 | } | |
74163907 DV |
1631 | } |
1632 | ||
1633 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1634 | { |
5c042287 BW |
1635 | struct drm_device *dev = obj->base.dev; |
1636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1637 | bool interruptible; | |
1638 | ||
1639 | interruptible = do_idling(dev_priv); | |
1640 | ||
9da3da66 CW |
1641 | if (!obj->has_dma_mapping) |
1642 | dma_unmap_sg(&dev->pdev->dev, | |
1643 | obj->pages->sgl, obj->pages->nents, | |
1644 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1645 | |
1646 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1647 | } |
644ec02b | 1648 | |
42d6ab48 CW |
1649 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1650 | unsigned long color, | |
1651 | unsigned long *start, | |
1652 | unsigned long *end) | |
1653 | { | |
1654 | if (node->color != color) | |
1655 | *start += 4096; | |
1656 | ||
1657 | if (!list_empty(&node->node_list)) { | |
1658 | node = list_entry(node->node_list.next, | |
1659 | struct drm_mm_node, | |
1660 | node_list); | |
1661 | if (node->allocated && node->color != color) | |
1662 | *end -= 4096; | |
1663 | } | |
1664 | } | |
fbe5d36e | 1665 | |
d7e5008f BW |
1666 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1667 | unsigned long start, | |
1668 | unsigned long mappable_end, | |
1669 | unsigned long end) | |
644ec02b | 1670 | { |
e78891ca BW |
1671 | /* Let GEM Manage all of the aperture. |
1672 | * | |
1673 | * However, leave one page at the end still bound to the scratch page. | |
1674 | * There are a number of places where the hardware apparently prefetches | |
1675 | * past the end of the object, and we've seen multiple hangs with the | |
1676 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1677 | * aperture. One page should be enough to keep any prefetching inside | |
1678 | * of the aperture. | |
1679 | */ | |
40d74980 BW |
1680 | struct drm_i915_private *dev_priv = dev->dev_private; |
1681 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1682 | struct drm_mm_node *entry; |
1683 | struct drm_i915_gem_object *obj; | |
1684 | unsigned long hole_start, hole_end; | |
644ec02b | 1685 | |
35451cb6 BW |
1686 | BUG_ON(mappable_end > end); |
1687 | ||
ed2f3452 | 1688 | /* Subtract the guard page ... */ |
40d74980 | 1689 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1690 | if (!HAS_LLC(dev)) |
93bd8649 | 1691 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1692 | |
ed2f3452 | 1693 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1694 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1695 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1696 | int ret; |
edd41a87 | 1697 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1698 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1699 | ||
1700 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1701 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1702 | if (ret) |
b3a070cc | 1703 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1704 | obj->has_global_gtt_mapping = 1; |
1705 | } | |
1706 | ||
853ba5d2 BW |
1707 | dev_priv->gtt.base.start = start; |
1708 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1709 | |
ed2f3452 | 1710 | /* Clear any non-preallocated blocks */ |
40d74980 | 1711 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1712 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1713 | hole_start, hole_end); | |
782f1495 BW |
1714 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1715 | hole_end - hole_start, true); | |
ed2f3452 CW |
1716 | } |
1717 | ||
1718 | /* And finally clear the reserved guard page */ | |
782f1495 | 1719 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1720 | } |
1721 | ||
d7e5008f BW |
1722 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1723 | { | |
1724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1725 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1726 | |
853ba5d2 | 1727 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1728 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1729 | |
e78891ca | 1730 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1731 | } |
1732 | ||
1733 | static int setup_scratch_page(struct drm_device *dev) | |
1734 | { | |
1735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1736 | struct page *page; | |
1737 | dma_addr_t dma_addr; | |
1738 | ||
1739 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1740 | if (page == NULL) | |
1741 | return -ENOMEM; | |
1742 | get_page(page); | |
1743 | set_pages_uc(page, 1); | |
1744 | ||
1745 | #ifdef CONFIG_INTEL_IOMMU | |
1746 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1747 | PCI_DMA_BIDIRECTIONAL); | |
1748 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1749 | return -EINVAL; | |
1750 | #else | |
1751 | dma_addr = page_to_phys(page); | |
1752 | #endif | |
853ba5d2 BW |
1753 | dev_priv->gtt.base.scratch.page = page; |
1754 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1755 | |
1756 | return 0; | |
1757 | } | |
1758 | ||
1759 | static void teardown_scratch_page(struct drm_device *dev) | |
1760 | { | |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1762 | struct page *page = dev_priv->gtt.base.scratch.page; |
1763 | ||
1764 | set_pages_wb(page, 1); | |
1765 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1766 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1767 | put_page(page); |
1768 | __free_page(page); | |
e76e9aeb BW |
1769 | } |
1770 | ||
1771 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1772 | { | |
1773 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1774 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1775 | return snb_gmch_ctl << 20; | |
1776 | } | |
1777 | ||
9459d252 BW |
1778 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1779 | { | |
1780 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1781 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1782 | if (bdw_gmch_ctl) | |
1783 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1784 | |
1785 | #ifdef CONFIG_X86_32 | |
1786 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1787 | if (bdw_gmch_ctl > 4) | |
1788 | bdw_gmch_ctl = 4; | |
1789 | #endif | |
1790 | ||
9459d252 BW |
1791 | return bdw_gmch_ctl << 20; |
1792 | } | |
1793 | ||
d7f25f23 DL |
1794 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1795 | { | |
1796 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1797 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1798 | ||
1799 | if (gmch_ctrl) | |
1800 | return 1 << (20 + gmch_ctrl); | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
baa09f5f | 1805 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1806 | { |
1807 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1808 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1809 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1810 | } | |
1811 | ||
9459d252 BW |
1812 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1813 | { | |
1814 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1815 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1816 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1817 | } | |
1818 | ||
d7f25f23 DL |
1819 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1820 | { | |
1821 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1822 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1823 | ||
1824 | /* | |
1825 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1826 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1827 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1828 | */ | |
1829 | if (gmch_ctrl < 0x11) | |
1830 | return gmch_ctrl << 25; | |
1831 | else if (gmch_ctrl < 0x17) | |
1832 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1833 | else | |
1834 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1835 | } | |
1836 | ||
63340133 BW |
1837 | static int ggtt_probe_common(struct drm_device *dev, |
1838 | size_t gtt_size) | |
1839 | { | |
1840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1841 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1842 | int ret; |
1843 | ||
1844 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1845 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1846 | (pci_resource_len(dev->pdev, 0) / 2); |
1847 | ||
21c34607 | 1848 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1849 | if (!dev_priv->gtt.gsm) { |
1850 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1851 | return -ENOMEM; | |
1852 | } | |
1853 | ||
1854 | ret = setup_scratch_page(dev); | |
1855 | if (ret) { | |
1856 | DRM_ERROR("Scratch setup failed\n"); | |
1857 | /* iounmap will also get called at remove, but meh */ | |
1858 | iounmap(dev_priv->gtt.gsm); | |
1859 | } | |
1860 | ||
1861 | return ret; | |
1862 | } | |
1863 | ||
fbe5d36e BW |
1864 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1865 | * bits. When using advanced contexts each context stores its own PAT, but | |
1866 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1867 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1868 | { |
fbe5d36e BW |
1869 | uint64_t pat; |
1870 | ||
1871 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1872 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1873 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1874 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1875 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1876 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1877 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1878 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1879 | ||
1880 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1881 | * write would work. */ | |
1882 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1883 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1884 | } | |
1885 | ||
ee0ce478 VS |
1886 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1887 | { | |
1888 | uint64_t pat; | |
1889 | ||
1890 | /* | |
1891 | * Map WB on BDW to snooped on CHV. | |
1892 | * | |
1893 | * Only the snoop bit has meaning for CHV, the rest is | |
1894 | * ignored. | |
1895 | * | |
1896 | * Note that the harware enforces snooping for all page | |
1897 | * table accesses. The snoop bit is actually ignored for | |
1898 | * PDEs. | |
1899 | */ | |
1900 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1901 | GEN8_PPAT(1, 0) | | |
1902 | GEN8_PPAT(2, 0) | | |
1903 | GEN8_PPAT(3, 0) | | |
1904 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1905 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1906 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1907 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1908 | ||
1909 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1910 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1911 | } | |
1912 | ||
63340133 BW |
1913 | static int gen8_gmch_probe(struct drm_device *dev, |
1914 | size_t *gtt_total, | |
1915 | size_t *stolen, | |
1916 | phys_addr_t *mappable_base, | |
1917 | unsigned long *mappable_end) | |
1918 | { | |
1919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1920 | unsigned int gtt_size; | |
1921 | u16 snb_gmch_ctl; | |
1922 | int ret; | |
1923 | ||
1924 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1925 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1926 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1927 | ||
1928 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1929 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1930 | ||
1931 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1932 | ||
d7f25f23 DL |
1933 | if (IS_CHERRYVIEW(dev)) { |
1934 | *stolen = chv_get_stolen_size(snb_gmch_ctl); | |
1935 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
1936 | } else { | |
1937 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1938 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
1939 | } | |
63340133 | 1940 | |
d31eb10e | 1941 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1942 | |
ee0ce478 VS |
1943 | if (IS_CHERRYVIEW(dev)) |
1944 | chv_setup_private_ppat(dev_priv); | |
1945 | else | |
1946 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 1947 | |
63340133 BW |
1948 | ret = ggtt_probe_common(dev, gtt_size); |
1949 | ||
94ec8f61 BW |
1950 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1951 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1952 | |
1953 | return ret; | |
1954 | } | |
1955 | ||
baa09f5f BW |
1956 | static int gen6_gmch_probe(struct drm_device *dev, |
1957 | size_t *gtt_total, | |
41907ddc BW |
1958 | size_t *stolen, |
1959 | phys_addr_t *mappable_base, | |
1960 | unsigned long *mappable_end) | |
e76e9aeb BW |
1961 | { |
1962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1963 | unsigned int gtt_size; |
e76e9aeb | 1964 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1965 | int ret; |
1966 | ||
41907ddc BW |
1967 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1968 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1969 | ||
baa09f5f BW |
1970 | /* 64/512MB is the current min/max we actually know of, but this is just |
1971 | * a coarse sanity check. | |
e76e9aeb | 1972 | */ |
41907ddc | 1973 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1974 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1975 | dev_priv->gtt.mappable_end); | |
1976 | return -ENXIO; | |
e76e9aeb BW |
1977 | } |
1978 | ||
e76e9aeb BW |
1979 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1980 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1981 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1982 | |
c4ae25ec | 1983 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1984 | |
63340133 BW |
1985 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1986 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1987 | |
63340133 | 1988 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1989 | |
853ba5d2 BW |
1990 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1991 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1992 | |
e76e9aeb BW |
1993 | return ret; |
1994 | } | |
1995 | ||
853ba5d2 | 1996 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1997 | { |
853ba5d2 BW |
1998 | |
1999 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
2000 | |
2001 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
2002 | iounmap(gtt->gsm); |
2003 | teardown_scratch_page(vm->dev); | |
644ec02b | 2004 | } |
baa09f5f BW |
2005 | |
2006 | static int i915_gmch_probe(struct drm_device *dev, | |
2007 | size_t *gtt_total, | |
41907ddc BW |
2008 | size_t *stolen, |
2009 | phys_addr_t *mappable_base, | |
2010 | unsigned long *mappable_end) | |
baa09f5f BW |
2011 | { |
2012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2013 | int ret; | |
2014 | ||
baa09f5f BW |
2015 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2016 | if (!ret) { | |
2017 | DRM_ERROR("failed to set up gmch\n"); | |
2018 | return -EIO; | |
2019 | } | |
2020 | ||
41907ddc | 2021 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2022 | |
2023 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2024 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2025 | |
c0a7f818 CW |
2026 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2027 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2028 | ||
baa09f5f BW |
2029 | return 0; |
2030 | } | |
2031 | ||
853ba5d2 | 2032 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2033 | { |
2034 | intel_gmch_remove(); | |
2035 | } | |
2036 | ||
2037 | int i915_gem_gtt_init(struct drm_device *dev) | |
2038 | { | |
2039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2040 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2041 | int ret; |
2042 | ||
baa09f5f | 2043 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2044 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2045 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2046 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2047 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2048 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2049 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2050 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2051 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2052 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2053 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2054 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2055 | else if (INTEL_INFO(dev)->gen >= 7) |
2056 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2057 | else |
350ec881 | 2058 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2059 | } else { |
2060 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2061 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2062 | } |
2063 | ||
853ba5d2 | 2064 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2065 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2066 | if (ret) |
baa09f5f | 2067 | return ret; |
baa09f5f | 2068 | |
853ba5d2 BW |
2069 | gtt->base.dev = dev; |
2070 | ||
baa09f5f | 2071 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2072 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2073 | gtt->base.total >> 20); | |
b2f21b4d BW |
2074 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2075 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2076 | #ifdef CONFIG_INTEL_IOMMU |
2077 | if (intel_iommu_gfx_mapped) | |
2078 | DRM_INFO("VT-d active for gfx access\n"); | |
2079 | #endif | |
cfa7c862 DV |
2080 | /* |
2081 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2082 | * user's requested state against the hardware/driver capabilities. We | |
2083 | * do this now so that we can print out any log messages once rather | |
2084 | * than every time we check intel_enable_ppgtt(). | |
2085 | */ | |
2086 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2087 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2088 | |
2089 | return 0; | |
2090 | } | |
6f65e29a BW |
2091 | |
2092 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2093 | struct i915_address_space *vm) | |
2094 | { | |
2095 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2096 | if (vma == NULL) | |
2097 | return ERR_PTR(-ENOMEM); | |
2098 | ||
2099 | INIT_LIST_HEAD(&vma->vma_link); | |
2100 | INIT_LIST_HEAD(&vma->mm_list); | |
2101 | INIT_LIST_HEAD(&vma->exec_list); | |
2102 | vma->vm = vm; | |
2103 | vma->obj = obj; | |
2104 | ||
2105 | switch (INTEL_INFO(vm->dev)->gen) { | |
2106 | case 8: | |
2107 | case 7: | |
2108 | case 6: | |
7e0d96bc BW |
2109 | if (i915_is_ggtt(vm)) { |
2110 | vma->unbind_vma = ggtt_unbind_vma; | |
2111 | vma->bind_vma = ggtt_bind_vma; | |
2112 | } else { | |
2113 | vma->unbind_vma = ppgtt_unbind_vma; | |
2114 | vma->bind_vma = ppgtt_bind_vma; | |
2115 | } | |
6f65e29a BW |
2116 | break; |
2117 | case 5: | |
2118 | case 4: | |
2119 | case 3: | |
2120 | case 2: | |
2121 | BUG_ON(!i915_is_ggtt(vm)); | |
2122 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2123 | vma->bind_vma = i915_ggtt_bind_vma; | |
2124 | break; | |
2125 | default: | |
2126 | BUG(); | |
2127 | } | |
2128 | ||
2129 | /* Keep GGTT vmas first to make debug easier */ | |
2130 | if (i915_is_ggtt(vm)) | |
2131 | list_add(&vma->vma_link, &obj->vma_list); | |
2132 | else | |
2133 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2134 | ||
2135 | return vma; | |
2136 | } | |
2137 | ||
2138 | struct i915_vma * | |
2139 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2140 | struct i915_address_space *vm) | |
2141 | { | |
2142 | struct i915_vma *vma; | |
2143 | ||
2144 | vma = i915_gem_obj_to_vma(obj, vm); | |
2145 | if (!vma) | |
2146 | vma = __i915_gem_vma_create(obj, vm); | |
2147 | ||
2148 | return vma; | |
2149 | } |