Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
33 | ||
26b1ff35 BW |
34 | /* PPGTT stuff */ |
35 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
36 | ||
37 | #define GEN6_PDE_VALID (1 << 0) | |
38 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
39 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
40 | ||
41 | #define GEN6_PTE_VALID (1 << 0) | |
42 | #define GEN6_PTE_UNCACHED (1 << 1) | |
43 | #define HSW_PTE_UNCACHED (0) | |
44 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
45 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
46 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
47 | ||
2d04befb KG |
48 | static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
49 | dma_addr_t addr, | |
50 | enum i915_cache_level level) | |
54d12527 | 51 | { |
e7c2b58b | 52 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 53 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
54 | |
55 | switch (level) { | |
56 | case I915_CACHE_LLC_MLC: | |
9119708c | 57 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
58 | break; |
59 | case I915_CACHE_LLC: | |
60 | pte |= GEN6_PTE_CACHE_LLC; | |
61 | break; | |
62 | case I915_CACHE_NONE: | |
9119708c | 63 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
64 | break; |
65 | default: | |
66 | BUG(); | |
67 | } | |
68 | ||
54d12527 BW |
69 | return pte; |
70 | } | |
71 | ||
93c34e70 KG |
72 | #define BYT_PTE_WRITEABLE (1 << 1) |
73 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
74 | ||
75 | static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, | |
76 | dma_addr_t addr, | |
77 | enum i915_cache_level level) | |
78 | { | |
79 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
80 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
81 | ||
82 | /* Mark the page as writeable. Other platforms don't have a | |
83 | * setting for read-only/writable, so this matches that behavior. | |
84 | */ | |
85 | pte |= BYT_PTE_WRITEABLE; | |
86 | ||
87 | if (level != I915_CACHE_NONE) | |
88 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
89 | ||
90 | return pte; | |
91 | } | |
92 | ||
9119708c KG |
93 | static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev, |
94 | dma_addr_t addr, | |
95 | enum i915_cache_level level) | |
96 | { | |
97 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
98 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
99 | ||
100 | if (level != I915_CACHE_NONE) | |
101 | pte |= GEN6_PTE_CACHE_LLC; | |
102 | ||
103 | return pte; | |
104 | } | |
105 | ||
3e302542 | 106 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 107 | { |
3e302542 | 108 | struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; |
6197349b BW |
109 | gen6_gtt_pte_t __iomem *pd_addr; |
110 | uint32_t pd_entry; | |
111 | int i; | |
112 | ||
0a732870 | 113 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
114 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
115 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
116 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
117 | dma_addr_t pt_addr; | |
118 | ||
119 | pt_addr = ppgtt->pt_dma_addr[i]; | |
120 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
121 | pd_entry |= GEN6_PDE_VALID; | |
122 | ||
123 | writel(pd_entry, pd_addr + i); | |
124 | } | |
125 | readl(pd_addr); | |
3e302542 BW |
126 | } |
127 | ||
128 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
129 | { | |
130 | drm_i915_private_t *dev_priv = dev->dev_private; | |
131 | uint32_t pd_offset; | |
132 | struct intel_ring_buffer *ring; | |
133 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
134 | int i; | |
135 | ||
136 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
137 | ||
138 | gen6_write_pdes(ppgtt); | |
6197349b BW |
139 | |
140 | pd_offset = ppgtt->pd_offset; | |
141 | pd_offset /= 64; /* in cachelines, */ | |
142 | pd_offset <<= 16; | |
143 | ||
144 | if (INTEL_INFO(dev)->gen == 6) { | |
145 | uint32_t ecochk, gab_ctl, ecobits; | |
146 | ||
147 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
148 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
149 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
150 | |
151 | gab_ctl = I915_READ(GAB_CTL); | |
152 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
153 | ||
154 | ecochk = I915_READ(GAM_ECOCHK); | |
155 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
156 | ECOCHK_PPGTT_CACHE64B); | |
157 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
158 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 159 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
160 | |
161 | ecobits = I915_READ(GAC_ECO_BITS); | |
162 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
163 | ||
a6f429a5 VS |
164 | ecochk = I915_READ(GAM_ECOCHK); |
165 | if (IS_HASWELL(dev)) { | |
166 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
167 | } else { | |
168 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
169 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
170 | } | |
171 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
172 | /* GFX_MODE is per-ring on gen7+ */ |
173 | } | |
174 | ||
175 | for_each_ring(ring, dev_priv, i) { | |
176 | if (INTEL_INFO(dev)->gen >= 7) | |
177 | I915_WRITE(RING_MODE_GEN7(ring), | |
178 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
179 | ||
180 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
181 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
182 | } | |
b7c36d25 | 183 | return 0; |
6197349b BW |
184 | } |
185 | ||
1d2a314c | 186 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 187 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
188 | unsigned first_entry, |
189 | unsigned num_entries) | |
190 | { | |
84f13560 | 191 | struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; |
e7c2b58b | 192 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 193 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
194 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
195 | unsigned last_pte, i; | |
1d2a314c | 196 | |
2d04befb | 197 | scratch_pte = ppgtt->pte_encode(ppgtt->dev, |
67167240 | 198 | dev_priv->gtt.scratch.addr, |
2d04befb | 199 | I915_CACHE_LLC); |
1d2a314c | 200 | |
7bddb01f DV |
201 | while (num_entries) { |
202 | last_pte = first_pte + num_entries; | |
203 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
204 | last_pte = I915_PPGTT_PT_ENTRIES; | |
205 | ||
a15326a5 | 206 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 207 | |
7bddb01f DV |
208 | for (i = first_pte; i < last_pte; i++) |
209 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
210 | |
211 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 212 | |
7bddb01f DV |
213 | num_entries -= last_pte - first_pte; |
214 | first_pte = 0; | |
a15326a5 | 215 | act_pt++; |
7bddb01f | 216 | } |
1d2a314c DV |
217 | } |
218 | ||
def886c3 DV |
219 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
220 | struct sg_table *pages, | |
221 | unsigned first_entry, | |
222 | enum i915_cache_level cache_level) | |
223 | { | |
e7c2b58b | 224 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 225 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
226 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
227 | struct sg_page_iter sg_iter; | |
228 | ||
a15326a5 | 229 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
230 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
231 | dma_addr_t page_addr; | |
232 | ||
2db76d7c | 233 | page_addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
234 | pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr, |
235 | cache_level); | |
6e995e23 ID |
236 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
237 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
238 | act_pt++; |
239 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 240 | act_pte = 0; |
def886c3 | 241 | |
def886c3 | 242 | } |
def886c3 | 243 | } |
6e995e23 | 244 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
245 | } |
246 | ||
3440d265 | 247 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 248 | { |
3440d265 DV |
249 | int i; |
250 | ||
251 | if (ppgtt->pt_dma_addr) { | |
252 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
253 | pci_unmap_page(ppgtt->dev->pdev, | |
254 | ppgtt->pt_dma_addr[i], | |
255 | 4096, PCI_DMA_BIDIRECTIONAL); | |
256 | } | |
257 | ||
258 | kfree(ppgtt->pt_dma_addr); | |
259 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
260 | __free_page(ppgtt->pt_pages[i]); | |
261 | kfree(ppgtt->pt_pages); | |
262 | kfree(ppgtt); | |
263 | } | |
264 | ||
265 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
266 | { | |
267 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 268 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 269 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
270 | int i; |
271 | int ret = -ENOMEM; | |
272 | ||
273 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
274 | * entries. For aliasing ppgtt support we just steal them at the end for | |
275 | * now. */ | |
e1b73cba | 276 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 277 | |
9119708c KG |
278 | if (IS_HASWELL(dev)) { |
279 | ppgtt->pte_encode = hsw_pte_encode; | |
280 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
281 | ppgtt->pte_encode = byt_pte_encode; |
282 | } else { | |
283 | ppgtt->pte_encode = gen6_pte_encode; | |
284 | } | |
6670a5a5 | 285 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 286 | ppgtt->enable = gen6_ppgtt_enable; |
def886c3 DV |
287 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
288 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 289 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
290 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
291 | GFP_KERNEL); | |
292 | if (!ppgtt->pt_pages) | |
3440d265 | 293 | return -ENOMEM; |
1d2a314c DV |
294 | |
295 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
296 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
297 | if (!ppgtt->pt_pages[i]) | |
298 | goto err_pt_alloc; | |
299 | } | |
300 | ||
8d2e6308 BW |
301 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
302 | GFP_KERNEL); | |
303 | if (!ppgtt->pt_dma_addr) | |
304 | goto err_pt_alloc; | |
1d2a314c | 305 | |
8d2e6308 BW |
306 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
307 | dma_addr_t pt_addr; | |
211c568b | 308 | |
8d2e6308 BW |
309 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
310 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 311 | |
8d2e6308 BW |
312 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
313 | ret = -EIO; | |
314 | goto err_pd_pin; | |
1d2a314c | 315 | |
211c568b | 316 | } |
8d2e6308 | 317 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 318 | } |
1d2a314c | 319 | |
def886c3 DV |
320 | ppgtt->clear_range(ppgtt, 0, |
321 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 322 | |
e7c2b58b | 323 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 324 | |
1d2a314c DV |
325 | return 0; |
326 | ||
327 | err_pd_pin: | |
328 | if (ppgtt->pt_dma_addr) { | |
329 | for (i--; i >= 0; i--) | |
330 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
331 | 4096, PCI_DMA_BIDIRECTIONAL); | |
332 | } | |
333 | err_pt_alloc: | |
334 | kfree(ppgtt->pt_dma_addr); | |
335 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
336 | if (ppgtt->pt_pages[i]) | |
337 | __free_page(ppgtt->pt_pages[i]); | |
338 | } | |
339 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
340 | |
341 | return ret; | |
342 | } | |
343 | ||
344 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
345 | { | |
346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
347 | struct i915_hw_ppgtt *ppgtt; | |
348 | int ret; | |
349 | ||
350 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
351 | if (!ppgtt) | |
352 | return -ENOMEM; | |
353 | ||
354 | ppgtt->dev = dev; | |
355 | ||
3ed124b2 BW |
356 | if (INTEL_INFO(dev)->gen < 8) |
357 | ret = gen6_ppgtt_init(ppgtt); | |
358 | else | |
359 | BUG(); | |
360 | ||
3440d265 DV |
361 | if (ret) |
362 | kfree(ppgtt); | |
363 | else | |
364 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
365 | |
366 | return ret; | |
367 | } | |
368 | ||
369 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
370 | { | |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
372 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
373 | |
374 | if (!ppgtt) | |
375 | return; | |
376 | ||
3440d265 | 377 | ppgtt->cleanup(ppgtt); |
5963cf04 | 378 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
379 | } |
380 | ||
7bddb01f DV |
381 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
382 | struct drm_i915_gem_object *obj, | |
383 | enum i915_cache_level cache_level) | |
384 | { | |
def886c3 DV |
385 | ppgtt->insert_entries(ppgtt, obj->pages, |
386 | obj->gtt_space->start >> PAGE_SHIFT, | |
387 | cache_level); | |
7bddb01f DV |
388 | } |
389 | ||
390 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
391 | struct drm_i915_gem_object *obj) | |
392 | { | |
def886c3 DV |
393 | ppgtt->clear_range(ppgtt, |
394 | obj->gtt_space->start >> PAGE_SHIFT, | |
395 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
396 | } |
397 | ||
a81cc00c BW |
398 | extern int intel_iommu_gfx_mapped; |
399 | /* Certain Gen5 chipsets require require idling the GPU before | |
400 | * unmapping anything from the GTT when VT-d is enabled. | |
401 | */ | |
402 | static inline bool needs_idle_maps(struct drm_device *dev) | |
403 | { | |
404 | #ifdef CONFIG_INTEL_IOMMU | |
405 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
406 | * was loaded first. | |
407 | */ | |
408 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
409 | return true; | |
410 | #endif | |
411 | return false; | |
412 | } | |
413 | ||
5c042287 BW |
414 | static bool do_idling(struct drm_i915_private *dev_priv) |
415 | { | |
416 | bool ret = dev_priv->mm.interruptible; | |
417 | ||
a81cc00c | 418 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 419 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 420 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
421 | DRM_ERROR("Couldn't idle GPU\n"); |
422 | /* Wait a bit, in hopes it avoids the hang */ | |
423 | udelay(10); | |
424 | } | |
425 | } | |
426 | ||
427 | return ret; | |
428 | } | |
429 | ||
430 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
431 | { | |
a81cc00c | 432 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
433 | dev_priv->mm.interruptible = interruptible; |
434 | } | |
435 | ||
76aaf220 DV |
436 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
437 | { | |
438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 439 | struct drm_i915_gem_object *obj; |
76aaf220 | 440 | |
bee4a186 | 441 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
442 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
443 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 444 | |
35c20a60 | 445 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
a8e93126 | 446 | i915_gem_clflush_object(obj); |
74163907 | 447 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
448 | } |
449 | ||
e76e9aeb | 450 | i915_gem_chipset_flush(dev); |
76aaf220 | 451 | } |
7c2e6fdf | 452 | |
74163907 | 453 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 454 | { |
9da3da66 | 455 | if (obj->has_dma_mapping) |
74163907 | 456 | return 0; |
9da3da66 CW |
457 | |
458 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
459 | obj->pages->sgl, obj->pages->nents, | |
460 | PCI_DMA_BIDIRECTIONAL)) | |
461 | return -ENOSPC; | |
462 | ||
463 | return 0; | |
7c2e6fdf DV |
464 | } |
465 | ||
e76e9aeb BW |
466 | /* |
467 | * Binds an object into the global gtt with the specified cache level. The object | |
468 | * will be accessible to the GPU via commands whose operands reference offsets | |
469 | * within the global GTT as well as accessible by the GPU through the GMADR | |
470 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
471 | */ | |
7faf1ab2 DV |
472 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
473 | struct sg_table *st, | |
474 | unsigned int first_entry, | |
475 | enum i915_cache_level level) | |
e76e9aeb | 476 | { |
e76e9aeb | 477 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
478 | gen6_gtt_pte_t __iomem *gtt_entries = |
479 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
480 | int i = 0; |
481 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
482 | dma_addr_t addr; |
483 | ||
6e995e23 | 484 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 485 | addr = sg_page_iter_dma_address(&sg_iter); |
2d04befb KG |
486 | iowrite32(dev_priv->gtt.pte_encode(dev, addr, level), |
487 | >t_entries[i]); | |
6e995e23 | 488 | i++; |
e76e9aeb BW |
489 | } |
490 | ||
e76e9aeb BW |
491 | /* XXX: This serves as a posting read to make sure that the PTE has |
492 | * actually been updated. There is some concern that even though | |
493 | * registers and PTEs are within the same BAR that they are potentially | |
494 | * of NUMA access patterns. Therefore, even with the way we assume | |
495 | * hardware should work, we must keep this posting read for paranoia. | |
496 | */ | |
497 | if (i != 0) | |
960e3e42 | 498 | WARN_ON(readl(>t_entries[i-1]) |
2d04befb | 499 | != dev_priv->gtt.pte_encode(dev, addr, level)); |
0f9b91c7 BW |
500 | |
501 | /* This next bit makes the above posting read even more important. We | |
502 | * want to flush the TLBs only after we're certain all the PTE updates | |
503 | * have finished. | |
504 | */ | |
505 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
506 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
507 | } |
508 | ||
7faf1ab2 DV |
509 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
510 | unsigned int first_entry, | |
511 | unsigned int num_entries) | |
512 | { | |
513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
514 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
515 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 516 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
517 | int i; |
518 | ||
519 | if (WARN(num_entries > max_entries, | |
520 | "First entry = %d; Num entries = %d (max=%d)\n", | |
521 | first_entry, num_entries, max_entries)) | |
522 | num_entries = max_entries; | |
523 | ||
67167240 | 524 | scratch_pte = dev_priv->gtt.pte_encode(dev, dev_priv->gtt.scratch.addr, |
2d04befb | 525 | I915_CACHE_LLC); |
7faf1ab2 DV |
526 | for (i = 0; i < num_entries; i++) |
527 | iowrite32(scratch_pte, >t_base[i]); | |
528 | readl(gtt_base); | |
529 | } | |
530 | ||
531 | ||
532 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
533 | struct sg_table *st, | |
534 | unsigned int pg_start, | |
535 | enum i915_cache_level cache_level) | |
536 | { | |
537 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
538 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
539 | ||
540 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
541 | ||
542 | } | |
543 | ||
544 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
545 | unsigned int first_entry, | |
546 | unsigned int num_entries) | |
547 | { | |
548 | intel_gtt_clear_range(first_entry, num_entries); | |
549 | } | |
550 | ||
551 | ||
74163907 DV |
552 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
553 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
554 | { |
555 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
556 | struct drm_i915_private *dev_priv = dev->dev_private; |
557 | ||
558 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
559 | obj->gtt_space->start >> PAGE_SHIFT, | |
560 | cache_level); | |
d5bd1449 | 561 | |
74898d7e | 562 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
563 | } |
564 | ||
05394f39 | 565 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 566 | { |
7faf1ab2 DV |
567 | struct drm_device *dev = obj->base.dev; |
568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
569 | ||
570 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
571 | obj->gtt_space->start >> PAGE_SHIFT, | |
572 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
573 | |
574 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
575 | } |
576 | ||
577 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 578 | { |
5c042287 BW |
579 | struct drm_device *dev = obj->base.dev; |
580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
581 | bool interruptible; | |
582 | ||
583 | interruptible = do_idling(dev_priv); | |
584 | ||
9da3da66 CW |
585 | if (!obj->has_dma_mapping) |
586 | dma_unmap_sg(&dev->pdev->dev, | |
587 | obj->pages->sgl, obj->pages->nents, | |
588 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
589 | |
590 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 591 | } |
644ec02b | 592 | |
42d6ab48 CW |
593 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
594 | unsigned long color, | |
595 | unsigned long *start, | |
596 | unsigned long *end) | |
597 | { | |
598 | if (node->color != color) | |
599 | *start += 4096; | |
600 | ||
601 | if (!list_empty(&node->node_list)) { | |
602 | node = list_entry(node->node_list.next, | |
603 | struct drm_mm_node, | |
604 | node_list); | |
605 | if (node->allocated && node->color != color) | |
606 | *end -= 4096; | |
607 | } | |
608 | } | |
d7e5008f BW |
609 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
610 | unsigned long start, | |
611 | unsigned long mappable_end, | |
612 | unsigned long end) | |
644ec02b | 613 | { |
e78891ca BW |
614 | /* Let GEM Manage all of the aperture. |
615 | * | |
616 | * However, leave one page at the end still bound to the scratch page. | |
617 | * There are a number of places where the hardware apparently prefetches | |
618 | * past the end of the object, and we've seen multiple hangs with the | |
619 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
620 | * aperture. One page should be enough to keep any prefetching inside | |
621 | * of the aperture. | |
622 | */ | |
644ec02b | 623 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
624 | struct drm_mm_node *entry; |
625 | struct drm_i915_gem_object *obj; | |
626 | unsigned long hole_start, hole_end; | |
644ec02b | 627 | |
35451cb6 BW |
628 | BUG_ON(mappable_end > end); |
629 | ||
ed2f3452 | 630 | /* Subtract the guard page ... */ |
d1dd20a9 | 631 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
632 | if (!HAS_LLC(dev)) |
633 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 634 | |
ed2f3452 | 635 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 636 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
ed2f3452 CW |
637 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", |
638 | obj->gtt_offset, obj->base.size); | |
639 | ||
640 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
641 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
642 | obj->gtt_offset, | |
643 | obj->base.size, | |
644 | false); | |
645 | obj->has_global_gtt_mapping = 1; | |
646 | } | |
647 | ||
5d4545ae | 648 | dev_priv->gtt.start = start; |
5d4545ae | 649 | dev_priv->gtt.total = end - start; |
644ec02b | 650 | |
ed2f3452 CW |
651 | /* Clear any non-preallocated blocks */ |
652 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
653 | hole_start, hole_end) { | |
654 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
655 | hole_start, hole_end); | |
7faf1ab2 DV |
656 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
657 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
658 | } |
659 | ||
660 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 661 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
662 | } |
663 | ||
d7e5008f BW |
664 | static bool |
665 | intel_enable_ppgtt(struct drm_device *dev) | |
666 | { | |
667 | if (i915_enable_ppgtt >= 0) | |
668 | return i915_enable_ppgtt; | |
669 | ||
670 | #ifdef CONFIG_INTEL_IOMMU | |
671 | /* Disable ppgtt on SNB if VT-d is on. */ | |
672 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
673 | return false; | |
674 | #endif | |
675 | ||
676 | return true; | |
677 | } | |
678 | ||
679 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
680 | { | |
681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
682 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 683 | |
a54c0c27 | 684 | gtt_size = dev_priv->gtt.total; |
93d18799 | 685 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
686 | |
687 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 688 | int ret; |
3eb1c005 BW |
689 | |
690 | if (INTEL_INFO(dev)->gen <= 7) { | |
691 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
692 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 693 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 694 | } |
d7e5008f BW |
695 | |
696 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
697 | ||
698 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 699 | if (!ret) |
d7e5008f | 700 | return; |
e78891ca BW |
701 | |
702 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
703 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
6670a5a5 | 704 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 705 | } |
e78891ca | 706 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
707 | } |
708 | ||
709 | static int setup_scratch_page(struct drm_device *dev) | |
710 | { | |
711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
712 | struct page *page; | |
713 | dma_addr_t dma_addr; | |
714 | ||
715 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
716 | if (page == NULL) | |
717 | return -ENOMEM; | |
718 | get_page(page); | |
719 | set_pages_uc(page, 1); | |
720 | ||
721 | #ifdef CONFIG_INTEL_IOMMU | |
722 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
723 | PCI_DMA_BIDIRECTIONAL); | |
724 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
725 | return -EINVAL; | |
726 | #else | |
727 | dma_addr = page_to_phys(page); | |
728 | #endif | |
67167240 BW |
729 | dev_priv->gtt.scratch.page = page; |
730 | dev_priv->gtt.scratch.addr = dma_addr; | |
e76e9aeb BW |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
735 | static void teardown_scratch_page(struct drm_device *dev) | |
736 | { | |
737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67167240 BW |
738 | set_pages_wb(dev_priv->gtt.scratch.page, 1); |
739 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch.addr, | |
e76e9aeb | 740 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
67167240 BW |
741 | put_page(dev_priv->gtt.scratch.page); |
742 | __free_page(dev_priv->gtt.scratch.page); | |
e76e9aeb BW |
743 | } |
744 | ||
745 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
746 | { | |
747 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
748 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
749 | return snb_gmch_ctl << 20; | |
750 | } | |
751 | ||
baa09f5f | 752 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
753 | { |
754 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
755 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
756 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
757 | } | |
758 | ||
baa09f5f BW |
759 | static int gen6_gmch_probe(struct drm_device *dev, |
760 | size_t *gtt_total, | |
41907ddc BW |
761 | size_t *stolen, |
762 | phys_addr_t *mappable_base, | |
763 | unsigned long *mappable_end) | |
e76e9aeb BW |
764 | { |
765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 767 | unsigned int gtt_size; |
e76e9aeb | 768 | u16 snb_gmch_ctl; |
e76e9aeb BW |
769 | int ret; |
770 | ||
41907ddc BW |
771 | *mappable_base = pci_resource_start(dev->pdev, 2); |
772 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
773 | ||
baa09f5f BW |
774 | /* 64/512MB is the current min/max we actually know of, but this is just |
775 | * a coarse sanity check. | |
e76e9aeb | 776 | */ |
41907ddc | 777 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
778 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
779 | dev_priv->gtt.mappable_end); | |
780 | return -ENXIO; | |
e76e9aeb BW |
781 | } |
782 | ||
e76e9aeb BW |
783 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
784 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 785 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 786 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 787 | |
c4ae25ec | 788 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 789 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 790 | |
a93e4161 BW |
791 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
792 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
793 | (pci_resource_len(dev->pdev, 0) / 2); | |
794 | ||
baa09f5f | 795 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 796 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 797 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 798 | return -ENOMEM; |
e76e9aeb BW |
799 | } |
800 | ||
baa09f5f BW |
801 | ret = setup_scratch_page(dev); |
802 | if (ret) | |
803 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 804 | |
7faf1ab2 DV |
805 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
806 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
807 | ||
e76e9aeb BW |
808 | return ret; |
809 | } | |
810 | ||
d93c6233 | 811 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
812 | { |
813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 814 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 815 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 816 | } |
baa09f5f BW |
817 | |
818 | static int i915_gmch_probe(struct drm_device *dev, | |
819 | size_t *gtt_total, | |
41907ddc BW |
820 | size_t *stolen, |
821 | phys_addr_t *mappable_base, | |
822 | unsigned long *mappable_end) | |
baa09f5f BW |
823 | { |
824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
825 | int ret; | |
826 | ||
baa09f5f BW |
827 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
828 | if (!ret) { | |
829 | DRM_ERROR("failed to set up gmch\n"); | |
830 | return -EIO; | |
831 | } | |
832 | ||
41907ddc | 833 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
834 | |
835 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
836 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
837 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | static void i915_gmch_remove(struct drm_device *dev) | |
843 | { | |
844 | intel_gmch_remove(); | |
845 | } | |
846 | ||
847 | int i915_gem_gtt_init(struct drm_device *dev) | |
848 | { | |
849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
850 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
851 | int ret; |
852 | ||
baa09f5f BW |
853 | if (INTEL_INFO(dev)->gen <= 5) { |
854 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
855 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
856 | } else { | |
857 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
858 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
9119708c KG |
859 | if (IS_HASWELL(dev)) { |
860 | dev_priv->gtt.pte_encode = hsw_pte_encode; | |
861 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
862 | dev_priv->gtt.pte_encode = byt_pte_encode; |
863 | } else { | |
864 | dev_priv->gtt.pte_encode = gen6_pte_encode; | |
865 | } | |
baa09f5f BW |
866 | } |
867 | ||
868 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
869 | &dev_priv->gtt.stolen_size, |
870 | >t->mappable_base, | |
871 | >t->mappable_end); | |
a54c0c27 | 872 | if (ret) |
baa09f5f | 873 | return ret; |
baa09f5f | 874 | |
baa09f5f BW |
875 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
876 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
877 | dev_priv->gtt.total >> 20); | |
878 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
879 | dev_priv->gtt.mappable_end >> 20); | |
880 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
881 | dev_priv->gtt.stolen_size >> 20); | |
882 | ||
883 | return 0; | |
884 | } |