Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 DV |
29 | #include "i915_drv.h" |
30 | #include "i915_trace.h" | |
31 | #include "intel_drv.h" | |
32 | ||
ee0ce478 VS |
33 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
34 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 35 | |
93a25a9e DV |
36 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) |
37 | { | |
38 | if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | |
39 | return false; | |
40 | ||
41 | if (i915.enable_ppgtt == 1 && full) | |
42 | return false; | |
43 | ||
44 | #ifdef CONFIG_INTEL_IOMMU | |
45 | /* Disable ppgtt on SNB if VT-d is on. */ | |
46 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
47 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
48 | return false; | |
49 | } | |
50 | #endif | |
51 | ||
52 | /* Full ppgtt disabled by default for now due to issues. */ | |
53 | if (full) | |
8d214b7d | 54 | return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2); |
93a25a9e DV |
55 | else |
56 | return HAS_ALIASING_PPGTT(dev); | |
57 | } | |
58 | ||
fbe5d36e | 59 | |
6f65e29a BW |
60 | static void ppgtt_bind_vma(struct i915_vma *vma, |
61 | enum i915_cache_level cache_level, | |
62 | u32 flags); | |
63 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 64 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 65 | |
94ec8f61 BW |
66 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
67 | enum i915_cache_level level, | |
68 | bool valid) | |
69 | { | |
70 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
71 | pte |= addr; | |
63c42e56 BW |
72 | |
73 | switch (level) { | |
74 | case I915_CACHE_NONE: | |
fbe5d36e | 75 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
76 | break; |
77 | case I915_CACHE_WT: | |
78 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
79 | break; | |
80 | default: | |
81 | pte |= PPAT_CACHED_INDEX; | |
82 | break; | |
83 | } | |
84 | ||
94ec8f61 BW |
85 | return pte; |
86 | } | |
87 | ||
b1fe6673 BW |
88 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
89 | dma_addr_t addr, | |
90 | enum i915_cache_level level) | |
91 | { | |
92 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
93 | pde |= addr; | |
94 | if (level != I915_CACHE_NONE) | |
95 | pde |= PPAT_CACHED_PDE_INDEX; | |
96 | else | |
97 | pde |= PPAT_UNCACHED_INDEX; | |
98 | return pde; | |
99 | } | |
100 | ||
350ec881 | 101 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
102 | enum i915_cache_level level, |
103 | bool valid) | |
54d12527 | 104 | { |
b35b380e | 105 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 106 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
107 | |
108 | switch (level) { | |
350ec881 CW |
109 | case I915_CACHE_L3_LLC: |
110 | case I915_CACHE_LLC: | |
111 | pte |= GEN6_PTE_CACHE_LLC; | |
112 | break; | |
113 | case I915_CACHE_NONE: | |
114 | pte |= GEN6_PTE_UNCACHED; | |
115 | break; | |
116 | default: | |
117 | WARN_ON(1); | |
118 | } | |
119 | ||
120 | return pte; | |
121 | } | |
122 | ||
123 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
124 | enum i915_cache_level level, |
125 | bool valid) | |
350ec881 | 126 | { |
b35b380e | 127 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
128 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
129 | ||
130 | switch (level) { | |
131 | case I915_CACHE_L3_LLC: | |
132 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
133 | break; |
134 | case I915_CACHE_LLC: | |
135 | pte |= GEN6_PTE_CACHE_LLC; | |
136 | break; | |
137 | case I915_CACHE_NONE: | |
9119708c | 138 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
139 | break; |
140 | default: | |
350ec881 | 141 | WARN_ON(1); |
e7210c3c BW |
142 | } |
143 | ||
54d12527 BW |
144 | return pte; |
145 | } | |
146 | ||
80a74f7f | 147 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
148 | enum i915_cache_level level, |
149 | bool valid) | |
93c34e70 | 150 | { |
b35b380e | 151 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
152 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
153 | ||
154 | /* Mark the page as writeable. Other platforms don't have a | |
155 | * setting for read-only/writable, so this matches that behavior. | |
156 | */ | |
157 | pte |= BYT_PTE_WRITEABLE; | |
158 | ||
159 | if (level != I915_CACHE_NONE) | |
160 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
161 | ||
162 | return pte; | |
163 | } | |
164 | ||
80a74f7f | 165 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
166 | enum i915_cache_level level, |
167 | bool valid) | |
9119708c | 168 | { |
b35b380e | 169 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 170 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
171 | |
172 | if (level != I915_CACHE_NONE) | |
87a6b688 | 173 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
174 | |
175 | return pte; | |
176 | } | |
177 | ||
4d15c145 | 178 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
179 | enum i915_cache_level level, |
180 | bool valid) | |
4d15c145 | 181 | { |
b35b380e | 182 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
183 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
184 | ||
651d794f CW |
185 | switch (level) { |
186 | case I915_CACHE_NONE: | |
187 | break; | |
188 | case I915_CACHE_WT: | |
c51e9701 | 189 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
190 | break; |
191 | default: | |
c51e9701 | 192 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
193 | break; |
194 | } | |
4d15c145 BW |
195 | |
196 | return pte; | |
197 | } | |
198 | ||
94e409c1 BW |
199 | /* Broadwell Page Directory Pointer Descriptors */ |
200 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 201 | uint64_t val, bool synchronous) |
94e409c1 | 202 | { |
e178f705 | 203 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
204 | int ret; |
205 | ||
206 | BUG_ON(entry >= 4); | |
207 | ||
e178f705 BW |
208 | if (synchronous) { |
209 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
210 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
211 | return 0; | |
212 | } | |
213 | ||
94e409c1 BW |
214 | ret = intel_ring_begin(ring, 6); |
215 | if (ret) | |
216 | return ret; | |
217 | ||
218 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
219 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
220 | intel_ring_emit(ring, (u32)(val >> 32)); | |
221 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
222 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
223 | intel_ring_emit(ring, (u32)(val)); | |
224 | intel_ring_advance(ring); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
eeb9488e BW |
229 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
230 | struct intel_ring_buffer *ring, | |
231 | bool synchronous) | |
94e409c1 | 232 | { |
eeb9488e | 233 | int i, ret; |
94e409c1 BW |
234 | |
235 | /* bit of a hack to find the actual last used pd */ | |
236 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
237 | ||
94e409c1 BW |
238 | for (i = used_pd - 1; i >= 0; i--) { |
239 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
240 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
241 | if (ret) | |
242 | return ret; | |
94e409c1 | 243 | } |
d595bd4b | 244 | |
eeb9488e | 245 | return 0; |
94e409c1 BW |
246 | } |
247 | ||
459108b8 | 248 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
249 | uint64_t start, |
250 | uint64_t length, | |
459108b8 BW |
251 | bool use_scratch) |
252 | { | |
253 | struct i915_hw_ppgtt *ppgtt = | |
254 | container_of(vm, struct i915_hw_ppgtt, base); | |
255 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
256 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
257 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
258 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 259 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
260 | unsigned last_pte, i; |
261 | ||
262 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
263 | I915_CACHE_LLC, use_scratch); | |
264 | ||
265 | while (num_entries) { | |
7ad47cf2 | 266 | struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde]; |
459108b8 | 267 | |
7ad47cf2 | 268 | last_pte = pte + num_entries; |
459108b8 BW |
269 | if (last_pte > GEN8_PTES_PER_PAGE) |
270 | last_pte = GEN8_PTES_PER_PAGE; | |
271 | ||
272 | pt_vaddr = kmap_atomic(page_table); | |
273 | ||
7ad47cf2 | 274 | for (i = pte; i < last_pte; i++) { |
459108b8 | 275 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
276 | num_entries--; |
277 | } | |
459108b8 | 278 | |
fd1ab8f4 RB |
279 | if (!HAS_LLC(ppgtt->base.dev)) |
280 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
281 | kunmap_atomic(pt_vaddr); |
282 | ||
7ad47cf2 BW |
283 | pte = 0; |
284 | if (++pde == GEN8_PDES_PER_PAGE) { | |
285 | pdpe++; | |
286 | pde = 0; | |
287 | } | |
459108b8 BW |
288 | } |
289 | } | |
290 | ||
9df15b49 BW |
291 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
292 | struct sg_table *pages, | |
782f1495 | 293 | uint64_t start, |
9df15b49 BW |
294 | enum i915_cache_level cache_level) |
295 | { | |
296 | struct i915_hw_ppgtt *ppgtt = | |
297 | container_of(vm, struct i915_hw_ppgtt, base); | |
298 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
299 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
300 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
301 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
302 | struct sg_page_iter sg_iter; |
303 | ||
6f1cc993 | 304 | pt_vaddr = NULL; |
7ad47cf2 | 305 | |
9df15b49 | 306 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
7ad47cf2 BW |
307 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS)) |
308 | break; | |
309 | ||
6f1cc993 | 310 | if (pt_vaddr == NULL) |
7ad47cf2 | 311 | pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]); |
9df15b49 | 312 | |
7ad47cf2 | 313 | pt_vaddr[pte] = |
6f1cc993 CW |
314 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
315 | cache_level, true); | |
7ad47cf2 | 316 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
317 | if (!HAS_LLC(ppgtt->base.dev)) |
318 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 319 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 320 | pt_vaddr = NULL; |
7ad47cf2 BW |
321 | if (++pde == GEN8_PDES_PER_PAGE) { |
322 | pdpe++; | |
323 | pde = 0; | |
324 | } | |
325 | pte = 0; | |
9df15b49 BW |
326 | } |
327 | } | |
fd1ab8f4 RB |
328 | if (pt_vaddr) { |
329 | if (!HAS_LLC(ppgtt->base.dev)) | |
330 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 331 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 332 | } |
9df15b49 BW |
333 | } |
334 | ||
7ad47cf2 BW |
335 | static void gen8_free_page_tables(struct page **pt_pages) |
336 | { | |
337 | int i; | |
338 | ||
339 | if (pt_pages == NULL) | |
340 | return; | |
341 | ||
342 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
343 | if (pt_pages[i]) | |
344 | __free_pages(pt_pages[i], 0); | |
345 | } | |
346 | ||
347 | static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
348 | { |
349 | int i; | |
350 | ||
7ad47cf2 BW |
351 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
352 | gen8_free_page_tables(ppgtt->gen8_pt_pages[i]); | |
353 | kfree(ppgtt->gen8_pt_pages[i]); | |
b45a6715 | 354 | kfree(ppgtt->gen8_pt_dma_addr[i]); |
7ad47cf2 | 355 | } |
b45a6715 | 356 | |
b45a6715 BW |
357 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); |
358 | } | |
359 | ||
360 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
361 | { | |
f3a964b9 | 362 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
363 | int i, j; |
364 | ||
365 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
366 | /* TODO: In the future we'll support sparse mappings, so this | |
367 | * will have to change. */ | |
368 | if (!ppgtt->pd_dma_addr[i]) | |
369 | continue; | |
370 | ||
f3a964b9 BW |
371 | pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE, |
372 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
373 | |
374 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
375 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
376 | if (addr) | |
f3a964b9 BW |
377 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
378 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
379 | } |
380 | } | |
381 | } | |
382 | ||
37aca44a BW |
383 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
384 | { | |
385 | struct i915_hw_ppgtt *ppgtt = | |
386 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 387 | |
7e0d96bc | 388 | list_del(&vm->global_link); |
686e1f6f BW |
389 | drm_mm_takedown(&vm->mm); |
390 | ||
b45a6715 BW |
391 | gen8_ppgtt_unmap_pages(ppgtt); |
392 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
393 | } |
394 | ||
7ad47cf2 BW |
395 | static struct page **__gen8_alloc_page_tables(void) |
396 | { | |
397 | struct page **pt_pages; | |
398 | int i; | |
399 | ||
400 | pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL); | |
401 | if (!pt_pages) | |
402 | return ERR_PTR(-ENOMEM); | |
403 | ||
404 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { | |
405 | pt_pages[i] = alloc_page(GFP_KERNEL); | |
406 | if (!pt_pages[i]) | |
407 | goto bail; | |
408 | } | |
409 | ||
410 | return pt_pages; | |
411 | ||
412 | bail: | |
413 | gen8_free_page_tables(pt_pages); | |
414 | kfree(pt_pages); | |
415 | return ERR_PTR(-ENOMEM); | |
416 | } | |
417 | ||
bf2b4ed2 BW |
418 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt, |
419 | const int max_pdp) | |
420 | { | |
7ad47cf2 | 421 | struct page **pt_pages[GEN8_LEGACY_PDPS]; |
7ad47cf2 | 422 | int i, ret; |
bf2b4ed2 | 423 | |
7ad47cf2 BW |
424 | for (i = 0; i < max_pdp; i++) { |
425 | pt_pages[i] = __gen8_alloc_page_tables(); | |
426 | if (IS_ERR(pt_pages[i])) { | |
427 | ret = PTR_ERR(pt_pages[i]); | |
428 | goto unwind_out; | |
429 | } | |
430 | } | |
431 | ||
432 | /* NB: Avoid touching gen8_pt_pages until last to keep the allocation, | |
433 | * "atomic" - for cleanup purposes. | |
434 | */ | |
435 | for (i = 0; i < max_pdp; i++) | |
436 | ppgtt->gen8_pt_pages[i] = pt_pages[i]; | |
bf2b4ed2 | 437 | |
bf2b4ed2 | 438 | return 0; |
7ad47cf2 BW |
439 | |
440 | unwind_out: | |
441 | while (i--) { | |
442 | gen8_free_page_tables(pt_pages[i]); | |
443 | kfree(pt_pages[i]); | |
444 | } | |
445 | ||
446 | return ret; | |
bf2b4ed2 BW |
447 | } |
448 | ||
449 | static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt) | |
450 | { | |
451 | int i; | |
452 | ||
453 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
454 | ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE, | |
455 | sizeof(dma_addr_t), | |
456 | GFP_KERNEL); | |
457 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
458 | return -ENOMEM; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, | |
465 | const int max_pdp) | |
466 | { | |
467 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
468 | if (!ppgtt->pd_pages) | |
469 | return -ENOMEM; | |
470 | ||
471 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
472 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
478 | const int max_pdp) | |
479 | { | |
480 | int ret; | |
481 | ||
482 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
486 | ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp); | |
487 | if (ret) { | |
488 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
489 | return ret; | |
490 | } | |
491 | ||
492 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
493 | ||
494 | ret = gen8_ppgtt_allocate_dma(ppgtt); | |
495 | if (ret) | |
496 | gen8_ppgtt_free(ppgtt); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
502 | const int pd) | |
503 | { | |
504 | dma_addr_t pd_addr; | |
505 | int ret; | |
506 | ||
507 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
508 | &ppgtt->pd_pages[pd], 0, | |
509 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
510 | ||
511 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
512 | if (ret) | |
513 | return ret; | |
514 | ||
515 | ppgtt->pd_dma_addr[pd] = pd_addr; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
521 | const int pd, | |
522 | const int pt) | |
523 | { | |
524 | dma_addr_t pt_addr; | |
525 | struct page *p; | |
526 | int ret; | |
527 | ||
7ad47cf2 | 528 | p = ppgtt->gen8_pt_pages[pd][pt]; |
bf2b4ed2 BW |
529 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
530 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
531 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
532 | if (ret) | |
533 | return ret; | |
534 | ||
535 | ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr; | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
37aca44a | 540 | /** |
f3a964b9 BW |
541 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
542 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
543 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
544 | * space. | |
37aca44a | 545 | * |
f3a964b9 BW |
546 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
547 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 548 | * TODO: Do something with the size parameter |
f3a964b9 | 549 | */ |
37aca44a BW |
550 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
551 | { | |
37aca44a | 552 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 553 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 554 | int i, j, ret; |
37aca44a BW |
555 | |
556 | if (size % (1<<30)) | |
557 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
558 | ||
bf2b4ed2 BW |
559 | /* 1. Do all our allocations for page directories and page tables. */ |
560 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
561 | if (ret) | |
562 | return ret; | |
f3a964b9 | 563 | |
37aca44a | 564 | /* |
bf2b4ed2 | 565 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
566 | */ |
567 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 568 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
569 | if (ret) |
570 | goto bail; | |
37aca44a | 571 | |
37aca44a | 572 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 573 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
574 | if (ret) |
575 | goto bail; | |
37aca44a BW |
576 | } |
577 | } | |
578 | ||
f3a964b9 BW |
579 | /* |
580 | * 3. Map all the page directory entires to point to the page tables | |
581 | * we've allocated. | |
582 | * | |
583 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 584 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
585 | * will never need to touch the PDEs again. |
586 | */ | |
b1fe6673 BW |
587 | for (i = 0; i < max_pdp; i++) { |
588 | gen8_ppgtt_pde_t *pd_vaddr; | |
589 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
590 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
591 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
592 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
593 | I915_CACHE_LLC); | |
594 | } | |
fd1ab8f4 RB |
595 | if (!HAS_LLC(ppgtt->base.dev)) |
596 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
597 | kunmap_atomic(pd_vaddr); |
598 | } | |
599 | ||
f3a964b9 BW |
600 | ppgtt->enable = gen8_ppgtt_enable; |
601 | ppgtt->switch_mm = gen8_mm_switch; | |
602 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
603 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
604 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
605 | ppgtt->base.start = 0; | |
5abbcca3 | 606 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 607 | |
5abbcca3 | 608 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 609 | |
37aca44a BW |
610 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
611 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
612 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
613 | ppgtt->num_pd_entries, |
614 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 615 | return 0; |
37aca44a | 616 | |
f3a964b9 BW |
617 | bail: |
618 | gen8_ppgtt_unmap_pages(ppgtt); | |
619 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
620 | return ret; |
621 | } | |
622 | ||
87d60b63 BW |
623 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
624 | { | |
625 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
626 | struct i915_address_space *vm = &ppgtt->base; | |
627 | gen6_gtt_pte_t __iomem *pd_addr; | |
628 | gen6_gtt_pte_t scratch_pte; | |
629 | uint32_t pd_entry; | |
630 | int pte, pde; | |
631 | ||
632 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
633 | ||
634 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
635 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
636 | ||
637 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
638 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
639 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
640 | u32 expected; | |
641 | gen6_gtt_pte_t *pt_vaddr; | |
642 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
643 | pd_entry = readl(pd_addr + pde); | |
644 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
645 | ||
646 | if (pd_entry != expected) | |
647 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
648 | pde, | |
649 | pd_entry, | |
650 | expected); | |
651 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
652 | ||
653 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
654 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
655 | unsigned long va = | |
656 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
657 | (pte * PAGE_SIZE); | |
658 | int i; | |
659 | bool found = false; | |
660 | for (i = 0; i < 4; i++) | |
661 | if (pt_vaddr[pte + i] != scratch_pte) | |
662 | found = true; | |
663 | if (!found) | |
664 | continue; | |
665 | ||
666 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
667 | for (i = 0; i < 4; i++) { | |
668 | if (pt_vaddr[pte + i] != scratch_pte) | |
669 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
670 | else | |
671 | seq_puts(m, " SCRATCH "); | |
672 | } | |
673 | seq_puts(m, "\n"); | |
674 | } | |
675 | kunmap_atomic(pt_vaddr); | |
676 | } | |
677 | } | |
678 | ||
3e302542 | 679 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 680 | { |
853ba5d2 | 681 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
682 | gen6_gtt_pte_t __iomem *pd_addr; |
683 | uint32_t pd_entry; | |
684 | int i; | |
685 | ||
0a732870 | 686 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
687 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
688 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
689 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
690 | dma_addr_t pt_addr; | |
691 | ||
692 | pt_addr = ppgtt->pt_dma_addr[i]; | |
693 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
694 | pd_entry |= GEN6_PDE_VALID; | |
695 | ||
696 | writel(pd_entry, pd_addr + i); | |
697 | } | |
698 | readl(pd_addr); | |
3e302542 BW |
699 | } |
700 | ||
b4a74e3a | 701 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 702 | { |
b4a74e3a BW |
703 | BUG_ON(ppgtt->pd_offset & 0x3f); |
704 | ||
705 | return (ppgtt->pd_offset / 64) << 16; | |
706 | } | |
707 | ||
90252e5c BW |
708 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
709 | struct intel_ring_buffer *ring, | |
710 | bool synchronous) | |
711 | { | |
712 | struct drm_device *dev = ppgtt->base.dev; | |
713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
714 | int ret; | |
715 | ||
716 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
717 | * manually frob these bits. Ideally we could use the ring functions, | |
718 | * except our error handling makes it quite difficult (can't use | |
719 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
720 | * | |
721 | * FIXME: We should try not to special case reset | |
722 | */ | |
723 | if (synchronous || | |
724 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
725 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
726 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
727 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
728 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
733 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
734 | if (ret) | |
735 | return ret; | |
736 | ||
737 | ret = intel_ring_begin(ring, 6); | |
738 | if (ret) | |
739 | return ret; | |
740 | ||
741 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
742 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
743 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
744 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
745 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
746 | intel_ring_emit(ring, MI_NOOP); | |
747 | intel_ring_advance(ring); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
48a10389 BW |
752 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
753 | struct intel_ring_buffer *ring, | |
754 | bool synchronous) | |
755 | { | |
756 | struct drm_device *dev = ppgtt->base.dev; | |
757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
758 | int ret; | |
759 | ||
760 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
761 | * manually frob these bits. Ideally we could use the ring functions, | |
762 | * except our error handling makes it quite difficult (can't use | |
763 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
764 | * | |
765 | * FIXME: We should try not to special case reset | |
766 | */ | |
767 | if (synchronous || | |
768 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
769 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
770 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
771 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
772 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
773 | return 0; | |
774 | } | |
775 | ||
776 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
777 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
778 | if (ret) | |
779 | return ret; | |
780 | ||
781 | ret = intel_ring_begin(ring, 6); | |
782 | if (ret) | |
783 | return ret; | |
784 | ||
785 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
786 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
787 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
788 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
789 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
790 | intel_ring_emit(ring, MI_NOOP); | |
791 | intel_ring_advance(ring); | |
792 | ||
90252e5c BW |
793 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
794 | if (ring->id != RCS) { | |
795 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
796 | if (ret) | |
797 | return ret; | |
798 | } | |
799 | ||
48a10389 BW |
800 | return 0; |
801 | } | |
802 | ||
eeb9488e BW |
803 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
804 | struct intel_ring_buffer *ring, | |
805 | bool synchronous) | |
806 | { | |
807 | struct drm_device *dev = ppgtt->base.dev; | |
808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
809 | ||
48a10389 BW |
810 | if (!synchronous) |
811 | return 0; | |
812 | ||
eeb9488e BW |
813 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
814 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
815 | ||
816 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
822 | { | |
823 | struct drm_device *dev = ppgtt->base.dev; | |
824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3e302542 | 825 | struct intel_ring_buffer *ring; |
eeb9488e | 826 | int j, ret; |
3e302542 | 827 | |
eeb9488e BW |
828 | for_each_ring(ring, dev_priv, j) { |
829 | I915_WRITE(RING_MODE_GEN7(ring), | |
830 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 831 | |
d2ff7192 BW |
832 | /* We promise to do a switch later with FULL PPGTT. If this is |
833 | * aliasing, this is the one and only switch we'll do */ | |
834 | if (USES_FULL_PPGTT(dev)) | |
835 | continue; | |
6197349b | 836 | |
eeb9488e BW |
837 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
838 | if (ret) | |
839 | goto err_out; | |
840 | } | |
6197349b | 841 | |
eeb9488e | 842 | return 0; |
6197349b | 843 | |
eeb9488e BW |
844 | err_out: |
845 | for_each_ring(ring, dev_priv, j) | |
846 | I915_WRITE(RING_MODE_GEN7(ring), | |
847 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
848 | return ret; | |
849 | } | |
6197349b | 850 | |
b4a74e3a | 851 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 852 | { |
a3d67d23 | 853 | struct drm_device *dev = ppgtt->base.dev; |
50227e1c | 854 | struct drm_i915_private *dev_priv = dev->dev_private; |
3e302542 | 855 | struct intel_ring_buffer *ring; |
b4a74e3a | 856 | uint32_t ecochk, ecobits; |
3e302542 | 857 | int i; |
6197349b | 858 | |
b4a74e3a BW |
859 | ecobits = I915_READ(GAC_ECO_BITS); |
860 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 861 | |
b4a74e3a BW |
862 | ecochk = I915_READ(GAM_ECOCHK); |
863 | if (IS_HASWELL(dev)) { | |
864 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
865 | } else { | |
866 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
867 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
868 | } | |
869 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 870 | |
b4a74e3a | 871 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 872 | int ret; |
6197349b | 873 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
874 | I915_WRITE(RING_MODE_GEN7(ring), |
875 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
876 | |
877 | /* We promise to do a switch later with FULL PPGTT. If this is | |
878 | * aliasing, this is the one and only switch we'll do */ | |
879 | if (USES_FULL_PPGTT(dev)) | |
880 | continue; | |
881 | ||
eeb9488e BW |
882 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
883 | if (ret) | |
884 | return ret; | |
6197349b BW |
885 | } |
886 | ||
b4a74e3a BW |
887 | return 0; |
888 | } | |
6197349b | 889 | |
b4a74e3a BW |
890 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
891 | { | |
892 | struct drm_device *dev = ppgtt->base.dev; | |
50227e1c | 893 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a BW |
894 | struct intel_ring_buffer *ring; |
895 | uint32_t ecochk, gab_ctl, ecobits; | |
896 | int i; | |
a65c2fcd | 897 | |
b4a74e3a BW |
898 | ecobits = I915_READ(GAC_ECO_BITS); |
899 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
900 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 901 | |
b4a74e3a BW |
902 | gab_ctl = I915_READ(GAB_CTL); |
903 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
904 | ||
905 | ecochk = I915_READ(GAM_ECOCHK); | |
906 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
907 | ||
908 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 909 | |
b4a74e3a | 910 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
911 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
912 | if (ret) | |
913 | return ret; | |
6197349b | 914 | } |
b4a74e3a | 915 | |
b7c36d25 | 916 | return 0; |
6197349b BW |
917 | } |
918 | ||
1d2a314c | 919 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 920 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
921 | uint64_t start, |
922 | uint64_t length, | |
828c7908 | 923 | bool use_scratch) |
1d2a314c | 924 | { |
853ba5d2 BW |
925 | struct i915_hw_ppgtt *ppgtt = |
926 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 927 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
928 | unsigned first_entry = start >> PAGE_SHIFT; |
929 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 930 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
931 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
932 | unsigned last_pte, i; | |
1d2a314c | 933 | |
b35b380e | 934 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 935 | |
7bddb01f DV |
936 | while (num_entries) { |
937 | last_pte = first_pte + num_entries; | |
938 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
939 | last_pte = I915_PPGTT_PT_ENTRIES; | |
940 | ||
a15326a5 | 941 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 942 | |
7bddb01f DV |
943 | for (i = first_pte; i < last_pte; i++) |
944 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
945 | |
946 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 947 | |
7bddb01f DV |
948 | num_entries -= last_pte - first_pte; |
949 | first_pte = 0; | |
a15326a5 | 950 | act_pt++; |
7bddb01f | 951 | } |
1d2a314c DV |
952 | } |
953 | ||
853ba5d2 | 954 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 955 | struct sg_table *pages, |
782f1495 | 956 | uint64_t start, |
def886c3 DV |
957 | enum i915_cache_level cache_level) |
958 | { | |
853ba5d2 BW |
959 | struct i915_hw_ppgtt *ppgtt = |
960 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 961 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 962 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 963 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
964 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
965 | struct sg_page_iter sg_iter; | |
966 | ||
cc79714f | 967 | pt_vaddr = NULL; |
6e995e23 | 968 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
969 | if (pt_vaddr == NULL) |
970 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 971 | |
cc79714f CW |
972 | pt_vaddr[act_pte] = |
973 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
974 | cache_level, true); | |
6e995e23 ID |
975 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
976 | kunmap_atomic(pt_vaddr); | |
cc79714f | 977 | pt_vaddr = NULL; |
a15326a5 | 978 | act_pt++; |
6e995e23 | 979 | act_pte = 0; |
def886c3 | 980 | } |
def886c3 | 981 | } |
cc79714f CW |
982 | if (pt_vaddr) |
983 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
984 | } |
985 | ||
a00d825d | 986 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 987 | { |
3440d265 DV |
988 | int i; |
989 | ||
990 | if (ppgtt->pt_dma_addr) { | |
991 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 992 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
993 | ppgtt->pt_dma_addr[i], |
994 | 4096, PCI_DMA_BIDIRECTIONAL); | |
995 | } | |
a00d825d BW |
996 | } |
997 | ||
998 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
999 | { | |
1000 | int i; | |
3440d265 DV |
1001 | |
1002 | kfree(ppgtt->pt_dma_addr); | |
1003 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
1004 | __free_page(ppgtt->pt_pages[i]); | |
1005 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
1006 | } |
1007 | ||
a00d825d BW |
1008 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1009 | { | |
1010 | struct i915_hw_ppgtt *ppgtt = | |
1011 | container_of(vm, struct i915_hw_ppgtt, base); | |
1012 | ||
1013 | list_del(&vm->global_link); | |
1014 | drm_mm_takedown(&ppgtt->base.mm); | |
1015 | drm_mm_remove_node(&ppgtt->node); | |
1016 | ||
1017 | gen6_ppgtt_unmap_pages(ppgtt); | |
1018 | gen6_ppgtt_free(ppgtt); | |
1019 | } | |
1020 | ||
b146520f | 1021 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1022 | { |
853ba5d2 | 1023 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1024 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1025 | bool retried = false; |
b146520f | 1026 | int ret; |
1d2a314c | 1027 | |
c8d4c0d6 BW |
1028 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1029 | * allocator works in address space sizes, so it's multiplied by page | |
1030 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1031 | */ | |
1032 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1033 | alloc: |
c8d4c0d6 BW |
1034 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1035 | &ppgtt->node, GEN6_PD_SIZE, | |
1036 | GEN6_PD_ALIGN, 0, | |
1037 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1038 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1039 | if (ret == -ENOSPC && !retried) { |
1040 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1041 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d47c3ea2 | 1042 | I915_CACHE_NONE, 0); |
e3cc1995 BW |
1043 | if (ret) |
1044 | return ret; | |
1045 | ||
1046 | retried = true; | |
1047 | goto alloc; | |
1048 | } | |
c8d4c0d6 BW |
1049 | |
1050 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
1051 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1052 | |
6670a5a5 | 1053 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
b146520f BW |
1054 | return ret; |
1055 | } | |
1056 | ||
1057 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1058 | { | |
1059 | int i; | |
1060 | ||
a1e22653 | 1061 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 1062 | GFP_KERNEL); |
b146520f BW |
1063 | |
1064 | if (!ppgtt->pt_pages) | |
3440d265 | 1065 | return -ENOMEM; |
1d2a314c DV |
1066 | |
1067 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
1068 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
b146520f BW |
1069 | if (!ppgtt->pt_pages[i]) { |
1070 | gen6_ppgtt_free(ppgtt); | |
1071 | return -ENOMEM; | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1079 | { | |
1080 | int ret; | |
1081 | ||
1082 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
1086 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1087 | if (ret) { | |
1088 | drm_mm_remove_node(&ppgtt->node); | |
1089 | return ret; | |
1d2a314c DV |
1090 | } |
1091 | ||
a1e22653 | 1092 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 | 1093 | GFP_KERNEL); |
b146520f BW |
1094 | if (!ppgtt->pt_dma_addr) { |
1095 | drm_mm_remove_node(&ppgtt->node); | |
1096 | gen6_ppgtt_free(ppgtt); | |
1097 | return -ENOMEM; | |
1098 | } | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1104 | { | |
1105 | struct drm_device *dev = ppgtt->base.dev; | |
1106 | int i; | |
1d2a314c | 1107 | |
8d2e6308 BW |
1108 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
1109 | dma_addr_t pt_addr; | |
211c568b | 1110 | |
8d2e6308 BW |
1111 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
1112 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 1113 | |
8d2e6308 | 1114 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1115 | gen6_ppgtt_unmap_pages(ppgtt); |
1116 | return -EIO; | |
211c568b | 1117 | } |
b146520f | 1118 | |
8d2e6308 | 1119 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 1120 | } |
1d2a314c | 1121 | |
b146520f BW |
1122 | return 0; |
1123 | } | |
1124 | ||
1125 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1126 | { | |
1127 | struct drm_device *dev = ppgtt->base.dev; | |
1128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1129 | int ret; | |
1130 | ||
1131 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1132 | if (IS_GEN6(dev)) { | |
1133 | ppgtt->enable = gen6_ppgtt_enable; | |
1134 | ppgtt->switch_mm = gen6_mm_switch; | |
1135 | } else if (IS_HASWELL(dev)) { | |
1136 | ppgtt->enable = gen7_ppgtt_enable; | |
1137 | ppgtt->switch_mm = hsw_mm_switch; | |
1138 | } else if (IS_GEN7(dev)) { | |
1139 | ppgtt->enable = gen7_ppgtt_enable; | |
1140 | ppgtt->switch_mm = gen7_mm_switch; | |
1141 | } else | |
1142 | BUG(); | |
1143 | ||
1144 | ret = gen6_ppgtt_alloc(ppgtt); | |
1145 | if (ret) | |
1146 | return ret; | |
1147 | ||
1148 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1149 | if (ret) { | |
1150 | gen6_ppgtt_free(ppgtt); | |
1151 | return ret; | |
1152 | } | |
1153 | ||
1154 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1155 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1156 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1157 | ppgtt->base.start = 0; |
5a6c93fe | 1158 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1159 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1160 | |
c8d4c0d6 BW |
1161 | ppgtt->pd_offset = |
1162 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 1163 | |
b146520f | 1164 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1165 | |
b146520f BW |
1166 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1167 | ppgtt->node.size >> 20, | |
1168 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1169 | |
b146520f | 1170 | return 0; |
3440d265 DV |
1171 | } |
1172 | ||
246cbfb5 | 1173 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1174 | { |
1175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 1176 | int ret = 0; |
3440d265 | 1177 | |
853ba5d2 | 1178 | ppgtt->base.dev = dev; |
8407bb91 | 1179 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1180 | |
3ed124b2 BW |
1181 | if (INTEL_INFO(dev)->gen < 8) |
1182 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 1183 | else if (IS_GEN8(dev)) |
37aca44a | 1184 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
1185 | else |
1186 | BUG(); | |
1187 | ||
c7c48dfd | 1188 | if (!ret) { |
7e0d96bc | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 1190 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1191 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1192 | ppgtt->base.total); | |
7e0d96bc BW |
1193 | i915_init_vm(dev_priv, &ppgtt->base); |
1194 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1195 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1196 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1197 | ppgtt->pd_offset << 10); | |
1198 | } | |
93bd8649 | 1199 | } |
1d2a314c DV |
1200 | |
1201 | return ret; | |
1202 | } | |
1203 | ||
7e0d96bc | 1204 | static void |
6f65e29a BW |
1205 | ppgtt_bind_vma(struct i915_vma *vma, |
1206 | enum i915_cache_level cache_level, | |
1207 | u32 flags) | |
1d2a314c | 1208 | { |
782f1495 BW |
1209 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
1210 | cache_level); | |
1d2a314c DV |
1211 | } |
1212 | ||
7e0d96bc | 1213 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1214 | { |
6f65e29a | 1215 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1216 | vma->node.start, |
1217 | vma->obj->base.size, | |
6f65e29a | 1218 | true); |
7bddb01f DV |
1219 | } |
1220 | ||
a81cc00c BW |
1221 | extern int intel_iommu_gfx_mapped; |
1222 | /* Certain Gen5 chipsets require require idling the GPU before | |
1223 | * unmapping anything from the GTT when VT-d is enabled. | |
1224 | */ | |
1225 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1226 | { | |
1227 | #ifdef CONFIG_INTEL_IOMMU | |
1228 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1229 | * was loaded first. | |
1230 | */ | |
1231 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1232 | return true; | |
1233 | #endif | |
1234 | return false; | |
1235 | } | |
1236 | ||
5c042287 BW |
1237 | static bool do_idling(struct drm_i915_private *dev_priv) |
1238 | { | |
1239 | bool ret = dev_priv->mm.interruptible; | |
1240 | ||
a81cc00c | 1241 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1242 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1243 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1244 | DRM_ERROR("Couldn't idle GPU\n"); |
1245 | /* Wait a bit, in hopes it avoids the hang */ | |
1246 | udelay(10); | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | return ret; | |
1251 | } | |
1252 | ||
1253 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1254 | { | |
a81cc00c | 1255 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1256 | dev_priv->mm.interruptible = interruptible; |
1257 | } | |
1258 | ||
828c7908 BW |
1259 | void i915_check_and_clear_faults(struct drm_device *dev) |
1260 | { | |
1261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1262 | struct intel_ring_buffer *ring; | |
1263 | int i; | |
1264 | ||
1265 | if (INTEL_INFO(dev)->gen < 6) | |
1266 | return; | |
1267 | ||
1268 | for_each_ring(ring, dev_priv, i) { | |
1269 | u32 fault_reg; | |
1270 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1271 | if (fault_reg & RING_FAULT_VALID) { | |
1272 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1273 | "\tAddr: 0x%08lx\\n" | |
1274 | "\tAddress space: %s\n" | |
1275 | "\tSource ID: %d\n" | |
1276 | "\tType: %d\n", | |
1277 | fault_reg & PAGE_MASK, | |
1278 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1279 | RING_FAULT_SRCID(fault_reg), | |
1280 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1281 | I915_WRITE(RING_FAULT_REG(ring), | |
1282 | fault_reg & ~RING_FAULT_VALID); | |
1283 | } | |
1284 | } | |
1285 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1286 | } | |
1287 | ||
1288 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1289 | { | |
1290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1291 | ||
1292 | /* Don't bother messing with faults pre GEN6 as we have little | |
1293 | * documentation supporting that it's a good idea. | |
1294 | */ | |
1295 | if (INTEL_INFO(dev)->gen < 6) | |
1296 | return; | |
1297 | ||
1298 | i915_check_and_clear_faults(dev); | |
1299 | ||
1300 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1301 | dev_priv->gtt.base.start, |
1302 | dev_priv->gtt.base.total, | |
e568af1c | 1303 | true); |
828c7908 BW |
1304 | } |
1305 | ||
76aaf220 DV |
1306 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1307 | { | |
1308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1309 | struct drm_i915_gem_object *obj; |
80da2161 | 1310 | struct i915_address_space *vm; |
76aaf220 | 1311 | |
828c7908 BW |
1312 | i915_check_and_clear_faults(dev); |
1313 | ||
bee4a186 | 1314 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1315 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1316 | dev_priv->gtt.base.start, |
1317 | dev_priv->gtt.base.total, | |
828c7908 | 1318 | true); |
bee4a186 | 1319 | |
35c20a60 | 1320 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1321 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1322 | &dev_priv->gtt.base); | |
1323 | if (!vma) | |
1324 | continue; | |
1325 | ||
2c22569b | 1326 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1327 | /* The bind_vma code tries to be smart about tracking mappings. |
1328 | * Unfortunately above, we've just wiped out the mappings | |
1329 | * without telling our object about it. So we need to fake it. | |
1330 | */ | |
1331 | obj->has_global_gtt_mapping = 0; | |
1332 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1333 | } |
1334 | ||
80da2161 | 1335 | |
a2319c08 | 1336 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1337 | if (IS_CHERRYVIEW(dev)) |
1338 | chv_setup_private_ppat(dev_priv); | |
1339 | else | |
1340 | bdw_setup_private_ppat(dev_priv); | |
1341 | ||
80da2161 | 1342 | return; |
a2319c08 | 1343 | } |
80da2161 BW |
1344 | |
1345 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1346 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1347 | if (i915_is_ggtt(vm)) { | |
1348 | if (dev_priv->mm.aliasing_ppgtt) | |
1349 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1350 | continue; | |
1351 | } | |
1352 | ||
1353 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1354 | } |
1355 | ||
e76e9aeb | 1356 | i915_gem_chipset_flush(dev); |
76aaf220 | 1357 | } |
7c2e6fdf | 1358 | |
74163907 | 1359 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1360 | { |
9da3da66 | 1361 | if (obj->has_dma_mapping) |
74163907 | 1362 | return 0; |
9da3da66 CW |
1363 | |
1364 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1365 | obj->pages->sgl, obj->pages->nents, | |
1366 | PCI_DMA_BIDIRECTIONAL)) | |
1367 | return -ENOSPC; | |
1368 | ||
1369 | return 0; | |
7c2e6fdf DV |
1370 | } |
1371 | ||
94ec8f61 BW |
1372 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1373 | { | |
1374 | #ifdef writeq | |
1375 | writeq(pte, addr); | |
1376 | #else | |
1377 | iowrite32((u32)pte, addr); | |
1378 | iowrite32(pte >> 32, addr + 4); | |
1379 | #endif | |
1380 | } | |
1381 | ||
1382 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1383 | struct sg_table *st, | |
782f1495 | 1384 | uint64_t start, |
94ec8f61 BW |
1385 | enum i915_cache_level level) |
1386 | { | |
1387 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1388 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1389 | gen8_gtt_pte_t __iomem *gtt_entries = |
1390 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1391 | int i = 0; | |
1392 | struct sg_page_iter sg_iter; | |
63c42e56 | 1393 | dma_addr_t addr = 0; |
94ec8f61 BW |
1394 | |
1395 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1396 | addr = sg_dma_address(sg_iter.sg) + | |
1397 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1398 | gen8_set_pte(>t_entries[i], | |
1399 | gen8_pte_encode(addr, level, true)); | |
1400 | i++; | |
1401 | } | |
1402 | ||
1403 | /* | |
1404 | * XXX: This serves as a posting read to make sure that the PTE has | |
1405 | * actually been updated. There is some concern that even though | |
1406 | * registers and PTEs are within the same BAR that they are potentially | |
1407 | * of NUMA access patterns. Therefore, even with the way we assume | |
1408 | * hardware should work, we must keep this posting read for paranoia. | |
1409 | */ | |
1410 | if (i != 0) | |
1411 | WARN_ON(readq(>t_entries[i-1]) | |
1412 | != gen8_pte_encode(addr, level, true)); | |
1413 | ||
94ec8f61 BW |
1414 | /* This next bit makes the above posting read even more important. We |
1415 | * want to flush the TLBs only after we're certain all the PTE updates | |
1416 | * have finished. | |
1417 | */ | |
1418 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1419 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1420 | } |
1421 | ||
e76e9aeb BW |
1422 | /* |
1423 | * Binds an object into the global gtt with the specified cache level. The object | |
1424 | * will be accessible to the GPU via commands whose operands reference offsets | |
1425 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1426 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1427 | */ | |
853ba5d2 | 1428 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1429 | struct sg_table *st, |
782f1495 | 1430 | uint64_t start, |
7faf1ab2 | 1431 | enum i915_cache_level level) |
e76e9aeb | 1432 | { |
853ba5d2 | 1433 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1434 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1435 | gen6_gtt_pte_t __iomem *gtt_entries = |
1436 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1437 | int i = 0; |
1438 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1439 | dma_addr_t addr; |
1440 | ||
6e995e23 | 1441 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1442 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1443 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1444 | i++; |
e76e9aeb BW |
1445 | } |
1446 | ||
e76e9aeb BW |
1447 | /* XXX: This serves as a posting read to make sure that the PTE has |
1448 | * actually been updated. There is some concern that even though | |
1449 | * registers and PTEs are within the same BAR that they are potentially | |
1450 | * of NUMA access patterns. Therefore, even with the way we assume | |
1451 | * hardware should work, we must keep this posting read for paranoia. | |
1452 | */ | |
1453 | if (i != 0) | |
853ba5d2 | 1454 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1455 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1456 | |
1457 | /* This next bit makes the above posting read even more important. We | |
1458 | * want to flush the TLBs only after we're certain all the PTE updates | |
1459 | * have finished. | |
1460 | */ | |
1461 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1462 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1463 | } |
1464 | ||
94ec8f61 | 1465 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1466 | uint64_t start, |
1467 | uint64_t length, | |
94ec8f61 BW |
1468 | bool use_scratch) |
1469 | { | |
1470 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1471 | unsigned first_entry = start >> PAGE_SHIFT; |
1472 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1473 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1474 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1475 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1476 | int i; | |
1477 | ||
1478 | if (WARN(num_entries > max_entries, | |
1479 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1480 | first_entry, num_entries, max_entries)) | |
1481 | num_entries = max_entries; | |
1482 | ||
1483 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1484 | I915_CACHE_LLC, | |
1485 | use_scratch); | |
1486 | for (i = 0; i < num_entries; i++) | |
1487 | gen8_set_pte(>t_base[i], scratch_pte); | |
1488 | readl(gtt_base); | |
1489 | } | |
1490 | ||
853ba5d2 | 1491 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1492 | uint64_t start, |
1493 | uint64_t length, | |
828c7908 | 1494 | bool use_scratch) |
7faf1ab2 | 1495 | { |
853ba5d2 | 1496 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1497 | unsigned first_entry = start >> PAGE_SHIFT; |
1498 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1499 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1500 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1501 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1502 | int i; |
1503 | ||
1504 | if (WARN(num_entries > max_entries, | |
1505 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1506 | first_entry, num_entries, max_entries)) | |
1507 | num_entries = max_entries; | |
1508 | ||
828c7908 BW |
1509 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1510 | ||
7faf1ab2 DV |
1511 | for (i = 0; i < num_entries; i++) |
1512 | iowrite32(scratch_pte, >t_base[i]); | |
1513 | readl(gtt_base); | |
1514 | } | |
1515 | ||
6f65e29a BW |
1516 | |
1517 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1518 | enum i915_cache_level cache_level, | |
1519 | u32 unused) | |
7faf1ab2 | 1520 | { |
6f65e29a | 1521 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1522 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1523 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1524 | ||
6f65e29a BW |
1525 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1526 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1527 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1528 | } |
1529 | ||
853ba5d2 | 1530 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1531 | uint64_t start, |
1532 | uint64_t length, | |
828c7908 | 1533 | bool unused) |
7faf1ab2 | 1534 | { |
782f1495 BW |
1535 | unsigned first_entry = start >> PAGE_SHIFT; |
1536 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1537 | intel_gtt_clear_range(first_entry, num_entries); |
1538 | } | |
1539 | ||
6f65e29a BW |
1540 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1541 | { | |
1542 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1543 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1544 | |
6f65e29a BW |
1545 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1546 | vma->obj->has_global_gtt_mapping = 0; | |
1547 | intel_gtt_clear_range(first, size); | |
1548 | } | |
7faf1ab2 | 1549 | |
6f65e29a BW |
1550 | static void ggtt_bind_vma(struct i915_vma *vma, |
1551 | enum i915_cache_level cache_level, | |
1552 | u32 flags) | |
d5bd1449 | 1553 | { |
6f65e29a | 1554 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1555 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1556 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1557 | |
6f65e29a BW |
1558 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1559 | * or we have a global mapping already but the cacheability flags have | |
1560 | * changed, set the global PTEs. | |
1561 | * | |
1562 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1563 | * instead if none of the above hold true. | |
1564 | * | |
1565 | * NB: A global mapping should only be needed for special regions like | |
1566 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1567 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1568 | */ | |
1569 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1570 | if (!obj->has_global_gtt_mapping || | |
1571 | (cache_level != obj->cache_level)) { | |
782f1495 BW |
1572 | vma->vm->insert_entries(vma->vm, obj->pages, |
1573 | vma->node.start, | |
6f65e29a BW |
1574 | cache_level); |
1575 | obj->has_global_gtt_mapping = 1; | |
1576 | } | |
1577 | } | |
d5bd1449 | 1578 | |
6f65e29a BW |
1579 | if (dev_priv->mm.aliasing_ppgtt && |
1580 | (!obj->has_aliasing_ppgtt_mapping || | |
1581 | (cache_level != obj->cache_level))) { | |
1582 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1583 | appgtt->base.insert_entries(&appgtt->base, | |
782f1495 BW |
1584 | vma->obj->pages, |
1585 | vma->node.start, | |
1586 | cache_level); | |
6f65e29a BW |
1587 | vma->obj->has_aliasing_ppgtt_mapping = 1; |
1588 | } | |
d5bd1449 CW |
1589 | } |
1590 | ||
6f65e29a | 1591 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1592 | { |
6f65e29a | 1593 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1594 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1595 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a BW |
1596 | |
1597 | if (obj->has_global_gtt_mapping) { | |
782f1495 BW |
1598 | vma->vm->clear_range(vma->vm, |
1599 | vma->node.start, | |
1600 | obj->base.size, | |
6f65e29a BW |
1601 | true); |
1602 | obj->has_global_gtt_mapping = 0; | |
1603 | } | |
74898d7e | 1604 | |
6f65e29a BW |
1605 | if (obj->has_aliasing_ppgtt_mapping) { |
1606 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1607 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1608 | vma->node.start, |
1609 | obj->base.size, | |
6f65e29a BW |
1610 | true); |
1611 | obj->has_aliasing_ppgtt_mapping = 0; | |
1612 | } | |
74163907 DV |
1613 | } |
1614 | ||
1615 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1616 | { |
5c042287 BW |
1617 | struct drm_device *dev = obj->base.dev; |
1618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1619 | bool interruptible; | |
1620 | ||
1621 | interruptible = do_idling(dev_priv); | |
1622 | ||
9da3da66 CW |
1623 | if (!obj->has_dma_mapping) |
1624 | dma_unmap_sg(&dev->pdev->dev, | |
1625 | obj->pages->sgl, obj->pages->nents, | |
1626 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1627 | |
1628 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1629 | } |
644ec02b | 1630 | |
42d6ab48 CW |
1631 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1632 | unsigned long color, | |
1633 | unsigned long *start, | |
1634 | unsigned long *end) | |
1635 | { | |
1636 | if (node->color != color) | |
1637 | *start += 4096; | |
1638 | ||
1639 | if (!list_empty(&node->node_list)) { | |
1640 | node = list_entry(node->node_list.next, | |
1641 | struct drm_mm_node, | |
1642 | node_list); | |
1643 | if (node->allocated && node->color != color) | |
1644 | *end -= 4096; | |
1645 | } | |
1646 | } | |
fbe5d36e | 1647 | |
d7e5008f BW |
1648 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1649 | unsigned long start, | |
1650 | unsigned long mappable_end, | |
1651 | unsigned long end) | |
644ec02b | 1652 | { |
e78891ca BW |
1653 | /* Let GEM Manage all of the aperture. |
1654 | * | |
1655 | * However, leave one page at the end still bound to the scratch page. | |
1656 | * There are a number of places where the hardware apparently prefetches | |
1657 | * past the end of the object, and we've seen multiple hangs with the | |
1658 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1659 | * aperture. One page should be enough to keep any prefetching inside | |
1660 | * of the aperture. | |
1661 | */ | |
40d74980 BW |
1662 | struct drm_i915_private *dev_priv = dev->dev_private; |
1663 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1664 | struct drm_mm_node *entry; |
1665 | struct drm_i915_gem_object *obj; | |
1666 | unsigned long hole_start, hole_end; | |
644ec02b | 1667 | |
35451cb6 BW |
1668 | BUG_ON(mappable_end > end); |
1669 | ||
ed2f3452 | 1670 | /* Subtract the guard page ... */ |
40d74980 | 1671 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1672 | if (!HAS_LLC(dev)) |
93bd8649 | 1673 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1674 | |
ed2f3452 | 1675 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1676 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1677 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1678 | int ret; |
edd41a87 | 1679 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1680 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1681 | ||
1682 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1683 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1684 | if (ret) |
b3a070cc | 1685 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1686 | obj->has_global_gtt_mapping = 1; |
1687 | } | |
1688 | ||
853ba5d2 BW |
1689 | dev_priv->gtt.base.start = start; |
1690 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1691 | |
ed2f3452 | 1692 | /* Clear any non-preallocated blocks */ |
40d74980 | 1693 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1694 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1695 | hole_start, hole_end); | |
782f1495 BW |
1696 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1697 | hole_end - hole_start, true); | |
ed2f3452 CW |
1698 | } |
1699 | ||
1700 | /* And finally clear the reserved guard page */ | |
782f1495 | 1701 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
e76e9aeb BW |
1702 | } |
1703 | ||
d7e5008f BW |
1704 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1705 | { | |
1706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1707 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1708 | |
853ba5d2 | 1709 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1710 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1711 | |
e78891ca | 1712 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1713 | } |
1714 | ||
1715 | static int setup_scratch_page(struct drm_device *dev) | |
1716 | { | |
1717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1718 | struct page *page; | |
1719 | dma_addr_t dma_addr; | |
1720 | ||
1721 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1722 | if (page == NULL) | |
1723 | return -ENOMEM; | |
1724 | get_page(page); | |
1725 | set_pages_uc(page, 1); | |
1726 | ||
1727 | #ifdef CONFIG_INTEL_IOMMU | |
1728 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1729 | PCI_DMA_BIDIRECTIONAL); | |
1730 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1731 | return -EINVAL; | |
1732 | #else | |
1733 | dma_addr = page_to_phys(page); | |
1734 | #endif | |
853ba5d2 BW |
1735 | dev_priv->gtt.base.scratch.page = page; |
1736 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1737 | |
1738 | return 0; | |
1739 | } | |
1740 | ||
1741 | static void teardown_scratch_page(struct drm_device *dev) | |
1742 | { | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1744 | struct page *page = dev_priv->gtt.base.scratch.page; |
1745 | ||
1746 | set_pages_wb(page, 1); | |
1747 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1748 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1749 | put_page(page); |
1750 | __free_page(page); | |
e76e9aeb BW |
1751 | } |
1752 | ||
1753 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1754 | { | |
1755 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1756 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1757 | return snb_gmch_ctl << 20; | |
1758 | } | |
1759 | ||
9459d252 BW |
1760 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1761 | { | |
1762 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1763 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1764 | if (bdw_gmch_ctl) | |
1765 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
1766 | return bdw_gmch_ctl << 20; | |
1767 | } | |
1768 | ||
baa09f5f | 1769 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1770 | { |
1771 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1772 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1773 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1774 | } | |
1775 | ||
9459d252 BW |
1776 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1777 | { | |
1778 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1779 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1780 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1781 | } | |
1782 | ||
63340133 BW |
1783 | static int ggtt_probe_common(struct drm_device *dev, |
1784 | size_t gtt_size) | |
1785 | { | |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1787 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1788 | int ret; |
1789 | ||
1790 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1791 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1792 | (pci_resource_len(dev->pdev, 0) / 2); |
1793 | ||
21c34607 | 1794 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1795 | if (!dev_priv->gtt.gsm) { |
1796 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1797 | return -ENOMEM; | |
1798 | } | |
1799 | ||
1800 | ret = setup_scratch_page(dev); | |
1801 | if (ret) { | |
1802 | DRM_ERROR("Scratch setup failed\n"); | |
1803 | /* iounmap will also get called at remove, but meh */ | |
1804 | iounmap(dev_priv->gtt.gsm); | |
1805 | } | |
1806 | ||
1807 | return ret; | |
1808 | } | |
1809 | ||
fbe5d36e BW |
1810 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1811 | * bits. When using advanced contexts each context stores its own PAT, but | |
1812 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1813 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1814 | { |
fbe5d36e BW |
1815 | uint64_t pat; |
1816 | ||
1817 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1818 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1819 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1820 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1821 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1822 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1823 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1824 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1825 | ||
1826 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1827 | * write would work. */ | |
1828 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1829 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1830 | } | |
1831 | ||
ee0ce478 VS |
1832 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
1833 | { | |
1834 | uint64_t pat; | |
1835 | ||
1836 | /* | |
1837 | * Map WB on BDW to snooped on CHV. | |
1838 | * | |
1839 | * Only the snoop bit has meaning for CHV, the rest is | |
1840 | * ignored. | |
1841 | * | |
1842 | * Note that the harware enforces snooping for all page | |
1843 | * table accesses. The snoop bit is actually ignored for | |
1844 | * PDEs. | |
1845 | */ | |
1846 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
1847 | GEN8_PPAT(1, 0) | | |
1848 | GEN8_PPAT(2, 0) | | |
1849 | GEN8_PPAT(3, 0) | | |
1850 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
1851 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
1852 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
1853 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
1854 | ||
1855 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1856 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1857 | } | |
1858 | ||
63340133 BW |
1859 | static int gen8_gmch_probe(struct drm_device *dev, |
1860 | size_t *gtt_total, | |
1861 | size_t *stolen, | |
1862 | phys_addr_t *mappable_base, | |
1863 | unsigned long *mappable_end) | |
1864 | { | |
1865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1866 | unsigned int gtt_size; | |
1867 | u16 snb_gmch_ctl; | |
1868 | int ret; | |
1869 | ||
1870 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1871 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1872 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1873 | ||
1874 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1875 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1876 | ||
1877 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1878 | ||
1879 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1880 | ||
1881 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1882 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1883 | |
ee0ce478 VS |
1884 | if (IS_CHERRYVIEW(dev)) |
1885 | chv_setup_private_ppat(dev_priv); | |
1886 | else | |
1887 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 1888 | |
63340133 BW |
1889 | ret = ggtt_probe_common(dev, gtt_size); |
1890 | ||
94ec8f61 BW |
1891 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1892 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1893 | |
1894 | return ret; | |
1895 | } | |
1896 | ||
baa09f5f BW |
1897 | static int gen6_gmch_probe(struct drm_device *dev, |
1898 | size_t *gtt_total, | |
41907ddc BW |
1899 | size_t *stolen, |
1900 | phys_addr_t *mappable_base, | |
1901 | unsigned long *mappable_end) | |
e76e9aeb BW |
1902 | { |
1903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1904 | unsigned int gtt_size; |
e76e9aeb | 1905 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1906 | int ret; |
1907 | ||
41907ddc BW |
1908 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1909 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1910 | ||
baa09f5f BW |
1911 | /* 64/512MB is the current min/max we actually know of, but this is just |
1912 | * a coarse sanity check. | |
e76e9aeb | 1913 | */ |
41907ddc | 1914 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1915 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1916 | dev_priv->gtt.mappable_end); | |
1917 | return -ENXIO; | |
e76e9aeb BW |
1918 | } |
1919 | ||
e76e9aeb BW |
1920 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1921 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1922 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1923 | |
c4ae25ec | 1924 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1925 | |
63340133 BW |
1926 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1927 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1928 | |
63340133 | 1929 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1930 | |
853ba5d2 BW |
1931 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1932 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1933 | |
e76e9aeb BW |
1934 | return ret; |
1935 | } | |
1936 | ||
853ba5d2 | 1937 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1938 | { |
853ba5d2 BW |
1939 | |
1940 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1941 | |
1942 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1943 | iounmap(gtt->gsm); |
1944 | teardown_scratch_page(vm->dev); | |
644ec02b | 1945 | } |
baa09f5f BW |
1946 | |
1947 | static int i915_gmch_probe(struct drm_device *dev, | |
1948 | size_t *gtt_total, | |
41907ddc BW |
1949 | size_t *stolen, |
1950 | phys_addr_t *mappable_base, | |
1951 | unsigned long *mappable_end) | |
baa09f5f BW |
1952 | { |
1953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1954 | int ret; | |
1955 | ||
baa09f5f BW |
1956 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1957 | if (!ret) { | |
1958 | DRM_ERROR("failed to set up gmch\n"); | |
1959 | return -EIO; | |
1960 | } | |
1961 | ||
41907ddc | 1962 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1963 | |
1964 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1965 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 1966 | |
c0a7f818 CW |
1967 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
1968 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
1969 | ||
baa09f5f BW |
1970 | return 0; |
1971 | } | |
1972 | ||
853ba5d2 | 1973 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1974 | { |
1975 | intel_gmch_remove(); | |
1976 | } | |
1977 | ||
1978 | int i915_gem_gtt_init(struct drm_device *dev) | |
1979 | { | |
1980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1981 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1982 | int ret; |
1983 | ||
baa09f5f | 1984 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1985 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1986 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1987 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1988 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1989 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1990 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1991 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1992 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1993 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1994 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1995 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1996 | else if (INTEL_INFO(dev)->gen >= 7) |
1997 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1998 | else |
350ec881 | 1999 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2000 | } else { |
2001 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2002 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2003 | } |
2004 | ||
853ba5d2 | 2005 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2006 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2007 | if (ret) |
baa09f5f | 2008 | return ret; |
baa09f5f | 2009 | |
853ba5d2 BW |
2010 | gtt->base.dev = dev; |
2011 | ||
baa09f5f | 2012 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2013 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2014 | gtt->base.total >> 20); | |
b2f21b4d BW |
2015 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2016 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2017 | #ifdef CONFIG_INTEL_IOMMU |
2018 | if (intel_iommu_gfx_mapped) | |
2019 | DRM_INFO("VT-d active for gfx access\n"); | |
2020 | #endif | |
baa09f5f BW |
2021 | |
2022 | return 0; | |
2023 | } | |
6f65e29a BW |
2024 | |
2025 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2026 | struct i915_address_space *vm) | |
2027 | { | |
2028 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2029 | if (vma == NULL) | |
2030 | return ERR_PTR(-ENOMEM); | |
2031 | ||
2032 | INIT_LIST_HEAD(&vma->vma_link); | |
2033 | INIT_LIST_HEAD(&vma->mm_list); | |
2034 | INIT_LIST_HEAD(&vma->exec_list); | |
2035 | vma->vm = vm; | |
2036 | vma->obj = obj; | |
2037 | ||
2038 | switch (INTEL_INFO(vm->dev)->gen) { | |
2039 | case 8: | |
2040 | case 7: | |
2041 | case 6: | |
7e0d96bc BW |
2042 | if (i915_is_ggtt(vm)) { |
2043 | vma->unbind_vma = ggtt_unbind_vma; | |
2044 | vma->bind_vma = ggtt_bind_vma; | |
2045 | } else { | |
2046 | vma->unbind_vma = ppgtt_unbind_vma; | |
2047 | vma->bind_vma = ppgtt_bind_vma; | |
2048 | } | |
6f65e29a BW |
2049 | break; |
2050 | case 5: | |
2051 | case 4: | |
2052 | case 3: | |
2053 | case 2: | |
2054 | BUG_ON(!i915_is_ggtt(vm)); | |
2055 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2056 | vma->bind_vma = i915_ggtt_bind_vma; | |
2057 | break; | |
2058 | default: | |
2059 | BUG(); | |
2060 | } | |
2061 | ||
2062 | /* Keep GGTT vmas first to make debug easier */ | |
2063 | if (i915_is_ggtt(vm)) | |
2064 | list_add(&vma->vma_link, &obj->vma_list); | |
2065 | else | |
2066 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
2067 | ||
2068 | return vma; | |
2069 | } | |
2070 | ||
2071 | struct i915_vma * | |
2072 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2073 | struct i915_address_space *vm) | |
2074 | { | |
2075 | struct i915_vma *vma; | |
2076 | ||
2077 | vma = i915_gem_obj_to_vma(obj, vm); | |
2078 | if (!vma) | |
2079 | vma = __i915_gem_vma_create(obj, vm); | |
2080 | ||
2081 | return vma; | |
2082 | } |