Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
e7c2b58b | 31 | typedef uint32_t gen6_gtt_pte_t; |
f61c0609 | 32 | |
26b1ff35 BW |
33 | /* PPGTT stuff */ |
34 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
35 | ||
36 | #define GEN6_PDE_VALID (1 << 0) | |
37 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
38 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
39 | ||
40 | #define GEN6_PTE_VALID (1 << 0) | |
41 | #define GEN6_PTE_UNCACHED (1 << 1) | |
42 | #define HSW_PTE_UNCACHED (0) | |
43 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
44 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
45 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
46 | ||
e7c2b58b | 47 | static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, |
c81dbe05 BW |
48 | dma_addr_t addr, |
49 | enum i915_cache_level level) | |
54d12527 | 50 | { |
e7c2b58b | 51 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 52 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
53 | |
54 | switch (level) { | |
55 | case I915_CACHE_LLC_MLC: | |
56 | /* Haswell doesn't set L3 this way */ | |
57 | if (IS_HASWELL(dev)) | |
58 | pte |= GEN6_PTE_CACHE_LLC; | |
59 | else | |
60 | pte |= GEN6_PTE_CACHE_LLC_MLC; | |
61 | break; | |
62 | case I915_CACHE_LLC: | |
63 | pte |= GEN6_PTE_CACHE_LLC; | |
64 | break; | |
65 | case I915_CACHE_NONE: | |
66 | if (IS_HASWELL(dev)) | |
67 | pte |= HSW_PTE_UNCACHED; | |
68 | else | |
69 | pte |= GEN6_PTE_UNCACHED; | |
70 | break; | |
71 | default: | |
72 | BUG(); | |
73 | } | |
74 | ||
54d12527 BW |
75 | return pte; |
76 | } | |
77 | ||
b7c36d25 | 78 | static int gen6_ppgtt_enable(struct drm_device *dev) |
6197349b BW |
79 | { |
80 | drm_i915_private_t *dev_priv = dev->dev_private; | |
81 | uint32_t pd_offset; | |
82 | struct intel_ring_buffer *ring; | |
83 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
84 | gen6_gtt_pte_t __iomem *pd_addr; | |
85 | uint32_t pd_entry; | |
86 | int i; | |
87 | ||
88 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + | |
89 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
90 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
91 | dma_addr_t pt_addr; | |
92 | ||
93 | pt_addr = ppgtt->pt_dma_addr[i]; | |
94 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
95 | pd_entry |= GEN6_PDE_VALID; | |
96 | ||
97 | writel(pd_entry, pd_addr + i); | |
98 | } | |
99 | readl(pd_addr); | |
100 | ||
101 | pd_offset = ppgtt->pd_offset; | |
102 | pd_offset /= 64; /* in cachelines, */ | |
103 | pd_offset <<= 16; | |
104 | ||
105 | if (INTEL_INFO(dev)->gen == 6) { | |
106 | uint32_t ecochk, gab_ctl, ecobits; | |
107 | ||
108 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
109 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
110 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
111 | |
112 | gab_ctl = I915_READ(GAB_CTL); | |
113 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
114 | ||
115 | ecochk = I915_READ(GAM_ECOCHK); | |
116 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
117 | ECOCHK_PPGTT_CACHE64B); | |
118 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
119 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 120 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
121 | |
122 | ecobits = I915_READ(GAC_ECO_BITS); | |
123 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
124 | ||
a6f429a5 VS |
125 | ecochk = I915_READ(GAM_ECOCHK); |
126 | if (IS_HASWELL(dev)) { | |
127 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
128 | } else { | |
129 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
130 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
131 | } | |
132 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
133 | /* GFX_MODE is per-ring on gen7+ */ |
134 | } | |
135 | ||
136 | for_each_ring(ring, dev_priv, i) { | |
137 | if (INTEL_INFO(dev)->gen >= 7) | |
138 | I915_WRITE(RING_MODE_GEN7(ring), | |
139 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
140 | ||
141 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
142 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
143 | } | |
b7c36d25 | 144 | return 0; |
6197349b BW |
145 | } |
146 | ||
1d2a314c | 147 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 148 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
149 | unsigned first_entry, |
150 | unsigned num_entries) | |
151 | { | |
e7c2b58b | 152 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 153 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
154 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
155 | unsigned last_pte, i; | |
1d2a314c | 156 | |
960e3e42 DV |
157 | scratch_pte = gen6_pte_encode(ppgtt->dev, |
158 | ppgtt->scratch_page_dma_addr, | |
159 | I915_CACHE_LLC); | |
1d2a314c | 160 | |
7bddb01f DV |
161 | while (num_entries) { |
162 | last_pte = first_pte + num_entries; | |
163 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
164 | last_pte = I915_PPGTT_PT_ENTRIES; | |
165 | ||
a15326a5 | 166 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 167 | |
7bddb01f DV |
168 | for (i = first_pte; i < last_pte; i++) |
169 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
170 | |
171 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 172 | |
7bddb01f DV |
173 | num_entries -= last_pte - first_pte; |
174 | first_pte = 0; | |
a15326a5 | 175 | act_pt++; |
7bddb01f | 176 | } |
1d2a314c DV |
177 | } |
178 | ||
def886c3 DV |
179 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
180 | struct sg_table *pages, | |
181 | unsigned first_entry, | |
182 | enum i915_cache_level cache_level) | |
183 | { | |
e7c2b58b | 184 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 185 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
186 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
187 | struct sg_page_iter sg_iter; | |
188 | ||
a15326a5 | 189 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
190 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
191 | dma_addr_t page_addr; | |
192 | ||
2db76d7c | 193 | page_addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 | 194 | pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr, |
6ddc4fc7 | 195 | cache_level); |
6e995e23 ID |
196 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
197 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
198 | act_pt++; |
199 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 200 | act_pte = 0; |
def886c3 | 201 | |
def886c3 | 202 | } |
def886c3 | 203 | } |
6e995e23 | 204 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
205 | } |
206 | ||
3440d265 | 207 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 208 | { |
3440d265 DV |
209 | int i; |
210 | ||
211 | if (ppgtt->pt_dma_addr) { | |
212 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
213 | pci_unmap_page(ppgtt->dev->pdev, | |
214 | ppgtt->pt_dma_addr[i], | |
215 | 4096, PCI_DMA_BIDIRECTIONAL); | |
216 | } | |
217 | ||
218 | kfree(ppgtt->pt_dma_addr); | |
219 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
220 | __free_page(ppgtt->pt_pages[i]); | |
221 | kfree(ppgtt->pt_pages); | |
222 | kfree(ppgtt); | |
223 | } | |
224 | ||
225 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
226 | { | |
227 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 228 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 229 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
230 | int i; |
231 | int ret = -ENOMEM; | |
232 | ||
233 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
234 | * entries. For aliasing ppgtt support we just steal them at the end for | |
235 | * now. */ | |
a54c0c27 BW |
236 | first_pd_entry_in_global_pt = |
237 | gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES; | |
1d2a314c | 238 | |
1d2a314c | 239 | ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES; |
6197349b | 240 | ppgtt->enable = gen6_ppgtt_enable; |
def886c3 DV |
241 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
242 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 243 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
244 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
245 | GFP_KERNEL); | |
246 | if (!ppgtt->pt_pages) | |
3440d265 | 247 | return -ENOMEM; |
1d2a314c DV |
248 | |
249 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
250 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
251 | if (!ppgtt->pt_pages[i]) | |
252 | goto err_pt_alloc; | |
253 | } | |
254 | ||
8d2e6308 BW |
255 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
256 | GFP_KERNEL); | |
257 | if (!ppgtt->pt_dma_addr) | |
258 | goto err_pt_alloc; | |
1d2a314c | 259 | |
8d2e6308 BW |
260 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
261 | dma_addr_t pt_addr; | |
211c568b | 262 | |
8d2e6308 BW |
263 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
264 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 265 | |
8d2e6308 BW |
266 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
267 | ret = -EIO; | |
268 | goto err_pd_pin; | |
1d2a314c | 269 | |
211c568b | 270 | } |
8d2e6308 | 271 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 272 | } |
1d2a314c | 273 | |
def886c3 DV |
274 | ppgtt->clear_range(ppgtt, 0, |
275 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 276 | |
e7c2b58b | 277 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 278 | |
1d2a314c DV |
279 | return 0; |
280 | ||
281 | err_pd_pin: | |
282 | if (ppgtt->pt_dma_addr) { | |
283 | for (i--; i >= 0; i--) | |
284 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
285 | 4096, PCI_DMA_BIDIRECTIONAL); | |
286 | } | |
287 | err_pt_alloc: | |
288 | kfree(ppgtt->pt_dma_addr); | |
289 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
290 | if (ppgtt->pt_pages[i]) | |
291 | __free_page(ppgtt->pt_pages[i]); | |
292 | } | |
293 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
294 | |
295 | return ret; | |
296 | } | |
297 | ||
298 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
299 | { | |
300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
301 | struct i915_hw_ppgtt *ppgtt; | |
302 | int ret; | |
303 | ||
304 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
305 | if (!ppgtt) | |
306 | return -ENOMEM; | |
307 | ||
308 | ppgtt->dev = dev; | |
1e7d12d4 | 309 | ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma; |
3440d265 | 310 | |
3ed124b2 BW |
311 | if (INTEL_INFO(dev)->gen < 8) |
312 | ret = gen6_ppgtt_init(ppgtt); | |
313 | else | |
314 | BUG(); | |
315 | ||
3440d265 DV |
316 | if (ret) |
317 | kfree(ppgtt); | |
318 | else | |
319 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
320 | |
321 | return ret; | |
322 | } | |
323 | ||
324 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
325 | { | |
326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
327 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
328 | |
329 | if (!ppgtt) | |
330 | return; | |
331 | ||
3440d265 | 332 | ppgtt->cleanup(ppgtt); |
5963cf04 | 333 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
334 | } |
335 | ||
7bddb01f DV |
336 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
337 | struct drm_i915_gem_object *obj, | |
338 | enum i915_cache_level cache_level) | |
339 | { | |
def886c3 DV |
340 | ppgtt->insert_entries(ppgtt, obj->pages, |
341 | obj->gtt_space->start >> PAGE_SHIFT, | |
342 | cache_level); | |
7bddb01f DV |
343 | } |
344 | ||
345 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
346 | struct drm_i915_gem_object *obj) | |
347 | { | |
def886c3 DV |
348 | ppgtt->clear_range(ppgtt, |
349 | obj->gtt_space->start >> PAGE_SHIFT, | |
350 | obj->base.size >> PAGE_SHIFT); | |
7bddb01f DV |
351 | } |
352 | ||
a81cc00c BW |
353 | extern int intel_iommu_gfx_mapped; |
354 | /* Certain Gen5 chipsets require require idling the GPU before | |
355 | * unmapping anything from the GTT when VT-d is enabled. | |
356 | */ | |
357 | static inline bool needs_idle_maps(struct drm_device *dev) | |
358 | { | |
359 | #ifdef CONFIG_INTEL_IOMMU | |
360 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
361 | * was loaded first. | |
362 | */ | |
363 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
364 | return true; | |
365 | #endif | |
366 | return false; | |
367 | } | |
368 | ||
5c042287 BW |
369 | static bool do_idling(struct drm_i915_private *dev_priv) |
370 | { | |
371 | bool ret = dev_priv->mm.interruptible; | |
372 | ||
a81cc00c | 373 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 374 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 375 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
376 | DRM_ERROR("Couldn't idle GPU\n"); |
377 | /* Wait a bit, in hopes it avoids the hang */ | |
378 | udelay(10); | |
379 | } | |
380 | } | |
381 | ||
382 | return ret; | |
383 | } | |
384 | ||
385 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
386 | { | |
a81cc00c | 387 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
388 | dev_priv->mm.interruptible = interruptible; |
389 | } | |
390 | ||
76aaf220 DV |
391 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
392 | { | |
393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 394 | struct drm_i915_gem_object *obj; |
76aaf220 | 395 | |
bee4a186 | 396 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
397 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
398 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 399 | |
6c085a72 | 400 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { |
a8e93126 | 401 | i915_gem_clflush_object(obj); |
74163907 | 402 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
403 | } |
404 | ||
e76e9aeb | 405 | i915_gem_chipset_flush(dev); |
76aaf220 | 406 | } |
7c2e6fdf | 407 | |
74163907 | 408 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 409 | { |
9da3da66 | 410 | if (obj->has_dma_mapping) |
74163907 | 411 | return 0; |
9da3da66 CW |
412 | |
413 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
414 | obj->pages->sgl, obj->pages->nents, | |
415 | PCI_DMA_BIDIRECTIONAL)) | |
416 | return -ENOSPC; | |
417 | ||
418 | return 0; | |
7c2e6fdf DV |
419 | } |
420 | ||
e76e9aeb BW |
421 | /* |
422 | * Binds an object into the global gtt with the specified cache level. The object | |
423 | * will be accessible to the GPU via commands whose operands reference offsets | |
424 | * within the global GTT as well as accessible by the GPU through the GMADR | |
425 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
426 | */ | |
7faf1ab2 DV |
427 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
428 | struct sg_table *st, | |
429 | unsigned int first_entry, | |
430 | enum i915_cache_level level) | |
e76e9aeb | 431 | { |
e76e9aeb | 432 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
433 | gen6_gtt_pte_t __iomem *gtt_entries = |
434 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
435 | int i = 0; |
436 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
437 | dma_addr_t addr; |
438 | ||
6e995e23 | 439 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 440 | addr = sg_page_iter_dma_address(&sg_iter); |
6e995e23 ID |
441 | iowrite32(gen6_pte_encode(dev, addr, level), >t_entries[i]); |
442 | i++; | |
e76e9aeb BW |
443 | } |
444 | ||
e76e9aeb BW |
445 | /* XXX: This serves as a posting read to make sure that the PTE has |
446 | * actually been updated. There is some concern that even though | |
447 | * registers and PTEs are within the same BAR that they are potentially | |
448 | * of NUMA access patterns. Therefore, even with the way we assume | |
449 | * hardware should work, we must keep this posting read for paranoia. | |
450 | */ | |
451 | if (i != 0) | |
960e3e42 DV |
452 | WARN_ON(readl(>t_entries[i-1]) |
453 | != gen6_pte_encode(dev, addr, level)); | |
0f9b91c7 BW |
454 | |
455 | /* This next bit makes the above posting read even more important. We | |
456 | * want to flush the TLBs only after we're certain all the PTE updates | |
457 | * have finished. | |
458 | */ | |
459 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
460 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
461 | } |
462 | ||
7faf1ab2 DV |
463 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
464 | unsigned int first_entry, | |
465 | unsigned int num_entries) | |
466 | { | |
467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
468 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
469 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 470 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
471 | int i; |
472 | ||
473 | if (WARN(num_entries > max_entries, | |
474 | "First entry = %d; Num entries = %d (max=%d)\n", | |
475 | first_entry, num_entries, max_entries)) | |
476 | num_entries = max_entries; | |
477 | ||
960e3e42 DV |
478 | scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma, |
479 | I915_CACHE_LLC); | |
7faf1ab2 DV |
480 | for (i = 0; i < num_entries; i++) |
481 | iowrite32(scratch_pte, >t_base[i]); | |
482 | readl(gtt_base); | |
483 | } | |
484 | ||
485 | ||
486 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
487 | struct sg_table *st, | |
488 | unsigned int pg_start, | |
489 | enum i915_cache_level cache_level) | |
490 | { | |
491 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
492 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
493 | ||
494 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
495 | ||
496 | } | |
497 | ||
498 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
499 | unsigned int first_entry, | |
500 | unsigned int num_entries) | |
501 | { | |
502 | intel_gtt_clear_range(first_entry, num_entries); | |
503 | } | |
504 | ||
505 | ||
74163907 DV |
506 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
507 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
508 | { |
509 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
510 | struct drm_i915_private *dev_priv = dev->dev_private; |
511 | ||
512 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
513 | obj->gtt_space->start >> PAGE_SHIFT, | |
514 | cache_level); | |
d5bd1449 | 515 | |
74898d7e | 516 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
517 | } |
518 | ||
05394f39 | 519 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 520 | { |
7faf1ab2 DV |
521 | struct drm_device *dev = obj->base.dev; |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
523 | ||
524 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
525 | obj->gtt_space->start >> PAGE_SHIFT, | |
526 | obj->base.size >> PAGE_SHIFT); | |
74898d7e DV |
527 | |
528 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
529 | } |
530 | ||
531 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 532 | { |
5c042287 BW |
533 | struct drm_device *dev = obj->base.dev; |
534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
535 | bool interruptible; | |
536 | ||
537 | interruptible = do_idling(dev_priv); | |
538 | ||
9da3da66 CW |
539 | if (!obj->has_dma_mapping) |
540 | dma_unmap_sg(&dev->pdev->dev, | |
541 | obj->pages->sgl, obj->pages->nents, | |
542 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
543 | |
544 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 545 | } |
644ec02b | 546 | |
42d6ab48 CW |
547 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
548 | unsigned long color, | |
549 | unsigned long *start, | |
550 | unsigned long *end) | |
551 | { | |
552 | if (node->color != color) | |
553 | *start += 4096; | |
554 | ||
555 | if (!list_empty(&node->node_list)) { | |
556 | node = list_entry(node->node_list.next, | |
557 | struct drm_mm_node, | |
558 | node_list); | |
559 | if (node->allocated && node->color != color) | |
560 | *end -= 4096; | |
561 | } | |
562 | } | |
d7e5008f BW |
563 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
564 | unsigned long start, | |
565 | unsigned long mappable_end, | |
566 | unsigned long end) | |
644ec02b | 567 | { |
e78891ca BW |
568 | /* Let GEM Manage all of the aperture. |
569 | * | |
570 | * However, leave one page at the end still bound to the scratch page. | |
571 | * There are a number of places where the hardware apparently prefetches | |
572 | * past the end of the object, and we've seen multiple hangs with the | |
573 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
574 | * aperture. One page should be enough to keep any prefetching inside | |
575 | * of the aperture. | |
576 | */ | |
644ec02b | 577 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
578 | struct drm_mm_node *entry; |
579 | struct drm_i915_gem_object *obj; | |
580 | unsigned long hole_start, hole_end; | |
644ec02b | 581 | |
35451cb6 BW |
582 | BUG_ON(mappable_end > end); |
583 | ||
ed2f3452 | 584 | /* Subtract the guard page ... */ |
d1dd20a9 | 585 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
586 | if (!HAS_LLC(dev)) |
587 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 588 | |
ed2f3452 CW |
589 | /* Mark any preallocated objects as occupied */ |
590 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) { | |
591 | DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n", | |
592 | obj->gtt_offset, obj->base.size); | |
593 | ||
594 | BUG_ON(obj->gtt_space != I915_GTT_RESERVED); | |
595 | obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space, | |
596 | obj->gtt_offset, | |
597 | obj->base.size, | |
598 | false); | |
599 | obj->has_global_gtt_mapping = 1; | |
600 | } | |
601 | ||
5d4545ae | 602 | dev_priv->gtt.start = start; |
5d4545ae | 603 | dev_priv->gtt.total = end - start; |
644ec02b | 604 | |
ed2f3452 CW |
605 | /* Clear any non-preallocated blocks */ |
606 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
607 | hole_start, hole_end) { | |
608 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
609 | hole_start, hole_end); | |
7faf1ab2 DV |
610 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
611 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
612 | } |
613 | ||
614 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 615 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
616 | } |
617 | ||
d7e5008f BW |
618 | static bool |
619 | intel_enable_ppgtt(struct drm_device *dev) | |
620 | { | |
621 | if (i915_enable_ppgtt >= 0) | |
622 | return i915_enable_ppgtt; | |
623 | ||
624 | #ifdef CONFIG_INTEL_IOMMU | |
625 | /* Disable ppgtt on SNB if VT-d is on. */ | |
626 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
627 | return false; | |
628 | #endif | |
629 | ||
630 | return true; | |
631 | } | |
632 | ||
633 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
634 | { | |
635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 637 | |
a54c0c27 | 638 | gtt_size = dev_priv->gtt.total; |
93d18799 | 639 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
640 | |
641 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 642 | int ret; |
3eb1c005 BW |
643 | |
644 | if (INTEL_INFO(dev)->gen <= 7) { | |
645 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
646 | * aperture accordingly when using aliasing ppgtt. */ | |
647 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
648 | } | |
d7e5008f BW |
649 | |
650 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
651 | ||
652 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 653 | if (!ret) |
d7e5008f | 654 | return; |
e78891ca BW |
655 | |
656 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
657 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
658 | gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
d7e5008f | 659 | } |
e78891ca | 660 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
661 | } |
662 | ||
663 | static int setup_scratch_page(struct drm_device *dev) | |
664 | { | |
665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
666 | struct page *page; | |
667 | dma_addr_t dma_addr; | |
668 | ||
669 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
670 | if (page == NULL) | |
671 | return -ENOMEM; | |
672 | get_page(page); | |
673 | set_pages_uc(page, 1); | |
674 | ||
675 | #ifdef CONFIG_INTEL_IOMMU | |
676 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
677 | PCI_DMA_BIDIRECTIONAL); | |
678 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
679 | return -EINVAL; | |
680 | #else | |
681 | dma_addr = page_to_phys(page); | |
682 | #endif | |
9c61a32d BW |
683 | dev_priv->gtt.scratch_page = page; |
684 | dev_priv->gtt.scratch_page_dma = dma_addr; | |
e76e9aeb BW |
685 | |
686 | return 0; | |
687 | } | |
688 | ||
689 | static void teardown_scratch_page(struct drm_device *dev) | |
690 | { | |
691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9c61a32d BW |
692 | set_pages_wb(dev_priv->gtt.scratch_page, 1); |
693 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma, | |
e76e9aeb | 694 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
9c61a32d BW |
695 | put_page(dev_priv->gtt.scratch_page); |
696 | __free_page(dev_priv->gtt.scratch_page); | |
e76e9aeb BW |
697 | } |
698 | ||
699 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
700 | { | |
701 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
702 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
703 | return snb_gmch_ctl << 20; | |
704 | } | |
705 | ||
baa09f5f | 706 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
707 | { |
708 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
709 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
710 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
711 | } | |
712 | ||
baa09f5f | 713 | static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl) |
03752f5b BW |
714 | { |
715 | static const int stolen_decoder[] = { | |
716 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352}; | |
717 | snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT; | |
718 | snb_gmch_ctl &= IVB_GMCH_GMS_MASK; | |
719 | return stolen_decoder[snb_gmch_ctl] << 20; | |
720 | } | |
721 | ||
baa09f5f BW |
722 | static int gen6_gmch_probe(struct drm_device *dev, |
723 | size_t *gtt_total, | |
41907ddc BW |
724 | size_t *stolen, |
725 | phys_addr_t *mappable_base, | |
726 | unsigned long *mappable_end) | |
e76e9aeb BW |
727 | { |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
729 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 730 | unsigned int gtt_size; |
e76e9aeb | 731 | u16 snb_gmch_ctl; |
e76e9aeb BW |
732 | int ret; |
733 | ||
41907ddc BW |
734 | *mappable_base = pci_resource_start(dev->pdev, 2); |
735 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
736 | ||
baa09f5f BW |
737 | /* 64/512MB is the current min/max we actually know of, but this is just |
738 | * a coarse sanity check. | |
e76e9aeb | 739 | */ |
41907ddc | 740 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
741 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
742 | dev_priv->gtt.mappable_end); | |
743 | return -ENXIO; | |
e76e9aeb BW |
744 | } |
745 | ||
e76e9aeb BW |
746 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
747 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 748 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 749 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 750 | |
086ddcce | 751 | if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) |
baa09f5f BW |
752 | *stolen = gen7_get_stolen_size(snb_gmch_ctl); |
753 | else | |
754 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); | |
e76e9aeb | 755 | |
e7c2b58b | 756 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 757 | |
a93e4161 BW |
758 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
759 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
760 | (pci_resource_len(dev->pdev, 0) / 2); | |
761 | ||
baa09f5f | 762 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 763 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 764 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 765 | return -ENOMEM; |
e76e9aeb BW |
766 | } |
767 | ||
baa09f5f BW |
768 | ret = setup_scratch_page(dev); |
769 | if (ret) | |
770 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 771 | |
7faf1ab2 DV |
772 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
773 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
774 | ||
e76e9aeb BW |
775 | return ret; |
776 | } | |
777 | ||
d93c6233 | 778 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
779 | { |
780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 781 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 782 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 783 | } |
baa09f5f BW |
784 | |
785 | static int i915_gmch_probe(struct drm_device *dev, | |
786 | size_t *gtt_total, | |
41907ddc BW |
787 | size_t *stolen, |
788 | phys_addr_t *mappable_base, | |
789 | unsigned long *mappable_end) | |
baa09f5f BW |
790 | { |
791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
792 | int ret; | |
793 | ||
baa09f5f BW |
794 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
795 | if (!ret) { | |
796 | DRM_ERROR("failed to set up gmch\n"); | |
797 | return -EIO; | |
798 | } | |
799 | ||
41907ddc | 800 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
801 | |
802 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
803 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
804 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static void i915_gmch_remove(struct drm_device *dev) | |
810 | { | |
811 | intel_gmch_remove(); | |
812 | } | |
813 | ||
814 | int i915_gem_gtt_init(struct drm_device *dev) | |
815 | { | |
816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
817 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
818 | int ret; |
819 | ||
baa09f5f BW |
820 | if (INTEL_INFO(dev)->gen <= 5) { |
821 | dev_priv->gtt.gtt_probe = i915_gmch_probe; | |
822 | dev_priv->gtt.gtt_remove = i915_gmch_remove; | |
823 | } else { | |
824 | dev_priv->gtt.gtt_probe = gen6_gmch_probe; | |
825 | dev_priv->gtt.gtt_remove = gen6_gmch_remove; | |
826 | } | |
827 | ||
828 | ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total, | |
41907ddc BW |
829 | &dev_priv->gtt.stolen_size, |
830 | >t->mappable_base, | |
831 | >t->mappable_end); | |
a54c0c27 | 832 | if (ret) |
baa09f5f | 833 | return ret; |
baa09f5f | 834 | |
baa09f5f BW |
835 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
836 | DRM_INFO("Memory usable by graphics device = %zdM\n", | |
837 | dev_priv->gtt.total >> 20); | |
838 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", | |
839 | dev_priv->gtt.mappable_end >> 20); | |
840 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", | |
841 | dev_priv->gtt.stolen_size >> 20); | |
842 | ||
843 | return 0; | |
844 | } |