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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
0e46ce2e | 25 | #include <linux/seq_file.h> |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/i915_drm.h> | |
76aaf220 DV |
28 | #include "i915_drv.h" |
29 | #include "i915_trace.h" | |
30 | #include "intel_drv.h" | |
31 | ||
6670a5a5 BW |
32 | #define GEN6_PPGTT_PD_ENTRIES 512 |
33 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
d31eb10e | 34 | typedef uint64_t gen8_gtt_pte_t; |
37aca44a | 35 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; |
6670a5a5 | 36 | |
26b1ff35 BW |
37 | /* PPGTT stuff */ |
38 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 39 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
40 | |
41 | #define GEN6_PDE_VALID (1 << 0) | |
42 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
43 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
44 | ||
45 | #define GEN6_PTE_VALID (1 << 0) | |
46 | #define GEN6_PTE_UNCACHED (1 << 1) | |
47 | #define HSW_PTE_UNCACHED (0) | |
48 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
350ec881 | 49 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) |
26b1ff35 | 50 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) |
0d8ff15e BW |
51 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
52 | ||
53 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
54 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
55 | */ | |
56 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
57 | (((bits) & 0x8) << (11 - 3))) | |
87a6b688 | 58 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) |
0d8ff15e | 59 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) |
4d15c145 | 60 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
c51e9701 | 61 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) |
651d794f | 62 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) |
c51e9701 | 63 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) |
26b1ff35 | 64 | |
459108b8 | 65 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
37aca44a BW |
66 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) |
67 | #define GEN8_LEGACY_PDPS 4 | |
68 | ||
fbe5d36e BW |
69 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) |
70 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
71 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
72 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
73 | ||
6f65e29a BW |
74 | static void ppgtt_bind_vma(struct i915_vma *vma, |
75 | enum i915_cache_level cache_level, | |
76 | u32 flags); | |
77 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
eeb9488e | 78 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt); |
6f65e29a | 79 | |
94ec8f61 BW |
80 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
81 | enum i915_cache_level level, | |
82 | bool valid) | |
83 | { | |
84 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
85 | pte |= addr; | |
fbe5d36e BW |
86 | if (level != I915_CACHE_NONE) |
87 | pte |= PPAT_CACHED_INDEX; | |
88 | else | |
89 | pte |= PPAT_UNCACHED_INDEX; | |
94ec8f61 BW |
90 | return pte; |
91 | } | |
92 | ||
b1fe6673 BW |
93 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
94 | dma_addr_t addr, | |
95 | enum i915_cache_level level) | |
96 | { | |
97 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
98 | pde |= addr; | |
99 | if (level != I915_CACHE_NONE) | |
100 | pde |= PPAT_CACHED_PDE_INDEX; | |
101 | else | |
102 | pde |= PPAT_UNCACHED_INDEX; | |
103 | return pde; | |
104 | } | |
105 | ||
350ec881 | 106 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e BW |
107 | enum i915_cache_level level, |
108 | bool valid) | |
54d12527 | 109 | { |
b35b380e | 110 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 111 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
112 | |
113 | switch (level) { | |
350ec881 CW |
114 | case I915_CACHE_L3_LLC: |
115 | case I915_CACHE_LLC: | |
116 | pte |= GEN6_PTE_CACHE_LLC; | |
117 | break; | |
118 | case I915_CACHE_NONE: | |
119 | pte |= GEN6_PTE_UNCACHED; | |
120 | break; | |
121 | default: | |
122 | WARN_ON(1); | |
123 | } | |
124 | ||
125 | return pte; | |
126 | } | |
127 | ||
128 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e BW |
129 | enum i915_cache_level level, |
130 | bool valid) | |
350ec881 | 131 | { |
b35b380e | 132 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
133 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
134 | ||
135 | switch (level) { | |
136 | case I915_CACHE_L3_LLC: | |
137 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
138 | break; |
139 | case I915_CACHE_LLC: | |
140 | pte |= GEN6_PTE_CACHE_LLC; | |
141 | break; | |
142 | case I915_CACHE_NONE: | |
9119708c | 143 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
144 | break; |
145 | default: | |
350ec881 | 146 | WARN_ON(1); |
e7210c3c BW |
147 | } |
148 | ||
54d12527 BW |
149 | return pte; |
150 | } | |
151 | ||
93c34e70 KG |
152 | #define BYT_PTE_WRITEABLE (1 << 1) |
153 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
154 | ||
80a74f7f | 155 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e BW |
156 | enum i915_cache_level level, |
157 | bool valid) | |
93c34e70 | 158 | { |
b35b380e | 159 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
160 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
161 | ||
162 | /* Mark the page as writeable. Other platforms don't have a | |
163 | * setting for read-only/writable, so this matches that behavior. | |
164 | */ | |
165 | pte |= BYT_PTE_WRITEABLE; | |
166 | ||
167 | if (level != I915_CACHE_NONE) | |
168 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
169 | ||
170 | return pte; | |
171 | } | |
172 | ||
80a74f7f | 173 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e BW |
174 | enum i915_cache_level level, |
175 | bool valid) | |
9119708c | 176 | { |
b35b380e | 177 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 178 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
179 | |
180 | if (level != I915_CACHE_NONE) | |
87a6b688 | 181 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
182 | |
183 | return pte; | |
184 | } | |
185 | ||
4d15c145 | 186 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e BW |
187 | enum i915_cache_level level, |
188 | bool valid) | |
4d15c145 | 189 | { |
b35b380e | 190 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
191 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
192 | ||
651d794f CW |
193 | switch (level) { |
194 | case I915_CACHE_NONE: | |
195 | break; | |
196 | case I915_CACHE_WT: | |
c51e9701 | 197 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
198 | break; |
199 | default: | |
c51e9701 | 200 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
201 | break; |
202 | } | |
4d15c145 BW |
203 | |
204 | return pte; | |
205 | } | |
206 | ||
94e409c1 BW |
207 | /* Broadwell Page Directory Pointer Descriptors */ |
208 | static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry, | |
e178f705 | 209 | uint64_t val, bool synchronous) |
94e409c1 | 210 | { |
e178f705 | 211 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
94e409c1 BW |
212 | int ret; |
213 | ||
214 | BUG_ON(entry >= 4); | |
215 | ||
e178f705 BW |
216 | if (synchronous) { |
217 | I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32); | |
218 | I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val); | |
219 | return 0; | |
220 | } | |
221 | ||
94e409c1 BW |
222 | ret = intel_ring_begin(ring, 6); |
223 | if (ret) | |
224 | return ret; | |
225 | ||
226 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
227 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
228 | intel_ring_emit(ring, (u32)(val >> 32)); | |
229 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
230 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
231 | intel_ring_emit(ring, (u32)(val)); | |
232 | intel_ring_advance(ring); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
eeb9488e BW |
237 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
238 | struct intel_ring_buffer *ring, | |
239 | bool synchronous) | |
94e409c1 | 240 | { |
eeb9488e | 241 | int i, ret; |
94e409c1 BW |
242 | |
243 | /* bit of a hack to find the actual last used pd */ | |
244 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
245 | ||
94e409c1 BW |
246 | for (i = used_pd - 1; i >= 0; i--) { |
247 | dma_addr_t addr = ppgtt->pd_dma_addr[i]; | |
eeb9488e BW |
248 | ret = gen8_write_pdp(ring, i, addr, synchronous); |
249 | if (ret) | |
250 | return ret; | |
94e409c1 | 251 | } |
d595bd4b | 252 | |
eeb9488e | 253 | return 0; |
94e409c1 BW |
254 | } |
255 | ||
459108b8 BW |
256 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
257 | unsigned first_entry, | |
258 | unsigned num_entries, | |
259 | bool use_scratch) | |
260 | { | |
261 | struct i915_hw_ppgtt *ppgtt = | |
262 | container_of(vm, struct i915_hw_ppgtt, base); | |
263 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
264 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
265 | unsigned first_pte = first_entry % GEN8_PTES_PER_PAGE; | |
266 | unsigned last_pte, i; | |
267 | ||
268 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
269 | I915_CACHE_LLC, use_scratch); | |
270 | ||
271 | while (num_entries) { | |
272 | struct page *page_table = &ppgtt->gen8_pt_pages[act_pt]; | |
273 | ||
274 | last_pte = first_pte + num_entries; | |
275 | if (last_pte > GEN8_PTES_PER_PAGE) | |
276 | last_pte = GEN8_PTES_PER_PAGE; | |
277 | ||
278 | pt_vaddr = kmap_atomic(page_table); | |
279 | ||
280 | for (i = first_pte; i < last_pte; i++) | |
281 | pt_vaddr[i] = scratch_pte; | |
282 | ||
283 | kunmap_atomic(pt_vaddr); | |
284 | ||
285 | num_entries -= last_pte - first_pte; | |
286 | first_pte = 0; | |
287 | act_pt++; | |
288 | } | |
289 | } | |
290 | ||
9df15b49 BW |
291 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
292 | struct sg_table *pages, | |
293 | unsigned first_entry, | |
294 | enum i915_cache_level cache_level) | |
295 | { | |
296 | struct i915_hw_ppgtt *ppgtt = | |
297 | container_of(vm, struct i915_hw_ppgtt, base); | |
298 | gen8_gtt_pte_t *pt_vaddr; | |
299 | unsigned act_pt = first_entry / GEN8_PTES_PER_PAGE; | |
300 | unsigned act_pte = first_entry % GEN8_PTES_PER_PAGE; | |
301 | struct sg_page_iter sg_iter; | |
302 | ||
6f1cc993 | 303 | pt_vaddr = NULL; |
9df15b49 | 304 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
6f1cc993 CW |
305 | if (pt_vaddr == NULL) |
306 | pt_vaddr = kmap_atomic(&ppgtt->gen8_pt_pages[act_pt]); | |
9df15b49 | 307 | |
6f1cc993 CW |
308 | pt_vaddr[act_pte] = |
309 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), | |
310 | cache_level, true); | |
9df15b49 BW |
311 | if (++act_pte == GEN8_PTES_PER_PAGE) { |
312 | kunmap_atomic(pt_vaddr); | |
6f1cc993 | 313 | pt_vaddr = NULL; |
9df15b49 | 314 | act_pt++; |
9df15b49 | 315 | act_pte = 0; |
9df15b49 BW |
316 | } |
317 | } | |
6f1cc993 CW |
318 | if (pt_vaddr) |
319 | kunmap_atomic(pt_vaddr); | |
9df15b49 BW |
320 | } |
321 | ||
b45a6715 BW |
322 | static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) |
323 | { | |
324 | int i; | |
325 | ||
326 | for (i = 0; i < ppgtt->num_pd_pages ; i++) | |
327 | kfree(ppgtt->gen8_pt_dma_addr[i]); | |
328 | ||
329 | __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); | |
330 | __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); | |
331 | } | |
332 | ||
333 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
334 | { | |
335 | int i, j; | |
336 | ||
337 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
338 | /* TODO: In the future we'll support sparse mappings, so this | |
339 | * will have to change. */ | |
340 | if (!ppgtt->pd_dma_addr[i]) | |
341 | continue; | |
342 | ||
343 | pci_unmap_page(ppgtt->base.dev->pdev, | |
344 | ppgtt->pd_dma_addr[i], | |
345 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
346 | ||
347 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
348 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
349 | if (addr) | |
350 | pci_unmap_page(ppgtt->base.dev->pdev, | |
351 | addr, | |
352 | PAGE_SIZE, | |
353 | PCI_DMA_BIDIRECTIONAL); | |
354 | ||
355 | } | |
356 | } | |
357 | } | |
358 | ||
37aca44a BW |
359 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
360 | { | |
361 | struct i915_hw_ppgtt *ppgtt = | |
362 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 363 | |
7e0d96bc | 364 | list_del(&vm->global_link); |
686e1f6f BW |
365 | drm_mm_takedown(&vm->mm); |
366 | ||
b45a6715 BW |
367 | gen8_ppgtt_unmap_pages(ppgtt); |
368 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
369 | } |
370 | ||
371 | /** | |
372 | * GEN8 legacy ppgtt programming is accomplished through 4 PDP registers with a | |
373 | * net effect resembling a 2-level page table in normal x86 terms. Each PDP | |
374 | * represents 1GB of memory | |
375 | * 4 * 512 * 512 * 4096 = 4GB legacy 32b address space. | |
376 | * | |
377 | * TODO: Do something with the size parameter | |
378 | **/ | |
379 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) | |
380 | { | |
381 | struct page *pt_pages; | |
382 | int i, j, ret = -ENOMEM; | |
383 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); | |
384 | const int num_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; | |
385 | ||
386 | if (size % (1<<30)) | |
387 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
388 | ||
389 | /* FIXME: split allocation into smaller pieces. For now we only ever do | |
390 | * this once, but with full PPGTT, the multiple contiguous allocations | |
391 | * will be bad. | |
392 | */ | |
393 | ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT)); | |
394 | if (!ppgtt->pd_pages) | |
395 | return -ENOMEM; | |
396 | ||
397 | pt_pages = alloc_pages(GFP_KERNEL, get_order(num_pt_pages << PAGE_SHIFT)); | |
398 | if (!pt_pages) { | |
399 | __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT)); | |
400 | return -ENOMEM; | |
401 | } | |
402 | ||
403 | ppgtt->gen8_pt_pages = pt_pages; | |
404 | ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT); | |
405 | ppgtt->num_pt_pages = 1 << get_order(num_pt_pages << PAGE_SHIFT); | |
406 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
94e409c1 | 407 | ppgtt->enable = gen8_ppgtt_enable; |
eeb9488e | 408 | ppgtt->switch_mm = gen8_mm_switch; |
459108b8 | 409 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
9df15b49 | 410 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
37aca44a | 411 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
686e1f6f BW |
412 | ppgtt->base.start = 0; |
413 | ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE; | |
37aca44a BW |
414 | |
415 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); | |
416 | ||
417 | /* | |
418 | * - Create a mapping for the page directories. | |
419 | * - For each page directory: | |
420 | * allocate space for page table mappings. | |
421 | * map each page table | |
422 | */ | |
423 | for (i = 0; i < max_pdp; i++) { | |
424 | dma_addr_t temp; | |
425 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
426 | &ppgtt->pd_pages[i], 0, | |
427 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
428 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
429 | goto err_out; | |
430 | ||
431 | ppgtt->pd_dma_addr[i] = temp; | |
432 | ||
433 | ppgtt->gen8_pt_dma_addr[i] = kmalloc(sizeof(dma_addr_t) * GEN8_PDES_PER_PAGE, GFP_KERNEL); | |
434 | if (!ppgtt->gen8_pt_dma_addr[i]) | |
435 | goto err_out; | |
436 | ||
437 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
438 | struct page *p = &pt_pages[i * GEN8_PDES_PER_PAGE + j]; | |
439 | temp = pci_map_page(ppgtt->base.dev->pdev, | |
440 | p, 0, PAGE_SIZE, | |
441 | PCI_DMA_BIDIRECTIONAL); | |
442 | ||
443 | if (pci_dma_mapping_error(ppgtt->base.dev->pdev, temp)) | |
444 | goto err_out; | |
445 | ||
446 | ppgtt->gen8_pt_dma_addr[i][j] = temp; | |
447 | } | |
448 | } | |
449 | ||
b1fe6673 BW |
450 | /* For now, the PPGTT helper functions all require that the PDEs are |
451 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we | |
452 | * will never need to touch the PDEs again */ | |
453 | for (i = 0; i < max_pdp; i++) { | |
454 | gen8_ppgtt_pde_t *pd_vaddr; | |
455 | pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]); | |
456 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
457 | dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; | |
458 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, | |
459 | I915_CACHE_LLC); | |
460 | } | |
461 | kunmap_atomic(pd_vaddr); | |
462 | } | |
463 | ||
459108b8 BW |
464 | ppgtt->base.clear_range(&ppgtt->base, 0, |
465 | ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE, | |
466 | true); | |
467 | ||
37aca44a BW |
468 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
469 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
470 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
471 | ppgtt->num_pt_pages, | |
472 | (ppgtt->num_pt_pages - num_pt_pages) + | |
473 | size % (1<<30)); | |
28cf5415 | 474 | return 0; |
37aca44a BW |
475 | |
476 | err_out: | |
477 | ppgtt->base.cleanup(&ppgtt->base); | |
478 | return ret; | |
479 | } | |
480 | ||
87d60b63 BW |
481 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
482 | { | |
483 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
484 | struct i915_address_space *vm = &ppgtt->base; | |
485 | gen6_gtt_pte_t __iomem *pd_addr; | |
486 | gen6_gtt_pte_t scratch_pte; | |
487 | uint32_t pd_entry; | |
488 | int pte, pde; | |
489 | ||
490 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); | |
491 | ||
492 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
493 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
494 | ||
495 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
496 | ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries); | |
497 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { | |
498 | u32 expected; | |
499 | gen6_gtt_pte_t *pt_vaddr; | |
500 | dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde]; | |
501 | pd_entry = readl(pd_addr + pde); | |
502 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
503 | ||
504 | if (pd_entry != expected) | |
505 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
506 | pde, | |
507 | pd_entry, | |
508 | expected); | |
509 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
510 | ||
511 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]); | |
512 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { | |
513 | unsigned long va = | |
514 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
515 | (pte * PAGE_SIZE); | |
516 | int i; | |
517 | bool found = false; | |
518 | for (i = 0; i < 4; i++) | |
519 | if (pt_vaddr[pte + i] != scratch_pte) | |
520 | found = true; | |
521 | if (!found) | |
522 | continue; | |
523 | ||
524 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
525 | for (i = 0; i < 4; i++) { | |
526 | if (pt_vaddr[pte + i] != scratch_pte) | |
527 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
528 | else | |
529 | seq_puts(m, " SCRATCH "); | |
530 | } | |
531 | seq_puts(m, "\n"); | |
532 | } | |
533 | kunmap_atomic(pt_vaddr); | |
534 | } | |
535 | } | |
536 | ||
3e302542 | 537 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 538 | { |
853ba5d2 | 539 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
540 | gen6_gtt_pte_t __iomem *pd_addr; |
541 | uint32_t pd_entry; | |
542 | int i; | |
543 | ||
0a732870 | 544 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
545 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
546 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
547 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
548 | dma_addr_t pt_addr; | |
549 | ||
550 | pt_addr = ppgtt->pt_dma_addr[i]; | |
551 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
552 | pd_entry |= GEN6_PDE_VALID; | |
553 | ||
554 | writel(pd_entry, pd_addr + i); | |
555 | } | |
556 | readl(pd_addr); | |
3e302542 BW |
557 | } |
558 | ||
b4a74e3a | 559 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 560 | { |
b4a74e3a BW |
561 | BUG_ON(ppgtt->pd_offset & 0x3f); |
562 | ||
563 | return (ppgtt->pd_offset / 64) << 16; | |
564 | } | |
565 | ||
90252e5c BW |
566 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
567 | struct intel_ring_buffer *ring, | |
568 | bool synchronous) | |
569 | { | |
570 | struct drm_device *dev = ppgtt->base.dev; | |
571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
572 | int ret; | |
573 | ||
574 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
575 | * manually frob these bits. Ideally we could use the ring functions, | |
576 | * except our error handling makes it quite difficult (can't use | |
577 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
578 | * | |
579 | * FIXME: We should try not to special case reset | |
580 | */ | |
581 | if (synchronous || | |
582 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
583 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
584 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
585 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
586 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
587 | return 0; | |
588 | } | |
589 | ||
590 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
591 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
592 | if (ret) | |
593 | return ret; | |
594 | ||
595 | ret = intel_ring_begin(ring, 6); | |
596 | if (ret) | |
597 | return ret; | |
598 | ||
599 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
600 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
601 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
602 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
603 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
604 | intel_ring_emit(ring, MI_NOOP); | |
605 | intel_ring_advance(ring); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
48a10389 BW |
610 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
611 | struct intel_ring_buffer *ring, | |
612 | bool synchronous) | |
613 | { | |
614 | struct drm_device *dev = ppgtt->base.dev; | |
615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
616 | int ret; | |
617 | ||
618 | /* If we're in reset, we can assume the GPU is sufficiently idle to | |
619 | * manually frob these bits. Ideally we could use the ring functions, | |
620 | * except our error handling makes it quite difficult (can't use | |
621 | * intel_ring_begin, ring->flush, or intel_ring_advance) | |
622 | * | |
623 | * FIXME: We should try not to special case reset | |
624 | */ | |
625 | if (synchronous || | |
626 | i915_reset_in_progress(&dev_priv->gpu_error)) { | |
627 | WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt); | |
628 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
629 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
630 | POSTING_READ(RING_PP_DIR_BASE(ring)); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | /* NB: TLBs must be flushed and invalidated before a switch */ | |
635 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
636 | if (ret) | |
637 | return ret; | |
638 | ||
639 | ret = intel_ring_begin(ring, 6); | |
640 | if (ret) | |
641 | return ret; | |
642 | ||
643 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
644 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
645 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
646 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
647 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
648 | intel_ring_emit(ring, MI_NOOP); | |
649 | intel_ring_advance(ring); | |
650 | ||
90252e5c BW |
651 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
652 | if (ring->id != RCS) { | |
653 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
654 | if (ret) | |
655 | return ret; | |
656 | } | |
657 | ||
48a10389 BW |
658 | return 0; |
659 | } | |
660 | ||
eeb9488e BW |
661 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
662 | struct intel_ring_buffer *ring, | |
663 | bool synchronous) | |
664 | { | |
665 | struct drm_device *dev = ppgtt->base.dev; | |
666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
667 | ||
48a10389 BW |
668 | if (!synchronous) |
669 | return 0; | |
670 | ||
eeb9488e BW |
671 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
672 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
673 | ||
674 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
679 | static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) | |
680 | { | |
681 | struct drm_device *dev = ppgtt->base.dev; | |
682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3e302542 | 683 | struct intel_ring_buffer *ring; |
eeb9488e | 684 | int j, ret; |
3e302542 | 685 | |
eeb9488e BW |
686 | for_each_ring(ring, dev_priv, j) { |
687 | I915_WRITE(RING_MODE_GEN7(ring), | |
688 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
3e302542 | 689 | |
d2ff7192 BW |
690 | /* We promise to do a switch later with FULL PPGTT. If this is |
691 | * aliasing, this is the one and only switch we'll do */ | |
692 | if (USES_FULL_PPGTT(dev)) | |
693 | continue; | |
6197349b | 694 | |
eeb9488e BW |
695 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
696 | if (ret) | |
697 | goto err_out; | |
698 | } | |
6197349b | 699 | |
eeb9488e | 700 | return 0; |
6197349b | 701 | |
eeb9488e BW |
702 | err_out: |
703 | for_each_ring(ring, dev_priv, j) | |
704 | I915_WRITE(RING_MODE_GEN7(ring), | |
705 | _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE)); | |
706 | return ret; | |
707 | } | |
6197349b | 708 | |
b4a74e3a | 709 | static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 710 | { |
a3d67d23 | 711 | struct drm_device *dev = ppgtt->base.dev; |
3e302542 | 712 | drm_i915_private_t *dev_priv = dev->dev_private; |
3e302542 | 713 | struct intel_ring_buffer *ring; |
b4a74e3a | 714 | uint32_t ecochk, ecobits; |
3e302542 | 715 | int i; |
6197349b | 716 | |
b4a74e3a BW |
717 | ecobits = I915_READ(GAC_ECO_BITS); |
718 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 719 | |
b4a74e3a BW |
720 | ecochk = I915_READ(GAM_ECOCHK); |
721 | if (IS_HASWELL(dev)) { | |
722 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
723 | } else { | |
724 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
725 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
726 | } | |
727 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 728 | |
b4a74e3a | 729 | for_each_ring(ring, dev_priv, i) { |
eeb9488e | 730 | int ret; |
6197349b | 731 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
732 | I915_WRITE(RING_MODE_GEN7(ring), |
733 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
d2ff7192 BW |
734 | |
735 | /* We promise to do a switch later with FULL PPGTT. If this is | |
736 | * aliasing, this is the one and only switch we'll do */ | |
737 | if (USES_FULL_PPGTT(dev)) | |
738 | continue; | |
739 | ||
eeb9488e BW |
740 | ret = ppgtt->switch_mm(ppgtt, ring, true); |
741 | if (ret) | |
742 | return ret; | |
6197349b BW |
743 | } |
744 | ||
b4a74e3a BW |
745 | return 0; |
746 | } | |
6197349b | 747 | |
b4a74e3a BW |
748 | static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt) |
749 | { | |
750 | struct drm_device *dev = ppgtt->base.dev; | |
751 | drm_i915_private_t *dev_priv = dev->dev_private; | |
752 | struct intel_ring_buffer *ring; | |
753 | uint32_t ecochk, gab_ctl, ecobits; | |
754 | int i; | |
a65c2fcd | 755 | |
b4a74e3a BW |
756 | ecobits = I915_READ(GAC_ECO_BITS); |
757 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
758 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 759 | |
b4a74e3a BW |
760 | gab_ctl = I915_READ(GAB_CTL); |
761 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
762 | ||
763 | ecochk = I915_READ(GAM_ECOCHK); | |
764 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
765 | ||
766 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 767 | |
b4a74e3a | 768 | for_each_ring(ring, dev_priv, i) { |
eeb9488e BW |
769 | int ret = ppgtt->switch_mm(ppgtt, ring, true); |
770 | if (ret) | |
771 | return ret; | |
6197349b | 772 | } |
b4a74e3a | 773 | |
b7c36d25 | 774 | return 0; |
6197349b BW |
775 | } |
776 | ||
1d2a314c | 777 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 778 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
1d2a314c | 779 | unsigned first_entry, |
828c7908 BW |
780 | unsigned num_entries, |
781 | bool use_scratch) | |
1d2a314c | 782 | { |
853ba5d2 BW |
783 | struct i915_hw_ppgtt *ppgtt = |
784 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 785 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 786 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
787 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
788 | unsigned last_pte, i; | |
1d2a314c | 789 | |
b35b380e | 790 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
1d2a314c | 791 | |
7bddb01f DV |
792 | while (num_entries) { |
793 | last_pte = first_pte + num_entries; | |
794 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
795 | last_pte = I915_PPGTT_PT_ENTRIES; | |
796 | ||
a15326a5 | 797 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 798 | |
7bddb01f DV |
799 | for (i = first_pte; i < last_pte; i++) |
800 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
801 | |
802 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 803 | |
7bddb01f DV |
804 | num_entries -= last_pte - first_pte; |
805 | first_pte = 0; | |
a15326a5 | 806 | act_pt++; |
7bddb01f | 807 | } |
1d2a314c DV |
808 | } |
809 | ||
853ba5d2 | 810 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 DV |
811 | struct sg_table *pages, |
812 | unsigned first_entry, | |
813 | enum i915_cache_level cache_level) | |
814 | { | |
853ba5d2 BW |
815 | struct i915_hw_ppgtt *ppgtt = |
816 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 817 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 818 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
819 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
820 | struct sg_page_iter sg_iter; | |
821 | ||
cc79714f | 822 | pt_vaddr = NULL; |
6e995e23 | 823 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f CW |
824 | if (pt_vaddr == NULL) |
825 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 826 | |
cc79714f CW |
827 | pt_vaddr[act_pte] = |
828 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
829 | cache_level, true); | |
6e995e23 ID |
830 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
831 | kunmap_atomic(pt_vaddr); | |
cc79714f | 832 | pt_vaddr = NULL; |
a15326a5 | 833 | act_pt++; |
6e995e23 | 834 | act_pte = 0; |
def886c3 | 835 | } |
def886c3 | 836 | } |
cc79714f CW |
837 | if (pt_vaddr) |
838 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
839 | } |
840 | ||
853ba5d2 | 841 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
1d2a314c | 842 | { |
853ba5d2 BW |
843 | struct i915_hw_ppgtt *ppgtt = |
844 | container_of(vm, struct i915_hw_ppgtt, base); | |
3440d265 DV |
845 | int i; |
846 | ||
7e0d96bc | 847 | list_del(&vm->global_link); |
93bd8649 | 848 | drm_mm_takedown(&ppgtt->base.mm); |
c8d4c0d6 | 849 | drm_mm_remove_node(&ppgtt->node); |
93bd8649 | 850 | |
3440d265 DV |
851 | if (ppgtt->pt_dma_addr) { |
852 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
853ba5d2 | 853 | pci_unmap_page(ppgtt->base.dev->pdev, |
3440d265 DV |
854 | ppgtt->pt_dma_addr[i], |
855 | 4096, PCI_DMA_BIDIRECTIONAL); | |
856 | } | |
857 | ||
858 | kfree(ppgtt->pt_dma_addr); | |
859 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
860 | __free_page(ppgtt->pt_pages[i]); | |
861 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
862 | } |
863 | ||
864 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
865 | { | |
c8d4c0d6 BW |
866 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) |
867 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
853ba5d2 | 868 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 869 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 870 | bool retried = false; |
c8d4c0d6 | 871 | int i, ret; |
1d2a314c | 872 | |
c8d4c0d6 BW |
873 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
874 | * allocator works in address space sizes, so it's multiplied by page | |
875 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
876 | */ | |
877 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 878 | alloc: |
c8d4c0d6 BW |
879 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
880 | &ppgtt->node, GEN6_PD_SIZE, | |
881 | GEN6_PD_ALIGN, 0, | |
882 | 0, dev_priv->gtt.base.total, | |
883 | DRM_MM_SEARCH_DEFAULT); | |
e3cc1995 BW |
884 | if (ret == -ENOSPC && !retried) { |
885 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
886 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d47c3ea2 | 887 | I915_CACHE_NONE, 0); |
e3cc1995 BW |
888 | if (ret) |
889 | return ret; | |
890 | ||
891 | retried = true; | |
892 | goto alloc; | |
893 | } | |
c8d4c0d6 BW |
894 | |
895 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) | |
896 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 897 | |
08c45263 | 898 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
6670a5a5 | 899 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
48a10389 | 900 | if (IS_GEN6(dev)) { |
b4a74e3a | 901 | ppgtt->enable = gen6_ppgtt_enable; |
48a10389 | 902 | ppgtt->switch_mm = gen6_mm_switch; |
90252e5c BW |
903 | } else if (IS_HASWELL(dev)) { |
904 | ppgtt->enable = gen7_ppgtt_enable; | |
905 | ppgtt->switch_mm = hsw_mm_switch; | |
48a10389 | 906 | } else if (IS_GEN7(dev)) { |
b4a74e3a | 907 | ppgtt->enable = gen7_ppgtt_enable; |
48a10389 BW |
908 | ppgtt->switch_mm = gen7_mm_switch; |
909 | } else | |
b4a74e3a | 910 | BUG(); |
853ba5d2 BW |
911 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
912 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
913 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
914 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; | |
686e1f6f BW |
915 | ppgtt->base.start = 0; |
916 | ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; | |
a1e22653 | 917 | ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), |
1d2a314c | 918 | GFP_KERNEL); |
c8d4c0d6 BW |
919 | if (!ppgtt->pt_pages) { |
920 | drm_mm_remove_node(&ppgtt->node); | |
3440d265 | 921 | return -ENOMEM; |
c8d4c0d6 | 922 | } |
1d2a314c DV |
923 | |
924 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
925 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
926 | if (!ppgtt->pt_pages[i]) | |
927 | goto err_pt_alloc; | |
928 | } | |
929 | ||
a1e22653 | 930 | ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t), |
8d2e6308 BW |
931 | GFP_KERNEL); |
932 | if (!ppgtt->pt_dma_addr) | |
933 | goto err_pt_alloc; | |
1d2a314c | 934 | |
8d2e6308 BW |
935 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
936 | dma_addr_t pt_addr; | |
211c568b | 937 | |
8d2e6308 BW |
938 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
939 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 940 | |
8d2e6308 BW |
941 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
942 | ret = -EIO; | |
943 | goto err_pd_pin; | |
1d2a314c | 944 | |
211c568b | 945 | } |
8d2e6308 | 946 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 947 | } |
1d2a314c | 948 | |
853ba5d2 | 949 | ppgtt->base.clear_range(&ppgtt->base, 0, |
828c7908 | 950 | ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true); |
87d60b63 | 951 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 952 | |
c8d4c0d6 BW |
953 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
954 | ppgtt->node.size >> 20, | |
955 | ppgtt->node.start / PAGE_SIZE); | |
956 | ppgtt->pd_offset = | |
957 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); | |
1d2a314c | 958 | |
1d2a314c DV |
959 | return 0; |
960 | ||
961 | err_pd_pin: | |
962 | if (ppgtt->pt_dma_addr) { | |
963 | for (i--; i >= 0; i--) | |
964 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
965 | 4096, PCI_DMA_BIDIRECTIONAL); | |
966 | } | |
967 | err_pt_alloc: | |
968 | kfree(ppgtt->pt_dma_addr); | |
969 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
970 | if (ppgtt->pt_pages[i]) | |
971 | __free_page(ppgtt->pt_pages[i]); | |
972 | } | |
973 | kfree(ppgtt->pt_pages); | |
c8d4c0d6 | 974 | drm_mm_remove_node(&ppgtt->node); |
3440d265 DV |
975 | |
976 | return ret; | |
977 | } | |
978 | ||
246cbfb5 | 979 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
980 | { |
981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6660add | 982 | int ret = 0; |
3440d265 | 983 | |
853ba5d2 | 984 | ppgtt->base.dev = dev; |
3440d265 | 985 | |
3ed124b2 BW |
986 | if (INTEL_INFO(dev)->gen < 8) |
987 | ret = gen6_ppgtt_init(ppgtt); | |
8fe6bd23 | 988 | else if (IS_GEN8(dev)) |
37aca44a | 989 | ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
3ed124b2 BW |
990 | else |
991 | BUG(); | |
992 | ||
c7c48dfd | 993 | if (!ret) { |
7e0d96bc | 994 | struct drm_i915_private *dev_priv = dev->dev_private; |
c7c48dfd | 995 | kref_init(&ppgtt->ref); |
93bd8649 BW |
996 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
997 | ppgtt->base.total); | |
7e0d96bc BW |
998 | i915_init_vm(dev_priv, &ppgtt->base); |
999 | if (INTEL_INFO(dev)->gen < 8) { | |
9f273d48 | 1000 | gen6_write_pdes(ppgtt); |
7e0d96bc BW |
1001 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
1002 | ppgtt->pd_offset << 10); | |
1003 | } | |
93bd8649 | 1004 | } |
1d2a314c DV |
1005 | |
1006 | return ret; | |
1007 | } | |
1008 | ||
7e0d96bc | 1009 | static void |
6f65e29a BW |
1010 | ppgtt_bind_vma(struct i915_vma *vma, |
1011 | enum i915_cache_level cache_level, | |
1012 | u32 flags) | |
1d2a314c | 1013 | { |
6f65e29a | 1014 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
1d2a314c | 1015 | |
6f65e29a | 1016 | WARN_ON(flags); |
1d2a314c | 1017 | |
6f65e29a | 1018 | vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); |
1d2a314c DV |
1019 | } |
1020 | ||
7e0d96bc | 1021 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1022 | { |
6f65e29a | 1023 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7bddb01f | 1024 | |
6f65e29a BW |
1025 | vma->vm->clear_range(vma->vm, |
1026 | entry, | |
1027 | vma->obj->base.size >> PAGE_SHIFT, | |
1028 | true); | |
7bddb01f DV |
1029 | } |
1030 | ||
a81cc00c BW |
1031 | extern int intel_iommu_gfx_mapped; |
1032 | /* Certain Gen5 chipsets require require idling the GPU before | |
1033 | * unmapping anything from the GTT when VT-d is enabled. | |
1034 | */ | |
1035 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1036 | { | |
1037 | #ifdef CONFIG_INTEL_IOMMU | |
1038 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1039 | * was loaded first. | |
1040 | */ | |
1041 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1042 | return true; | |
1043 | #endif | |
1044 | return false; | |
1045 | } | |
1046 | ||
5c042287 BW |
1047 | static bool do_idling(struct drm_i915_private *dev_priv) |
1048 | { | |
1049 | bool ret = dev_priv->mm.interruptible; | |
1050 | ||
a81cc00c | 1051 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1052 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1053 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1054 | DRM_ERROR("Couldn't idle GPU\n"); |
1055 | /* Wait a bit, in hopes it avoids the hang */ | |
1056 | udelay(10); | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1064 | { | |
a81cc00c | 1065 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1066 | dev_priv->mm.interruptible = interruptible; |
1067 | } | |
1068 | ||
828c7908 BW |
1069 | void i915_check_and_clear_faults(struct drm_device *dev) |
1070 | { | |
1071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1072 | struct intel_ring_buffer *ring; | |
1073 | int i; | |
1074 | ||
1075 | if (INTEL_INFO(dev)->gen < 6) | |
1076 | return; | |
1077 | ||
1078 | for_each_ring(ring, dev_priv, i) { | |
1079 | u32 fault_reg; | |
1080 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1081 | if (fault_reg & RING_FAULT_VALID) { | |
1082 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
1083 | "\tAddr: 0x%08lx\\n" | |
1084 | "\tAddress space: %s\n" | |
1085 | "\tSource ID: %d\n" | |
1086 | "\tType: %d\n", | |
1087 | fault_reg & PAGE_MASK, | |
1088 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1089 | RING_FAULT_SRCID(fault_reg), | |
1090 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1091 | I915_WRITE(RING_FAULT_REG(ring), | |
1092 | fault_reg & ~RING_FAULT_VALID); | |
1093 | } | |
1094 | } | |
1095 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1096 | } | |
1097 | ||
1098 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) | |
1099 | { | |
1100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1101 | ||
1102 | /* Don't bother messing with faults pre GEN6 as we have little | |
1103 | * documentation supporting that it's a good idea. | |
1104 | */ | |
1105 | if (INTEL_INFO(dev)->gen < 6) | |
1106 | return; | |
1107 | ||
1108 | i915_check_and_clear_faults(dev); | |
1109 | ||
1110 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
1111 | dev_priv->gtt.base.start / PAGE_SIZE, | |
1112 | dev_priv->gtt.base.total / PAGE_SIZE, | |
1113 | false); | |
1114 | } | |
1115 | ||
76aaf220 DV |
1116 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1117 | { | |
1118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1119 | struct drm_i915_gem_object *obj; |
80da2161 | 1120 | struct i915_address_space *vm; |
76aaf220 | 1121 | |
828c7908 BW |
1122 | i915_check_and_clear_faults(dev); |
1123 | ||
bee4a186 | 1124 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 BW |
1125 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
1126 | dev_priv->gtt.base.start / PAGE_SIZE, | |
828c7908 BW |
1127 | dev_priv->gtt.base.total / PAGE_SIZE, |
1128 | true); | |
bee4a186 | 1129 | |
35c20a60 | 1130 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1131 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1132 | &dev_priv->gtt.base); | |
1133 | if (!vma) | |
1134 | continue; | |
1135 | ||
2c22569b | 1136 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1137 | /* The bind_vma code tries to be smart about tracking mappings. |
1138 | * Unfortunately above, we've just wiped out the mappings | |
1139 | * without telling our object about it. So we need to fake it. | |
1140 | */ | |
1141 | obj->has_global_gtt_mapping = 0; | |
1142 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); | |
76aaf220 DV |
1143 | } |
1144 | ||
80da2161 BW |
1145 | |
1146 | if (INTEL_INFO(dev)->gen >= 8) | |
1147 | return; | |
1148 | ||
1149 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1150 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1151 | if (i915_is_ggtt(vm)) { | |
1152 | if (dev_priv->mm.aliasing_ppgtt) | |
1153 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1154 | continue; | |
1155 | } | |
1156 | ||
1157 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1158 | } |
1159 | ||
e76e9aeb | 1160 | i915_gem_chipset_flush(dev); |
76aaf220 | 1161 | } |
7c2e6fdf | 1162 | |
74163907 | 1163 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1164 | { |
9da3da66 | 1165 | if (obj->has_dma_mapping) |
74163907 | 1166 | return 0; |
9da3da66 CW |
1167 | |
1168 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1169 | obj->pages->sgl, obj->pages->nents, | |
1170 | PCI_DMA_BIDIRECTIONAL)) | |
1171 | return -ENOSPC; | |
1172 | ||
1173 | return 0; | |
7c2e6fdf DV |
1174 | } |
1175 | ||
94ec8f61 BW |
1176 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1177 | { | |
1178 | #ifdef writeq | |
1179 | writeq(pte, addr); | |
1180 | #else | |
1181 | iowrite32((u32)pte, addr); | |
1182 | iowrite32(pte >> 32, addr + 4); | |
1183 | #endif | |
1184 | } | |
1185 | ||
1186 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1187 | struct sg_table *st, | |
1188 | unsigned int first_entry, | |
1189 | enum i915_cache_level level) | |
1190 | { | |
1191 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1192 | gen8_gtt_pte_t __iomem *gtt_entries = | |
1193 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1194 | int i = 0; | |
1195 | struct sg_page_iter sg_iter; | |
1196 | dma_addr_t addr; | |
1197 | ||
1198 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1199 | addr = sg_dma_address(sg_iter.sg) + | |
1200 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1201 | gen8_set_pte(>t_entries[i], | |
1202 | gen8_pte_encode(addr, level, true)); | |
1203 | i++; | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * XXX: This serves as a posting read to make sure that the PTE has | |
1208 | * actually been updated. There is some concern that even though | |
1209 | * registers and PTEs are within the same BAR that they are potentially | |
1210 | * of NUMA access patterns. Therefore, even with the way we assume | |
1211 | * hardware should work, we must keep this posting read for paranoia. | |
1212 | */ | |
1213 | if (i != 0) | |
1214 | WARN_ON(readq(>t_entries[i-1]) | |
1215 | != gen8_pte_encode(addr, level, true)); | |
1216 | ||
94ec8f61 BW |
1217 | /* This next bit makes the above posting read even more important. We |
1218 | * want to flush the TLBs only after we're certain all the PTE updates | |
1219 | * have finished. | |
1220 | */ | |
1221 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1222 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1223 | } |
1224 | ||
e76e9aeb BW |
1225 | /* |
1226 | * Binds an object into the global gtt with the specified cache level. The object | |
1227 | * will be accessible to the GPU via commands whose operands reference offsets | |
1228 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1229 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1230 | */ | |
853ba5d2 | 1231 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 DV |
1232 | struct sg_table *st, |
1233 | unsigned int first_entry, | |
1234 | enum i915_cache_level level) | |
e76e9aeb | 1235 | { |
853ba5d2 | 1236 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1237 | gen6_gtt_pte_t __iomem *gtt_entries = |
1238 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1239 | int i = 0; |
1240 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
1241 | dma_addr_t addr; |
1242 | ||
6e995e23 | 1243 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1244 | addr = sg_page_iter_dma_address(&sg_iter); |
b35b380e | 1245 | iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]); |
6e995e23 | 1246 | i++; |
e76e9aeb BW |
1247 | } |
1248 | ||
e76e9aeb BW |
1249 | /* XXX: This serves as a posting read to make sure that the PTE has |
1250 | * actually been updated. There is some concern that even though | |
1251 | * registers and PTEs are within the same BAR that they are potentially | |
1252 | * of NUMA access patterns. Therefore, even with the way we assume | |
1253 | * hardware should work, we must keep this posting read for paranoia. | |
1254 | */ | |
1255 | if (i != 0) | |
853ba5d2 | 1256 | WARN_ON(readl(>t_entries[i-1]) != |
b35b380e | 1257 | vm->pte_encode(addr, level, true)); |
0f9b91c7 BW |
1258 | |
1259 | /* This next bit makes the above posting read even more important. We | |
1260 | * want to flush the TLBs only after we're certain all the PTE updates | |
1261 | * have finished. | |
1262 | */ | |
1263 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1264 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1265 | } |
1266 | ||
94ec8f61 BW |
1267 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
1268 | unsigned int first_entry, | |
1269 | unsigned int num_entries, | |
1270 | bool use_scratch) | |
1271 | { | |
1272 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
1273 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = | |
1274 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1275 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1276 | int i; | |
1277 | ||
1278 | if (WARN(num_entries > max_entries, | |
1279 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1280 | first_entry, num_entries, max_entries)) | |
1281 | num_entries = max_entries; | |
1282 | ||
1283 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1284 | I915_CACHE_LLC, | |
1285 | use_scratch); | |
1286 | for (i = 0; i < num_entries; i++) | |
1287 | gen8_set_pte(>t_base[i], scratch_pte); | |
1288 | readl(gtt_base); | |
1289 | } | |
1290 | ||
853ba5d2 | 1291 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1292 | unsigned int first_entry, |
828c7908 BW |
1293 | unsigned int num_entries, |
1294 | bool use_scratch) | |
7faf1ab2 | 1295 | { |
853ba5d2 | 1296 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
e7c2b58b BW |
1297 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1298 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1299 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1300 | int i; |
1301 | ||
1302 | if (WARN(num_entries > max_entries, | |
1303 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1304 | first_entry, num_entries, max_entries)) | |
1305 | num_entries = max_entries; | |
1306 | ||
828c7908 BW |
1307 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch); |
1308 | ||
7faf1ab2 DV |
1309 | for (i = 0; i < num_entries; i++) |
1310 | iowrite32(scratch_pte, >t_base[i]); | |
1311 | readl(gtt_base); | |
1312 | } | |
1313 | ||
6f65e29a BW |
1314 | |
1315 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1316 | enum i915_cache_level cache_level, | |
1317 | u32 unused) | |
7faf1ab2 | 1318 | { |
6f65e29a | 1319 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1320 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1321 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1322 | ||
6f65e29a BW |
1323 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1324 | intel_gtt_insert_sg_entries(vma->obj->pages, entry, flags); | |
1325 | vma->obj->has_global_gtt_mapping = 1; | |
7faf1ab2 DV |
1326 | } |
1327 | ||
853ba5d2 | 1328 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
7faf1ab2 | 1329 | unsigned int first_entry, |
828c7908 BW |
1330 | unsigned int num_entries, |
1331 | bool unused) | |
7faf1ab2 DV |
1332 | { |
1333 | intel_gtt_clear_range(first_entry, num_entries); | |
1334 | } | |
1335 | ||
6f65e29a BW |
1336 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1337 | { | |
1338 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1339 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1340 | |
6f65e29a BW |
1341 | BUG_ON(!i915_is_ggtt(vma->vm)); |
1342 | vma->obj->has_global_gtt_mapping = 0; | |
1343 | intel_gtt_clear_range(first, size); | |
1344 | } | |
7faf1ab2 | 1345 | |
6f65e29a BW |
1346 | static void ggtt_bind_vma(struct i915_vma *vma, |
1347 | enum i915_cache_level cache_level, | |
1348 | u32 flags) | |
d5bd1449 | 1349 | { |
6f65e29a | 1350 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1351 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1352 | struct drm_i915_gem_object *obj = vma->obj; |
1353 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
7faf1ab2 | 1354 | |
6f65e29a BW |
1355 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1356 | * or we have a global mapping already but the cacheability flags have | |
1357 | * changed, set the global PTEs. | |
1358 | * | |
1359 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1360 | * instead if none of the above hold true. | |
1361 | * | |
1362 | * NB: A global mapping should only be needed for special regions like | |
1363 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1364 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1365 | */ | |
1366 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
1367 | if (!obj->has_global_gtt_mapping || | |
1368 | (cache_level != obj->cache_level)) { | |
1369 | vma->vm->insert_entries(vma->vm, obj->pages, entry, | |
1370 | cache_level); | |
1371 | obj->has_global_gtt_mapping = 1; | |
1372 | } | |
1373 | } | |
d5bd1449 | 1374 | |
6f65e29a BW |
1375 | if (dev_priv->mm.aliasing_ppgtt && |
1376 | (!obj->has_aliasing_ppgtt_mapping || | |
1377 | (cache_level != obj->cache_level))) { | |
1378 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1379 | appgtt->base.insert_entries(&appgtt->base, | |
1380 | vma->obj->pages, entry, cache_level); | |
1381 | vma->obj->has_aliasing_ppgtt_mapping = 1; | |
1382 | } | |
d5bd1449 CW |
1383 | } |
1384 | ||
6f65e29a | 1385 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1386 | { |
6f65e29a | 1387 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1388 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a BW |
1389 | struct drm_i915_gem_object *obj = vma->obj; |
1390 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; | |
1391 | ||
1392 | if (obj->has_global_gtt_mapping) { | |
1393 | vma->vm->clear_range(vma->vm, entry, | |
1394 | vma->obj->base.size >> PAGE_SHIFT, | |
1395 | true); | |
1396 | obj->has_global_gtt_mapping = 0; | |
1397 | } | |
74898d7e | 1398 | |
6f65e29a BW |
1399 | if (obj->has_aliasing_ppgtt_mapping) { |
1400 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1401 | appgtt->base.clear_range(&appgtt->base, | |
1402 | entry, | |
1403 | obj->base.size >> PAGE_SHIFT, | |
1404 | true); | |
1405 | obj->has_aliasing_ppgtt_mapping = 0; | |
1406 | } | |
74163907 DV |
1407 | } |
1408 | ||
1409 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1410 | { |
5c042287 BW |
1411 | struct drm_device *dev = obj->base.dev; |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1413 | bool interruptible; | |
1414 | ||
1415 | interruptible = do_idling(dev_priv); | |
1416 | ||
9da3da66 CW |
1417 | if (!obj->has_dma_mapping) |
1418 | dma_unmap_sg(&dev->pdev->dev, | |
1419 | obj->pages->sgl, obj->pages->nents, | |
1420 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1421 | |
1422 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1423 | } |
644ec02b | 1424 | |
42d6ab48 CW |
1425 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1426 | unsigned long color, | |
1427 | unsigned long *start, | |
1428 | unsigned long *end) | |
1429 | { | |
1430 | if (node->color != color) | |
1431 | *start += 4096; | |
1432 | ||
1433 | if (!list_empty(&node->node_list)) { | |
1434 | node = list_entry(node->node_list.next, | |
1435 | struct drm_mm_node, | |
1436 | node_list); | |
1437 | if (node->allocated && node->color != color) | |
1438 | *end -= 4096; | |
1439 | } | |
1440 | } | |
fbe5d36e | 1441 | |
d7e5008f BW |
1442 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
1443 | unsigned long start, | |
1444 | unsigned long mappable_end, | |
1445 | unsigned long end) | |
644ec02b | 1446 | { |
e78891ca BW |
1447 | /* Let GEM Manage all of the aperture. |
1448 | * | |
1449 | * However, leave one page at the end still bound to the scratch page. | |
1450 | * There are a number of places where the hardware apparently prefetches | |
1451 | * past the end of the object, and we've seen multiple hangs with the | |
1452 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1453 | * aperture. One page should be enough to keep any prefetching inside | |
1454 | * of the aperture. | |
1455 | */ | |
40d74980 BW |
1456 | struct drm_i915_private *dev_priv = dev->dev_private; |
1457 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1458 | struct drm_mm_node *entry; |
1459 | struct drm_i915_gem_object *obj; | |
1460 | unsigned long hole_start, hole_end; | |
644ec02b | 1461 | |
35451cb6 BW |
1462 | BUG_ON(mappable_end > end); |
1463 | ||
ed2f3452 | 1464 | /* Subtract the guard page ... */ |
40d74980 | 1465 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
42d6ab48 | 1466 | if (!HAS_LLC(dev)) |
93bd8649 | 1467 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1468 | |
ed2f3452 | 1469 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1470 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1471 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
b3a070cc | 1472 | int ret; |
edd41a87 | 1473 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1474 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1475 | ||
1476 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1477 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
c6cfb325 | 1478 | if (ret) |
b3a070cc | 1479 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
1480 | obj->has_global_gtt_mapping = 1; |
1481 | } | |
1482 | ||
853ba5d2 BW |
1483 | dev_priv->gtt.base.start = start; |
1484 | dev_priv->gtt.base.total = end - start; | |
644ec02b | 1485 | |
ed2f3452 | 1486 | /* Clear any non-preallocated blocks */ |
40d74980 | 1487 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
853ba5d2 | 1488 | const unsigned long count = (hole_end - hole_start) / PAGE_SIZE; |
ed2f3452 CW |
1489 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1490 | hole_start, hole_end); | |
828c7908 | 1491 | ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true); |
ed2f3452 CW |
1492 | } |
1493 | ||
1494 | /* And finally clear the reserved guard page */ | |
828c7908 | 1495 | ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true); |
e76e9aeb BW |
1496 | } |
1497 | ||
d7e5008f BW |
1498 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1501 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1502 | |
853ba5d2 | 1503 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1504 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1505 | |
e78891ca | 1506 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1507 | } |
1508 | ||
1509 | static int setup_scratch_page(struct drm_device *dev) | |
1510 | { | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | struct page *page; | |
1513 | dma_addr_t dma_addr; | |
1514 | ||
1515 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1516 | if (page == NULL) | |
1517 | return -ENOMEM; | |
1518 | get_page(page); | |
1519 | set_pages_uc(page, 1); | |
1520 | ||
1521 | #ifdef CONFIG_INTEL_IOMMU | |
1522 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1523 | PCI_DMA_BIDIRECTIONAL); | |
1524 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1525 | return -EINVAL; | |
1526 | #else | |
1527 | dma_addr = page_to_phys(page); | |
1528 | #endif | |
853ba5d2 BW |
1529 | dev_priv->gtt.base.scratch.page = page; |
1530 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1531 | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | static void teardown_scratch_page(struct drm_device *dev) | |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1538 | struct page *page = dev_priv->gtt.base.scratch.page; |
1539 | ||
1540 | set_pages_wb(page, 1); | |
1541 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1542 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 BW |
1543 | put_page(page); |
1544 | __free_page(page); | |
e76e9aeb BW |
1545 | } |
1546 | ||
1547 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1548 | { | |
1549 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1550 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1551 | return snb_gmch_ctl << 20; | |
1552 | } | |
1553 | ||
9459d252 BW |
1554 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1555 | { | |
1556 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1557 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1558 | if (bdw_gmch_ctl) | |
1559 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
3a2ffb65 | 1560 | if (bdw_gmch_ctl > 4) { |
d330a953 | 1561 | WARN_ON(!i915.preliminary_hw_support); |
3a2ffb65 BW |
1562 | return 4<<20; |
1563 | } | |
1564 | ||
9459d252 BW |
1565 | return bdw_gmch_ctl << 20; |
1566 | } | |
1567 | ||
baa09f5f | 1568 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1569 | { |
1570 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1571 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1572 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1573 | } | |
1574 | ||
9459d252 BW |
1575 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1576 | { | |
1577 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1578 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1579 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1580 | } | |
1581 | ||
63340133 BW |
1582 | static int ggtt_probe_common(struct drm_device *dev, |
1583 | size_t gtt_size) | |
1584 | { | |
1585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1586 | phys_addr_t gtt_bus_addr; | |
1587 | int ret; | |
1588 | ||
1589 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
1590 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
1591 | (pci_resource_len(dev->pdev, 0) / 2); | |
1592 | ||
1593 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); | |
1594 | if (!dev_priv->gtt.gsm) { | |
1595 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1596 | return -ENOMEM; | |
1597 | } | |
1598 | ||
1599 | ret = setup_scratch_page(dev); | |
1600 | if (ret) { | |
1601 | DRM_ERROR("Scratch setup failed\n"); | |
1602 | /* iounmap will also get called at remove, but meh */ | |
1603 | iounmap(dev_priv->gtt.gsm); | |
1604 | } | |
1605 | ||
1606 | return ret; | |
1607 | } | |
1608 | ||
fbe5d36e BW |
1609 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1610 | * bits. When using advanced contexts each context stores its own PAT, but | |
1611 | * writing this data shouldn't be harmful even in those cases. */ | |
1612 | static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv) | |
1613 | { | |
1614 | #define GEN8_PPAT_UC (0<<0) | |
1615 | #define GEN8_PPAT_WC (1<<0) | |
1616 | #define GEN8_PPAT_WT (2<<0) | |
1617 | #define GEN8_PPAT_WB (3<<0) | |
1618 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
1619 | /* FIXME(BDW): Bspec is completely confused about cache control bits. */ | |
1620 | #define GEN8_PPAT_LLC (1<<2) | |
1621 | #define GEN8_PPAT_LLCELLC (2<<2) | |
1622 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
1623 | #define GEN8_PPAT_AGE(x) (x<<4) | |
1624 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
1625 | uint64_t pat; | |
1626 | ||
1627 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1628 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1629 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1630 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1631 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1632 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1633 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
1634 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
1635 | ||
1636 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b | |
1637 | * write would work. */ | |
1638 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
1639 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
1640 | } | |
1641 | ||
63340133 BW |
1642 | static int gen8_gmch_probe(struct drm_device *dev, |
1643 | size_t *gtt_total, | |
1644 | size_t *stolen, | |
1645 | phys_addr_t *mappable_base, | |
1646 | unsigned long *mappable_end) | |
1647 | { | |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1649 | unsigned int gtt_size; | |
1650 | u16 snb_gmch_ctl; | |
1651 | int ret; | |
1652 | ||
1653 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
1654 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
1655 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1656 | ||
1657 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
1658 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
1659 | ||
1660 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
1661 | ||
1662 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
1663 | ||
1664 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
d31eb10e | 1665 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 1666 | |
fbe5d36e BW |
1667 | gen8_setup_private_ppat(dev_priv); |
1668 | ||
63340133 BW |
1669 | ret = ggtt_probe_common(dev, gtt_size); |
1670 | ||
94ec8f61 BW |
1671 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
1672 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
1673 | |
1674 | return ret; | |
1675 | } | |
1676 | ||
baa09f5f BW |
1677 | static int gen6_gmch_probe(struct drm_device *dev, |
1678 | size_t *gtt_total, | |
41907ddc BW |
1679 | size_t *stolen, |
1680 | phys_addr_t *mappable_base, | |
1681 | unsigned long *mappable_end) | |
e76e9aeb BW |
1682 | { |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 1684 | unsigned int gtt_size; |
e76e9aeb | 1685 | u16 snb_gmch_ctl; |
e76e9aeb BW |
1686 | int ret; |
1687 | ||
41907ddc BW |
1688 | *mappable_base = pci_resource_start(dev->pdev, 2); |
1689 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
1690 | ||
baa09f5f BW |
1691 | /* 64/512MB is the current min/max we actually know of, but this is just |
1692 | * a coarse sanity check. | |
e76e9aeb | 1693 | */ |
41907ddc | 1694 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
1695 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
1696 | dev_priv->gtt.mappable_end); | |
1697 | return -ENXIO; | |
e76e9aeb BW |
1698 | } |
1699 | ||
e76e9aeb BW |
1700 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
1701 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 1702 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 1703 | |
c4ae25ec | 1704 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 1705 | |
63340133 BW |
1706 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
1707 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 1708 | |
63340133 | 1709 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 1710 | |
853ba5d2 BW |
1711 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
1712 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 1713 | |
e76e9aeb BW |
1714 | return ret; |
1715 | } | |
1716 | ||
853ba5d2 | 1717 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 1718 | { |
853ba5d2 BW |
1719 | |
1720 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 BW |
1721 | |
1722 | drm_mm_takedown(&vm->mm); | |
853ba5d2 BW |
1723 | iounmap(gtt->gsm); |
1724 | teardown_scratch_page(vm->dev); | |
644ec02b | 1725 | } |
baa09f5f BW |
1726 | |
1727 | static int i915_gmch_probe(struct drm_device *dev, | |
1728 | size_t *gtt_total, | |
41907ddc BW |
1729 | size_t *stolen, |
1730 | phys_addr_t *mappable_base, | |
1731 | unsigned long *mappable_end) | |
baa09f5f BW |
1732 | { |
1733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1734 | int ret; | |
1735 | ||
baa09f5f BW |
1736 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
1737 | if (!ret) { | |
1738 | DRM_ERROR("failed to set up gmch\n"); | |
1739 | return -EIO; | |
1740 | } | |
1741 | ||
41907ddc | 1742 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
1743 | |
1744 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 1745 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 1746 | |
c0a7f818 CW |
1747 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
1748 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
1749 | ||
baa09f5f BW |
1750 | return 0; |
1751 | } | |
1752 | ||
853ba5d2 | 1753 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
1754 | { |
1755 | intel_gmch_remove(); | |
1756 | } | |
1757 | ||
1758 | int i915_gem_gtt_init(struct drm_device *dev) | |
1759 | { | |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1761 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
1762 | int ret; |
1763 | ||
baa09f5f | 1764 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 1765 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 1766 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 1767 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 1768 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 1769 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 1770 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 1771 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 1772 | else if (IS_HASWELL(dev)) |
853ba5d2 | 1773 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 1774 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 1775 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
1776 | else if (INTEL_INFO(dev)->gen >= 7) |
1777 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 1778 | else |
350ec881 | 1779 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
1780 | } else { |
1781 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
1782 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
1783 | } |
1784 | ||
853ba5d2 | 1785 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 1786 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 1787 | if (ret) |
baa09f5f | 1788 | return ret; |
baa09f5f | 1789 | |
853ba5d2 BW |
1790 | gtt->base.dev = dev; |
1791 | ||
baa09f5f | 1792 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
1793 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
1794 | gtt->base.total >> 20); | |
b2f21b4d BW |
1795 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
1796 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
1797 | |
1798 | return 0; | |
1799 | } | |
6f65e29a BW |
1800 | |
1801 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
1802 | struct i915_address_space *vm) | |
1803 | { | |
1804 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
1805 | if (vma == NULL) | |
1806 | return ERR_PTR(-ENOMEM); | |
1807 | ||
1808 | INIT_LIST_HEAD(&vma->vma_link); | |
1809 | INIT_LIST_HEAD(&vma->mm_list); | |
1810 | INIT_LIST_HEAD(&vma->exec_list); | |
1811 | vma->vm = vm; | |
1812 | vma->obj = obj; | |
1813 | ||
1814 | switch (INTEL_INFO(vm->dev)->gen) { | |
1815 | case 8: | |
1816 | case 7: | |
1817 | case 6: | |
7e0d96bc BW |
1818 | if (i915_is_ggtt(vm)) { |
1819 | vma->unbind_vma = ggtt_unbind_vma; | |
1820 | vma->bind_vma = ggtt_bind_vma; | |
1821 | } else { | |
1822 | vma->unbind_vma = ppgtt_unbind_vma; | |
1823 | vma->bind_vma = ppgtt_bind_vma; | |
1824 | } | |
6f65e29a BW |
1825 | break; |
1826 | case 5: | |
1827 | case 4: | |
1828 | case 3: | |
1829 | case 2: | |
1830 | BUG_ON(!i915_is_ggtt(vm)); | |
1831 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
1832 | vma->bind_vma = i915_ggtt_bind_vma; | |
1833 | break; | |
1834 | default: | |
1835 | BUG(); | |
1836 | } | |
1837 | ||
1838 | /* Keep GGTT vmas first to make debug easier */ | |
1839 | if (i915_is_ggtt(vm)) | |
1840 | list_add(&vma->vma_link, &obj->vma_list); | |
1841 | else | |
1842 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
1843 | ||
1844 | return vma; | |
1845 | } | |
1846 | ||
1847 | struct i915_vma * | |
1848 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
1849 | struct i915_address_space *vm) | |
1850 | { | |
1851 | struct i915_vma *vma; | |
1852 | ||
1853 | vma = i915_gem_obj_to_vma(obj, vm); | |
1854 | if (!vma) | |
1855 | vma = __i915_gem_vma_create(obj, vm); | |
1856 | ||
1857 | return vma; | |
1858 | } |