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drm/i915/gen8: Abstract PDP usage
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
76aaf220 29#include "i915_drv.h"
5dda8fa3 30#include "i915_vgpu.h"
76aaf220
DV		 31#include "i915_trace.h"
32#include "intel_drv.h"
33
45f8f69a
TU		 34/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 73 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
70b9f6f8
DV		 95static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
fe14d5f4 98const struct i915_ggtt_view i915_ggtt_view_normal;
9abc4648
JL		 99const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
fe14d5f4 102
cfa7c862
DV		 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
1893a71b
CW		 105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
1893a71b 110
71ba2d64
YZ		 111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
70ee45e1
DL		 114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
cfa7c862
DV		 120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
1893a71b 125 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 126 return 2;
127
93a25a9e
DV		 128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 132 return 0;
93a25a9e
DV		 133 }
134#endif
135
62942ed7 136 /* Early VLV doesn't have this */
ca2aed6c
VS		 137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
62942ed7
JB		 139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
2f82bbdf
MT		 143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 147}
148
70b9f6f8
DV		 149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
47552659
DV		 152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
70b9f6f8
DV		 161
162 return 0;
47552659
DV		 163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
6f65e29a 172
2c642b07
DV		 173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
94ec8f61 176{
07749ef3 177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 178 pte |= addr;
63c42e56
BW		 179
180 switch (level) {
181 case I915_CACHE_NONE:
fbe5d36e 182 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
94ec8f61
BW		 192 return pte;
193}
194
fe36f55d
MK		 195static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
b1fe6673 197{
07749ef3 198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 199 pde |= addr;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
202 else
203 pde |= PPAT_UNCACHED_INDEX;
204 return pde;
205}
206
07749ef3
MT		 207static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
54d12527 210{
07749ef3 211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 213
214 switch (level) {
350ec881
CW		 215 case I915_CACHE_L3_LLC:
216 case I915_CACHE_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
218 break;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
221 break;
222 default:
5f77eeb0 223 MISSING_CASE(level);
350ec881
CW		 224 }
225
226 return pte;
227}
228
07749ef3
MT		 229static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
350ec881 232{
07749ef3 233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
235
236 switch (level) {
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 239 break;
240 case I915_CACHE_LLC:
241 pte |= GEN6_PTE_CACHE_LLC;
242 break;
243 case I915_CACHE_NONE:
9119708c 244 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 245 break;
246 default:
5f77eeb0 247 MISSING_CASE(level);
e7210c3c
BW		 248 }
249
54d12527
BW		 250 return pte;
251}
252
07749ef3
MT		 253static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
93c34e70 256{
07749ef3 257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
259
24f3a8cf
AG		 260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 262
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265
266 return pte;
267}
268
07749ef3
MT		 269static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
9119708c 272{
07749ef3 273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 274 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 275
276 if (level != I915_CACHE_NONE)
87a6b688 277 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 278
279 return pte;
280}
281
07749ef3
MT		 282static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
4d15c145 285{
07749ef3 286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 287 pte |= HSW_PTE_ADDR_ENCODE(addr);
288
651d794f
CW		 289 switch (level) {
290 case I915_CACHE_NONE:
291 break;
292 case I915_CACHE_WT:
c51e9701 293 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 294 break;
295 default:
c51e9701 296 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 297 break;
298 }
4d15c145
BW		 299
300 return pte;
301}
302
c114f76a
MK		 303static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 305{
306 struct device *device = &dev->pdev->dev;
307
c114f76a 308 p->page = alloc_page(flags);
44159ddb
MK		 309 if (!p->page)
310 return -ENOMEM;
678d96fb 311
44159ddb
MK		 312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 314
44159ddb
MK		 315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
1266cdb1
MT		 319
320 return 0;
678d96fb
BW		 321}
322
c114f76a
MK		 323static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 return __setup_page_dma(dev, p, GFP_KERNEL);
326}
327
44159ddb 328static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 329{
44159ddb 330 if (WARN_ON(!p->page))
06fda602 331 return;
678d96fb 332
44159ddb
MK		 333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
336}
337
d1c54acd 338static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 339{
d1c54acd
MK		 340 return kmap_atomic(p->page);
341}
73eeea53 342
d1c54acd
MK		 343/* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
345 */
346static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
347{
73eeea53
MK		 348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
350 */
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
353
354 kunmap_atomic(vaddr);
355}
356
567047be 357#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 358#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
359
567047be
MK		 360#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
364
d1c54acd
MK		 365static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
366 const uint64_t val)
367{
368 int i;
369 uint64_t * const vaddr = kmap_page_dma(p);
370
371 for (i = 0; i < 512; i++)
372 vaddr[i] = val;
373
374 kunmap_page_dma(dev, vaddr);
375}
376
73eeea53
MK		 377static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
379{
380 uint64_t v = val32;
381
382 v = v << 32 | val32;
383
384 fill_page_dma(dev, p, v);
385}
386
4ad2af1e
MK		 387static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
388{
389 struct i915_page_scratch *sp;
390 int ret;
391
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
393 if (sp == NULL)
394 return ERR_PTR(-ENOMEM);
395
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
397 if (ret) {
398 kfree(sp);
399 return ERR_PTR(ret);
400 }
401
402 set_pages_uc(px_page(sp), 1);
403
404 return sp;
405}
406
407static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
409{
410 set_pages_wb(px_page(sp), 1);
411
412 cleanup_px(dev, sp);
413 kfree(sp);
414}
415
8a1ebd74 416static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 417{
ec565b3c 418 struct i915_page_table *pt;
678d96fb
BW		 419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
421 int ret = -ENOMEM;
06fda602
BW		 422
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
424 if (!pt)
425 return ERR_PTR(-ENOMEM);
426
678d96fb
BW		 427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
428 GFP_KERNEL);
429
430 if (!pt->used_ptes)
431 goto fail_bitmap;
432
567047be 433 ret = setup_px(dev, pt);
678d96fb 434 if (ret)
44159ddb 435 goto fail_page_m;
06fda602
BW		 436
437 return pt;
678d96fb 438
44159ddb 439fail_page_m:
678d96fb
BW		 440 kfree(pt->used_ptes);
441fail_bitmap:
442 kfree(pt);
443
444 return ERR_PTR(ret);
06fda602
BW		 445}
446
2e906bea 447static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 448{
2e906bea
MK		 449 cleanup_px(dev, pt);
450 kfree(pt->used_ptes);
451 kfree(pt);
452}
453
454static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
456{
457 gen8_pte_t scratch_pte;
458
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
461
462 fill_px(vm->dev, pt, scratch_pte);
463}
464
465static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
467{
468 gen6_pte_t scratch_pte;
469
470 WARN_ON(px_dma(vm->scratch_page) == 0);
471
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
474
475 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 476}
477
8a1ebd74 478static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 479{
ec565b3c 480 struct i915_page_directory *pd;
33c8819f 481 int ret = -ENOMEM;
06fda602
BW		 482
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
484 if (!pd)
485 return ERR_PTR(-ENOMEM);
486
33c8819f
MT		 487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
489 if (!pd->used_pdes)
a08e111a 490 goto fail_bitmap;
33c8819f 491
567047be 492 ret = setup_px(dev, pd);
33c8819f 493 if (ret)
a08e111a 494 goto fail_page_m;
e5815a2e 495
06fda602 496 return pd;
33c8819f 497
a08e111a 498fail_page_m:
33c8819f 499 kfree(pd->used_pdes);
a08e111a 500fail_bitmap:
33c8819f
MT		 501 kfree(pd);
502
503 return ERR_PTR(ret);
06fda602
BW		 504}
505
2e906bea
MK		 506static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
507{
508 if (px_page(pd)) {
509 cleanup_px(dev, pd);
510 kfree(pd->used_pdes);
511 kfree(pd);
512 }
513}
514
515static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
517{
518 gen8_pde_t scratch_pde;
519
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
521
522 fill_px(vm->dev, pd, scratch_pde);
523}
524
6ac18502
MT		 525static int __pdp_init(struct drm_device *dev,
526 struct i915_page_directory_pointer *pdp)
527{
528 size_t pdpes = I915_PDPES_PER_PDP(dev);
529
530 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
531 sizeof(unsigned long),
532 GFP_KERNEL);
533 if (!pdp->used_pdpes)
534 return -ENOMEM;
535
536 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
537 GFP_KERNEL);
538 if (!pdp->page_directory) {
539 kfree(pdp->used_pdpes);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp->used_pdpes = NULL;
543 return -ENOMEM;
544 }
545
546 return 0;
547}
548
549static void __pdp_fini(struct i915_page_directory_pointer *pdp)
550{
551 kfree(pdp->used_pdpes);
552 kfree(pdp->page_directory);
553 pdp->page_directory = NULL;
554}
555
556static void free_pdp(struct drm_device *dev,
557 struct i915_page_directory_pointer *pdp)
558{
559 __pdp_fini(pdp);
560}
561
94e409c1 562/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 563static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 564 unsigned entry,
565 dma_addr_t addr)
94e409c1 566{
e85b26dc 567 struct intel_engine_cs *ring = req->ring;
94e409c1
BW		 568 int ret;
569
570 BUG_ON(entry >= 4);
571
5fb9de1a 572 ret = intel_ring_begin(req, 6);
94e409c1
BW		 573 if (ret)
574 return ret;
575
576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
7cb6d7ac 578 intel_ring_emit(ring, upper_32_bits(addr));
94e409c1
BW		 579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
7cb6d7ac 581 intel_ring_emit(ring, lower_32_bits(addr));
94e409c1
BW		 582 intel_ring_advance(ring);
583
584 return 0;
585}
586
eeb9488e 587static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 588 struct drm_i915_gem_request *req)
94e409c1 589{
eeb9488e 590 int i, ret;
94e409c1 591
7cb6d7ac 592 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
594
e85b26dc 595 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 596 if (ret)
597 return ret;
94e409c1 598 }
d595bd4b 599
eeb9488e 600 return 0;
94e409c1
BW		 601}
602
459108b8 603static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 604 uint64_t start,
605 uint64_t length,
459108b8
BW		 606 bool use_scratch)
607{
608 struct i915_hw_ppgtt *ppgtt =
609 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0 610 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
07749ef3 611 gen8_pte_t *pt_vaddr, scratch_pte;
7ad47cf2
BW		 612 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
613 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
614 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
782f1495 615 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 616 unsigned last_pte, i;
617
c114f76a 618 scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page),
459108b8
BW		 619 I915_CACHE_LLC, use_scratch);
620
621 while (num_entries) {
ec565b3c
MT		 622 struct i915_page_directory *pd;
623 struct i915_page_table *pt;
06fda602 624
d4ec9da0 625 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 626 break;
06fda602 627
d4ec9da0 628 pd = pdp->page_directory[pdpe];
06fda602
BW		 629
630 if (WARN_ON(!pd->page_table[pde]))
00245266 631 break;
06fda602
BW		 632
633 pt = pd->page_table[pde];
634
567047be 635 if (WARN_ON(!px_page(pt)))
00245266 636 break;
06fda602 637
7ad47cf2 638 last_pte = pte + num_entries;
07749ef3
MT		 639 if (last_pte > GEN8_PTES)
640 last_pte = GEN8_PTES;
459108b8 641
d1c54acd 642 pt_vaddr = kmap_px(pt);
459108b8 643
7ad47cf2 644 for (i = pte; i < last_pte; i++) {
459108b8 645 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 646 num_entries--;
647 }
459108b8 648
d1c54acd 649 kunmap_px(ppgtt, pt);
459108b8 650
7ad47cf2 651 pte = 0;
07749ef3 652 if (++pde == I915_PDES) {
7ad47cf2
BW		 653 pdpe++;
654 pde = 0;
655 }
459108b8
BW		 656 }
657}
658
9df15b49
BW		 659static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
660 struct sg_table *pages,
782f1495 661 uint64_t start,
24f3a8cf 662 enum i915_cache_level cache_level, u32 unused)
9df15b49
BW		 663{
664 struct i915_hw_ppgtt *ppgtt =
665 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0 666 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
07749ef3 667 gen8_pte_t *pt_vaddr;
7ad47cf2
BW		 668 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
669 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
670 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
9df15b49
BW		 671 struct sg_page_iter sg_iter;
672
6f1cc993 673 pt_vaddr = NULL;
7ad47cf2 674
9df15b49 675 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
76643600 676 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
7ad47cf2
BW		 677 break;
678
d7b3de91 679 if (pt_vaddr == NULL) {
d4ec9da0 680 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 681 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 682 pt_vaddr = kmap_px(pt);
d7b3de91 683 }
9df15b49 684
7ad47cf2 685 pt_vaddr[pte] =
6f1cc993
CW		 686 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
687 cache_level, true);
07749ef3 688 if (++pte == GEN8_PTES) {
d1c54acd 689 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 690 pt_vaddr = NULL;
07749ef3 691 if (++pde == I915_PDES) {
7ad47cf2
BW		 692 pdpe++;
693 pde = 0;
694 }
695 pte = 0;
9df15b49
BW		 696 }
697 }
d1c54acd
MK		 698
699 if (pt_vaddr)
700 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 701}
702
f37c0505
MT		 703static void gen8_free_page_tables(struct drm_device *dev,
704 struct i915_page_directory *pd)
7ad47cf2
BW		 705{
706 int i;
707
567047be 708 if (!px_page(pd))
7ad47cf2
BW		 709 return;
710
33c8819f 711 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 712 if (WARN_ON(!pd->page_table[i]))
713 continue;
7ad47cf2 714
a08e111a 715 free_pt(dev, pd->page_table[i]);
06fda602
BW		 716 pd->page_table[i] = NULL;
717 }
d7b3de91
BW		 718}
719
8776f02b
MK		 720static int gen8_init_scratch(struct i915_address_space *vm)
721{
722 struct drm_device *dev = vm->dev;
723
724 vm->scratch_page = alloc_scratch_page(dev);
725 if (IS_ERR(vm->scratch_page))
726 return PTR_ERR(vm->scratch_page);
727
728 vm->scratch_pt = alloc_pt(dev);
729 if (IS_ERR(vm->scratch_pt)) {
730 free_scratch_page(dev, vm->scratch_page);
731 return PTR_ERR(vm->scratch_pt);
732 }
733
734 vm->scratch_pd = alloc_pd(dev);
735 if (IS_ERR(vm->scratch_pd)) {
736 free_pt(dev, vm->scratch_pt);
737 free_scratch_page(dev, vm->scratch_page);
738 return PTR_ERR(vm->scratch_pd);
739 }
740
741 gen8_initialize_pt(vm, vm->scratch_pt);
742 gen8_initialize_pd(vm, vm->scratch_pd);
743
744 return 0;
745}
746
747static void gen8_free_scratch(struct i915_address_space *vm)
748{
749 struct drm_device *dev = vm->dev;
750
751 free_pd(dev, vm->scratch_pd);
752 free_pt(dev, vm->scratch_pt);
753 free_scratch_page(dev, vm->scratch_page);
754}
755
061dd493 756static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
b45a6715 757{
061dd493
DV		 758 struct i915_hw_ppgtt *ppgtt =
759 container_of(vm, struct i915_hw_ppgtt, base);
d4ec9da0
MT		 760 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
761 struct drm_device *dev = ppgtt->base.dev;
b45a6715
BW		 762 int i;
763
d4ec9da0
MT		 764 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
765 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 766 continue;
767
d4ec9da0
MT		 768 gen8_free_page_tables(dev, pdp->page_directory[i]);
769 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 770 }
69876bed 771
d4ec9da0
MT		 772 free_pdp(dev, pdp);
773
8776f02b 774 gen8_free_scratch(vm);
b45a6715
BW		 775}
776
d7b2633d
MT		 777/**
778 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 779 * @vm: Master vm structure.
780 * @pd: Page directory for this address range.
d7b2633d 781 * @start: Starting virtual address to begin allocations.
d4ec9da0 782 * @length: Size of the allocations.
d7b2633d
MT		 783 * @new_pts: Bitmap set by function with new allocations. Likely used by the
784 * caller to free on error.
785 *
786 * Allocate the required number of page tables. Extremely similar to
787 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
788 * the page directory boundary (instead of the page directory pointer). That
789 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
790 * possible, and likely that the caller will need to use multiple calls of this
791 * function to achieve the appropriate allocation.
792 *
793 * Return: 0 if success; negative error code otherwise.
794 */
d4ec9da0 795static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 796 struct i915_page_directory *pd,
5441f0cb 797 uint64_t start,
d7b2633d
MT		 798 uint64_t length,
799 unsigned long *new_pts)
bf2b4ed2 800{
d4ec9da0 801 struct drm_device *dev = vm->dev;
d7b2633d 802 struct i915_page_table *pt;
5441f0cb
MT		 803 uint64_t temp;
804 uint32_t pde;
bf2b4ed2 805
d7b2633d
MT		 806 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
807 /* Don't reallocate page tables */
6ac18502 808 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 809 /* Scratch is never allocated this way */
d4ec9da0 810 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 811 continue;
812 }
813
8a1ebd74 814 pt = alloc_pt(dev);
d7b2633d 815 if (IS_ERR(pt))
5441f0cb
MT		 816 goto unwind_out;
817
d4ec9da0 818 gen8_initialize_pt(vm, pt);
d7b2633d 819 pd->page_table[pde] = pt;
966082c9 820 __set_bit(pde, new_pts);
7ad47cf2
BW		 821 }
822
bf2b4ed2 823 return 0;
7ad47cf2
BW		 824
825unwind_out:
d7b2633d 826 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 827 free_pt(dev, pd->page_table[pde]);
7ad47cf2 828
d7b3de91 829 return -ENOMEM;
bf2b4ed2
BW		 830}
831
d7b2633d
MT		 832/**
833 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 834 * @vm: Master vm structure.
d7b2633d
MT		 835 * @pdp: Page directory pointer for this address range.
836 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 837 * @length: Size of the allocations.
838 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 839 * caller to free on error.
840 *
841 * Allocate the required number of page directories starting at the pde index of
842 * @start, and ending at the pde index @start + @length. This function will skip
843 * over already allocated page directories within the range, and only allocate
844 * new ones, setting the appropriate pointer within the pdp as well as the
845 * correct position in the bitmap @new_pds.
846 *
847 * The function will only allocate the pages within the range for a give page
848 * directory pointer. In other words, if @start + @length straddles a virtually
849 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
850 * required by the caller, This is not currently possible, and the BUG in the
851 * code will prevent it.
852 *
853 * Return: 0 if success; negative error code otherwise.
854 */
d4ec9da0
MT		 855static int
856gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
857 struct i915_page_directory_pointer *pdp,
858 uint64_t start,
859 uint64_t length,
860 unsigned long *new_pds)
bf2b4ed2 861{
d4ec9da0 862 struct drm_device *dev = vm->dev;
d7b2633d 863 struct i915_page_directory *pd;
69876bed
MT		 864 uint64_t temp;
865 uint32_t pdpe;
6ac18502 866 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 867
6ac18502 868 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 869
d7b2633d 870 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
6ac18502 871 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 872 continue;
33c8819f 873
8a1ebd74 874 pd = alloc_pd(dev);
d7b2633d 875 if (IS_ERR(pd))
d7b3de91 876 goto unwind_out;
69876bed 877
d4ec9da0 878 gen8_initialize_pd(vm, pd);
d7b2633d 879 pdp->page_directory[pdpe] = pd;
966082c9 880 __set_bit(pdpe, new_pds);
d7b3de91
BW		 881 }
882
bf2b4ed2 883 return 0;
d7b3de91
BW		 884
885unwind_out:
6ac18502 886 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 887 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 888
889 return -ENOMEM;
bf2b4ed2
BW		 890}
891
d7b2633d 892static void
6ac18502
MT		 893free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
894 uint32_t pdpes)
d7b2633d
MT		 895{
896 int i;
897
6ac18502 898 for (i = 0; i < pdpes; i++)
d7b2633d
MT		 899 kfree(new_pts[i]);
900 kfree(new_pts);
901 kfree(new_pds);
902}
903
904/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
905 * of these are based on the number of PDPEs in the system.
906 */
907static
908int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
6ac18502
MT		 909 unsigned long ***new_pts,
910 uint32_t pdpes)
d7b2633d
MT		 911{
912 int i;
913 unsigned long *pds;
914 unsigned long **pts;
915
6ac18502 916 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
d7b2633d
MT		 917 if (!pds)
918 return -ENOMEM;
919
6ac18502 920 pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
d7b2633d
MT		 921 if (!pts) {
922 kfree(pds);
923 return -ENOMEM;
924 }
925
6ac18502 926 for (i = 0; i < pdpes; i++) {
d7b2633d
MT		 927 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
928 sizeof(unsigned long), GFP_KERNEL);
929 if (!pts[i])
930 goto err_out;
931 }
932
933 *new_pds = pds;
934 *new_pts = pts;
935
936 return 0;
937
938err_out:
6ac18502 939 free_gen8_temp_bitmaps(pds, pts, pdpes);
d7b2633d
MT		 940 return -ENOMEM;
941}
942
5b7e4c9c
MK		 943/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
944 * the page table structures, we mark them dirty so that
945 * context switching/execlist queuing code takes extra steps
946 * to ensure that tlbs are flushed.
947 */
948static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
949{
950 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
951}
952
e5815a2e 953static int gen8_alloc_va_range(struct i915_address_space *vm,
d4ec9da0 954 uint64_t start, uint64_t length)
bf2b4ed2 955{
e5815a2e
MT		 956 struct i915_hw_ppgtt *ppgtt =
957 container_of(vm, struct i915_hw_ppgtt, base);
d7b2633d 958 unsigned long *new_page_dirs, **new_page_tables;
d4ec9da0
MT		 959 struct drm_device *dev = vm->dev;
960 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
5441f0cb 961 struct i915_page_directory *pd;
33c8819f
MT		 962 const uint64_t orig_start = start;
963 const uint64_t orig_length = length;
5441f0cb
MT		 964 uint64_t temp;
965 uint32_t pdpe;
d4ec9da0 966 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 967 int ret;
968
d7b2633d
MT		 969 /* Wrap is never okay since we can only represent 48b, and we don't
970 * actually use the other side of the canonical address space.
971 */
972 if (WARN_ON(start + length < start))
a05d80ee
MK		 973 return -ENODEV;
974
d4ec9da0 975 if (WARN_ON(start + length > vm->total))
a05d80ee 976 return -ENODEV;
d7b2633d 977
6ac18502 978 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 979 if (ret)
980 return ret;
981
d7b2633d 982 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 983 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
984 new_page_dirs);
d7b2633d 985 if (ret) {
6ac18502 986 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
d7b2633d
MT		 987 return ret;
988 }
989
990 /* For every page directory referenced, allocate page tables */
d4ec9da0
MT		 991 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
992 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
d7b2633d 993 new_page_tables[pdpe]);
5441f0cb
MT		 994 if (ret)
995 goto err_out;
5441f0cb
MT		 996 }
997
33c8819f
MT		 998 start = orig_start;
999 length = orig_length;
1000
d7b2633d
MT		 1001 /* Allocations have completed successfully, so set the bitmaps, and do
1002 * the mappings. */
d4ec9da0 1003 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
d1c54acd 1004 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1005 struct i915_page_table *pt;
09120d4e 1006 uint64_t pd_len = length;
33c8819f
MT		 1007 uint64_t pd_start = start;
1008 uint32_t pde;
1009
d7b2633d
MT		 1010 /* Every pd should be allocated, we just did that above. */
1011 WARN_ON(!pd);
1012
1013 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1014 /* Same reasoning as pd */
1015 WARN_ON(!pt);
1016 WARN_ON(!pd_len);
1017 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1018
1019 /* Set our used ptes within the page table */
1020 bitmap_set(pt->used_ptes,
1021 gen8_pte_index(pd_start),
1022 gen8_pte_count(pd_start, pd_len));
1023
1024 /* Our pde is now pointing to the pagetable, pt */
966082c9 1025 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1026
1027 /* Map the PDE to the page table */
fe36f55d
MK		 1028 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1029 I915_CACHE_LLC);
d7b2633d
MT		 1030
1031 /* NB: We haven't yet mapped ptes to pages. At this
1032 * point we're still relying on insert_entries() */
33c8819f 1033 }
d7b2633d 1034
d1c54acd 1035 kunmap_px(ppgtt, page_directory);
d4ec9da0 1036 __set_bit(pdpe, pdp->used_pdpes);
33c8819f
MT		 1037 }
1038
6ac18502 1039 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1040 mark_tlbs_dirty(ppgtt);
d7b3de91 1041 return 0;
bf2b4ed2 1042
d7b3de91 1043err_out:
d7b2633d
MT		 1044 while (pdpe--) {
1045 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
d4ec9da0 1046 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1047 }
1048
6ac18502 1049 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1050 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1051
6ac18502 1052 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
5b7e4c9c 1053 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1054 return ret;
1055}
1056
eb0b44ad 1057/*
f3a964b9
BW		 1058 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1059 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1060 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1061 * space.
37aca44a 1062 *
f3a964b9 1063 */
5c5f6457 1064static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1065{
8776f02b 1066 int ret;
7cb6d7ac 1067
8776f02b
MK		 1068 ret = gen8_init_scratch(&ppgtt->base);
1069 if (ret)
1070 return ret;
69876bed 1071
d7b2633d 1072 ppgtt->base.start = 0;
5c5f6457 1073 ppgtt->base.total = 1ULL << 32;
501fd70f
MT		 1074 if (IS_ENABLED(CONFIG_X86_32))
1075 /* While we have a proliferation of size_t variables
1076 * we cannot represent the full ppgtt size on 32bit,
1077 * so limit it to the same size as the GGTT (currently
1078 * 2GiB).
1079 */
1080 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
d7b2633d 1081 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1082 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1083 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1084 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1085 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1086 ppgtt->base.bind_vma = ppgtt_bind_vma;
d7b2633d
MT		 1087
1088 ppgtt->switch_mm = gen8_mm_switch;
1089
6ac18502
MT		 1090 ret = __pdp_init(false, &ppgtt->pdp);
1091
1092 if (ret)
1093 goto free_scratch;
1094
d7b2633d 1095 return 0;
6ac18502
MT		 1096
1097free_scratch:
1098 gen8_free_scratch(&ppgtt->base);
1099 return ret;
d7b2633d
MT		 1100}
1101
87d60b63
BW		 1102static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1103{
87d60b63 1104 struct i915_address_space *vm = &ppgtt->base;
09942c65 1105 struct i915_page_table *unused;
07749ef3 1106 gen6_pte_t scratch_pte;
87d60b63 1107 uint32_t pd_entry;
09942c65
MT		 1108 uint32_t pte, pde, temp;
1109 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1110
79ab9370
MK		 1111 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1112 I915_CACHE_LLC, true, 0);
87d60b63 1113
09942c65 1114 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
87d60b63 1115 u32 expected;
07749ef3 1116 gen6_pte_t *pt_vaddr;
567047be 1117 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1118 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1119 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1120
1121 if (pd_entry != expected)
1122 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1123 pde,
1124 pd_entry,
1125 expected);
1126 seq_printf(m, "\tPDE: %x\n", pd_entry);
1127
d1c54acd
MK		 1128 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1129
07749ef3 1130 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1131 unsigned long va =
07749ef3 1132 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1133 (pte * PAGE_SIZE);
1134 int i;
1135 bool found = false;
1136 for (i = 0; i < 4; i++)
1137 if (pt_vaddr[pte + i] != scratch_pte)
1138 found = true;
1139 if (!found)
1140 continue;
1141
1142 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1143 for (i = 0; i < 4; i++) {
1144 if (pt_vaddr[pte + i] != scratch_pte)
1145 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1146 else
1147 seq_puts(m, " SCRATCH ");
1148 }
1149 seq_puts(m, "\n");
1150 }
d1c54acd 1151 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1152 }
1153}
1154
678d96fb 1155/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1156static void gen6_write_pde(struct i915_page_directory *pd,
1157 const int pde, struct i915_page_table *pt)
6197349b 1158{
678d96fb
BW		 1159 /* Caller needs to make sure the write completes if necessary */
1160 struct i915_hw_ppgtt *ppgtt =
1161 container_of(pd, struct i915_hw_ppgtt, pd);
1162 u32 pd_entry;
6197349b 1163
567047be 1164 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1165 pd_entry |= GEN6_PDE_VALID;
6197349b 1166
678d96fb
BW		 1167 writel(pd_entry, ppgtt->pd_addr + pde);
1168}
6197349b 1169
678d96fb
BW		 1170/* Write all the page tables found in the ppgtt structure to incrementing page
1171 * directories. */
1172static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1173 struct i915_page_directory *pd,
678d96fb
BW		 1174 uint32_t start, uint32_t length)
1175{
ec565b3c 1176 struct i915_page_table *pt;
678d96fb
BW		 1177 uint32_t pde, temp;
1178
1179 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1180 gen6_write_pde(pd, pde, pt);
1181
1182 /* Make sure write is complete before other code can use this page
1183 * table. Also require for WC mapped PTEs */
1184 readl(dev_priv->gtt.gsm);
3e302542
BW		 1185}
1186
b4a74e3a 1187static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1188{
44159ddb 1189 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1190
44159ddb 1191 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1192}
1193
90252e5c 1194static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1195 struct drm_i915_gem_request *req)
90252e5c 1196{
e85b26dc 1197 struct intel_engine_cs *ring = req->ring;
90252e5c
BW		 1198 int ret;
1199
90252e5c 1200 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1201 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1202 if (ret)
1203 return ret;
1204
5fb9de1a 1205 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1206 if (ret)
1207 return ret;
1208
1209 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1210 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1211 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1212 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1213 intel_ring_emit(ring, get_pd_offset(ppgtt));
1214 intel_ring_emit(ring, MI_NOOP);
1215 intel_ring_advance(ring);
1216
1217 return 0;
1218}
1219
71ba2d64 1220static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1221 struct drm_i915_gem_request *req)
71ba2d64 1222{
e85b26dc 1223 struct intel_engine_cs *ring = req->ring;
71ba2d64
YZ		 1224 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1225
1226 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1227 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1228 return 0;
1229}
1230
48a10389 1231static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1232 struct drm_i915_gem_request *req)
48a10389 1233{
e85b26dc 1234 struct intel_engine_cs *ring = req->ring;
48a10389
BW		 1235 int ret;
1236
48a10389 1237 /* NB: TLBs must be flushed and invalidated before a switch */
a84c3ae1 1238 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1239 if (ret)
1240 return ret;
1241
5fb9de1a 1242 ret = intel_ring_begin(req, 6);
48a10389
BW		 1243 if (ret)
1244 return ret;
1245
1246 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1247 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1248 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1249 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1250 intel_ring_emit(ring, get_pd_offset(ppgtt));
1251 intel_ring_emit(ring, MI_NOOP);
1252 intel_ring_advance(ring);
1253
90252e5c
BW		 1254 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1255 if (ring->id != RCS) {
a84c3ae1 1256 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1257 if (ret)
1258 return ret;
1259 }
1260
48a10389
BW		 1261 return 0;
1262}
1263
eeb9488e 1264static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1265 struct drm_i915_gem_request *req)
eeb9488e 1266{
e85b26dc 1267 struct intel_engine_cs *ring = req->ring;
eeb9488e
BW		 1268 struct drm_device *dev = ppgtt->base.dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
48a10389 1271
eeb9488e
BW		 1272 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1273 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1274
1275 POSTING_READ(RING_PP_DIR_DCLV(ring));
1276
1277 return 0;
1278}
1279
82460d97 1280static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1281{
eeb9488e 1282 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1283 struct intel_engine_cs *ring;
82460d97 1284 int j;
3e302542 1285
eeb9488e
BW		 1286 for_each_ring(ring, dev_priv, j) {
1287 I915_WRITE(RING_MODE_GEN7(ring),
1288 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
eeb9488e 1289 }
eeb9488e 1290}
6197349b 1291
82460d97 1292static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1293{
50227e1c 1294 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1295 struct intel_engine_cs *ring;
b4a74e3a 1296 uint32_t ecochk, ecobits;
3e302542 1297 int i;
6197349b 1298
b4a74e3a
BW		 1299 ecobits = I915_READ(GAC_ECO_BITS);
1300 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1301
b4a74e3a
BW		 1302 ecochk = I915_READ(GAM_ECOCHK);
1303 if (IS_HASWELL(dev)) {
1304 ecochk |= ECOCHK_PPGTT_WB_HSW;
1305 } else {
1306 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1307 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1308 }
1309 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1310
b4a74e3a 1311 for_each_ring(ring, dev_priv, i) {
6197349b 1312 /* GFX_MODE is per-ring on gen7+ */
b4a74e3a
BW		 1313 I915_WRITE(RING_MODE_GEN7(ring),
1314 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1315 }
b4a74e3a 1316}
6197349b 1317
82460d97 1318static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1319{
50227e1c 1320 struct drm_i915_private *dev_priv = dev->dev_private;
b4a74e3a 1321 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1322
b4a74e3a
BW		 1323 ecobits = I915_READ(GAC_ECO_BITS);
1324 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1325 ECOBITS_PPGTT_CACHE64B);
6197349b 1326
b4a74e3a
BW		 1327 gab_ctl = I915_READ(GAB_CTL);
1328 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1329
1330 ecochk = I915_READ(GAM_ECOCHK);
1331 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1332
1333 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1334}
1335
1d2a314c 1336/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1337static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1338 uint64_t start,
1339 uint64_t length,
828c7908 1340 bool use_scratch)
1d2a314c 1341{
853ba5d2
BW		 1342 struct i915_hw_ppgtt *ppgtt =
1343 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1344 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1345 unsigned first_entry = start >> PAGE_SHIFT;
1346 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1347 unsigned act_pt = first_entry / GEN6_PTES;
1348 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1349 unsigned last_pte, i;
1d2a314c 1350
c114f76a
MK		 1351 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1352 I915_CACHE_LLC, true, 0);
1d2a314c 1353
7bddb01f
DV		 1354 while (num_entries) {
1355 last_pte = first_pte + num_entries;
07749ef3
MT		 1356 if (last_pte > GEN6_PTES)
1357 last_pte = GEN6_PTES;
7bddb01f 1358
d1c54acd 1359 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1360
7bddb01f
DV		 1361 for (i = first_pte; i < last_pte; i++)
1362 pt_vaddr[i] = scratch_pte;
1d2a314c 1363
d1c54acd 1364 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1365
7bddb01f
DV		 1366 num_entries -= last_pte - first_pte;
1367 first_pte = 0;
a15326a5 1368 act_pt++;
7bddb01f 1369 }
1d2a314c
DV		 1370}
1371
853ba5d2 1372static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1373 struct sg_table *pages,
782f1495 1374 uint64_t start,
24f3a8cf 1375 enum i915_cache_level cache_level, u32 flags)
def886c3 1376{
853ba5d2
BW		 1377 struct i915_hw_ppgtt *ppgtt =
1378 container_of(vm, struct i915_hw_ppgtt, base);
07749ef3 1379 gen6_pte_t *pt_vaddr;
782f1495 1380 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1381 unsigned act_pt = first_entry / GEN6_PTES;
1382 unsigned act_pte = first_entry % GEN6_PTES;
6e995e23
ID		 1383 struct sg_page_iter sg_iter;
1384
cc79714f 1385 pt_vaddr = NULL;
6e995e23 1386 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
cc79714f 1387 if (pt_vaddr == NULL)
d1c54acd 1388 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1389
cc79714f
CW		 1390 pt_vaddr[act_pte] =
1391 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
24f3a8cf
AG		 1392 cache_level, true, flags);
1393
07749ef3 1394 if (++act_pte == GEN6_PTES) {
d1c54acd 1395 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1396 pt_vaddr = NULL;
a15326a5 1397 act_pt++;
6e995e23 1398 act_pte = 0;
def886c3 1399 }
def886c3 1400 }
cc79714f 1401 if (pt_vaddr)
d1c54acd 1402 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1403}
1404
678d96fb 1405static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1406 uint64_t start_in, uint64_t length_in)
678d96fb 1407{
4933d519
MT		 1408 DECLARE_BITMAP(new_page_tables, I915_PDES);
1409 struct drm_device *dev = vm->dev;
1410 struct drm_i915_private *dev_priv = dev->dev_private;
678d96fb
BW		 1411 struct i915_hw_ppgtt *ppgtt =
1412 container_of(vm, struct i915_hw_ppgtt, base);
ec565b3c 1413 struct i915_page_table *pt;
a05d80ee 1414 uint32_t start, length, start_save, length_save;
678d96fb 1415 uint32_t pde, temp;
4933d519
MT		 1416 int ret;
1417
a05d80ee
MK		 1418 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1419 return -ENODEV;
1420
1421 start = start_save = start_in;
1422 length = length_save = length_in;
4933d519
MT		 1423
1424 bitmap_zero(new_page_tables, I915_PDES);
1425
1426 /* The allocation is done in two stages so that we can bail out with
1427 * minimal amount of pain. The first stage finds new page tables that
1428 * need allocation. The second stage marks use ptes within the page
1429 * tables.
1430 */
1431 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
79ab9370 1432 if (pt != vm->scratch_pt) {
4933d519
MT		 1433 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1434 continue;
1435 }
1436
1437 /* We've already allocated a page table */
1438 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1439
8a1ebd74 1440 pt = alloc_pt(dev);
4933d519
MT		 1441 if (IS_ERR(pt)) {
1442 ret = PTR_ERR(pt);
1443 goto unwind_out;
1444 }
1445
1446 gen6_initialize_pt(vm, pt);
1447
1448 ppgtt->pd.page_table[pde] = pt;
966082c9 1449 __set_bit(pde, new_page_tables);
72744cb1 1450 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1451 }
1452
1453 start = start_save;
1454 length = length_save;
678d96fb
BW		 1455
1456 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1457 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1458
1459 bitmap_zero(tmp_bitmap, GEN6_PTES);
1460 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1461 gen6_pte_count(start, length));
1462
966082c9 1463 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1464 gen6_write_pde(&ppgtt->pd, pde, pt);
1465
72744cb1
MT		 1466 trace_i915_page_table_entry_map(vm, pde, pt,
1467 gen6_pte_index(start),
1468 gen6_pte_count(start, length),
1469 GEN6_PTES);
4933d519 1470 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1471 GEN6_PTES);
1472 }
1473
4933d519
MT		 1474 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1475
1476 /* Make sure write is complete before other code can use this page
1477 * table. Also require for WC mapped PTEs */
1478 readl(dev_priv->gtt.gsm);
1479
563222a7 1480 mark_tlbs_dirty(ppgtt);
678d96fb 1481 return 0;
4933d519
MT		 1482
1483unwind_out:
1484 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1485 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1486
79ab9370 1487 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1488 free_pt(vm->dev, pt);
4933d519
MT		 1489 }
1490
1491 mark_tlbs_dirty(ppgtt);
1492 return ret;
678d96fb
BW		 1493}
1494
8776f02b
MK		 1495static int gen6_init_scratch(struct i915_address_space *vm)
1496{
1497 struct drm_device *dev = vm->dev;
1498
1499 vm->scratch_page = alloc_scratch_page(dev);
1500 if (IS_ERR(vm->scratch_page))
1501 return PTR_ERR(vm->scratch_page);
1502
1503 vm->scratch_pt = alloc_pt(dev);
1504 if (IS_ERR(vm->scratch_pt)) {
1505 free_scratch_page(dev, vm->scratch_page);
1506 return PTR_ERR(vm->scratch_pt);
1507 }
1508
1509 gen6_initialize_pt(vm, vm->scratch_pt);
1510
1511 return 0;
1512}
1513
1514static void gen6_free_scratch(struct i915_address_space *vm)
1515{
1516 struct drm_device *dev = vm->dev;
1517
1518 free_pt(dev, vm->scratch_pt);
1519 free_scratch_page(dev, vm->scratch_page);
1520}
1521
061dd493 1522static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1523{
061dd493
DV		 1524 struct i915_hw_ppgtt *ppgtt =
1525 container_of(vm, struct i915_hw_ppgtt, base);
09942c65
MT		 1526 struct i915_page_table *pt;
1527 uint32_t pde;
4933d519 1528
061dd493
DV		 1529 drm_mm_remove_node(&ppgtt->node);
1530
09942c65 1531 gen6_for_all_pdes(pt, ppgtt, pde) {
79ab9370 1532 if (pt != vm->scratch_pt)
a08e111a 1533 free_pt(ppgtt->base.dev, pt);
4933d519 1534 }
06fda602 1535
8776f02b 1536 gen6_free_scratch(vm);
3440d265
DV		 1537}
1538
b146520f 1539static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 1540{
8776f02b 1541 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 1542 struct drm_device *dev = ppgtt->base.dev;
1d2a314c 1543 struct drm_i915_private *dev_priv = dev->dev_private;
e3cc1995 1544 bool retried = false;
b146520f 1545 int ret;
1d2a314c 1546
c8d4c0d6
BW		 1547 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1548 * allocator works in address space sizes, so it's multiplied by page
1549 * size. We allocate at the top of the GTT to avoid fragmentation.
1550 */
1551 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
4933d519 1552
8776f02b
MK		 1553 ret = gen6_init_scratch(vm);
1554 if (ret)
1555 return ret;
4933d519 1556
e3cc1995 1557alloc:
c8d4c0d6
BW		 1558 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1559 &ppgtt->node, GEN6_PD_SIZE,
1560 GEN6_PD_ALIGN, 0,
1561 0, dev_priv->gtt.base.total,
3e8b5ae9 1562 DRM_MM_TOPDOWN);
e3cc1995
BW		 1563 if (ret == -ENOSPC && !retried) {
1564 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1565 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c
CW		 1566 I915_CACHE_NONE,
1567 0, dev_priv->gtt.base.total,
1568 0);
e3cc1995 1569 if (ret)
678d96fb 1570 goto err_out;
e3cc1995
BW		 1571
1572 retried = true;
1573 goto alloc;
1574 }
c8d4c0d6 1575
c8c26622 1576 if (ret)
678d96fb
BW		 1577 goto err_out;
1578
c8c26622 1579
c8d4c0d6
BW		 1580 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1581 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 1582
c8c26622 1583 return 0;
678d96fb
BW		 1584
1585err_out:
8776f02b 1586 gen6_free_scratch(vm);
678d96fb 1587 return ret;
b146520f
BW		 1588}
1589
b146520f
BW		 1590static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1591{
2f2cf682 1592 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 1593}
06dc68d6 1594
4933d519
MT		 1595static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1596 uint64_t start, uint64_t length)
1597{
ec565b3c 1598 struct i915_page_table *unused;
4933d519 1599 uint32_t pde, temp;
1d2a314c 1600
4933d519 1601 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
79ab9370 1602 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 1603}
1604
5c5f6457 1605static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 1606{
1607 struct drm_device *dev = ppgtt->base.dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 int ret;
1610
1611 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1612 if (IS_GEN6(dev)) {
b146520f
BW		 1613 ppgtt->switch_mm = gen6_mm_switch;
1614 } else if (IS_HASWELL(dev)) {
b146520f
BW		 1615 ppgtt->switch_mm = hsw_mm_switch;
1616 } else if (IS_GEN7(dev)) {
b146520f
BW		 1617 ppgtt->switch_mm = gen7_mm_switch;
1618 } else
1619 BUG();
1620
71ba2d64
YZ		 1621 if (intel_vgpu_active(dev))
1622 ppgtt->switch_mm = vgpu_mm_switch;
1623
b146520f
BW		 1624 ret = gen6_ppgtt_alloc(ppgtt);
1625 if (ret)
1626 return ret;
1627
5c5f6457 1628 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 1629 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1630 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 1631 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1632 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 1633 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 1634 ppgtt->base.start = 0;
09942c65 1635 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 1636 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 1637
44159ddb 1638 ppgtt->pd.base.ggtt_offset =
07749ef3 1639 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 1640
678d96fb 1641 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
44159ddb 1642 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 1643
5c5f6457 1644 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 1645
678d96fb
BW		 1646 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1647
440fd528 1648 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 1649 ppgtt->node.size >> 20,
1650 ppgtt->node.start / PAGE_SIZE);
3440d265 1651
fa76da34 1652 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 1653 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 1654
b146520f 1655 return 0;
3440d265
DV		 1656}
1657
5c5f6457 1658static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 1659{
853ba5d2 1660 ppgtt->base.dev = dev;
3440d265 1661
3ed124b2 1662 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 1663 return gen6_ppgtt_init(ppgtt);
3ed124b2 1664 else
d7b2633d 1665 return gen8_ppgtt_init(ppgtt);
fa76da34 1666}
c114f76a 1667
fa76da34
DV		 1668int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1669{
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int ret = 0;
3ed124b2 1672
5c5f6457 1673 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 1674 if (ret == 0) {
c7c48dfd 1675 kref_init(&ppgtt->ref);
93bd8649
BW		 1676 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1677 ppgtt->base.total);
7e0d96bc 1678 i915_init_vm(dev_priv, &ppgtt->base);
93bd8649 1679 }
1d2a314c
DV		 1680
1681 return ret;
1682}
1683
82460d97
DV		 1684int i915_ppgtt_init_hw(struct drm_device *dev)
1685{
671b5013
TD		 1686 /* In the case of execlists, PPGTT is enabled by the context descriptor
1687 * and the PDPs are contained within the context itself. We don't
1688 * need to do anything here. */
1689 if (i915.enable_execlists)
1690 return 0;
1691
82460d97
DV		 1692 if (!USES_PPGTT(dev))
1693 return 0;
1694
1695 if (IS_GEN6(dev))
1696 gen6_ppgtt_enable(dev);
1697 else if (IS_GEN7(dev))
1698 gen7_ppgtt_enable(dev);
1699 else if (INTEL_INFO(dev)->gen >= 8)
1700 gen8_ppgtt_enable(dev);
1701 else
5f77eeb0 1702 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 1703
4ad2fd88
JH		 1704 return 0;
1705}
1d2a314c 1706
b3dd6b96 1707int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
4ad2fd88 1708{
b3dd6b96 1709 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
4ad2fd88
JH		 1710 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1711
1712 if (i915.enable_execlists)
1713 return 0;
1714
1715 if (!ppgtt)
1716 return 0;
1717
e85b26dc 1718 return ppgtt->switch_mm(ppgtt, req);
1d2a314c 1719}
4ad2fd88 1720
4d884705
DV		 1721struct i915_hw_ppgtt *
1722i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1723{
1724 struct i915_hw_ppgtt *ppgtt;
1725 int ret;
1726
1727 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1728 if (!ppgtt)
1729 return ERR_PTR(-ENOMEM);
1730
1731 ret = i915_ppgtt_init(dev, ppgtt);
1732 if (ret) {
1733 kfree(ppgtt);
1734 return ERR_PTR(ret);
1735 }
1736
1737 ppgtt->file_priv = fpriv;
1738
198c974d
DCS		 1739 trace_i915_ppgtt_create(&ppgtt->base);
1740
4d884705
DV		 1741 return ppgtt;
1742}
1743
ee960be7
DV		 1744void i915_ppgtt_release(struct kref *kref)
1745{
1746 struct i915_hw_ppgtt *ppgtt =
1747 container_of(kref, struct i915_hw_ppgtt, ref);
1748
198c974d
DCS		 1749 trace_i915_ppgtt_release(&ppgtt->base);
1750
ee960be7
DV		 1751 /* vmas should already be unbound */
1752 WARN_ON(!list_empty(&ppgtt->base.active_list));
1753 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1754
19dd120c
DV		 1755 list_del(&ppgtt->base.global_link);
1756 drm_mm_takedown(&ppgtt->base.mm);
1757
ee960be7
DV		 1758 ppgtt->base.cleanup(&ppgtt->base);
1759 kfree(ppgtt);
1760}
1d2a314c 1761
a81cc00c
BW		 1762extern int intel_iommu_gfx_mapped;
1763/* Certain Gen5 chipsets require require idling the GPU before
1764 * unmapping anything from the GTT when VT-d is enabled.
1765 */
2c642b07 1766static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 1767{
1768#ifdef CONFIG_INTEL_IOMMU
1769 /* Query intel_iommu to see if we need the workaround. Presumably that
1770 * was loaded first.
1771 */
1772 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1773 return true;
1774#endif
1775 return false;
1776}
1777
5c042287
BW		 1778static bool do_idling(struct drm_i915_private *dev_priv)
1779{
1780 bool ret = dev_priv->mm.interruptible;
1781
a81cc00c 1782 if (unlikely(dev_priv->gtt.do_idle_maps)) {
5c042287 1783 dev_priv->mm.interruptible = false;
b2da9fe5 1784 if (i915_gpu_idle(dev_priv->dev)) {
5c042287
BW		 1785 DRM_ERROR("Couldn't idle GPU\n");
1786 /* Wait a bit, in hopes it avoids the hang */
1787 udelay(10);
1788 }
1789 }
1790
1791 return ret;
1792}
1793
1794static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1795{
a81cc00c 1796 if (unlikely(dev_priv->gtt.do_idle_maps))
5c042287
BW		 1797 dev_priv->mm.interruptible = interruptible;
1798}
1799
828c7908
BW		 1800void i915_check_and_clear_faults(struct drm_device *dev)
1801{
1802 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1803 struct intel_engine_cs *ring;
828c7908
BW		 1804 int i;
1805
1806 if (INTEL_INFO(dev)->gen < 6)
1807 return;
1808
1809 for_each_ring(ring, dev_priv, i) {
1810 u32 fault_reg;
1811 fault_reg = I915_READ(RING_FAULT_REG(ring));
1812 if (fault_reg & RING_FAULT_VALID) {
1813 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 1814 "\tAddr: 0x%08lx\n"
828c7908
BW		 1815 "\tAddress space: %s\n"
1816 "\tSource ID: %d\n"
1817 "\tType: %d\n",
1818 fault_reg & PAGE_MASK,
1819 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1820 RING_FAULT_SRCID(fault_reg),
1821 RING_FAULT_FAULT_TYPE(fault_reg));
1822 I915_WRITE(RING_FAULT_REG(ring),
1823 fault_reg & ~RING_FAULT_VALID);
1824 }
1825 }
1826 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1827}
1828
91e56499
CW		 1829static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1830{
1831 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1832 intel_gtt_chipset_flush();
1833 } else {
1834 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1835 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1836 }
1837}
1838
828c7908
BW		 1839void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1840{
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842
1843 /* Don't bother messing with faults pre GEN6 as we have little
1844 * documentation supporting that it's a good idea.
1845 */
1846 if (INTEL_INFO(dev)->gen < 6)
1847 return;
1848
1849 i915_check_and_clear_faults(dev);
1850
1851 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
782f1495
BW		 1852 dev_priv->gtt.base.start,
1853 dev_priv->gtt.base.total,
e568af1c 1854 true);
91e56499
CW		 1855
1856 i915_ggtt_flush(dev_priv);
828c7908
BW		 1857}
1858
74163907 1859int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 1860{
9da3da66
CW		 1861 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1862 obj->pages->sgl, obj->pages->nents,
1863 PCI_DMA_BIDIRECTIONAL))
1864 return -ENOSPC;
1865
1866 return 0;
7c2e6fdf
DV		 1867}
1868
2c642b07 1869static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 1870{
1871#ifdef writeq
1872 writeq(pte, addr);
1873#else
1874 iowrite32((u32)pte, addr);
1875 iowrite32(pte >> 32, addr + 4);
1876#endif
1877}
1878
1879static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1880 struct sg_table *st,
782f1495 1881 uint64_t start,
24f3a8cf 1882 enum i915_cache_level level, u32 unused)
94ec8f61
BW		 1883{
1884 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1885 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1886 gen8_pte_t __iomem *gtt_entries =
1887 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1888 int i = 0;
1889 struct sg_page_iter sg_iter;
57007df7 1890 dma_addr_t addr = 0; /* shut up gcc */
94ec8f61
BW		 1891
1892 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1893 addr = sg_dma_address(sg_iter.sg) +
1894 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1895 gen8_set_pte(&gtt_entries[i],
1896 gen8_pte_encode(addr, level, true));
1897 i++;
1898 }
1899
1900 /*
1901 * XXX: This serves as a posting read to make sure that the PTE has
1902 * actually been updated. There is some concern that even though
1903 * registers and PTEs are within the same BAR that they are potentially
1904 * of NUMA access patterns. Therefore, even with the way we assume
1905 * hardware should work, we must keep this posting read for paranoia.
1906 */
1907 if (i != 0)
1908 WARN_ON(readq(&gtt_entries[i-1])
1909 != gen8_pte_encode(addr, level, true));
1910
94ec8f61
BW		 1911 /* This next bit makes the above posting read even more important. We
1912 * want to flush the TLBs only after we're certain all the PTE updates
1913 * have finished.
1914 */
1915 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1916 POSTING_READ(GFX_FLSH_CNTL_GEN6);
94ec8f61
BW		 1917}
1918
e76e9aeb
BW		 1919/*
1920 * Binds an object into the global gtt with the specified cache level. The object
1921 * will be accessible to the GPU via commands whose operands reference offsets
1922 * within the global GTT as well as accessible by the GPU through the GMADR
1923 * mapped BAR (dev_priv->mm.gtt->gtt).
1924 */
853ba5d2 1925static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 1926 struct sg_table *st,
782f1495 1927 uint64_t start,
24f3a8cf 1928 enum i915_cache_level level, u32 flags)
e76e9aeb 1929{
853ba5d2 1930 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495 1931 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1932 gen6_pte_t __iomem *gtt_entries =
1933 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
6e995e23
ID		 1934 int i = 0;
1935 struct sg_page_iter sg_iter;
57007df7 1936 dma_addr_t addr = 0;
e76e9aeb 1937
6e995e23 1938 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2db76d7c 1939 addr = sg_page_iter_dma_address(&sg_iter);
24f3a8cf 1940 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
6e995e23 1941 i++;
e76e9aeb
BW		 1942 }
1943
e76e9aeb
BW		 1944 /* XXX: This serves as a posting read to make sure that the PTE has
1945 * actually been updated. There is some concern that even though
1946 * registers and PTEs are within the same BAR that they are potentially
1947 * of NUMA access patterns. Therefore, even with the way we assume
1948 * hardware should work, we must keep this posting read for paranoia.
1949 */
57007df7
PM		 1950 if (i != 0) {
1951 unsigned long gtt = readl(&gtt_entries[i-1]);
1952 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1953 }
0f9b91c7
BW		 1954
1955 /* This next bit makes the above posting read even more important. We
1956 * want to flush the TLBs only after we're certain all the PTE updates
1957 * have finished.
1958 */
1959 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1960 POSTING_READ(GFX_FLSH_CNTL_GEN6);
e76e9aeb
BW		 1961}
1962
94ec8f61 1963static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1964 uint64_t start,
1965 uint64_t length,
94ec8f61
BW		 1966 bool use_scratch)
1967{
1968 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 1969 unsigned first_entry = start >> PAGE_SHIFT;
1970 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1971 gen8_pte_t scratch_pte, __iomem *gtt_base =
1972 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
94ec8f61
BW		 1973 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1974 int i;
1975
1976 if (WARN(num_entries > max_entries,
1977 "First entry = %d; Num entries = %d (max=%d)\n",
1978 first_entry, num_entries, max_entries))
1979 num_entries = max_entries;
1980
c114f76a 1981 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 1982 I915_CACHE_LLC,
1983 use_scratch);
1984 for (i = 0; i < num_entries; i++)
1985 gen8_set_pte(&gtt_base[i], scratch_pte);
1986 readl(gtt_base);
1987}
1988
853ba5d2 1989static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1990 uint64_t start,
1991 uint64_t length,
828c7908 1992 bool use_scratch)
7faf1ab2 1993{
853ba5d2 1994 struct drm_i915_private *dev_priv = vm->dev->dev_private;
782f1495
BW		 1995 unsigned first_entry = start >> PAGE_SHIFT;
1996 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1997 gen6_pte_t scratch_pte, __iomem *gtt_base =
1998 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
a54c0c27 1999 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
7faf1ab2
DV		 2000 int i;
2001
2002 if (WARN(num_entries > max_entries,
2003 "First entry = %d; Num entries = %d (max=%d)\n",
2004 first_entry, num_entries, max_entries))
2005 num_entries = max_entries;
2006
c114f76a
MK		 2007 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2008 I915_CACHE_LLC, use_scratch, 0);
828c7908 2009
7faf1ab2
DV		 2010 for (i = 0; i < num_entries; i++)
2011 iowrite32(scratch_pte, &gtt_base[i]);
2012 readl(gtt_base);
2013}
2014
d369d2d9
DV		 2015static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2016 struct sg_table *pages,
2017 uint64_t start,
2018 enum i915_cache_level cache_level, u32 unused)
7faf1ab2
DV		 2019{
2020 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2021 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2022
d369d2d9 2023 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2024
7faf1ab2
DV		 2025}
2026
853ba5d2 2027static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2028 uint64_t start,
2029 uint64_t length,
828c7908 2030 bool unused)
7faf1ab2 2031{
782f1495
BW		 2032 unsigned first_entry = start >> PAGE_SHIFT;
2033 unsigned num_entries = length >> PAGE_SHIFT;
7faf1ab2
DV		 2034 intel_gtt_clear_range(first_entry, num_entries);
2035}
2036
70b9f6f8
DV		 2037static int ggtt_bind_vma(struct i915_vma *vma,
2038 enum i915_cache_level cache_level,
2039 u32 flags)
d5bd1449 2040{
6f65e29a 2041 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2042 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2043 struct drm_i915_gem_object *obj = vma->obj;
ec7adb6e 2044 struct sg_table *pages = obj->pages;
f329f5f6 2045 u32 pte_flags = 0;
70b9f6f8
DV		 2046 int ret;
2047
2048 ret = i915_get_ggtt_vma_pages(vma);
2049 if (ret)
2050 return ret;
2051 pages = vma->ggtt_view.pages;
7faf1ab2 2052
24f3a8cf
AG		 2053 /* Currently applicable only to VLV */
2054 if (obj->gt_ro)
f329f5f6 2055 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2056
ec7adb6e 2057
6f65e29a 2058 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
0875546c
DV		 2059 vma->vm->insert_entries(vma->vm, pages,
2060 vma->node.start,
2061 cache_level, pte_flags);
d0e30adc
CW		 2062
2063 /* Note the inconsistency here is due to absence of the
2064 * aliasing ppgtt on gen4 and earlier. Though we always
2065 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2066 * without the appgtt, we cannot honour that request and so
2067 * must substitute it with a global binding. Since we do this
2068 * behind the upper layers back, we need to explicitly set
2069 * the bound flag ourselves.
2070 */
2071 vma->bound |= GLOBAL_BIND;
2072
6f65e29a 2073 }
d5bd1449 2074
0875546c 2075 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
6f65e29a 2076 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
ec7adb6e 2077 appgtt->base.insert_entries(&appgtt->base, pages,
782f1495 2078 vma->node.start,
f329f5f6 2079 cache_level, pte_flags);
6f65e29a 2080 }
70b9f6f8
DV		 2081
2082 return 0;
d5bd1449
CW		 2083}
2084
6f65e29a 2085static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2086{
6f65e29a 2087 struct drm_device *dev = vma->vm->dev;
7faf1ab2 2088 struct drm_i915_private *dev_priv = dev->dev_private;
6f65e29a 2089 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2090 const uint64_t size = min_t(uint64_t,
2091 obj->base.size,
2092 vma->node.size);
6f65e29a 2093
aff43766 2094 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2095 vma->vm->clear_range(vma->vm,
2096 vma->node.start,
06615ee5 2097 size,
6f65e29a 2098 true);
6f65e29a 2099 }
74898d7e 2100
0875546c 2101 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2102 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2103
6f65e29a 2104 appgtt->base.clear_range(&appgtt->base,
782f1495 2105 vma->node.start,
06615ee5 2106 size,
6f65e29a 2107 true);
6f65e29a 2108 }
74163907
DV		 2109}
2110
2111void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2112{
5c042287
BW		 2113 struct drm_device *dev = obj->base.dev;
2114 struct drm_i915_private *dev_priv = dev->dev_private;
2115 bool interruptible;
2116
2117 interruptible = do_idling(dev_priv);
2118
5ec5b516
ID		 2119 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2120 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2121
2122 undo_idling(dev_priv, interruptible);
7c2e6fdf 2123}
644ec02b 2124
42d6ab48
CW		 2125static void i915_gtt_color_adjust(struct drm_mm_node *node,
2126 unsigned long color,
440fd528
TR		 2127 u64 *start,
2128 u64 *end)
42d6ab48
CW		 2129{
2130 if (node->color != color)
2131 *start += 4096;
2132
2133 if (!list_empty(&node->node_list)) {
2134 node = list_entry(node->node_list.next,
2135 struct drm_mm_node,
2136 node_list);
2137 if (node->allocated && node->color != color)
2138 *end -= 4096;
2139 }
2140}
fbe5d36e 2141
f548c0e9
DV		 2142static int i915_gem_setup_global_gtt(struct drm_device *dev,
2143 unsigned long start,
2144 unsigned long mappable_end,
2145 unsigned long end)
644ec02b 2146{
e78891ca
BW		 2147 /* Let GEM Manage all of the aperture.
2148 *
2149 * However, leave one page at the end still bound to the scratch page.
2150 * There are a number of places where the hardware apparently prefetches
2151 * past the end of the object, and we've seen multiple hangs with the
2152 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2153 * aperture. One page should be enough to keep any prefetching inside
2154 * of the aperture.
2155 */
40d74980
BW		 2156 struct drm_i915_private *dev_priv = dev->dev_private;
2157 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
ed2f3452
CW		 2158 struct drm_mm_node *entry;
2159 struct drm_i915_gem_object *obj;
2160 unsigned long hole_start, hole_end;
fa76da34 2161 int ret;
644ec02b 2162
35451cb6
BW		 2163 BUG_ON(mappable_end > end);
2164
ed2f3452 2165 /* Subtract the guard page ... */
40d74980 2166 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
5dda8fa3
YZ		 2167
2168 dev_priv->gtt.base.start = start;
2169 dev_priv->gtt.base.total = end - start;
2170
2171 if (intel_vgpu_active(dev)) {
2172 ret = intel_vgt_balloon(dev);
2173 if (ret)
2174 return ret;
2175 }
2176
42d6ab48 2177 if (!HAS_LLC(dev))
93bd8649 2178 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2179
ed2f3452 2180 /* Mark any preallocated objects as occupied */
35c20a60 2181 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
40d74980 2182 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
fa76da34 2183
edd41a87 2184 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
c6cfb325
BW		 2185 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2186
2187 WARN_ON(i915_gem_obj_ggtt_bound(obj));
40d74980 2188 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
6c5566a8
DV		 2189 if (ret) {
2190 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2191 return ret;
2192 }
aff43766 2193 vma->bound |= GLOBAL_BIND;
ed2f3452
CW		 2194 }
2195
ed2f3452 2196 /* Clear any non-preallocated blocks */
40d74980 2197 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
ed2f3452
CW		 2198 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2199 hole_start, hole_end);
782f1495
BW		 2200 ggtt_vm->clear_range(ggtt_vm, hole_start,
2201 hole_end - hole_start, true);
ed2f3452
CW		 2202 }
2203
2204 /* And finally clear the reserved guard page */
782f1495 2205 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2206
fa76da34
DV		 2207 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2208 struct i915_hw_ppgtt *ppgtt;
2209
2210 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2211 if (!ppgtt)
2212 return -ENOMEM;
2213
5c5f6457
DV		 2214 ret = __hw_ppgtt_init(dev, ppgtt);
2215 if (ret) {
2216 ppgtt->base.cleanup(&ppgtt->base);
2217 kfree(ppgtt);
2218 return ret;
2219 }
2220
2221 if (ppgtt->base.allocate_va_range)
2222 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2223 ppgtt->base.total);
4933d519 2224 if (ret) {
061dd493 2225 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2226 kfree(ppgtt);
fa76da34 2227 return ret;
4933d519 2228 }
fa76da34 2229
5c5f6457
DV		 2230 ppgtt->base.clear_range(&ppgtt->base,
2231 ppgtt->base.start,
2232 ppgtt->base.total,
2233 true);
2234
fa76da34
DV		 2235 dev_priv->mm.aliasing_ppgtt = ppgtt;
2236 }
2237
6c5566a8 2238 return 0;
e76e9aeb
BW		 2239}
2240
d7e5008f
BW		 2241void i915_gem_init_global_gtt(struct drm_device *dev)
2242{
2243 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2244 u64 gtt_size, mappable_size;
d7e5008f 2245
853ba5d2 2246 gtt_size = dev_priv->gtt.base.total;
93d18799 2247 mappable_size = dev_priv->gtt.mappable_end;
d7e5008f 2248
e78891ca 2249 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
e76e9aeb
BW		 2250}
2251
90d0a0e8
DV		 2252void i915_global_gtt_cleanup(struct drm_device *dev)
2253{
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct i915_address_space *vm = &dev_priv->gtt.base;
2256
70e32544
DV		 2257 if (dev_priv->mm.aliasing_ppgtt) {
2258 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2259
2260 ppgtt->base.cleanup(&ppgtt->base);
2261 }
2262
90d0a0e8 2263 if (drm_mm_initialized(&vm->mm)) {
5dda8fa3
YZ		 2264 if (intel_vgpu_active(dev))
2265 intel_vgt_deballoon();
2266
90d0a0e8
DV		 2267 drm_mm_takedown(&vm->mm);
2268 list_del(&vm->global_link);
2269 }
2270
2271 vm->cleanup(vm);
2272}
70e32544 2273
2c642b07 2274static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2275{
2276 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2277 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2278 return snb_gmch_ctl << 20;
2279}
2280
2c642b07 2281static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2282{
2283 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2284 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2285 if (bdw_gmch_ctl)
2286 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2287
2288#ifdef CONFIG_X86_32
2289 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2290 if (bdw_gmch_ctl > 4)
2291 bdw_gmch_ctl = 4;
2292#endif
2293
9459d252
BW		 2294 return bdw_gmch_ctl << 20;
2295}
2296
2c642b07 2297static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2298{
2299 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2300 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2301
2302 if (gmch_ctrl)
2303 return 1 << (20 + gmch_ctrl);
2304
2305 return 0;
2306}
2307
2c642b07 2308static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2309{
2310 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2311 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2312 return snb_gmch_ctl << 25; /* 32 MB units */
2313}
2314
2c642b07 2315static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2316{
2317 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2318 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2319 return bdw_gmch_ctl << 25; /* 32 MB units */
2320}
2321
d7f25f23
DL		 2322static size_t chv_get_stolen_size(u16 gmch_ctrl)
2323{
2324 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2325 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2326
2327 /*
2328 * 0x0 to 0x10: 32MB increments starting at 0MB
2329 * 0x11 to 0x16: 4MB increments starting at 8MB
2330 * 0x17 to 0x1d: 4MB increments start at 36MB
2331 */
2332 if (gmch_ctrl < 0x11)
2333 return gmch_ctrl << 25;
2334 else if (gmch_ctrl < 0x17)
2335 return (gmch_ctrl - 0x11 + 2) << 22;
2336 else
2337 return (gmch_ctrl - 0x17 + 9) << 22;
2338}
2339
66375014
DL		 2340static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2341{
2342 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2343 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2344
2345 if (gen9_gmch_ctl < 0xf0)
2346 return gen9_gmch_ctl << 25; /* 32 MB units */
2347 else
2348 /* 4MB increments starting at 0xf0 for 4MB */
2349 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2350}
2351
63340133
BW		 2352static int ggtt_probe_common(struct drm_device *dev,
2353 size_t gtt_size)
2354{
2355 struct drm_i915_private *dev_priv = dev->dev_private;
4ad2af1e 2356 struct i915_page_scratch *scratch_page;
21c34607 2357 phys_addr_t gtt_phys_addr;
63340133
BW		 2358
2359 /* For Modern GENs the PTEs and register space are split in the BAR */
21c34607 2360 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
63340133
BW		 2361 (pci_resource_len(dev->pdev, 0) / 2);
2362
2a073f89
ID		 2363 /*
2364 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2365 * dropped. For WC mappings in general we have 64 byte burst writes
2366 * when the WC buffer is flushed, so we can't use it, but have to
2367 * resort to an uncached mapping. The WC issue is easily caught by the
2368 * readback check when writing GTT PTE entries.
2369 */
2370 if (IS_BROXTON(dev))
2371 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2372 else
2373 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
63340133
BW		 2374 if (!dev_priv->gtt.gsm) {
2375 DRM_ERROR("Failed to map the gtt page table\n");
2376 return -ENOMEM;
2377 }
2378
4ad2af1e
MK		 2379 scratch_page = alloc_scratch_page(dev);
2380 if (IS_ERR(scratch_page)) {
63340133
BW		 2381 DRM_ERROR("Scratch setup failed\n");
2382 /* iounmap will also get called at remove, but meh */
2383 iounmap(dev_priv->gtt.gsm);
4ad2af1e 2384 return PTR_ERR(scratch_page);
63340133
BW		 2385 }
2386
4ad2af1e
MK		 2387 dev_priv->gtt.base.scratch_page = scratch_page;
2388
2389 return 0;
63340133
BW		 2390}
2391
fbe5d36e
BW		 2392/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2393 * bits. When using advanced contexts each context stores its own PAT, but
2394 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 2395static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 2396{
fbe5d36e
BW		 2397 uint64_t pat;
2398
2399 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2400 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2401 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2402 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2403 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2404 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2405 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2406 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2407
d6a8b72e
RV		 2408 if (!USES_PPGTT(dev_priv->dev))
2409 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2410 * so RTL will always use the value corresponding to
2411 * pat_sel = 000".
2412 * So let's disable cache for GGTT to avoid screen corruptions.
2413 * MOCS still can be used though.
2414 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2415 * before this patch, i.e. the same uncached + snooping access
2416 * like on gen6/7 seems to be in effect.
2417 * - So this just fixes blitter/render access. Again it looks
2418 * like it's not just uncached access, but uncached + snooping.
2419 * So we can still hold onto all our assumptions wrt cpu
2420 * clflushing on LLC machines.
2421 */
2422 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2423
fbe5d36e
BW		 2424 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2425 * write would work. */
2426 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2427 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2428}
2429
ee0ce478
VS		 2430static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2431{
2432 uint64_t pat;
2433
2434 /*
2435 * Map WB on BDW to snooped on CHV.
2436 *
2437 * Only the snoop bit has meaning for CHV, the rest is
2438 * ignored.
2439 *
cf3d262e
VS		 2440 * The hardware will never snoop for certain types of accesses:
2441 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2442 * - PPGTT page tables
2443 * - some other special cycles
2444 *
2445 * As with BDW, we also need to consider the following for GT accesses:
2446 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2447 * so RTL will always use the value corresponding to
2448 * pat_sel = 000".
2449 * Which means we must set the snoop bit in PAT entry 0
2450 * in order to keep the global status page working.
ee0ce478
VS		 2451 */
2452 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2453 GEN8_PPAT(1, 0) |
2454 GEN8_PPAT(2, 0) |
2455 GEN8_PPAT(3, 0) |
2456 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2457 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2458 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2459 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2460
2461 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2462 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2463}
2464
63340133 2465static int gen8_gmch_probe(struct drm_device *dev,
c44ef60e 2466 u64 *gtt_total,
63340133
BW		 2467 size_t *stolen,
2468 phys_addr_t *mappable_base,
c44ef60e 2469 u64 *mappable_end)
63340133
BW		 2470{
2471 struct drm_i915_private *dev_priv = dev->dev_private;
c44ef60e 2472 u64 gtt_size;
63340133
BW		 2473 u16 snb_gmch_ctl;
2474 int ret;
2475
2476 /* TODO: We're not aware of mappable constraints on gen8 yet */
2477 *mappable_base = pci_resource_start(dev->pdev, 2);
2478 *mappable_end = pci_resource_len(dev->pdev, 2);
2479
2480 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2481 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2482
2483 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2484
66375014
DL		 2485 if (INTEL_INFO(dev)->gen >= 9) {
2486 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2487 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2488 } else if (IS_CHERRYVIEW(dev)) {
d7f25f23
DL		 2489 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2490 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2491 } else {
2492 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2493 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2494 }
63340133 2495
07749ef3 2496 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 2497
5a4e33a3 2498 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 2499 chv_setup_private_ppat(dev_priv);
2500 else
2501 bdw_setup_private_ppat(dev_priv);
fbe5d36e 2502
63340133
BW		 2503 ret = ggtt_probe_common(dev, gtt_size);
2504
94ec8f61
BW		 2505 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2506 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
777dc5bb
DV		 2507 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2508 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
63340133
BW		 2509
2510 return ret;
2511}
2512
baa09f5f 2513static int gen6_gmch_probe(struct drm_device *dev,
c44ef60e 2514 u64 *gtt_total,
41907ddc
BW		 2515 size_t *stolen,
2516 phys_addr_t *mappable_base,
c44ef60e 2517 u64 *mappable_end)
e76e9aeb
BW		 2518{
2519 struct drm_i915_private *dev_priv = dev->dev_private;
baa09f5f 2520 unsigned int gtt_size;
e76e9aeb 2521 u16 snb_gmch_ctl;
e76e9aeb
BW		 2522 int ret;
2523
41907ddc
BW		 2524 *mappable_base = pci_resource_start(dev->pdev, 2);
2525 *mappable_end = pci_resource_len(dev->pdev, 2);
2526
baa09f5f
BW		 2527 /* 64/512MB is the current min/max we actually know of, but this is just
2528 * a coarse sanity check.
e76e9aeb 2529 */
41907ddc 2530 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
c44ef60e 2531 DRM_ERROR("Unknown GMADR size (%llx)\n",
baa09f5f
BW		 2532 dev_priv->gtt.mappable_end);
2533 return -ENXIO;
e76e9aeb
BW		 2534 }
2535
e76e9aeb
BW		 2536 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2537 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 2538 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 2539
c4ae25ec 2540 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
a93e4161 2541
63340133 2542 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
07749ef3 2543 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 2544
63340133 2545 ret = ggtt_probe_common(dev, gtt_size);
e76e9aeb 2546
853ba5d2
BW		 2547 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2548 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
777dc5bb
DV		 2549 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2550 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 2551
e76e9aeb
BW		 2552 return ret;
2553}
2554
853ba5d2 2555static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 2556{
853ba5d2
BW		 2557
2558 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
5ed16782 2559
853ba5d2 2560 iounmap(gtt->gsm);
4ad2af1e 2561 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 2562}
baa09f5f
BW		 2563
2564static int i915_gmch_probe(struct drm_device *dev,
c44ef60e 2565 u64 *gtt_total,
41907ddc
BW		 2566 size_t *stolen,
2567 phys_addr_t *mappable_base,
c44ef60e 2568 u64 *mappable_end)
baa09f5f
BW		 2569{
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 int ret;
2572
baa09f5f
BW		 2573 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2574 if (!ret) {
2575 DRM_ERROR("failed to set up gmch\n");
2576 return -EIO;
2577 }
2578
41907ddc 2579 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
baa09f5f
BW		 2580
2581 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
d369d2d9 2582 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
853ba5d2 2583 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
d369d2d9
DV		 2584 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2585 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
baa09f5f 2586
c0a7f818
CW		 2587 if (unlikely(dev_priv->gtt.do_idle_maps))
2588 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2589
baa09f5f
BW		 2590 return 0;
2591}
2592
853ba5d2 2593static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 2594{
2595 intel_gmch_remove();
2596}
2597
2598int i915_gem_gtt_init(struct drm_device *dev)
2599{
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct i915_gtt *gtt = &dev_priv->gtt;
baa09f5f
BW		 2602 int ret;
2603
baa09f5f 2604 if (INTEL_INFO(dev)->gen <= 5) {
b2f21b4d 2605 gtt->gtt_probe = i915_gmch_probe;
853ba5d2 2606 gtt->base.cleanup = i915_gmch_remove;
63340133 2607 } else if (INTEL_INFO(dev)->gen < 8) {
b2f21b4d 2608 gtt->gtt_probe = gen6_gmch_probe;
853ba5d2 2609 gtt->base.cleanup = gen6_gmch_remove;
4d15c145 2610 if (IS_HASWELL(dev) && dev_priv->ellc_size)
853ba5d2 2611 gtt->base.pte_encode = iris_pte_encode;
4d15c145 2612 else if (IS_HASWELL(dev))
853ba5d2 2613 gtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 2614 else if (IS_VALLEYVIEW(dev))
853ba5d2 2615 gtt->base.pte_encode = byt_pte_encode;
350ec881
CW		 2616 else if (INTEL_INFO(dev)->gen >= 7)
2617 gtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 2618 else
350ec881 2619 gtt->base.pte_encode = snb_pte_encode;
63340133
BW		 2620 } else {
2621 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2622 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 2623 }
2624
c114f76a
MK		 2625 gtt->base.dev = dev;
2626
853ba5d2 2627 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
b2f21b4d 2628 &gtt->mappable_base, &gtt->mappable_end);
a54c0c27 2629 if (ret)
baa09f5f 2630 return ret;
baa09f5f 2631
baa09f5f 2632 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 2633 DRM_INFO("Memory usable by graphics device = %lluM\n",
853ba5d2 2634 gtt->base.total >> 20);
c44ef60e 2635 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
b2f21b4d 2636 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
5db6c735
DV		 2637#ifdef CONFIG_INTEL_IOMMU
2638 if (intel_iommu_gfx_mapped)
2639 DRM_INFO("VT-d active for gfx access\n");
2640#endif
cfa7c862
DV		 2641 /*
2642 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2643 * user's requested state against the hardware/driver capabilities. We
2644 * do this now so that we can print out any log messages once rather
2645 * than every time we check intel_enable_ppgtt().
2646 */
2647 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2648 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
baa09f5f
BW		 2649
2650 return 0;
2651}
6f65e29a 2652
fa42331b
DV		 2653void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2654{
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct drm_i915_gem_object *obj;
2657 struct i915_address_space *vm;
2c3d9984
TU		 2658 struct i915_vma *vma;
2659 bool flush;
fa42331b
DV		 2660
2661 i915_check_and_clear_faults(dev);
2662
2663 /* First fill our portion of the GTT with scratch pages */
2664 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2665 dev_priv->gtt.base.start,
2666 dev_priv->gtt.base.total,
2667 true);
2668
2c3d9984
TU		 2669 /* Cache flush objects bound into GGTT and rebind them. */
2670 vm = &dev_priv->gtt.base;
fa42331b 2671 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2c3d9984
TU		 2672 flush = false;
2673 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2674 if (vma->vm != vm)
2675 continue;
fa42331b 2676
2c3d9984
TU		 2677 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2678 PIN_UPDATE));
fa42331b 2679
2c3d9984
TU		 2680 flush = true;
2681 }
2682
2683 if (flush)
2684 i915_gem_clflush_object(obj, obj->pin_display);
2685 }
fa42331b
DV		 2686
2687 if (INTEL_INFO(dev)->gen >= 8) {
2688 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2689 chv_setup_private_ppat(dev_priv);
2690 else
2691 bdw_setup_private_ppat(dev_priv);
2692
2693 return;
2694 }
2695
2696 if (USES_PPGTT(dev)) {
2697 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2698 /* TODO: Perhaps it shouldn't be gen6 specific */
2699
2700 struct i915_hw_ppgtt *ppgtt =
2701 container_of(vm, struct i915_hw_ppgtt,
2702 base);
2703
2704 if (i915_is_ggtt(vm))
2705 ppgtt = dev_priv->mm.aliasing_ppgtt;
2706
2707 gen6_write_page_range(dev_priv, &ppgtt->pd,
2708 0, ppgtt->base.total);
2709 }
2710 }
2711
2712 i915_ggtt_flush(dev_priv);
2713}
2714
ec7adb6e
JL		 2715static struct i915_vma *
2716__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2717 struct i915_address_space *vm,
2718 const struct i915_ggtt_view *ggtt_view)
6f65e29a 2719{
dabde5c7 2720 struct i915_vma *vma;
6f65e29a 2721
ec7adb6e
JL		 2722 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2723 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 2724
2725 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 2726 if (vma == NULL)
2727 return ERR_PTR(-ENOMEM);
ec7adb6e 2728
6f65e29a
BW		 2729 INIT_LIST_HEAD(&vma->vma_link);
2730 INIT_LIST_HEAD(&vma->mm_list);
2731 INIT_LIST_HEAD(&vma->exec_list);
2732 vma->vm = vm;
2733 vma->obj = obj;
2734
777dc5bb 2735 if (i915_is_ggtt(vm))
ec7adb6e 2736 vma->ggtt_view = *ggtt_view;
6f65e29a 2737
f7635669
TU		 2738 list_add_tail(&vma->vma_link, &obj->vma_list);
2739 if (!i915_is_ggtt(vm))
e07f0552 2740 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a
BW		 2741
2742 return vma;
2743}
2744
2745struct i915_vma *
ec7adb6e
JL		 2746i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2747 struct i915_address_space *vm)
2748{
2749 struct i915_vma *vma;
2750
2751 vma = i915_gem_obj_to_vma(obj, vm);
2752 if (!vma)
2753 vma = __i915_gem_vma_create(obj, vm,
2754 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2755
2756 return vma;
2757}
2758
2759struct i915_vma *
2760i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 2761 const struct i915_ggtt_view *view)
6f65e29a 2762{
ec7adb6e 2763 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
6f65e29a
BW		 2764 struct i915_vma *vma;
2765
ec7adb6e
JL		 2766 if (WARN_ON(!view))
2767 return ERR_PTR(-EINVAL);
2768
2769 vma = i915_gem_obj_to_ggtt_view(obj, view);
2770
2771 if (IS_ERR(vma))
2772 return vma;
2773
6f65e29a 2774 if (!vma)
ec7adb6e 2775 vma = __i915_gem_vma_create(obj, ggtt, view);
6f65e29a
BW		 2776
2777 return vma;
ec7adb6e 2778
6f65e29a 2779}
fe14d5f4 2780
50470bb0
TU		 2781static void
2782rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2783 struct sg_table *st)
2784{
2785 unsigned int column, row;
2786 unsigned int src_idx;
2787 struct scatterlist *sg = st->sgl;
2788
2789 st->nents = 0;
2790
2791 for (column = 0; column < width; column++) {
2792 src_idx = width * (height - 1) + column;
2793 for (row = 0; row < height; row++) {
2794 st->nents++;
2795 /* We don't need the pages, but need to initialize
2796 * the entries so the sg list can be happily traversed.
2797 * The only thing we need are DMA addresses.
2798 */
2799 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2800 sg_dma_address(sg) = in[src_idx];
2801 sg_dma_len(sg) = PAGE_SIZE;
2802 sg = sg_next(sg);
2803 src_idx -= width;
2804 }
2805 }
2806}
2807
2808static struct sg_table *
2809intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2810 struct drm_i915_gem_object *obj)
2811{
50470bb0 2812 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
84fe03f7 2813 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
50470bb0
TU		 2814 struct sg_page_iter sg_iter;
2815 unsigned long i;
2816 dma_addr_t *page_addr_list;
2817 struct sg_table *st;
1d00dad5 2818 int ret = -ENOMEM;
50470bb0 2819
50470bb0 2820 /* Allocate a temporary list of source pages for random access. */
84fe03f7
TU		 2821 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2822 sizeof(dma_addr_t));
50470bb0
TU		 2823 if (!page_addr_list)
2824 return ERR_PTR(ret);
2825
2826 /* Allocate target SG list. */
2827 st = kmalloc(sizeof(*st), GFP_KERNEL);
2828 if (!st)
2829 goto err_st_alloc;
2830
84fe03f7 2831 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
50470bb0
TU		 2832 if (ret)
2833 goto err_sg_alloc;
2834
2835 /* Populate source page list from the object. */
2836 i = 0;
2837 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2838 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2839 i++;
2840 }
2841
2842 /* Rotate the pages. */
84fe03f7
TU		 2843 rotate_pages(page_addr_list,
2844 rot_info->width_pages, rot_info->height_pages,
2845 st);
50470bb0
TU		 2846
2847 DRM_DEBUG_KMS(
84fe03f7 2848 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
c9f8fd2d 2849 obj->base.size, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2850 rot_info->pixel_format, rot_info->width_pages,
2851 rot_info->height_pages, size_pages);
50470bb0
TU		 2852
2853 drm_free_large(page_addr_list);
2854
2855 return st;
2856
2857err_sg_alloc:
2858 kfree(st);
2859err_st_alloc:
2860 drm_free_large(page_addr_list);
2861
2862 DRM_DEBUG_KMS(
84fe03f7 2863 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
c9f8fd2d 2864 obj->base.size, ret, rot_info->pitch, rot_info->height,
84fe03f7
TU		 2865 rot_info->pixel_format, rot_info->width_pages,
2866 rot_info->height_pages, size_pages);
50470bb0
TU		 2867 return ERR_PTR(ret);
2868}
ec7adb6e 2869
8bd7ef16
JL		 2870static struct sg_table *
2871intel_partial_pages(const struct i915_ggtt_view *view,
2872 struct drm_i915_gem_object *obj)
2873{
2874 struct sg_table *st;
2875 struct scatterlist *sg;
2876 struct sg_page_iter obj_sg_iter;
2877 int ret = -ENOMEM;
2878
2879 st = kmalloc(sizeof(*st), GFP_KERNEL);
2880 if (!st)
2881 goto err_st_alloc;
2882
2883 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2884 if (ret)
2885 goto err_sg_alloc;
2886
2887 sg = st->sgl;
2888 st->nents = 0;
2889 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2890 view->params.partial.offset)
2891 {
2892 if (st->nents >= view->params.partial.size)
2893 break;
2894
2895 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2896 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2897 sg_dma_len(sg) = PAGE_SIZE;
2898
2899 sg = sg_next(sg);
2900 st->nents++;
2901 }
2902
2903 return st;
2904
2905err_sg_alloc:
2906 kfree(st);
2907err_st_alloc:
2908 return ERR_PTR(ret);
2909}
2910
70b9f6f8 2911static int
50470bb0 2912i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 2913{
50470bb0
TU		 2914 int ret = 0;
2915
fe14d5f4
TU		 2916 if (vma->ggtt_view.pages)
2917 return 0;
2918
2919 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2920 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 2921 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2922 vma->ggtt_view.pages =
2923 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
8bd7ef16
JL		 2924 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2925 vma->ggtt_view.pages =
2926 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 2927 else
2928 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2929 vma->ggtt_view.type);
2930
2931 if (!vma->ggtt_view.pages) {
ec7adb6e 2932 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 2933 vma->ggtt_view.type);
50470bb0
TU		 2934 ret = -EINVAL;
2935 } else if (IS_ERR(vma->ggtt_view.pages)) {
2936 ret = PTR_ERR(vma->ggtt_view.pages);
2937 vma->ggtt_view.pages = NULL;
2938 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2939 vma->ggtt_view.type, ret);
fe14d5f4
TU		 2940 }
2941
50470bb0 2942 return ret;
fe14d5f4
TU		 2943}
2944
2945/**
2946 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2947 * @vma: VMA to map
2948 * @cache_level: mapping cache level
2949 * @flags: flags like global or local mapping
2950 *
2951 * DMA addresses are taken from the scatter-gather table of this object (or of
2952 * this VMA in case of non-default GGTT views) and PTE entries set up.
2953 * Note that DMA addresses are also the only part of the SG table we care about.
2954 */
2955int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2956 u32 flags)
2957{
75d04a37
MK		 2958 int ret;
2959 u32 bind_flags;
1d335d1b 2960
75d04a37
MK		 2961 if (WARN_ON(flags == 0))
2962 return -EINVAL;
1d335d1b 2963
75d04a37 2964 bind_flags = 0;
0875546c
DV		 2965 if (flags & PIN_GLOBAL)
2966 bind_flags |= GLOBAL_BIND;
2967 if (flags & PIN_USER)
2968 bind_flags |= LOCAL_BIND;
2969
2970 if (flags & PIN_UPDATE)
2971 bind_flags |= vma->bound;
2972 else
2973 bind_flags &= ~vma->bound;
2974
75d04a37
MK		 2975 if (bind_flags == 0)
2976 return 0;
2977
2978 if (vma->bound == 0 && vma->vm->allocate_va_range) {
2979 trace_i915_va_alloc(vma->vm,
2980 vma->node.start,
2981 vma->node.size,
2982 VM_TO_TRACE_NAME(vma->vm));
2983
b2dd4511
MK		 2984 /* XXX: i915_vma_pin() will fix this +- hack */
2985 vma->pin_count++;
75d04a37
MK		 2986 ret = vma->vm->allocate_va_range(vma->vm,
2987 vma->node.start,
2988 vma->node.size);
b2dd4511 2989 vma->pin_count--;
75d04a37
MK		 2990 if (ret)
2991 return ret;
2992 }
2993
2994 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 2995 if (ret)
2996 return ret;
0875546c
DV		 2997
2998 vma->bound |= bind_flags;
fe14d5f4
TU		 2999
3000 return 0;
3001}
91e6711e
JL		 3002
3003/**
3004 * i915_ggtt_view_size - Get the size of a GGTT view.
3005 * @obj: Object the view is of.
3006 * @view: The view in question.
3007 *
3008 * @return The size of the GGTT view in bytes.
3009 */
3010size_t
3011i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3012 const struct i915_ggtt_view *view)
3013{
9e759ff1 3014 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3015 return obj->base.size;
9e759ff1
TU		 3016 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3017 return view->rotation_info.size;
8bd7ef16
JL		 3018 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3019 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3020 } else {
3021 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3022 return obj->base.size;
3023 }
3024}
Linux kernel - Deliverables
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