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drm/i915: Mass convert dev->dev_private to to_i915(dev)
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_gtt.c
CommitLineData
76aaf220
DV		 1/*
2 * Copyright © 2010 Daniel Vetter
c4ac524c 3 * Copyright © 2011-2014 Intel Corporation
76aaf220
DV		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
0e46ce2e 26#include <linux/seq_file.h>
5bab6f60 27#include <linux/stop_machine.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
76aaf220 30#include "i915_drv.h"
5dda8fa3 31#include "i915_vgpu.h"
76aaf220
DV		 32#include "i915_trace.h"
33#include "intel_drv.h"
34
45f8f69a
TU		 35/**
36 * DOC: Global GTT views
37 *
38 * Background and previous state
39 *
40 * Historically objects could exists (be bound) in global GTT space only as
41 * singular instances with a view representing all of the object's backing pages
42 * in a linear fashion. This view will be called a normal view.
43 *
44 * To support multiple views of the same object, where the number of mapped
45 * pages is not equal to the backing store, or where the layout of the pages
46 * is not linear, concept of a GGTT view was added.
47 *
48 * One example of an alternative view is a stereo display driven by a single
49 * image. In this case we would have a framebuffer looking like this
50 * (2x2 pages):
51 *
52 * 12
53 * 34
54 *
55 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
56 * rendering. In contrast, fed to the display engine would be an alternative
57 * view which could look something like this:
58 *
59 * 1212
60 * 3434
61 *
62 * In this example both the size and layout of pages in the alternative view is
63 * different from the normal view.
64 *
65 * Implementation and usage
66 *
67 * GGTT views are implemented using VMAs and are distinguished via enum
68 * i915_ggtt_view_type and struct i915_ggtt_view.
69 *
70 * A new flavour of core GEM functions which work with GGTT bound objects were
ec7adb6e
JL		 71 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
72 * renaming in large amounts of code. They take the struct i915_ggtt_view
73 * parameter encapsulating all metadata required to implement a view.
45f8f69a
TU		 74 *
75 * As a helper for callers which are only interested in the normal view,
76 * globally const i915_ggtt_view_normal singleton instance exists. All old core
77 * GEM API functions, the ones not taking the view parameter, are operating on,
78 * or with the normal GGTT view.
79 *
80 * Code wanting to add or use a new GGTT view needs to:
81 *
82 * 1. Add a new enum with a suitable name.
83 * 2. Extend the metadata in the i915_ggtt_view structure if required.
84 * 3. Add support to i915_get_vma_pages().
85 *
86 * New views are required to build a scatter-gather table from within the
87 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
88 * exists for the lifetime of an VMA.
89 *
90 * Core API is designed to have copy semantics which means that passed in
91 * struct i915_ggtt_view does not need to be persistent (left around after
92 * calling the core API functions).
93 *
94 */
95
ce7fda2e
CW		 96static inline struct i915_ggtt *
97i915_vm_to_ggtt(struct i915_address_space *vm)
98{
99 GEM_BUG_ON(!i915_is_ggtt(vm));
100 return container_of(vm, struct i915_ggtt, base);
101}
102
70b9f6f8
DV		 103static int
104i915_get_ggtt_vma_pages(struct i915_vma *vma);
105
b5e16987
VS		 106const struct i915_ggtt_view i915_ggtt_view_normal = {
107 .type = I915_GGTT_VIEW_NORMAL,
108};
9abc4648 109const struct i915_ggtt_view i915_ggtt_view_rotated = {
b5e16987 110 .type = I915_GGTT_VIEW_ROTATED,
9abc4648 111};
fe14d5f4 112
c033666a
CW		 113int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
114 int enable_ppgtt)
cfa7c862 115{
1893a71b
CW		 116 bool has_aliasing_ppgtt;
117 bool has_full_ppgtt;
1f9a99e0 118 bool has_full_48bit_ppgtt;
1893a71b 119
c033666a
CW		 120 has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
121 has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
122 has_full_48bit_ppgtt =
123 IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
1893a71b 124
c033666a 125 if (intel_vgpu_active(dev_priv))
71ba2d64
YZ		 126 has_full_ppgtt = false; /* emulation is too hard */
127
0e4ca100
CW		 128 if (!has_aliasing_ppgtt)
129 return 0;
130
70ee45e1
DL		 131 /*
132 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
133 * execlists, the sole mechanism available to submit work.
134 */
c033666a 135 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
cfa7c862
DV		 136 return 0;
137
138 if (enable_ppgtt == 1)
139 return 1;
140
1893a71b 141 if (enable_ppgtt == 2 && has_full_ppgtt)
cfa7c862
DV		 142 return 2;
143
1f9a99e0
MT		 144 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
145 return 3;
146
93a25a9e
DV		 147#ifdef CONFIG_INTEL_IOMMU
148 /* Disable ppgtt on SNB if VT-d is on. */
c033666a 149 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
93a25a9e 150 DRM_INFO("Disabling PPGTT because VT-d is on\n");
cfa7c862 151 return 0;
93a25a9e
DV		 152 }
153#endif
154
62942ed7 155 /* Early VLV doesn't have this */
c033666a 156 if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
62942ed7
JB		 157 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
158 return 0;
159 }
160
c033666a 161 if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
1f9a99e0 162 return has_full_48bit_ppgtt ? 3 : 2;
2f82bbdf
MT		 163 else
164 return has_aliasing_ppgtt ? 1 : 0;
93a25a9e
DV		 165}
166
70b9f6f8
DV		 167static int ppgtt_bind_vma(struct i915_vma *vma,
168 enum i915_cache_level cache_level,
169 u32 unused)
47552659
DV		 170{
171 u32 pte_flags = 0;
172
173 /* Currently applicable only to VLV */
174 if (vma->obj->gt_ro)
175 pte_flags |= PTE_READ_ONLY;
176
177 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
178 cache_level, pte_flags);
70b9f6f8
DV		 179
180 return 0;
47552659
DV		 181}
182
183static void ppgtt_unbind_vma(struct i915_vma *vma)
184{
185 vma->vm->clear_range(vma->vm,
186 vma->node.start,
187 vma->obj->base.size,
188 true);
189}
6f65e29a 190
2c642b07
DV		 191static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
192 enum i915_cache_level level,
193 bool valid)
94ec8f61 194{
07749ef3 195 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
94ec8f61 196 pte |= addr;
63c42e56
BW		 197
198 switch (level) {
199 case I915_CACHE_NONE:
fbe5d36e 200 pte |= PPAT_UNCACHED_INDEX;
63c42e56
BW		 201 break;
202 case I915_CACHE_WT:
203 pte |= PPAT_DISPLAY_ELLC_INDEX;
204 break;
205 default:
206 pte |= PPAT_CACHED_INDEX;
207 break;
208 }
209
94ec8f61
BW		 210 return pte;
211}
212
fe36f55d
MK		 213static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
214 const enum i915_cache_level level)
b1fe6673 215{
07749ef3 216 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
b1fe6673
BW		 217 pde |= addr;
218 if (level != I915_CACHE_NONE)
219 pde |= PPAT_CACHED_PDE_INDEX;
220 else
221 pde |= PPAT_UNCACHED_INDEX;
222 return pde;
223}
224
762d9936
MT		 225#define gen8_pdpe_encode gen8_pde_encode
226#define gen8_pml4e_encode gen8_pde_encode
227
07749ef3
MT		 228static gen6_pte_t snb_pte_encode(dma_addr_t addr,
229 enum i915_cache_level level,
230 bool valid, u32 unused)
54d12527 231{
07749ef3 232 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
54d12527 233 pte |= GEN6_PTE_ADDR_ENCODE(addr);
e7210c3c
BW		 234
235 switch (level) {
350ec881
CW		 236 case I915_CACHE_L3_LLC:
237 case I915_CACHE_LLC:
238 pte |= GEN6_PTE_CACHE_LLC;
239 break;
240 case I915_CACHE_NONE:
241 pte |= GEN6_PTE_UNCACHED;
242 break;
243 default:
5f77eeb0 244 MISSING_CASE(level);
350ec881
CW		 245 }
246
247 return pte;
248}
249
07749ef3
MT		 250static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
251 enum i915_cache_level level,
252 bool valid, u32 unused)
350ec881 253{
07749ef3 254 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
350ec881
CW		 255 pte |= GEN6_PTE_ADDR_ENCODE(addr);
256
257 switch (level) {
258 case I915_CACHE_L3_LLC:
259 pte |= GEN7_PTE_CACHE_L3_LLC;
e7210c3c
BW		 260 break;
261 case I915_CACHE_LLC:
262 pte |= GEN6_PTE_CACHE_LLC;
263 break;
264 case I915_CACHE_NONE:
9119708c 265 pte |= GEN6_PTE_UNCACHED;
e7210c3c
BW		 266 break;
267 default:
5f77eeb0 268 MISSING_CASE(level);
e7210c3c
BW		 269 }
270
54d12527
BW		 271 return pte;
272}
273
07749ef3
MT		 274static gen6_pte_t byt_pte_encode(dma_addr_t addr,
275 enum i915_cache_level level,
276 bool valid, u32 flags)
93c34e70 277{
07749ef3 278 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
93c34e70
KG		 279 pte |= GEN6_PTE_ADDR_ENCODE(addr);
280
24f3a8cf
AG		 281 if (!(flags & PTE_READ_ONLY))
282 pte |= BYT_PTE_WRITEABLE;
93c34e70
KG		 283
284 if (level != I915_CACHE_NONE)
285 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
286
287 return pte;
288}
289
07749ef3
MT		 290static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
291 enum i915_cache_level level,
292 bool valid, u32 unused)
9119708c 293{
07749ef3 294 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
0d8ff15e 295 pte |= HSW_PTE_ADDR_ENCODE(addr);
9119708c
KG		 296
297 if (level != I915_CACHE_NONE)
87a6b688 298 pte |= HSW_WB_LLC_AGE3;
9119708c
KG		 299
300 return pte;
301}
302
07749ef3
MT		 303static gen6_pte_t iris_pte_encode(dma_addr_t addr,
304 enum i915_cache_level level,
305 bool valid, u32 unused)
4d15c145 306{
07749ef3 307 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
4d15c145
BW		 308 pte |= HSW_PTE_ADDR_ENCODE(addr);
309
651d794f
CW		 310 switch (level) {
311 case I915_CACHE_NONE:
312 break;
313 case I915_CACHE_WT:
c51e9701 314 pte |= HSW_WT_ELLC_LLC_AGE3;
651d794f
CW		 315 break;
316 default:
c51e9701 317 pte |= HSW_WB_ELLC_LLC_AGE3;
651d794f
CW		 318 break;
319 }
4d15c145
BW		 320
321 return pte;
322}
323
c114f76a
MK		 324static int __setup_page_dma(struct drm_device *dev,
325 struct i915_page_dma *p, gfp_t flags)
678d96fb
BW		 326{
327 struct device *device = &dev->pdev->dev;
328
c114f76a 329 p->page = alloc_page(flags);
44159ddb
MK		 330 if (!p->page)
331 return -ENOMEM;
678d96fb 332
44159ddb
MK		 333 p->daddr = dma_map_page(device,
334 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
678d96fb 335
44159ddb
MK		 336 if (dma_mapping_error(device, p->daddr)) {
337 __free_page(p->page);
338 return -EINVAL;
339 }
1266cdb1
MT		 340
341 return 0;
678d96fb
BW		 342}
343
c114f76a
MK		 344static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
345{
346 return __setup_page_dma(dev, p, GFP_KERNEL);
347}
348
44159ddb 349static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
06fda602 350{
44159ddb 351 if (WARN_ON(!p->page))
06fda602 352 return;
678d96fb 353
44159ddb
MK		 354 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
355 __free_page(p->page);
356 memset(p, 0, sizeof(*p));
357}
358
d1c54acd 359static void *kmap_page_dma(struct i915_page_dma *p)
73eeea53 360{
d1c54acd
MK		 361 return kmap_atomic(p->page);
362}
73eeea53 363
d1c54acd
MK		 364/* We use the flushing unmap only with ppgtt structures:
365 * page directories, page tables and scratch pages.
366 */
367static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
368{
73eeea53
MK		 369 /* There are only few exceptions for gen >=6. chv and bxt.
370 * And we are not sure about the latter so play safe for now.
371 */
372 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
373 drm_clflush_virt_range(vaddr, PAGE_SIZE);
374
375 kunmap_atomic(vaddr);
376}
377
567047be 378#define kmap_px(px) kmap_page_dma(px_base(px))
d1c54acd
MK		 379#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
380
567047be
MK		 381#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
382#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
383#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
384#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
385
d1c54acd
MK		 386static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
387 const uint64_t val)
388{
389 int i;
390 uint64_t * const vaddr = kmap_page_dma(p);
391
392 for (i = 0; i < 512; i++)
393 vaddr[i] = val;
394
395 kunmap_page_dma(dev, vaddr);
396}
397
73eeea53
MK		 398static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
399 const uint32_t val32)
400{
401 uint64_t v = val32;
402
403 v = v << 32 | val32;
404
405 fill_page_dma(dev, p, v);
406}
407
4ad2af1e
MK		 408static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
409{
410 struct i915_page_scratch *sp;
411 int ret;
412
413 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
414 if (sp == NULL)
415 return ERR_PTR(-ENOMEM);
416
417 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
418 if (ret) {
419 kfree(sp);
420 return ERR_PTR(ret);
421 }
422
423 set_pages_uc(px_page(sp), 1);
424
425 return sp;
426}
427
428static void free_scratch_page(struct drm_device *dev,
429 struct i915_page_scratch *sp)
430{
431 set_pages_wb(px_page(sp), 1);
432
433 cleanup_px(dev, sp);
434 kfree(sp);
435}
436
8a1ebd74 437static struct i915_page_table *alloc_pt(struct drm_device *dev)
06fda602 438{
ec565b3c 439 struct i915_page_table *pt;
678d96fb
BW		 440 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
441 GEN8_PTES : GEN6_PTES;
442 int ret = -ENOMEM;
06fda602
BW		 443
444 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
445 if (!pt)
446 return ERR_PTR(-ENOMEM);
447
678d96fb
BW		 448 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
449 GFP_KERNEL);
450
451 if (!pt->used_ptes)
452 goto fail_bitmap;
453
567047be 454 ret = setup_px(dev, pt);
678d96fb 455 if (ret)
44159ddb 456 goto fail_page_m;
06fda602
BW		 457
458 return pt;
678d96fb 459
44159ddb 460fail_page_m:
678d96fb
BW		 461 kfree(pt->used_ptes);
462fail_bitmap:
463 kfree(pt);
464
465 return ERR_PTR(ret);
06fda602
BW		 466}
467
2e906bea 468static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
06fda602 469{
2e906bea
MK		 470 cleanup_px(dev, pt);
471 kfree(pt->used_ptes);
472 kfree(pt);
473}
474
475static void gen8_initialize_pt(struct i915_address_space *vm,
476 struct i915_page_table *pt)
477{
478 gen8_pte_t scratch_pte;
479
480 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
481 I915_CACHE_LLC, true);
482
483 fill_px(vm->dev, pt, scratch_pte);
484}
485
486static void gen6_initialize_pt(struct i915_address_space *vm,
487 struct i915_page_table *pt)
488{
489 gen6_pte_t scratch_pte;
490
491 WARN_ON(px_dma(vm->scratch_page) == 0);
492
493 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
494 I915_CACHE_LLC, true, 0);
495
496 fill32_px(vm->dev, pt, scratch_pte);
06fda602
BW		 497}
498
8a1ebd74 499static struct i915_page_directory *alloc_pd(struct drm_device *dev)
06fda602 500{
ec565b3c 501 struct i915_page_directory *pd;
33c8819f 502 int ret = -ENOMEM;
06fda602
BW		 503
504 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
505 if (!pd)
506 return ERR_PTR(-ENOMEM);
507
33c8819f
MT		 508 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
509 sizeof(*pd->used_pdes), GFP_KERNEL);
510 if (!pd->used_pdes)
a08e111a 511 goto fail_bitmap;
33c8819f 512
567047be 513 ret = setup_px(dev, pd);
33c8819f 514 if (ret)
a08e111a 515 goto fail_page_m;
e5815a2e 516
06fda602 517 return pd;
33c8819f 518
a08e111a 519fail_page_m:
33c8819f 520 kfree(pd->used_pdes);
a08e111a 521fail_bitmap:
33c8819f
MT		 522 kfree(pd);
523
524 return ERR_PTR(ret);
06fda602
BW		 525}
526
2e906bea
MK		 527static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
528{
529 if (px_page(pd)) {
530 cleanup_px(dev, pd);
531 kfree(pd->used_pdes);
532 kfree(pd);
533 }
534}
535
536static void gen8_initialize_pd(struct i915_address_space *vm,
537 struct i915_page_directory *pd)
538{
539 gen8_pde_t scratch_pde;
540
541 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
542
543 fill_px(vm->dev, pd, scratch_pde);
544}
545
6ac18502
MT		 546static int __pdp_init(struct drm_device *dev,
547 struct i915_page_directory_pointer *pdp)
548{
549 size_t pdpes = I915_PDPES_PER_PDP(dev);
550
551 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
552 sizeof(unsigned long),
553 GFP_KERNEL);
554 if (!pdp->used_pdpes)
555 return -ENOMEM;
556
557 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
558 GFP_KERNEL);
559 if (!pdp->page_directory) {
560 kfree(pdp->used_pdpes);
561 /* the PDP might be the statically allocated top level. Keep it
562 * as clean as possible */
563 pdp->used_pdpes = NULL;
564 return -ENOMEM;
565 }
566
567 return 0;
568}
569
570static void __pdp_fini(struct i915_page_directory_pointer *pdp)
571{
572 kfree(pdp->used_pdpes);
573 kfree(pdp->page_directory);
574 pdp->page_directory = NULL;
575}
576
762d9936
MT		 577static struct
578i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
579{
580 struct i915_page_directory_pointer *pdp;
581 int ret = -ENOMEM;
582
583 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
584
585 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
586 if (!pdp)
587 return ERR_PTR(-ENOMEM);
588
589 ret = __pdp_init(dev, pdp);
590 if (ret)
591 goto fail_bitmap;
592
593 ret = setup_px(dev, pdp);
594 if (ret)
595 goto fail_page_m;
596
597 return pdp;
598
599fail_page_m:
600 __pdp_fini(pdp);
601fail_bitmap:
602 kfree(pdp);
603
604 return ERR_PTR(ret);
605}
606
6ac18502
MT		 607static void free_pdp(struct drm_device *dev,
608 struct i915_page_directory_pointer *pdp)
609{
610 __pdp_fini(pdp);
762d9936
MT		 611 if (USES_FULL_48BIT_PPGTT(dev)) {
612 cleanup_px(dev, pdp);
613 kfree(pdp);
614 }
615}
616
69ab76fd
MT		 617static void gen8_initialize_pdp(struct i915_address_space *vm,
618 struct i915_page_directory_pointer *pdp)
619{
620 gen8_ppgtt_pdpe_t scratch_pdpe;
621
622 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
623
624 fill_px(vm->dev, pdp, scratch_pdpe);
625}
626
627static void gen8_initialize_pml4(struct i915_address_space *vm,
628 struct i915_pml4 *pml4)
629{
630 gen8_ppgtt_pml4e_t scratch_pml4e;
631
632 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
633 I915_CACHE_LLC);
634
635 fill_px(vm->dev, pml4, scratch_pml4e);
636}
637
762d9936
MT		 638static void
639gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
640 struct i915_page_directory_pointer *pdp,
641 struct i915_page_directory *pd,
642 int index)
643{
644 gen8_ppgtt_pdpe_t *page_directorypo;
645
646 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
647 return;
648
649 page_directorypo = kmap_px(pdp);
650 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
651 kunmap_px(ppgtt, page_directorypo);
652}
653
654static void
655gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
656 struct i915_pml4 *pml4,
657 struct i915_page_directory_pointer *pdp,
658 int index)
659{
660 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
661
662 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
663 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
664 kunmap_px(ppgtt, pagemap);
6ac18502
MT		 665}
666
94e409c1 667/* Broadwell Page Directory Pointer Descriptors */
e85b26dc 668static int gen8_write_pdp(struct drm_i915_gem_request *req,
7cb6d7ac
MT		 669 unsigned entry,
670 dma_addr_t addr)
94e409c1 671{
4a570db5 672 struct intel_engine_cs *engine = req->engine;
94e409c1
BW		 673 int ret;
674
675 BUG_ON(entry >= 4);
676
5fb9de1a 677 ret = intel_ring_begin(req, 6);
94e409c1
BW		 678 if (ret)
679 return ret;
680
e2f80391
TU		 681 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
682 intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
683 intel_ring_emit(engine, upper_32_bits(addr));
684 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
685 intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
686 intel_ring_emit(engine, lower_32_bits(addr));
687 intel_ring_advance(engine);
94e409c1
BW		 688
689 return 0;
690}
691
2dba3239
MT		 692static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
693 struct drm_i915_gem_request *req)
94e409c1 694{
eeb9488e 695 int i, ret;
94e409c1 696
7cb6d7ac 697 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
d852c7bf
MK		 698 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
699
e85b26dc 700 ret = gen8_write_pdp(req, i, pd_daddr);
eeb9488e
BW		 701 if (ret)
702 return ret;
94e409c1 703 }
d595bd4b 704
eeb9488e 705 return 0;
94e409c1
BW		 706}
707
2dba3239
MT		 708static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
709 struct drm_i915_gem_request *req)
710{
711 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
712}
713
f9b5b782
MT		 714static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
715 struct i915_page_directory_pointer *pdp,
716 uint64_t start,
717 uint64_t length,
718 gen8_pte_t scratch_pte)
459108b8 719{
e5716f55 720 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782 721 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 722 unsigned pdpe = gen8_pdpe_index(start);
723 unsigned pde = gen8_pde_index(start);
724 unsigned pte = gen8_pte_index(start);
782f1495 725 unsigned num_entries = length >> PAGE_SHIFT;
459108b8
BW		 726 unsigned last_pte, i;
727
f9b5b782
MT		 728 if (WARN_ON(!pdp))
729 return;
459108b8
BW		 730
731 while (num_entries) {
ec565b3c
MT		 732 struct i915_page_directory *pd;
733 struct i915_page_table *pt;
06fda602 734
d4ec9da0 735 if (WARN_ON(!pdp->page_directory[pdpe]))
00245266 736 break;
06fda602 737
d4ec9da0 738 pd = pdp->page_directory[pdpe];
06fda602
BW		 739
740 if (WARN_ON(!pd->page_table[pde]))
00245266 741 break;
06fda602
BW		 742
743 pt = pd->page_table[pde];
744
567047be 745 if (WARN_ON(!px_page(pt)))
00245266 746 break;
06fda602 747
7ad47cf2 748 last_pte = pte + num_entries;
07749ef3
MT		 749 if (last_pte > GEN8_PTES)
750 last_pte = GEN8_PTES;
459108b8 751
d1c54acd 752 pt_vaddr = kmap_px(pt);
459108b8 753
7ad47cf2 754 for (i = pte; i < last_pte; i++) {
459108b8 755 pt_vaddr[i] = scratch_pte;
7ad47cf2
BW		 756 num_entries--;
757 }
459108b8 758
44a71024 759 kunmap_px(ppgtt, pt_vaddr);
459108b8 760
7ad47cf2 761 pte = 0;
07749ef3 762 if (++pde == I915_PDES) {
de5ba8eb
MT		 763 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
764 break;
7ad47cf2
BW		 765 pde = 0;
766 }
459108b8
BW		 767 }
768}
769
f9b5b782
MT		 770static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
771 uint64_t start,
772 uint64_t length,
773 bool use_scratch)
9df15b49 774{
e5716f55 775 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
f9b5b782
MT		 776 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
777 I915_CACHE_LLC, use_scratch);
778
de5ba8eb
MT		 779 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
780 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
781 scratch_pte);
782 } else {
e8ebd8e2 783 uint64_t pml4e;
de5ba8eb
MT		 784 struct i915_page_directory_pointer *pdp;
785
e8ebd8e2 786 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 787 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
788 scratch_pte);
789 }
790 }
f9b5b782
MT		 791}
792
793static void
794gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
795 struct i915_page_directory_pointer *pdp,
3387d433 796 struct sg_page_iter *sg_iter,
f9b5b782
MT		 797 uint64_t start,
798 enum i915_cache_level cache_level)
799{
e5716f55 800 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 801 gen8_pte_t *pt_vaddr;
de5ba8eb
MT		 802 unsigned pdpe = gen8_pdpe_index(start);
803 unsigned pde = gen8_pde_index(start);
804 unsigned pte = gen8_pte_index(start);
9df15b49 805
6f1cc993 806 pt_vaddr = NULL;
7ad47cf2 807
3387d433 808 while (__sg_page_iter_next(sg_iter)) {
d7b3de91 809 if (pt_vaddr == NULL) {
d4ec9da0 810 struct i915_page_directory *pd = pdp->page_directory[pdpe];
ec565b3c 811 struct i915_page_table *pt = pd->page_table[pde];
d1c54acd 812 pt_vaddr = kmap_px(pt);
d7b3de91 813 }
9df15b49 814
7ad47cf2 815 pt_vaddr[pte] =
3387d433 816 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
6f1cc993 817 cache_level, true);
07749ef3 818 if (++pte == GEN8_PTES) {
d1c54acd 819 kunmap_px(ppgtt, pt_vaddr);
6f1cc993 820 pt_vaddr = NULL;
07749ef3 821 if (++pde == I915_PDES) {
de5ba8eb
MT		 822 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
823 break;
7ad47cf2
BW		 824 pde = 0;
825 }
826 pte = 0;
9df15b49
BW		 827 }
828 }
d1c54acd
MK		 829
830 if (pt_vaddr)
831 kunmap_px(ppgtt, pt_vaddr);
9df15b49
BW		 832}
833
f9b5b782
MT		 834static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
835 struct sg_table *pages,
836 uint64_t start,
837 enum i915_cache_level cache_level,
838 u32 unused)
839{
e5716f55 840 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3387d433 841 struct sg_page_iter sg_iter;
f9b5b782 842
3387d433 843 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
de5ba8eb
MT		 844
845 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
846 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
847 cache_level);
848 } else {
849 struct i915_page_directory_pointer *pdp;
e8ebd8e2 850 uint64_t pml4e;
de5ba8eb
MT		 851 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
852
e8ebd8e2 853 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
de5ba8eb
MT		 854 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
855 start, cache_level);
856 }
857 }
f9b5b782
MT		 858}
859
f37c0505
MT		 860static void gen8_free_page_tables(struct drm_device *dev,
861 struct i915_page_directory *pd)
7ad47cf2
BW		 862{
863 int i;
864
567047be 865 if (!px_page(pd))
7ad47cf2
BW		 866 return;
867
33c8819f 868 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
06fda602
BW		 869 if (WARN_ON(!pd->page_table[i]))
870 continue;
7ad47cf2 871
a08e111a 872 free_pt(dev, pd->page_table[i]);
06fda602
BW		 873 pd->page_table[i] = NULL;
874 }
d7b3de91
BW		 875}
876
8776f02b
MK		 877static int gen8_init_scratch(struct i915_address_space *vm)
878{
879 struct drm_device *dev = vm->dev;
64c050db 880 int ret;
8776f02b
MK		 881
882 vm->scratch_page = alloc_scratch_page(dev);
883 if (IS_ERR(vm->scratch_page))
884 return PTR_ERR(vm->scratch_page);
885
886 vm->scratch_pt = alloc_pt(dev);
887 if (IS_ERR(vm->scratch_pt)) {
64c050db
MA		 888 ret = PTR_ERR(vm->scratch_pt);
889 goto free_scratch_page;
8776f02b
MK		 890 }
891
892 vm->scratch_pd = alloc_pd(dev);
893 if (IS_ERR(vm->scratch_pd)) {
64c050db
MA		 894 ret = PTR_ERR(vm->scratch_pd);
895 goto free_pt;
8776f02b
MK		 896 }
897
69ab76fd
MT		 898 if (USES_FULL_48BIT_PPGTT(dev)) {
899 vm->scratch_pdp = alloc_pdp(dev);
900 if (IS_ERR(vm->scratch_pdp)) {
64c050db
MA		 901 ret = PTR_ERR(vm->scratch_pdp);
902 goto free_pd;
69ab76fd
MT		 903 }
904 }
905
8776f02b
MK		 906 gen8_initialize_pt(vm, vm->scratch_pt);
907 gen8_initialize_pd(vm, vm->scratch_pd);
69ab76fd
MT		 908 if (USES_FULL_48BIT_PPGTT(dev))
909 gen8_initialize_pdp(vm, vm->scratch_pdp);
8776f02b
MK		 910
911 return 0;
64c050db
MA		 912
913free_pd:
914 free_pd(dev, vm->scratch_pd);
915free_pt:
916 free_pt(dev, vm->scratch_pt);
917free_scratch_page:
918 free_scratch_page(dev, vm->scratch_page);
919
920 return ret;
8776f02b
MK		 921}
922
650da34c
ZL		 923static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
924{
925 enum vgt_g2v_type msg;
df28564d 926 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
650da34c
ZL		 927 int i;
928
df28564d 929 if (USES_FULL_48BIT_PPGTT(dev_priv)) {
650da34c
ZL		 930 u64 daddr = px_dma(&ppgtt->pml4);
931
ab75bb5d
VS		 932 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
933 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
650da34c
ZL		 934
935 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
936 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
937 } else {
938 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
939 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
940
ab75bb5d
VS		 941 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
942 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
650da34c
ZL		 943 }
944
945 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
946 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
947 }
948
949 I915_WRITE(vgtif_reg(g2v_notify), msg);
950
951 return 0;
952}
953
8776f02b
MK		 954static void gen8_free_scratch(struct i915_address_space *vm)
955{
956 struct drm_device *dev = vm->dev;
957
69ab76fd
MT		 958 if (USES_FULL_48BIT_PPGTT(dev))
959 free_pdp(dev, vm->scratch_pdp);
8776f02b
MK		 960 free_pd(dev, vm->scratch_pd);
961 free_pt(dev, vm->scratch_pt);
962 free_scratch_page(dev, vm->scratch_page);
963}
964
762d9936
MT		 965static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
966 struct i915_page_directory_pointer *pdp)
b45a6715
BW		 967{
968 int i;
969
d4ec9da0
MT		 970 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
971 if (WARN_ON(!pdp->page_directory[i]))
06fda602
BW		 972 continue;
973
d4ec9da0
MT		 974 gen8_free_page_tables(dev, pdp->page_directory[i]);
975 free_pd(dev, pdp->page_directory[i]);
7ad47cf2 976 }
69876bed 977
d4ec9da0 978 free_pdp(dev, pdp);
762d9936
MT		 979}
980
981static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
982{
983 int i;
984
985 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
986 if (WARN_ON(!ppgtt->pml4.pdps[i]))
987 continue;
988
989 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
990 }
991
992 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
993}
994
995static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
996{
e5716f55 997 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 998
c033666a 999 if (intel_vgpu_active(to_i915(vm->dev)))
650da34c
ZL		 1000 gen8_ppgtt_notify_vgt(ppgtt, false);
1001
762d9936
MT		 1002 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
1003 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
1004 else
1005 gen8_ppgtt_cleanup_4lvl(ppgtt);
d4ec9da0 1006
8776f02b 1007 gen8_free_scratch(vm);
b45a6715
BW		 1008}
1009
d7b2633d
MT		 1010/**
1011 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
d4ec9da0
MT		 1012 * @vm: Master vm structure.
1013 * @pd: Page directory for this address range.
d7b2633d 1014 * @start: Starting virtual address to begin allocations.
d4ec9da0 1015 * @length: Size of the allocations.
d7b2633d
MT		 1016 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1017 * caller to free on error.
1018 *
1019 * Allocate the required number of page tables. Extremely similar to
1020 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1021 * the page directory boundary (instead of the page directory pointer). That
1022 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1023 * possible, and likely that the caller will need to use multiple calls of this
1024 * function to achieve the appropriate allocation.
1025 *
1026 * Return: 0 if success; negative error code otherwise.
1027 */
d4ec9da0 1028static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
e5815a2e 1029 struct i915_page_directory *pd,
5441f0cb 1030 uint64_t start,
d7b2633d
MT		 1031 uint64_t length,
1032 unsigned long *new_pts)
bf2b4ed2 1033{
d4ec9da0 1034 struct drm_device *dev = vm->dev;
d7b2633d 1035 struct i915_page_table *pt;
5441f0cb 1036 uint32_t pde;
bf2b4ed2 1037
e8ebd8e2 1038 gen8_for_each_pde(pt, pd, start, length, pde) {
d7b2633d 1039 /* Don't reallocate page tables */
6ac18502 1040 if (test_bit(pde, pd->used_pdes)) {
d7b2633d 1041 /* Scratch is never allocated this way */
d4ec9da0 1042 WARN_ON(pt == vm->scratch_pt);
d7b2633d
MT		 1043 continue;
1044 }
1045
8a1ebd74 1046 pt = alloc_pt(dev);
d7b2633d 1047 if (IS_ERR(pt))
5441f0cb
MT		 1048 goto unwind_out;
1049
d4ec9da0 1050 gen8_initialize_pt(vm, pt);
d7b2633d 1051 pd->page_table[pde] = pt;
966082c9 1052 __set_bit(pde, new_pts);
4c06ec8d 1053 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
7ad47cf2
BW		 1054 }
1055
bf2b4ed2 1056 return 0;
7ad47cf2
BW		 1057
1058unwind_out:
d7b2633d 1059 for_each_set_bit(pde, new_pts, I915_PDES)
a08e111a 1060 free_pt(dev, pd->page_table[pde]);
7ad47cf2 1061
d7b3de91 1062 return -ENOMEM;
bf2b4ed2
BW		 1063}
1064
d7b2633d
MT		 1065/**
1066 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
d4ec9da0 1067 * @vm: Master vm structure.
d7b2633d
MT		 1068 * @pdp: Page directory pointer for this address range.
1069 * @start: Starting virtual address to begin allocations.
d4ec9da0
MT		 1070 * @length: Size of the allocations.
1071 * @new_pds: Bitmap set by function with new allocations. Likely used by the
d7b2633d
MT		 1072 * caller to free on error.
1073 *
1074 * Allocate the required number of page directories starting at the pde index of
1075 * @start, and ending at the pde index @start + @length. This function will skip
1076 * over already allocated page directories within the range, and only allocate
1077 * new ones, setting the appropriate pointer within the pdp as well as the
1078 * correct position in the bitmap @new_pds.
1079 *
1080 * The function will only allocate the pages within the range for a give page
1081 * directory pointer. In other words, if @start + @length straddles a virtually
1082 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1083 * required by the caller, This is not currently possible, and the BUG in the
1084 * code will prevent it.
1085 *
1086 * Return: 0 if success; negative error code otherwise.
1087 */
d4ec9da0
MT		 1088static int
1089gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1090 struct i915_page_directory_pointer *pdp,
1091 uint64_t start,
1092 uint64_t length,
1093 unsigned long *new_pds)
bf2b4ed2 1094{
d4ec9da0 1095 struct drm_device *dev = vm->dev;
d7b2633d 1096 struct i915_page_directory *pd;
69876bed 1097 uint32_t pdpe;
6ac18502 1098 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
69876bed 1099
6ac18502 1100 WARN_ON(!bitmap_empty(new_pds, pdpes));
d7b2633d 1101
e8ebd8e2 1102 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
6ac18502 1103 if (test_bit(pdpe, pdp->used_pdpes))
d7b2633d 1104 continue;
33c8819f 1105
8a1ebd74 1106 pd = alloc_pd(dev);
d7b2633d 1107 if (IS_ERR(pd))
d7b3de91 1108 goto unwind_out;
69876bed 1109
d4ec9da0 1110 gen8_initialize_pd(vm, pd);
d7b2633d 1111 pdp->page_directory[pdpe] = pd;
966082c9 1112 __set_bit(pdpe, new_pds);
4c06ec8d 1113 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
d7b3de91
BW		 1114 }
1115
bf2b4ed2 1116 return 0;
d7b3de91
BW		 1117
1118unwind_out:
6ac18502 1119 for_each_set_bit(pdpe, new_pds, pdpes)
a08e111a 1120 free_pd(dev, pdp->page_directory[pdpe]);
d7b3de91
BW		 1121
1122 return -ENOMEM;
bf2b4ed2
BW		 1123}
1124
762d9936
MT		 1125/**
1126 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1127 * @vm: Master vm structure.
1128 * @pml4: Page map level 4 for this address range.
1129 * @start: Starting virtual address to begin allocations.
1130 * @length: Size of the allocations.
1131 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1132 * caller to free on error.
1133 *
1134 * Allocate the required number of page directory pointers. Extremely similar to
1135 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1136 * The main difference is here we are limited by the pml4 boundary (instead of
1137 * the page directory pointer).
1138 *
1139 * Return: 0 if success; negative error code otherwise.
1140 */
1141static int
1142gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1143 struct i915_pml4 *pml4,
1144 uint64_t start,
1145 uint64_t length,
1146 unsigned long *new_pdps)
1147{
1148 struct drm_device *dev = vm->dev;
1149 struct i915_page_directory_pointer *pdp;
762d9936
MT		 1150 uint32_t pml4e;
1151
1152 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1153
e8ebd8e2 1154 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1155 if (!test_bit(pml4e, pml4->used_pml4es)) {
1156 pdp = alloc_pdp(dev);
1157 if (IS_ERR(pdp))
1158 goto unwind_out;
1159
69ab76fd 1160 gen8_initialize_pdp(vm, pdp);
762d9936
MT		 1161 pml4->pdps[pml4e] = pdp;
1162 __set_bit(pml4e, new_pdps);
1163 trace_i915_page_directory_pointer_entry_alloc(vm,
1164 pml4e,
1165 start,
1166 GEN8_PML4E_SHIFT);
1167 }
1168 }
1169
1170 return 0;
1171
1172unwind_out:
1173 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1174 free_pdp(dev, pml4->pdps[pml4e]);
1175
1176 return -ENOMEM;
1177}
1178
d7b2633d 1179static void
3a41a05d 1180free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
d7b2633d 1181{
d7b2633d
MT		 1182 kfree(new_pts);
1183 kfree(new_pds);
1184}
1185
1186/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1187 * of these are based on the number of PDPEs in the system.
1188 */
1189static
1190int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
3a41a05d 1191 unsigned long **new_pts,
6ac18502 1192 uint32_t pdpes)
d7b2633d 1193{
d7b2633d 1194 unsigned long *pds;
3a41a05d 1195 unsigned long *pts;
d7b2633d 1196
3a41a05d 1197 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
d7b2633d
MT		 1198 if (!pds)
1199 return -ENOMEM;
1200
3a41a05d
MW		 1201 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1202 GFP_TEMPORARY);
1203 if (!pts)
1204 goto err_out;
d7b2633d
MT		 1205
1206 *new_pds = pds;
1207 *new_pts = pts;
1208
1209 return 0;
1210
1211err_out:
3a41a05d 1212 free_gen8_temp_bitmaps(pds, pts);
d7b2633d
MT		 1213 return -ENOMEM;
1214}
1215
5b7e4c9c
MK		 1216/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1217 * the page table structures, we mark them dirty so that
1218 * context switching/execlist queuing code takes extra steps
1219 * to ensure that tlbs are flushed.
1220 */
1221static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1222{
1223 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1224}
1225
762d9936
MT		 1226static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1227 struct i915_page_directory_pointer *pdp,
1228 uint64_t start,
1229 uint64_t length)
bf2b4ed2 1230{
e5716f55 1231 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
3a41a05d 1232 unsigned long *new_page_dirs, *new_page_tables;
d4ec9da0 1233 struct drm_device *dev = vm->dev;
5441f0cb 1234 struct i915_page_directory *pd;
33c8819f
MT		 1235 const uint64_t orig_start = start;
1236 const uint64_t orig_length = length;
5441f0cb 1237 uint32_t pdpe;
d4ec9da0 1238 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
bf2b4ed2
BW		 1239 int ret;
1240
d7b2633d
MT		 1241 /* Wrap is never okay since we can only represent 48b, and we don't
1242 * actually use the other side of the canonical address space.
1243 */
1244 if (WARN_ON(start + length < start))
a05d80ee
MK		 1245 return -ENODEV;
1246
d4ec9da0 1247 if (WARN_ON(start + length > vm->total))
a05d80ee 1248 return -ENODEV;
d7b2633d 1249
6ac18502 1250 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
bf2b4ed2
BW		 1251 if (ret)
1252 return ret;
1253
d7b2633d 1254 /* Do the allocations first so we can easily bail out */
d4ec9da0
MT		 1255 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1256 new_page_dirs);
d7b2633d 1257 if (ret) {
3a41a05d 1258 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
d7b2633d
MT		 1259 return ret;
1260 }
1261
1262 /* For every page directory referenced, allocate page tables */
e8ebd8e2 1263 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d4ec9da0 1264 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
3a41a05d 1265 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
5441f0cb
MT		 1266 if (ret)
1267 goto err_out;
5441f0cb
MT		 1268 }
1269
33c8819f
MT		 1270 start = orig_start;
1271 length = orig_length;
1272
d7b2633d
MT		 1273 /* Allocations have completed successfully, so set the bitmaps, and do
1274 * the mappings. */
e8ebd8e2 1275 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
d1c54acd 1276 gen8_pde_t *const page_directory = kmap_px(pd);
33c8819f 1277 struct i915_page_table *pt;
09120d4e 1278 uint64_t pd_len = length;
33c8819f
MT		 1279 uint64_t pd_start = start;
1280 uint32_t pde;
1281
d7b2633d
MT		 1282 /* Every pd should be allocated, we just did that above. */
1283 WARN_ON(!pd);
1284
e8ebd8e2 1285 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
d7b2633d
MT		 1286 /* Same reasoning as pd */
1287 WARN_ON(!pt);
1288 WARN_ON(!pd_len);
1289 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1290
1291 /* Set our used ptes within the page table */
1292 bitmap_set(pt->used_ptes,
1293 gen8_pte_index(pd_start),
1294 gen8_pte_count(pd_start, pd_len));
1295
1296 /* Our pde is now pointing to the pagetable, pt */
966082c9 1297 __set_bit(pde, pd->used_pdes);
d7b2633d
MT		 1298
1299 /* Map the PDE to the page table */
fe36f55d
MK		 1300 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1301 I915_CACHE_LLC);
4c06ec8d
MT		 1302 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1303 gen8_pte_index(start),
1304 gen8_pte_count(start, length),
1305 GEN8_PTES);
d7b2633d
MT		 1306
1307 /* NB: We haven't yet mapped ptes to pages. At this
1308 * point we're still relying on insert_entries() */
33c8819f 1309 }
d7b2633d 1310
d1c54acd 1311 kunmap_px(ppgtt, page_directory);
d4ec9da0 1312 __set_bit(pdpe, pdp->used_pdpes);
762d9936 1313 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
33c8819f
MT		 1314 }
1315
3a41a05d 1316 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1317 mark_tlbs_dirty(ppgtt);
d7b3de91 1318 return 0;
bf2b4ed2 1319
d7b3de91 1320err_out:
d7b2633d 1321 while (pdpe--) {
e8ebd8e2
DG		 1322 unsigned long temp;
1323
3a41a05d
MW		 1324 for_each_set_bit(temp, new_page_tables + pdpe *
1325 BITS_TO_LONGS(I915_PDES), I915_PDES)
d4ec9da0 1326 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
d7b2633d
MT		 1327 }
1328
6ac18502 1329 for_each_set_bit(pdpe, new_page_dirs, pdpes)
d4ec9da0 1330 free_pd(dev, pdp->page_directory[pdpe]);
d7b2633d 1331
3a41a05d 1332 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
5b7e4c9c 1333 mark_tlbs_dirty(ppgtt);
bf2b4ed2
BW		 1334 return ret;
1335}
1336
762d9936
MT		 1337static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1338 struct i915_pml4 *pml4,
1339 uint64_t start,
1340 uint64_t length)
1341{
1342 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
e5716f55 1343 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936 1344 struct i915_page_directory_pointer *pdp;
e8ebd8e2 1345 uint64_t pml4e;
762d9936
MT		 1346 int ret = 0;
1347
1348 /* Do the pml4 allocations first, so we don't need to track the newly
1349 * allocated tables below the pdp */
1350 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1351
1352 /* The pagedirectory and pagetable allocations are done in the shared 3
1353 * and 4 level code. Just allocate the pdps.
1354 */
1355 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1356 new_pdps);
1357 if (ret)
1358 return ret;
1359
1360 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1361 "The allocation has spanned more than 512GB. "
1362 "It is highly likely this is incorrect.");
1363
e8ebd8e2 1364 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
762d9936
MT		 1365 WARN_ON(!pdp);
1366
1367 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1368 if (ret)
1369 goto err_out;
1370
1371 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1372 }
1373
1374 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1375 GEN8_PML4ES_PER_PML4);
1376
1377 return 0;
1378
1379err_out:
1380 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1381 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1382
1383 return ret;
1384}
1385
1386static int gen8_alloc_va_range(struct i915_address_space *vm,
1387 uint64_t start, uint64_t length)
1388{
e5716f55 1389 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
762d9936
MT		 1390
1391 if (USES_FULL_48BIT_PPGTT(vm->dev))
1392 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1393 else
1394 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1395}
1396
ea91e401
MT		 1397static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1398 uint64_t start, uint64_t length,
1399 gen8_pte_t scratch_pte,
1400 struct seq_file *m)
1401{
1402 struct i915_page_directory *pd;
ea91e401
MT		 1403 uint32_t pdpe;
1404
e8ebd8e2 1405 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
ea91e401
MT		 1406 struct i915_page_table *pt;
1407 uint64_t pd_len = length;
1408 uint64_t pd_start = start;
1409 uint32_t pde;
1410
1411 if (!test_bit(pdpe, pdp->used_pdpes))
1412 continue;
1413
1414 seq_printf(m, "\tPDPE #%d\n", pdpe);
e8ebd8e2 1415 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
ea91e401
MT		 1416 uint32_t pte;
1417 gen8_pte_t *pt_vaddr;
1418
1419 if (!test_bit(pde, pd->used_pdes))
1420 continue;
1421
1422 pt_vaddr = kmap_px(pt);
1423 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1424 uint64_t va =
1425 (pdpe << GEN8_PDPE_SHIFT) |
1426 (pde << GEN8_PDE_SHIFT) |
1427 (pte << GEN8_PTE_SHIFT);
1428 int i;
1429 bool found = false;
1430
1431 for (i = 0; i < 4; i++)
1432 if (pt_vaddr[pte + i] != scratch_pte)
1433 found = true;
1434 if (!found)
1435 continue;
1436
1437 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1438 for (i = 0; i < 4; i++) {
1439 if (pt_vaddr[pte + i] != scratch_pte)
1440 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1441 else
1442 seq_puts(m, " SCRATCH ");
1443 }
1444 seq_puts(m, "\n");
1445 }
1446 /* don't use kunmap_px, it could trigger
1447 * an unnecessary flush.
1448 */
1449 kunmap_atomic(pt_vaddr);
1450 }
1451 }
1452}
1453
1454static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1455{
1456 struct i915_address_space *vm = &ppgtt->base;
1457 uint64_t start = ppgtt->base.start;
1458 uint64_t length = ppgtt->base.total;
1459 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1460 I915_CACHE_LLC, true);
1461
1462 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1463 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1464 } else {
e8ebd8e2 1465 uint64_t pml4e;
ea91e401
MT		 1466 struct i915_pml4 *pml4 = &ppgtt->pml4;
1467 struct i915_page_directory_pointer *pdp;
1468
e8ebd8e2 1469 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
ea91e401
MT		 1470 if (!test_bit(pml4e, pml4->used_pml4es))
1471 continue;
1472
1473 seq_printf(m, " PML4E #%llu\n", pml4e);
1474 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1475 }
1476 }
1477}
1478
331f38e7
ZL		 1479static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1480{
3a41a05d 1481 unsigned long *new_page_dirs, *new_page_tables;
331f38e7
ZL		 1482 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1483 int ret;
1484
1485 /* We allocate temp bitmap for page tables for no gain
1486 * but as this is for init only, lets keep the things simple
1487 */
1488 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1489 if (ret)
1490 return ret;
1491
1492 /* Allocate for all pdps regardless of how the ppgtt
1493 * was defined.
1494 */
1495 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1496 0, 1ULL << 32,
1497 new_page_dirs);
1498 if (!ret)
1499 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1500
3a41a05d 1501 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
331f38e7
ZL		 1502
1503 return ret;
1504}
1505
eb0b44ad 1506/*
f3a964b9
BW		 1507 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1508 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1509 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1510 * space.
37aca44a 1511 *
f3a964b9 1512 */
5c5f6457 1513static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
37aca44a 1514{
8776f02b 1515 int ret;
7cb6d7ac 1516
8776f02b
MK		 1517 ret = gen8_init_scratch(&ppgtt->base);
1518 if (ret)
1519 return ret;
69876bed 1520
d7b2633d 1521 ppgtt->base.start = 0;
d7b2633d 1522 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
5c5f6457 1523 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
d7b2633d 1524 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
c7e16f22 1525 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
777dc5bb
DV		 1526 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1527 ppgtt->base.bind_vma = ppgtt_bind_vma;
ea91e401 1528 ppgtt->debug_dump = gen8_dump_ppgtt;
d7b2633d 1529
762d9936
MT		 1530 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1531 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1532 if (ret)
1533 goto free_scratch;
6ac18502 1534
69ab76fd
MT		 1535 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1536
762d9936 1537 ppgtt->base.total = 1ULL << 48;
2dba3239 1538 ppgtt->switch_mm = gen8_48b_mm_switch;
762d9936 1539 } else {
25f50337 1540 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
81ba8aef
MT		 1541 if (ret)
1542 goto free_scratch;
1543
1544 ppgtt->base.total = 1ULL << 32;
2dba3239 1545 ppgtt->switch_mm = gen8_legacy_mm_switch;
762d9936
MT		 1546 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1547 0, 0,
1548 GEN8_PML4E_SHIFT);
331f38e7 1549
c033666a 1550 if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
331f38e7
ZL		 1551 ret = gen8_preallocate_top_level_pdps(ppgtt);
1552 if (ret)
1553 goto free_scratch;
1554 }
81ba8aef 1555 }
6ac18502 1556
c033666a 1557 if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
650da34c
ZL		 1558 gen8_ppgtt_notify_vgt(ppgtt, true);
1559
d7b2633d 1560 return 0;
6ac18502
MT		 1561
1562free_scratch:
1563 gen8_free_scratch(&ppgtt->base);
1564 return ret;
d7b2633d
MT		 1565}
1566
87d60b63
BW		 1567static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1568{
87d60b63 1569 struct i915_address_space *vm = &ppgtt->base;
09942c65 1570 struct i915_page_table *unused;
07749ef3 1571 gen6_pte_t scratch_pte;
87d60b63 1572 uint32_t pd_entry;
731f74c5 1573 uint32_t pte, pde;
09942c65 1574 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
87d60b63 1575
79ab9370
MK		 1576 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1577 I915_CACHE_LLC, true, 0);
87d60b63 1578
731f74c5 1579 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
87d60b63 1580 u32 expected;
07749ef3 1581 gen6_pte_t *pt_vaddr;
567047be 1582 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
09942c65 1583 pd_entry = readl(ppgtt->pd_addr + pde);
87d60b63
BW		 1584 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1585
1586 if (pd_entry != expected)
1587 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1588 pde,
1589 pd_entry,
1590 expected);
1591 seq_printf(m, "\tPDE: %x\n", pd_entry);
1592
d1c54acd
MK		 1593 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1594
07749ef3 1595 for (pte = 0; pte < GEN6_PTES; pte+=4) {
87d60b63 1596 unsigned long va =
07749ef3 1597 (pde * PAGE_SIZE * GEN6_PTES) +
87d60b63
BW		 1598 (pte * PAGE_SIZE);
1599 int i;
1600 bool found = false;
1601 for (i = 0; i < 4; i++)
1602 if (pt_vaddr[pte + i] != scratch_pte)
1603 found = true;
1604 if (!found)
1605 continue;
1606
1607 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1608 for (i = 0; i < 4; i++) {
1609 if (pt_vaddr[pte + i] != scratch_pte)
1610 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1611 else
1612 seq_puts(m, " SCRATCH ");
1613 }
1614 seq_puts(m, "\n");
1615 }
d1c54acd 1616 kunmap_px(ppgtt, pt_vaddr);
87d60b63
BW		 1617 }
1618}
1619
678d96fb 1620/* Write pde (index) from the page directory @pd to the page table @pt */
ec565b3c
MT		 1621static void gen6_write_pde(struct i915_page_directory *pd,
1622 const int pde, struct i915_page_table *pt)
6197349b 1623{
678d96fb
BW		 1624 /* Caller needs to make sure the write completes if necessary */
1625 struct i915_hw_ppgtt *ppgtt =
1626 container_of(pd, struct i915_hw_ppgtt, pd);
1627 u32 pd_entry;
6197349b 1628
567047be 1629 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
678d96fb 1630 pd_entry |= GEN6_PDE_VALID;
6197349b 1631
678d96fb
BW		 1632 writel(pd_entry, ppgtt->pd_addr + pde);
1633}
6197349b 1634
678d96fb
BW		 1635/* Write all the page tables found in the ppgtt structure to incrementing page
1636 * directories. */
1637static void gen6_write_page_range(struct drm_i915_private *dev_priv,
ec565b3c 1638 struct i915_page_directory *pd,
678d96fb
BW		 1639 uint32_t start, uint32_t length)
1640{
72e96d64 1641 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ec565b3c 1642 struct i915_page_table *pt;
731f74c5 1643 uint32_t pde;
678d96fb 1644
731f74c5 1645 gen6_for_each_pde(pt, pd, start, length, pde)
678d96fb
BW		 1646 gen6_write_pde(pd, pde, pt);
1647
1648 /* Make sure write is complete before other code can use this page
1649 * table. Also require for WC mapped PTEs */
72e96d64 1650 readl(ggtt->gsm);
3e302542
BW		 1651}
1652
b4a74e3a 1653static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
3e302542 1654{
44159ddb 1655 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
b4a74e3a 1656
44159ddb 1657 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
b4a74e3a
BW		 1658}
1659
90252e5c 1660static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1661 struct drm_i915_gem_request *req)
90252e5c 1662{
4a570db5 1663 struct intel_engine_cs *engine = req->engine;
90252e5c
BW		 1664 int ret;
1665
90252e5c 1666 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1667 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1668 if (ret)
1669 return ret;
1670
5fb9de1a 1671 ret = intel_ring_begin(req, 6);
90252e5c
BW		 1672 if (ret)
1673 return ret;
1674
e2f80391
TU		 1675 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1676 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1677 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1678 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1679 intel_ring_emit(engine, get_pd_offset(ppgtt));
1680 intel_ring_emit(engine, MI_NOOP);
1681 intel_ring_advance(engine);
90252e5c
BW		 1682
1683 return 0;
1684}
1685
71ba2d64 1686static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1687 struct drm_i915_gem_request *req)
71ba2d64 1688{
4a570db5 1689 struct intel_engine_cs *engine = req->engine;
71ba2d64
YZ		 1690 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1691
e2f80391
TU		 1692 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1693 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
71ba2d64
YZ		 1694 return 0;
1695}
1696
48a10389 1697static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1698 struct drm_i915_gem_request *req)
48a10389 1699{
4a570db5 1700 struct intel_engine_cs *engine = req->engine;
48a10389
BW		 1701 int ret;
1702
48a10389 1703 /* NB: TLBs must be flushed and invalidated before a switch */
e2f80391 1704 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
48a10389
BW		 1705 if (ret)
1706 return ret;
1707
5fb9de1a 1708 ret = intel_ring_begin(req, 6);
48a10389
BW		 1709 if (ret)
1710 return ret;
1711
e2f80391
TU		 1712 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1713 intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1714 intel_ring_emit(engine, PP_DIR_DCLV_2G);
1715 intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1716 intel_ring_emit(engine, get_pd_offset(ppgtt));
1717 intel_ring_emit(engine, MI_NOOP);
1718 intel_ring_advance(engine);
48a10389 1719
90252e5c 1720 /* XXX: RCS is the only one to auto invalidate the TLBs? */
e2f80391
TU		 1721 if (engine->id != RCS) {
1722 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
90252e5c
BW		 1723 if (ret)
1724 return ret;
1725 }
1726
48a10389
BW		 1727 return 0;
1728}
1729
eeb9488e 1730static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
e85b26dc 1731 struct drm_i915_gem_request *req)
eeb9488e 1732{
4a570db5 1733 struct intel_engine_cs *engine = req->engine;
eeb9488e 1734 struct drm_device *dev = ppgtt->base.dev;
fac5e23e 1735 struct drm_i915_private *dev_priv = to_i915(dev);
eeb9488e 1736
48a10389 1737
e2f80391
TU		 1738 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1739 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
eeb9488e 1740
e2f80391 1741 POSTING_READ(RING_PP_DIR_DCLV(engine));
eeb9488e
BW		 1742
1743 return 0;
1744}
1745
82460d97 1746static void gen8_ppgtt_enable(struct drm_device *dev)
eeb9488e 1747{
fac5e23e 1748 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1749 struct intel_engine_cs *engine;
3e302542 1750
b4ac5afc 1751 for_each_engine(engine, dev_priv) {
2dba3239 1752 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
e2f80391 1753 I915_WRITE(RING_MODE_GEN7(engine),
2dba3239 1754 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
eeb9488e 1755 }
eeb9488e 1756}
6197349b 1757
82460d97 1758static void gen7_ppgtt_enable(struct drm_device *dev)
3e302542 1759{
fac5e23e 1760 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1761 struct intel_engine_cs *engine;
b4a74e3a 1762 uint32_t ecochk, ecobits;
6197349b 1763
b4a74e3a
BW		 1764 ecobits = I915_READ(GAC_ECO_BITS);
1765 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
a65c2fcd 1766
b4a74e3a
BW		 1767 ecochk = I915_READ(GAM_ECOCHK);
1768 if (IS_HASWELL(dev)) {
1769 ecochk |= ECOCHK_PPGTT_WB_HSW;
1770 } else {
1771 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1772 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1773 }
1774 I915_WRITE(GAM_ECOCHK, ecochk);
a65c2fcd 1775
b4ac5afc 1776 for_each_engine(engine, dev_priv) {
6197349b 1777 /* GFX_MODE is per-ring on gen7+ */
e2f80391 1778 I915_WRITE(RING_MODE_GEN7(engine),
b4a74e3a 1779 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b 1780 }
b4a74e3a 1781}
6197349b 1782
82460d97 1783static void gen6_ppgtt_enable(struct drm_device *dev)
b4a74e3a 1784{
fac5e23e 1785 struct drm_i915_private *dev_priv = to_i915(dev);
b4a74e3a 1786 uint32_t ecochk, gab_ctl, ecobits;
a65c2fcd 1787
b4a74e3a
BW		 1788 ecobits = I915_READ(GAC_ECO_BITS);
1789 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1790 ECOBITS_PPGTT_CACHE64B);
6197349b 1791
b4a74e3a
BW		 1792 gab_ctl = I915_READ(GAB_CTL);
1793 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1794
1795 ecochk = I915_READ(GAM_ECOCHK);
1796 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1797
1798 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
6197349b
BW		 1799}
1800
1d2a314c 1801/* PPGTT support for Sandybdrige/Gen6 and later */
853ba5d2 1802static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 1803 uint64_t start,
1804 uint64_t length,
828c7908 1805 bool use_scratch)
1d2a314c 1806{
e5716f55 1807 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
07749ef3 1808 gen6_pte_t *pt_vaddr, scratch_pte;
782f1495
BW		 1809 unsigned first_entry = start >> PAGE_SHIFT;
1810 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3
MT		 1811 unsigned act_pt = first_entry / GEN6_PTES;
1812 unsigned first_pte = first_entry % GEN6_PTES;
7bddb01f 1813 unsigned last_pte, i;
1d2a314c 1814
c114f76a
MK		 1815 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1816 I915_CACHE_LLC, true, 0);
1d2a314c 1817
7bddb01f
DV		 1818 while (num_entries) {
1819 last_pte = first_pte + num_entries;
07749ef3
MT		 1820 if (last_pte > GEN6_PTES)
1821 last_pte = GEN6_PTES;
7bddb01f 1822
d1c54acd 1823 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1d2a314c 1824
7bddb01f
DV		 1825 for (i = first_pte; i < last_pte; i++)
1826 pt_vaddr[i] = scratch_pte;
1d2a314c 1827
d1c54acd 1828 kunmap_px(ppgtt, pt_vaddr);
1d2a314c 1829
7bddb01f
DV		 1830 num_entries -= last_pte - first_pte;
1831 first_pte = 0;
a15326a5 1832 act_pt++;
7bddb01f 1833 }
1d2a314c
DV		 1834}
1835
853ba5d2 1836static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
def886c3 1837 struct sg_table *pages,
782f1495 1838 uint64_t start,
24f3a8cf 1839 enum i915_cache_level cache_level, u32 flags)
def886c3 1840{
e5716f55 1841 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
782f1495 1842 unsigned first_entry = start >> PAGE_SHIFT;
07749ef3
MT		 1843 unsigned act_pt = first_entry / GEN6_PTES;
1844 unsigned act_pte = first_entry % GEN6_PTES;
85d1225e
DG		 1845 gen6_pte_t *pt_vaddr = NULL;
1846 struct sgt_iter sgt_iter;
1847 dma_addr_t addr;
6e995e23 1848
85d1225e 1849 for_each_sgt_dma(addr, sgt_iter, pages) {
cc79714f 1850 if (pt_vaddr == NULL)
d1c54acd 1851 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
6e995e23 1852
cc79714f 1853 pt_vaddr[act_pte] =
85d1225e 1854 vm->pte_encode(addr, cache_level, true, flags);
24f3a8cf 1855
07749ef3 1856 if (++act_pte == GEN6_PTES) {
d1c54acd 1857 kunmap_px(ppgtt, pt_vaddr);
cc79714f 1858 pt_vaddr = NULL;
a15326a5 1859 act_pt++;
6e995e23 1860 act_pte = 0;
def886c3 1861 }
def886c3 1862 }
85d1225e 1863
cc79714f 1864 if (pt_vaddr)
d1c54acd 1865 kunmap_px(ppgtt, pt_vaddr);
def886c3
DV		 1866}
1867
678d96fb 1868static int gen6_alloc_va_range(struct i915_address_space *vm,
a05d80ee 1869 uint64_t start_in, uint64_t length_in)
678d96fb 1870{
4933d519
MT		 1871 DECLARE_BITMAP(new_page_tables, I915_PDES);
1872 struct drm_device *dev = vm->dev;
72e96d64
JL		 1873 struct drm_i915_private *dev_priv = to_i915(dev);
1874 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e5716f55 1875 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
ec565b3c 1876 struct i915_page_table *pt;
a05d80ee 1877 uint32_t start, length, start_save, length_save;
731f74c5 1878 uint32_t pde;
4933d519
MT		 1879 int ret;
1880
a05d80ee
MK		 1881 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1882 return -ENODEV;
1883
1884 start = start_save = start_in;
1885 length = length_save = length_in;
4933d519
MT		 1886
1887 bitmap_zero(new_page_tables, I915_PDES);
1888
1889 /* The allocation is done in two stages so that we can bail out with
1890 * minimal amount of pain. The first stage finds new page tables that
1891 * need allocation. The second stage marks use ptes within the page
1892 * tables.
1893 */
731f74c5 1894 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
79ab9370 1895 if (pt != vm->scratch_pt) {
4933d519
MT		 1896 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1897 continue;
1898 }
1899
1900 /* We've already allocated a page table */
1901 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1902
8a1ebd74 1903 pt = alloc_pt(dev);
4933d519
MT		 1904 if (IS_ERR(pt)) {
1905 ret = PTR_ERR(pt);
1906 goto unwind_out;
1907 }
1908
1909 gen6_initialize_pt(vm, pt);
1910
1911 ppgtt->pd.page_table[pde] = pt;
966082c9 1912 __set_bit(pde, new_page_tables);
72744cb1 1913 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
4933d519
MT		 1914 }
1915
1916 start = start_save;
1917 length = length_save;
678d96fb 1918
731f74c5 1919 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
678d96fb
BW		 1920 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1921
1922 bitmap_zero(tmp_bitmap, GEN6_PTES);
1923 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1924 gen6_pte_count(start, length));
1925
966082c9 1926 if (__test_and_clear_bit(pde, new_page_tables))
4933d519
MT		 1927 gen6_write_pde(&ppgtt->pd, pde, pt);
1928
72744cb1
MT		 1929 trace_i915_page_table_entry_map(vm, pde, pt,
1930 gen6_pte_index(start),
1931 gen6_pte_count(start, length),
1932 GEN6_PTES);
4933d519 1933 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
678d96fb
BW		 1934 GEN6_PTES);
1935 }
1936
4933d519
MT		 1937 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1938
1939 /* Make sure write is complete before other code can use this page
1940 * table. Also require for WC mapped PTEs */
72e96d64 1941 readl(ggtt->gsm);
4933d519 1942
563222a7 1943 mark_tlbs_dirty(ppgtt);
678d96fb 1944 return 0;
4933d519
MT		 1945
1946unwind_out:
1947 for_each_set_bit(pde, new_page_tables, I915_PDES) {
ec565b3c 1948 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
4933d519 1949
79ab9370 1950 ppgtt->pd.page_table[pde] = vm->scratch_pt;
a08e111a 1951 free_pt(vm->dev, pt);
4933d519
MT		 1952 }
1953
1954 mark_tlbs_dirty(ppgtt);
1955 return ret;
678d96fb
BW		 1956}
1957
8776f02b
MK		 1958static int gen6_init_scratch(struct i915_address_space *vm)
1959{
1960 struct drm_device *dev = vm->dev;
1961
1962 vm->scratch_page = alloc_scratch_page(dev);
1963 if (IS_ERR(vm->scratch_page))
1964 return PTR_ERR(vm->scratch_page);
1965
1966 vm->scratch_pt = alloc_pt(dev);
1967 if (IS_ERR(vm->scratch_pt)) {
1968 free_scratch_page(dev, vm->scratch_page);
1969 return PTR_ERR(vm->scratch_pt);
1970 }
1971
1972 gen6_initialize_pt(vm, vm->scratch_pt);
1973
1974 return 0;
1975}
1976
1977static void gen6_free_scratch(struct i915_address_space *vm)
1978{
1979 struct drm_device *dev = vm->dev;
1980
1981 free_pt(dev, vm->scratch_pt);
1982 free_scratch_page(dev, vm->scratch_page);
1983}
1984
061dd493 1985static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
a00d825d 1986{
e5716f55 1987 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
731f74c5
DG		 1988 struct i915_page_directory *pd = &ppgtt->pd;
1989 struct drm_device *dev = vm->dev;
09942c65
MT		 1990 struct i915_page_table *pt;
1991 uint32_t pde;
4933d519 1992
061dd493
DV		 1993 drm_mm_remove_node(&ppgtt->node);
1994
731f74c5 1995 gen6_for_all_pdes(pt, pd, pde)
79ab9370 1996 if (pt != vm->scratch_pt)
731f74c5 1997 free_pt(dev, pt);
06fda602 1998
8776f02b 1999 gen6_free_scratch(vm);
3440d265
DV		 2000}
2001
b146520f 2002static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
3440d265 2003{
8776f02b 2004 struct i915_address_space *vm = &ppgtt->base;
853ba5d2 2005 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 2006 struct drm_i915_private *dev_priv = to_i915(dev);
2007 struct i915_ggtt *ggtt = &dev_priv->ggtt;
e3cc1995 2008 bool retried = false;
b146520f 2009 int ret;
1d2a314c 2010
c8d4c0d6
BW		 2011 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2012 * allocator works in address space sizes, so it's multiplied by page
2013 * size. We allocate at the top of the GTT to avoid fragmentation.
2014 */
72e96d64 2015 BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
4933d519 2016
8776f02b
MK		 2017 ret = gen6_init_scratch(vm);
2018 if (ret)
2019 return ret;
4933d519 2020
e3cc1995 2021alloc:
72e96d64 2022 ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
c8d4c0d6
BW		 2023 &ppgtt->node, GEN6_PD_SIZE,
2024 GEN6_PD_ALIGN, 0,
72e96d64 2025 0, ggtt->base.total,
3e8b5ae9 2026 DRM_MM_TOPDOWN);
e3cc1995 2027 if (ret == -ENOSPC && !retried) {
72e96d64 2028 ret = i915_gem_evict_something(dev, &ggtt->base,
e3cc1995 2029 GEN6_PD_SIZE, GEN6_PD_ALIGN,
d23db88c 2030 I915_CACHE_NONE,
72e96d64 2031 0, ggtt->base.total,
d23db88c 2032 0);
e3cc1995 2033 if (ret)
678d96fb 2034 goto err_out;
e3cc1995
BW		 2035
2036 retried = true;
2037 goto alloc;
2038 }
c8d4c0d6 2039
c8c26622 2040 if (ret)
678d96fb
BW		 2041 goto err_out;
2042
c8c26622 2043
72e96d64 2044 if (ppgtt->node.start < ggtt->mappable_end)
c8d4c0d6 2045 DRM_DEBUG("Forced to use aperture for PDEs\n");
1d2a314c 2046
c8c26622 2047 return 0;
678d96fb
BW		 2048
2049err_out:
8776f02b 2050 gen6_free_scratch(vm);
678d96fb 2051 return ret;
b146520f
BW		 2052}
2053
b146520f
BW		 2054static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2055{
2f2cf682 2056 return gen6_ppgtt_allocate_page_directories(ppgtt);
4933d519 2057}
06dc68d6 2058
4933d519
MT		 2059static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2060 uint64_t start, uint64_t length)
2061{
ec565b3c 2062 struct i915_page_table *unused;
731f74c5 2063 uint32_t pde;
1d2a314c 2064
731f74c5 2065 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
79ab9370 2066 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
b146520f
BW		 2067}
2068
5c5f6457 2069static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
b146520f
BW		 2070{
2071 struct drm_device *dev = ppgtt->base.dev;
72e96d64
JL		 2072 struct drm_i915_private *dev_priv = to_i915(dev);
2073 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b146520f
BW		 2074 int ret;
2075
72e96d64 2076 ppgtt->base.pte_encode = ggtt->base.pte_encode;
b146520f 2077 if (IS_GEN6(dev)) {
b146520f
BW		 2078 ppgtt->switch_mm = gen6_mm_switch;
2079 } else if (IS_HASWELL(dev)) {
b146520f
BW		 2080 ppgtt->switch_mm = hsw_mm_switch;
2081 } else if (IS_GEN7(dev)) {
b146520f
BW		 2082 ppgtt->switch_mm = gen7_mm_switch;
2083 } else
2084 BUG();
2085
c033666a 2086 if (intel_vgpu_active(dev_priv))
71ba2d64
YZ		 2087 ppgtt->switch_mm = vgpu_mm_switch;
2088
b146520f
BW		 2089 ret = gen6_ppgtt_alloc(ppgtt);
2090 if (ret)
2091 return ret;
2092
5c5f6457 2093 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
b146520f
BW		 2094 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2095 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
777dc5bb
DV		 2096 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2097 ppgtt->base.bind_vma = ppgtt_bind_vma;
b146520f 2098 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
b146520f 2099 ppgtt->base.start = 0;
09942c65 2100 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
87d60b63 2101 ppgtt->debug_dump = gen6_dump_ppgtt;
1d2a314c 2102
44159ddb 2103 ppgtt->pd.base.ggtt_offset =
07749ef3 2104 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1d2a314c 2105
72e96d64 2106 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
44159ddb 2107 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
678d96fb 2108
5c5f6457 2109 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1d2a314c 2110
678d96fb
BW		 2111 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2112
440fd528 2113 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
b146520f
BW		 2114 ppgtt->node.size >> 20,
2115 ppgtt->node.start / PAGE_SIZE);
3440d265 2116
fa76da34 2117 DRM_DEBUG("Adding PPGTT at offset %x\n",
44159ddb 2118 ppgtt->pd.base.ggtt_offset << 10);
fa76da34 2119
b146520f 2120 return 0;
3440d265
DV		 2121}
2122
5c5f6457 2123static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
3440d265 2124{
853ba5d2 2125 ppgtt->base.dev = dev;
3440d265 2126
3ed124b2 2127 if (INTEL_INFO(dev)->gen < 8)
5c5f6457 2128 return gen6_ppgtt_init(ppgtt);
3ed124b2 2129 else
d7b2633d 2130 return gen8_ppgtt_init(ppgtt);
fa76da34 2131}
c114f76a 2132
a2cad9df
MW		 2133static void i915_address_space_init(struct i915_address_space *vm,
2134 struct drm_i915_private *dev_priv)
2135{
2136 drm_mm_init(&vm->mm, vm->start, vm->total);
2137 vm->dev = dev_priv->dev;
2138 INIT_LIST_HEAD(&vm->active_list);
2139 INIT_LIST_HEAD(&vm->inactive_list);
2140 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2141}
2142
d5165ebd
TG		 2143static void gtt_write_workarounds(struct drm_device *dev)
2144{
fac5e23e 2145 struct drm_i915_private *dev_priv = to_i915(dev);
d5165ebd
TG		 2146
2147 /* This function is for gtt related workarounds. This function is
2148 * called on driver load and after a GPU reset, so you can place
2149 * workarounds here even if they get overwritten by GPU reset.
2150 */
2151 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2152 if (IS_BROADWELL(dev))
2153 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2154 else if (IS_CHERRYVIEW(dev))
2155 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2156 else if (IS_SKYLAKE(dev))
2157 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2158 else if (IS_BROXTON(dev))
2159 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2160}
2161
cba6dba4 2162static int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
fa76da34 2163{
fac5e23e 2164 struct drm_i915_private *dev_priv = to_i915(dev);
fa76da34 2165 int ret = 0;
3ed124b2 2166
5c5f6457 2167 ret = __hw_ppgtt_init(dev, ppgtt);
fa76da34 2168 if (ret == 0) {
c7c48dfd 2169 kref_init(&ppgtt->ref);
a2cad9df 2170 i915_address_space_init(&ppgtt->base, dev_priv);
93bd8649 2171 }
1d2a314c
DV		 2172
2173 return ret;
2174}
2175
82460d97
DV		 2176int i915_ppgtt_init_hw(struct drm_device *dev)
2177{
d5165ebd
TG		 2178 gtt_write_workarounds(dev);
2179
671b5013
TD		 2180 /* In the case of execlists, PPGTT is enabled by the context descriptor
2181 * and the PDPs are contained within the context itself. We don't
2182 * need to do anything here. */
2183 if (i915.enable_execlists)
2184 return 0;
2185
82460d97
DV		 2186 if (!USES_PPGTT(dev))
2187 return 0;
2188
2189 if (IS_GEN6(dev))
2190 gen6_ppgtt_enable(dev);
2191 else if (IS_GEN7(dev))
2192 gen7_ppgtt_enable(dev);
2193 else if (INTEL_INFO(dev)->gen >= 8)
2194 gen8_ppgtt_enable(dev);
2195 else
5f77eeb0 2196 MISSING_CASE(INTEL_INFO(dev)->gen);
82460d97 2197
4ad2fd88
JH		 2198 return 0;
2199}
1d2a314c 2200
4d884705
DV		 2201struct i915_hw_ppgtt *
2202i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2203{
2204 struct i915_hw_ppgtt *ppgtt;
2205 int ret;
2206
2207 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2208 if (!ppgtt)
2209 return ERR_PTR(-ENOMEM);
2210
2211 ret = i915_ppgtt_init(dev, ppgtt);
2212 if (ret) {
2213 kfree(ppgtt);
2214 return ERR_PTR(ret);
2215 }
2216
2217 ppgtt->file_priv = fpriv;
2218
198c974d
DCS		 2219 trace_i915_ppgtt_create(&ppgtt->base);
2220
4d884705
DV		 2221 return ppgtt;
2222}
2223
ee960be7
DV		 2224void i915_ppgtt_release(struct kref *kref)
2225{
2226 struct i915_hw_ppgtt *ppgtt =
2227 container_of(kref, struct i915_hw_ppgtt, ref);
2228
198c974d
DCS		 2229 trace_i915_ppgtt_release(&ppgtt->base);
2230
ee960be7
DV		 2231 /* vmas should already be unbound */
2232 WARN_ON(!list_empty(&ppgtt->base.active_list));
2233 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2234
19dd120c
DV		 2235 list_del(&ppgtt->base.global_link);
2236 drm_mm_takedown(&ppgtt->base.mm);
2237
ee960be7
DV		 2238 ppgtt->base.cleanup(&ppgtt->base);
2239 kfree(ppgtt);
2240}
1d2a314c 2241
a81cc00c
BW		 2242extern int intel_iommu_gfx_mapped;
2243/* Certain Gen5 chipsets require require idling the GPU before
2244 * unmapping anything from the GTT when VT-d is enabled.
2245 */
2c642b07 2246static bool needs_idle_maps(struct drm_device *dev)
a81cc00c
BW		 2247{
2248#ifdef CONFIG_INTEL_IOMMU
2249 /* Query intel_iommu to see if we need the workaround. Presumably that
2250 * was loaded first.
2251 */
2252 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2253 return true;
2254#endif
2255 return false;
2256}
2257
5c042287
BW		 2258static bool do_idling(struct drm_i915_private *dev_priv)
2259{
72e96d64 2260 struct i915_ggtt *ggtt = &dev_priv->ggtt;
5c042287
BW		 2261 bool ret = dev_priv->mm.interruptible;
2262
72e96d64 2263 if (unlikely(ggtt->do_idle_maps)) {
5c042287 2264 dev_priv->mm.interruptible = false;
6e5a5beb
CW		 2265 if (i915_gem_wait_for_idle(dev_priv)) {
2266 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
5c042287
BW		 2267 /* Wait a bit, in hopes it avoids the hang */
2268 udelay(10);
2269 }
2270 }
2271
2272 return ret;
2273}
2274
2275static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2276{
72e96d64
JL		 2277 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2278
2279 if (unlikely(ggtt->do_idle_maps))
5c042287
BW		 2280 dev_priv->mm.interruptible = interruptible;
2281}
2282
dc97997a 2283void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
828c7908 2284{
e2f80391 2285 struct intel_engine_cs *engine;
828c7908 2286
dc97997a 2287 if (INTEL_INFO(dev_priv)->gen < 6)
828c7908
BW		 2288 return;
2289
b4ac5afc 2290 for_each_engine(engine, dev_priv) {
828c7908 2291 u32 fault_reg;
e2f80391 2292 fault_reg = I915_READ(RING_FAULT_REG(engine));
828c7908
BW		 2293 if (fault_reg & RING_FAULT_VALID) {
2294 DRM_DEBUG_DRIVER("Unexpected fault\n"
59a5d290 2295 "\tAddr: 0x%08lx\n"
828c7908
BW		 2296 "\tAddress space: %s\n"
2297 "\tSource ID: %d\n"
2298 "\tType: %d\n",
2299 fault_reg & PAGE_MASK,
2300 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2301 RING_FAULT_SRCID(fault_reg),
2302 RING_FAULT_FAULT_TYPE(fault_reg));
e2f80391 2303 I915_WRITE(RING_FAULT_REG(engine),
828c7908
BW		 2304 fault_reg & ~RING_FAULT_VALID);
2305 }
2306 }
4a570db5 2307 POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
828c7908
BW		 2308}
2309
91e56499
CW		 2310static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2311{
2d1fe073 2312 if (INTEL_INFO(dev_priv)->gen < 6) {
91e56499
CW		 2313 intel_gtt_chipset_flush();
2314 } else {
2315 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2316 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2317 }
2318}
2319
828c7908
BW		 2320void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2321{
72e96d64
JL		 2322 struct drm_i915_private *dev_priv = to_i915(dev);
2323 struct i915_ggtt *ggtt = &dev_priv->ggtt;
828c7908
BW		 2324
2325 /* Don't bother messing with faults pre GEN6 as we have little
2326 * documentation supporting that it's a good idea.
2327 */
2328 if (INTEL_INFO(dev)->gen < 6)
2329 return;
2330
dc97997a 2331 i915_check_and_clear_faults(dev_priv);
828c7908 2332
72e96d64
JL		 2333 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2334 true);
91e56499
CW		 2335
2336 i915_ggtt_flush(dev_priv);
828c7908
BW		 2337}
2338
74163907 2339int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2340{
9da3da66
CW		 2341 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2342 obj->pages->sgl, obj->pages->nents,
2343 PCI_DMA_BIDIRECTIONAL))
2344 return -ENOSPC;
2345
2346 return 0;
7c2e6fdf
DV		 2347}
2348
2c642b07 2349static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
94ec8f61
BW		 2350{
2351#ifdef writeq
2352 writeq(pte, addr);
2353#else
2354 iowrite32((u32)pte, addr);
2355 iowrite32(pte >> 32, addr + 4);
2356#endif
2357}
2358
d6473f56
CW		 2359static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2360 dma_addr_t addr,
2361 uint64_t offset,
2362 enum i915_cache_level level,
2363 u32 unused)
2364{
2365 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2366 gen8_pte_t __iomem *pte =
2367 (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
2368 (offset >> PAGE_SHIFT);
2369 int rpm_atomic_seq;
2370
2371 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2372
2373 gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
2374
2375 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2376 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2377
2378 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2379}
2380
94ec8f61
BW		 2381static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2382 struct sg_table *st,
782f1495 2383 uint64_t start,
24f3a8cf 2384 enum i915_cache_level level, u32 unused)
94ec8f61 2385{
72e96d64 2386 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2387 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
85d1225e
DG		 2388 struct sgt_iter sgt_iter;
2389 gen8_pte_t __iomem *gtt_entries;
2390 gen8_pte_t gtt_entry;
2391 dma_addr_t addr;
be69459a 2392 int rpm_atomic_seq;
85d1225e 2393 int i = 0;
be69459a
ID		 2394
2395 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61 2396
85d1225e
DG		 2397 gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2398
2399 for_each_sgt_dma(addr, sgt_iter, st) {
2400 gtt_entry = gen8_pte_encode(addr, level, true);
2401 gen8_set_pte(&gtt_entries[i++], gtt_entry);
94ec8f61
BW		 2402 }
2403
2404 /*
2405 * XXX: This serves as a posting read to make sure that the PTE has
2406 * actually been updated. There is some concern that even though
2407 * registers and PTEs are within the same BAR that they are potentially
2408 * of NUMA access patterns. Therefore, even with the way we assume
2409 * hardware should work, we must keep this posting read for paranoia.
2410 */
2411 if (i != 0)
85d1225e 2412 WARN_ON(readq(&gtt_entries[i-1]) != gtt_entry);
94ec8f61 2413
94ec8f61
BW		 2414 /* This next bit makes the above posting read even more important. We
2415 * want to flush the TLBs only after we're certain all the PTE updates
2416 * have finished.
2417 */
2418 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2419 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2420
2421 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2422}
2423
c140330b
CW		 2424struct insert_entries {
2425 struct i915_address_space *vm;
2426 struct sg_table *st;
2427 uint64_t start;
2428 enum i915_cache_level level;
2429 u32 flags;
2430};
2431
2432static int gen8_ggtt_insert_entries__cb(void *_arg)
2433{
2434 struct insert_entries *arg = _arg;
2435 gen8_ggtt_insert_entries(arg->vm, arg->st,
2436 arg->start, arg->level, arg->flags);
2437 return 0;
2438}
2439
2440static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2441 struct sg_table *st,
2442 uint64_t start,
2443 enum i915_cache_level level,
2444 u32 flags)
2445{
2446 struct insert_entries arg = { vm, st, start, level, flags };
2447 stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2448}
2449
d6473f56
CW		 2450static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2451 dma_addr_t addr,
2452 uint64_t offset,
2453 enum i915_cache_level level,
2454 u32 flags)
2455{
2456 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2457 gen6_pte_t __iomem *pte =
2458 (gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
2459 (offset >> PAGE_SHIFT);
2460 int rpm_atomic_seq;
2461
2462 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2463
2464 iowrite32(vm->pte_encode(addr, level, true, flags), pte);
2465
2466 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2467 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2468
2469 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2470}
2471
e76e9aeb
BW		 2472/*
2473 * Binds an object into the global gtt with the specified cache level. The object
2474 * will be accessible to the GPU via commands whose operands reference offsets
2475 * within the global GTT as well as accessible by the GPU through the GMADR
2476 * mapped BAR (dev_priv->mm.gtt->gtt).
2477 */
853ba5d2 2478static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
7faf1ab2 2479 struct sg_table *st,
782f1495 2480 uint64_t start,
24f3a8cf 2481 enum i915_cache_level level, u32 flags)
e76e9aeb 2482{
72e96d64 2483 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2484 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
85d1225e
DG		 2485 struct sgt_iter sgt_iter;
2486 gen6_pte_t __iomem *gtt_entries;
2487 gen6_pte_t gtt_entry;
2488 dma_addr_t addr;
be69459a 2489 int rpm_atomic_seq;
85d1225e 2490 int i = 0;
be69459a
ID		 2491
2492 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
e76e9aeb 2493
85d1225e
DG		 2494 gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2495
2496 for_each_sgt_dma(addr, sgt_iter, st) {
2497 gtt_entry = vm->pte_encode(addr, level, true, flags);
2498 iowrite32(gtt_entry, &gtt_entries[i++]);
e76e9aeb
BW		 2499 }
2500
e76e9aeb
BW		 2501 /* XXX: This serves as a posting read to make sure that the PTE has
2502 * actually been updated. There is some concern that even though
2503 * registers and PTEs are within the same BAR that they are potentially
2504 * of NUMA access patterns. Therefore, even with the way we assume
2505 * hardware should work, we must keep this posting read for paranoia.
2506 */
85d1225e
DG		 2507 if (i != 0)
2508 WARN_ON(readl(&gtt_entries[i-1]) != gtt_entry);
0f9b91c7
BW		 2509
2510 /* This next bit makes the above posting read even more important. We
2511 * want to flush the TLBs only after we're certain all the PTE updates
2512 * have finished.
2513 */
2514 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2515 POSTING_READ(GFX_FLSH_CNTL_GEN6);
be69459a
ID		 2516
2517 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
e76e9aeb
BW		 2518}
2519
f7770bfd
CW		 2520static void nop_clear_range(struct i915_address_space *vm,
2521 uint64_t start,
2522 uint64_t length,
2523 bool use_scratch)
2524{
2525}
2526
94ec8f61 2527static void gen8_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2528 uint64_t start,
2529 uint64_t length,
94ec8f61
BW		 2530 bool use_scratch)
2531{
72e96d64 2532 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2533 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
782f1495
BW		 2534 unsigned first_entry = start >> PAGE_SHIFT;
2535 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2536 gen8_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2537 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2538 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
94ec8f61 2539 int i;
be69459a
ID		 2540 int rpm_atomic_seq;
2541
2542 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
94ec8f61
BW		 2543
2544 if (WARN(num_entries > max_entries,
2545 "First entry = %d; Num entries = %d (max=%d)\n",
2546 first_entry, num_entries, max_entries))
2547 num_entries = max_entries;
2548
c114f76a 2549 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
94ec8f61
BW		 2550 I915_CACHE_LLC,
2551 use_scratch);
2552 for (i = 0; i < num_entries; i++)
2553 gen8_set_pte(&gtt_base[i], scratch_pte);
2554 readl(gtt_base);
be69459a
ID		 2555
2556 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
94ec8f61
BW		 2557}
2558
853ba5d2 2559static void gen6_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2560 uint64_t start,
2561 uint64_t length,
828c7908 2562 bool use_scratch)
7faf1ab2 2563{
72e96d64 2564 struct drm_i915_private *dev_priv = to_i915(vm->dev);
ce7fda2e 2565 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
782f1495
BW		 2566 unsigned first_entry = start >> PAGE_SHIFT;
2567 unsigned num_entries = length >> PAGE_SHIFT;
07749ef3 2568 gen6_pte_t scratch_pte, __iomem *gtt_base =
72e96d64
JL		 2569 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2570 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
7faf1ab2 2571 int i;
be69459a
ID		 2572 int rpm_atomic_seq;
2573
2574 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2
DV		 2575
2576 if (WARN(num_entries > max_entries,
2577 "First entry = %d; Num entries = %d (max=%d)\n",
2578 first_entry, num_entries, max_entries))
2579 num_entries = max_entries;
2580
c114f76a
MK		 2581 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2582 I915_CACHE_LLC, use_scratch, 0);
828c7908 2583
7faf1ab2
DV		 2584 for (i = 0; i < num_entries; i++)
2585 iowrite32(scratch_pte, &gtt_base[i]);
2586 readl(gtt_base);
be69459a
ID		 2587
2588 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2589}
2590
d6473f56
CW		 2591static void i915_ggtt_insert_page(struct i915_address_space *vm,
2592 dma_addr_t addr,
2593 uint64_t offset,
2594 enum i915_cache_level cache_level,
2595 u32 unused)
2596{
2597 struct drm_i915_private *dev_priv = to_i915(vm->dev);
2598 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2599 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2600 int rpm_atomic_seq;
2601
2602 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2603
2604 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2605
2606 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2607}
2608
d369d2d9
DV		 2609static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2610 struct sg_table *pages,
2611 uint64_t start,
2612 enum i915_cache_level cache_level, u32 unused)
7faf1ab2 2613{
fac5e23e 2614 struct drm_i915_private *dev_priv = to_i915(vm->dev);
7faf1ab2
DV		 2615 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2616 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
be69459a
ID		 2617 int rpm_atomic_seq;
2618
2619 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
7faf1ab2 2620
d369d2d9 2621 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
0875546c 2622
be69459a
ID		 2623 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2624
7faf1ab2
DV		 2625}
2626
853ba5d2 2627static void i915_ggtt_clear_range(struct i915_address_space *vm,
782f1495
BW		 2628 uint64_t start,
2629 uint64_t length,
828c7908 2630 bool unused)
7faf1ab2 2631{
fac5e23e 2632 struct drm_i915_private *dev_priv = to_i915(vm->dev);
782f1495
BW		 2633 unsigned first_entry = start >> PAGE_SHIFT;
2634 unsigned num_entries = length >> PAGE_SHIFT;
be69459a
ID		 2635 int rpm_atomic_seq;
2636
2637 rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2638
7faf1ab2 2639 intel_gtt_clear_range(first_entry, num_entries);
be69459a
ID		 2640
2641 assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
7faf1ab2
DV		 2642}
2643
70b9f6f8
DV		 2644static int ggtt_bind_vma(struct i915_vma *vma,
2645 enum i915_cache_level cache_level,
2646 u32 flags)
0a878716
DV		 2647{
2648 struct drm_i915_gem_object *obj = vma->obj;
2649 u32 pte_flags = 0;
2650 int ret;
2651
2652 ret = i915_get_ggtt_vma_pages(vma);
2653 if (ret)
2654 return ret;
2655
2656 /* Currently applicable only to VLV */
2657 if (obj->gt_ro)
2658 pte_flags |= PTE_READ_ONLY;
2659
2660 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2661 vma->node.start,
2662 cache_level, pte_flags);
2663
2664 /*
2665 * Without aliasing PPGTT there's no difference between
2666 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2667 * upgrade to both bound if we bind either to avoid double-binding.
2668 */
2669 vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2670
2671 return 0;
2672}
2673
2674static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2675 enum i915_cache_level cache_level,
2676 u32 flags)
d5bd1449 2677{
321d178e 2678 u32 pte_flags;
70b9f6f8
DV		 2679 int ret;
2680
2681 ret = i915_get_ggtt_vma_pages(vma);
2682 if (ret)
2683 return ret;
7faf1ab2 2684
24f3a8cf 2685 /* Currently applicable only to VLV */
321d178e
CW		 2686 pte_flags = 0;
2687 if (vma->obj->gt_ro)
f329f5f6 2688 pte_flags |= PTE_READ_ONLY;
24f3a8cf 2689
ec7adb6e 2690
0a878716 2691 if (flags & GLOBAL_BIND) {
321d178e
CW		 2692 vma->vm->insert_entries(vma->vm,
2693 vma->ggtt_view.pages,
0875546c
DV		 2694 vma->node.start,
2695 cache_level, pte_flags);
6f65e29a 2696 }
d5bd1449 2697
0a878716 2698 if (flags & LOCAL_BIND) {
321d178e
CW		 2699 struct i915_hw_ppgtt *appgtt =
2700 to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2701 appgtt->base.insert_entries(&appgtt->base,
2702 vma->ggtt_view.pages,
782f1495 2703 vma->node.start,
f329f5f6 2704 cache_level, pte_flags);
6f65e29a 2705 }
70b9f6f8
DV		 2706
2707 return 0;
d5bd1449
CW		 2708}
2709
6f65e29a 2710static void ggtt_unbind_vma(struct i915_vma *vma)
74163907 2711{
6f65e29a 2712 struct drm_device *dev = vma->vm->dev;
fac5e23e 2713 struct drm_i915_private *dev_priv = to_i915(dev);
6f65e29a 2714 struct drm_i915_gem_object *obj = vma->obj;
06615ee5
JL		 2715 const uint64_t size = min_t(uint64_t,
2716 obj->base.size,
2717 vma->node.size);
6f65e29a 2718
aff43766 2719 if (vma->bound & GLOBAL_BIND) {
782f1495
BW		 2720 vma->vm->clear_range(vma->vm,
2721 vma->node.start,
06615ee5 2722 size,
6f65e29a 2723 true);
6f65e29a 2724 }
74898d7e 2725
0875546c 2726 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
6f65e29a 2727 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
06615ee5 2728
6f65e29a 2729 appgtt->base.clear_range(&appgtt->base,
782f1495 2730 vma->node.start,
06615ee5 2731 size,
6f65e29a 2732 true);
6f65e29a 2733 }
74163907
DV		 2734}
2735
2736void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
7c2e6fdf 2737{
5c042287 2738 struct drm_device *dev = obj->base.dev;
fac5e23e 2739 struct drm_i915_private *dev_priv = to_i915(dev);
5c042287
BW		 2740 bool interruptible;
2741
2742 interruptible = do_idling(dev_priv);
2743
5ec5b516
ID		 2744 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2745 PCI_DMA_BIDIRECTIONAL);
5c042287
BW		 2746
2747 undo_idling(dev_priv, interruptible);
7c2e6fdf 2748}
644ec02b 2749
42d6ab48
CW		 2750static void i915_gtt_color_adjust(struct drm_mm_node *node,
2751 unsigned long color,
440fd528
TR		 2752 u64 *start,
2753 u64 *end)
42d6ab48
CW		 2754{
2755 if (node->color != color)
2756 *start += 4096;
2757
2758 if (!list_empty(&node->node_list)) {
2759 node = list_entry(node->node_list.next,
2760 struct drm_mm_node,
2761 node_list);
2762 if (node->allocated && node->color != color)
2763 *end -= 4096;
2764 }
2765}
fbe5d36e 2766
f548c0e9 2767static int i915_gem_setup_global_gtt(struct drm_device *dev,
088e0df4
MT		 2768 u64 start,
2769 u64 mappable_end,
2770 u64 end)
644ec02b 2771{
e78891ca
BW		 2772 /* Let GEM Manage all of the aperture.
2773 *
2774 * However, leave one page at the end still bound to the scratch page.
2775 * There are a number of places where the hardware apparently prefetches
2776 * past the end of the object, and we've seen multiple hangs with the
2777 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2778 * aperture. One page should be enough to keep any prefetching inside
2779 * of the aperture.
2780 */
72e96d64
JL		 2781 struct drm_i915_private *dev_priv = to_i915(dev);
2782 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ed2f3452
CW		 2783 struct drm_mm_node *entry;
2784 struct drm_i915_gem_object *obj;
2785 unsigned long hole_start, hole_end;
fa76da34 2786 int ret;
644ec02b 2787
35451cb6
BW		 2788 BUG_ON(mappable_end > end);
2789
72e96d64 2790 ggtt->base.start = start;
5dda8fa3 2791
a2cad9df
MW		 2792 /* Subtract the guard page before address space initialization to
2793 * shrink the range used by drm_mm */
72e96d64
JL		 2794 ggtt->base.total = end - start - PAGE_SIZE;
2795 i915_address_space_init(&ggtt->base, dev_priv);
2796 ggtt->base.total += PAGE_SIZE;
5dda8fa3 2797
b02d22a3
ZW		 2798 ret = intel_vgt_balloon(dev_priv);
2799 if (ret)
2800 return ret;
5dda8fa3 2801
42d6ab48 2802 if (!HAS_LLC(dev))
72e96d64 2803 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
644ec02b 2804
ed2f3452 2805 /* Mark any preallocated objects as occupied */
35c20a60 2806 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
72e96d64 2807 struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base);
fa76da34 2808
088e0df4 2809 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
c6cfb325
BW		 2810 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2811
2812 WARN_ON(i915_gem_obj_ggtt_bound(obj));
72e96d64 2813 ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
6c5566a8
DV		 2814 if (ret) {
2815 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2816 return ret;
2817 }
aff43766 2818 vma->bound |= GLOBAL_BIND;
d0710abb 2819 __i915_vma_set_map_and_fenceable(vma);
72e96d64 2820 list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
ed2f3452
CW		 2821 }
2822
ed2f3452 2823 /* Clear any non-preallocated blocks */
72e96d64 2824 drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
ed2f3452
CW		 2825 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2826 hole_start, hole_end);
72e96d64 2827 ggtt->base.clear_range(&ggtt->base, hole_start,
782f1495 2828 hole_end - hole_start, true);
ed2f3452
CW		 2829 }
2830
2831 /* And finally clear the reserved guard page */
72e96d64 2832 ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true);
6c5566a8 2833
fa76da34
DV		 2834 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2835 struct i915_hw_ppgtt *ppgtt;
2836
2837 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2838 if (!ppgtt)
2839 return -ENOMEM;
2840
5c5f6457
DV		 2841 ret = __hw_ppgtt_init(dev, ppgtt);
2842 if (ret) {
2843 ppgtt->base.cleanup(&ppgtt->base);
2844 kfree(ppgtt);
2845 return ret;
2846 }
2847
2848 if (ppgtt->base.allocate_va_range)
2849 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2850 ppgtt->base.total);
4933d519 2851 if (ret) {
061dd493 2852 ppgtt->base.cleanup(&ppgtt->base);
4933d519 2853 kfree(ppgtt);
fa76da34 2854 return ret;
4933d519 2855 }
fa76da34 2856
5c5f6457
DV		 2857 ppgtt->base.clear_range(&ppgtt->base,
2858 ppgtt->base.start,
2859 ppgtt->base.total,
2860 true);
2861
fa76da34 2862 dev_priv->mm.aliasing_ppgtt = ppgtt;
72e96d64
JL		 2863 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2864 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
fa76da34
DV		 2865 }
2866
6c5566a8 2867 return 0;
e76e9aeb
BW		 2868}
2869
d85489d3
JL		 2870/**
2871 * i915_gem_init_ggtt - Initialize GEM for Global GTT
2872 * @dev: DRM device
2873 */
2874void i915_gem_init_ggtt(struct drm_device *dev)
d7e5008f 2875{
72e96d64
JL		 2876 struct drm_i915_private *dev_priv = to_i915(dev);
2877 struct i915_ggtt *ggtt = &dev_priv->ggtt;
d7e5008f 2878
72e96d64 2879 i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
e76e9aeb
BW		 2880}
2881
d85489d3
JL		 2882/**
2883 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2884 * @dev: DRM device
2885 */
2886void i915_ggtt_cleanup_hw(struct drm_device *dev)
90d0a0e8 2887{
72e96d64
JL		 2888 struct drm_i915_private *dev_priv = to_i915(dev);
2889 struct i915_ggtt *ggtt = &dev_priv->ggtt;
90d0a0e8 2890
70e32544
DV		 2891 if (dev_priv->mm.aliasing_ppgtt) {
2892 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2893
2894 ppgtt->base.cleanup(&ppgtt->base);
2895 }
2896
a4eba47b
ID		 2897 i915_gem_cleanup_stolen(dev);
2898
72e96d64 2899 if (drm_mm_initialized(&ggtt->base.mm)) {
b02d22a3 2900 intel_vgt_deballoon(dev_priv);
5dda8fa3 2901
72e96d64
JL		 2902 drm_mm_takedown(&ggtt->base.mm);
2903 list_del(&ggtt->base.global_link);
90d0a0e8
DV		 2904 }
2905
72e96d64 2906 ggtt->base.cleanup(&ggtt->base);
90d0a0e8 2907}
70e32544 2908
2c642b07 2909static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2910{
2911 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2912 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2913 return snb_gmch_ctl << 20;
2914}
2915
2c642b07 2916static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
9459d252
BW		 2917{
2918 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2919 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2920 if (bdw_gmch_ctl)
2921 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
562d55d9
BW		 2922
2923#ifdef CONFIG_X86_32
2924 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2925 if (bdw_gmch_ctl > 4)
2926 bdw_gmch_ctl = 4;
2927#endif
2928
9459d252
BW		 2929 return bdw_gmch_ctl << 20;
2930}
2931
2c642b07 2932static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
d7f25f23
DL		 2933{
2934 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2935 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2936
2937 if (gmch_ctrl)
2938 return 1 << (20 + gmch_ctrl);
2939
2940 return 0;
2941}
2942
2c642b07 2943static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
e76e9aeb
BW		 2944{
2945 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2946 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2947 return snb_gmch_ctl << 25; /* 32 MB units */
2948}
2949
2c642b07 2950static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
9459d252
BW		 2951{
2952 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2953 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2954 return bdw_gmch_ctl << 25; /* 32 MB units */
2955}
2956
d7f25f23
DL		 2957static size_t chv_get_stolen_size(u16 gmch_ctrl)
2958{
2959 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2960 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2961
2962 /*
2963 * 0x0 to 0x10: 32MB increments starting at 0MB
2964 * 0x11 to 0x16: 4MB increments starting at 8MB
2965 * 0x17 to 0x1d: 4MB increments start at 36MB
2966 */
2967 if (gmch_ctrl < 0x11)
2968 return gmch_ctrl << 25;
2969 else if (gmch_ctrl < 0x17)
2970 return (gmch_ctrl - 0x11 + 2) << 22;
2971 else
2972 return (gmch_ctrl - 0x17 + 9) << 22;
2973}
2974
66375014
DL		 2975static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2976{
2977 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2978 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2979
2980 if (gen9_gmch_ctl < 0xf0)
2981 return gen9_gmch_ctl << 25; /* 32 MB units */
2982 else
2983 /* 4MB increments starting at 0xf0 for 4MB */
2984 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2985}
2986
63340133
BW		 2987static int ggtt_probe_common(struct drm_device *dev,
2988 size_t gtt_size)
2989{
72e96d64
JL		 2990 struct drm_i915_private *dev_priv = to_i915(dev);
2991 struct i915_ggtt *ggtt = &dev_priv->ggtt;
4ad2af1e 2992 struct i915_page_scratch *scratch_page;
72e96d64 2993 phys_addr_t ggtt_phys_addr;
63340133
BW		 2994
2995 /* For Modern GENs the PTEs and register space are split in the BAR */
72e96d64
JL		 2996 ggtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2997 (pci_resource_len(dev->pdev, 0) / 2);
63340133 2998
2a073f89
ID		 2999 /*
3000 * On BXT writes larger than 64 bit to the GTT pagetable range will be
3001 * dropped. For WC mappings in general we have 64 byte burst writes
3002 * when the WC buffer is flushed, so we can't use it, but have to
3003 * resort to an uncached mapping. The WC issue is easily caught by the
3004 * readback check when writing GTT PTE entries.
3005 */
3006 if (IS_BROXTON(dev))
72e96d64 3007 ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size);
2a073f89 3008 else
72e96d64
JL		 3009 ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size);
3010 if (!ggtt->gsm) {
63340133
BW		 3011 DRM_ERROR("Failed to map the gtt page table\n");
3012 return -ENOMEM;
3013 }
3014
4ad2af1e
MK		 3015 scratch_page = alloc_scratch_page(dev);
3016 if (IS_ERR(scratch_page)) {
63340133
BW		 3017 DRM_ERROR("Scratch setup failed\n");
3018 /* iounmap will also get called at remove, but meh */
72e96d64 3019 iounmap(ggtt->gsm);
4ad2af1e 3020 return PTR_ERR(scratch_page);
63340133
BW		 3021 }
3022
72e96d64 3023 ggtt->base.scratch_page = scratch_page;
4ad2af1e
MK		 3024
3025 return 0;
63340133
BW		 3026}
3027
fbe5d36e
BW		 3028/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3029 * bits. When using advanced contexts each context stores its own PAT, but
3030 * writing this data shouldn't be harmful even in those cases. */
ee0ce478 3031static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
fbe5d36e 3032{
fbe5d36e
BW		 3033 uint64_t pat;
3034
3035 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
3036 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
3037 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
3038 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
3039 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
3040 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
3041 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
3042 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3043
2d1fe073 3044 if (!USES_PPGTT(dev_priv))
d6a8b72e
RV		 3045 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3046 * so RTL will always use the value corresponding to
3047 * pat_sel = 000".
3048 * So let's disable cache for GGTT to avoid screen corruptions.
3049 * MOCS still can be used though.
3050 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3051 * before this patch, i.e. the same uncached + snooping access
3052 * like on gen6/7 seems to be in effect.
3053 * - So this just fixes blitter/render access. Again it looks
3054 * like it's not just uncached access, but uncached + snooping.
3055 * So we can still hold onto all our assumptions wrt cpu
3056 * clflushing on LLC machines.
3057 */
3058 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
3059
fbe5d36e
BW		 3060 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
3061 * write would work. */
7e435ad2
VS		 3062 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3063 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
fbe5d36e
BW		 3064}
3065
ee0ce478
VS		 3066static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3067{
3068 uint64_t pat;
3069
3070 /*
3071 * Map WB on BDW to snooped on CHV.
3072 *
3073 * Only the snoop bit has meaning for CHV, the rest is
3074 * ignored.
3075 *
cf3d262e
VS		 3076 * The hardware will never snoop for certain types of accesses:
3077 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3078 * - PPGTT page tables
3079 * - some other special cycles
3080 *
3081 * As with BDW, we also need to consider the following for GT accesses:
3082 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3083 * so RTL will always use the value corresponding to
3084 * pat_sel = 000".
3085 * Which means we must set the snoop bit in PAT entry 0
3086 * in order to keep the global status page working.
ee0ce478
VS		 3087 */
3088 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3089 GEN8_PPAT(1, 0) |
3090 GEN8_PPAT(2, 0) |
3091 GEN8_PPAT(3, 0) |
3092 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3093 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3094 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3095 GEN8_PPAT(7, CHV_PPAT_SNOOP);
3096
7e435ad2
VS		 3097 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3098 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
ee0ce478
VS		 3099}
3100
d507d735 3101static int gen8_gmch_probe(struct i915_ggtt *ggtt)
63340133 3102{
d507d735 3103 struct drm_device *dev = ggtt->base.dev;
72e96d64 3104 struct drm_i915_private *dev_priv = to_i915(dev);
63340133
BW		 3105 u16 snb_gmch_ctl;
3106 int ret;
3107
3108 /* TODO: We're not aware of mappable constraints on gen8 yet */
d507d735
JL		 3109 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3110 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
63340133
BW		 3111
3112 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3113 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3114
3115 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3116
66375014 3117 if (INTEL_INFO(dev)->gen >= 9) {
d507d735
JL		 3118 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3119 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
66375014 3120 } else if (IS_CHERRYVIEW(dev)) {
d507d735
JL		 3121 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3122 ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3123 } else {
d507d735
JL		 3124 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3125 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
d7f25f23 3126 }
63340133 3127
d507d735 3128 ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
63340133 3129
5a4e33a3 3130 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
ee0ce478
VS		 3131 chv_setup_private_ppat(dev_priv);
3132 else
3133 bdw_setup_private_ppat(dev_priv);
fbe5d36e 3134
d507d735 3135 ret = ggtt_probe_common(dev, ggtt->size);
63340133 3136
d507d735
JL		 3137 ggtt->base.bind_vma = ggtt_bind_vma;
3138 ggtt->base.unbind_vma = ggtt_unbind_vma;
d6473f56 3139 ggtt->base.insert_page = gen8_ggtt_insert_page;
f7770bfd
CW		 3140 ggtt->base.clear_range = nop_clear_range;
3141 if (!USES_FULL_PPGTT(dev_priv))
3142 ggtt->base.clear_range = gen8_ggtt_clear_range;
3143
3144 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3145 if (IS_CHERRYVIEW(dev_priv))
3146 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3147
63340133
BW		 3148 return ret;
3149}
3150
d507d735 3151static int gen6_gmch_probe(struct i915_ggtt *ggtt)
e76e9aeb 3152{
d507d735 3153 struct drm_device *dev = ggtt->base.dev;
e76e9aeb 3154 u16 snb_gmch_ctl;
e76e9aeb
BW		 3155 int ret;
3156
d507d735
JL		 3157 ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3158 ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
41907ddc 3159
baa09f5f
BW		 3160 /* 64/512MB is the current min/max we actually know of, but this is just
3161 * a coarse sanity check.
e76e9aeb 3162 */
d507d735
JL		 3163 if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
3164 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
baa09f5f 3165 return -ENXIO;
e76e9aeb
BW		 3166 }
3167
e76e9aeb
BW		 3168 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3169 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
e76e9aeb 3170 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
e76e9aeb 3171
d507d735
JL		 3172 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3173 ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
3174 ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
e76e9aeb 3175
d507d735 3176 ret = ggtt_probe_common(dev, ggtt->size);
e76e9aeb 3177
d507d735 3178 ggtt->base.clear_range = gen6_ggtt_clear_range;
d6473f56 3179 ggtt->base.insert_page = gen6_ggtt_insert_page;
d507d735
JL		 3180 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3181 ggtt->base.bind_vma = ggtt_bind_vma;
3182 ggtt->base.unbind_vma = ggtt_unbind_vma;
7faf1ab2 3183
e76e9aeb
BW		 3184 return ret;
3185}
3186
853ba5d2 3187static void gen6_gmch_remove(struct i915_address_space *vm)
e76e9aeb 3188{
62106b4f 3189 struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
853ba5d2 3190
62106b4f 3191 iounmap(ggtt->gsm);
4ad2af1e 3192 free_scratch_page(vm->dev, vm->scratch_page);
644ec02b 3193}
baa09f5f 3194
d507d735 3195static int i915_gmch_probe(struct i915_ggtt *ggtt)
baa09f5f 3196{
d507d735 3197 struct drm_device *dev = ggtt->base.dev;
72e96d64 3198 struct drm_i915_private *dev_priv = to_i915(dev);
baa09f5f
BW		 3199 int ret;
3200
baa09f5f
BW		 3201 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3202 if (!ret) {
3203 DRM_ERROR("failed to set up gmch\n");
3204 return -EIO;
3205 }
3206
d507d735
JL		 3207 intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3208 &ggtt->mappable_base, &ggtt->mappable_end);
baa09f5f 3209
d507d735 3210 ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
d6473f56 3211 ggtt->base.insert_page = i915_ggtt_insert_page;
d507d735
JL		 3212 ggtt->base.insert_entries = i915_ggtt_insert_entries;
3213 ggtt->base.clear_range = i915_ggtt_clear_range;
3214 ggtt->base.bind_vma = ggtt_bind_vma;
3215 ggtt->base.unbind_vma = ggtt_unbind_vma;
baa09f5f 3216
d507d735 3217 if (unlikely(ggtt->do_idle_maps))
c0a7f818
CW		 3218 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3219
baa09f5f
BW		 3220 return 0;
3221}
3222
853ba5d2 3223static void i915_gmch_remove(struct i915_address_space *vm)
baa09f5f
BW		 3224{
3225 intel_gmch_remove();
3226}
3227
d85489d3
JL		 3228/**
3229 * i915_ggtt_init_hw - Initialize GGTT hardware
3230 * @dev: DRM device
3231 */
3232int i915_ggtt_init_hw(struct drm_device *dev)
baa09f5f 3233{
72e96d64 3234 struct drm_i915_private *dev_priv = to_i915(dev);
62106b4f 3235 struct i915_ggtt *ggtt = &dev_priv->ggtt;
baa09f5f
BW		 3236 int ret;
3237
baa09f5f 3238 if (INTEL_INFO(dev)->gen <= 5) {
62106b4f
JL		 3239 ggtt->probe = i915_gmch_probe;
3240 ggtt->base.cleanup = i915_gmch_remove;
63340133 3241 } else if (INTEL_INFO(dev)->gen < 8) {
62106b4f
JL		 3242 ggtt->probe = gen6_gmch_probe;
3243 ggtt->base.cleanup = gen6_gmch_remove;
3accaf7e
MK		 3244
3245 if (HAS_EDRAM(dev))
62106b4f 3246 ggtt->base.pte_encode = iris_pte_encode;
4d15c145 3247 else if (IS_HASWELL(dev))
62106b4f 3248 ggtt->base.pte_encode = hsw_pte_encode;
b2f21b4d 3249 else if (IS_VALLEYVIEW(dev))
62106b4f 3250 ggtt->base.pte_encode = byt_pte_encode;
350ec881 3251 else if (INTEL_INFO(dev)->gen >= 7)
62106b4f 3252 ggtt->base.pte_encode = ivb_pte_encode;
b2f21b4d 3253 else
62106b4f 3254 ggtt->base.pte_encode = snb_pte_encode;
63340133 3255 } else {
62106b4f
JL		 3256 ggtt->probe = gen8_gmch_probe;
3257 ggtt->base.cleanup = gen6_gmch_remove;
baa09f5f
BW		 3258 }
3259
62106b4f
JL		 3260 ggtt->base.dev = dev;
3261 ggtt->base.is_ggtt = true;
c114f76a 3262
d507d735 3263 ret = ggtt->probe(ggtt);
a54c0c27 3264 if (ret)
baa09f5f 3265 return ret;
baa09f5f 3266
c890e2d5
CW		 3267 if ((ggtt->base.total - 1) >> 32) {
3268 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3269 "of address space! Found %lldM!\n",
3270 ggtt->base.total >> 20);
3271 ggtt->base.total = 1ULL << 32;
3272 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3273 }
3274
a4eba47b
ID		 3275 /*
3276 * Initialise stolen early so that we may reserve preallocated
3277 * objects for the BIOS to KMS transition.
3278 */
3279 ret = i915_gem_init_stolen(dev);
3280 if (ret)
3281 goto out_gtt_cleanup;
3282
baa09f5f 3283 /* GMADR is the PCI mmio aperture into the global GTT. */
c44ef60e 3284 DRM_INFO("Memory usable by graphics device = %lluM\n",
62106b4f
JL		 3285 ggtt->base.total >> 20);
3286 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3287 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
5db6c735
DV		 3288#ifdef CONFIG_INTEL_IOMMU
3289 if (intel_iommu_gfx_mapped)
3290 DRM_INFO("VT-d active for gfx access\n");
3291#endif
baa09f5f
BW		 3292
3293 return 0;
a4eba47b
ID		 3294
3295out_gtt_cleanup:
72e96d64 3296 ggtt->base.cleanup(&ggtt->base);
a4eba47b
ID		 3297
3298 return ret;
baa09f5f 3299}
6f65e29a 3300
ac840ae5
VS		 3301int i915_ggtt_enable_hw(struct drm_device *dev)
3302{
3303 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3304 return -EIO;
3305
3306 return 0;
3307}
3308
fa42331b
DV		 3309void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3310{
72e96d64
JL		 3311 struct drm_i915_private *dev_priv = to_i915(dev);
3312 struct i915_ggtt *ggtt = &dev_priv->ggtt;
fa42331b 3313 struct drm_i915_gem_object *obj;
2c3d9984 3314 struct i915_vma *vma;
fa42331b 3315
dc97997a 3316 i915_check_and_clear_faults(dev_priv);
fa42331b
DV		 3317
3318 /* First fill our portion of the GTT with scratch pages */
72e96d64
JL		 3319 ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3320 true);
fa42331b 3321
2c3d9984 3322 /* Cache flush objects bound into GGTT and rebind them. */
fa42331b 3323 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1c7f4bca 3324 list_for_each_entry(vma, &obj->vma_list, obj_link) {
72e96d64 3325 if (vma->vm != &ggtt->base)
2c3d9984 3326 continue;
fa42331b 3327
2c3d9984
TU		 3328 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3329 PIN_UPDATE));
2c3d9984
TU		 3330 }
3331
975f7ff4
CW		 3332 if (obj->pin_display)
3333 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
2c3d9984 3334 }
fa42331b
DV		 3335
3336 if (INTEL_INFO(dev)->gen >= 8) {
3337 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3338 chv_setup_private_ppat(dev_priv);
3339 else
3340 bdw_setup_private_ppat(dev_priv);
3341
3342 return;
3343 }
3344
3345 if (USES_PPGTT(dev)) {
72e96d64
JL		 3346 struct i915_address_space *vm;
3347
fa42331b
DV		 3348 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3349 /* TODO: Perhaps it shouldn't be gen6 specific */
3350
e5716f55 3351 struct i915_hw_ppgtt *ppgtt;
fa42331b 3352
e5716f55 3353 if (vm->is_ggtt)
fa42331b 3354 ppgtt = dev_priv->mm.aliasing_ppgtt;
e5716f55
JL		 3355 else
3356 ppgtt = i915_vm_to_ppgtt(vm);
fa42331b
DV		 3357
3358 gen6_write_page_range(dev_priv, &ppgtt->pd,
3359 0, ppgtt->base.total);
3360 }
3361 }
3362
3363 i915_ggtt_flush(dev_priv);
3364}
3365
ec7adb6e
JL		 3366static struct i915_vma *
3367__i915_gem_vma_create(struct drm_i915_gem_object *obj,
3368 struct i915_address_space *vm,
3369 const struct i915_ggtt_view *ggtt_view)
6f65e29a 3370{
dabde5c7 3371 struct i915_vma *vma;
6f65e29a 3372
ec7adb6e
JL		 3373 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3374 return ERR_PTR(-EINVAL);
e20d2ab7
CW		 3375
3376 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
dabde5c7
DC		 3377 if (vma == NULL)
3378 return ERR_PTR(-ENOMEM);
ec7adb6e 3379
1c7f4bca
CW		 3380 INIT_LIST_HEAD(&vma->vm_link);
3381 INIT_LIST_HEAD(&vma->obj_link);
6f65e29a
BW		 3382 INIT_LIST_HEAD(&vma->exec_list);
3383 vma->vm = vm;
3384 vma->obj = obj;
596c5923 3385 vma->is_ggtt = i915_is_ggtt(vm);
6f65e29a 3386
777dc5bb 3387 if (i915_is_ggtt(vm))
ec7adb6e 3388 vma->ggtt_view = *ggtt_view;
596c5923
CW		 3389 else
3390 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
6f65e29a 3391
1c7f4bca 3392 list_add_tail(&vma->obj_link, &obj->vma_list);
6f65e29a
BW		 3393
3394 return vma;
3395}
3396
3397struct i915_vma *
ec7adb6e
JL		 3398i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3399 struct i915_address_space *vm)
3400{
3401 struct i915_vma *vma;
3402
3403 vma = i915_gem_obj_to_vma(obj, vm);
3404 if (!vma)
3405 vma = __i915_gem_vma_create(obj, vm,
3406 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3407
3408 return vma;
3409}
3410
3411struct i915_vma *
3412i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
fe14d5f4 3413 const struct i915_ggtt_view *view)
6f65e29a 3414{
72e96d64
JL		 3415 struct drm_device *dev = obj->base.dev;
3416 struct drm_i915_private *dev_priv = to_i915(dev);
3417 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ade7daa1 3418 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
ec7adb6e 3419
6f65e29a 3420 if (!vma)
72e96d64 3421 vma = __i915_gem_vma_create(obj, &ggtt->base, view);
6f65e29a
BW		 3422
3423 return vma;
ec7adb6e 3424
6f65e29a 3425}
fe14d5f4 3426
804beb4b 3427static struct scatterlist *
2d7f3bdb 3428rotate_pages(const dma_addr_t *in, unsigned int offset,
804beb4b 3429 unsigned int width, unsigned int height,
87130255 3430 unsigned int stride,
804beb4b 3431 struct sg_table *st, struct scatterlist *sg)
50470bb0
TU		 3432{
3433 unsigned int column, row;
3434 unsigned int src_idx;
50470bb0 3435
50470bb0 3436 for (column = 0; column < width; column++) {
87130255 3437 src_idx = stride * (height - 1) + column;
50470bb0
TU		 3438 for (row = 0; row < height; row++) {
3439 st->nents++;
3440 /* We don't need the pages, but need to initialize
3441 * the entries so the sg list can be happily traversed.
3442 * The only thing we need are DMA addresses.
3443 */
3444 sg_set_page(sg, NULL, PAGE_SIZE, 0);
804beb4b 3445 sg_dma_address(sg) = in[offset + src_idx];
50470bb0
TU		 3446 sg_dma_len(sg) = PAGE_SIZE;
3447 sg = sg_next(sg);
87130255 3448 src_idx -= stride;
50470bb0
TU		 3449 }
3450 }
804beb4b
TU		 3451
3452 return sg;
50470bb0
TU		 3453}
3454
3455static struct sg_table *
11d23e6f 3456intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
50470bb0
TU		 3457 struct drm_i915_gem_object *obj)
3458{
85d1225e 3459 const size_t n_pages = obj->base.size / PAGE_SIZE;
1663b9d6 3460 unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
89e3e142 3461 unsigned int size_pages_uv;
85d1225e
DG		 3462 struct sgt_iter sgt_iter;
3463 dma_addr_t dma_addr;
50470bb0
TU		 3464 unsigned long i;
3465 dma_addr_t *page_addr_list;
3466 struct sg_table *st;
89e3e142
TU		 3467 unsigned int uv_start_page;
3468 struct scatterlist *sg;
1d00dad5 3469 int ret = -ENOMEM;
50470bb0 3470
50470bb0 3471 /* Allocate a temporary list of source pages for random access. */
85d1225e 3472 page_addr_list = drm_malloc_gfp(n_pages,
f2a85e19
CW		 3473 sizeof(dma_addr_t),
3474 GFP_TEMPORARY);
50470bb0
TU		 3475 if (!page_addr_list)
3476 return ERR_PTR(ret);
3477
89e3e142
TU		 3478 /* Account for UV plane with NV12. */
3479 if (rot_info->pixel_format == DRM_FORMAT_NV12)
1663b9d6 3480 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
89e3e142
TU		 3481 else
3482 size_pages_uv = 0;
3483
50470bb0
TU		 3484 /* Allocate target SG list. */
3485 st = kmalloc(sizeof(*st), GFP_KERNEL);
3486 if (!st)
3487 goto err_st_alloc;
3488
89e3e142 3489 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
50470bb0
TU		 3490 if (ret)
3491 goto err_sg_alloc;
3492
3493 /* Populate source page list from the object. */
3494 i = 0;
85d1225e
DG		 3495 for_each_sgt_dma(dma_addr, sgt_iter, obj->pages)
3496 page_addr_list[i++] = dma_addr;
50470bb0 3497
85d1225e 3498 GEM_BUG_ON(i != n_pages);
11f20322
VS		 3499 st->nents = 0;
3500 sg = st->sgl;
3501
50470bb0 3502 /* Rotate the pages. */
89e3e142 3503 sg = rotate_pages(page_addr_list, 0,
1663b9d6
VS		 3504 rot_info->plane[0].width, rot_info->plane[0].height,
3505 rot_info->plane[0].width,
11f20322 3506 st, sg);
50470bb0 3507
89e3e142
TU		 3508 /* Append the UV plane if NV12. */
3509 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3510 uv_start_page = size_pages;
3511
3512 /* Check for tile-row un-alignment. */
3513 if (offset_in_page(rot_info->uv_offset))
3514 uv_start_page--;
3515
dedf278c
TU		 3516 rot_info->uv_start_page = uv_start_page;
3517
11f20322
VS		 3518 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3519 rot_info->plane[1].width, rot_info->plane[1].height,
3520 rot_info->plane[1].width,
3521 st, sg);
89e3e142
TU		 3522 }
3523
1663b9d6
VS		 3524 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3525 obj->base.size, rot_info->plane[0].width,
3526 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3527 size_pages);
50470bb0
TU		 3528
3529 drm_free_large(page_addr_list);
3530
3531 return st;
3532
3533err_sg_alloc:
3534 kfree(st);
3535err_st_alloc:
3536 drm_free_large(page_addr_list);
3537
1663b9d6
VS		 3538 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3539 obj->base.size, ret, rot_info->plane[0].width,
3540 rot_info->plane[0].height, size_pages + size_pages_uv,
89e3e142 3541 size_pages);
50470bb0
TU		 3542 return ERR_PTR(ret);
3543}
ec7adb6e 3544
8bd7ef16
JL		 3545static struct sg_table *
3546intel_partial_pages(const struct i915_ggtt_view *view,
3547 struct drm_i915_gem_object *obj)
3548{
3549 struct sg_table *st;
3550 struct scatterlist *sg;
3551 struct sg_page_iter obj_sg_iter;
3552 int ret = -ENOMEM;
3553
3554 st = kmalloc(sizeof(*st), GFP_KERNEL);
3555 if (!st)
3556 goto err_st_alloc;
3557
3558 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3559 if (ret)
3560 goto err_sg_alloc;
3561
3562 sg = st->sgl;
3563 st->nents = 0;
3564 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3565 view->params.partial.offset)
3566 {
3567 if (st->nents >= view->params.partial.size)
3568 break;
3569
3570 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3571 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3572 sg_dma_len(sg) = PAGE_SIZE;
3573
3574 sg = sg_next(sg);
3575 st->nents++;
3576 }
3577
3578 return st;
3579
3580err_sg_alloc:
3581 kfree(st);
3582err_st_alloc:
3583 return ERR_PTR(ret);
3584}
3585
70b9f6f8 3586static int
50470bb0 3587i915_get_ggtt_vma_pages(struct i915_vma *vma)
fe14d5f4 3588{
50470bb0
TU		 3589 int ret = 0;
3590
fe14d5f4
TU		 3591 if (vma->ggtt_view.pages)
3592 return 0;
3593
3594 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3595 vma->ggtt_view.pages = vma->obj->pages;
50470bb0
TU		 3596 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3597 vma->ggtt_view.pages =
11d23e6f 3598 intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
8bd7ef16
JL		 3599 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3600 vma->ggtt_view.pages =
3601 intel_partial_pages(&vma->ggtt_view, vma->obj);
fe14d5f4
TU		 3602 else
3603 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3604 vma->ggtt_view.type);
3605
3606 if (!vma->ggtt_view.pages) {
ec7adb6e 3607 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
fe14d5f4 3608 vma->ggtt_view.type);
50470bb0
TU		 3609 ret = -EINVAL;
3610 } else if (IS_ERR(vma->ggtt_view.pages)) {
3611 ret = PTR_ERR(vma->ggtt_view.pages);
3612 vma->ggtt_view.pages = NULL;
3613 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3614 vma->ggtt_view.type, ret);
fe14d5f4
TU		 3615 }
3616
50470bb0 3617 return ret;
fe14d5f4
TU		 3618}
3619
3620/**
3621 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3622 * @vma: VMA to map
3623 * @cache_level: mapping cache level
3624 * @flags: flags like global or local mapping
3625 *
3626 * DMA addresses are taken from the scatter-gather table of this object (or of
3627 * this VMA in case of non-default GGTT views) and PTE entries set up.
3628 * Note that DMA addresses are also the only part of the SG table we care about.
3629 */
3630int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3631 u32 flags)
3632{
75d04a37
MK		 3633 int ret;
3634 u32 bind_flags;
1d335d1b 3635
75d04a37
MK		 3636 if (WARN_ON(flags == 0))
3637 return -EINVAL;
1d335d1b 3638
75d04a37 3639 bind_flags = 0;
0875546c
DV		 3640 if (flags & PIN_GLOBAL)
3641 bind_flags |= GLOBAL_BIND;
3642 if (flags & PIN_USER)
3643 bind_flags |= LOCAL_BIND;
3644
3645 if (flags & PIN_UPDATE)
3646 bind_flags |= vma->bound;
3647 else
3648 bind_flags &= ~vma->bound;
3649
75d04a37
MK		 3650 if (bind_flags == 0)
3651 return 0;
3652
3653 if (vma->bound == 0 && vma->vm->allocate_va_range) {
b2dd4511
MK		 3654 /* XXX: i915_vma_pin() will fix this +- hack */
3655 vma->pin_count++;
596c5923 3656 trace_i915_va_alloc(vma);
75d04a37
MK		 3657 ret = vma->vm->allocate_va_range(vma->vm,
3658 vma->node.start,
3659 vma->node.size);
b2dd4511 3660 vma->pin_count--;
75d04a37
MK		 3661 if (ret)
3662 return ret;
3663 }
3664
3665 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
70b9f6f8
DV		 3666 if (ret)
3667 return ret;
0875546c
DV		 3668
3669 vma->bound |= bind_flags;
fe14d5f4
TU		 3670
3671 return 0;
3672}
91e6711e
JL		 3673
3674/**
3675 * i915_ggtt_view_size - Get the size of a GGTT view.
3676 * @obj: Object the view is of.
3677 * @view: The view in question.
3678 *
3679 * @return The size of the GGTT view in bytes.
3680 */
3681size_t
3682i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3683 const struct i915_ggtt_view *view)
3684{
9e759ff1 3685 if (view->type == I915_GGTT_VIEW_NORMAL) {
91e6711e 3686 return obj->base.size;
9e759ff1 3687 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
1663b9d6 3688 return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
8bd7ef16
JL		 3689 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3690 return view->params.partial.size << PAGE_SHIFT;
91e6711e
JL		 3691 } else {
3692 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3693 return obj->base.size;
3694 }
3695}
8ef8561f
CW		 3696
3697void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
3698{
3699 void __iomem *ptr;
3700
3701 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3702 if (WARN_ON(!vma->obj->map_and_fenceable))
3703 return ERR_PTR(-ENODEV);
3704
3705 GEM_BUG_ON(!vma->is_ggtt);
3706 GEM_BUG_ON((vma->bound & GLOBAL_BIND) == 0);
3707
3708 ptr = vma->iomap;
3709 if (ptr == NULL) {
3710 ptr = io_mapping_map_wc(i915_vm_to_ggtt(vma->vm)->mappable,
3711 vma->node.start,
3712 vma->node.size);
3713 if (ptr == NULL)
3714 return ERR_PTR(-ENOMEM);
3715
3716 vma->iomap = ptr;
3717 }
3718
3719 vma->pin_count++;
3720 return ptr;
3721}
Linux kernel - Deliverables
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