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0260c420 BW |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Please try to maintain the following order within this file unless it makes | |
24 | * sense to do otherwise. From top to bottom: | |
25 | * 1. typedefs | |
26 | * 2. #defines, and macros | |
27 | * 3. structure definitions | |
28 | * 4. function prototypes | |
29 | * | |
30 | * Within each section, please try to order by generation in ascending order, | |
31 | * from top to bottom (ie. gen6 on the top, gen8 on the bottom). | |
32 | */ | |
33 | ||
34 | #ifndef __I915_GEM_GTT_H__ | |
35 | #define __I915_GEM_GTT_H__ | |
36 | ||
4d884705 DV |
37 | struct drm_i915_file_private; |
38 | ||
0260c420 BW |
39 | typedef uint32_t gen6_gtt_pte_t; |
40 | typedef uint64_t gen8_gtt_pte_t; | |
41 | typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; | |
42 | ||
43 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) | |
44 | ||
45 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
46 | /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ | |
47 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
48 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
49 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
50 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
51 | #define GEN6_PTE_UNCACHED (1 << 1) | |
52 | #define GEN6_PTE_VALID (1 << 0) | |
53 | ||
54 | #define GEN6_PPGTT_PD_ENTRIES 512 | |
55 | #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) | |
56 | #define GEN6_PD_ALIGN (PAGE_SIZE * 16) | |
57 | #define GEN6_PDE_VALID (1 << 0) | |
58 | ||
59 | #define GEN7_PTE_CACHE_L3_LLC (3 << 1) | |
60 | ||
61 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
62 | #define BYT_PTE_WRITEABLE (1 << 1) | |
63 | ||
64 | /* Cacheability Control is a 4-bit value. The low three bits are stored in bits | |
65 | * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
66 | */ | |
67 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
68 | (((bits) & 0x8) << (11 - 3))) | |
69 | #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) | |
70 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
71 | #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) | |
72 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) | |
73 | #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) | |
74 | #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) | |
75 | #define HSW_PTE_UNCACHED (0) | |
76 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) | |
77 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) | |
78 | ||
79 | /* GEN8 legacy style address is defined as a 3 level page table: | |
80 | * 31:30 | 29:21 | 20:12 | 11:0 | |
81 | * PDPE | PDE | PTE | offset | |
82 | * The difference as compared to normal x86 3 level page table is the PDPEs are | |
83 | * programmed via register. | |
84 | */ | |
85 | #define GEN8_PDPE_SHIFT 30 | |
86 | #define GEN8_PDPE_MASK 0x3 | |
87 | #define GEN8_PDE_SHIFT 21 | |
88 | #define GEN8_PDE_MASK 0x1ff | |
89 | #define GEN8_PTE_SHIFT 12 | |
90 | #define GEN8_PTE_MASK 0x1ff | |
76643600 | 91 | #define GEN8_LEGACY_PDPES 4 |
0260c420 BW |
92 | #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) |
93 | #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) | |
94 | ||
95 | #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) | |
96 | #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ | |
97 | #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ | |
98 | #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ | |
99 | ||
ee0ce478 | 100 | #define CHV_PPAT_SNOOP (1<<6) |
0260c420 BW |
101 | #define GEN8_PPAT_AGE(x) (x<<4) |
102 | #define GEN8_PPAT_LLCeLLC (3<<2) | |
103 | #define GEN8_PPAT_LLCELLC (2<<2) | |
104 | #define GEN8_PPAT_LLC (1<<2) | |
105 | #define GEN8_PPAT_WB (3<<0) | |
106 | #define GEN8_PPAT_WT (2<<0) | |
107 | #define GEN8_PPAT_WC (1<<0) | |
108 | #define GEN8_PPAT_UC (0<<0) | |
109 | #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) | |
110 | #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) | |
111 | ||
fe14d5f4 TU |
112 | enum i915_ggtt_view_type { |
113 | I915_GGTT_VIEW_NORMAL = 0, | |
114 | }; | |
115 | ||
116 | struct i915_ggtt_view { | |
117 | enum i915_ggtt_view_type type; | |
118 | ||
119 | struct sg_table *pages; | |
120 | }; | |
121 | ||
122 | extern const struct i915_ggtt_view i915_ggtt_view_normal; | |
123 | ||
0260c420 | 124 | enum i915_cache_level; |
fe14d5f4 | 125 | |
0260c420 BW |
126 | /** |
127 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
128 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
129 | * object into/from the address space. | |
130 | * | |
131 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
132 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
133 | */ | |
134 | struct i915_vma { | |
135 | struct drm_mm_node node; | |
136 | struct drm_i915_gem_object *obj; | |
137 | struct i915_address_space *vm; | |
138 | ||
aff43766 TU |
139 | /** Flags and address space this VMA is bound to */ |
140 | #define GLOBAL_BIND (1<<0) | |
141 | #define LOCAL_BIND (1<<1) | |
142 | #define PTE_READ_ONLY (1<<2) | |
143 | unsigned int bound : 4; | |
144 | ||
fe14d5f4 TU |
145 | /** |
146 | * Support different GGTT views into the same object. | |
147 | * This means there can be multiple VMA mappings per object and per VM. | |
148 | * i915_ggtt_view_type is used to distinguish between those entries. | |
149 | * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also | |
150 | * assumed in GEM functions which take no ggtt view parameter. | |
151 | */ | |
152 | struct i915_ggtt_view ggtt_view; | |
153 | ||
0260c420 BW |
154 | /** This object's place on the active/inactive lists */ |
155 | struct list_head mm_list; | |
156 | ||
157 | struct list_head vma_link; /* Link in the object's VMA list */ | |
158 | ||
159 | /** This vma's place in the batchbuffer or on the eviction list */ | |
160 | struct list_head exec_list; | |
161 | ||
162 | /** | |
163 | * Used for performing relocations during execbuffer insertion. | |
164 | */ | |
165 | struct hlist_node exec_node; | |
166 | unsigned long exec_handle; | |
167 | struct drm_i915_gem_exec_object2 *exec_entry; | |
168 | ||
169 | /** | |
170 | * How many users have pinned this object in GTT space. The following | |
4feb7659 DV |
171 | * users can each hold at most one reference: pwrite/pread, execbuffer |
172 | * (objects are not allowed multiple times for the same batchbuffer), | |
173 | * and the framebuffer code. When switching/pageflipping, the | |
174 | * framebuffer code has at most two buffers pinned per crtc. | |
0260c420 BW |
175 | * |
176 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
177 | * bits with absolutely no headroom. So use 4 bits. */ | |
178 | unsigned int pin_count:4; | |
179 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf | |
180 | ||
181 | /** Unmap an object from an address space. This usually consists of | |
182 | * setting the valid PTE entries to a reserved scratch page. */ | |
183 | void (*unbind_vma)(struct i915_vma *vma); | |
184 | /* Map an object into an address space with the given cache flags. */ | |
0260c420 BW |
185 | void (*bind_vma)(struct i915_vma *vma, |
186 | enum i915_cache_level cache_level, | |
187 | u32 flags); | |
188 | }; | |
189 | ||
d7b3de91 BW |
190 | struct i915_page_table_entry { |
191 | struct page *page; | |
192 | }; | |
193 | ||
194 | struct i915_page_directory_entry { | |
195 | struct page *page; /* NULL for GEN6-GEN7 */ | |
196 | struct i915_page_table_entry *page_table; | |
197 | }; | |
198 | ||
199 | struct i915_page_directory_pointer_entry { | |
200 | /* struct page *page; */ | |
201 | struct i915_page_directory_entry page_directory[GEN8_LEGACY_PDPES]; | |
202 | }; | |
203 | ||
0260c420 BW |
204 | struct i915_address_space { |
205 | struct drm_mm mm; | |
206 | struct drm_device *dev; | |
207 | struct list_head global_link; | |
208 | unsigned long start; /* Start offset always 0 for dri2 */ | |
209 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
210 | ||
211 | struct { | |
212 | dma_addr_t addr; | |
213 | struct page *page; | |
214 | } scratch; | |
215 | ||
216 | /** | |
217 | * List of objects currently involved in rendering. | |
218 | * | |
219 | * Includes buffers having the contents of their GPU caches | |
97b2a6a1 | 220 | * flushed, not necessarily primitives. last_read_req |
0260c420 BW |
221 | * represents when the rendering involved will be completed. |
222 | * | |
223 | * A reference is held on the buffer while on this list. | |
224 | */ | |
225 | struct list_head active_list; | |
226 | ||
227 | /** | |
228 | * LRU list of objects which are not in the ringbuffer and | |
229 | * are ready to unbind, but are still in the GTT. | |
230 | * | |
97b2a6a1 | 231 | * last_read_req is NULL while an object is in this list. |
0260c420 BW |
232 | * |
233 | * A reference is not held on the buffer while on this list, | |
234 | * as merely being GTT-bound shouldn't prevent its being | |
235 | * freed, and we'll pull it off the list in the free path. | |
236 | */ | |
237 | struct list_head inactive_list; | |
238 | ||
239 | /* FIXME: Need a more generic return type */ | |
240 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, | |
241 | enum i915_cache_level level, | |
24f3a8cf | 242 | bool valid, u32 flags); /* Create a valid PTE */ |
0260c420 BW |
243 | void (*clear_range)(struct i915_address_space *vm, |
244 | uint64_t start, | |
245 | uint64_t length, | |
246 | bool use_scratch); | |
247 | void (*insert_entries)(struct i915_address_space *vm, | |
248 | struct sg_table *st, | |
249 | uint64_t start, | |
24f3a8cf | 250 | enum i915_cache_level cache_level, u32 flags); |
0260c420 BW |
251 | void (*cleanup)(struct i915_address_space *vm); |
252 | }; | |
253 | ||
254 | /* The Graphics Translation Table is the way in which GEN hardware translates a | |
255 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
256 | * collateral associated with any va->pa translations GEN hardware also has a | |
257 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
258 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
259 | * the spec. | |
260 | */ | |
261 | struct i915_gtt { | |
262 | struct i915_address_space base; | |
263 | size_t stolen_size; /* Total size of stolen memory */ | |
264 | ||
265 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
266 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
267 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
268 | ||
269 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
270 | void __iomem *gsm; | |
271 | ||
272 | bool do_idle_maps; | |
273 | ||
274 | int mtrr; | |
275 | ||
276 | /* global gtt ops */ | |
277 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, | |
278 | size_t *stolen, phys_addr_t *mappable_base, | |
279 | unsigned long *mappable_end); | |
280 | }; | |
281 | ||
282 | struct i915_hw_ppgtt { | |
283 | struct i915_address_space base; | |
284 | struct kref ref; | |
285 | struct drm_mm_node node; | |
286 | unsigned num_pd_entries; | |
287 | unsigned num_pd_pages; /* gen8+ */ | |
0260c420 BW |
288 | union { |
289 | uint32_t pd_offset; | |
76643600 | 290 | dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPES]; |
0260c420 BW |
291 | }; |
292 | union { | |
293 | dma_addr_t *pt_dma_addr; | |
17d5538d | 294 | dma_addr_t *gen8_pt_dma_addr[GEN8_LEGACY_PDPES]; |
0260c420 | 295 | }; |
d7b3de91 BW |
296 | union { |
297 | struct i915_page_directory_pointer_entry pdp; | |
298 | struct i915_page_directory_entry pd; | |
299 | }; | |
0260c420 | 300 | |
4d884705 | 301 | struct drm_i915_file_private *file_priv; |
0260c420 BW |
302 | |
303 | int (*enable)(struct i915_hw_ppgtt *ppgtt); | |
304 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, | |
6689c167 | 305 | struct intel_engine_cs *ring); |
0260c420 BW |
306 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
307 | }; | |
308 | ||
309 | int i915_gem_gtt_init(struct drm_device *dev); | |
310 | void i915_gem_init_global_gtt(struct drm_device *dev); | |
90d0a0e8 | 311 | void i915_global_gtt_cleanup(struct drm_device *dev); |
0260c420 | 312 | |
ee960be7 DV |
313 | |
314 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); | |
82460d97 | 315 | int i915_ppgtt_init_hw(struct drm_device *dev); |
ee960be7 | 316 | void i915_ppgtt_release(struct kref *kref); |
4d884705 DV |
317 | struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, |
318 | struct drm_i915_file_private *fpriv); | |
ee960be7 DV |
319 | static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) |
320 | { | |
321 | if (ppgtt) | |
322 | kref_get(&ppgtt->ref); | |
323 | } | |
324 | static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) | |
325 | { | |
326 | if (ppgtt) | |
327 | kref_put(&ppgtt->ref, i915_ppgtt_release); | |
328 | } | |
0260c420 BW |
329 | |
330 | void i915_check_and_clear_faults(struct drm_device *dev); | |
331 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
332 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
333 | ||
334 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); | |
335 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); | |
336 | ||
337 | #endif |