[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include <linux/string.h>
#include <linux/bitops.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"

/**
 * DOC: buffer object tiling
 *
 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
 * declare fence register requirements.
 *
 * In principle GEM doesn't care at all about the internal data layout of an
 * object, and hence it also doesn't care about tiling or swizzling. There's two
 * exceptions:
 *
 * - For X and Y tiling the hardware provides detilers for CPU access, so called
 *   fences. Since there's only a limited amount of them the kernel must manage
 *   these, and therefore userspace must tell the kernel the object tiling if it
 *   wants to use fences for detiling.
 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
 *   depends upon the physical page frame number. When swapping such objects the
 *   page frame number might change and the kernel must be able to fix this up
 *   and hence now the tiling. Note that on a subset of platforms with
 *   asymmetric memory channel population the swizzling pattern changes in an
 *   unknown way, and for those the kernel simply forbids swapping completely.
 *
 * Since neither of this applies for new tiling layouts on modern platforms like
 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
 * Anything else can be handled in userspace entirely without the kernel's
 * invovlement.
 */

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (IS_GEN2(dev) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	/* i965+ stores the end address of the gtt mapping in the fence
	 * reg, so dont bother to check the size */
	if (INTEL_INFO(dev)->gen >= 7) {
		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (INTEL_INFO(dev)->gen >= 4) {
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;

		if (IS_GEN3(dev)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}

	if (stride < tile_width)
		return false;

	/* 965+ just needs multiples of tile width */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride & (stride - 1))
		return false;

	return true;
}

/* Is the current GTT allocation valid for the change in tiling? */
static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
	u32 size;

	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen >= 4)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen == 3) {
		if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
			return false;
	} else {
		if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
			return false;
	}

	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
	if (i915_gem_obj_ggtt_size(obj) != size)
		return false;

	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
		return false;

	return true;
}

/**
 * i915_gem_set_tiling - IOCTL handler to set tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret = 0;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	if (!i915_tiling_ok(dev,
			    args->stride, obj->base.size, args->tiling_mode)) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EINVAL;
	}

	intel_runtime_pm_get(dev_priv);

	mutex_lock(&dev->struct_mutex);
	if (obj->pin_display || obj->framebuffer_references) {
		ret = -EBUSY;
		goto err;
	}

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}

	if (args->tiling_mode != obj->tiling_mode ||
	    args->stride != obj->stride) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is updated before
		 * the next fenced (either through the GTT or by the BLT unit
		 * on older GPUs) access.
		 *
		 * After updating the tiling parameters, we then flag whether
		 * we need to update an associated fence register. Note this
		 * has to also include the unfenced register the GPU uses
		 * whilst executing a fenced command for an untiled object.
		 */
		if (obj->map_and_fenceable &&
		    !i915_gem_object_fence_ok(obj, args->tiling_mode))
			ret = i915_gem_object_ggtt_unbind(obj);

		if (ret == 0) {
			if (obj->pages &&
			    obj->madv == I915_MADV_WILLNEED &&
			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
				if (args->tiling_mode == I915_TILING_NONE)
					i915_gem_object_unpin_pages(obj);
				if (obj->tiling_mode == I915_TILING_NONE)
					i915_gem_object_pin_pages(obj);
			}

			obj->fence_dirty =
				obj->last_fenced_req ||
				obj->fence_reg != I915_FENCE_REG_NONE;

			obj->tiling_mode = args->tiling_mode;
			obj->stride = args->stride;

			/* Force the fence to be reacquired for GTT access */
			i915_gem_release_mmap(obj);
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = obj->stride;
	args->tiling_mode = obj->tiling_mode;

	/* Try to preallocate memory required to save swizzling on put-pages */
	if (i915_gem_object_needs_bit17_swizzle(obj)) {
		if (obj->bit_17 == NULL) {
			obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
					      sizeof(long), GFP_KERNEL);
		}
	} else {
		kfree(obj->bit_17);
		obj->bit_17 = NULL;
	}

err:
	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	intel_runtime_pm_put(dev_priv);

	return ret;
}

/**
 * i915_gem_get_tiling - IOCTL handler to get tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	mutex_lock(&dev->struct_mutex);

	args->tiling_mode = obj->tiling_mode;
	switch (obj->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	else
		args->phys_swizzle_mode = args->swizzle_mode;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
760285e7 DH	28	#include <linux/string.h>
	29	#include <linux/bitops.h>
	30	#include <drm/drmP.h>
	31	#include <drm/i915_drm.h>
673a394b EA	32	#include "i915_drv.h"
673a394b EA	33
3271dca4 DV	34	/**
3271dca4 DV	35	* DOC: buffer object tiling
673a394b	36	*
3271dca4 DV	37	* i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
3271dca4 DV	38	* declare fence register requirements.
673a394b	39	*
3271dca4 DV	40	* In principle GEM doesn't care at all about the internal data layout of an
	41	* object, and hence it also doesn't care about tiling or swizzling. There's two
	42	* exceptions:
673a394b	43	*
3271dca4 DV	44	* - For X and Y tiling the hardware provides detilers for CPU access, so called
	45	* fences. Since there's only a limited amount of them the kernel must manage
	46	* these, and therefore userspace must tell the kernel the object tiling if it
	47	* wants to use fences for detiling.
	48	* - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
	49	* depends upon the physical page frame number. When swapping such objects the
	50	* page frame number might change and the kernel must be able to fix this up
	51	* and hence now the tiling. Note that on a subset of platforms with
	52	* asymmetric memory channel population the swizzling pattern changes in an
	53	* unknown way, and for those the kernel simply forbids swapping completely.
673a394b	54	*
3271dca4 DV	55	* Since neither of this applies for new tiling layouts on modern platforms like
	56	* W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
	57	* Anything else can be handled in userspace entirely without the kernel's
	58	* invovlement.
673a394b EA	59	*/
673a394b EA	60
0f973f27	61	/* Check pitch constriants for all chips & tiling formats */
a00b10c3	62	static bool
0f973f27 JB	63	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
0f973f27 JB	64	{
0ee537ab	65	int tile_width;
0f973f27 JB	66
	67	/* Linear is always fine */
	68	if (tiling_mode == I915_TILING_NONE)
	69	return true;
	70
a6c45cf0	71	if (IS_GEN2(dev) \|\|
e76a16de	72	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
0f973f27 JB	73	tile_width = 128;
	74	else
	75	tile_width = 512;
	76
8d7773a3	77	/* check maximum stride & object size */
3a062478 VS	78	/* i965+ stores the end address of the gtt mapping in the fence
	79	* reg, so dont bother to check the size */
	80	if (INTEL_INFO(dev)->gen >= 7) {
	81	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
	82	return false;
	83	} else if (INTEL_INFO(dev)->gen >= 4) {
8d7773a3 DV	84	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
8d7773a3 DV	85	return false;
a6c45cf0	86	} else {
c36a2a6d	87	if (stride > 8192)
8d7773a3	88	return false;
e76a16de	89
c36a2a6d DV	90	if (IS_GEN3(dev)) {
	91	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
	92	return false;
	93	} else {
	94	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
	95	return false;
	96	}
8d7773a3 DV	97	}
8d7773a3 DV	98
fe48d8de VS	99	if (stride < tile_width)
	100	return false;
	101
0f973f27	102	/* 965+ just needs multiples of tile width */
a6c45cf0	103	if (INTEL_INFO(dev)->gen >= 4) {
0f973f27 JB	104	if (stride & (tile_width - 1))
	105	return false;
	106	return true;
	107	}
	108
	109	/* Pre-965 needs power of two tile widths */
0f973f27 JB	110	if (stride & (stride - 1))
	111	return false;
	112
0f973f27 JB	113	return true;
	114	}
	115
a00b10c3 CW	116	/* Is the current GTT allocation valid for the change in tiling? */
a00b10c3 CW	117	static bool
05394f39	118	i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
52dc7d32	119	{
a00b10c3	120	u32 size;
52dc7d32 CW	121
	122	if (tiling_mode == I915_TILING_NONE)
	123	return true;
	124
05394f39	125	if (INTEL_INFO(obj->base.dev)->gen >= 4)
a6c45cf0 CW	126	return true;
a6c45cf0 CW	127
05394f39	128	if (INTEL_INFO(obj->base.dev)->gen == 3) {
f343c5f6	129	if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
df153158 CW	130	return false;
df153158 CW	131	} else {
f343c5f6	132	if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
df153158 CW	133	return false;
	134	}
	135
0fa87796	136	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
f343c5f6	137	if (i915_gem_obj_ggtt_size(obj) != size)
a6c45cf0 CW	138	return false;
a6c45cf0 CW	139
f343c5f6	140	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
df153158	141	return false;
52dc7d32 CW	142
	143	return true;
	144	}
	145
673a394b	146	/**
3271dca4 DV	147	* i915_gem_set_tiling - IOCTL handler to set tiling mode
	148	* @dev: DRM device
	149	* @data: data pointer for the ioctl
	150	* @file: DRM file for the ioctl call
	151	*
673a394b EA	152	* Sets the tiling mode of an object, returning the required swizzling of
673a394b EA	153	* bit 6 of addresses in the object.
3271dca4 DV	154	*
	155	* Called by the user via ioctl.
	156	*
	157	* Returns:
	158	* Zero on success, negative errno on failure.
673a394b EA	159	*/
	160	int
	161	i915_gem_set_tiling(struct drm_device dev, void data,
05394f39	162	struct drm_file *file)
673a394b EA	163	{
673a394b EA	164	struct drm_i915_gem_set_tiling *args = data;
50227e1c	165	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	166	struct drm_i915_gem_object *obj;
47ae63e0	167	int ret = 0;
673a394b	168
05394f39	169	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	170	if (&obj->base == NULL)
bf79cb91	171	return -ENOENT;
673a394b	172
05394f39 CW	173	if (!i915_tiling_ok(dev,
	174	args->stride, obj->base.size, args->tiling_mode)) {
	175	drm_gem_object_unreference_unlocked(&obj->base);
0f973f27	176	return -EINVAL;
72daad40	177	}
0f973f27	178
e64e6bd0 ID	179	intel_runtime_pm_get(dev_priv);
e64e6bd0 ID	180
6c31a614	181	mutex_lock(&dev->struct_mutex);
1f30a614	182	if (obj->pin_display \|\| obj->framebuffer_references) {
6c31a614 CW	183	ret = -EBUSY;
6c31a614 CW	184	goto err;
31770bd4 DV	185	}
31770bd4 DV	186
673a394b	187	if (args->tiling_mode == I915_TILING_NONE) {
673a394b	188	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	189	args->stride = 0;
673a394b EA	190	} else {
	191	if (args->tiling_mode == I915_TILING_X)
	192	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	193	else
	194	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	195
	196	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	197	* from aborting the application on sw fallbacks to bit 17,
	198	* and we use the pread/pwrite bit17 paths to swizzle for it.
	199	* If there was a user that was relying on the swizzle
	200	* information for drm_intel_bo_map()ed reads/writes this would
	201	* break it, but we don't have any of those.
	202	*/
	203	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	204	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	205	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	206	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	207
673a394b EA	208	/* If we can't handle the swizzling, make it untiled. */
	209	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	210	args->tiling_mode = I915_TILING_NONE;
	211	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	212	args->stride = 0;
673a394b EA	213	}
673a394b EA	214	}
0f973f27	215
05394f39 CW	216	if (args->tiling_mode != obj->tiling_mode \|\|
05394f39 CW	217	args->stride != obj->stride) {
52dc7d32 CW	218	/* We need to rebind the object if its current allocation
	219	* no longer meets the alignment restrictions for its new
	220	* tiling mode. Otherwise we can just leave it alone, but
1869b620 CW	221	* need to ensure that any fence register is updated before
	222	* the next fenced (either through the GTT or by the BLT unit
	223	* on older GPUs) access.
5d82e3e6 CW	224	*
	225	* After updating the tiling parameters, we then flag whether
	226	* we need to update an associated fence register. Note this
	227	* has to also include the unfenced register the GPU uses
	228	* whilst executing a fenced command for an untiled object.
0f973f27	229	*/
e9d784d5 CW	230	if (obj->map_and_fenceable &&
	231	!i915_gem_object_fence_ok(obj, args->tiling_mode))
	232	ret = i915_gem_object_ggtt_unbind(obj);
467cffba CW	233
467cffba CW	234	if (ret == 0) {
656bfa3a DV	235	if (obj->pages &&
	236	obj->madv == I915_MADV_WILLNEED &&
	237	dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
	238	if (args->tiling_mode == I915_TILING_NONE)
	239	i915_gem_object_unpin_pages(obj);
	240	if (obj->tiling_mode == I915_TILING_NONE)
	241	i915_gem_object_pin_pages(obj);
	242	}
	243
5d82e3e6	244	obj->fence_dirty =
97b2a6a1	245	obj->last_fenced_req \|\|
5d82e3e6 CW	246	obj->fence_reg != I915_FENCE_REG_NONE;
5d82e3e6 CW	247
467cffba CW	248	obj->tiling_mode = args->tiling_mode;
467cffba CW	249	obj->stride = args->stride;
1869b620 CW	250
	251	/* Force the fence to be reacquired for GTT access */
	252	i915_gem_release_mmap(obj);
467cffba	253	}
0f973f27	254	}
467cffba CW	255	/* we have to maintain this existing ABI... */
	256	args->stride = obj->stride;
	257	args->tiling_mode = obj->tiling_mode;
e9b73c67 CW	258
	259	/* Try to preallocate memory required to save swizzling on put-pages */
	260	if (i915_gem_object_needs_bit17_swizzle(obj)) {
	261	if (obj->bit_17 == NULL) {
a1e22653	262	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
e9b73c67 CW	263	sizeof(long), GFP_KERNEL);
	264	}
	265	} else {
	266	kfree(obj->bit_17);
	267	obj->bit_17 = NULL;
	268	}
	269
6c31a614	270	err:
05394f39	271	drm_gem_object_unreference(&obj->base);
d6873102	272	mutex_unlock(&dev->struct_mutex);
673a394b	273
e64e6bd0 ID	274	intel_runtime_pm_put(dev_priv);
e64e6bd0 ID	275
467cffba	276	return ret;
673a394b EA	277	}
	278
	279	/**
3271dca4 DV	280	* i915_gem_get_tiling - IOCTL handler to get tiling mode
	281	* @dev: DRM device
	282	* @data: data pointer for the ioctl
	283	* @file: DRM file for the ioctl call
	284	*
673a394b	285	* Returns the current tiling mode and required bit 6 swizzling for the object.
3271dca4 DV	286	*
	287	* Called by the user via ioctl.
	288	*
	289	* Returns:
	290	* Zero on success, negative errno on failure.
673a394b EA	291	*/
	292	int
	293	i915_gem_get_tiling(struct drm_device dev, void data,
05394f39	294	struct drm_file *file)
673a394b EA	295	{
673a394b EA	296	struct drm_i915_gem_get_tiling *args = data;
50227e1c	297	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	298	struct drm_i915_gem_object *obj;
673a394b	299
05394f39	300	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	301	if (&obj->base == NULL)
bf79cb91	302	return -ENOENT;
673a394b EA	303
	304	mutex_lock(&dev->struct_mutex);
	305
05394f39 CW	306	args->tiling_mode = obj->tiling_mode;
05394f39 CW	307	switch (obj->tiling_mode) {
673a394b EA	308	case I915_TILING_X:
	309	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	310	break;
	311	case I915_TILING_Y:
	312	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	313	break;
	314	case I915_TILING_NONE:
	315	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	316	break;
	317	default:
	318	DRM_ERROR("unknown tiling mode\n");
	319	}
	320
280b713b	321	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
5eb3e5a5 CW	322	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
	323	args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	324	else
	325	args->phys_swizzle_mode = args->swizzle_mode;
280b713b EA	326	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	327	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	328	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	329	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	330
05394f39	331	drm_gem_object_unreference(&obj->base);
d6873102	332	mutex_unlock(&dev->struct_mutex);
673a394b EA	333
	334	return 0;
	335	}