[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include <linux/string.h>
#include <linux/bitops.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"

/** @file i915_gem_tiling.c
 *
 * Support for managing tiling state of buffer objects.
 *
 * The idea behind tiling is to increase cache hit rates by rearranging
 * pixel data so that a group of pixel accesses are in the same cacheline.
 * Performance improvement from doing this on the back/depth buffer are on
 * the order of 30%.
 *
 * Intel architectures make this somewhat more complicated, though, by
 * adjustments made to addressing of data when the memory is in interleaved
 * mode (matched pairs of DIMMS) to improve memory bandwidth.
 * For interleaved memory, the CPU sends every sequential 64 bytes
 * to an alternate memory channel so it can get the bandwidth from both.
 *
 * The GPU also rearranges its accesses for increased bandwidth to interleaved
 * memory, and it matches what the CPU does for non-tiled.  However, when tiled
 * it does it a little differently, since one walks addresses not just in the
 * X direction but also Y.  So, along with alternating channels when bit
 * 6 of the address flips, it also alternates when other bits flip --  Bits 9
 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
 * are common to both the 915 and 965-class hardware.
 *
 * The CPU also sometimes XORs in higher bits as well, to improve
 * bandwidth doing strided access like we do so frequently in graphics.  This
 * is called "Channel XOR Randomization" in the MCH documentation.  The result
 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
 * decode.
 *
 * All of this bit 6 XORing has an effect on our memory management,
 * as we need to make sure that the 3d driver can correctly address object
 * contents.
 *
 * If we don't have interleaved memory, all tiling is safe and no swizzling is
 * required.
 *
 * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
 * 17 is not just a page offset, so as we page an objet out and back in,
 * individual pages in it will have different bit 17 addresses, resulting in
 * each 64 bytes being swapped with its neighbor!
 *
 * Otherwise, if interleaved, we have to tell the 3d driver what the address
 * swizzling it needs to do is, since it's writing with the CPU to the pages
 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
 * to match what the GPU expects.
 */

/**
 * Detects bit 6 swizzling of address lookup between IGD access and CPU
 * access through main memory.
 */
void
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

	if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
		/*
		 * On BDW+, swizzling is not used. We leave the CPU memory
		 * controller in charge of optimizing memory accesses without
		 * the extra address manipulation GPU side.
		 *
		 * VLV and CHV don't have GPU swizzling.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (INTEL_INFO(dev)->gen >= 6) {
		if (dev_priv->preserve_bios_swizzle) {
			if (I915_READ(DISP_ARB_CTL) &
			    DISP_TILE_SURFACE_SWIZZLING) {
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else {
				swizzle_x = I915_BIT_6_SWIZZLE_NONE;
				swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			}
		} else {
			uint32_t dimm_c0, dimm_c1;
			dimm_c0 = I915_READ(MAD_DIMM_C0);
			dimm_c1 = I915_READ(MAD_DIMM_C1);
			dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
			dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
			/* Enable swizzling when the channels are populated
			 * with identically sized dimms. We don't need to check
			 * the 3rd channel because no cpu with gpu attached
			 * ships in that configuration. Also, swizzling only
			 * makes sense for 2 channels anyway. */
			if (dimm_c0 == dimm_c1) {
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else {
				swizzle_x = I915_BIT_6_SWIZZLE_NONE;
				swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			}
		}
	} else if (IS_GEN5(dev)) {
		/* On Ironlake whatever DRAM config, GPU always do
		 * same swizzling setup.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_9_10;
		swizzle_y = I915_BIT_6_SWIZZLE_9;
	} else if (IS_GEN2(dev)) {
		/* As far as we know, the 865 doesn't have these bit 6
		 * swizzling issues.
		 */
		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
		uint32_t dcc;

		/* On 9xx chipsets, channel interleave by the CPU is
		 * determined by DCC.  For single-channel, neither the CPU
		 * nor the GPU do swizzling.  For dual channel interleaved,
		 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
		 * 9 for Y tiled.  The CPU's interleave is independent, and
		 * can be based on either bit 11 (haven't seen this yet) or
		 * bit 17 (common).
		 */
		dcc = I915_READ(DCC);
		switch (dcc & DCC_ADDRESSING_MODE_MASK) {
		case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
			break;
		case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
			if (dcc & DCC_CHANNEL_XOR_DISABLE) {
				/* This is the base swizzling by the GPU for
				 * tiled buffers.
				 */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10;
				swizzle_y = I915_BIT_6_SWIZZLE_9;
			} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
				/* Bit 11 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
				swizzle_y = I915_BIT_6_SWIZZLE_9_11;
			} else {
				/* Bit 17 swizzling by the CPU in addition. */
				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
			}
			break;
		}
		if (dcc == 0xffffffff) {
			DRM_ERROR("Couldn't read from MCHBAR.  "
				  "Disabling tiling.\n");
			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
		}
	} else {
		/* The 965, G33, and newer, have a very flexible memory
		 * configuration.  It will enable dual-channel mode
		 * (interleaving) on as much memory as it can, and the GPU
		 * will additionally sometimes enable different bit 6
		 * swizzling for tiled objects from the CPU.
		 *
		 * Here's what I found on the G965:
		 *    slot fill         memory size  swizzling
		 * 0A   0B   1A   1B    1-ch   2-ch
		 * 512  0    0    0     512    0     O
		 * 512  0    512  0     16     1008  X
		 * 512  0    0    512   16     1008  X
		 * 0    512  0    512   16     1008  X
		 * 1024 1024 1024 0     2048   1024  O
		 *
		 * We could probably detect this based on either the DRB
		 * matching, which was the case for the swizzling required in
		 * the table above, or from the 1-ch value being less than
		 * the minimum size of a rank.
		 */
		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
			swizzle_x = I915_BIT_6_SWIZZLE_NONE;
			swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		} else {
			swizzle_x = I915_BIT_6_SWIZZLE_9_10;
			swizzle_y = I915_BIT_6_SWIZZLE_9;
		}
	}

	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
}

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (IS_GEN2(dev) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	/* i965+ stores the end address of the gtt mapping in the fence
	 * reg, so dont bother to check the size */
	if (INTEL_INFO(dev)->gen >= 7) {
		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (INTEL_INFO(dev)->gen >= 4) {
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;

		if (IS_GEN3(dev)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}

	if (stride < tile_width)
		return false;

	/* 965+ just needs multiples of tile width */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride & (stride - 1))
		return false;

	return true;
}

/* Is the current GTT allocation valid for the change in tiling? */
static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
{
	u32 size;

	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen >= 4)
		return true;

	if (INTEL_INFO(obj->base.dev)->gen == 3) {
		if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
			return false;
	} else {
		if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
			return false;
	}

	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
	if (i915_gem_obj_ggtt_size(obj) != size)
		return false;

	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
		return false;

	return true;
}

/**
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	int ret = 0;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	if (!i915_tiling_ok(dev,
			    args->stride, obj->base.size, args->tiling_mode)) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EINVAL;
	}

	if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
		drm_gem_object_unreference_unlocked(&obj->base);
		return -EBUSY;
	}

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}

	mutex_lock(&dev->struct_mutex);
	if (args->tiling_mode != obj->tiling_mode ||
	    args->stride != obj->stride) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is updated before
		 * the next fenced (either through the GTT or by the BLT unit
		 * on older GPUs) access.
		 *
		 * After updating the tiling parameters, we then flag whether
		 * we need to update an associated fence register. Note this
		 * has to also include the unfenced register the GPU uses
		 * whilst executing a fenced command for an untiled object.
		 */

		obj->map_and_fenceable =
			!i915_gem_obj_ggtt_bound(obj) ||
			(i915_gem_obj_ggtt_offset(obj) +
			 obj->base.size <= dev_priv->gtt.mappable_end &&
			 i915_gem_object_fence_ok(obj, args->tiling_mode));

		/* Rebind if we need a change of alignment */
		if (!obj->map_and_fenceable) {
			u32 unfenced_align =
				i915_gem_get_gtt_alignment(dev, obj->base.size,
							    args->tiling_mode,
							    false);
			if (i915_gem_obj_ggtt_offset(obj) & (unfenced_align - 1))
				ret = i915_gem_object_ggtt_unbind(obj);
		}

		if (ret == 0) {
			obj->fence_dirty =
				obj->last_fenced_seqno ||
				obj->fence_reg != I915_FENCE_REG_NONE;

			obj->tiling_mode = args->tiling_mode;
			obj->stride = args->stride;

			/* Force the fence to be reacquired for GTT access */
			i915_gem_release_mmap(obj);
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = obj->stride;
	args->tiling_mode = obj->tiling_mode;

	/* Try to preallocate memory required to save swizzling on put-pages */
	if (i915_gem_object_needs_bit17_swizzle(obj)) {
		if (obj->bit_17 == NULL) {
			obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
					      sizeof(long), GFP_KERNEL);
		}
	} else {
		kfree(obj->bit_17);
		obj->bit_17 = NULL;
	}

	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	return ret;
}

/**
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;

	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
	if (&obj->base == NULL)
		return -ENOENT;

	mutex_lock(&dev->struct_mutex);

	args->tiling_mode = obj->tiling_mode;
	switch (obj->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	args->phys_swizzle_mode = args->swizzle_mode;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	drm_gem_object_unreference(&obj->base);
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

/**
 * Swap every 64 bytes of this page around, to account for it having a new
 * bit 17 of its physical address and therefore being interpreted differently
 * by the GPU.
 */
static void
i915_gem_swizzle_page(struct page *page)
{
	char temp[64];
	char *vaddr;
	int i;

	vaddr = kmap(page);

	for (i = 0; i < PAGE_SIZE; i += 128) {
		memcpy(temp, &vaddr[i], 64);
		memcpy(&vaddr[i], &vaddr[i + 64], 64);
		memcpy(&vaddr[i + 64], temp, 64);
	}

	kunmap(page);
}

void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct sg_page_iter sg_iter;
	int i;

	if (obj->bit_17 == NULL)
		return;

	i = 0;
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
		struct page *page = sg_page_iter_page(&sg_iter);
		char new_bit_17 = page_to_phys(page) >> 17;
		if ((new_bit_17 & 0x1) !=
		    (test_bit(i, obj->bit_17) != 0)) {
			i915_gem_swizzle_page(page);
			set_page_dirty(page);
		}
		i++;
	}
}

void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
{
	struct sg_page_iter sg_iter;
	int page_count = obj->base.size >> PAGE_SHIFT;
	int i;

	if (obj->bit_17 == NULL) {
		obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
				      sizeof(long), GFP_KERNEL);
		if (obj->bit_17 == NULL) {
			DRM_ERROR("Failed to allocate memory for bit 17 "
				  "record\n");
			return;
		}
	}

	i = 0;
	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
		if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
			__set_bit(i, obj->bit_17);
		else
			__clear_bit(i, obj->bit_17);
		i++;
	}
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
760285e7 DH	28	#include <linux/string.h>
	29	#include <linux/bitops.h>
	30	#include <drm/drmP.h>
	31	#include <drm/i915_drm.h>
673a394b EA	32	#include "i915_drv.h"
	33
	34	/** @file i915_gem_tiling.c
	35	*
	36	* Support for managing tiling state of buffer objects.
	37	*
	38	* The idea behind tiling is to increase cache hit rates by rearranging
	39	* pixel data so that a group of pixel accesses are in the same cacheline.
	40	* Performance improvement from doing this on the back/depth buffer are on
	41	* the order of 30%.
	42	*
	43	* Intel architectures make this somewhat more complicated, though, by
	44	* adjustments made to addressing of data when the memory is in interleaved
	45	* mode (matched pairs of DIMMS) to improve memory bandwidth.
	46	* For interleaved memory, the CPU sends every sequential 64 bytes
	47	* to an alternate memory channel so it can get the bandwidth from both.
	48	*
	49	* The GPU also rearranges its accesses for increased bandwidth to interleaved
	50	* memory, and it matches what the CPU does for non-tiled. However, when tiled
	51	* it does it a little differently, since one walks addresses not just in the
	52	* X direction but also Y. So, along with alternating channels when bit
	53	* 6 of the address flips, it also alternates when other bits flip -- Bits 9
	54	* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
	55	* are common to both the 915 and 965-class hardware.
	56	*
	57	* The CPU also sometimes XORs in higher bits as well, to improve
	58	* bandwidth doing strided access like we do so frequently in graphics. This
	59	* is called "Channel XOR Randomization" in the MCH documentation. The result
	60	* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
	61	* decode.
	62	*
	63	* All of this bit 6 XORing has an effect on our memory management,
	64	* as we need to make sure that the 3d driver can correctly address object
	65	* contents.
	66	*
	67	* If we don't have interleaved memory, all tiling is safe and no swizzling is
	68	* required.
	69	*
	70	* When bit 17 is XORed in, we simply refuse to tile at all. Bit
	71	* 17 is not just a page offset, so as we page an objet out and back in,
	72	* individual pages in it will have different bit 17 addresses, resulting in
	73	* each 64 bytes being swapped with its neighbor!
	74	*
	75	* Otherwise, if interleaved, we have to tell the 3d driver what the address
	76	* swizzling it needs to do is, since it's writing with the CPU to the pages
	77	* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
	78	* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
	79	* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
	80	* to match what the GPU expects.
	81	*/
	82
	83	/**
	84	* Detects bit 6 swizzling of address lookup between IGD access and CPU
	85	* access through main memory.
	86	*/
	87	void
	88	i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
	89	{
50227e1c	90	struct drm_i915_private *dev_priv = dev->dev_private;
673a394b EA	91	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	92	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
	93
be292e15 DL	94	if (INTEL_INFO(dev)->gen >= 8 \|\| IS_VALLEYVIEW(dev)) {
	95	/*
	96	* On BDW+, swizzling is not used. We leave the CPU memory
	97	* controller in charge of optimizing memory accesses without
	98	* the extra address manipulation GPU side.
	99	*
	100	* VLV and CHV don't have GPU swizzling.
	101	*/
7f661341 JB	102	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	103	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	104	} else if (INTEL_INFO(dev)->gen >= 6) {
d9ceb816 JB	105	if (dev_priv->preserve_bios_swizzle) {
	106	if (I915_READ(DISP_ARB_CTL) &
	107	DISP_TILE_SURFACE_SWIZZLING) {
	108	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	109	swizzle_y = I915_BIT_6_SWIZZLE_9;
	110	} else {
	111	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	112	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	113	}
f691e2f4	114	} else {
d9ceb816 JB	115	uint32_t dimm_c0, dimm_c1;
	116	dimm_c0 = I915_READ(MAD_DIMM_C0);
	117	dimm_c1 = I915_READ(MAD_DIMM_C1);
	118	dimm_c0 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;
	119	dimm_c1 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;
	120	/* Enable swizzling when the channels are populated
	121	* with identically sized dimms. We don't need to check
	122	* the 3rd channel because no cpu with gpu attached
	123	* ships in that configuration. Also, swizzling only
	124	* makes sense for 2 channels anyway. */
	125	if (dimm_c0 == dimm_c1) {
	126	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	127	swizzle_y = I915_BIT_6_SWIZZLE_9;
	128	} else {
	129	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	130	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	131	}
f691e2f4	132	}
acc83eb5	133	} else if (IS_GEN5(dev)) {
f2b115e6	134	/* On Ironlake whatever DRAM config, GPU always do
553bd149 ZW	135	* same swizzling setup.
	136	*/
	137	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	138	swizzle_y = I915_BIT_6_SWIZZLE_9;
a6c45cf0	139	} else if (IS_GEN2(dev)) {
673a394b EA	140	/* As far as we know, the 865 doesn't have these bit 6
	141	* swizzling issues.
	142	*/
	143	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	144	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
c9c4b6f6	145	} else if (IS_MOBILE(dev) \|\| (IS_GEN3(dev) && !IS_G33(dev))) {
673a394b EA	146	uint32_t dcc;
673a394b EA	147
c9c4b6f6	148	/* On 9xx chipsets, channel interleave by the CPU is
568d9a8f EA	149	* determined by DCC. For single-channel, neither the CPU
	150	* nor the GPU do swizzling. For dual channel interleaved,
	151	* the GPU's interleave is bit 9 and 10 for X tiled, and bit
	152	* 9 for Y tiled. The CPU's interleave is independent, and
	153	* can be based on either bit 11 (haven't seen this yet) or
	154	* bit 17 (common).
673a394b EA	155	*/
	156	dcc = I915_READ(DCC);
	157	switch (dcc & DCC_ADDRESSING_MODE_MASK) {
	158	case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
	159	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
	160	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	161	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	162	break;
	163	case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
568d9a8f EA	164	if (dcc & DCC_CHANNEL_XOR_DISABLE) {
	165	/* This is the base swizzling by the GPU for
	166	* tiled buffers.
	167	*/
673a394b EA	168	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
673a394b EA	169	swizzle_y = I915_BIT_6_SWIZZLE_9;
568d9a8f EA	170	} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
568d9a8f EA	171	/* Bit 11 swizzling by the CPU in addition. */
673a394b EA	172	swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
	173	swizzle_y = I915_BIT_6_SWIZZLE_9_11;
	174	} else {
568d9a8f	175	/* Bit 17 swizzling by the CPU in addition. */
280b713b EA	176	swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
280b713b EA	177	swizzle_y = I915_BIT_6_SWIZZLE_9_17;
673a394b EA	178	}
	179	break;
	180	}
	181	if (dcc == 0xffffffff) {
	182	DRM_ERROR("Couldn't read from MCHBAR. "
	183	"Disabling tiling.\n");
	184	swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
	185	swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
	186	}
	187	} else {
	188	/* The 965, G33, and newer, have a very flexible memory
	189	* configuration. It will enable dual-channel mode
	190	* (interleaving) on as much memory as it can, and the GPU
	191	* will additionally sometimes enable different bit 6
	192	* swizzling for tiled objects from the CPU.
	193	*
	194	* Here's what I found on the G965:
	195	* slot fill memory size swizzling
	196	* 0A 0B 1A 1B 1-ch 2-ch
	197	* 512 0 0 0 512 0 O
	198	* 512 0 512 0 16 1008 X
	199	* 512 0 0 512 16 1008 X
	200	* 0 512 0 512 16 1008 X
	201	* 1024 1024 1024 0 2048 1024 O
	202	*
	203	* We could probably detect this based on either the DRB
	204	* matching, which was the case for the swizzling required in
	205	* the table above, or from the 1-ch value being less than
	206	* the minimum size of a rank.
	207	*/
	208	if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
	209	swizzle_x = I915_BIT_6_SWIZZLE_NONE;
	210	swizzle_y = I915_BIT_6_SWIZZLE_NONE;
	211	} else {
	212	swizzle_x = I915_BIT_6_SWIZZLE_9_10;
	213	swizzle_y = I915_BIT_6_SWIZZLE_9;
	214	}
	215	}
	216
	217	dev_priv->mm.bit_6_swizzle_x = swizzle_x;
	218	dev_priv->mm.bit_6_swizzle_y = swizzle_y;
	219	}
	220
0f973f27	221	/* Check pitch constriants for all chips & tiling formats */
a00b10c3	222	static bool
0f973f27 JB	223	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
0f973f27 JB	224	{
0ee537ab	225	int tile_width;
0f973f27 JB	226
	227	/* Linear is always fine */
	228	if (tiling_mode == I915_TILING_NONE)
	229	return true;
	230
a6c45cf0	231	if (IS_GEN2(dev) \|\|
e76a16de	232	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
0f973f27 JB	233	tile_width = 128;
	234	else
	235	tile_width = 512;
	236
8d7773a3	237	/* check maximum stride & object size */
3a062478 VS	238	/* i965+ stores the end address of the gtt mapping in the fence
	239	* reg, so dont bother to check the size */
	240	if (INTEL_INFO(dev)->gen >= 7) {
	241	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
	242	return false;
	243	} else if (INTEL_INFO(dev)->gen >= 4) {
8d7773a3 DV	244	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
8d7773a3 DV	245	return false;
a6c45cf0	246	} else {
c36a2a6d	247	if (stride > 8192)
8d7773a3	248	return false;
e76a16de	249
c36a2a6d DV	250	if (IS_GEN3(dev)) {
	251	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
	252	return false;
	253	} else {
	254	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
	255	return false;
	256	}
8d7773a3 DV	257	}
8d7773a3 DV	258
fe48d8de VS	259	if (stride < tile_width)
	260	return false;
	261
0f973f27	262	/* 965+ just needs multiples of tile width */
a6c45cf0	263	if (INTEL_INFO(dev)->gen >= 4) {
0f973f27 JB	264	if (stride & (tile_width - 1))
	265	return false;
	266	return true;
	267	}
	268
	269	/* Pre-965 needs power of two tile widths */
0f973f27 JB	270	if (stride & (stride - 1))
	271	return false;
	272
0f973f27 JB	273	return true;
	274	}
	275
a00b10c3 CW	276	/* Is the current GTT allocation valid for the change in tiling? */
a00b10c3 CW	277	static bool
05394f39	278	i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
52dc7d32	279	{
a00b10c3	280	u32 size;
52dc7d32 CW	281
	282	if (tiling_mode == I915_TILING_NONE)
	283	return true;
	284
05394f39	285	if (INTEL_INFO(obj->base.dev)->gen >= 4)
a6c45cf0 CW	286	return true;
a6c45cf0 CW	287
05394f39	288	if (INTEL_INFO(obj->base.dev)->gen == 3) {
f343c5f6	289	if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
df153158 CW	290	return false;
df153158 CW	291	} else {
f343c5f6	292	if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
df153158 CW	293	return false;
	294	}
	295
0fa87796	296	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
f343c5f6	297	if (i915_gem_obj_ggtt_size(obj) != size)
a6c45cf0 CW	298	return false;
a6c45cf0 CW	299
f343c5f6	300	if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
df153158	301	return false;
52dc7d32 CW	302
	303	return true;
	304	}
	305
673a394b EA	306	/**
	307	* Sets the tiling mode of an object, returning the required swizzling of
	308	* bit 6 of addresses in the object.
	309	*/
	310	int
	311	i915_gem_set_tiling(struct drm_device dev, void data,
05394f39	312	struct drm_file *file)
673a394b EA	313	{
673a394b EA	314	struct drm_i915_gem_set_tiling *args = data;
50227e1c	315	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	316	struct drm_i915_gem_object *obj;
47ae63e0	317	int ret = 0;
673a394b	318
05394f39	319	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	320	if (&obj->base == NULL)
bf79cb91	321	return -ENOENT;
673a394b	322
05394f39 CW	323	if (!i915_tiling_ok(dev,
	324	args->stride, obj->base.size, args->tiling_mode)) {
	325	drm_gem_object_unreference_unlocked(&obj->base);
0f973f27	326	return -EINVAL;
72daad40	327	}
0f973f27	328
d7f46fc4	329	if (i915_gem_obj_is_pinned(obj) \|\| obj->framebuffer_references) {
05394f39	330	drm_gem_object_unreference_unlocked(&obj->base);
31770bd4 DV	331	return -EBUSY;
	332	}
	333
673a394b	334	if (args->tiling_mode == I915_TILING_NONE) {
673a394b	335	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	336	args->stride = 0;
673a394b EA	337	} else {
	338	if (args->tiling_mode == I915_TILING_X)
	339	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	340	else
	341	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	342
	343	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	344	* from aborting the application on sw fallbacks to bit 17,
	345	* and we use the pread/pwrite bit17 paths to swizzle for it.
	346	* If there was a user that was relying on the swizzle
	347	* information for drm_intel_bo_map()ed reads/writes this would
	348	* break it, but we don't have any of those.
	349	*/
	350	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	351	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	352	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	353	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	354
673a394b EA	355	/* If we can't handle the swizzling, make it untiled. */
	356	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	357	args->tiling_mode = I915_TILING_NONE;
	358	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	359	args->stride = 0;
673a394b EA	360	}
673a394b EA	361	}
0f973f27	362
52dc7d32	363	mutex_lock(&dev->struct_mutex);
05394f39 CW	364	if (args->tiling_mode != obj->tiling_mode \|\|
05394f39 CW	365	args->stride != obj->stride) {
52dc7d32 CW	366	/* We need to rebind the object if its current allocation
	367	* no longer meets the alignment restrictions for its new
	368	* tiling mode. Otherwise we can just leave it alone, but
1869b620 CW	369	* need to ensure that any fence register is updated before
	370	* the next fenced (either through the GTT or by the BLT unit
	371	* on older GPUs) access.
5d82e3e6 CW	372	*
	373	* After updating the tiling parameters, we then flag whether
	374	* we need to update an associated fence register. Note this
	375	* has to also include the unfenced register the GPU uses
	376	* whilst executing a fenced command for an untiled object.
0f973f27	377	*/
fe305198	378
d9e86c0e	379	obj->map_and_fenceable =
f343c5f6	380	!i915_gem_obj_ggtt_bound(obj) \|\|
07fe0b12 BW	381	(i915_gem_obj_ggtt_offset(obj) +
07fe0b12 BW	382	obj->base.size <= dev_priv->gtt.mappable_end &&
d9e86c0e	383	i915_gem_object_fence_ok(obj, args->tiling_mode));
52dc7d32	384
467cffba CW	385	/* Rebind if we need a change of alignment */
467cffba CW	386	if (!obj->map_and_fenceable) {
07fe0b12	387	u32 unfenced_align =
d865110c ID	388	i915_gem_get_gtt_alignment(dev, obj->base.size,
	389	args->tiling_mode,
	390	false);
07fe0b12 BW	391	if (i915_gem_obj_ggtt_offset(obj) & (unfenced_align - 1))
07fe0b12 BW	392	ret = i915_gem_object_ggtt_unbind(obj);
467cffba CW	393	}
	394
	395	if (ret == 0) {
5d82e3e6	396	obj->fence_dirty =
82b6b6d7	397	obj->last_fenced_seqno \|\|
5d82e3e6 CW	398	obj->fence_reg != I915_FENCE_REG_NONE;
5d82e3e6 CW	399
467cffba CW	400	obj->tiling_mode = args->tiling_mode;
467cffba CW	401	obj->stride = args->stride;
1869b620 CW	402
	403	/* Force the fence to be reacquired for GTT access */
	404	i915_gem_release_mmap(obj);
467cffba	405	}
0f973f27	406	}
467cffba CW	407	/* we have to maintain this existing ABI... */
	408	args->stride = obj->stride;
	409	args->tiling_mode = obj->tiling_mode;
e9b73c67 CW	410
	411	/* Try to preallocate memory required to save swizzling on put-pages */
	412	if (i915_gem_object_needs_bit17_swizzle(obj)) {
	413	if (obj->bit_17 == NULL) {
a1e22653	414	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
e9b73c67 CW	415	sizeof(long), GFP_KERNEL);
	416	}
	417	} else {
	418	kfree(obj->bit_17);
	419	obj->bit_17 = NULL;
	420	}
	421
05394f39	422	drm_gem_object_unreference(&obj->base);
d6873102	423	mutex_unlock(&dev->struct_mutex);
673a394b	424
467cffba	425	return ret;
673a394b EA	426	}
	427
	428	/**
	429	* Returns the current tiling mode and required bit 6 swizzling for the object.
	430	*/
	431	int
	432	i915_gem_get_tiling(struct drm_device dev, void data,
05394f39	433	struct drm_file *file)
673a394b EA	434	{
673a394b EA	435	struct drm_i915_gem_get_tiling *args = data;
50227e1c	436	struct drm_i915_private *dev_priv = dev->dev_private;
05394f39	437	struct drm_i915_gem_object *obj;
673a394b	438
05394f39	439	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226	440	if (&obj->base == NULL)
bf79cb91	441	return -ENOENT;
673a394b EA	442
	443	mutex_lock(&dev->struct_mutex);
	444
05394f39 CW	445	args->tiling_mode = obj->tiling_mode;
05394f39 CW	446	switch (obj->tiling_mode) {
673a394b EA	447	case I915_TILING_X:
	448	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	449	break;
	450	case I915_TILING_Y:
	451	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	452	break;
	453	case I915_TILING_NONE:
	454	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	455	break;
	456	default:
	457	DRM_ERROR("unknown tiling mode\n");
	458	}
	459
280b713b	460	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
70f2f5c7	461	args->phys_swizzle_mode = args->swizzle_mode;
280b713b EA	462	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	463	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	464	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	465	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	466
05394f39	467	drm_gem_object_unreference(&obj->base);
d6873102	468	mutex_unlock(&dev->struct_mutex);
673a394b EA	469
	470	return 0;
	471	}
280b713b EA	472
	473	/**
	474	* Swap every 64 bytes of this page around, to account for it having a new
	475	* bit 17 of its physical address and therefore being interpreted differently
	476	* by the GPU.
	477	*/
dd2575ff	478	static void
280b713b EA	479	i915_gem_swizzle_page(struct page *page)
280b713b EA	480	{
dd2575ff	481	char temp[64];
280b713b EA	482	char *vaddr;
280b713b EA	483	int i;
280b713b EA	484
280b713b EA	485	vaddr = kmap(page);
280b713b EA	486
	487	for (i = 0; i < PAGE_SIZE; i += 128) {
	488	memcpy(temp, &vaddr[i], 64);
	489	memcpy(&vaddr[i], &vaddr[i + 64], 64);
	490	memcpy(&vaddr[i + 64], temp, 64);
	491	}
	492
	493	kunmap(page);
280b713b EA	494	}
	495
	496	void
05394f39	497	i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
280b713b	498	{
67d5a50c	499	struct sg_page_iter sg_iter;
280b713b EA	500	int i;
280b713b EA	501
05394f39	502	if (obj->bit_17 == NULL)
280b713b EA	503	return;
280b713b EA	504
67d5a50c ID	505	i = 0;
67d5a50c ID	506	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2db76d7c	507	struct page *page = sg_page_iter_page(&sg_iter);
9da3da66	508	char new_bit_17 = page_to_phys(page) >> 17;
280b713b	509	if ((new_bit_17 & 0x1) !=
05394f39	510	(test_bit(i, obj->bit_17) != 0)) {
9da3da66 CW	511	i915_gem_swizzle_page(page);
9da3da66 CW	512	set_page_dirty(page);
280b713b	513	}
67d5a50c	514	i++;
280b713b EA	515	}
	516	}
	517
	518	void
05394f39	519	i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
280b713b	520	{
67d5a50c	521	struct sg_page_iter sg_iter;
05394f39	522	int page_count = obj->base.size >> PAGE_SHIFT;
280b713b EA	523	int i;
280b713b EA	524
05394f39	525	if (obj->bit_17 == NULL) {
a1e22653 DV	526	obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
a1e22653 DV	527	sizeof(long), GFP_KERNEL);
05394f39	528	if (obj->bit_17 == NULL) {
280b713b EA	529	DRM_ERROR("Failed to allocate memory for bit 17 "
	530	"record\n");
	531	return;
	532	}
	533	}
	534
67d5a50c ID	535	i = 0;
67d5a50c ID	536	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2db76d7c	537	if (page_to_phys(sg_page_iter_page(&sg_iter)) & (1 << 17))
05394f39	538	__set_bit(i, obj->bit_17);
280b713b	539	else
05394f39	540	__clear_bit(i, obj->bit_17);
67d5a50c	541	i++;
280b713b EA	542	}
280b713b EA	543	}