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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
d7658989 JB |
28 | #include <linux/acpi.h> |
29 | #include <linux/pnp.h> | |
280b713b EA |
30 | #include "linux/string.h" |
31 | #include "linux/bitops.h" | |
673a394b EA |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | ||
37 | /** @file i915_gem_tiling.c | |
38 | * | |
39 | * Support for managing tiling state of buffer objects. | |
40 | * | |
41 | * The idea behind tiling is to increase cache hit rates by rearranging | |
42 | * pixel data so that a group of pixel accesses are in the same cacheline. | |
43 | * Performance improvement from doing this on the back/depth buffer are on | |
44 | * the order of 30%. | |
45 | * | |
46 | * Intel architectures make this somewhat more complicated, though, by | |
47 | * adjustments made to addressing of data when the memory is in interleaved | |
48 | * mode (matched pairs of DIMMS) to improve memory bandwidth. | |
49 | * For interleaved memory, the CPU sends every sequential 64 bytes | |
50 | * to an alternate memory channel so it can get the bandwidth from both. | |
51 | * | |
52 | * The GPU also rearranges its accesses for increased bandwidth to interleaved | |
53 | * memory, and it matches what the CPU does for non-tiled. However, when tiled | |
54 | * it does it a little differently, since one walks addresses not just in the | |
55 | * X direction but also Y. So, along with alternating channels when bit | |
56 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 | |
57 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) | |
58 | * are common to both the 915 and 965-class hardware. | |
59 | * | |
60 | * The CPU also sometimes XORs in higher bits as well, to improve | |
61 | * bandwidth doing strided access like we do so frequently in graphics. This | |
62 | * is called "Channel XOR Randomization" in the MCH documentation. The result | |
63 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address | |
64 | * decode. | |
65 | * | |
66 | * All of this bit 6 XORing has an effect on our memory management, | |
67 | * as we need to make sure that the 3d driver can correctly address object | |
68 | * contents. | |
69 | * | |
70 | * If we don't have interleaved memory, all tiling is safe and no swizzling is | |
71 | * required. | |
72 | * | |
73 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit | |
74 | * 17 is not just a page offset, so as we page an objet out and back in, | |
75 | * individual pages in it will have different bit 17 addresses, resulting in | |
76 | * each 64 bytes being swapped with its neighbor! | |
77 | * | |
78 | * Otherwise, if interleaved, we have to tell the 3d driver what the address | |
79 | * swizzling it needs to do is, since it's writing with the CPU to the pages | |
80 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the | |
81 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling | |
82 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order | |
83 | * to match what the GPU expects. | |
84 | */ | |
85 | ||
d7658989 JB |
86 | #define MCHBAR_I915 0x44 |
87 | #define MCHBAR_I965 0x48 | |
88 | #define MCHBAR_SIZE (4*4096) | |
89 | ||
90 | #define DEVEN_REG 0x54 | |
91 | #define DEVEN_MCHBAR_EN (1 << 28) | |
92 | ||
93 | /* Allocate space for the MCH regs if needed, return nonzero on error */ | |
94 | static int | |
95 | intel_alloc_mchbar_resource(struct drm_device *dev) | |
96 | { | |
d7658989 JB |
97 | drm_i915_private_t *dev_priv = dev->dev_private; |
98 | int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; | |
99 | u32 temp_lo, temp_hi = 0; | |
100 | u64 mchbar_addr; | |
101 | int ret = 0; | |
102 | ||
d7658989 | 103 | if (IS_I965G(dev)) |
ec2a4c3f DA |
104 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
105 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); | |
d7658989 JB |
106 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
107 | ||
108 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ | |
b99e228d | 109 | #ifdef CONFIG_PNP |
d7658989 JB |
110 | if (mchbar_addr && |
111 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { | |
112 | ret = 0; | |
ec2a4c3f | 113 | goto out; |
d7658989 | 114 | } |
b99e228d | 115 | #endif |
d7658989 JB |
116 | |
117 | /* Get some space for it */ | |
ec2a4c3f | 118 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, |
d7658989 JB |
119 | MCHBAR_SIZE, MCHBAR_SIZE, |
120 | PCIBIOS_MIN_MEM, | |
121 | 0, pcibios_align_resource, | |
ec2a4c3f | 122 | dev_priv->bridge_dev); |
d7658989 | 123 | if (ret) { |
44d98a61 | 124 | DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); |
d7658989 | 125 | dev_priv->mch_res.start = 0; |
ec2a4c3f | 126 | goto out; |
d7658989 JB |
127 | } |
128 | ||
129 | if (IS_I965G(dev)) | |
ec2a4c3f | 130 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
d7658989 JB |
131 | upper_32_bits(dev_priv->mch_res.start)); |
132 | ||
ec2a4c3f | 133 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
d7658989 | 134 | lower_32_bits(dev_priv->mch_res.start)); |
d7658989 JB |
135 | out: |
136 | return ret; | |
137 | } | |
138 | ||
139 | /* Setup MCHBAR if possible, return true if we should disable it again */ | |
140 | static bool | |
141 | intel_setup_mchbar(struct drm_device *dev) | |
142 | { | |
ec2a4c3f | 143 | drm_i915_private_t *dev_priv = dev->dev_private; |
d7658989 JB |
144 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; |
145 | u32 temp; | |
146 | bool need_disable = false, enabled; | |
147 | ||
d7658989 | 148 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
ec2a4c3f | 149 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
d7658989 JB |
150 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
151 | } else { | |
ec2a4c3f | 152 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
d7658989 JB |
153 | enabled = temp & 1; |
154 | } | |
155 | ||
156 | /* If it's already enabled, don't have to do anything */ | |
157 | if (enabled) | |
ec2a4c3f | 158 | goto out; |
d7658989 JB |
159 | |
160 | if (intel_alloc_mchbar_resource(dev)) | |
ec2a4c3f | 161 | goto out; |
d7658989 JB |
162 | |
163 | need_disable = true; | |
164 | ||
165 | /* Space is allocated or reserved, so enable it. */ | |
166 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
ec2a4c3f | 167 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, |
d7658989 JB |
168 | temp | DEVEN_MCHBAR_EN); |
169 | } else { | |
ec2a4c3f DA |
170 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
171 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); | |
d7658989 | 172 | } |
d7658989 JB |
173 | out: |
174 | return need_disable; | |
175 | } | |
176 | ||
177 | static void | |
178 | intel_teardown_mchbar(struct drm_device *dev, bool disable) | |
179 | { | |
180 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d7658989 JB |
181 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; |
182 | u32 temp; | |
183 | ||
d7658989 JB |
184 | if (disable) { |
185 | if (IS_I915G(dev) || IS_I915GM(dev)) { | |
ec2a4c3f | 186 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); |
d7658989 | 187 | temp &= ~DEVEN_MCHBAR_EN; |
ec2a4c3f | 188 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); |
d7658989 | 189 | } else { |
ec2a4c3f | 190 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
d7658989 | 191 | temp &= ~1; |
ec2a4c3f | 192 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); |
d7658989 JB |
193 | } |
194 | } | |
195 | ||
196 | if (dev_priv->mch_res.start) | |
197 | release_resource(&dev_priv->mch_res); | |
198 | } | |
199 | ||
673a394b EA |
200 | /** |
201 | * Detects bit 6 swizzling of address lookup between IGD access and CPU | |
202 | * access through main memory. | |
203 | */ | |
204 | void | |
205 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) | |
206 | { | |
207 | drm_i915_private_t *dev_priv = dev->dev_private; | |
208 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; | |
209 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; | |
d7658989 | 210 | bool need_disable; |
673a394b | 211 | |
f2b115e6 AJ |
212 | if (IS_IRONLAKE(dev)) { |
213 | /* On Ironlake whatever DRAM config, GPU always do | |
553bd149 ZW |
214 | * same swizzling setup. |
215 | */ | |
216 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; | |
217 | swizzle_y = I915_BIT_6_SWIZZLE_9; | |
218 | } else if (!IS_I9XX(dev)) { | |
673a394b EA |
219 | /* As far as we know, the 865 doesn't have these bit 6 |
220 | * swizzling issues. | |
221 | */ | |
222 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
223 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
568d9a8f | 224 | } else if (IS_MOBILE(dev)) { |
673a394b EA |
225 | uint32_t dcc; |
226 | ||
d7658989 JB |
227 | /* Try to make sure MCHBAR is enabled before poking at it */ |
228 | need_disable = intel_setup_mchbar(dev); | |
229 | ||
568d9a8f EA |
230 | /* On mobile 9xx chipsets, channel interleave by the CPU is |
231 | * determined by DCC. For single-channel, neither the CPU | |
232 | * nor the GPU do swizzling. For dual channel interleaved, | |
233 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit | |
234 | * 9 for Y tiled. The CPU's interleave is independent, and | |
235 | * can be based on either bit 11 (haven't seen this yet) or | |
236 | * bit 17 (common). | |
673a394b EA |
237 | */ |
238 | dcc = I915_READ(DCC); | |
239 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { | |
240 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: | |
241 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: | |
242 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
243 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
244 | break; | |
245 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: | |
568d9a8f EA |
246 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
247 | /* This is the base swizzling by the GPU for | |
248 | * tiled buffers. | |
249 | */ | |
673a394b EA |
250 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
251 | swizzle_y = I915_BIT_6_SWIZZLE_9; | |
568d9a8f EA |
252 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
253 | /* Bit 11 swizzling by the CPU in addition. */ | |
673a394b EA |
254 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
255 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; | |
256 | } else { | |
568d9a8f | 257 | /* Bit 17 swizzling by the CPU in addition. */ |
280b713b EA |
258 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
259 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; | |
673a394b EA |
260 | } |
261 | break; | |
262 | } | |
263 | if (dcc == 0xffffffff) { | |
264 | DRM_ERROR("Couldn't read from MCHBAR. " | |
265 | "Disabling tiling.\n"); | |
266 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; | |
267 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; | |
268 | } | |
d7658989 JB |
269 | |
270 | intel_teardown_mchbar(dev, need_disable); | |
673a394b EA |
271 | } else { |
272 | /* The 965, G33, and newer, have a very flexible memory | |
273 | * configuration. It will enable dual-channel mode | |
274 | * (interleaving) on as much memory as it can, and the GPU | |
275 | * will additionally sometimes enable different bit 6 | |
276 | * swizzling for tiled objects from the CPU. | |
277 | * | |
278 | * Here's what I found on the G965: | |
279 | * slot fill memory size swizzling | |
280 | * 0A 0B 1A 1B 1-ch 2-ch | |
281 | * 512 0 0 0 512 0 O | |
282 | * 512 0 512 0 16 1008 X | |
283 | * 512 0 0 512 16 1008 X | |
284 | * 0 512 0 512 16 1008 X | |
285 | * 1024 1024 1024 0 2048 1024 O | |
286 | * | |
287 | * We could probably detect this based on either the DRB | |
288 | * matching, which was the case for the swizzling required in | |
289 | * the table above, or from the 1-ch value being less than | |
290 | * the minimum size of a rank. | |
291 | */ | |
292 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { | |
293 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; | |
294 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; | |
295 | } else { | |
296 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; | |
297 | swizzle_y = I915_BIT_6_SWIZZLE_9; | |
298 | } | |
299 | } | |
300 | ||
301 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; | |
302 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; | |
303 | } | |
304 | ||
0f973f27 JB |
305 | |
306 | /** | |
76446cac JB |
307 | * Returns whether an object is currently fenceable. If not, it may need |
308 | * to be unbound and have its pitch adjusted. | |
0f973f27 | 309 | */ |
76446cac JB |
310 | bool |
311 | i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj) | |
0f973f27 | 312 | { |
76446cac | 313 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
0f973f27 JB |
314 | |
315 | if (IS_I965G(dev)) { | |
316 | /* The 965 can have fences at any page boundary. */ | |
76446cac JB |
317 | if (obj->size & 4095) |
318 | return false; | |
319 | return true; | |
320 | } else if (IS_I9XX(dev)) { | |
321 | if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK) | |
322 | return false; | |
0f973f27 | 323 | } else { |
76446cac JB |
324 | if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK) |
325 | return false; | |
326 | } | |
0f973f27 | 327 | |
76446cac JB |
328 | /* Power of two sized... */ |
329 | if (obj->size & (obj->size - 1)) | |
330 | return false; | |
0f973f27 | 331 | |
76446cac JB |
332 | /* Objects must be size aligned as well */ |
333 | if (obj_priv->gtt_offset & (obj->size - 1)) | |
334 | return false; | |
335 | return true; | |
0f973f27 JB |
336 | } |
337 | ||
338 | /* Check pitch constriants for all chips & tiling formats */ | |
76446cac | 339 | bool |
0f973f27 JB |
340 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
341 | { | |
342 | int tile_width; | |
343 | ||
344 | /* Linear is always fine */ | |
345 | if (tiling_mode == I915_TILING_NONE) | |
346 | return true; | |
347 | ||
e76a16de EA |
348 | if (!IS_I9XX(dev) || |
349 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) | |
0f973f27 JB |
350 | tile_width = 128; |
351 | else | |
352 | tile_width = 512; | |
353 | ||
8d7773a3 DV |
354 | /* check maximum stride & object size */ |
355 | if (IS_I965G(dev)) { | |
356 | /* i965 stores the end address of the gtt mapping in the fence | |
357 | * reg, so dont bother to check the size */ | |
358 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) | |
359 | return false; | |
360 | } else if (IS_I9XX(dev)) { | |
e76a16de EA |
361 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
362 | ||
363 | /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB) | |
364 | * instead of 4 (2KB) on 945s. | |
365 | */ | |
366 | if (pitch_val > I915_FENCE_MAX_PITCH_VAL || | |
8d7773a3 DV |
367 | size > (I830_FENCE_MAX_SIZE_VAL << 20)) |
368 | return false; | |
369 | } else { | |
e76a16de EA |
370 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
371 | ||
372 | if (pitch_val > I830_FENCE_MAX_PITCH_VAL || | |
8d7773a3 DV |
373 | size > (I830_FENCE_MAX_SIZE_VAL << 19)) |
374 | return false; | |
375 | } | |
376 | ||
0f973f27 JB |
377 | /* 965+ just needs multiples of tile width */ |
378 | if (IS_I965G(dev)) { | |
379 | if (stride & (tile_width - 1)) | |
380 | return false; | |
381 | return true; | |
382 | } | |
383 | ||
384 | /* Pre-965 needs power of two tile widths */ | |
385 | if (stride < tile_width) | |
386 | return false; | |
387 | ||
388 | if (stride & (stride - 1)) | |
389 | return false; | |
390 | ||
0f973f27 JB |
391 | return true; |
392 | } | |
393 | ||
52dc7d32 CW |
394 | static bool |
395 | i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode) | |
396 | { | |
397 | struct drm_device *dev = obj->dev; | |
398 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
399 | ||
400 | if (obj_priv->gtt_space == NULL) | |
401 | return true; | |
402 | ||
403 | if (tiling_mode == I915_TILING_NONE) | |
404 | return true; | |
405 | ||
406 | if (!IS_I965G(dev)) { | |
407 | if (obj_priv->gtt_offset & (obj->size - 1)) | |
408 | return false; | |
409 | if (IS_I9XX(dev)) { | |
410 | if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK) | |
411 | return false; | |
412 | } else { | |
413 | if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK) | |
414 | return false; | |
415 | } | |
416 | } | |
417 | ||
418 | return true; | |
419 | } | |
420 | ||
673a394b EA |
421 | /** |
422 | * Sets the tiling mode of an object, returning the required swizzling of | |
423 | * bit 6 of addresses in the object. | |
424 | */ | |
425 | int | |
426 | i915_gem_set_tiling(struct drm_device *dev, void *data, | |
427 | struct drm_file *file_priv) | |
428 | { | |
429 | struct drm_i915_gem_set_tiling *args = data; | |
430 | drm_i915_private_t *dev_priv = dev->dev_private; | |
431 | struct drm_gem_object *obj; | |
432 | struct drm_i915_gem_object *obj_priv; | |
52dc7d32 | 433 | int ret = 0; |
673a394b EA |
434 | |
435 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
436 | if (obj == NULL) | |
437 | return -EINVAL; | |
438 | obj_priv = obj->driver_private; | |
439 | ||
72daad40 | 440 | if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { |
bc9025bd | 441 | drm_gem_object_unreference_unlocked(obj); |
0f973f27 | 442 | return -EINVAL; |
72daad40 | 443 | } |
0f973f27 | 444 | |
673a394b | 445 | if (args->tiling_mode == I915_TILING_NONE) { |
673a394b | 446 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
52dc7d32 | 447 | args->stride = 0; |
673a394b EA |
448 | } else { |
449 | if (args->tiling_mode == I915_TILING_X) | |
450 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; | |
451 | else | |
452 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; | |
280b713b EA |
453 | |
454 | /* Hide bit 17 swizzling from the user. This prevents old Mesa | |
455 | * from aborting the application on sw fallbacks to bit 17, | |
456 | * and we use the pread/pwrite bit17 paths to swizzle for it. | |
457 | * If there was a user that was relying on the swizzle | |
458 | * information for drm_intel_bo_map()ed reads/writes this would | |
459 | * break it, but we don't have any of those. | |
460 | */ | |
461 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) | |
462 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; | |
463 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) | |
464 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; | |
465 | ||
673a394b EA |
466 | /* If we can't handle the swizzling, make it untiled. */ |
467 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { | |
468 | args->tiling_mode = I915_TILING_NONE; | |
469 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; | |
52dc7d32 | 470 | args->stride = 0; |
673a394b EA |
471 | } |
472 | } | |
0f973f27 | 473 | |
52dc7d32 CW |
474 | mutex_lock(&dev->struct_mutex); |
475 | if (args->tiling_mode != obj_priv->tiling_mode || | |
476 | args->stride != obj_priv->stride) { | |
477 | /* We need to rebind the object if its current allocation | |
478 | * no longer meets the alignment restrictions for its new | |
479 | * tiling mode. Otherwise we can just leave it alone, but | |
480 | * need to ensure that any fence register is cleared. | |
0f973f27 | 481 | */ |
52dc7d32 CW |
482 | if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode)) |
483 | ret = i915_gem_object_unbind(obj); | |
484 | else | |
485 | ret = i915_gem_object_put_fence_reg(obj); | |
0f973f27 JB |
486 | if (ret != 0) { |
487 | WARN(ret != -ERESTARTSYS, | |
52dc7d32 | 488 | "failed to reset object for tiling switch"); |
0f973f27 | 489 | args->tiling_mode = obj_priv->tiling_mode; |
52dc7d32 CW |
490 | args->stride = obj_priv->stride; |
491 | goto err; | |
0f973f27 | 492 | } |
52dc7d32 | 493 | |
d05ca301 EA |
494 | /* If we've changed tiling, GTT-mappings of the object |
495 | * need to re-fault to ensure that the correct fence register | |
496 | * setup is in place. | |
497 | */ | |
498 | i915_gem_release_mmap(obj); | |
499 | ||
0f973f27 | 500 | obj_priv->tiling_mode = args->tiling_mode; |
52dc7d32 | 501 | obj_priv->stride = args->stride; |
0f973f27 | 502 | } |
52dc7d32 | 503 | err: |
673a394b | 504 | drm_gem_object_unreference(obj); |
d6873102 | 505 | mutex_unlock(&dev->struct_mutex); |
673a394b | 506 | |
52dc7d32 | 507 | return ret; |
673a394b EA |
508 | } |
509 | ||
510 | /** | |
511 | * Returns the current tiling mode and required bit 6 swizzling for the object. | |
512 | */ | |
513 | int | |
514 | i915_gem_get_tiling(struct drm_device *dev, void *data, | |
515 | struct drm_file *file_priv) | |
516 | { | |
517 | struct drm_i915_gem_get_tiling *args = data; | |
518 | drm_i915_private_t *dev_priv = dev->dev_private; | |
519 | struct drm_gem_object *obj; | |
520 | struct drm_i915_gem_object *obj_priv; | |
521 | ||
522 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
523 | if (obj == NULL) | |
524 | return -EINVAL; | |
525 | obj_priv = obj->driver_private; | |
526 | ||
527 | mutex_lock(&dev->struct_mutex); | |
528 | ||
529 | args->tiling_mode = obj_priv->tiling_mode; | |
530 | switch (obj_priv->tiling_mode) { | |
531 | case I915_TILING_X: | |
532 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; | |
533 | break; | |
534 | case I915_TILING_Y: | |
535 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; | |
536 | break; | |
537 | case I915_TILING_NONE: | |
538 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; | |
539 | break; | |
540 | default: | |
541 | DRM_ERROR("unknown tiling mode\n"); | |
542 | } | |
543 | ||
280b713b EA |
544 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
545 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) | |
546 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; | |
547 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) | |
548 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; | |
549 | ||
673a394b | 550 | drm_gem_object_unreference(obj); |
d6873102 | 551 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
552 | |
553 | return 0; | |
554 | } | |
280b713b EA |
555 | |
556 | /** | |
557 | * Swap every 64 bytes of this page around, to account for it having a new | |
558 | * bit 17 of its physical address and therefore being interpreted differently | |
559 | * by the GPU. | |
560 | */ | |
561 | static int | |
562 | i915_gem_swizzle_page(struct page *page) | |
563 | { | |
564 | char *vaddr; | |
565 | int i; | |
566 | char temp[64]; | |
567 | ||
568 | vaddr = kmap(page); | |
569 | if (vaddr == NULL) | |
570 | return -ENOMEM; | |
571 | ||
572 | for (i = 0; i < PAGE_SIZE; i += 128) { | |
573 | memcpy(temp, &vaddr[i], 64); | |
574 | memcpy(&vaddr[i], &vaddr[i + 64], 64); | |
575 | memcpy(&vaddr[i + 64], temp, 64); | |
576 | } | |
577 | ||
578 | kunmap(page); | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | void | |
584 | i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj) | |
585 | { | |
586 | struct drm_device *dev = obj->dev; | |
587 | drm_i915_private_t *dev_priv = dev->dev_private; | |
588 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
589 | int page_count = obj->size >> PAGE_SHIFT; | |
590 | int i; | |
591 | ||
592 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) | |
593 | return; | |
594 | ||
595 | if (obj_priv->bit_17 == NULL) | |
596 | return; | |
597 | ||
598 | for (i = 0; i < page_count; i++) { | |
599 | char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17; | |
600 | if ((new_bit_17 & 0x1) != | |
601 | (test_bit(i, obj_priv->bit_17) != 0)) { | |
602 | int ret = i915_gem_swizzle_page(obj_priv->pages[i]); | |
603 | if (ret != 0) { | |
604 | DRM_ERROR("Failed to swizzle page\n"); | |
605 | return; | |
606 | } | |
607 | set_page_dirty(obj_priv->pages[i]); | |
608 | } | |
609 | } | |
610 | } | |
611 | ||
612 | void | |
613 | i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj) | |
614 | { | |
615 | struct drm_device *dev = obj->dev; | |
616 | drm_i915_private_t *dev_priv = dev->dev_private; | |
617 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
618 | int page_count = obj->size >> PAGE_SHIFT; | |
619 | int i; | |
620 | ||
621 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) | |
622 | return; | |
623 | ||
624 | if (obj_priv->bit_17 == NULL) { | |
625 | obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * | |
626 | sizeof(long), GFP_KERNEL); | |
627 | if (obj_priv->bit_17 == NULL) { | |
628 | DRM_ERROR("Failed to allocate memory for bit 17 " | |
629 | "record\n"); | |
630 | return; | |
631 | } | |
632 | } | |
633 | ||
634 | for (i = 0; i < page_count; i++) { | |
635 | if (page_to_phys(obj_priv->pages[i]) & (1 << 17)) | |
636 | __set_bit(i, obj_priv->bit_17); | |
637 | else | |
638 | __clear_bit(i, obj_priv->bit_17); | |
639 | } | |
640 | } |