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drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
845f74a7 45 case VCS2: return "bsd2";
84734a04
MK		 46 default: return "";
47 }
48}
49
50static const char *pin_flag(int pinned)
51{
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58}
59
60static const char *tiling_flag(int tiling)
61{
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68}
69
70static const char *dirty_flag(int dirty)
71{
72 return dirty ? " dirty" : "";
73}
74
75static const char *purgeable_flag(int purgeable)
76{
77 return purgeable ? " purgeable" : "";
78}
79
80static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81{
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92}
93
94static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96{
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109}
110
111static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113{
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135}
136
137static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139{
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
e29bb4eb
CW		 147 va_list tmp;
148
149 va_copy(tmp, args);
1d2cb9a5
MK		 150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
84734a04
MK		 154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162}
163
164static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166{
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185}
186
187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188#define err_puts(e, s) i915_error_puts(e, s)
189
190static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194{
195 err_printf(m, "%s [%d]:\n", name, count);
196
197 while (count--) {
198 err_printf(m, " %08x %8u %02x %02x %x %x",
199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 208 err_puts(m, err->userptr ? " userptr" : "");
84734a04
MK		 209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(err->cache_level));
212
213 if (err->name)
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
217
218 err_puts(m, "\n");
219 err++;
220 }
221}
222
da661464
MK		 223static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224{
225 switch (a) {
226 case HANGCHECK_IDLE:
227 return "idle";
228 case HANGCHECK_WAIT:
229 return "wait";
230 case HANGCHECK_ACTIVE:
231 return "active";
232 case HANGCHECK_KICK:
233 return "kick";
234 case HANGCHECK_HUNG:
235 return "hung";
236 }
237
238 return "unknown";
239}
240
84734a04
MK		 241static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
242 struct drm_device *dev,
362b8af7 243 struct drm_i915_error_ring *ring)
84734a04 244{
362b8af7 245 if (!ring->valid)
372fbb8e
CW		 246 return;
247
362b8af7
BW		 248 err_printf(m, " HEAD: 0x%08x\n", ring->head);
249 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
250 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
251 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 252 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 253 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
254 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
255 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 256 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 257 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 258 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
259 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 260 }
362b8af7 261 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 262 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
263 lower_32_bits(ring->faddr));
84734a04 264 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 265 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
266 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 267 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 268 ring->semaphore_mboxes[0],
269 ring->semaphore_seqno[0]);
84734a04 270 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 271 ring->semaphore_mboxes[1],
272 ring->semaphore_seqno[1]);
4e5aabfd
BW		 273 if (HAS_VEBOX(dev)) {
274 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 275 ring->semaphore_mboxes[2],
276 ring->semaphore_seqno[2]);
4e5aabfd 277 }
84734a04 278 }
6c7a01ec
BW		 279 if (USES_PPGTT(dev)) {
280 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
281
282 if (INTEL_INFO(dev)->gen >= 8) {
283 int i;
284 for (i = 0; i < 4; i++)
285 err_printf(m, " PDP%d: 0x%016llx\n",
286 i, ring->vm_info.pdp[i]);
287 } else {
288 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
289 ring->vm_info.pp_dir_base);
290 }
291 }
362b8af7
BW		 292 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
293 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
294 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
295 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 296 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 297 hangcheck_action_to_str(ring->hangcheck_action),
298 ring->hangcheck_score);
84734a04
MK		 299}
300
301void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
302{
303 va_list args;
304
305 va_start(args, f);
306 i915_error_vprintf(e, f, args);
307 va_end(args);
308}
309
ab0e7ff9
CW		 310static void print_error_obj(struct drm_i915_error_state_buf *m,
311 struct drm_i915_error_object *obj)
312{
313 int page, offset, elt;
314
315 for (page = offset = 0; page < obj->page_count; page++) {
316 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
317 err_printf(m, "%08x : %08x\n", offset,
318 obj->pages[page][elt]);
319 offset += 4;
320 }
321 }
322}
323
84734a04
MK		 324int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
325 const struct i915_error_state_file_priv *error_priv)
326{
327 struct drm_device *dev = error_priv->dev;
50227e1c 328 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 329 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 330 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 331 int i, j, offset, elt;
332 int max_hangcheck_score;
84734a04
MK		 333
334 if (!error) {
335 err_printf(m, "no error state collected\n");
336 goto out;
337 }
338
cb383002 339 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 340 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
341 error->time.tv_usec);
342 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 343 max_hangcheck_score = 0;
344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
345 if (error->ring[i].hangcheck_score > max_hangcheck_score)
346 max_hangcheck_score = error->ring[i].hangcheck_score;
347 }
348 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
349 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
350 error->ring[i].pid != -1) {
351 err_printf(m, "Active process (on ring %s): %s [%d]\n",
352 ring_str(i),
353 error->ring[i].comm,
354 error->ring[i].pid);
355 }
356 }
48b031e3 357 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 358 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 359 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 360 err_printf(m, "EIR: 0x%08x\n", error->eir);
361 err_printf(m, "IER: 0x%08x\n", error->ier);
843db716
RV		 362 if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
363 err_printf(m, "GTIER: 0x%08x\n", error->gtier);
84734a04
MK		 364 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
365 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
366 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
367 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 368 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 369
370 for (i = 0; i < dev_priv->num_fence_regs; i++)
371 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
372
373 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
374 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
375 error->extra_instdone[i]);
376
377 if (INTEL_INFO(dev)->gen >= 6) {
378 err_printf(m, "ERROR: 0x%08x\n", error->error);
379 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
380 }
381
382 if (INTEL_INFO(dev)->gen == 7)
383 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
384
362b8af7
BW		 385 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
386 err_printf(m, "%s command stream:\n", ring_str(i));
387 i915_ring_error_state(m, dev, &error->ring[i]);
388 }
84734a04
MK		 389
390 if (error->active_bo)
391 print_error_buffers(m, "Active",
95f5301d
BW		 392 error->active_bo[0],
393 error->active_bo_count[0]);
84734a04
MK		 394
395 if (error->pinned_bo)
396 print_error_buffers(m, "Pinned",
95f5301d
BW		 397 error->pinned_bo[0],
398 error->pinned_bo_count[0]);
84734a04
MK		 399
400 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
ab0e7ff9
CW		 401 obj = error->ring[i].batchbuffer;
402 if (obj) {
403 err_puts(m, dev_priv->ring[i].name);
404 if (error->ring[i].pid != -1)
405 err_printf(m, " (submitted by %s [%d])",
406 error->ring[i].comm,
407 error->ring[i].pid);
408 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 409 obj->gtt_offset);
ab0e7ff9
CW		 410 print_error_obj(m, obj);
411 }
412
413 obj = error->ring[i].wa_batchbuffer;
414 if (obj) {
415 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
416 dev_priv->ring[i].name, obj->gtt_offset);
417 print_error_obj(m, obj);
84734a04
MK		 418 }
419
420 if (error->ring[i].num_requests) {
421 err_printf(m, "%s --- %d requests\n",
422 dev_priv->ring[i].name,
423 error->ring[i].num_requests);
424 for (j = 0; j < error->ring[i].num_requests; j++) {
425 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
426 error->ring[i].requests[j].seqno,
427 error->ring[i].requests[j].jiffies,
428 error->ring[i].requests[j].tail);
429 }
430 }
431
432 if ((obj = error->ring[i].ringbuffer)) {
433 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
434 dev_priv->ring[i].name,
435 obj->gtt_offset);
ab0e7ff9 436 print_error_obj(m, obj);
84734a04
MK		 437 }
438
362b8af7 439 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 440 err_printf(m, "%s --- HW Status = 0x%08x\n",
441 dev_priv->ring[i].name,
442 obj->gtt_offset);
443 offset = 0;
444 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
445 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
446 offset,
447 obj->pages[0][elt],
448 obj->pages[0][elt+1],
449 obj->pages[0][elt+2],
450 obj->pages[0][elt+3]);
451 offset += 16;
452 }
453 }
454
372fbb8e 455 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 456 err_printf(m, "%s --- HW Context = 0x%08x\n",
457 dev_priv->ring[i].name,
458 obj->gtt_offset);
17d36749 459 print_error_obj(m, obj);
84734a04
MK		 460 }
461 }
462
0ca36d78
BW		 463 if ((obj = error->semaphore_obj)) {
464 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
465 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
466 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
467 elt * 4,
468 obj->pages[0][elt],
469 obj->pages[0][elt+1],
470 obj->pages[0][elt+2],
471 obj->pages[0][elt+3]);
472 }
473 }
474
84734a04
MK		 475 if (error->overlay)
476 intel_overlay_print_error_state(m, error->overlay);
477
478 if (error->display)
479 intel_display_print_error_state(m, dev, error->display);
480
481out:
482 if (m->bytes == 0 && m->err)
483 return m->err;
484
485 return 0;
486}
487
488int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
489 size_t count, loff_t pos)
490{
491 memset(ebuf, 0, sizeof(*ebuf));
492
493 /* We need to have enough room to store any i915_error_state printf
494 * so that we can move it to start position.
495 */
496 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
497 ebuf->buf = kmalloc(ebuf->size,
498 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
499
500 if (ebuf->buf == NULL) {
501 ebuf->size = PAGE_SIZE;
502 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
503 }
504
505 if (ebuf->buf == NULL) {
506 ebuf->size = 128;
507 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
508 }
509
510 if (ebuf->buf == NULL)
511 return -ENOMEM;
512
513 ebuf->start = pos;
514
515 return 0;
516}
517
518static void i915_error_object_free(struct drm_i915_error_object *obj)
519{
520 int page;
521
522 if (obj == NULL)
523 return;
524
525 for (page = 0; page < obj->page_count; page++)
526 kfree(obj->pages[page]);
527
528 kfree(obj);
529}
530
531static void i915_error_state_free(struct kref *error_ref)
532{
533 struct drm_i915_error_state *error = container_of(error_ref,
534 typeof(*error), ref);
535 int i;
536
537 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
538 i915_error_object_free(error->ring[i].batchbuffer);
539 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 540 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 541 i915_error_object_free(error->ring[i].ctx);
542 kfree(error->ring[i].requests);
543 }
544
0ca36d78 545 i915_error_object_free(error->semaphore_obj);
84734a04
MK		 546 kfree(error->active_bo);
547 kfree(error->overlay);
548 kfree(error->display);
549 kfree(error);
550}
551
552static struct drm_i915_error_object *
553i915_error_object_create_sized(struct drm_i915_private *dev_priv,
554 struct drm_i915_gem_object *src,
a7b91078 555 struct i915_address_space *vm,
84734a04
MK		 556 const int num_pages)
557{
558 struct drm_i915_error_object *dst;
559 int i;
560 u32 reloc_offset;
561
562 if (src == NULL || src->pages == NULL)
563 return NULL;
564
565 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
566 if (dst == NULL)
567 return NULL;
568
a7b91078 569 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 570 for (i = 0; i < num_pages; i++) {
571 unsigned long flags;
572 void *d;
573
574 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
575 if (d == NULL)
576 goto unwind;
577
578 local_irq_save(flags);
8b6124a6
CW		 579 if (src->cache_level == I915_CACHE_NONE &&
580 reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 581 src->has_global_gtt_mapping &&
582 i915_is_ggtt(vm)) {
84734a04
MK		 583 void __iomem *s;
584
585 /* Simply ignore tiling or any overlapping fence.
586 * It's part of the error state, and this hopefully
587 * captures what the GPU read.
588 */
589
590 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
591 reloc_offset);
592 memcpy_fromio(d, s, PAGE_SIZE);
593 io_mapping_unmap_atomic(s);
594 } else if (src->stolen) {
595 unsigned long offset;
596
597 offset = dev_priv->mm.stolen_base;
598 offset += src->stolen->start;
599 offset += i << PAGE_SHIFT;
600
601 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
602 } else {
603 struct page *page;
604 void *s;
605
606 page = i915_gem_object_get_page(src, i);
607
608 drm_clflush_pages(&page, 1);
609
610 s = kmap_atomic(page);
611 memcpy(d, s, PAGE_SIZE);
612 kunmap_atomic(s);
613
614 drm_clflush_pages(&page, 1);
615 }
616 local_irq_restore(flags);
617
618 dst->pages[i] = d;
619
620 reloc_offset += PAGE_SIZE;
621 }
622 dst->page_count = num_pages;
623
624 return dst;
625
626unwind:
627 while (i--)
628 kfree(dst->pages[i]);
629 kfree(dst);
630 return NULL;
631}
a7b91078
BW		 632#define i915_error_object_create(dev_priv, src, vm) \
633 i915_error_object_create_sized((dev_priv), (src), (vm), \
634 (src)->base.size>>PAGE_SHIFT)
635
636#define i915_error_ggtt_object_create(dev_priv, src) \
637 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 638 (src)->base.size>>PAGE_SHIFT)
639
640static void capture_bo(struct drm_i915_error_buffer *err,
641 struct drm_i915_gem_object *obj)
642{
643 err->size = obj->base.size;
644 err->name = obj->base.name;
645 err->rseqno = obj->last_read_seqno;
646 err->wseqno = obj->last_write_seqno;
647 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
648 err->read_domains = obj->base.read_domains;
649 err->write_domain = obj->base.write_domain;
650 err->fence_reg = obj->fence_reg;
651 err->pinned = 0;
d7f46fc4 652 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 653 err->pinned = 1;
654 if (obj->user_pin_count > 0)
655 err->pinned = -1;
656 err->tiling = obj->tiling_mode;
657 err->dirty = obj->dirty;
658 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 659 err->userptr = obj->userptr.mm != NULL;
84734a04
MK		 660 err->ring = obj->ring ? obj->ring->id : -1;
661 err->cache_level = obj->cache_level;
662}
663
664static u32 capture_active_bo(struct drm_i915_error_buffer *err,
665 int count, struct list_head *head)
666{
ca191b13 667 struct i915_vma *vma;
84734a04
MK		 668 int i = 0;
669
ca191b13
BW		 670 list_for_each_entry(vma, head, mm_list) {
671 capture_bo(err++, vma->obj);
84734a04
MK		 672 if (++i == count)
673 break;
674 }
675
676 return i;
677}
678
679static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
680 int count, struct list_head *head)
681{
682 struct drm_i915_gem_object *obj;
683 int i = 0;
684
685 list_for_each_entry(obj, head, global_list) {
d7f46fc4 686 if (!i915_gem_obj_is_pinned(obj))
84734a04
MK		 687 continue;
688
689 capture_bo(err++, obj);
690 if (++i == count)
691 break;
692 }
693
694 return i;
695}
696
011cf577
BW		 697/* Generate a semi-unique error code. The code is not meant to have meaning, The
698 * code's only purpose is to try to prevent false duplicated bug reports by
699 * grossly estimating a GPU error state.
700 *
701 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
702 * the hang if we could strip the GTT offset information from it.
703 *
704 * It's only a small step better than a random number in its current form.
705 */
706static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 707 struct drm_i915_error_state *error,
708 int *ring_id)
011cf577
BW		 709{
710 uint32_t error_code = 0;
711 int i;
712
713 /* IPEHR would be an ideal way to detect errors, as it's the gross
714 * measure of "the command that hung." However, has some very common
715 * synchronization commands which almost always appear in the case
716 * strictly a client bug. Use instdone to differentiate those some.
717 */
cb383002
MK		 718 for (i = 0; i < I915_NUM_RINGS; i++) {
719 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
720 if (ring_id)
721 *ring_id = i;
722
011cf577 723 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 724 }
725 }
011cf577
BW		 726
727 return error_code;
728}
729
84734a04
MK		 730static void i915_gem_record_fences(struct drm_device *dev,
731 struct drm_i915_error_state *error)
732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 int i;
735
736 /* Fences */
737 switch (INTEL_INFO(dev)->gen) {
5ab31333 738 case 8:
84734a04
MK		 739 case 7:
740 case 6:
741 for (i = 0; i < dev_priv->num_fence_regs; i++)
742 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
743 break;
744 case 5:
745 case 4:
746 for (i = 0; i < 16; i++)
747 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
748 break;
749 case 3:
750 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
751 for (i = 0; i < 8; i++)
752 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
753 case 2:
754 for (i = 0; i < 8; i++)
755 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
756 break;
757
758 default:
759 BUG();
760 }
761}
762
87f85ebc 763
0ca36d78
BW		 764static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
765 struct drm_i915_error_state *error,
766 struct intel_engine_cs *ring,
767 struct drm_i915_error_ring *ering)
768{
b4558b46 769 struct intel_engine_cs *to;
0ca36d78
BW		 770 int i;
771
772 if (!i915_semaphore_is_enabled(dev_priv->dev))
773 return;
774
775 if (!error->semaphore_obj)
776 error->semaphore_obj =
777 i915_error_object_create(dev_priv,
778 dev_priv->semaphore_obj,
779 &dev_priv->gtt.base);
780
b4558b46
RV		 781 for_each_ring(to, dev_priv, i) {
782 int idx;
783 u16 signal_offset;
784 u32 *tmp;
0ca36d78 785
b4558b46
RV		 786 if (ring == to)
787 continue;
788
864c6181
RV		 789 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
790 / 4;
b4558b46
RV		 791 tmp = error->semaphore_obj->pages[0];
792 idx = intel_ring_sync_index(ring, to);
793
794 ering->semaphore_mboxes[idx] = tmp[signal_offset];
795 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
0ca36d78
BW		 796 }
797}
798
87f85ebc
BW		 799static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
800 struct intel_engine_cs *ring,
801 struct drm_i915_error_ring *ering)
802{
803 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
804 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
805 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
806 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
807
808 if (HAS_VEBOX(dev_priv->dev)) {
809 ering->semaphore_mboxes[2] =
810 I915_READ(RING_SYNC_2(ring->mmio_base));
811 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
812 }
813}
814
84734a04 815static void i915_record_ring_state(struct drm_device *dev,
0ca36d78 816 struct drm_i915_error_state *error,
a4872ba6 817 struct intel_engine_cs *ring,
362b8af7 818 struct drm_i915_error_ring *ering)
84734a04
MK		 819{
820 struct drm_i915_private *dev_priv = dev->dev_private;
821
822 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 823 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
824 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
0ca36d78
BW		 825 if (INTEL_INFO(dev)->gen >= 8)
826 gen8_record_semaphore_state(dev_priv, error, ring, ering);
827 else
828 gen6_record_semaphore_state(dev_priv, ring, ering);
4e5aabfd
BW		 829 }
830
84734a04 831 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 832 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
833 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
834 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
835 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
836 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
837 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 838 if (INTEL_INFO(dev)->gen >= 8) {
839 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 840 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 841 }
362b8af7 842 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 843 } else {
362b8af7
BW		 844 ering->faddr = I915_READ(DMA_FADD_I8XX);
845 ering->ipeir = I915_READ(IPEIR);
846 ering->ipehr = I915_READ(IPEHR);
847 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 848 }
849
362b8af7
BW		 850 ering->waiting = waitqueue_active(&ring->irq_queue);
851 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
852 ering->seqno = ring->get_seqno(ring, false);
853 ering->acthd = intel_ring_get_active_head(ring);
854 ering->head = I915_READ_HEAD(ring);
855 ering->tail = I915_READ_TAIL(ring);
856 ering->ctl = I915_READ_CTL(ring);
84734a04 857
f3ce3821
CW		 858 if (I915_NEED_GFX_HWS(dev)) {
859 int mmio;
860
861 if (IS_GEN7(dev)) {
862 switch (ring->id) {
863 default:
864 case RCS:
865 mmio = RENDER_HWS_PGA_GEN7;
866 break;
867 case BCS:
868 mmio = BLT_HWS_PGA_GEN7;
869 break;
870 case VCS:
871 mmio = BSD_HWS_PGA_GEN7;
872 break;
873 case VECS:
874 mmio = VEBOX_HWS_PGA_GEN7;
875 break;
876 }
877 } else if (IS_GEN6(ring->dev)) {
878 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
879 } else {
880 /* XXX: gen8 returns to sanity */
881 mmio = RING_HWS_PGA(ring->mmio_base);
882 }
883
362b8af7 884 ering->hws = I915_READ(mmio);
f3ce3821
CW		 885 }
886
ee1b1e5e
OM		 887 ering->cpu_ring_head = ring->buffer->head;
888 ering->cpu_ring_tail = ring->buffer->tail;
da661464 889
362b8af7
BW		 890 ering->hangcheck_score = ring->hangcheck.score;
891 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 892
893 if (USES_PPGTT(dev)) {
894 int i;
895
896 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
897
898 switch (INTEL_INFO(dev)->gen) {
899 case 8:
900 for (i = 0; i < 4; i++) {
901 ering->vm_info.pdp[i] =
902 I915_READ(GEN8_RING_PDP_UDW(ring, i));
903 ering->vm_info.pdp[i] <<= 32;
904 ering->vm_info.pdp[i] |=
905 I915_READ(GEN8_RING_PDP_LDW(ring, i));
906 }
907 break;
908 case 7:
ae89f44d
BW		 909 ering->vm_info.pp_dir_base =
910 I915_READ(RING_PP_DIR_BASE(ring));
6c7a01ec
BW		 911 break;
912 case 6:
ae89f44d
BW		 913 ering->vm_info.pp_dir_base =
914 I915_READ(RING_PP_DIR_BASE_READ(ring));
6c7a01ec
BW		 915 break;
916 }
917 }
84734a04
MK		 918}
919
920
a4872ba6 921static void i915_gem_record_active_context(struct intel_engine_cs *ring,
84734a04
MK		 922 struct drm_i915_error_state *error,
923 struct drm_i915_error_ring *ering)
924{
925 struct drm_i915_private *dev_priv = ring->dev->dev_private;
926 struct drm_i915_gem_object *obj;
927
928 /* Currently render ring is the only HW context user */
929 if (ring->id != RCS || !error->ccid)
930 return;
931
932 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
36362ad3
BW		 933 if (!i915_gem_obj_ggtt_bound(obj))
934 continue;
935
84734a04 936 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
17d36749 937 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 938 break;
939 }
940 }
941}
942
943static void i915_gem_record_rings(struct drm_device *dev,
944 struct drm_i915_error_state *error)
945{
946 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 947 struct drm_i915_gem_request *request;
948 int i, count;
949
372fbb8e 950 for (i = 0; i < I915_NUM_RINGS; i++) {
a4872ba6 951 struct intel_engine_cs *ring = &dev_priv->ring[i];
372fbb8e 952
eee73b46
CW		 953 error->ring[i].pid = -1;
954
372fbb8e
CW		 955 if (ring->dev == NULL)
956 continue;
957
958 error->ring[i].valid = true;
959
0ca36d78 960 i915_record_ring_state(dev, error, ring, &error->ring[i]);
84734a04 961
ab0e7ff9
CW		 962 request = i915_gem_find_active_request(ring);
963 if (request) {
964 /* We need to copy these to an anonymous buffer
965 * as the simplest method to avoid being overwritten
966 * by userspace.
967 */
968 error->ring[i].batchbuffer =
969 i915_error_object_create(dev_priv,
970 request->batch_obj,
971 request->ctx ?
972 request->ctx->vm :
973 &dev_priv->gtt.base);
974
975 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
976 ring->scratch.obj)
977 error->ring[i].wa_batchbuffer =
978 i915_error_ggtt_object_create(dev_priv,
979 ring->scratch.obj);
980
981 if (request->file_priv) {
982 struct task_struct *task;
983
984 rcu_read_lock();
985 task = pid_task(request->file_priv->file->pid,
986 PIDTYPE_PID);
987 if (task) {
988 strcpy(error->ring[i].comm, task->comm);
989 error->ring[i].pid = task->pid;
990 }
991 rcu_read_unlock();
992 }
993 }
84734a04
MK		 994
995 error->ring[i].ringbuffer =
ee1b1e5e 996 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj);
84734a04 997
f3ce3821 998 if (ring->status_page.obj)
362b8af7 999 error->ring[i].hws_page =
f3ce3821 1000 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 1001
1002 i915_gem_record_active_context(ring, error, &error->ring[i]);
1003
1004 count = 0;
1005 list_for_each_entry(request, &ring->request_list, list)
1006 count++;
1007
1008 error->ring[i].num_requests = count;
1009 error->ring[i].requests =
a1e22653 1010 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 1011 GFP_ATOMIC);
1012 if (error->ring[i].requests == NULL) {
1013 error->ring[i].num_requests = 0;
1014 continue;
1015 }
1016
1017 count = 0;
1018 list_for_each_entry(request, &ring->request_list, list) {
1019 struct drm_i915_error_request *erq;
1020
1021 erq = &error->ring[i].requests[count++];
1022 erq->seqno = request->seqno;
1023 erq->jiffies = request->emitted_jiffies;
1024 erq->tail = request->tail;
1025 }
1026 }
1027}
1028
95f5301d
BW		 1029/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1030 * VM.
1031 */
1032static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1033 struct drm_i915_error_state *error,
1034 struct i915_address_space *vm,
1035 const int ndx)
84734a04 1036{
95f5301d 1037 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 1038 struct drm_i915_gem_object *obj;
95f5301d 1039 struct i915_vma *vma;
84734a04
MK		 1040 int i;
1041
1042 i = 0;
ca191b13 1043 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 1044 i++;
95f5301d 1045 error->active_bo_count[ndx] = i;
84734a04 1046 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
d7f46fc4 1047 if (i915_gem_obj_is_pinned(obj))
84734a04 1048 i++;
95f5301d 1049 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 1050
1051 if (i) {
a1e22653 1052 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 1053 if (active_bo)
1054 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1055 }
1056
95f5301d
BW		 1057 if (active_bo)
1058 error->active_bo_count[ndx] =
1059 capture_active_bo(active_bo,
1060 error->active_bo_count[ndx],
5cef07e1 1061 &vm->active_list);
84734a04 1062
95f5301d
BW		 1063 if (pinned_bo)
1064 error->pinned_bo_count[ndx] =
1065 capture_pinned_bo(pinned_bo,
1066 error->pinned_bo_count[ndx],
84734a04 1067 &dev_priv->mm.bound_list);
95f5301d
BW		 1068 error->active_bo[ndx] = active_bo;
1069 error->pinned_bo[ndx] = pinned_bo;
1070}
1071
1072static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1073 struct drm_i915_error_state *error)
1074{
1075 struct i915_address_space *vm;
1076 int cnt = 0, i = 0;
1077
1078 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1079 cnt++;
1080
95f5301d
BW		 1081 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1082 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1083 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1084 GFP_ATOMIC);
1085 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1086 GFP_ATOMIC);
1087
1088 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1089 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 1090}
1091
1d762aad
BW		 1092/* Capture all registers which don't fit into another category. */
1093static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1094 struct drm_i915_error_state *error)
84734a04 1095{
1d762aad 1096 struct drm_device *dev = dev_priv->dev;
84734a04 1097
654c90c6
BW		 1098 /* General organization
1099 * 1. Registers specific to a single generation
1100 * 2. Registers which belong to multiple generations
1101 * 3. Feature specific registers.
1102 * 4. Everything else
1103 * Please try to follow the order.
1104 */
84734a04 1105
654c90c6
BW		 1106 /* 1: Registers specific to a single generation */
1107 if (IS_VALLEYVIEW(dev)) {
843db716
RV		 1108 error->gtier = I915_READ(GTIER);
1109 error->ier = I915_READ(VLV_IER);
654c90c6
BW		 1110 error->forcewake = I915_READ(FORCEWAKE_VLV);
1111 }
84734a04 1112
654c90c6
BW		 1113 if (IS_GEN7(dev))
1114 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1115
91ec5d11 1116 if (IS_GEN6(dev)) {
84734a04 1117 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1118 error->gab_ctl = I915_READ(GAB_CTL);
1119 error->gfx_mode = I915_READ(GFX_MODE);
1120 }
84734a04 1121
654c90c6
BW		 1122 /* 2: Registers which belong to multiple generations */
1123 if (INTEL_INFO(dev)->gen >= 7)
1124 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1125
1126 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1127 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1128 error->error = I915_READ(ERROR_GEN6);
1129 error->done_reg = I915_READ(DONE_REG);
1130 }
1131
654c90c6 1132 /* 3: Feature specific registers */
91ec5d11
BW		 1133 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1134 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1135 error->gac_eco = I915_READ(GAC_ECO_BITS);
1136 }
1137
1138 /* 4: Everything else */
654c90c6
BW		 1139 if (HAS_HW_CONTEXTS(dev))
1140 error->ccid = I915_READ(CCID);
1141
843db716
RV		 1142 if (HAS_PCH_SPLIT(dev)) {
1143 error->ier = I915_READ(DEIER);
1144 error->gtier = I915_READ(GTIER);
1145 } else if (IS_GEN2(dev)) {
1146 error->ier = I915_READ16(IER);
1147 } else if (!IS_VALLEYVIEW(dev)) {
1148 error->ier = I915_READ(IER);
654c90c6 1149 }
654c90c6
BW		 1150 error->eir = I915_READ(EIR);
1151 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1152
1153 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1154}
1155
cb383002 1156static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1157 struct drm_i915_error_state *error,
1158 bool wedged,
1159 const char *error_msg)
cb383002
MK		 1160{
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 ecode;
58174462 1163 int ring_id = -1, len;
cb383002
MK		 1164
1165 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1166
58174462
MK		 1167 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1168 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1169
1170 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1171 len += scnprintf(error->error_msg + len,
1172 sizeof(error->error_msg) - len,
1173 ", in %s [%d]",
1174 error->ring[ring_id].comm,
1175 error->ring[ring_id].pid);
1176
1177 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1178 ", reason: %s, action: %s",
1179 error_msg,
1180 wedged ? "reset" : "continue");
cb383002
MK		 1181}
1182
48b031e3
MK		 1183static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1184 struct drm_i915_error_state *error)
1185{
1186 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1187 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1188}
1189
1d762aad
BW		 1190/**
1191 * i915_capture_error_state - capture an error record for later analysis
1192 * @dev: drm device
1193 *
1194 * Should be called when an error is detected (either a hang or an error
1195 * interrupt) to capture error state from the time of the error. Fills
1196 * out a structure which becomes available in debugfs for user level tools
1197 * to pick up.
1198 */
58174462
MK		 1199void i915_capture_error_state(struct drm_device *dev, bool wedged,
1200 const char *error_msg)
1d762aad 1201{
53a4c6b2 1202 static bool warned;
1d762aad
BW		 1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 struct drm_i915_error_state *error;
1205 unsigned long flags;
1d762aad
BW		 1206
1207 /* Account for pipe specific data like PIPE*STAT */
1208 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1209 if (!error) {
1210 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1211 return;
1212 }
1213
011cf577
BW		 1214 kref_init(&error->ref);
1215
48b031e3 1216 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1217 i915_capture_reg_state(dev_priv, error);
1218 i915_gem_capture_buffers(dev_priv, error);
1219 i915_gem_record_fences(dev, error);
1220 i915_gem_record_rings(dev, error);
1d762aad 1221
84734a04
MK		 1222 do_gettimeofday(&error->time);
1223
1224 error->overlay = intel_overlay_capture_error_state(dev);
1225 error->display = intel_display_capture_error_state(dev);
1226
58174462 1227 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1228 DRM_INFO("%s\n", error->error_msg);
1229
84734a04
MK		 1230 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1231 if (dev_priv->gpu_error.first_error == NULL) {
1232 dev_priv->gpu_error.first_error = error;
1233 error = NULL;
1234 }
1235 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1236
cb383002 1237 if (error) {
84734a04 1238 i915_error_state_free(&error->ref);
cb383002
MK		 1239 return;
1240 }
1241
1242 if (!warned) {
1243 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1244 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1245 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1246 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1247 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1248 warned = true;
1249 }
84734a04
MK		 1250}
1251
1252void i915_error_state_get(struct drm_device *dev,
1253 struct i915_error_state_file_priv *error_priv)
1254{
1255 struct drm_i915_private *dev_priv = dev->dev_private;
1256 unsigned long flags;
1257
1258 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1259 error_priv->error = dev_priv->gpu_error.first_error;
1260 if (error_priv->error)
1261 kref_get(&error_priv->error->ref);
1262 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1263
1264}
1265
1266void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1267{
1268 if (error_priv->error)
1269 kref_put(&error_priv->error->ref, i915_error_state_free);
1270}
1271
1272void i915_destroy_error_state(struct drm_device *dev)
1273{
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 struct drm_i915_error_state *error;
1276 unsigned long flags;
1277
1278 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1279 error = dev_priv->gpu_error.first_error;
1280 dev_priv->gpu_error.first_error = NULL;
1281 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1282
1283 if (error)
1284 kref_put(&error->ref, i915_error_state_free);
1285}
1286
1287const char *i915_cache_level_str(int type)
1288{
1289 switch (type) {
1290 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1291 case I915_CACHE_LLC: return " snooped or LLC";
1292 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1293 case I915_CACHE_WT: return " WT";
84734a04
MK		 1294 default: return "";
1295 }
1296}
1297
1298/* NB: please notice the memset */
1299void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1300{
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1303
1304 switch (INTEL_INFO(dev)->gen) {
1305 case 2:
1306 case 3:
1307 instdone[0] = I915_READ(INSTDONE);
1308 break;
1309 case 4:
1310 case 5:
1311 case 6:
1312 instdone[0] = I915_READ(INSTDONE_I965);
1313 instdone[1] = I915_READ(INSTDONE1);
1314 break;
1315 default:
1316 WARN_ONCE(1, "Unsupported platform\n");
1317 case 7:
d0582ed2 1318 case 8:
84734a04
MK		 1319 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1320 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1321 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1322 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1323 break;
1324 }
1325}
Linux kernel - Deliverables
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