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drm/i915: Add reset count to error state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
e29bb4eb
CW		 146 va_list tmp;
147
148 va_copy(tmp, args);
149 if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp)))
84734a04
MK		 150 return;
151 }
152
153 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
154 if (len >= e->size - e->bytes)
155 len = e->size - e->bytes - 1;
156
157 __i915_error_advance(e, len);
158}
159
160static void i915_error_puts(struct drm_i915_error_state_buf *e,
161 const char *str)
162{
163 unsigned len;
164
165 if (!__i915_error_ok(e))
166 return;
167
168 len = strlen(str);
169
170 /* Seek the first printf which is hits start position */
171 if (e->pos < e->start) {
172 if (!__i915_error_seek(e, len))
173 return;
174 }
175
176 if (len >= e->size - e->bytes)
177 len = e->size - e->bytes - 1;
178 memcpy(e->buf + e->bytes, str, len);
179
180 __i915_error_advance(e, len);
181}
182
183#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
184#define err_puts(e, s) i915_error_puts(e, s)
185
186static void print_error_buffers(struct drm_i915_error_state_buf *m,
187 const char *name,
188 struct drm_i915_error_buffer *err,
189 int count)
190{
191 err_printf(m, "%s [%d]:\n", name, count);
192
193 while (count--) {
194 err_printf(m, " %08x %8u %02x %02x %x %x",
195 err->gtt_offset,
196 err->size,
197 err->read_domains,
198 err->write_domain,
199 err->rseqno, err->wseqno);
200 err_puts(m, pin_flag(err->pinned));
201 err_puts(m, tiling_flag(err->tiling));
202 err_puts(m, dirty_flag(err->dirty));
203 err_puts(m, purgeable_flag(err->purgeable));
204 err_puts(m, err->ring != -1 ? " " : "");
205 err_puts(m, ring_str(err->ring));
206 err_puts(m, i915_cache_level_str(err->cache_level));
207
208 if (err->name)
209 err_printf(m, " (name: %d)", err->name);
210 if (err->fence_reg != I915_FENCE_REG_NONE)
211 err_printf(m, " (fence: %d)", err->fence_reg);
212
213 err_puts(m, "\n");
214 err++;
215 }
216}
217
da661464
MK		 218static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
219{
220 switch (a) {
221 case HANGCHECK_IDLE:
222 return "idle";
223 case HANGCHECK_WAIT:
224 return "wait";
225 case HANGCHECK_ACTIVE:
226 return "active";
227 case HANGCHECK_KICK:
228 return "kick";
229 case HANGCHECK_HUNG:
230 return "hung";
231 }
232
233 return "unknown";
234}
235
84734a04
MK		 236static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
237 struct drm_device *dev,
362b8af7 238 struct drm_i915_error_ring *ring)
84734a04 239{
362b8af7 240 if (!ring->valid)
372fbb8e
CW		 241 return;
242
362b8af7
BW		 243 err_printf(m, " HEAD: 0x%08x\n", ring->head);
244 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
245 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
246 err_printf(m, " HWS: 0x%08x\n", ring->hws);
247 err_printf(m, " ACTHD: 0x%08x\n", ring->acthd);
248 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
249 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
250 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 251 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 252 err_printf(m, " BBADDR: 0x%08llx\n", ring->bbaddr);
253 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
254 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 255 }
362b8af7
BW		 256 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
257 err_printf(m, " FADDR: 0x%08x\n", ring->faddr);
84734a04 258 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 259 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
260 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 261 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 262 ring->semaphore_mboxes[0],
263 ring->semaphore_seqno[0]);
84734a04 264 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 265 ring->semaphore_mboxes[1],
266 ring->semaphore_seqno[1]);
4e5aabfd
BW		 267 if (HAS_VEBOX(dev)) {
268 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 269 ring->semaphore_mboxes[2],
270 ring->semaphore_seqno[2]);
4e5aabfd 271 }
84734a04 272 }
6c7a01ec
BW		 273 if (USES_PPGTT(dev)) {
274 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
275
276 if (INTEL_INFO(dev)->gen >= 8) {
277 int i;
278 for (i = 0; i < 4; i++)
279 err_printf(m, " PDP%d: 0x%016llx\n",
280 i, ring->vm_info.pdp[i]);
281 } else {
282 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
283 ring->vm_info.pp_dir_base);
284 }
285 }
362b8af7
BW		 286 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
287 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
288 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
289 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 290 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 291 hangcheck_action_to_str(ring->hangcheck_action),
292 ring->hangcheck_score);
84734a04
MK		 293}
294
295void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
296{
297 va_list args;
298
299 va_start(args, f);
300 i915_error_vprintf(e, f, args);
301 va_end(args);
302}
303
ab0e7ff9
CW		 304static void print_error_obj(struct drm_i915_error_state_buf *m,
305 struct drm_i915_error_object *obj)
306{
307 int page, offset, elt;
308
309 for (page = offset = 0; page < obj->page_count; page++) {
310 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
311 err_printf(m, "%08x : %08x\n", offset,
312 obj->pages[page][elt]);
313 offset += 4;
314 }
315 }
316}
317
84734a04
MK		 318int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
319 const struct i915_error_state_file_priv *error_priv)
320{
321 struct drm_device *dev = error_priv->dev;
322 drm_i915_private_t *dev_priv = dev->dev_private;
323 struct drm_i915_error_state *error = error_priv->error;
ab0e7ff9
CW		 324 int i, j, offset, elt;
325 int max_hangcheck_score;
84734a04
MK		 326
327 if (!error) {
328 err_printf(m, "no error state collected\n");
329 goto out;
330 }
331
cb383002 332 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 333 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
334 error->time.tv_usec);
335 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 336 max_hangcheck_score = 0;
337 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
338 if (error->ring[i].hangcheck_score > max_hangcheck_score)
339 max_hangcheck_score = error->ring[i].hangcheck_score;
340 }
341 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
342 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
343 error->ring[i].pid != -1) {
344 err_printf(m, "Active process (on ring %s): %s [%d]\n",
345 ring_str(i),
346 error->ring[i].comm,
347 error->ring[i].pid);
348 }
349 }
48b031e3 350 err_printf(m, "Reset count: %u\n", error->reset_count);
ffbab09b 351 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 352 err_printf(m, "EIR: 0x%08x\n", error->eir);
353 err_printf(m, "IER: 0x%08x\n", error->ier);
354 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
355 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
356 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
357 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 358 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 359
360 for (i = 0; i < dev_priv->num_fence_regs; i++)
361 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
362
363 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
364 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
365 error->extra_instdone[i]);
366
367 if (INTEL_INFO(dev)->gen >= 6) {
368 err_printf(m, "ERROR: 0x%08x\n", error->error);
369 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
370 }
371
372 if (INTEL_INFO(dev)->gen == 7)
373 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
374
362b8af7
BW		 375 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
376 err_printf(m, "%s command stream:\n", ring_str(i));
377 i915_ring_error_state(m, dev, &error->ring[i]);
378 }
84734a04
MK		 379
380 if (error->active_bo)
381 print_error_buffers(m, "Active",
95f5301d
BW		 382 error->active_bo[0],
383 error->active_bo_count[0]);
84734a04
MK		 384
385 if (error->pinned_bo)
386 print_error_buffers(m, "Pinned",
95f5301d
BW		 387 error->pinned_bo[0],
388 error->pinned_bo_count[0]);
84734a04
MK		 389
390 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
391 struct drm_i915_error_object *obj;
392
ab0e7ff9
CW		 393 obj = error->ring[i].batchbuffer;
394 if (obj) {
395 err_puts(m, dev_priv->ring[i].name);
396 if (error->ring[i].pid != -1)
397 err_printf(m, " (submitted by %s [%d])",
398 error->ring[i].comm,
399 error->ring[i].pid);
400 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 401 obj->gtt_offset);
ab0e7ff9
CW		 402 print_error_obj(m, obj);
403 }
404
405 obj = error->ring[i].wa_batchbuffer;
406 if (obj) {
407 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
408 dev_priv->ring[i].name, obj->gtt_offset);
409 print_error_obj(m, obj);
84734a04
MK		 410 }
411
412 if (error->ring[i].num_requests) {
413 err_printf(m, "%s --- %d requests\n",
414 dev_priv->ring[i].name,
415 error->ring[i].num_requests);
416 for (j = 0; j < error->ring[i].num_requests; j++) {
417 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
418 error->ring[i].requests[j].seqno,
419 error->ring[i].requests[j].jiffies,
420 error->ring[i].requests[j].tail);
421 }
422 }
423
424 if ((obj = error->ring[i].ringbuffer)) {
425 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
426 dev_priv->ring[i].name,
427 obj->gtt_offset);
ab0e7ff9 428 print_error_obj(m, obj);
84734a04
MK		 429 }
430
362b8af7 431 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 432 err_printf(m, "%s --- HW Status = 0x%08x\n",
433 dev_priv->ring[i].name,
434 obj->gtt_offset);
435 offset = 0;
436 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
437 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
438 offset,
439 obj->pages[0][elt],
440 obj->pages[0][elt+1],
441 obj->pages[0][elt+2],
442 obj->pages[0][elt+3]);
443 offset += 16;
444 }
445 }
446
372fbb8e 447 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 448 err_printf(m, "%s --- HW Context = 0x%08x\n",
449 dev_priv->ring[i].name,
450 obj->gtt_offset);
451 offset = 0;
452 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
453 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
454 offset,
455 obj->pages[0][elt],
456 obj->pages[0][elt+1],
457 obj->pages[0][elt+2],
458 obj->pages[0][elt+3]);
459 offset += 16;
460 }
461 }
462 }
463
464 if (error->overlay)
465 intel_overlay_print_error_state(m, error->overlay);
466
467 if (error->display)
468 intel_display_print_error_state(m, dev, error->display);
469
470out:
471 if (m->bytes == 0 && m->err)
472 return m->err;
473
474 return 0;
475}
476
477int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
478 size_t count, loff_t pos)
479{
480 memset(ebuf, 0, sizeof(*ebuf));
481
482 /* We need to have enough room to store any i915_error_state printf
483 * so that we can move it to start position.
484 */
485 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
486 ebuf->buf = kmalloc(ebuf->size,
487 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
488
489 if (ebuf->buf == NULL) {
490 ebuf->size = PAGE_SIZE;
491 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
492 }
493
494 if (ebuf->buf == NULL) {
495 ebuf->size = 128;
496 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
497 }
498
499 if (ebuf->buf == NULL)
500 return -ENOMEM;
501
502 ebuf->start = pos;
503
504 return 0;
505}
506
507static void i915_error_object_free(struct drm_i915_error_object *obj)
508{
509 int page;
510
511 if (obj == NULL)
512 return;
513
514 for (page = 0; page < obj->page_count; page++)
515 kfree(obj->pages[page]);
516
517 kfree(obj);
518}
519
520static void i915_error_state_free(struct kref *error_ref)
521{
522 struct drm_i915_error_state *error = container_of(error_ref,
523 typeof(*error), ref);
524 int i;
525
526 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
527 i915_error_object_free(error->ring[i].batchbuffer);
528 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 529 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 530 i915_error_object_free(error->ring[i].ctx);
531 kfree(error->ring[i].requests);
532 }
533
534 kfree(error->active_bo);
535 kfree(error->overlay);
536 kfree(error->display);
537 kfree(error);
538}
539
540static struct drm_i915_error_object *
541i915_error_object_create_sized(struct drm_i915_private *dev_priv,
542 struct drm_i915_gem_object *src,
a7b91078 543 struct i915_address_space *vm,
84734a04
MK		 544 const int num_pages)
545{
546 struct drm_i915_error_object *dst;
547 int i;
548 u32 reloc_offset;
549
550 if (src == NULL || src->pages == NULL)
551 return NULL;
552
553 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
554 if (dst == NULL)
555 return NULL;
556
a7b91078 557 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 558 for (i = 0; i < num_pages; i++) {
559 unsigned long flags;
560 void *d;
561
562 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
563 if (d == NULL)
564 goto unwind;
565
566 local_irq_save(flags);
8b6124a6
CW		 567 if (src->cache_level == I915_CACHE_NONE &&
568 reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 569 src->has_global_gtt_mapping &&
570 i915_is_ggtt(vm)) {
84734a04
MK		 571 void __iomem *s;
572
573 /* Simply ignore tiling or any overlapping fence.
574 * It's part of the error state, and this hopefully
575 * captures what the GPU read.
576 */
577
578 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
579 reloc_offset);
580 memcpy_fromio(d, s, PAGE_SIZE);
581 io_mapping_unmap_atomic(s);
582 } else if (src->stolen) {
583 unsigned long offset;
584
585 offset = dev_priv->mm.stolen_base;
586 offset += src->stolen->start;
587 offset += i << PAGE_SHIFT;
588
589 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
590 } else {
591 struct page *page;
592 void *s;
593
594 page = i915_gem_object_get_page(src, i);
595
596 drm_clflush_pages(&page, 1);
597
598 s = kmap_atomic(page);
599 memcpy(d, s, PAGE_SIZE);
600 kunmap_atomic(s);
601
602 drm_clflush_pages(&page, 1);
603 }
604 local_irq_restore(flags);
605
606 dst->pages[i] = d;
607
608 reloc_offset += PAGE_SIZE;
609 }
610 dst->page_count = num_pages;
611
612 return dst;
613
614unwind:
615 while (i--)
616 kfree(dst->pages[i]);
617 kfree(dst);
618 return NULL;
619}
a7b91078
BW		 620#define i915_error_object_create(dev_priv, src, vm) \
621 i915_error_object_create_sized((dev_priv), (src), (vm), \
622 (src)->base.size>>PAGE_SHIFT)
623
624#define i915_error_ggtt_object_create(dev_priv, src) \
625 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 626 (src)->base.size>>PAGE_SHIFT)
627
628static void capture_bo(struct drm_i915_error_buffer *err,
629 struct drm_i915_gem_object *obj)
630{
631 err->size = obj->base.size;
632 err->name = obj->base.name;
633 err->rseqno = obj->last_read_seqno;
634 err->wseqno = obj->last_write_seqno;
635 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
636 err->read_domains = obj->base.read_domains;
637 err->write_domain = obj->base.write_domain;
638 err->fence_reg = obj->fence_reg;
639 err->pinned = 0;
d7f46fc4 640 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 641 err->pinned = 1;
642 if (obj->user_pin_count > 0)
643 err->pinned = -1;
644 err->tiling = obj->tiling_mode;
645 err->dirty = obj->dirty;
646 err->purgeable = obj->madv != I915_MADV_WILLNEED;
647 err->ring = obj->ring ? obj->ring->id : -1;
648 err->cache_level = obj->cache_level;
649}
650
651static u32 capture_active_bo(struct drm_i915_error_buffer *err,
652 int count, struct list_head *head)
653{
ca191b13 654 struct i915_vma *vma;
84734a04
MK		 655 int i = 0;
656
ca191b13
BW		 657 list_for_each_entry(vma, head, mm_list) {
658 capture_bo(err++, vma->obj);
84734a04
MK		 659 if (++i == count)
660 break;
661 }
662
663 return i;
664}
665
666static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
667 int count, struct list_head *head)
668{
669 struct drm_i915_gem_object *obj;
670 int i = 0;
671
672 list_for_each_entry(obj, head, global_list) {
d7f46fc4 673 if (!i915_gem_obj_is_pinned(obj))
84734a04
MK		 674 continue;
675
676 capture_bo(err++, obj);
677 if (++i == count)
678 break;
679 }
680
681 return i;
682}
683
011cf577
BW		 684/* Generate a semi-unique error code. The code is not meant to have meaning, The
685 * code's only purpose is to try to prevent false duplicated bug reports by
686 * grossly estimating a GPU error state.
687 *
688 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
689 * the hang if we could strip the GTT offset information from it.
690 *
691 * It's only a small step better than a random number in its current form.
692 */
693static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 694 struct drm_i915_error_state *error,
695 int *ring_id)
011cf577
BW		 696{
697 uint32_t error_code = 0;
698 int i;
699
700 /* IPEHR would be an ideal way to detect errors, as it's the gross
701 * measure of "the command that hung." However, has some very common
702 * synchronization commands which almost always appear in the case
703 * strictly a client bug. Use instdone to differentiate those some.
704 */
cb383002
MK		 705 for (i = 0; i < I915_NUM_RINGS; i++) {
706 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
707 if (ring_id)
708 *ring_id = i;
709
011cf577 710 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 711 }
712 }
011cf577
BW		 713
714 return error_code;
715}
716
84734a04
MK		 717static void i915_gem_record_fences(struct drm_device *dev,
718 struct drm_i915_error_state *error)
719{
720 struct drm_i915_private *dev_priv = dev->dev_private;
721 int i;
722
723 /* Fences */
724 switch (INTEL_INFO(dev)->gen) {
5ab31333 725 case 8:
84734a04
MK		 726 case 7:
727 case 6:
728 for (i = 0; i < dev_priv->num_fence_regs; i++)
729 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
730 break;
731 case 5:
732 case 4:
733 for (i = 0; i < 16; i++)
734 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
735 break;
736 case 3:
737 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
738 for (i = 0; i < 8; i++)
739 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
740 case 2:
741 for (i = 0; i < 8; i++)
742 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
743 break;
744
745 default:
746 BUG();
747 }
748}
749
84734a04 750static void i915_record_ring_state(struct drm_device *dev,
362b8af7
BW		 751 struct intel_ring_buffer *ring,
752 struct drm_i915_error_ring *ering)
84734a04
MK		 753{
754 struct drm_i915_private *dev_priv = dev->dev_private;
755
756 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 757 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
758 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
759 ering->semaphore_mboxes[0]
84734a04 760 = I915_READ(RING_SYNC_0(ring->mmio_base));
362b8af7 761 ering->semaphore_mboxes[1]
84734a04 762 = I915_READ(RING_SYNC_1(ring->mmio_base));
362b8af7
BW		 763 ering->semaphore_seqno[0] = ring->sync_seqno[0];
764 ering->semaphore_seqno[1] = ring->sync_seqno[1];
84734a04
MK		 765 }
766
4e5aabfd 767 if (HAS_VEBOX(dev)) {
362b8af7 768 ering->semaphore_mboxes[2] =
4e5aabfd 769 I915_READ(RING_SYNC_2(ring->mmio_base));
362b8af7 770 ering->semaphore_seqno[2] = ring->sync_seqno[2];
4e5aabfd
BW		 771 }
772
84734a04 773 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 774 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
775 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
776 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
777 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
778 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
779 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
3dda20a9 780 if (INTEL_INFO(dev)->gen >= 8)
362b8af7
BW		 781 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
782 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 783 } else {
362b8af7
BW		 784 ering->faddr = I915_READ(DMA_FADD_I8XX);
785 ering->ipeir = I915_READ(IPEIR);
786 ering->ipehr = I915_READ(IPEHR);
787 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 788 }
789
362b8af7
BW		 790 ering->waiting = waitqueue_active(&ring->irq_queue);
791 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
792 ering->seqno = ring->get_seqno(ring, false);
793 ering->acthd = intel_ring_get_active_head(ring);
794 ering->head = I915_READ_HEAD(ring);
795 ering->tail = I915_READ_TAIL(ring);
796 ering->ctl = I915_READ_CTL(ring);
84734a04 797
f3ce3821
CW		 798 if (I915_NEED_GFX_HWS(dev)) {
799 int mmio;
800
801 if (IS_GEN7(dev)) {
802 switch (ring->id) {
803 default:
804 case RCS:
805 mmio = RENDER_HWS_PGA_GEN7;
806 break;
807 case BCS:
808 mmio = BLT_HWS_PGA_GEN7;
809 break;
810 case VCS:
811 mmio = BSD_HWS_PGA_GEN7;
812 break;
813 case VECS:
814 mmio = VEBOX_HWS_PGA_GEN7;
815 break;
816 }
817 } else if (IS_GEN6(ring->dev)) {
818 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
819 } else {
820 /* XXX: gen8 returns to sanity */
821 mmio = RING_HWS_PGA(ring->mmio_base);
822 }
823
362b8af7 824 ering->hws = I915_READ(mmio);
f3ce3821
CW		 825 }
826
362b8af7
BW		 827 ering->cpu_ring_head = ring->head;
828 ering->cpu_ring_tail = ring->tail;
da661464 829
362b8af7
BW		 830 ering->hangcheck_score = ring->hangcheck.score;
831 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 832
833 if (USES_PPGTT(dev)) {
834 int i;
835
836 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
837
838 switch (INTEL_INFO(dev)->gen) {
839 case 8:
840 for (i = 0; i < 4; i++) {
841 ering->vm_info.pdp[i] =
842 I915_READ(GEN8_RING_PDP_UDW(ring, i));
843 ering->vm_info.pdp[i] <<= 32;
844 ering->vm_info.pdp[i] |=
845 I915_READ(GEN8_RING_PDP_LDW(ring, i));
846 }
847 break;
848 case 7:
849 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring);
850 break;
851 case 6:
852 ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring);
853 break;
854 }
855 }
84734a04
MK		 856}
857
858
859static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
860 struct drm_i915_error_state *error,
861 struct drm_i915_error_ring *ering)
862{
863 struct drm_i915_private *dev_priv = ring->dev->dev_private;
864 struct drm_i915_gem_object *obj;
865
866 /* Currently render ring is the only HW context user */
867 if (ring->id != RCS || !error->ccid)
868 return;
869
870 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
871 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
872 ering->ctx = i915_error_object_create_sized(dev_priv,
a7b91078
BW		 873 obj,
874 &dev_priv->gtt.base,
875 1);
84734a04
MK		 876 break;
877 }
878 }
879}
880
881static void i915_gem_record_rings(struct drm_device *dev,
882 struct drm_i915_error_state *error)
883{
884 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 885 struct drm_i915_gem_request *request;
886 int i, count;
887
372fbb8e
CW		 888 for (i = 0; i < I915_NUM_RINGS; i++) {
889 struct intel_ring_buffer *ring = &dev_priv->ring[i];
890
891 if (ring->dev == NULL)
892 continue;
893
894 error->ring[i].valid = true;
895
362b8af7 896 i915_record_ring_state(dev, ring, &error->ring[i]);
84734a04 897
ab0e7ff9
CW		 898 error->ring[i].pid = -1;
899 request = i915_gem_find_active_request(ring);
900 if (request) {
901 /* We need to copy these to an anonymous buffer
902 * as the simplest method to avoid being overwritten
903 * by userspace.
904 */
905 error->ring[i].batchbuffer =
906 i915_error_object_create(dev_priv,
907 request->batch_obj,
908 request->ctx ?
909 request->ctx->vm :
910 &dev_priv->gtt.base);
911
912 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
913 ring->scratch.obj)
914 error->ring[i].wa_batchbuffer =
915 i915_error_ggtt_object_create(dev_priv,
916 ring->scratch.obj);
917
918 if (request->file_priv) {
919 struct task_struct *task;
920
921 rcu_read_lock();
922 task = pid_task(request->file_priv->file->pid,
923 PIDTYPE_PID);
924 if (task) {
925 strcpy(error->ring[i].comm, task->comm);
926 error->ring[i].pid = task->pid;
927 }
928 rcu_read_unlock();
929 }
930 }
84734a04
MK		 931
932 error->ring[i].ringbuffer =
a7b91078 933 i915_error_ggtt_object_create(dev_priv, ring->obj);
84734a04 934
f3ce3821 935 if (ring->status_page.obj)
362b8af7 936 error->ring[i].hws_page =
f3ce3821 937 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 938
939 i915_gem_record_active_context(ring, error, &error->ring[i]);
940
941 count = 0;
942 list_for_each_entry(request, &ring->request_list, list)
943 count++;
944
945 error->ring[i].num_requests = count;
946 error->ring[i].requests =
a1e22653 947 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 948 GFP_ATOMIC);
949 if (error->ring[i].requests == NULL) {
950 error->ring[i].num_requests = 0;
951 continue;
952 }
953
954 count = 0;
955 list_for_each_entry(request, &ring->request_list, list) {
956 struct drm_i915_error_request *erq;
957
958 erq = &error->ring[i].requests[count++];
959 erq->seqno = request->seqno;
960 erq->jiffies = request->emitted_jiffies;
961 erq->tail = request->tail;
962 }
963 }
964}
965
95f5301d
BW		 966/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
967 * VM.
968 */
969static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
970 struct drm_i915_error_state *error,
971 struct i915_address_space *vm,
972 const int ndx)
84734a04 973{
95f5301d 974 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 975 struct drm_i915_gem_object *obj;
95f5301d 976 struct i915_vma *vma;
84734a04
MK		 977 int i;
978
979 i = 0;
ca191b13 980 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 981 i++;
95f5301d 982 error->active_bo_count[ndx] = i;
84734a04 983 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
d7f46fc4 984 if (i915_gem_obj_is_pinned(obj))
84734a04 985 i++;
95f5301d 986 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 987
988 if (i) {
a1e22653 989 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 990 if (active_bo)
991 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 992 }
993
95f5301d
BW		 994 if (active_bo)
995 error->active_bo_count[ndx] =
996 capture_active_bo(active_bo,
997 error->active_bo_count[ndx],
5cef07e1 998 &vm->active_list);
84734a04 999
95f5301d
BW		 1000 if (pinned_bo)
1001 error->pinned_bo_count[ndx] =
1002 capture_pinned_bo(pinned_bo,
1003 error->pinned_bo_count[ndx],
84734a04 1004 &dev_priv->mm.bound_list);
95f5301d
BW		 1005 error->active_bo[ndx] = active_bo;
1006 error->pinned_bo[ndx] = pinned_bo;
1007}
1008
1009static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1010 struct drm_i915_error_state *error)
1011{
1012 struct i915_address_space *vm;
1013 int cnt = 0, i = 0;
1014
1015 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1016 cnt++;
1017
95f5301d
BW		 1018 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1019 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1020 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1021 GFP_ATOMIC);
1022 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1023 GFP_ATOMIC);
1024
1025 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1026 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 1027}
1028
1d762aad
BW		 1029/* Capture all registers which don't fit into another category. */
1030static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1031 struct drm_i915_error_state *error)
84734a04 1032{
1d762aad 1033 struct drm_device *dev = dev_priv->dev;
84734a04
MK		 1034 int pipe;
1035
654c90c6
BW		 1036 /* General organization
1037 * 1. Registers specific to a single generation
1038 * 2. Registers which belong to multiple generations
1039 * 3. Feature specific registers.
1040 * 4. Everything else
1041 * Please try to follow the order.
1042 */
84734a04 1043
654c90c6
BW		 1044 /* 1: Registers specific to a single generation */
1045 if (IS_VALLEYVIEW(dev)) {
84734a04 1046 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
654c90c6
BW		 1047 error->forcewake = I915_READ(FORCEWAKE_VLV);
1048 }
84734a04 1049
654c90c6
BW		 1050 if (IS_GEN7(dev))
1051 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1052
91ec5d11 1053 if (IS_GEN6(dev)) {
84734a04 1054 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1055 error->gab_ctl = I915_READ(GAB_CTL);
1056 error->gfx_mode = I915_READ(GFX_MODE);
1057 }
84734a04 1058
654c90c6
BW		 1059 if (IS_GEN2(dev))
1060 error->ier = I915_READ16(IER);
1061
1062 /* 2: Registers which belong to multiple generations */
1063 if (INTEL_INFO(dev)->gen >= 7)
1064 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1065
1066 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1067 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1068 error->error = I915_READ(ERROR_GEN6);
1069 error->done_reg = I915_READ(DONE_REG);
1070 }
1071
654c90c6 1072 /* 3: Feature specific registers */
91ec5d11
BW		 1073 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1074 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1075 error->gac_eco = I915_READ(GAC_ECO_BITS);
1076 }
1077
1078 /* 4: Everything else */
654c90c6
BW		 1079 if (HAS_HW_CONTEXTS(dev))
1080 error->ccid = I915_READ(CCID);
1081
1082 if (HAS_PCH_SPLIT(dev))
1083 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1084 else {
1085 error->ier = I915_READ(IER);
1086 for_each_pipe(pipe)
1087 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1088 }
1089
1090 /* 4: Everything else */
1091 error->eir = I915_READ(EIR);
1092 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1093
1094 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1095}
1096
cb383002 1097static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1098 struct drm_i915_error_state *error,
1099 bool wedged,
1100 const char *error_msg)
cb383002
MK		 1101{
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 u32 ecode;
58174462 1104 int ring_id = -1, len;
cb383002
MK		 1105
1106 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1107
58174462
MK		 1108 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1109 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1110
1111 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1112 len += scnprintf(error->error_msg + len,
1113 sizeof(error->error_msg) - len,
1114 ", in %s [%d]",
1115 error->ring[ring_id].comm,
1116 error->ring[ring_id].pid);
1117
1118 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1119 ", reason: %s, action: %s",
1120 error_msg,
1121 wedged ? "reset" : "continue");
cb383002
MK		 1122}
1123
48b031e3
MK		 1124static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1125 struct drm_i915_error_state *error)
1126{
1127 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1128}
1129
1d762aad
BW		 1130/**
1131 * i915_capture_error_state - capture an error record for later analysis
1132 * @dev: drm device
1133 *
1134 * Should be called when an error is detected (either a hang or an error
1135 * interrupt) to capture error state from the time of the error. Fills
1136 * out a structure which becomes available in debugfs for user level tools
1137 * to pick up.
1138 */
58174462
MK		 1139void i915_capture_error_state(struct drm_device *dev, bool wedged,
1140 const char *error_msg)
1d762aad 1141{
53a4c6b2 1142 static bool warned;
1d762aad
BW		 1143 struct drm_i915_private *dev_priv = dev->dev_private;
1144 struct drm_i915_error_state *error;
1145 unsigned long flags;
1d762aad
BW		 1146
1147 /* Account for pipe specific data like PIPE*STAT */
1148 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1149 if (!error) {
1150 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1151 return;
1152 }
1153
011cf577
BW		 1154 kref_init(&error->ref);
1155
48b031e3 1156 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1157 i915_capture_reg_state(dev_priv, error);
1158 i915_gem_capture_buffers(dev_priv, error);
1159 i915_gem_record_fences(dev, error);
1160 i915_gem_record_rings(dev, error);
1d762aad 1161
84734a04
MK		 1162 do_gettimeofday(&error->time);
1163
1164 error->overlay = intel_overlay_capture_error_state(dev);
1165 error->display = intel_display_capture_error_state(dev);
1166
58174462 1167 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1168 DRM_INFO("%s\n", error->error_msg);
1169
84734a04
MK		 1170 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1171 if (dev_priv->gpu_error.first_error == NULL) {
1172 dev_priv->gpu_error.first_error = error;
1173 error = NULL;
1174 }
1175 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1176
cb383002 1177 if (error) {
84734a04 1178 i915_error_state_free(&error->ref);
cb383002
MK		 1179 return;
1180 }
1181
1182 if (!warned) {
1183 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1184 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1185 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1186 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1187 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1188 warned = true;
1189 }
84734a04
MK		 1190}
1191
1192void i915_error_state_get(struct drm_device *dev,
1193 struct i915_error_state_file_priv *error_priv)
1194{
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 unsigned long flags;
1197
1198 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1199 error_priv->error = dev_priv->gpu_error.first_error;
1200 if (error_priv->error)
1201 kref_get(&error_priv->error->ref);
1202 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1203
1204}
1205
1206void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1207{
1208 if (error_priv->error)
1209 kref_put(&error_priv->error->ref, i915_error_state_free);
1210}
1211
1212void i915_destroy_error_state(struct drm_device *dev)
1213{
1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 struct drm_i915_error_state *error;
1216 unsigned long flags;
1217
1218 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1219 error = dev_priv->gpu_error.first_error;
1220 dev_priv->gpu_error.first_error = NULL;
1221 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1222
1223 if (error)
1224 kref_put(&error->ref, i915_error_state_free);
1225}
1226
1227const char *i915_cache_level_str(int type)
1228{
1229 switch (type) {
1230 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1231 case I915_CACHE_LLC: return " snooped or LLC";
1232 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1233 case I915_CACHE_WT: return " WT";
84734a04
MK		 1234 default: return "";
1235 }
1236}
1237
1238/* NB: please notice the memset */
1239void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1240{
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1243
1244 switch (INTEL_INFO(dev)->gen) {
1245 case 2:
1246 case 3:
1247 instdone[0] = I915_READ(INSTDONE);
1248 break;
1249 case 4:
1250 case 5:
1251 case 6:
1252 instdone[0] = I915_READ(INSTDONE_I965);
1253 instdone[1] = I915_READ(INSTDONE1);
1254 break;
1255 default:
1256 WARN_ONCE(1, "Unsupported platform\n");
1257 case 7:
d0582ed2 1258 case 8:
84734a04
MK		 1259 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1260 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1261 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1262 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1263 break;
1264 }
1265}
Linux kernel - Deliverables
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