projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Interrupt routing for GuC submission
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
845f74a7 45 case VCS2: return "bsd2";
84734a04
MK		 46 default: return "";
47 }
48}
49
50static const char *pin_flag(int pinned)
51{
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58}
59
60static const char *tiling_flag(int tiling)
61{
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68}
69
70static const char *dirty_flag(int dirty)
71{
72 return dirty ? " dirty" : "";
73}
74
75static const char *purgeable_flag(int purgeable)
76{
77 return purgeable ? " purgeable" : "";
78}
79
80static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81{
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92}
93
94static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96{
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109}
110
111static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113{
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135}
136
137static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139{
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
e29bb4eb
CW		 147 va_list tmp;
148
149 va_copy(tmp, args);
1d2cb9a5
MK		 150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
84734a04
MK		 154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162}
163
164static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166{
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185}
186
187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188#define err_puts(e, s) i915_error_puts(e, s)
189
190static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194{
b4716185
CW		 195 int i;
196
3a448734 197 err_printf(m, " %s [%d]:\n", name, count);
84734a04
MK		 198
199 while (count--) {
e1f12325
MT		 200 err_printf(m, " %08x_%08x %8u %02x %02x [ ",
201 upper_32_bits(err->gtt_offset),
202 lower_32_bits(err->gtt_offset),
84734a04
MK		 203 err->size,
204 err->read_domains,
b4716185
CW		 205 err->write_domain);
206 for (i = 0; i < I915_NUM_RINGS; i++)
207 err_printf(m, "%02x ", err->rseqno[i]);
208
209 err_printf(m, "] %02x", err->wseqno);
84734a04
MK		 210 err_puts(m, pin_flag(err->pinned));
211 err_puts(m, tiling_flag(err->tiling));
212 err_puts(m, dirty_flag(err->dirty));
213 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 214 err_puts(m, err->userptr ? " userptr" : "");
84734a04
MK		 215 err_puts(m, err->ring != -1 ? " " : "");
216 err_puts(m, ring_str(err->ring));
0a4cd7c8 217 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
84734a04
MK		 218
219 if (err->name)
220 err_printf(m, " (name: %d)", err->name);
221 if (err->fence_reg != I915_FENCE_REG_NONE)
222 err_printf(m, " (fence: %d)", err->fence_reg);
223
224 err_puts(m, "\n");
225 err++;
226 }
227}
228
da661464
MK		 229static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
230{
231 switch (a) {
232 case HANGCHECK_IDLE:
233 return "idle";
234 case HANGCHECK_WAIT:
235 return "wait";
236 case HANGCHECK_ACTIVE:
237 return "active";
f260fe7b
MK		 238 case HANGCHECK_ACTIVE_LOOP:
239 return "active (loop)";
da661464
MK		 240 case HANGCHECK_KICK:
241 return "kick";
242 case HANGCHECK_HUNG:
243 return "hung";
244 }
245
246 return "unknown";
247}
248
84734a04
MK		 249static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
250 struct drm_device *dev,
77c1aa84
DV		 251 struct drm_i915_error_state *error,
252 int ring_idx)
84734a04 253{
77c1aa84
DV		 254 struct drm_i915_error_ring *ring = &error->ring[ring_idx];
255
362b8af7 256 if (!ring->valid)
372fbb8e
CW		 257 return;
258
77c1aa84 259 err_printf(m, "%s command stream:\n", ring_str(ring_idx));
94f8cf10
CW		 260 err_printf(m, " START: 0x%08x\n", ring->start);
261 err_printf(m, " HEAD: 0x%08x\n", ring->head);
262 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
263 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
264 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 265 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 266 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
267 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
268 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 269 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 270 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 271 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
272 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 273 }
362b8af7 274 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 275 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
276 lower_32_bits(ring->faddr));
84734a04 277 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 278 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
279 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 280 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 281 ring->semaphore_mboxes[0],
282 ring->semaphore_seqno[0]);
84734a04 283 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 284 ring->semaphore_mboxes[1],
285 ring->semaphore_seqno[1]);
4e5aabfd
BW		 286 if (HAS_VEBOX(dev)) {
287 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 288 ring->semaphore_mboxes[2],
289 ring->semaphore_seqno[2]);
4e5aabfd 290 }
84734a04 291 }
6c7a01ec
BW		 292 if (USES_PPGTT(dev)) {
293 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
294
295 if (INTEL_INFO(dev)->gen >= 8) {
296 int i;
297 for (i = 0; i < 4; i++)
298 err_printf(m, " PDP%d: 0x%016llx\n",
299 i, ring->vm_info.pdp[i]);
300 } else {
301 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
302 ring->vm_info.pp_dir_base);
303 }
304 }
362b8af7
BW		 305 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
306 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
307 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
308 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 309 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 310 hangcheck_action_to_str(ring->hangcheck_action),
311 ring->hangcheck_score);
84734a04
MK		 312}
313
314void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
315{
316 va_list args;
317
318 va_start(args, f);
319 i915_error_vprintf(e, f, args);
320 va_end(args);
321}
322
ab0e7ff9
CW		 323static void print_error_obj(struct drm_i915_error_state_buf *m,
324 struct drm_i915_error_object *obj)
325{
326 int page, offset, elt;
327
328 for (page = offset = 0; page < obj->page_count; page++) {
329 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
330 err_printf(m, "%08x : %08x\n", offset,
331 obj->pages[page][elt]);
332 offset += 4;
333 }
334 }
335}
336
84734a04
MK		 337int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
338 const struct i915_error_state_file_priv *error_priv)
339{
340 struct drm_device *dev = error_priv->dev;
50227e1c 341 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 342 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 343 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 344 int i, j, offset, elt;
345 int max_hangcheck_score;
84734a04
MK		 346
347 if (!error) {
348 err_printf(m, "no error state collected\n");
349 goto out;
350 }
351
cb383002 352 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 353 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
354 error->time.tv_usec);
355 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 356 max_hangcheck_score = 0;
357 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
358 if (error->ring[i].hangcheck_score > max_hangcheck_score)
359 max_hangcheck_score = error->ring[i].hangcheck_score;
360 }
361 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
362 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
363 error->ring[i].pid != -1) {
364 err_printf(m, "Active process (on ring %s): %s [%d]\n",
365 ring_str(i),
366 error->ring[i].comm,
367 error->ring[i].pid);
368 }
369 }
48b031e3 370 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 371 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 372 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
eb5be9d0 373 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
84734a04
MK		 374 err_printf(m, "EIR: 0x%08x\n", error->eir);
375 err_printf(m, "IER: 0x%08x\n", error->ier);
885ea5a8
RV		 376 if (INTEL_INFO(dev)->gen >= 8) {
377 for (i = 0; i < 4; i++)
378 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
379 error->gtier[i]);
380 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
381 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
84734a04
MK		 382 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
383 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
384 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
385 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 386 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 387
388 for (i = 0; i < dev_priv->num_fence_regs; i++)
389 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
390
391 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
392 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
393 error->extra_instdone[i]);
394
395 if (INTEL_INFO(dev)->gen >= 6) {
396 err_printf(m, "ERROR: 0x%08x\n", error->error);
6c826f34
MK		 397
398 if (INTEL_INFO(dev)->gen >= 8)
399 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
400 error->fault_data1, error->fault_data0);
401
84734a04
MK		 402 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
403 }
404
405 if (INTEL_INFO(dev)->gen == 7)
406 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
407
77c1aa84
DV		 408 for (i = 0; i < ARRAY_SIZE(error->ring); i++)
409 i915_ring_error_state(m, dev, error, i);
84734a04 410
3a448734
CW		 411 for (i = 0; i < error->vm_count; i++) {
412 err_printf(m, "vm[%d]\n", i);
413
84734a04 414 print_error_buffers(m, "Active",
3a448734
CW		 415 error->active_bo[i],
416 error->active_bo_count[i]);
84734a04 417
84734a04 418 print_error_buffers(m, "Pinned",
3a448734
CW		 419 error->pinned_bo[i],
420 error->pinned_bo_count[i]);
421 }
84734a04
MK		 422
423 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
ab0e7ff9
CW		 424 obj = error->ring[i].batchbuffer;
425 if (obj) {
426 err_puts(m, dev_priv->ring[i].name);
427 if (error->ring[i].pid != -1)
428 err_printf(m, " (submitted by %s [%d])",
429 error->ring[i].comm,
430 error->ring[i].pid);
e1f12325
MT		 431 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
432 upper_32_bits(obj->gtt_offset),
433 lower_32_bits(obj->gtt_offset));
ab0e7ff9
CW		 434 print_error_obj(m, obj);
435 }
436
437 obj = error->ring[i].wa_batchbuffer;
438 if (obj) {
439 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
e1f12325
MT		 440 dev_priv->ring[i].name,
441 lower_32_bits(obj->gtt_offset));
ab0e7ff9 442 print_error_obj(m, obj);
84734a04
MK		 443 }
444
445 if (error->ring[i].num_requests) {
446 err_printf(m, "%s --- %d requests\n",
447 dev_priv->ring[i].name,
448 error->ring[i].num_requests);
449 for (j = 0; j < error->ring[i].num_requests; j++) {
450 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
451 error->ring[i].requests[j].seqno,
452 error->ring[i].requests[j].jiffies,
453 error->ring[i].requests[j].tail);
454 }
455 }
456
457 if ((obj = error->ring[i].ringbuffer)) {
458 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
459 dev_priv->ring[i].name,
e1f12325 460 lower_32_bits(obj->gtt_offset));
ab0e7ff9 461 print_error_obj(m, obj);
84734a04
MK		 462 }
463
362b8af7 464 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 465 err_printf(m, "%s --- HW Status = 0x%08x\n",
466 dev_priv->ring[i].name,
e1f12325 467 lower_32_bits(obj->gtt_offset));
f3ce3821
CW		 468 offset = 0;
469 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
470 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
471 offset,
472 obj->pages[0][elt],
473 obj->pages[0][elt+1],
474 obj->pages[0][elt+2],
475 obj->pages[0][elt+3]);
476 offset += 16;
477 }
478 }
479
372fbb8e 480 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 481 err_printf(m, "%s --- HW Context = 0x%08x\n",
482 dev_priv->ring[i].name,
e1f12325 483 lower_32_bits(obj->gtt_offset));
17d36749 484 print_error_obj(m, obj);
84734a04
MK		 485 }
486 }
487
0ca36d78 488 if ((obj = error->semaphore_obj)) {
e1f12325
MT		 489 err_printf(m, "Semaphore page = 0x%08x\n",
490 lower_32_bits(obj->gtt_offset));
0ca36d78
BW		 491 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
492 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
493 elt * 4,
494 obj->pages[0][elt],
495 obj->pages[0][elt+1],
496 obj->pages[0][elt+2],
497 obj->pages[0][elt+3]);
498 }
499 }
500
84734a04
MK		 501 if (error->overlay)
502 intel_overlay_print_error_state(m, error->overlay);
503
504 if (error->display)
505 intel_display_print_error_state(m, dev, error->display);
506
507out:
508 if (m->bytes == 0 && m->err)
509 return m->err;
510
511 return 0;
512}
513
514int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
0a4cd7c8 515 struct drm_i915_private *i915,
84734a04
MK		 516 size_t count, loff_t pos)
517{
518 memset(ebuf, 0, sizeof(*ebuf));
0a4cd7c8 519 ebuf->i915 = i915;
84734a04
MK		 520
521 /* We need to have enough room to store any i915_error_state printf
522 * so that we can move it to start position.
523 */
524 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
525 ebuf->buf = kmalloc(ebuf->size,
526 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
527
528 if (ebuf->buf == NULL) {
529 ebuf->size = PAGE_SIZE;
530 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
531 }
532
533 if (ebuf->buf == NULL) {
534 ebuf->size = 128;
535 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
536 }
537
538 if (ebuf->buf == NULL)
539 return -ENOMEM;
540
541 ebuf->start = pos;
542
543 return 0;
544}
545
546static void i915_error_object_free(struct drm_i915_error_object *obj)
547{
548 int page;
549
550 if (obj == NULL)
551 return;
552
553 for (page = 0; page < obj->page_count; page++)
554 kfree(obj->pages[page]);
555
556 kfree(obj);
557}
558
559static void i915_error_state_free(struct kref *error_ref)
560{
561 struct drm_i915_error_state *error = container_of(error_ref,
562 typeof(*error), ref);
563 int i;
564
565 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
566 i915_error_object_free(error->ring[i].batchbuffer);
b3da4a62 567 i915_error_object_free(error->ring[i].wa_batchbuffer);
84734a04 568 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 569 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 570 i915_error_object_free(error->ring[i].ctx);
571 kfree(error->ring[i].requests);
572 }
573
0ca36d78 574 i915_error_object_free(error->semaphore_obj);
0b37a9a9
MT		 575
576 for (i = 0; i < error->vm_count; i++)
577 kfree(error->active_bo[i]);
578
84734a04 579 kfree(error->active_bo);
0b37a9a9
MT		 580 kfree(error->active_bo_count);
581 kfree(error->pinned_bo);
582 kfree(error->pinned_bo_count);
84734a04
MK		 583 kfree(error->overlay);
584 kfree(error->display);
585 kfree(error);
586}
587
588static struct drm_i915_error_object *
8ae62dc6
CW		 589i915_error_object_create(struct drm_i915_private *dev_priv,
590 struct drm_i915_gem_object *src,
591 struct i915_address_space *vm)
84734a04
MK		 592{
593 struct drm_i915_error_object *dst;
aff43766 594 struct i915_vma *vma = NULL;
8ae62dc6 595 int num_pages;
b3c3f5e6
CW		 596 bool use_ggtt;
597 int i = 0;
e1f12325 598 u64 reloc_offset;
84734a04
MK		 599
600 if (src == NULL || src->pages == NULL)
601 return NULL;
602
8ae62dc6
CW		 603 num_pages = src->base.size >> PAGE_SHIFT;
604
84734a04
MK		 605 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
606 if (dst == NULL)
607 return NULL;
608
87a01e82
CW		 609 if (i915_gem_obj_bound(src, vm))
610 dst->gtt_offset = i915_gem_obj_offset(src, vm);
611 else
612 dst->gtt_offset = -1;
b3c3f5e6
CW		 613
614 reloc_offset = dst->gtt_offset;
aff43766
TU		 615 if (i915_is_ggtt(vm))
616 vma = i915_gem_obj_to_ggtt(src);
b3c3f5e6 617 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
aff43766
TU		 618 vma && (vma->bound & GLOBAL_BIND) &&
619 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
b3c3f5e6
CW		 620
621 /* Cannot access stolen address directly, try to use the aperture */
622 if (src->stolen) {
623 use_ggtt = true;
624
aff43766 625 if (!(vma && vma->bound & GLOBAL_BIND))
b3c3f5e6
CW		 626 goto unwind;
627
628 reloc_offset = i915_gem_obj_ggtt_offset(src);
629 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
630 goto unwind;
631 }
632
633 /* Cannot access snooped pages through the aperture */
634 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
635 goto unwind;
636
637 dst->page_count = num_pages;
638 while (num_pages--) {
84734a04
MK		 639 unsigned long flags;
640 void *d;
641
642 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
643 if (d == NULL)
644 goto unwind;
645
646 local_irq_save(flags);
b3c3f5e6 647 if (use_ggtt) {
84734a04
MK		 648 void __iomem *s;
649
650 /* Simply ignore tiling or any overlapping fence.
651 * It's part of the error state, and this hopefully
652 * captures what the GPU read.
653 */
654
655 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
656 reloc_offset);
657 memcpy_fromio(d, s, PAGE_SIZE);
658 io_mapping_unmap_atomic(s);
84734a04
MK		 659 } else {
660 struct page *page;
661 void *s;
662
663 page = i915_gem_object_get_page(src, i);
664
665 drm_clflush_pages(&page, 1);
666
667 s = kmap_atomic(page);
668 memcpy(d, s, PAGE_SIZE);
669 kunmap_atomic(s);
670
671 drm_clflush_pages(&page, 1);
672 }
673 local_irq_restore(flags);
674
b3c3f5e6 675 dst->pages[i++] = d;
84734a04
MK		 676 reloc_offset += PAGE_SIZE;
677 }
84734a04
MK		 678
679 return dst;
680
681unwind:
682 while (i--)
683 kfree(dst->pages[i]);
684 kfree(dst);
685 return NULL;
686}
a7b91078 687#define i915_error_ggtt_object_create(dev_priv, src) \
8ae62dc6 688 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
84734a04
MK		 689
690static void capture_bo(struct drm_i915_error_buffer *err,
3a448734 691 struct i915_vma *vma)
84734a04 692{
3a448734 693 struct drm_i915_gem_object *obj = vma->obj;
b4716185 694 int i;
3a448734 695
84734a04
MK		 696 err->size = obj->base.size;
697 err->name = obj->base.name;
b4716185
CW		 698 for (i = 0; i < I915_NUM_RINGS; i++)
699 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
97b2a6a1 700 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
3a448734 701 err->gtt_offset = vma->node.start;
84734a04
MK		 702 err->read_domains = obj->base.read_domains;
703 err->write_domain = obj->base.write_domain;
704 err->fence_reg = obj->fence_reg;
705 err->pinned = 0;
d7f46fc4 706 if (i915_gem_obj_is_pinned(obj))
84734a04 707 err->pinned = 1;
84734a04
MK		 708 err->tiling = obj->tiling_mode;
709 err->dirty = obj->dirty;
710 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 711 err->userptr = obj->userptr.mm != NULL;
b4716185
CW		 712 err->ring = obj->last_write_req ?
713 i915_gem_request_get_ring(obj->last_write_req)->id : -1;
84734a04
MK		 714 err->cache_level = obj->cache_level;
715}
716
717static u32 capture_active_bo(struct drm_i915_error_buffer *err,
718 int count, struct list_head *head)
719{
ca191b13 720 struct i915_vma *vma;
84734a04
MK		 721 int i = 0;
722
ca191b13 723 list_for_each_entry(vma, head, mm_list) {
3a448734 724 capture_bo(err++, vma);
84734a04
MK		 725 if (++i == count)
726 break;
727 }
728
729 return i;
730}
731
732static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
3a448734
CW		 733 int count, struct list_head *head,
734 struct i915_address_space *vm)
84734a04
MK		 735{
736 struct drm_i915_gem_object *obj;
3a448734
CW		 737 struct drm_i915_error_buffer * const first = err;
738 struct drm_i915_error_buffer * const last = err + count;
84734a04
MK		 739
740 list_for_each_entry(obj, head, global_list) {
3a448734 741 struct i915_vma *vma;
84734a04 742
3a448734 743 if (err == last)
84734a04 744 break;
3a448734
CW		 745
746 list_for_each_entry(vma, &obj->vma_list, vma_link)
fe14d5f4 747 if (vma->vm == vm && vma->pin_count > 0)
3a448734 748 capture_bo(err++, vma);
84734a04
MK		 749 }
750
3a448734 751 return err - first;
84734a04
MK		 752}
753
011cf577
BW		 754/* Generate a semi-unique error code. The code is not meant to have meaning, The
755 * code's only purpose is to try to prevent false duplicated bug reports by
756 * grossly estimating a GPU error state.
757 *
758 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
759 * the hang if we could strip the GTT offset information from it.
760 *
761 * It's only a small step better than a random number in its current form.
762 */
763static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 764 struct drm_i915_error_state *error,
765 int *ring_id)
011cf577
BW		 766{
767 uint32_t error_code = 0;
768 int i;
769
770 /* IPEHR would be an ideal way to detect errors, as it's the gross
771 * measure of "the command that hung." However, has some very common
772 * synchronization commands which almost always appear in the case
773 * strictly a client bug. Use instdone to differentiate those some.
774 */
cb383002
MK		 775 for (i = 0; i < I915_NUM_RINGS; i++) {
776 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
777 if (ring_id)
778 *ring_id = i;
779
011cf577 780 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 781 }
782 }
011cf577
BW		 783
784 return error_code;
785}
786
84734a04
MK		 787static void i915_gem_record_fences(struct drm_device *dev,
788 struct drm_i915_error_state *error)
789{
790 struct drm_i915_private *dev_priv = dev->dev_private;
791 int i;
792
ce38ab05 793 if (IS_GEN3(dev) || IS_GEN2(dev)) {
84734a04
MK		 794 for (i = 0; i < 8; i++)
795 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
ce38ab05
RV		 796 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
797 for (i = 0; i < 8; i++)
798 error->fence[i+8] = I915_READ(FENCE_REG_945_8 +
799 (i * 4));
800 } else if (IS_GEN5(dev) || IS_GEN4(dev))
801 for (i = 0; i < 16; i++)
802 error->fence[i] = I915_READ64(FENCE_REG_965_0 +
803 (i * 8));
804 else if (INTEL_INFO(dev)->gen >= 6)
805 for (i = 0; i < dev_priv->num_fence_regs; i++)
806 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 +
807 (i * 8));
84734a04
MK		 808}
809
87f85ebc 810
0ca36d78
BW		 811static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
812 struct drm_i915_error_state *error,
813 struct intel_engine_cs *ring,
814 struct drm_i915_error_ring *ering)
815{
b4558b46 816 struct intel_engine_cs *to;
0ca36d78
BW		 817 int i;
818
819 if (!i915_semaphore_is_enabled(dev_priv->dev))
820 return;
821
822 if (!error->semaphore_obj)
823 error->semaphore_obj =
cc1df8a3
DV		 824 i915_error_ggtt_object_create(dev_priv,
825 dev_priv->semaphore_obj);
0ca36d78 826
b4558b46
RV		 827 for_each_ring(to, dev_priv, i) {
828 int idx;
829 u16 signal_offset;
830 u32 *tmp;
0ca36d78 831
b4558b46
RV		 832 if (ring == to)
833 continue;
834
864c6181
RV		 835 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
836 / 4;
b4558b46
RV		 837 tmp = error->semaphore_obj->pages[0];
838 idx = intel_ring_sync_index(ring, to);
839
840 ering->semaphore_mboxes[idx] = tmp[signal_offset];
841 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
0ca36d78
BW		 842 }
843}
844
87f85ebc
BW		 845static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
846 struct intel_engine_cs *ring,
847 struct drm_i915_error_ring *ering)
848{
849 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
850 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
851 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
852 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
853
854 if (HAS_VEBOX(dev_priv->dev)) {
855 ering->semaphore_mboxes[2] =
856 I915_READ(RING_SYNC_2(ring->mmio_base));
857 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
858 }
859}
860
84734a04 861static void i915_record_ring_state(struct drm_device *dev,
0ca36d78 862 struct drm_i915_error_state *error,
a4872ba6 863 struct intel_engine_cs *ring,
362b8af7 864 struct drm_i915_error_ring *ering)
84734a04
MK		 865{
866 struct drm_i915_private *dev_priv = dev->dev_private;
867
868 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 869 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
870 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
0ca36d78
BW		 871 if (INTEL_INFO(dev)->gen >= 8)
872 gen8_record_semaphore_state(dev_priv, error, ring, ering);
873 else
874 gen6_record_semaphore_state(dev_priv, ring, ering);
4e5aabfd
BW		 875 }
876
84734a04 877 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 878 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
879 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
880 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
881 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
882 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
883 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 884 if (INTEL_INFO(dev)->gen >= 8) {
885 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 886 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 887 }
362b8af7 888 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 889 } else {
362b8af7
BW		 890 ering->faddr = I915_READ(DMA_FADD_I8XX);
891 ering->ipeir = I915_READ(IPEIR);
892 ering->ipehr = I915_READ(IPEHR);
893 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 894 }
895
362b8af7
BW		 896 ering->waiting = waitqueue_active(&ring->irq_queue);
897 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
898 ering->seqno = ring->get_seqno(ring, false);
899 ering->acthd = intel_ring_get_active_head(ring);
94f8cf10 900 ering->start = I915_READ_START(ring);
362b8af7
BW		 901 ering->head = I915_READ_HEAD(ring);
902 ering->tail = I915_READ_TAIL(ring);
903 ering->ctl = I915_READ_CTL(ring);
84734a04 904
f3ce3821
CW		 905 if (I915_NEED_GFX_HWS(dev)) {
906 int mmio;
907
908 if (IS_GEN7(dev)) {
909 switch (ring->id) {
910 default:
911 case RCS:
912 mmio = RENDER_HWS_PGA_GEN7;
913 break;
914 case BCS:
915 mmio = BLT_HWS_PGA_GEN7;
916 break;
917 case VCS:
918 mmio = BSD_HWS_PGA_GEN7;
919 break;
920 case VECS:
921 mmio = VEBOX_HWS_PGA_GEN7;
922 break;
923 }
924 } else if (IS_GEN6(ring->dev)) {
925 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
926 } else {
927 /* XXX: gen8 returns to sanity */
928 mmio = RING_HWS_PGA(ring->mmio_base);
929 }
930
362b8af7 931 ering->hws = I915_READ(mmio);
f3ce3821
CW		 932 }
933
362b8af7
BW		 934 ering->hangcheck_score = ring->hangcheck.score;
935 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 936
937 if (USES_PPGTT(dev)) {
938 int i;
939
940 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
941
74745b09
RV		 942 if (IS_GEN6(dev))
943 ering->vm_info.pp_dir_base =
944 I915_READ(RING_PP_DIR_BASE_READ(ring));
945 else if (IS_GEN7(dev))
946 ering->vm_info.pp_dir_base =
947 I915_READ(RING_PP_DIR_BASE(ring));
948 else if (INTEL_INFO(dev)->gen >= 8)
6c7a01ec
BW		 949 for (i = 0; i < 4; i++) {
950 ering->vm_info.pdp[i] =
951 I915_READ(GEN8_RING_PDP_UDW(ring, i));
952 ering->vm_info.pdp[i] <<= 32;
953 ering->vm_info.pdp[i] |=
954 I915_READ(GEN8_RING_PDP_LDW(ring, i));
955 }
6c7a01ec 956 }
84734a04
MK		 957}
958
959
a4872ba6 960static void i915_gem_record_active_context(struct intel_engine_cs *ring,
84734a04
MK		 961 struct drm_i915_error_state *error,
962 struct drm_i915_error_ring *ering)
963{
964 struct drm_i915_private *dev_priv = ring->dev->dev_private;
965 struct drm_i915_gem_object *obj;
966
967 /* Currently render ring is the only HW context user */
968 if (ring->id != RCS || !error->ccid)
969 return;
970
971 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
36362ad3
BW		 972 if (!i915_gem_obj_ggtt_bound(obj))
973 continue;
974
84734a04 975 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
17d36749 976 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 977 break;
978 }
979 }
980}
981
982static void i915_gem_record_rings(struct drm_device *dev,
983 struct drm_i915_error_state *error)
984{
985 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 986 struct drm_i915_gem_request *request;
987 int i, count;
988
372fbb8e 989 for (i = 0; i < I915_NUM_RINGS; i++) {
a4872ba6 990 struct intel_engine_cs *ring = &dev_priv->ring[i];
9075e52f 991 struct intel_ringbuffer *rbuf;
372fbb8e 992
eee73b46
CW		 993 error->ring[i].pid = -1;
994
372fbb8e
CW		 995 if (ring->dev == NULL)
996 continue;
997
998 error->ring[i].valid = true;
999
0ca36d78 1000 i915_record_ring_state(dev, error, ring, &error->ring[i]);
84734a04 1001
ab0e7ff9
CW		 1002 request = i915_gem_find_active_request(ring);
1003 if (request) {
ae6c4806
DV		 1004 struct i915_address_space *vm;
1005
1006 vm = request->ctx && request->ctx->ppgtt ?
1007 &request->ctx->ppgtt->base :
1008 &dev_priv->gtt.base;
1009
ab0e7ff9
CW		 1010 /* We need to copy these to an anonymous buffer
1011 * as the simplest method to avoid being overwritten
1012 * by userspace.
1013 */
1014 error->ring[i].batchbuffer =
1015 i915_error_object_create(dev_priv,
1016 request->batch_obj,
ae6c4806 1017 vm);
ab0e7ff9 1018
8ae62dc6 1019 if (HAS_BROKEN_CS_TLB(dev_priv->dev))
ab0e7ff9
CW		 1020 error->ring[i].wa_batchbuffer =
1021 i915_error_ggtt_object_create(dev_priv,
1022 ring->scratch.obj);
1023
071c92de 1024 if (request->pid) {
ab0e7ff9
CW		 1025 struct task_struct *task;
1026
1027 rcu_read_lock();
071c92de 1028 task = pid_task(request->pid, PIDTYPE_PID);
ab0e7ff9
CW		 1029 if (task) {
1030 strcpy(error->ring[i].comm, task->comm);
1031 error->ring[i].pid = task->pid;
1032 }
1033 rcu_read_unlock();
1034 }
1035 }
84734a04 1036
9075e52f
OM		 1037 if (i915.enable_execlists) {
1038 /* TODO: This is only a small fix to keep basic error
1039 * capture working, but we need to add more information
1040 * for it to be useful (e.g. dump the context being
1041 * executed).
1042 */
1043 if (request)
1044 rbuf = request->ctx->engine[ring->id].ringbuf;
1045 else
1046 rbuf = ring->default_context->engine[ring->id].ringbuf;
1047 } else
1048 rbuf = ring->buffer;
1049
1050 error->ring[i].cpu_ring_head = rbuf->head;
1051 error->ring[i].cpu_ring_tail = rbuf->tail;
1052
84734a04 1053 error->ring[i].ringbuffer =
9075e52f 1054 i915_error_ggtt_object_create(dev_priv, rbuf->obj);
84734a04 1055
8ae62dc6
CW		 1056 error->ring[i].hws_page =
1057 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 1058
1059 i915_gem_record_active_context(ring, error, &error->ring[i]);
1060
1061 count = 0;
1062 list_for_each_entry(request, &ring->request_list, list)
1063 count++;
1064
1065 error->ring[i].num_requests = count;
1066 error->ring[i].requests =
a1e22653 1067 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 1068 GFP_ATOMIC);
1069 if (error->ring[i].requests == NULL) {
1070 error->ring[i].num_requests = 0;
1071 continue;
1072 }
1073
1074 count = 0;
1075 list_for_each_entry(request, &ring->request_list, list) {
1076 struct drm_i915_error_request *erq;
1077
1078 erq = &error->ring[i].requests[count++];
1079 erq->seqno = request->seqno;
1080 erq->jiffies = request->emitted_jiffies;
72f95afa 1081 erq->tail = request->postfix;
84734a04
MK		 1082 }
1083 }
1084}
1085
95f5301d
BW		 1086/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1087 * VM.
1088 */
1089static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1090 struct drm_i915_error_state *error,
1091 struct i915_address_space *vm,
1092 const int ndx)
84734a04 1093{
95f5301d 1094 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 1095 struct drm_i915_gem_object *obj;
95f5301d 1096 struct i915_vma *vma;
84734a04
MK		 1097 int i;
1098
1099 i = 0;
ca191b13 1100 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 1101 i++;
95f5301d 1102 error->active_bo_count[ndx] = i;
3a448734
CW		 1103
1104 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1105 list_for_each_entry(vma, &obj->vma_list, vma_link)
fe14d5f4 1106 if (vma->vm == vm && vma->pin_count > 0)
3a448734 1107 i++;
3a448734 1108 }
95f5301d 1109 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 1110
1111 if (i) {
a1e22653 1112 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 1113 if (active_bo)
1114 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1115 }
1116
95f5301d
BW		 1117 if (active_bo)
1118 error->active_bo_count[ndx] =
1119 capture_active_bo(active_bo,
1120 error->active_bo_count[ndx],
5cef07e1 1121 &vm->active_list);
84734a04 1122
95f5301d
BW		 1123 if (pinned_bo)
1124 error->pinned_bo_count[ndx] =
1125 capture_pinned_bo(pinned_bo,
1126 error->pinned_bo_count[ndx],
3a448734 1127 &dev_priv->mm.bound_list, vm);
95f5301d
BW		 1128 error->active_bo[ndx] = active_bo;
1129 error->pinned_bo[ndx] = pinned_bo;
1130}
1131
1132static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1133 struct drm_i915_error_state *error)
1134{
1135 struct i915_address_space *vm;
1136 int cnt = 0, i = 0;
1137
1138 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1139 cnt++;
1140
95f5301d
BW		 1141 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1142 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1143 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1144 GFP_ATOMIC);
1145 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1146 GFP_ATOMIC);
1147
3a448734
CW		 1148 if (error->active_bo == NULL ||
1149 error->pinned_bo == NULL ||
1150 error->active_bo_count == NULL ||
1151 error->pinned_bo_count == NULL) {
1152 kfree(error->active_bo);
1153 kfree(error->active_bo_count);
1154 kfree(error->pinned_bo);
1155 kfree(error->pinned_bo_count);
1156
1157 error->active_bo = NULL;
1158 error->active_bo_count = NULL;
1159 error->pinned_bo = NULL;
1160 error->pinned_bo_count = NULL;
1161 } else {
1162 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1163 i915_gem_capture_vm(dev_priv, error, vm, i++);
1164
1165 error->vm_count = cnt;
1166 }
84734a04
MK		 1167}
1168
1d762aad
BW		 1169/* Capture all registers which don't fit into another category. */
1170static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1171 struct drm_i915_error_state *error)
84734a04 1172{
1d762aad 1173 struct drm_device *dev = dev_priv->dev;
885ea5a8 1174 int i;
84734a04 1175
654c90c6
BW		 1176 /* General organization
1177 * 1. Registers specific to a single generation
1178 * 2. Registers which belong to multiple generations
1179 * 3. Feature specific registers.
1180 * 4. Everything else
1181 * Please try to follow the order.
1182 */
84734a04 1183
654c90c6
BW		 1184 /* 1: Registers specific to a single generation */
1185 if (IS_VALLEYVIEW(dev)) {
885ea5a8 1186 error->gtier[0] = I915_READ(GTIER);
843db716 1187 error->ier = I915_READ(VLV_IER);
654c90c6
BW		 1188 error->forcewake = I915_READ(FORCEWAKE_VLV);
1189 }
84734a04 1190
654c90c6
BW		 1191 if (IS_GEN7(dev))
1192 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1193
6c826f34
MK		 1194 if (INTEL_INFO(dev)->gen >= 8) {
1195 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1196 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1197 }
1198
91ec5d11 1199 if (IS_GEN6(dev)) {
84734a04 1200 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1201 error->gab_ctl = I915_READ(GAB_CTL);
1202 error->gfx_mode = I915_READ(GFX_MODE);
1203 }
84734a04 1204
654c90c6
BW		 1205 /* 2: Registers which belong to multiple generations */
1206 if (INTEL_INFO(dev)->gen >= 7)
1207 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1208
1209 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1210 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1211 error->error = I915_READ(ERROR_GEN6);
1212 error->done_reg = I915_READ(DONE_REG);
1213 }
1214
654c90c6 1215 /* 3: Feature specific registers */
91ec5d11
BW		 1216 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1217 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1218 error->gac_eco = I915_READ(GAC_ECO_BITS);
1219 }
1220
1221 /* 4: Everything else */
654c90c6
BW		 1222 if (HAS_HW_CONTEXTS(dev))
1223 error->ccid = I915_READ(CCID);
1224
885ea5a8
RV		 1225 if (INTEL_INFO(dev)->gen >= 8) {
1226 error->ier = I915_READ(GEN8_DE_MISC_IER);
1227 for (i = 0; i < 4; i++)
1228 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1229 } else if (HAS_PCH_SPLIT(dev)) {
843db716 1230 error->ier = I915_READ(DEIER);
885ea5a8 1231 error->gtier[0] = I915_READ(GTIER);
843db716
RV		 1232 } else if (IS_GEN2(dev)) {
1233 error->ier = I915_READ16(IER);
1234 } else if (!IS_VALLEYVIEW(dev)) {
1235 error->ier = I915_READ(IER);
654c90c6 1236 }
654c90c6
BW		 1237 error->eir = I915_READ(EIR);
1238 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1239
1240 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1241}
1242
cb383002 1243static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1244 struct drm_i915_error_state *error,
1245 bool wedged,
1246 const char *error_msg)
cb383002
MK		 1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 u32 ecode;
58174462 1250 int ring_id = -1, len;
cb383002
MK		 1251
1252 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1253
58174462 1254 len = scnprintf(error->error_msg, sizeof(error->error_msg),
0b5492d6
MK		 1255 "GPU HANG: ecode %d:%d:0x%08x",
1256 INTEL_INFO(dev)->gen, ring_id, ecode);
58174462
MK		 1257
1258 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1259 len += scnprintf(error->error_msg + len,
1260 sizeof(error->error_msg) - len,
1261 ", in %s [%d]",
1262 error->ring[ring_id].comm,
1263 error->ring[ring_id].pid);
1264
1265 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1266 ", reason: %s, action: %s",
1267 error_msg,
1268 wedged ? "reset" : "continue");
cb383002
MK		 1269}
1270
48b031e3
MK		 1271static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1272 struct drm_i915_error_state *error)
1273{
eb5be9d0
CW		 1274 error->iommu = -1;
1275#ifdef CONFIG_INTEL_IOMMU
1276 error->iommu = intel_iommu_gfx_mapped;
1277#endif
48b031e3 1278 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1279 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1280}
1281
1d762aad
BW		 1282/**
1283 * i915_capture_error_state - capture an error record for later analysis
1284 * @dev: drm device
1285 *
1286 * Should be called when an error is detected (either a hang or an error
1287 * interrupt) to capture error state from the time of the error. Fills
1288 * out a structure which becomes available in debugfs for user level tools
1289 * to pick up.
1290 */
58174462
MK		 1291void i915_capture_error_state(struct drm_device *dev, bool wedged,
1292 const char *error_msg)
1d762aad 1293{
53a4c6b2 1294 static bool warned;
1d762aad
BW		 1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct drm_i915_error_state *error;
1297 unsigned long flags;
1d762aad
BW		 1298
1299 /* Account for pipe specific data like PIPE*STAT */
1300 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1301 if (!error) {
1302 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1303 return;
1304 }
1305
011cf577
BW		 1306 kref_init(&error->ref);
1307
48b031e3 1308 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1309 i915_capture_reg_state(dev_priv, error);
1310 i915_gem_capture_buffers(dev_priv, error);
1311 i915_gem_record_fences(dev, error);
1312 i915_gem_record_rings(dev, error);
1d762aad 1313
84734a04
MK		 1314 do_gettimeofday(&error->time);
1315
1316 error->overlay = intel_overlay_capture_error_state(dev);
1317 error->display = intel_display_capture_error_state(dev);
1318
58174462 1319 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1320 DRM_INFO("%s\n", error->error_msg);
1321
84734a04
MK		 1322 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1323 if (dev_priv->gpu_error.first_error == NULL) {
1324 dev_priv->gpu_error.first_error = error;
1325 error = NULL;
1326 }
1327 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1328
cb383002 1329 if (error) {
84734a04 1330 i915_error_state_free(&error->ref);
cb383002
MK		 1331 return;
1332 }
1333
1334 if (!warned) {
1335 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1336 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1337 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1338 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1339 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1340 warned = true;
1341 }
84734a04
MK		 1342}
1343
1344void i915_error_state_get(struct drm_device *dev,
1345 struct i915_error_state_file_priv *error_priv)
1346{
1347 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 1348
5b254c59 1349 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1350 error_priv->error = dev_priv->gpu_error.first_error;
1351 if (error_priv->error)
1352 kref_get(&error_priv->error->ref);
5b254c59 1353 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1354
1355}
1356
1357void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1358{
1359 if (error_priv->error)
1360 kref_put(&error_priv->error->ref, i915_error_state_free);
1361}
1362
1363void i915_destroy_error_state(struct drm_device *dev)
1364{
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 struct drm_i915_error_state *error;
84734a04 1367
5b254c59 1368 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1369 error = dev_priv->gpu_error.first_error;
1370 dev_priv->gpu_error.first_error = NULL;
5b254c59 1371 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1372
1373 if (error)
1374 kref_put(&error->ref, i915_error_state_free);
1375}
1376
0a4cd7c8 1377const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
84734a04
MK		 1378{
1379 switch (type) {
1380 case I915_CACHE_NONE: return " uncached";
0a4cd7c8 1381 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
350ec881 1382 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1383 case I915_CACHE_WT: return " WT";
84734a04
MK		 1384 default: return "";
1385 }
1386}
1387
1388/* NB: please notice the memset */
1389void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1390{
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1393
563f94f6 1394 if (IS_GEN2(dev) || IS_GEN3(dev))
84734a04 1395 instdone[0] = I915_READ(INSTDONE);
563f94f6 1396 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
84734a04
MK		 1397 instdone[0] = I915_READ(INSTDONE_I965);
1398 instdone[1] = I915_READ(INSTDONE1);
563f94f6 1399 } else if (INTEL_INFO(dev)->gen >= 7) {
84734a04
MK		 1400 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1401 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1402 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1403 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
84734a04
MK		 1404 }
1405}
Linux kernel - Deliverables
This page took 0.22734 seconds and 5 git commands to generate.