Commit | Line | Data |
---|---|---|
84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <generated/utsrelease.h> | |
31 | #include "i915_drv.h" | |
32 | ||
33 | static const char *yesno(int v) | |
34 | { | |
35 | return v ? "yes" : "no"; | |
36 | } | |
37 | ||
38 | static const char *ring_str(int ring) | |
39 | { | |
40 | switch (ring) { | |
41 | case RCS: return "render"; | |
42 | case VCS: return "bsd"; | |
43 | case BCS: return "blt"; | |
44 | case VECS: return "vebox"; | |
45 | default: return ""; | |
46 | } | |
47 | } | |
48 | ||
49 | static const char *pin_flag(int pinned) | |
50 | { | |
51 | if (pinned > 0) | |
52 | return " P"; | |
53 | else if (pinned < 0) | |
54 | return " p"; | |
55 | else | |
56 | return ""; | |
57 | } | |
58 | ||
59 | static const char *tiling_flag(int tiling) | |
60 | { | |
61 | switch (tiling) { | |
62 | default: | |
63 | case I915_TILING_NONE: return ""; | |
64 | case I915_TILING_X: return " X"; | |
65 | case I915_TILING_Y: return " Y"; | |
66 | } | |
67 | } | |
68 | ||
69 | static const char *dirty_flag(int dirty) | |
70 | { | |
71 | return dirty ? " dirty" : ""; | |
72 | } | |
73 | ||
74 | static const char *purgeable_flag(int purgeable) | |
75 | { | |
76 | return purgeable ? " purgeable" : ""; | |
77 | } | |
78 | ||
79 | static bool __i915_error_ok(struct drm_i915_error_state_buf *e) | |
80 | { | |
81 | ||
82 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { | |
83 | e->err = -ENOSPC; | |
84 | return false; | |
85 | } | |
86 | ||
87 | if (e->bytes == e->size - 1 || e->err) | |
88 | return false; | |
89 | ||
90 | return true; | |
91 | } | |
92 | ||
93 | static bool __i915_error_seek(struct drm_i915_error_state_buf *e, | |
94 | unsigned len) | |
95 | { | |
96 | if (e->pos + len <= e->start) { | |
97 | e->pos += len; | |
98 | return false; | |
99 | } | |
100 | ||
101 | /* First vsnprintf needs to fit in its entirety for memmove */ | |
102 | if (len >= e->size) { | |
103 | e->err = -EIO; | |
104 | return false; | |
105 | } | |
106 | ||
107 | return true; | |
108 | } | |
109 | ||
110 | static void __i915_error_advance(struct drm_i915_error_state_buf *e, | |
111 | unsigned len) | |
112 | { | |
113 | /* If this is first printf in this window, adjust it so that | |
114 | * start position matches start of the buffer | |
115 | */ | |
116 | ||
117 | if (e->pos < e->start) { | |
118 | const size_t off = e->start - e->pos; | |
119 | ||
120 | /* Should not happen but be paranoid */ | |
121 | if (off > len || e->bytes) { | |
122 | e->err = -EIO; | |
123 | return; | |
124 | } | |
125 | ||
126 | memmove(e->buf, e->buf + off, len - off); | |
127 | e->bytes = len - off; | |
128 | e->pos = e->start; | |
129 | return; | |
130 | } | |
131 | ||
132 | e->bytes += len; | |
133 | e->pos += len; | |
134 | } | |
135 | ||
136 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, | |
137 | const char *f, va_list args) | |
138 | { | |
139 | unsigned len; | |
140 | ||
141 | if (!__i915_error_ok(e)) | |
142 | return; | |
143 | ||
144 | /* Seek the first printf which is hits start position */ | |
145 | if (e->pos < e->start) { | |
e29bb4eb CW |
146 | va_list tmp; |
147 | ||
148 | va_copy(tmp, args); | |
149 | if (!__i915_error_seek(e, vsnprintf(NULL, 0, f, tmp))) | |
84734a04 MK |
150 | return; |
151 | } | |
152 | ||
153 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); | |
154 | if (len >= e->size - e->bytes) | |
155 | len = e->size - e->bytes - 1; | |
156 | ||
157 | __i915_error_advance(e, len); | |
158 | } | |
159 | ||
160 | static void i915_error_puts(struct drm_i915_error_state_buf *e, | |
161 | const char *str) | |
162 | { | |
163 | unsigned len; | |
164 | ||
165 | if (!__i915_error_ok(e)) | |
166 | return; | |
167 | ||
168 | len = strlen(str); | |
169 | ||
170 | /* Seek the first printf which is hits start position */ | |
171 | if (e->pos < e->start) { | |
172 | if (!__i915_error_seek(e, len)) | |
173 | return; | |
174 | } | |
175 | ||
176 | if (len >= e->size - e->bytes) | |
177 | len = e->size - e->bytes - 1; | |
178 | memcpy(e->buf + e->bytes, str, len); | |
179 | ||
180 | __i915_error_advance(e, len); | |
181 | } | |
182 | ||
183 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
184 | #define err_puts(e, s) i915_error_puts(e, s) | |
185 | ||
186 | static void print_error_buffers(struct drm_i915_error_state_buf *m, | |
187 | const char *name, | |
188 | struct drm_i915_error_buffer *err, | |
189 | int count) | |
190 | { | |
191 | err_printf(m, "%s [%d]:\n", name, count); | |
192 | ||
193 | while (count--) { | |
194 | err_printf(m, " %08x %8u %02x %02x %x %x", | |
195 | err->gtt_offset, | |
196 | err->size, | |
197 | err->read_domains, | |
198 | err->write_domain, | |
199 | err->rseqno, err->wseqno); | |
200 | err_puts(m, pin_flag(err->pinned)); | |
201 | err_puts(m, tiling_flag(err->tiling)); | |
202 | err_puts(m, dirty_flag(err->dirty)); | |
203 | err_puts(m, purgeable_flag(err->purgeable)); | |
204 | err_puts(m, err->ring != -1 ? " " : ""); | |
205 | err_puts(m, ring_str(err->ring)); | |
206 | err_puts(m, i915_cache_level_str(err->cache_level)); | |
207 | ||
208 | if (err->name) | |
209 | err_printf(m, " (name: %d)", err->name); | |
210 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
211 | err_printf(m, " (fence: %d)", err->fence_reg); | |
212 | ||
213 | err_puts(m, "\n"); | |
214 | err++; | |
215 | } | |
216 | } | |
217 | ||
da661464 MK |
218 | static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) |
219 | { | |
220 | switch (a) { | |
221 | case HANGCHECK_IDLE: | |
222 | return "idle"; | |
223 | case HANGCHECK_WAIT: | |
224 | return "wait"; | |
225 | case HANGCHECK_ACTIVE: | |
226 | return "active"; | |
227 | case HANGCHECK_KICK: | |
228 | return "kick"; | |
229 | case HANGCHECK_HUNG: | |
230 | return "hung"; | |
231 | } | |
232 | ||
233 | return "unknown"; | |
234 | } | |
235 | ||
84734a04 MK |
236 | static void i915_ring_error_state(struct drm_i915_error_state_buf *m, |
237 | struct drm_device *dev, | |
362b8af7 | 238 | struct drm_i915_error_ring *ring) |
84734a04 | 239 | { |
362b8af7 | 240 | if (!ring->valid) |
372fbb8e CW |
241 | return; |
242 | ||
362b8af7 BW |
243 | err_printf(m, " HEAD: 0x%08x\n", ring->head); |
244 | err_printf(m, " TAIL: 0x%08x\n", ring->tail); | |
245 | err_printf(m, " CTL: 0x%08x\n", ring->ctl); | |
246 | err_printf(m, " HWS: 0x%08x\n", ring->hws); | |
247 | err_printf(m, " ACTHD: 0x%08x\n", ring->acthd); | |
248 | err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); | |
249 | err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); | |
250 | err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); | |
3dda20a9 | 251 | if (INTEL_INFO(dev)->gen >= 4) { |
362b8af7 BW |
252 | err_printf(m, " BBADDR: 0x%08llx\n", ring->bbaddr); |
253 | err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); | |
254 | err_printf(m, " INSTPS: 0x%08x\n", ring->instps); | |
3dda20a9 | 255 | } |
362b8af7 BW |
256 | err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); |
257 | err_printf(m, " FADDR: 0x%08x\n", ring->faddr); | |
84734a04 | 258 | if (INTEL_INFO(dev)->gen >= 6) { |
362b8af7 BW |
259 | err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); |
260 | err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); | |
84734a04 | 261 | err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
262 | ring->semaphore_mboxes[0], |
263 | ring->semaphore_seqno[0]); | |
84734a04 | 264 | err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
265 | ring->semaphore_mboxes[1], |
266 | ring->semaphore_seqno[1]); | |
4e5aabfd BW |
267 | if (HAS_VEBOX(dev)) { |
268 | err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", | |
362b8af7 BW |
269 | ring->semaphore_mboxes[2], |
270 | ring->semaphore_seqno[2]); | |
4e5aabfd | 271 | } |
84734a04 | 272 | } |
6c7a01ec BW |
273 | if (USES_PPGTT(dev)) { |
274 | err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); | |
275 | ||
276 | if (INTEL_INFO(dev)->gen >= 8) { | |
277 | int i; | |
278 | for (i = 0; i < 4; i++) | |
279 | err_printf(m, " PDP%d: 0x%016llx\n", | |
280 | i, ring->vm_info.pdp[i]); | |
281 | } else { | |
282 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
283 | ring->vm_info.pp_dir_base); | |
284 | } | |
285 | } | |
362b8af7 BW |
286 | err_printf(m, " seqno: 0x%08x\n", ring->seqno); |
287 | err_printf(m, " waiting: %s\n", yesno(ring->waiting)); | |
288 | err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); | |
289 | err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); | |
da661464 | 290 | err_printf(m, " hangcheck: %s [%d]\n", |
362b8af7 BW |
291 | hangcheck_action_to_str(ring->hangcheck_action), |
292 | ring->hangcheck_score); | |
84734a04 MK |
293 | } |
294 | ||
295 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
296 | { | |
297 | va_list args; | |
298 | ||
299 | va_start(args, f); | |
300 | i915_error_vprintf(e, f, args); | |
301 | va_end(args); | |
302 | } | |
303 | ||
304 | int i915_error_state_to_str(struct drm_i915_error_state_buf *m, | |
305 | const struct i915_error_state_file_priv *error_priv) | |
306 | { | |
307 | struct drm_device *dev = error_priv->dev; | |
308 | drm_i915_private_t *dev_priv = dev->dev_private; | |
309 | struct drm_i915_error_state *error = error_priv->error; | |
84734a04 MK |
310 | int i, j, page, offset, elt; |
311 | ||
312 | if (!error) { | |
313 | err_printf(m, "no error state collected\n"); | |
314 | goto out; | |
315 | } | |
316 | ||
317 | err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, | |
318 | error->time.tv_usec); | |
319 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); | |
ffbab09b | 320 | err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); |
84734a04 MK |
321 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
322 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
323 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); | |
324 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
325 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
326 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
094f9a54 | 327 | err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); |
84734a04 MK |
328 | |
329 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
330 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); | |
331 | ||
332 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) | |
333 | err_printf(m, " INSTDONE_%d: 0x%08x\n", i, | |
334 | error->extra_instdone[i]); | |
335 | ||
336 | if (INTEL_INFO(dev)->gen >= 6) { | |
337 | err_printf(m, "ERROR: 0x%08x\n", error->error); | |
338 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); | |
339 | } | |
340 | ||
341 | if (INTEL_INFO(dev)->gen == 7) | |
342 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); | |
343 | ||
362b8af7 BW |
344 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { |
345 | err_printf(m, "%s command stream:\n", ring_str(i)); | |
346 | i915_ring_error_state(m, dev, &error->ring[i]); | |
347 | } | |
84734a04 MK |
348 | |
349 | if (error->active_bo) | |
350 | print_error_buffers(m, "Active", | |
95f5301d BW |
351 | error->active_bo[0], |
352 | error->active_bo_count[0]); | |
84734a04 MK |
353 | |
354 | if (error->pinned_bo) | |
355 | print_error_buffers(m, "Pinned", | |
95f5301d BW |
356 | error->pinned_bo[0], |
357 | error->pinned_bo_count[0]); | |
84734a04 MK |
358 | |
359 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
360 | struct drm_i915_error_object *obj; | |
361 | ||
362 | if ((obj = error->ring[i].batchbuffer)) { | |
363 | err_printf(m, "%s --- gtt_offset = 0x%08x\n", | |
364 | dev_priv->ring[i].name, | |
365 | obj->gtt_offset); | |
366 | offset = 0; | |
367 | for (page = 0; page < obj->page_count; page++) { | |
368 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
369 | err_printf(m, "%08x : %08x\n", offset, | |
370 | obj->pages[page][elt]); | |
371 | offset += 4; | |
372 | } | |
373 | } | |
374 | } | |
375 | ||
376 | if (error->ring[i].num_requests) { | |
377 | err_printf(m, "%s --- %d requests\n", | |
378 | dev_priv->ring[i].name, | |
379 | error->ring[i].num_requests); | |
380 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
381 | err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", | |
382 | error->ring[i].requests[j].seqno, | |
383 | error->ring[i].requests[j].jiffies, | |
384 | error->ring[i].requests[j].tail); | |
385 | } | |
386 | } | |
387 | ||
388 | if ((obj = error->ring[i].ringbuffer)) { | |
389 | err_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
390 | dev_priv->ring[i].name, | |
391 | obj->gtt_offset); | |
392 | offset = 0; | |
393 | for (page = 0; page < obj->page_count; page++) { | |
394 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
395 | err_printf(m, "%08x : %08x\n", | |
396 | offset, | |
397 | obj->pages[page][elt]); | |
398 | offset += 4; | |
399 | } | |
400 | } | |
401 | } | |
402 | ||
362b8af7 | 403 | if ((obj = error->ring[i].hws_page)) { |
f3ce3821 CW |
404 | err_printf(m, "%s --- HW Status = 0x%08x\n", |
405 | dev_priv->ring[i].name, | |
406 | obj->gtt_offset); | |
407 | offset = 0; | |
408 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
409 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
410 | offset, | |
411 | obj->pages[0][elt], | |
412 | obj->pages[0][elt+1], | |
413 | obj->pages[0][elt+2], | |
414 | obj->pages[0][elt+3]); | |
415 | offset += 16; | |
416 | } | |
417 | } | |
418 | ||
372fbb8e | 419 | if ((obj = error->ring[i].ctx)) { |
84734a04 MK |
420 | err_printf(m, "%s --- HW Context = 0x%08x\n", |
421 | dev_priv->ring[i].name, | |
422 | obj->gtt_offset); | |
423 | offset = 0; | |
424 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
425 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
426 | offset, | |
427 | obj->pages[0][elt], | |
428 | obj->pages[0][elt+1], | |
429 | obj->pages[0][elt+2], | |
430 | obj->pages[0][elt+3]); | |
431 | offset += 16; | |
432 | } | |
433 | } | |
434 | } | |
435 | ||
436 | if (error->overlay) | |
437 | intel_overlay_print_error_state(m, error->overlay); | |
438 | ||
439 | if (error->display) | |
440 | intel_display_print_error_state(m, dev, error->display); | |
441 | ||
442 | out: | |
443 | if (m->bytes == 0 && m->err) | |
444 | return m->err; | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
449 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, | |
450 | size_t count, loff_t pos) | |
451 | { | |
452 | memset(ebuf, 0, sizeof(*ebuf)); | |
453 | ||
454 | /* We need to have enough room to store any i915_error_state printf | |
455 | * so that we can move it to start position. | |
456 | */ | |
457 | ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; | |
458 | ebuf->buf = kmalloc(ebuf->size, | |
459 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); | |
460 | ||
461 | if (ebuf->buf == NULL) { | |
462 | ebuf->size = PAGE_SIZE; | |
463 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
464 | } | |
465 | ||
466 | if (ebuf->buf == NULL) { | |
467 | ebuf->size = 128; | |
468 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
469 | } | |
470 | ||
471 | if (ebuf->buf == NULL) | |
472 | return -ENOMEM; | |
473 | ||
474 | ebuf->start = pos; | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static void i915_error_object_free(struct drm_i915_error_object *obj) | |
480 | { | |
481 | int page; | |
482 | ||
483 | if (obj == NULL) | |
484 | return; | |
485 | ||
486 | for (page = 0; page < obj->page_count; page++) | |
487 | kfree(obj->pages[page]); | |
488 | ||
489 | kfree(obj); | |
490 | } | |
491 | ||
492 | static void i915_error_state_free(struct kref *error_ref) | |
493 | { | |
494 | struct drm_i915_error_state *error = container_of(error_ref, | |
495 | typeof(*error), ref); | |
496 | int i; | |
497 | ||
498 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
499 | i915_error_object_free(error->ring[i].batchbuffer); | |
500 | i915_error_object_free(error->ring[i].ringbuffer); | |
362b8af7 | 501 | i915_error_object_free(error->ring[i].hws_page); |
84734a04 MK |
502 | i915_error_object_free(error->ring[i].ctx); |
503 | kfree(error->ring[i].requests); | |
504 | } | |
505 | ||
506 | kfree(error->active_bo); | |
507 | kfree(error->overlay); | |
508 | kfree(error->display); | |
509 | kfree(error); | |
510 | } | |
511 | ||
512 | static struct drm_i915_error_object * | |
513 | i915_error_object_create_sized(struct drm_i915_private *dev_priv, | |
514 | struct drm_i915_gem_object *src, | |
a7b91078 | 515 | struct i915_address_space *vm, |
84734a04 MK |
516 | const int num_pages) |
517 | { | |
518 | struct drm_i915_error_object *dst; | |
519 | int i; | |
520 | u32 reloc_offset; | |
521 | ||
522 | if (src == NULL || src->pages == NULL) | |
523 | return NULL; | |
524 | ||
525 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); | |
526 | if (dst == NULL) | |
527 | return NULL; | |
528 | ||
a7b91078 | 529 | reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); |
84734a04 MK |
530 | for (i = 0; i < num_pages; i++) { |
531 | unsigned long flags; | |
532 | void *d; | |
533 | ||
534 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); | |
535 | if (d == NULL) | |
536 | goto unwind; | |
537 | ||
538 | local_irq_save(flags); | |
539 | if (reloc_offset < dev_priv->gtt.mappable_end && | |
496bfcb9 BW |
540 | src->has_global_gtt_mapping && |
541 | i915_is_ggtt(vm)) { | |
84734a04 MK |
542 | void __iomem *s; |
543 | ||
544 | /* Simply ignore tiling or any overlapping fence. | |
545 | * It's part of the error state, and this hopefully | |
546 | * captures what the GPU read. | |
547 | */ | |
548 | ||
549 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
550 | reloc_offset); | |
551 | memcpy_fromio(d, s, PAGE_SIZE); | |
552 | io_mapping_unmap_atomic(s); | |
553 | } else if (src->stolen) { | |
554 | unsigned long offset; | |
555 | ||
556 | offset = dev_priv->mm.stolen_base; | |
557 | offset += src->stolen->start; | |
558 | offset += i << PAGE_SHIFT; | |
559 | ||
560 | memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE); | |
561 | } else { | |
562 | struct page *page; | |
563 | void *s; | |
564 | ||
565 | page = i915_gem_object_get_page(src, i); | |
566 | ||
567 | drm_clflush_pages(&page, 1); | |
568 | ||
569 | s = kmap_atomic(page); | |
570 | memcpy(d, s, PAGE_SIZE); | |
571 | kunmap_atomic(s); | |
572 | ||
573 | drm_clflush_pages(&page, 1); | |
574 | } | |
575 | local_irq_restore(flags); | |
576 | ||
577 | dst->pages[i] = d; | |
578 | ||
579 | reloc_offset += PAGE_SIZE; | |
580 | } | |
581 | dst->page_count = num_pages; | |
582 | ||
583 | return dst; | |
584 | ||
585 | unwind: | |
586 | while (i--) | |
587 | kfree(dst->pages[i]); | |
588 | kfree(dst); | |
589 | return NULL; | |
590 | } | |
a7b91078 BW |
591 | #define i915_error_object_create(dev_priv, src, vm) \ |
592 | i915_error_object_create_sized((dev_priv), (src), (vm), \ | |
593 | (src)->base.size>>PAGE_SHIFT) | |
594 | ||
595 | #define i915_error_ggtt_object_create(dev_priv, src) \ | |
596 | i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ | |
84734a04 MK |
597 | (src)->base.size>>PAGE_SHIFT) |
598 | ||
599 | static void capture_bo(struct drm_i915_error_buffer *err, | |
600 | struct drm_i915_gem_object *obj) | |
601 | { | |
602 | err->size = obj->base.size; | |
603 | err->name = obj->base.name; | |
604 | err->rseqno = obj->last_read_seqno; | |
605 | err->wseqno = obj->last_write_seqno; | |
606 | err->gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
607 | err->read_domains = obj->base.read_domains; | |
608 | err->write_domain = obj->base.write_domain; | |
609 | err->fence_reg = obj->fence_reg; | |
610 | err->pinned = 0; | |
d7f46fc4 | 611 | if (i915_gem_obj_is_pinned(obj)) |
84734a04 MK |
612 | err->pinned = 1; |
613 | if (obj->user_pin_count > 0) | |
614 | err->pinned = -1; | |
615 | err->tiling = obj->tiling_mode; | |
616 | err->dirty = obj->dirty; | |
617 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
618 | err->ring = obj->ring ? obj->ring->id : -1; | |
619 | err->cache_level = obj->cache_level; | |
620 | } | |
621 | ||
622 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, | |
623 | int count, struct list_head *head) | |
624 | { | |
ca191b13 | 625 | struct i915_vma *vma; |
84734a04 MK |
626 | int i = 0; |
627 | ||
ca191b13 BW |
628 | list_for_each_entry(vma, head, mm_list) { |
629 | capture_bo(err++, vma->obj); | |
84734a04 MK |
630 | if (++i == count) |
631 | break; | |
632 | } | |
633 | ||
634 | return i; | |
635 | } | |
636 | ||
637 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
638 | int count, struct list_head *head) | |
639 | { | |
640 | struct drm_i915_gem_object *obj; | |
641 | int i = 0; | |
642 | ||
643 | list_for_each_entry(obj, head, global_list) { | |
d7f46fc4 | 644 | if (!i915_gem_obj_is_pinned(obj)) |
84734a04 MK |
645 | continue; |
646 | ||
647 | capture_bo(err++, obj); | |
648 | if (++i == count) | |
649 | break; | |
650 | } | |
651 | ||
652 | return i; | |
653 | } | |
654 | ||
655 | static void i915_gem_record_fences(struct drm_device *dev, | |
656 | struct drm_i915_error_state *error) | |
657 | { | |
658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
659 | int i; | |
660 | ||
661 | /* Fences */ | |
662 | switch (INTEL_INFO(dev)->gen) { | |
5ab31333 | 663 | case 8: |
84734a04 MK |
664 | case 7: |
665 | case 6: | |
666 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
667 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
668 | break; | |
669 | case 5: | |
670 | case 4: | |
671 | for (i = 0; i < 16; i++) | |
672 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
673 | break; | |
674 | case 3: | |
675 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
676 | for (i = 0; i < 8; i++) | |
677 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
678 | case 2: | |
679 | for (i = 0; i < 8; i++) | |
680 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
681 | break; | |
682 | ||
683 | default: | |
684 | BUG(); | |
685 | } | |
686 | } | |
687 | ||
685987c6 BW |
688 | /* This assumes all batchbuffers are executed from the PPGTT. It might have to |
689 | * change in the future. */ | |
690 | static bool is_active_vm(struct i915_address_space *vm, | |
691 | struct intel_ring_buffer *ring) | |
692 | { | |
693 | struct drm_device *dev = vm->dev; | |
694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
695 | struct i915_hw_ppgtt *ppgtt; | |
696 | ||
697 | if (INTEL_INFO(dev)->gen < 7) | |
698 | return i915_is_ggtt(vm); | |
699 | ||
700 | /* FIXME: This ignores that the global gtt vm is also on this list. */ | |
701 | ppgtt = container_of(vm, struct i915_hw_ppgtt, base); | |
702 | ||
703 | if (INTEL_INFO(dev)->gen >= 8) { | |
704 | u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32; | |
705 | pdp0 |= I915_READ(GEN8_RING_PDP_LDW(ring, 0)); | |
706 | return pdp0 == ppgtt->pd_dma_addr[0]; | |
707 | } else { | |
708 | u32 pp_db; | |
709 | pp_db = I915_READ(RING_PP_DIR_BASE(ring)); | |
710 | return (pp_db >> 10) == ppgtt->pd_offset; | |
711 | } | |
712 | } | |
713 | ||
84734a04 MK |
714 | static struct drm_i915_error_object * |
715 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
716 | struct intel_ring_buffer *ring) | |
717 | { | |
ca191b13 BW |
718 | struct i915_address_space *vm; |
719 | struct i915_vma *vma; | |
84734a04 | 720 | struct drm_i915_gem_object *obj; |
685987c6 | 721 | bool found_active = false; |
84734a04 MK |
722 | u32 seqno; |
723 | ||
724 | if (!ring->get_seqno) | |
725 | return NULL; | |
726 | ||
727 | if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { | |
728 | u32 acthd = I915_READ(ACTHD); | |
729 | ||
730 | if (WARN_ON(ring->id != RCS)) | |
731 | return NULL; | |
732 | ||
0d1aacac | 733 | obj = ring->scratch.obj; |
372fbb8e CW |
734 | if (obj != NULL && |
735 | acthd >= i915_gem_obj_ggtt_offset(obj) && | |
84734a04 | 736 | acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size) |
a7b91078 | 737 | return i915_error_ggtt_object_create(dev_priv, obj); |
84734a04 MK |
738 | } |
739 | ||
740 | seqno = ring->get_seqno(ring, false); | |
ca191b13 | 741 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
685987c6 BW |
742 | if (!is_active_vm(vm, ring)) |
743 | continue; | |
744 | ||
745 | found_active = true; | |
746 | ||
ca191b13 BW |
747 | list_for_each_entry(vma, &vm->active_list, mm_list) { |
748 | obj = vma->obj; | |
749 | if (obj->ring != ring) | |
750 | continue; | |
84734a04 | 751 | |
ca191b13 BW |
752 | if (i915_seqno_passed(seqno, obj->last_read_seqno)) |
753 | continue; | |
84734a04 | 754 | |
ca191b13 BW |
755 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) |
756 | continue; | |
84734a04 | 757 | |
ca191b13 BW |
758 | /* We need to copy these to an anonymous buffer as the simplest |
759 | * method to avoid being overwritten by userspace. | |
760 | */ | |
a7b91078 | 761 | return i915_error_object_create(dev_priv, obj, vm); |
ca191b13 | 762 | } |
84734a04 MK |
763 | } |
764 | ||
685987c6 | 765 | WARN_ON(!found_active); |
84734a04 MK |
766 | return NULL; |
767 | } | |
768 | ||
769 | static void i915_record_ring_state(struct drm_device *dev, | |
362b8af7 BW |
770 | struct intel_ring_buffer *ring, |
771 | struct drm_i915_error_ring *ering) | |
84734a04 MK |
772 | { |
773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
774 | ||
775 | if (INTEL_INFO(dev)->gen >= 6) { | |
362b8af7 BW |
776 | ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); |
777 | ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
778 | ering->semaphore_mboxes[0] | |
84734a04 | 779 | = I915_READ(RING_SYNC_0(ring->mmio_base)); |
362b8af7 | 780 | ering->semaphore_mboxes[1] |
84734a04 | 781 | = I915_READ(RING_SYNC_1(ring->mmio_base)); |
362b8af7 BW |
782 | ering->semaphore_seqno[0] = ring->sync_seqno[0]; |
783 | ering->semaphore_seqno[1] = ring->sync_seqno[1]; | |
84734a04 MK |
784 | } |
785 | ||
4e5aabfd | 786 | if (HAS_VEBOX(dev)) { |
362b8af7 | 787 | ering->semaphore_mboxes[2] = |
4e5aabfd | 788 | I915_READ(RING_SYNC_2(ring->mmio_base)); |
362b8af7 | 789 | ering->semaphore_seqno[2] = ring->sync_seqno[2]; |
4e5aabfd BW |
790 | } |
791 | ||
84734a04 | 792 | if (INTEL_INFO(dev)->gen >= 4) { |
362b8af7 BW |
793 | ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
794 | ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); | |
795 | ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
796 | ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
797 | ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); | |
798 | ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); | |
3dda20a9 | 799 | if (INTEL_INFO(dev)->gen >= 8) |
362b8af7 BW |
800 | ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; |
801 | ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); | |
84734a04 | 802 | } else { |
362b8af7 BW |
803 | ering->faddr = I915_READ(DMA_FADD_I8XX); |
804 | ering->ipeir = I915_READ(IPEIR); | |
805 | ering->ipehr = I915_READ(IPEHR); | |
806 | ering->instdone = I915_READ(INSTDONE); | |
84734a04 MK |
807 | } |
808 | ||
362b8af7 BW |
809 | ering->waiting = waitqueue_active(&ring->irq_queue); |
810 | ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); | |
811 | ering->seqno = ring->get_seqno(ring, false); | |
812 | ering->acthd = intel_ring_get_active_head(ring); | |
813 | ering->head = I915_READ_HEAD(ring); | |
814 | ering->tail = I915_READ_TAIL(ring); | |
815 | ering->ctl = I915_READ_CTL(ring); | |
84734a04 | 816 | |
f3ce3821 CW |
817 | if (I915_NEED_GFX_HWS(dev)) { |
818 | int mmio; | |
819 | ||
820 | if (IS_GEN7(dev)) { | |
821 | switch (ring->id) { | |
822 | default: | |
823 | case RCS: | |
824 | mmio = RENDER_HWS_PGA_GEN7; | |
825 | break; | |
826 | case BCS: | |
827 | mmio = BLT_HWS_PGA_GEN7; | |
828 | break; | |
829 | case VCS: | |
830 | mmio = BSD_HWS_PGA_GEN7; | |
831 | break; | |
832 | case VECS: | |
833 | mmio = VEBOX_HWS_PGA_GEN7; | |
834 | break; | |
835 | } | |
836 | } else if (IS_GEN6(ring->dev)) { | |
837 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
838 | } else { | |
839 | /* XXX: gen8 returns to sanity */ | |
840 | mmio = RING_HWS_PGA(ring->mmio_base); | |
841 | } | |
842 | ||
362b8af7 | 843 | ering->hws = I915_READ(mmio); |
f3ce3821 CW |
844 | } |
845 | ||
362b8af7 BW |
846 | ering->cpu_ring_head = ring->head; |
847 | ering->cpu_ring_tail = ring->tail; | |
da661464 | 848 | |
362b8af7 BW |
849 | ering->hangcheck_score = ring->hangcheck.score; |
850 | ering->hangcheck_action = ring->hangcheck.action; | |
6c7a01ec BW |
851 | |
852 | if (USES_PPGTT(dev)) { | |
853 | int i; | |
854 | ||
855 | ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); | |
856 | ||
857 | switch (INTEL_INFO(dev)->gen) { | |
858 | case 8: | |
859 | for (i = 0; i < 4; i++) { | |
860 | ering->vm_info.pdp[i] = | |
861 | I915_READ(GEN8_RING_PDP_UDW(ring, i)); | |
862 | ering->vm_info.pdp[i] <<= 32; | |
863 | ering->vm_info.pdp[i] |= | |
864 | I915_READ(GEN8_RING_PDP_LDW(ring, i)); | |
865 | } | |
866 | break; | |
867 | case 7: | |
868 | ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring); | |
869 | break; | |
870 | case 6: | |
871 | ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring); | |
872 | break; | |
873 | } | |
874 | } | |
84734a04 MK |
875 | } |
876 | ||
877 | ||
878 | static void i915_gem_record_active_context(struct intel_ring_buffer *ring, | |
879 | struct drm_i915_error_state *error, | |
880 | struct drm_i915_error_ring *ering) | |
881 | { | |
882 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
883 | struct drm_i915_gem_object *obj; | |
884 | ||
885 | /* Currently render ring is the only HW context user */ | |
886 | if (ring->id != RCS || !error->ccid) | |
887 | return; | |
888 | ||
889 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
890 | if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { | |
891 | ering->ctx = i915_error_object_create_sized(dev_priv, | |
a7b91078 BW |
892 | obj, |
893 | &dev_priv->gtt.base, | |
894 | 1); | |
84734a04 MK |
895 | break; |
896 | } | |
897 | } | |
898 | } | |
899 | ||
900 | static void i915_gem_record_rings(struct drm_device *dev, | |
901 | struct drm_i915_error_state *error) | |
902 | { | |
903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84734a04 MK |
904 | struct drm_i915_gem_request *request; |
905 | int i, count; | |
906 | ||
372fbb8e CW |
907 | for (i = 0; i < I915_NUM_RINGS; i++) { |
908 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
909 | ||
910 | if (ring->dev == NULL) | |
911 | continue; | |
912 | ||
913 | error->ring[i].valid = true; | |
914 | ||
362b8af7 | 915 | i915_record_ring_state(dev, ring, &error->ring[i]); |
84734a04 MK |
916 | |
917 | error->ring[i].batchbuffer = | |
918 | i915_error_first_batchbuffer(dev_priv, ring); | |
919 | ||
920 | error->ring[i].ringbuffer = | |
a7b91078 | 921 | i915_error_ggtt_object_create(dev_priv, ring->obj); |
84734a04 | 922 | |
f3ce3821 | 923 | if (ring->status_page.obj) |
362b8af7 | 924 | error->ring[i].hws_page = |
f3ce3821 | 925 | i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); |
84734a04 MK |
926 | |
927 | i915_gem_record_active_context(ring, error, &error->ring[i]); | |
928 | ||
929 | count = 0; | |
930 | list_for_each_entry(request, &ring->request_list, list) | |
931 | count++; | |
932 | ||
933 | error->ring[i].num_requests = count; | |
934 | error->ring[i].requests = | |
a1e22653 | 935 | kcalloc(count, sizeof(*error->ring[i].requests), |
84734a04 MK |
936 | GFP_ATOMIC); |
937 | if (error->ring[i].requests == NULL) { | |
938 | error->ring[i].num_requests = 0; | |
939 | continue; | |
940 | } | |
941 | ||
942 | count = 0; | |
943 | list_for_each_entry(request, &ring->request_list, list) { | |
944 | struct drm_i915_error_request *erq; | |
945 | ||
946 | erq = &error->ring[i].requests[count++]; | |
947 | erq->seqno = request->seqno; | |
948 | erq->jiffies = request->emitted_jiffies; | |
949 | erq->tail = request->tail; | |
950 | } | |
951 | } | |
952 | } | |
953 | ||
95f5301d BW |
954 | /* FIXME: Since pin count/bound list is global, we duplicate what we capture per |
955 | * VM. | |
956 | */ | |
957 | static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, | |
958 | struct drm_i915_error_state *error, | |
959 | struct i915_address_space *vm, | |
960 | const int ndx) | |
84734a04 | 961 | { |
95f5301d | 962 | struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; |
84734a04 | 963 | struct drm_i915_gem_object *obj; |
95f5301d | 964 | struct i915_vma *vma; |
84734a04 MK |
965 | int i; |
966 | ||
967 | i = 0; | |
ca191b13 | 968 | list_for_each_entry(vma, &vm->active_list, mm_list) |
84734a04 | 969 | i++; |
95f5301d | 970 | error->active_bo_count[ndx] = i; |
84734a04 | 971 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 972 | if (i915_gem_obj_is_pinned(obj)) |
84734a04 | 973 | i++; |
95f5301d | 974 | error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; |
84734a04 MK |
975 | |
976 | if (i) { | |
a1e22653 | 977 | active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); |
95f5301d BW |
978 | if (active_bo) |
979 | pinned_bo = active_bo + error->active_bo_count[ndx]; | |
84734a04 MK |
980 | } |
981 | ||
95f5301d BW |
982 | if (active_bo) |
983 | error->active_bo_count[ndx] = | |
984 | capture_active_bo(active_bo, | |
985 | error->active_bo_count[ndx], | |
5cef07e1 | 986 | &vm->active_list); |
84734a04 | 987 | |
95f5301d BW |
988 | if (pinned_bo) |
989 | error->pinned_bo_count[ndx] = | |
990 | capture_pinned_bo(pinned_bo, | |
991 | error->pinned_bo_count[ndx], | |
84734a04 | 992 | &dev_priv->mm.bound_list); |
95f5301d BW |
993 | error->active_bo[ndx] = active_bo; |
994 | error->pinned_bo[ndx] = pinned_bo; | |
995 | } | |
996 | ||
997 | static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, | |
998 | struct drm_i915_error_state *error) | |
999 | { | |
1000 | struct i915_address_space *vm; | |
1001 | int cnt = 0, i = 0; | |
1002 | ||
1003 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1004 | cnt++; | |
1005 | ||
95f5301d BW |
1006 | error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); |
1007 | error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); | |
1008 | error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), | |
1009 | GFP_ATOMIC); | |
1010 | error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), | |
1011 | GFP_ATOMIC); | |
1012 | ||
1013 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1014 | i915_gem_capture_vm(dev_priv, error, vm, i++); | |
84734a04 MK |
1015 | } |
1016 | ||
1d762aad BW |
1017 | /* Capture all registers which don't fit into another category. */ |
1018 | static void i915_capture_reg_state(struct drm_i915_private *dev_priv, | |
1019 | struct drm_i915_error_state *error) | |
84734a04 | 1020 | { |
1d762aad | 1021 | struct drm_device *dev = dev_priv->dev; |
84734a04 MK |
1022 | int pipe; |
1023 | ||
654c90c6 BW |
1024 | /* General organization |
1025 | * 1. Registers specific to a single generation | |
1026 | * 2. Registers which belong to multiple generations | |
1027 | * 3. Feature specific registers. | |
1028 | * 4. Everything else | |
1029 | * Please try to follow the order. | |
1030 | */ | |
84734a04 | 1031 | |
654c90c6 BW |
1032 | /* 1: Registers specific to a single generation */ |
1033 | if (IS_VALLEYVIEW(dev)) { | |
84734a04 | 1034 | error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); |
654c90c6 BW |
1035 | error->forcewake = I915_READ(FORCEWAKE_VLV); |
1036 | } | |
84734a04 | 1037 | |
654c90c6 BW |
1038 | if (IS_GEN7(dev)) |
1039 | error->err_int = I915_READ(GEN7_ERR_INT); | |
84734a04 | 1040 | |
91ec5d11 | 1041 | if (IS_GEN6(dev)) { |
84734a04 | 1042 | error->forcewake = I915_READ(FORCEWAKE); |
91ec5d11 BW |
1043 | error->gab_ctl = I915_READ(GAB_CTL); |
1044 | error->gfx_mode = I915_READ(GFX_MODE); | |
1045 | } | |
84734a04 | 1046 | |
654c90c6 BW |
1047 | if (IS_GEN2(dev)) |
1048 | error->ier = I915_READ16(IER); | |
1049 | ||
1050 | /* 2: Registers which belong to multiple generations */ | |
1051 | if (INTEL_INFO(dev)->gen >= 7) | |
1052 | error->forcewake = I915_READ(FORCEWAKE_MT); | |
84734a04 MK |
1053 | |
1054 | if (INTEL_INFO(dev)->gen >= 6) { | |
654c90c6 | 1055 | error->derrmr = I915_READ(DERRMR); |
84734a04 MK |
1056 | error->error = I915_READ(ERROR_GEN6); |
1057 | error->done_reg = I915_READ(DONE_REG); | |
1058 | } | |
1059 | ||
654c90c6 | 1060 | /* 3: Feature specific registers */ |
91ec5d11 BW |
1061 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1062 | error->gam_ecochk = I915_READ(GAM_ECOCHK); | |
1063 | error->gac_eco = I915_READ(GAC_ECO_BITS); | |
1064 | } | |
1065 | ||
1066 | /* 4: Everything else */ | |
654c90c6 BW |
1067 | if (HAS_HW_CONTEXTS(dev)) |
1068 | error->ccid = I915_READ(CCID); | |
1069 | ||
1070 | if (HAS_PCH_SPLIT(dev)) | |
1071 | error->ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1072 | else { | |
1073 | error->ier = I915_READ(IER); | |
1074 | for_each_pipe(pipe) | |
1075 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
1076 | } | |
1077 | ||
1078 | /* 4: Everything else */ | |
1079 | error->eir = I915_READ(EIR); | |
1080 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
84734a04 MK |
1081 | |
1082 | i915_get_extra_instdone(dev, error->extra_instdone); | |
1d762aad BW |
1083 | } |
1084 | ||
1085 | /** | |
1086 | * i915_capture_error_state - capture an error record for later analysis | |
1087 | * @dev: drm device | |
1088 | * | |
1089 | * Should be called when an error is detected (either a hang or an error | |
1090 | * interrupt) to capture error state from the time of the error. Fills | |
1091 | * out a structure which becomes available in debugfs for user level tools | |
1092 | * to pick up. | |
1093 | */ | |
1094 | void i915_capture_error_state(struct drm_device *dev) | |
1095 | { | |
53a4c6b2 | 1096 | static bool warned; |
1d762aad BW |
1097 | struct drm_i915_private *dev_priv = dev->dev_private; |
1098 | struct drm_i915_error_state *error; | |
1099 | unsigned long flags; | |
1100 | ||
1101 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); | |
1102 | error = dev_priv->gpu_error.first_error; | |
1103 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1104 | if (error) | |
1105 | return; | |
1106 | ||
1107 | /* Account for pipe specific data like PIPE*STAT */ | |
1108 | error = kzalloc(sizeof(*error), GFP_ATOMIC); | |
1109 | if (!error) { | |
1110 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", | |
1115 | dev->primary->index); | |
53a4c6b2 CW |
1116 | if (!warned) { |
1117 | DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); | |
1118 | DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); | |
1119 | DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); | |
1120 | DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); | |
1121 | warned = true; | |
1122 | } | |
1d762aad BW |
1123 | |
1124 | kref_init(&error->ref); | |
84734a04 | 1125 | |
1d762aad | 1126 | i915_capture_reg_state(dev_priv, error); |
84734a04 MK |
1127 | i915_gem_capture_buffers(dev_priv, error); |
1128 | i915_gem_record_fences(dev, error); | |
1129 | i915_gem_record_rings(dev, error); | |
1130 | ||
1131 | do_gettimeofday(&error->time); | |
1132 | ||
1133 | error->overlay = intel_overlay_capture_error_state(dev); | |
1134 | error->display = intel_display_capture_error_state(dev); | |
1135 | ||
1136 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); | |
1137 | if (dev_priv->gpu_error.first_error == NULL) { | |
1138 | dev_priv->gpu_error.first_error = error; | |
1139 | error = NULL; | |
1140 | } | |
1141 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1142 | ||
1143 | if (error) | |
1144 | i915_error_state_free(&error->ref); | |
1145 | } | |
1146 | ||
1147 | void i915_error_state_get(struct drm_device *dev, | |
1148 | struct i915_error_state_file_priv *error_priv) | |
1149 | { | |
1150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1151 | unsigned long flags; | |
1152 | ||
1153 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); | |
1154 | error_priv->error = dev_priv->gpu_error.first_error; | |
1155 | if (error_priv->error) | |
1156 | kref_get(&error_priv->error->ref); | |
1157 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1158 | ||
1159 | } | |
1160 | ||
1161 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv) | |
1162 | { | |
1163 | if (error_priv->error) | |
1164 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
1165 | } | |
1166 | ||
1167 | void i915_destroy_error_state(struct drm_device *dev) | |
1168 | { | |
1169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1170 | struct drm_i915_error_state *error; | |
1171 | unsigned long flags; | |
1172 | ||
1173 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); | |
1174 | error = dev_priv->gpu_error.first_error; | |
1175 | dev_priv->gpu_error.first_error = NULL; | |
1176 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1177 | ||
1178 | if (error) | |
1179 | kref_put(&error->ref, i915_error_state_free); | |
1180 | } | |
1181 | ||
1182 | const char *i915_cache_level_str(int type) | |
1183 | { | |
1184 | switch (type) { | |
1185 | case I915_CACHE_NONE: return " uncached"; | |
350ec881 CW |
1186 | case I915_CACHE_LLC: return " snooped or LLC"; |
1187 | case I915_CACHE_L3_LLC: return " L3+LLC"; | |
f56383cb | 1188 | case I915_CACHE_WT: return " WT"; |
84734a04 MK |
1189 | default: return ""; |
1190 | } | |
1191 | } | |
1192 | ||
1193 | /* NB: please notice the memset */ | |
1194 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) | |
1195 | { | |
1196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1197 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
1198 | ||
1199 | switch (INTEL_INFO(dev)->gen) { | |
1200 | case 2: | |
1201 | case 3: | |
1202 | instdone[0] = I915_READ(INSTDONE); | |
1203 | break; | |
1204 | case 4: | |
1205 | case 5: | |
1206 | case 6: | |
1207 | instdone[0] = I915_READ(INSTDONE_I965); | |
1208 | instdone[1] = I915_READ(INSTDONE1); | |
1209 | break; | |
1210 | default: | |
1211 | WARN_ONCE(1, "Unsupported platform\n"); | |
1212 | case 7: | |
d0582ed2 | 1213 | case 8: |
84734a04 MK |
1214 | instdone[0] = I915_READ(GEN7_INSTDONE_1); |
1215 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
1216 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
1217 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
1218 | break; | |
1219 | } | |
1220 | } |