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drm/i915: Do not unmap object unless no other VMAs reference it
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
845f74a7 45 case VCS2: return "bsd2";
84734a04
MK		 46 default: return "";
47 }
48}
49
50static const char *pin_flag(int pinned)
51{
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58}
59
60static const char *tiling_flag(int tiling)
61{
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68}
69
70static const char *dirty_flag(int dirty)
71{
72 return dirty ? " dirty" : "";
73}
74
75static const char *purgeable_flag(int purgeable)
76{
77 return purgeable ? " purgeable" : "";
78}
79
80static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81{
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92}
93
94static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96{
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109}
110
111static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113{
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135}
136
137static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139{
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
e29bb4eb
CW		 147 va_list tmp;
148
149 va_copy(tmp, args);
1d2cb9a5
MK		 150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
84734a04
MK		 154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162}
163
164static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166{
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185}
186
187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188#define err_puts(e, s) i915_error_puts(e, s)
189
190static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194{
195 err_printf(m, "%s [%d]:\n", name, count);
196
197 while (count--) {
198 err_printf(m, " %08x %8u %02x %02x %x %x",
199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 208 err_puts(m, err->userptr ? " userptr" : "");
84734a04
MK		 209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(err->cache_level));
212
213 if (err->name)
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
217
218 err_puts(m, "\n");
219 err++;
220 }
221}
222
da661464
MK		 223static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224{
225 switch (a) {
226 case HANGCHECK_IDLE:
227 return "idle";
228 case HANGCHECK_WAIT:
229 return "wait";
230 case HANGCHECK_ACTIVE:
231 return "active";
232 case HANGCHECK_KICK:
233 return "kick";
234 case HANGCHECK_HUNG:
235 return "hung";
236 }
237
238 return "unknown";
239}
240
84734a04
MK		 241static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
242 struct drm_device *dev,
362b8af7 243 struct drm_i915_error_ring *ring)
84734a04 244{
362b8af7 245 if (!ring->valid)
372fbb8e
CW		 246 return;
247
362b8af7
BW		 248 err_printf(m, " HEAD: 0x%08x\n", ring->head);
249 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
250 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
251 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 252 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 253 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
254 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
255 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 256 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 257 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 258 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
259 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 260 }
362b8af7 261 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 262 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
263 lower_32_bits(ring->faddr));
84734a04 264 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 265 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
266 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 267 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 268 ring->semaphore_mboxes[0],
269 ring->semaphore_seqno[0]);
84734a04 270 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 271 ring->semaphore_mboxes[1],
272 ring->semaphore_seqno[1]);
4e5aabfd
BW		 273 if (HAS_VEBOX(dev)) {
274 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 275 ring->semaphore_mboxes[2],
276 ring->semaphore_seqno[2]);
4e5aabfd 277 }
84734a04 278 }
6c7a01ec
BW		 279 if (USES_PPGTT(dev)) {
280 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
281
282 if (INTEL_INFO(dev)->gen >= 8) {
283 int i;
284 for (i = 0; i < 4; i++)
285 err_printf(m, " PDP%d: 0x%016llx\n",
286 i, ring->vm_info.pdp[i]);
287 } else {
288 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
289 ring->vm_info.pp_dir_base);
290 }
291 }
362b8af7
BW		 292 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
293 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
294 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
295 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 296 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 297 hangcheck_action_to_str(ring->hangcheck_action),
298 ring->hangcheck_score);
84734a04
MK		 299}
300
301void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
302{
303 va_list args;
304
305 va_start(args, f);
306 i915_error_vprintf(e, f, args);
307 va_end(args);
308}
309
ab0e7ff9
CW		 310static void print_error_obj(struct drm_i915_error_state_buf *m,
311 struct drm_i915_error_object *obj)
312{
313 int page, offset, elt;
314
315 for (page = offset = 0; page < obj->page_count; page++) {
316 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
317 err_printf(m, "%08x : %08x\n", offset,
318 obj->pages[page][elt]);
319 offset += 4;
320 }
321 }
322}
323
84734a04
MK		 324int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
325 const struct i915_error_state_file_priv *error_priv)
326{
327 struct drm_device *dev = error_priv->dev;
50227e1c 328 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 329 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 330 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 331 int i, j, offset, elt;
332 int max_hangcheck_score;
84734a04
MK		 333
334 if (!error) {
335 err_printf(m, "no error state collected\n");
336 goto out;
337 }
338
cb383002 339 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 340 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
341 error->time.tv_usec);
342 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 343 max_hangcheck_score = 0;
344 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
345 if (error->ring[i].hangcheck_score > max_hangcheck_score)
346 max_hangcheck_score = error->ring[i].hangcheck_score;
347 }
348 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
349 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
350 error->ring[i].pid != -1) {
351 err_printf(m, "Active process (on ring %s): %s [%d]\n",
352 ring_str(i),
353 error->ring[i].comm,
354 error->ring[i].pid);
355 }
356 }
48b031e3 357 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 358 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 359 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 360 err_printf(m, "EIR: 0x%08x\n", error->eir);
361 err_printf(m, "IER: 0x%08x\n", error->ier);
362 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
363 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
364 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
365 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 366 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 367
368 for (i = 0; i < dev_priv->num_fence_regs; i++)
369 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
370
371 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
372 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
373 error->extra_instdone[i]);
374
375 if (INTEL_INFO(dev)->gen >= 6) {
376 err_printf(m, "ERROR: 0x%08x\n", error->error);
377 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
378 }
379
380 if (INTEL_INFO(dev)->gen == 7)
381 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
382
362b8af7
BW		 383 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
384 err_printf(m, "%s command stream:\n", ring_str(i));
385 i915_ring_error_state(m, dev, &error->ring[i]);
386 }
84734a04
MK		 387
388 if (error->active_bo)
389 print_error_buffers(m, "Active",
95f5301d
BW		 390 error->active_bo[0],
391 error->active_bo_count[0]);
84734a04
MK		 392
393 if (error->pinned_bo)
394 print_error_buffers(m, "Pinned",
95f5301d
BW		 395 error->pinned_bo[0],
396 error->pinned_bo_count[0]);
84734a04
MK		 397
398 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
ab0e7ff9
CW		 399 obj = error->ring[i].batchbuffer;
400 if (obj) {
401 err_puts(m, dev_priv->ring[i].name);
402 if (error->ring[i].pid != -1)
403 err_printf(m, " (submitted by %s [%d])",
404 error->ring[i].comm,
405 error->ring[i].pid);
406 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 407 obj->gtt_offset);
ab0e7ff9
CW		 408 print_error_obj(m, obj);
409 }
410
411 obj = error->ring[i].wa_batchbuffer;
412 if (obj) {
413 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
414 dev_priv->ring[i].name, obj->gtt_offset);
415 print_error_obj(m, obj);
84734a04
MK		 416 }
417
418 if (error->ring[i].num_requests) {
419 err_printf(m, "%s --- %d requests\n",
420 dev_priv->ring[i].name,
421 error->ring[i].num_requests);
422 for (j = 0; j < error->ring[i].num_requests; j++) {
423 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
424 error->ring[i].requests[j].seqno,
425 error->ring[i].requests[j].jiffies,
426 error->ring[i].requests[j].tail);
427 }
428 }
429
430 if ((obj = error->ring[i].ringbuffer)) {
431 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
432 dev_priv->ring[i].name,
433 obj->gtt_offset);
ab0e7ff9 434 print_error_obj(m, obj);
84734a04
MK		 435 }
436
362b8af7 437 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 438 err_printf(m, "%s --- HW Status = 0x%08x\n",
439 dev_priv->ring[i].name,
440 obj->gtt_offset);
441 offset = 0;
442 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
443 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
444 offset,
445 obj->pages[0][elt],
446 obj->pages[0][elt+1],
447 obj->pages[0][elt+2],
448 obj->pages[0][elt+3]);
449 offset += 16;
450 }
451 }
452
372fbb8e 453 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 454 err_printf(m, "%s --- HW Context = 0x%08x\n",
455 dev_priv->ring[i].name,
456 obj->gtt_offset);
17d36749 457 print_error_obj(m, obj);
84734a04
MK		 458 }
459 }
460
0ca36d78
BW		 461 if ((obj = error->semaphore_obj)) {
462 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
463 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
464 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
465 elt * 4,
466 obj->pages[0][elt],
467 obj->pages[0][elt+1],
468 obj->pages[0][elt+2],
469 obj->pages[0][elt+3]);
470 }
471 }
472
84734a04
MK		 473 if (error->overlay)
474 intel_overlay_print_error_state(m, error->overlay);
475
476 if (error->display)
477 intel_display_print_error_state(m, dev, error->display);
478
479out:
480 if (m->bytes == 0 && m->err)
481 return m->err;
482
483 return 0;
484}
485
486int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
487 size_t count, loff_t pos)
488{
489 memset(ebuf, 0, sizeof(*ebuf));
490
491 /* We need to have enough room to store any i915_error_state printf
492 * so that we can move it to start position.
493 */
494 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
495 ebuf->buf = kmalloc(ebuf->size,
496 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
497
498 if (ebuf->buf == NULL) {
499 ebuf->size = PAGE_SIZE;
500 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
501 }
502
503 if (ebuf->buf == NULL) {
504 ebuf->size = 128;
505 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
506 }
507
508 if (ebuf->buf == NULL)
509 return -ENOMEM;
510
511 ebuf->start = pos;
512
513 return 0;
514}
515
516static void i915_error_object_free(struct drm_i915_error_object *obj)
517{
518 int page;
519
520 if (obj == NULL)
521 return;
522
523 for (page = 0; page < obj->page_count; page++)
524 kfree(obj->pages[page]);
525
526 kfree(obj);
527}
528
529static void i915_error_state_free(struct kref *error_ref)
530{
531 struct drm_i915_error_state *error = container_of(error_ref,
532 typeof(*error), ref);
533 int i;
534
535 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
536 i915_error_object_free(error->ring[i].batchbuffer);
537 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 538 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 539 i915_error_object_free(error->ring[i].ctx);
540 kfree(error->ring[i].requests);
541 }
542
0ca36d78 543 i915_error_object_free(error->semaphore_obj);
84734a04
MK		 544 kfree(error->active_bo);
545 kfree(error->overlay);
546 kfree(error->display);
547 kfree(error);
548}
549
550static struct drm_i915_error_object *
551i915_error_object_create_sized(struct drm_i915_private *dev_priv,
552 struct drm_i915_gem_object *src,
a7b91078 553 struct i915_address_space *vm,
84734a04
MK		 554 const int num_pages)
555{
556 struct drm_i915_error_object *dst;
557 int i;
558 u32 reloc_offset;
559
560 if (src == NULL || src->pages == NULL)
561 return NULL;
562
563 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
564 if (dst == NULL)
565 return NULL;
566
a7b91078 567 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
84734a04
MK		 568 for (i = 0; i < num_pages; i++) {
569 unsigned long flags;
570 void *d;
571
572 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
573 if (d == NULL)
574 goto unwind;
575
576 local_irq_save(flags);
8b6124a6
CW		 577 if (src->cache_level == I915_CACHE_NONE &&
578 reloc_offset < dev_priv->gtt.mappable_end &&
496bfcb9
BW		 579 src->has_global_gtt_mapping &&
580 i915_is_ggtt(vm)) {
84734a04
MK		 581 void __iomem *s;
582
583 /* Simply ignore tiling or any overlapping fence.
584 * It's part of the error state, and this hopefully
585 * captures what the GPU read.
586 */
587
588 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
589 reloc_offset);
590 memcpy_fromio(d, s, PAGE_SIZE);
591 io_mapping_unmap_atomic(s);
592 } else if (src->stolen) {
593 unsigned long offset;
594
595 offset = dev_priv->mm.stolen_base;
596 offset += src->stolen->start;
597 offset += i << PAGE_SHIFT;
598
599 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
600 } else {
601 struct page *page;
602 void *s;
603
604 page = i915_gem_object_get_page(src, i);
605
606 drm_clflush_pages(&page, 1);
607
608 s = kmap_atomic(page);
609 memcpy(d, s, PAGE_SIZE);
610 kunmap_atomic(s);
611
612 drm_clflush_pages(&page, 1);
613 }
614 local_irq_restore(flags);
615
616 dst->pages[i] = d;
617
618 reloc_offset += PAGE_SIZE;
619 }
620 dst->page_count = num_pages;
621
622 return dst;
623
624unwind:
625 while (i--)
626 kfree(dst->pages[i]);
627 kfree(dst);
628 return NULL;
629}
a7b91078
BW		 630#define i915_error_object_create(dev_priv, src, vm) \
631 i915_error_object_create_sized((dev_priv), (src), (vm), \
632 (src)->base.size>>PAGE_SHIFT)
633
634#define i915_error_ggtt_object_create(dev_priv, src) \
635 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 636 (src)->base.size>>PAGE_SHIFT)
637
638static void capture_bo(struct drm_i915_error_buffer *err,
639 struct drm_i915_gem_object *obj)
640{
641 err->size = obj->base.size;
642 err->name = obj->base.name;
643 err->rseqno = obj->last_read_seqno;
644 err->wseqno = obj->last_write_seqno;
645 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
646 err->read_domains = obj->base.read_domains;
647 err->write_domain = obj->base.write_domain;
648 err->fence_reg = obj->fence_reg;
649 err->pinned = 0;
d7f46fc4 650 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 651 err->pinned = 1;
652 if (obj->user_pin_count > 0)
653 err->pinned = -1;
654 err->tiling = obj->tiling_mode;
655 err->dirty = obj->dirty;
656 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 657 err->userptr = obj->userptr.mm != NULL;
84734a04
MK		 658 err->ring = obj->ring ? obj->ring->id : -1;
659 err->cache_level = obj->cache_level;
660}
661
662static u32 capture_active_bo(struct drm_i915_error_buffer *err,
663 int count, struct list_head *head)
664{
ca191b13 665 struct i915_vma *vma;
84734a04
MK		 666 int i = 0;
667
ca191b13
BW		 668 list_for_each_entry(vma, head, mm_list) {
669 capture_bo(err++, vma->obj);
84734a04
MK		 670 if (++i == count)
671 break;
672 }
673
674 return i;
675}
676
677static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
678 int count, struct list_head *head)
679{
680 struct drm_i915_gem_object *obj;
681 int i = 0;
682
683 list_for_each_entry(obj, head, global_list) {
d7f46fc4 684 if (!i915_gem_obj_is_pinned(obj))
84734a04
MK		 685 continue;
686
687 capture_bo(err++, obj);
688 if (++i == count)
689 break;
690 }
691
692 return i;
693}
694
011cf577
BW		 695/* Generate a semi-unique error code. The code is not meant to have meaning, The
696 * code's only purpose is to try to prevent false duplicated bug reports by
697 * grossly estimating a GPU error state.
698 *
699 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
700 * the hang if we could strip the GTT offset information from it.
701 *
702 * It's only a small step better than a random number in its current form.
703 */
704static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 705 struct drm_i915_error_state *error,
706 int *ring_id)
011cf577
BW		 707{
708 uint32_t error_code = 0;
709 int i;
710
711 /* IPEHR would be an ideal way to detect errors, as it's the gross
712 * measure of "the command that hung." However, has some very common
713 * synchronization commands which almost always appear in the case
714 * strictly a client bug. Use instdone to differentiate those some.
715 */
cb383002
MK		 716 for (i = 0; i < I915_NUM_RINGS; i++) {
717 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
718 if (ring_id)
719 *ring_id = i;
720
011cf577 721 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 722 }
723 }
011cf577
BW		 724
725 return error_code;
726}
727
84734a04
MK		 728static void i915_gem_record_fences(struct drm_device *dev,
729 struct drm_i915_error_state *error)
730{
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 int i;
733
734 /* Fences */
735 switch (INTEL_INFO(dev)->gen) {
5ab31333 736 case 8:
84734a04
MK		 737 case 7:
738 case 6:
739 for (i = 0; i < dev_priv->num_fence_regs; i++)
740 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
741 break;
742 case 5:
743 case 4:
744 for (i = 0; i < 16; i++)
745 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
746 break;
747 case 3:
748 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
749 for (i = 0; i < 8; i++)
750 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
751 case 2:
752 for (i = 0; i < 8; i++)
753 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
754 break;
755
756 default:
757 BUG();
758 }
759}
760
87f85ebc 761
0ca36d78
BW		 762static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
763 struct drm_i915_error_state *error,
764 struct intel_engine_cs *ring,
765 struct drm_i915_error_ring *ering)
766{
767 struct intel_engine_cs *useless;
768 int i;
769
770 if (!i915_semaphore_is_enabled(dev_priv->dev))
771 return;
772
773 if (!error->semaphore_obj)
774 error->semaphore_obj =
775 i915_error_object_create(dev_priv,
776 dev_priv->semaphore_obj,
777 &dev_priv->gtt.base);
778
779 for_each_ring(useless, dev_priv, i) {
780 u16 signal_offset =
781 (GEN8_SIGNAL_OFFSET(ring, i) & PAGE_MASK) / 4;
782 u32 *tmp = error->semaphore_obj->pages[0];
783
784 ering->semaphore_mboxes[i] = tmp[signal_offset];
785 ering->semaphore_seqno[i] = ring->semaphore.sync_seqno[i];
786 }
787}
788
87f85ebc
BW		 789static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
790 struct intel_engine_cs *ring,
791 struct drm_i915_error_ring *ering)
792{
793 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
794 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
795 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
796 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
797
798 if (HAS_VEBOX(dev_priv->dev)) {
799 ering->semaphore_mboxes[2] =
800 I915_READ(RING_SYNC_2(ring->mmio_base));
801 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
802 }
803}
804
84734a04 805static void i915_record_ring_state(struct drm_device *dev,
0ca36d78 806 struct drm_i915_error_state *error,
a4872ba6 807 struct intel_engine_cs *ring,
362b8af7 808 struct drm_i915_error_ring *ering)
84734a04
MK		 809{
810 struct drm_i915_private *dev_priv = dev->dev_private;
811
812 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 813 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
814 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
0ca36d78
BW		 815 if (INTEL_INFO(dev)->gen >= 8)
816 gen8_record_semaphore_state(dev_priv, error, ring, ering);
817 else
818 gen6_record_semaphore_state(dev_priv, ring, ering);
4e5aabfd
BW		 819 }
820
84734a04 821 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 822 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
823 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
824 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
825 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
826 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
827 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 828 if (INTEL_INFO(dev)->gen >= 8) {
829 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 830 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 831 }
362b8af7 832 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 833 } else {
362b8af7
BW		 834 ering->faddr = I915_READ(DMA_FADD_I8XX);
835 ering->ipeir = I915_READ(IPEIR);
836 ering->ipehr = I915_READ(IPEHR);
837 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 838 }
839
362b8af7
BW		 840 ering->waiting = waitqueue_active(&ring->irq_queue);
841 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
842 ering->seqno = ring->get_seqno(ring, false);
843 ering->acthd = intel_ring_get_active_head(ring);
844 ering->head = I915_READ_HEAD(ring);
845 ering->tail = I915_READ_TAIL(ring);
846 ering->ctl = I915_READ_CTL(ring);
84734a04 847
f3ce3821
CW		 848 if (I915_NEED_GFX_HWS(dev)) {
849 int mmio;
850
851 if (IS_GEN7(dev)) {
852 switch (ring->id) {
853 default:
854 case RCS:
855 mmio = RENDER_HWS_PGA_GEN7;
856 break;
857 case BCS:
858 mmio = BLT_HWS_PGA_GEN7;
859 break;
860 case VCS:
861 mmio = BSD_HWS_PGA_GEN7;
862 break;
863 case VECS:
864 mmio = VEBOX_HWS_PGA_GEN7;
865 break;
866 }
867 } else if (IS_GEN6(ring->dev)) {
868 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
869 } else {
870 /* XXX: gen8 returns to sanity */
871 mmio = RING_HWS_PGA(ring->mmio_base);
872 }
873
362b8af7 874 ering->hws = I915_READ(mmio);
f3ce3821
CW		 875 }
876
ee1b1e5e
OM		 877 ering->cpu_ring_head = ring->buffer->head;
878 ering->cpu_ring_tail = ring->buffer->tail;
da661464 879
362b8af7
BW		 880 ering->hangcheck_score = ring->hangcheck.score;
881 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 882
883 if (USES_PPGTT(dev)) {
884 int i;
885
886 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
887
888 switch (INTEL_INFO(dev)->gen) {
889 case 8:
890 for (i = 0; i < 4; i++) {
891 ering->vm_info.pdp[i] =
892 I915_READ(GEN8_RING_PDP_UDW(ring, i));
893 ering->vm_info.pdp[i] <<= 32;
894 ering->vm_info.pdp[i] |=
895 I915_READ(GEN8_RING_PDP_LDW(ring, i));
896 }
897 break;
898 case 7:
ae89f44d
BW		 899 ering->vm_info.pp_dir_base =
900 I915_READ(RING_PP_DIR_BASE(ring));
6c7a01ec
BW		 901 break;
902 case 6:
ae89f44d
BW		 903 ering->vm_info.pp_dir_base =
904 I915_READ(RING_PP_DIR_BASE_READ(ring));
6c7a01ec
BW		 905 break;
906 }
907 }
84734a04
MK		 908}
909
910
a4872ba6 911static void i915_gem_record_active_context(struct intel_engine_cs *ring,
84734a04
MK		 912 struct drm_i915_error_state *error,
913 struct drm_i915_error_ring *ering)
914{
915 struct drm_i915_private *dev_priv = ring->dev->dev_private;
916 struct drm_i915_gem_object *obj;
917
918 /* Currently render ring is the only HW context user */
919 if (ring->id != RCS || !error->ccid)
920 return;
921
922 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
36362ad3
BW		 923 if (!i915_gem_obj_ggtt_bound(obj))
924 continue;
925
84734a04 926 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
17d36749 927 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 928 break;
929 }
930 }
931}
932
933static void i915_gem_record_rings(struct drm_device *dev,
934 struct drm_i915_error_state *error)
935{
936 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 937 struct drm_i915_gem_request *request;
938 int i, count;
939
372fbb8e 940 for (i = 0; i < I915_NUM_RINGS; i++) {
a4872ba6 941 struct intel_engine_cs *ring = &dev_priv->ring[i];
372fbb8e 942
eee73b46
CW		 943 error->ring[i].pid = -1;
944
372fbb8e
CW		 945 if (ring->dev == NULL)
946 continue;
947
948 error->ring[i].valid = true;
949
0ca36d78 950 i915_record_ring_state(dev, error, ring, &error->ring[i]);
84734a04 951
ab0e7ff9
CW		 952 request = i915_gem_find_active_request(ring);
953 if (request) {
954 /* We need to copy these to an anonymous buffer
955 * as the simplest method to avoid being overwritten
956 * by userspace.
957 */
958 error->ring[i].batchbuffer =
959 i915_error_object_create(dev_priv,
960 request->batch_obj,
961 request->ctx ?
962 request->ctx->vm :
963 &dev_priv->gtt.base);
964
965 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
966 ring->scratch.obj)
967 error->ring[i].wa_batchbuffer =
968 i915_error_ggtt_object_create(dev_priv,
969 ring->scratch.obj);
970
971 if (request->file_priv) {
972 struct task_struct *task;
973
974 rcu_read_lock();
975 task = pid_task(request->file_priv->file->pid,
976 PIDTYPE_PID);
977 if (task) {
978 strcpy(error->ring[i].comm, task->comm);
979 error->ring[i].pid = task->pid;
980 }
981 rcu_read_unlock();
982 }
983 }
84734a04
MK		 984
985 error->ring[i].ringbuffer =
ee1b1e5e 986 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj);
84734a04 987
f3ce3821 988 if (ring->status_page.obj)
362b8af7 989 error->ring[i].hws_page =
f3ce3821 990 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 991
992 i915_gem_record_active_context(ring, error, &error->ring[i]);
993
994 count = 0;
995 list_for_each_entry(request, &ring->request_list, list)
996 count++;
997
998 error->ring[i].num_requests = count;
999 error->ring[i].requests =
a1e22653 1000 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 1001 GFP_ATOMIC);
1002 if (error->ring[i].requests == NULL) {
1003 error->ring[i].num_requests = 0;
1004 continue;
1005 }
1006
1007 count = 0;
1008 list_for_each_entry(request, &ring->request_list, list) {
1009 struct drm_i915_error_request *erq;
1010
1011 erq = &error->ring[i].requests[count++];
1012 erq->seqno = request->seqno;
1013 erq->jiffies = request->emitted_jiffies;
1014 erq->tail = request->tail;
1015 }
1016 }
1017}
1018
95f5301d
BW		 1019/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1020 * VM.
1021 */
1022static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1023 struct drm_i915_error_state *error,
1024 struct i915_address_space *vm,
1025 const int ndx)
84734a04 1026{
95f5301d 1027 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 1028 struct drm_i915_gem_object *obj;
95f5301d 1029 struct i915_vma *vma;
84734a04
MK		 1030 int i;
1031
1032 i = 0;
ca191b13 1033 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 1034 i++;
95f5301d 1035 error->active_bo_count[ndx] = i;
84734a04 1036 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
d7f46fc4 1037 if (i915_gem_obj_is_pinned(obj))
84734a04 1038 i++;
95f5301d 1039 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 1040
1041 if (i) {
a1e22653 1042 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 1043 if (active_bo)
1044 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1045 }
1046
95f5301d
BW		 1047 if (active_bo)
1048 error->active_bo_count[ndx] =
1049 capture_active_bo(active_bo,
1050 error->active_bo_count[ndx],
5cef07e1 1051 &vm->active_list);
84734a04 1052
95f5301d
BW		 1053 if (pinned_bo)
1054 error->pinned_bo_count[ndx] =
1055 capture_pinned_bo(pinned_bo,
1056 error->pinned_bo_count[ndx],
84734a04 1057 &dev_priv->mm.bound_list);
95f5301d
BW		 1058 error->active_bo[ndx] = active_bo;
1059 error->pinned_bo[ndx] = pinned_bo;
1060}
1061
1062static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1063 struct drm_i915_error_state *error)
1064{
1065 struct i915_address_space *vm;
1066 int cnt = 0, i = 0;
1067
1068 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1069 cnt++;
1070
95f5301d
BW		 1071 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1072 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1073 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1074 GFP_ATOMIC);
1075 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1076 GFP_ATOMIC);
1077
1078 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1079 i915_gem_capture_vm(dev_priv, error, vm, i++);
84734a04
MK		 1080}
1081
1d762aad
BW		 1082/* Capture all registers which don't fit into another category. */
1083static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1084 struct drm_i915_error_state *error)
84734a04 1085{
1d762aad 1086 struct drm_device *dev = dev_priv->dev;
84734a04 1087
654c90c6
BW		 1088 /* General organization
1089 * 1. Registers specific to a single generation
1090 * 2. Registers which belong to multiple generations
1091 * 3. Feature specific registers.
1092 * 4. Everything else
1093 * Please try to follow the order.
1094 */
84734a04 1095
654c90c6
BW		 1096 /* 1: Registers specific to a single generation */
1097 if (IS_VALLEYVIEW(dev)) {
84734a04 1098 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
654c90c6
BW		 1099 error->forcewake = I915_READ(FORCEWAKE_VLV);
1100 }
84734a04 1101
654c90c6
BW		 1102 if (IS_GEN7(dev))
1103 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1104
91ec5d11 1105 if (IS_GEN6(dev)) {
84734a04 1106 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1107 error->gab_ctl = I915_READ(GAB_CTL);
1108 error->gfx_mode = I915_READ(GFX_MODE);
1109 }
84734a04 1110
654c90c6
BW		 1111 /* 2: Registers which belong to multiple generations */
1112 if (INTEL_INFO(dev)->gen >= 7)
1113 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1114
1115 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1116 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1117 error->error = I915_READ(ERROR_GEN6);
1118 error->done_reg = I915_READ(DONE_REG);
1119 }
1120
654c90c6 1121 /* 3: Feature specific registers */
91ec5d11
BW		 1122 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1123 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1124 error->gac_eco = I915_READ(GAC_ECO_BITS);
1125 }
1126
1127 /* 4: Everything else */
654c90c6
BW		 1128 if (HAS_HW_CONTEXTS(dev))
1129 error->ccid = I915_READ(CCID);
1130
1131 if (HAS_PCH_SPLIT(dev))
1132 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1133 else {
51660e0e
ID		 1134 if (IS_GEN2(dev))
1135 error->ier = I915_READ16(IER);
1136 else
1137 error->ier = I915_READ(IER);
654c90c6
BW		 1138 }
1139
1140 /* 4: Everything else */
1141 error->eir = I915_READ(EIR);
1142 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1143
1144 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1145}
1146
cb383002 1147static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1148 struct drm_i915_error_state *error,
1149 bool wedged,
1150 const char *error_msg)
cb383002
MK		 1151{
1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 u32 ecode;
58174462 1154 int ring_id = -1, len;
cb383002
MK		 1155
1156 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1157
58174462
MK		 1158 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1159 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1160
1161 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1162 len += scnprintf(error->error_msg + len,
1163 sizeof(error->error_msg) - len,
1164 ", in %s [%d]",
1165 error->ring[ring_id].comm,
1166 error->ring[ring_id].pid);
1167
1168 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1169 ", reason: %s, action: %s",
1170 error_msg,
1171 wedged ? "reset" : "continue");
cb383002
MK		 1172}
1173
48b031e3
MK		 1174static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1175 struct drm_i915_error_state *error)
1176{
1177 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1178 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1179}
1180
1d762aad
BW		 1181/**
1182 * i915_capture_error_state - capture an error record for later analysis
1183 * @dev: drm device
1184 *
1185 * Should be called when an error is detected (either a hang or an error
1186 * interrupt) to capture error state from the time of the error. Fills
1187 * out a structure which becomes available in debugfs for user level tools
1188 * to pick up.
1189 */
58174462
MK		 1190void i915_capture_error_state(struct drm_device *dev, bool wedged,
1191 const char *error_msg)
1d762aad 1192{
53a4c6b2 1193 static bool warned;
1d762aad
BW		 1194 struct drm_i915_private *dev_priv = dev->dev_private;
1195 struct drm_i915_error_state *error;
1196 unsigned long flags;
1d762aad
BW		 1197
1198 /* Account for pipe specific data like PIPE*STAT */
1199 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1200 if (!error) {
1201 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1202 return;
1203 }
1204
011cf577
BW		 1205 kref_init(&error->ref);
1206
48b031e3 1207 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1208 i915_capture_reg_state(dev_priv, error);
1209 i915_gem_capture_buffers(dev_priv, error);
1210 i915_gem_record_fences(dev, error);
1211 i915_gem_record_rings(dev, error);
1d762aad 1212
84734a04
MK		 1213 do_gettimeofday(&error->time);
1214
1215 error->overlay = intel_overlay_capture_error_state(dev);
1216 error->display = intel_display_capture_error_state(dev);
1217
58174462 1218 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1219 DRM_INFO("%s\n", error->error_msg);
1220
84734a04
MK		 1221 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1222 if (dev_priv->gpu_error.first_error == NULL) {
1223 dev_priv->gpu_error.first_error = error;
1224 error = NULL;
1225 }
1226 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1227
cb383002 1228 if (error) {
84734a04 1229 i915_error_state_free(&error->ref);
cb383002
MK		 1230 return;
1231 }
1232
1233 if (!warned) {
1234 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1235 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1236 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1237 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1238 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1239 warned = true;
1240 }
84734a04
MK		 1241}
1242
1243void i915_error_state_get(struct drm_device *dev,
1244 struct i915_error_state_file_priv *error_priv)
1245{
1246 struct drm_i915_private *dev_priv = dev->dev_private;
1247 unsigned long flags;
1248
1249 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1250 error_priv->error = dev_priv->gpu_error.first_error;
1251 if (error_priv->error)
1252 kref_get(&error_priv->error->ref);
1253 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1254
1255}
1256
1257void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1258{
1259 if (error_priv->error)
1260 kref_put(&error_priv->error->ref, i915_error_state_free);
1261}
1262
1263void i915_destroy_error_state(struct drm_device *dev)
1264{
1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 struct drm_i915_error_state *error;
1267 unsigned long flags;
1268
1269 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1270 error = dev_priv->gpu_error.first_error;
1271 dev_priv->gpu_error.first_error = NULL;
1272 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1273
1274 if (error)
1275 kref_put(&error->ref, i915_error_state_free);
1276}
1277
1278const char *i915_cache_level_str(int type)
1279{
1280 switch (type) {
1281 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1282 case I915_CACHE_LLC: return " snooped or LLC";
1283 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1284 case I915_CACHE_WT: return " WT";
84734a04
MK		 1285 default: return "";
1286 }
1287}
1288
1289/* NB: please notice the memset */
1290void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1291{
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1294
1295 switch (INTEL_INFO(dev)->gen) {
1296 case 2:
1297 case 3:
1298 instdone[0] = I915_READ(INSTDONE);
1299 break;
1300 case 4:
1301 case 5:
1302 case 6:
1303 instdone[0] = I915_READ(INSTDONE_I965);
1304 instdone[1] = I915_READ(INSTDONE1);
1305 break;
1306 default:
1307 WARN_ONCE(1, "Unsupported platform\n");
1308 case 7:
d0582ed2 1309 case 8:
84734a04
MK		 1310 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1311 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1312 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1313 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1314 break;
1315 }
1316}
Linux kernel - Deliverables
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