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drm/i915: Create a global list of vms
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
45 default: return "";
46 }
47}
48
49static const char *pin_flag(int pinned)
50{
51 if (pinned > 0)
52 return " P";
53 else if (pinned < 0)
54 return " p";
55 else
56 return "";
57}
58
59static const char *tiling_flag(int tiling)
60{
61 switch (tiling) {
62 default:
63 case I915_TILING_NONE: return "";
64 case I915_TILING_X: return " X";
65 case I915_TILING_Y: return " Y";
66 }
67}
68
69static const char *dirty_flag(int dirty)
70{
71 return dirty ? " dirty" : "";
72}
73
74static const char *purgeable_flag(int purgeable)
75{
76 return purgeable ? " purgeable" : "";
77}
78
79static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
80{
81
82 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
83 e->err = -ENOSPC;
84 return false;
85 }
86
87 if (e->bytes == e->size - 1 || e->err)
88 return false;
89
90 return true;
91}
92
93static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
94 unsigned len)
95{
96 if (e->pos + len <= e->start) {
97 e->pos += len;
98 return false;
99 }
100
101 /* First vsnprintf needs to fit in its entirety for memmove */
102 if (len >= e->size) {
103 e->err = -EIO;
104 return false;
105 }
106
107 return true;
108}
109
110static void __i915_error_advance(struct drm_i915_error_state_buf *e,
111 unsigned len)
112{
113 /* If this is first printf in this window, adjust it so that
114 * start position matches start of the buffer
115 */
116
117 if (e->pos < e->start) {
118 const size_t off = e->start - e->pos;
119
120 /* Should not happen but be paranoid */
121 if (off > len || e->bytes) {
122 e->err = -EIO;
123 return;
124 }
125
126 memmove(e->buf, e->buf + off, len - off);
127 e->bytes = len - off;
128 e->pos = e->start;
129 return;
130 }
131
132 e->bytes += len;
133 e->pos += len;
134}
135
136static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
137 const char *f, va_list args)
138{
139 unsigned len;
140
141 if (!__i915_error_ok(e))
142 return;
143
144 /* Seek the first printf which is hits start position */
145 if (e->pos < e->start) {
146 len = vsnprintf(NULL, 0, f, args);
147 if (!__i915_error_seek(e, len))
148 return;
149 }
150
151 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
152 if (len >= e->size - e->bytes)
153 len = e->size - e->bytes - 1;
154
155 __i915_error_advance(e, len);
156}
157
158static void i915_error_puts(struct drm_i915_error_state_buf *e,
159 const char *str)
160{
161 unsigned len;
162
163 if (!__i915_error_ok(e))
164 return;
165
166 len = strlen(str);
167
168 /* Seek the first printf which is hits start position */
169 if (e->pos < e->start) {
170 if (!__i915_error_seek(e, len))
171 return;
172 }
173
174 if (len >= e->size - e->bytes)
175 len = e->size - e->bytes - 1;
176 memcpy(e->buf + e->bytes, str, len);
177
178 __i915_error_advance(e, len);
179}
180
181#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
182#define err_puts(e, s) i915_error_puts(e, s)
183
184static void print_error_buffers(struct drm_i915_error_state_buf *m,
185 const char *name,
186 struct drm_i915_error_buffer *err,
187 int count)
188{
189 err_printf(m, "%s [%d]:\n", name, count);
190
191 while (count--) {
192 err_printf(m, " %08x %8u %02x %02x %x %x",
193 err->gtt_offset,
194 err->size,
195 err->read_domains,
196 err->write_domain,
197 err->rseqno, err->wseqno);
198 err_puts(m, pin_flag(err->pinned));
199 err_puts(m, tiling_flag(err->tiling));
200 err_puts(m, dirty_flag(err->dirty));
201 err_puts(m, purgeable_flag(err->purgeable));
202 err_puts(m, err->ring != -1 ? " " : "");
203 err_puts(m, ring_str(err->ring));
204 err_puts(m, i915_cache_level_str(err->cache_level));
205
206 if (err->name)
207 err_printf(m, " (name: %d)", err->name);
208 if (err->fence_reg != I915_FENCE_REG_NONE)
209 err_printf(m, " (fence: %d)", err->fence_reg);
210
211 err_puts(m, "\n");
212 err++;
213 }
214}
215
216static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
217 struct drm_device *dev,
218 struct drm_i915_error_state *error,
219 unsigned ring)
220{
221 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
222 err_printf(m, "%s command stream:\n", ring_str(ring));
223 err_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
224 err_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
225 err_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
226 err_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
227 err_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
228 err_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
229 err_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
230 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
231 err_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
232
233 if (INTEL_INFO(dev)->gen >= 4)
234 err_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
235 err_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
236 err_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
237 if (INTEL_INFO(dev)->gen >= 6) {
238 err_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
239 err_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
240 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
241 error->semaphore_mboxes[ring][0],
242 error->semaphore_seqno[ring][0]);
243 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
244 error->semaphore_mboxes[ring][1],
245 error->semaphore_seqno[ring][1]);
246 }
247 err_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
248 err_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
249 err_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
250 err_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
251}
252
253void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
254{
255 va_list args;
256
257 va_start(args, f);
258 i915_error_vprintf(e, f, args);
259 va_end(args);
260}
261
262int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
263 const struct i915_error_state_file_priv *error_priv)
264{
265 struct drm_device *dev = error_priv->dev;
266 drm_i915_private_t *dev_priv = dev->dev_private;
267 struct drm_i915_error_state *error = error_priv->error;
268 struct intel_ring_buffer *ring;
269 int i, j, page, offset, elt;
270
271 if (!error) {
272 err_printf(m, "no error state collected\n");
273 goto out;
274 }
275
276 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
277 error->time.tv_usec);
278 err_printf(m, "Kernel: " UTS_RELEASE "\n");
279 err_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
280 err_printf(m, "EIR: 0x%08x\n", error->eir);
281 err_printf(m, "IER: 0x%08x\n", error->ier);
282 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
283 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
284 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
285 err_printf(m, "CCID: 0x%08x\n", error->ccid);
286
287 for (i = 0; i < dev_priv->num_fence_regs; i++)
288 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
289
290 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
291 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
292 error->extra_instdone[i]);
293
294 if (INTEL_INFO(dev)->gen >= 6) {
295 err_printf(m, "ERROR: 0x%08x\n", error->error);
296 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
297 }
298
299 if (INTEL_INFO(dev)->gen == 7)
300 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
301
302 for_each_ring(ring, dev_priv, i)
303 i915_ring_error_state(m, dev, error, i);
304
305 if (error->active_bo)
306 print_error_buffers(m, "Active",
307 error->active_bo,
308 error->active_bo_count);
309
310 if (error->pinned_bo)
311 print_error_buffers(m, "Pinned",
312 error->pinned_bo,
313 error->pinned_bo_count);
314
315 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
316 struct drm_i915_error_object *obj;
317
318 if ((obj = error->ring[i].batchbuffer)) {
319 err_printf(m, "%s --- gtt_offset = 0x%08x\n",
320 dev_priv->ring[i].name,
321 obj->gtt_offset);
322 offset = 0;
323 for (page = 0; page < obj->page_count; page++) {
324 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
325 err_printf(m, "%08x : %08x\n", offset,
326 obj->pages[page][elt]);
327 offset += 4;
328 }
329 }
330 }
331
332 if (error->ring[i].num_requests) {
333 err_printf(m, "%s --- %d requests\n",
334 dev_priv->ring[i].name,
335 error->ring[i].num_requests);
336 for (j = 0; j < error->ring[i].num_requests; j++) {
337 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
338 error->ring[i].requests[j].seqno,
339 error->ring[i].requests[j].jiffies,
340 error->ring[i].requests[j].tail);
341 }
342 }
343
344 if ((obj = error->ring[i].ringbuffer)) {
345 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
346 dev_priv->ring[i].name,
347 obj->gtt_offset);
348 offset = 0;
349 for (page = 0; page < obj->page_count; page++) {
350 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
351 err_printf(m, "%08x : %08x\n",
352 offset,
353 obj->pages[page][elt]);
354 offset += 4;
355 }
356 }
357 }
358
359 obj = error->ring[i].ctx;
360 if (obj) {
361 err_printf(m, "%s --- HW Context = 0x%08x\n",
362 dev_priv->ring[i].name,
363 obj->gtt_offset);
364 offset = 0;
365 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
366 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
367 offset,
368 obj->pages[0][elt],
369 obj->pages[0][elt+1],
370 obj->pages[0][elt+2],
371 obj->pages[0][elt+3]);
372 offset += 16;
373 }
374 }
375 }
376
377 if (error->overlay)
378 intel_overlay_print_error_state(m, error->overlay);
379
380 if (error->display)
381 intel_display_print_error_state(m, dev, error->display);
382
383out:
384 if (m->bytes == 0 && m->err)
385 return m->err;
386
387 return 0;
388}
389
390int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
391 size_t count, loff_t pos)
392{
393 memset(ebuf, 0, sizeof(*ebuf));
394
395 /* We need to have enough room to store any i915_error_state printf
396 * so that we can move it to start position.
397 */
398 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
399 ebuf->buf = kmalloc(ebuf->size,
400 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
401
402 if (ebuf->buf == NULL) {
403 ebuf->size = PAGE_SIZE;
404 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
405 }
406
407 if (ebuf->buf == NULL) {
408 ebuf->size = 128;
409 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
410 }
411
412 if (ebuf->buf == NULL)
413 return -ENOMEM;
414
415 ebuf->start = pos;
416
417 return 0;
418}
419
420static void i915_error_object_free(struct drm_i915_error_object *obj)
421{
422 int page;
423
424 if (obj == NULL)
425 return;
426
427 for (page = 0; page < obj->page_count; page++)
428 kfree(obj->pages[page]);
429
430 kfree(obj);
431}
432
433static void i915_error_state_free(struct kref *error_ref)
434{
435 struct drm_i915_error_state *error = container_of(error_ref,
436 typeof(*error), ref);
437 int i;
438
439 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
440 i915_error_object_free(error->ring[i].batchbuffer);
441 i915_error_object_free(error->ring[i].ringbuffer);
442 i915_error_object_free(error->ring[i].ctx);
443 kfree(error->ring[i].requests);
444 }
445
446 kfree(error->active_bo);
447 kfree(error->overlay);
448 kfree(error->display);
449 kfree(error);
450}
451
452static struct drm_i915_error_object *
453i915_error_object_create_sized(struct drm_i915_private *dev_priv,
454 struct drm_i915_gem_object *src,
455 const int num_pages)
456{
457 struct drm_i915_error_object *dst;
458 int i;
459 u32 reloc_offset;
460
461 if (src == NULL || src->pages == NULL)
462 return NULL;
463
464 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
465 if (dst == NULL)
466 return NULL;
467
468 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
469 for (i = 0; i < num_pages; i++) {
470 unsigned long flags;
471 void *d;
472
473 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
474 if (d == NULL)
475 goto unwind;
476
477 local_irq_save(flags);
478 if (reloc_offset < dev_priv->gtt.mappable_end &&
479 src->has_global_gtt_mapping) {
480 void __iomem *s;
481
482 /* Simply ignore tiling or any overlapping fence.
483 * It's part of the error state, and this hopefully
484 * captures what the GPU read.
485 */
486
487 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
488 reloc_offset);
489 memcpy_fromio(d, s, PAGE_SIZE);
490 io_mapping_unmap_atomic(s);
491 } else if (src->stolen) {
492 unsigned long offset;
493
494 offset = dev_priv->mm.stolen_base;
495 offset += src->stolen->start;
496 offset += i << PAGE_SHIFT;
497
498 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
499 } else {
500 struct page *page;
501 void *s;
502
503 page = i915_gem_object_get_page(src, i);
504
505 drm_clflush_pages(&page, 1);
506
507 s = kmap_atomic(page);
508 memcpy(d, s, PAGE_SIZE);
509 kunmap_atomic(s);
510
511 drm_clflush_pages(&page, 1);
512 }
513 local_irq_restore(flags);
514
515 dst->pages[i] = d;
516
517 reloc_offset += PAGE_SIZE;
518 }
519 dst->page_count = num_pages;
520
521 return dst;
522
523unwind:
524 while (i--)
525 kfree(dst->pages[i]);
526 kfree(dst);
527 return NULL;
528}
529#define i915_error_object_create(dev_priv, src) \
530 i915_error_object_create_sized((dev_priv), (src), \
531 (src)->base.size>>PAGE_SHIFT)
532
533static void capture_bo(struct drm_i915_error_buffer *err,
534 struct drm_i915_gem_object *obj)
535{
536 err->size = obj->base.size;
537 err->name = obj->base.name;
538 err->rseqno = obj->last_read_seqno;
539 err->wseqno = obj->last_write_seqno;
540 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
541 err->read_domains = obj->base.read_domains;
542 err->write_domain = obj->base.write_domain;
543 err->fence_reg = obj->fence_reg;
544 err->pinned = 0;
545 if (obj->pin_count > 0)
546 err->pinned = 1;
547 if (obj->user_pin_count > 0)
548 err->pinned = -1;
549 err->tiling = obj->tiling_mode;
550 err->dirty = obj->dirty;
551 err->purgeable = obj->madv != I915_MADV_WILLNEED;
552 err->ring = obj->ring ? obj->ring->id : -1;
553 err->cache_level = obj->cache_level;
554}
555
556static u32 capture_active_bo(struct drm_i915_error_buffer *err,
557 int count, struct list_head *head)
558{
559 struct drm_i915_gem_object *obj;
560 int i = 0;
561
562 list_for_each_entry(obj, head, mm_list) {
563 capture_bo(err++, obj);
564 if (++i == count)
565 break;
566 }
567
568 return i;
569}
570
571static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
572 int count, struct list_head *head)
573{
574 struct drm_i915_gem_object *obj;
575 int i = 0;
576
577 list_for_each_entry(obj, head, global_list) {
578 if (obj->pin_count == 0)
579 continue;
580
581 capture_bo(err++, obj);
582 if (++i == count)
583 break;
584 }
585
586 return i;
587}
588
589static void i915_gem_record_fences(struct drm_device *dev,
590 struct drm_i915_error_state *error)
591{
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 int i;
594
595 /* Fences */
596 switch (INTEL_INFO(dev)->gen) {
597 case 7:
598 case 6:
599 for (i = 0; i < dev_priv->num_fence_regs; i++)
600 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
601 break;
602 case 5:
603 case 4:
604 for (i = 0; i < 16; i++)
605 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
606 break;
607 case 3:
608 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
609 for (i = 0; i < 8; i++)
610 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
611 case 2:
612 for (i = 0; i < 8; i++)
613 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
614 break;
615
616 default:
617 BUG();
618 }
619}
620
621static struct drm_i915_error_object *
622i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
623 struct intel_ring_buffer *ring)
624{
625 struct drm_i915_gem_object *obj;
626 u32 seqno;
627
628 if (!ring->get_seqno)
629 return NULL;
630
631 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
632 u32 acthd = I915_READ(ACTHD);
633
634 if (WARN_ON(ring->id != RCS))
635 return NULL;
636
637 obj = ring->private;
638 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
639 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
640 return i915_error_object_create(dev_priv, obj);
641 }
642
643 seqno = ring->get_seqno(ring, false);
644 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
645 if (obj->ring != ring)
646 continue;
647
648 if (i915_seqno_passed(seqno, obj->last_read_seqno))
649 continue;
650
651 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
652 continue;
653
654 /* We need to copy these to an anonymous buffer as the simplest
655 * method to avoid being overwritten by userspace.
656 */
657 return i915_error_object_create(dev_priv, obj);
658 }
659
660 return NULL;
661}
662
663static void i915_record_ring_state(struct drm_device *dev,
664 struct drm_i915_error_state *error,
665 struct intel_ring_buffer *ring)
666{
667 struct drm_i915_private *dev_priv = dev->dev_private;
668
669 if (INTEL_INFO(dev)->gen >= 6) {
670 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
671 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
672 error->semaphore_mboxes[ring->id][0]
673 = I915_READ(RING_SYNC_0(ring->mmio_base));
674 error->semaphore_mboxes[ring->id][1]
675 = I915_READ(RING_SYNC_1(ring->mmio_base));
676 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
677 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
678 }
679
680 if (INTEL_INFO(dev)->gen >= 4) {
681 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
682 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
683 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
684 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
685 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
686 if (ring->id == RCS)
687 error->bbaddr = I915_READ64(BB_ADDR);
688 } else {
689 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
690 error->ipeir[ring->id] = I915_READ(IPEIR);
691 error->ipehr[ring->id] = I915_READ(IPEHR);
692 error->instdone[ring->id] = I915_READ(INSTDONE);
693 }
694
695 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
696 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
697 error->seqno[ring->id] = ring->get_seqno(ring, false);
698 error->acthd[ring->id] = intel_ring_get_active_head(ring);
699 error->head[ring->id] = I915_READ_HEAD(ring);
700 error->tail[ring->id] = I915_READ_TAIL(ring);
701 error->ctl[ring->id] = I915_READ_CTL(ring);
702
703 error->cpu_ring_head[ring->id] = ring->head;
704 error->cpu_ring_tail[ring->id] = ring->tail;
705}
706
707
708static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
709 struct drm_i915_error_state *error,
710 struct drm_i915_error_ring *ering)
711{
712 struct drm_i915_private *dev_priv = ring->dev->dev_private;
713 struct drm_i915_gem_object *obj;
714
715 /* Currently render ring is the only HW context user */
716 if (ring->id != RCS || !error->ccid)
717 return;
718
719 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
720 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
721 ering->ctx = i915_error_object_create_sized(dev_priv,
722 obj, 1);
723 break;
724 }
725 }
726}
727
728static void i915_gem_record_rings(struct drm_device *dev,
729 struct drm_i915_error_state *error)
730{
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 struct intel_ring_buffer *ring;
733 struct drm_i915_gem_request *request;
734 int i, count;
735
736 for_each_ring(ring, dev_priv, i) {
737 i915_record_ring_state(dev, error, ring);
738
739 error->ring[i].batchbuffer =
740 i915_error_first_batchbuffer(dev_priv, ring);
741
742 error->ring[i].ringbuffer =
743 i915_error_object_create(dev_priv, ring->obj);
744
745
746 i915_gem_record_active_context(ring, error, &error->ring[i]);
747
748 count = 0;
749 list_for_each_entry(request, &ring->request_list, list)
750 count++;
751
752 error->ring[i].num_requests = count;
753 error->ring[i].requests =
754 kmalloc(count*sizeof(struct drm_i915_error_request),
755 GFP_ATOMIC);
756 if (error->ring[i].requests == NULL) {
757 error->ring[i].num_requests = 0;
758 continue;
759 }
760
761 count = 0;
762 list_for_each_entry(request, &ring->request_list, list) {
763 struct drm_i915_error_request *erq;
764
765 erq = &error->ring[i].requests[count++];
766 erq->seqno = request->seqno;
767 erq->jiffies = request->emitted_jiffies;
768 erq->tail = request->tail;
769 }
770 }
771}
772
773static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
774 struct drm_i915_error_state *error)
775{
776 struct drm_i915_gem_object *obj;
777 int i;
778
779 i = 0;
780 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
781 i++;
782 error->active_bo_count = i;
783 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
784 if (obj->pin_count)
785 i++;
786 error->pinned_bo_count = i - error->active_bo_count;
787
788 if (i) {
789 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
790 GFP_ATOMIC);
791 if (error->active_bo)
792 error->pinned_bo =
793 error->active_bo + error->active_bo_count;
794 }
795
796 if (error->active_bo)
797 error->active_bo_count =
798 capture_active_bo(error->active_bo,
799 error->active_bo_count,
800 &dev_priv->mm.active_list);
801
802 if (error->pinned_bo)
803 error->pinned_bo_count =
804 capture_pinned_bo(error->pinned_bo,
805 error->pinned_bo_count,
806 &dev_priv->mm.bound_list);
807}
808
809/**
810 * i915_capture_error_state - capture an error record for later analysis
811 * @dev: drm device
812 *
813 * Should be called when an error is detected (either a hang or an error
814 * interrupt) to capture error state from the time of the error. Fills
815 * out a structure which becomes available in debugfs for user level tools
816 * to pick up.
817 */
818void i915_capture_error_state(struct drm_device *dev)
819{
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 struct drm_i915_error_state *error;
822 unsigned long flags;
823 int pipe;
824
825 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
826 error = dev_priv->gpu_error.first_error;
827 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
828 if (error)
829 return;
830
831 /* Account for pipe specific data like PIPE*STAT */
832 error = kzalloc(sizeof(*error), GFP_ATOMIC);
833 if (!error) {
834 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
835 return;
836 }
837
838 DRM_INFO("capturing error event; look for more information in "
839 "/sys/class/drm/card%d/error\n", dev->primary->index);
840
841 kref_init(&error->ref);
842 error->eir = I915_READ(EIR);
843 error->pgtbl_er = I915_READ(PGTBL_ER);
844 if (HAS_HW_CONTEXTS(dev))
845 error->ccid = I915_READ(CCID);
846
847 if (HAS_PCH_SPLIT(dev))
848 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
849 else if (IS_VALLEYVIEW(dev))
850 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
851 else if (IS_GEN2(dev))
852 error->ier = I915_READ16(IER);
853 else
854 error->ier = I915_READ(IER);
855
856 if (INTEL_INFO(dev)->gen >= 6)
857 error->derrmr = I915_READ(DERRMR);
858
859 if (IS_VALLEYVIEW(dev))
860 error->forcewake = I915_READ(FORCEWAKE_VLV);
861 else if (INTEL_INFO(dev)->gen >= 7)
862 error->forcewake = I915_READ(FORCEWAKE_MT);
863 else if (INTEL_INFO(dev)->gen == 6)
864 error->forcewake = I915_READ(FORCEWAKE);
865
866 if (!HAS_PCH_SPLIT(dev))
867 for_each_pipe(pipe)
868 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
869
870 if (INTEL_INFO(dev)->gen >= 6) {
871 error->error = I915_READ(ERROR_GEN6);
872 error->done_reg = I915_READ(DONE_REG);
873 }
874
875 if (INTEL_INFO(dev)->gen == 7)
876 error->err_int = I915_READ(GEN7_ERR_INT);
877
878 i915_get_extra_instdone(dev, error->extra_instdone);
879
880 i915_gem_capture_buffers(dev_priv, error);
881 i915_gem_record_fences(dev, error);
882 i915_gem_record_rings(dev, error);
883
884 do_gettimeofday(&error->time);
885
886 error->overlay = intel_overlay_capture_error_state(dev);
887 error->display = intel_display_capture_error_state(dev);
888
889 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
890 if (dev_priv->gpu_error.first_error == NULL) {
891 dev_priv->gpu_error.first_error = error;
892 error = NULL;
893 }
894 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
895
896 if (error)
897 i915_error_state_free(&error->ref);
898}
899
900void i915_error_state_get(struct drm_device *dev,
901 struct i915_error_state_file_priv *error_priv)
902{
903 struct drm_i915_private *dev_priv = dev->dev_private;
904 unsigned long flags;
905
906 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
907 error_priv->error = dev_priv->gpu_error.first_error;
908 if (error_priv->error)
909 kref_get(&error_priv->error->ref);
910 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
911
912}
913
914void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
915{
916 if (error_priv->error)
917 kref_put(&error_priv->error->ref, i915_error_state_free);
918}
919
920void i915_destroy_error_state(struct drm_device *dev)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923 struct drm_i915_error_state *error;
924 unsigned long flags;
925
926 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
927 error = dev_priv->gpu_error.first_error;
928 dev_priv->gpu_error.first_error = NULL;
929 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
930
931 if (error)
932 kref_put(&error->ref, i915_error_state_free);
933}
934
935const char *i915_cache_level_str(int type)
936{
937 switch (type) {
938 case I915_CACHE_NONE: return " uncached";
939 case I915_CACHE_LLC: return " snooped (LLC)";
940 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
941 default: return "";
942 }
943}
944
945/* NB: please notice the memset */
946void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
947{
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
950
951 switch (INTEL_INFO(dev)->gen) {
952 case 2:
953 case 3:
954 instdone[0] = I915_READ(INSTDONE);
955 break;
956 case 4:
957 case 5:
958 case 6:
959 instdone[0] = I915_READ(INSTDONE_I965);
960 instdone[1] = I915_READ(INSTDONE1);
961 break;
962 default:
963 WARN_ONCE(1, "Unsupported platform\n");
964 case 7:
965 instdone[0] = I915_READ(GEN7_INSTDONE_1);
966 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
967 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
968 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
969 break;
970 }
971}
Linux kernel - Deliverables
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