projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Do not access stolen memory directly by the CPU, even for error capture
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
33static const char *yesno(int v)
34{
35 return v ? "yes" : "no";
36}
37
38static const char *ring_str(int ring)
39{
40 switch (ring) {
41 case RCS: return "render";
42 case VCS: return "bsd";
43 case BCS: return "blt";
44 case VECS: return "vebox";
845f74a7 45 case VCS2: return "bsd2";
84734a04
MK		 46 default: return "";
47 }
48}
49
50static const char *pin_flag(int pinned)
51{
52 if (pinned > 0)
53 return " P";
54 else if (pinned < 0)
55 return " p";
56 else
57 return "";
58}
59
60static const char *tiling_flag(int tiling)
61{
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68}
69
70static const char *dirty_flag(int dirty)
71{
72 return dirty ? " dirty" : "";
73}
74
75static const char *purgeable_flag(int purgeable)
76{
77 return purgeable ? " purgeable" : "";
78}
79
80static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81{
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92}
93
94static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96{
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109}
110
111static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113{
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135}
136
137static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
138 const char *f, va_list args)
139{
140 unsigned len;
141
142 if (!__i915_error_ok(e))
143 return;
144
145 /* Seek the first printf which is hits start position */
146 if (e->pos < e->start) {
e29bb4eb
CW		 147 va_list tmp;
148
149 va_copy(tmp, args);
1d2cb9a5
MK		 150 len = vsnprintf(NULL, 0, f, tmp);
151 va_end(tmp);
152
153 if (!__i915_error_seek(e, len))
84734a04
MK		 154 return;
155 }
156
157 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
158 if (len >= e->size - e->bytes)
159 len = e->size - e->bytes - 1;
160
161 __i915_error_advance(e, len);
162}
163
164static void i915_error_puts(struct drm_i915_error_state_buf *e,
165 const char *str)
166{
167 unsigned len;
168
169 if (!__i915_error_ok(e))
170 return;
171
172 len = strlen(str);
173
174 /* Seek the first printf which is hits start position */
175 if (e->pos < e->start) {
176 if (!__i915_error_seek(e, len))
177 return;
178 }
179
180 if (len >= e->size - e->bytes)
181 len = e->size - e->bytes - 1;
182 memcpy(e->buf + e->bytes, str, len);
183
184 __i915_error_advance(e, len);
185}
186
187#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
188#define err_puts(e, s) i915_error_puts(e, s)
189
190static void print_error_buffers(struct drm_i915_error_state_buf *m,
191 const char *name,
192 struct drm_i915_error_buffer *err,
193 int count)
194{
3a448734 195 err_printf(m, " %s [%d]:\n", name, count);
84734a04
MK		 196
197 while (count--) {
3a448734 198 err_printf(m, " %08x %8u %02x %02x %x %x",
84734a04
MK		 199 err->gtt_offset,
200 err->size,
201 err->read_domains,
202 err->write_domain,
203 err->rseqno, err->wseqno);
204 err_puts(m, pin_flag(err->pinned));
205 err_puts(m, tiling_flag(err->tiling));
206 err_puts(m, dirty_flag(err->dirty));
207 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 208 err_puts(m, err->userptr ? " userptr" : "");
84734a04
MK		 209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(err->cache_level));
212
213 if (err->name)
214 err_printf(m, " (name: %d)", err->name);
215 if (err->fence_reg != I915_FENCE_REG_NONE)
216 err_printf(m, " (fence: %d)", err->fence_reg);
217
218 err_puts(m, "\n");
219 err++;
220 }
221}
222
da661464
MK		 223static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224{
225 switch (a) {
226 case HANGCHECK_IDLE:
227 return "idle";
228 case HANGCHECK_WAIT:
229 return "wait";
230 case HANGCHECK_ACTIVE:
231 return "active";
f260fe7b
MK		 232 case HANGCHECK_ACTIVE_LOOP:
233 return "active (loop)";
da661464
MK		 234 case HANGCHECK_KICK:
235 return "kick";
236 case HANGCHECK_HUNG:
237 return "hung";
238 }
239
240 return "unknown";
241}
242
84734a04
MK		 243static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
244 struct drm_device *dev,
362b8af7 245 struct drm_i915_error_ring *ring)
84734a04 246{
362b8af7 247 if (!ring->valid)
372fbb8e
CW		 248 return;
249
362b8af7
BW		 250 err_printf(m, " HEAD: 0x%08x\n", ring->head);
251 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
252 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
253 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 254 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 255 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
256 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
257 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 258 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 259 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 260 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
261 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 262 }
362b8af7 263 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 264 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
265 lower_32_bits(ring->faddr));
84734a04 266 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 267 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
268 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 269 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 270 ring->semaphore_mboxes[0],
271 ring->semaphore_seqno[0]);
84734a04 272 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 273 ring->semaphore_mboxes[1],
274 ring->semaphore_seqno[1]);
4e5aabfd
BW		 275 if (HAS_VEBOX(dev)) {
276 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 277 ring->semaphore_mboxes[2],
278 ring->semaphore_seqno[2]);
4e5aabfd 279 }
84734a04 280 }
6c7a01ec
BW		 281 if (USES_PPGTT(dev)) {
282 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
283
284 if (INTEL_INFO(dev)->gen >= 8) {
285 int i;
286 for (i = 0; i < 4; i++)
287 err_printf(m, " PDP%d: 0x%016llx\n",
288 i, ring->vm_info.pdp[i]);
289 } else {
290 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
291 ring->vm_info.pp_dir_base);
292 }
293 }
362b8af7
BW		 294 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
295 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
296 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
297 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 298 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 299 hangcheck_action_to_str(ring->hangcheck_action),
300 ring->hangcheck_score);
84734a04
MK		 301}
302
303void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
304{
305 va_list args;
306
307 va_start(args, f);
308 i915_error_vprintf(e, f, args);
309 va_end(args);
310}
311
ab0e7ff9
CW		 312static void print_error_obj(struct drm_i915_error_state_buf *m,
313 struct drm_i915_error_object *obj)
314{
315 int page, offset, elt;
316
317 for (page = offset = 0; page < obj->page_count; page++) {
318 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
319 err_printf(m, "%08x : %08x\n", offset,
320 obj->pages[page][elt]);
321 offset += 4;
322 }
323 }
324}
325
84734a04
MK		 326int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
327 const struct i915_error_state_file_priv *error_priv)
328{
329 struct drm_device *dev = error_priv->dev;
50227e1c 330 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 331 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 332 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 333 int i, j, offset, elt;
334 int max_hangcheck_score;
84734a04
MK		 335
336 if (!error) {
337 err_printf(m, "no error state collected\n");
338 goto out;
339 }
340
cb383002 341 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 342 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
343 error->time.tv_usec);
344 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 345 max_hangcheck_score = 0;
346 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
347 if (error->ring[i].hangcheck_score > max_hangcheck_score)
348 max_hangcheck_score = error->ring[i].hangcheck_score;
349 }
350 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
351 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
352 error->ring[i].pid != -1) {
353 err_printf(m, "Active process (on ring %s): %s [%d]\n",
354 ring_str(i),
355 error->ring[i].comm,
356 error->ring[i].pid);
357 }
358 }
48b031e3 359 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 360 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 361 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
84734a04
MK		 362 err_printf(m, "EIR: 0x%08x\n", error->eir);
363 err_printf(m, "IER: 0x%08x\n", error->ier);
885ea5a8
RV		 364 if (INTEL_INFO(dev)->gen >= 8) {
365 for (i = 0; i < 4; i++)
366 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
367 error->gtier[i]);
368 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
369 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
84734a04
MK		 370 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
371 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
372 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
373 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 374 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 375
376 for (i = 0; i < dev_priv->num_fence_regs; i++)
377 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
378
379 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
380 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
381 error->extra_instdone[i]);
382
383 if (INTEL_INFO(dev)->gen >= 6) {
384 err_printf(m, "ERROR: 0x%08x\n", error->error);
385 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
386 }
387
388 if (INTEL_INFO(dev)->gen == 7)
389 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
390
362b8af7
BW		 391 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
392 err_printf(m, "%s command stream:\n", ring_str(i));
393 i915_ring_error_state(m, dev, &error->ring[i]);
394 }
84734a04 395
3a448734
CW		 396 for (i = 0; i < error->vm_count; i++) {
397 err_printf(m, "vm[%d]\n", i);
398
84734a04 399 print_error_buffers(m, "Active",
3a448734
CW		 400 error->active_bo[i],
401 error->active_bo_count[i]);
84734a04 402
84734a04 403 print_error_buffers(m, "Pinned",
3a448734
CW		 404 error->pinned_bo[i],
405 error->pinned_bo_count[i]);
406 }
84734a04
MK		 407
408 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
ab0e7ff9
CW		 409 obj = error->ring[i].batchbuffer;
410 if (obj) {
411 err_puts(m, dev_priv->ring[i].name);
412 if (error->ring[i].pid != -1)
413 err_printf(m, " (submitted by %s [%d])",
414 error->ring[i].comm,
415 error->ring[i].pid);
416 err_printf(m, " --- gtt_offset = 0x%08x\n",
84734a04 417 obj->gtt_offset);
ab0e7ff9
CW		 418 print_error_obj(m, obj);
419 }
420
421 obj = error->ring[i].wa_batchbuffer;
422 if (obj) {
423 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
424 dev_priv->ring[i].name, obj->gtt_offset);
425 print_error_obj(m, obj);
84734a04
MK		 426 }
427
428 if (error->ring[i].num_requests) {
429 err_printf(m, "%s --- %d requests\n",
430 dev_priv->ring[i].name,
431 error->ring[i].num_requests);
432 for (j = 0; j < error->ring[i].num_requests; j++) {
433 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
434 error->ring[i].requests[j].seqno,
435 error->ring[i].requests[j].jiffies,
436 error->ring[i].requests[j].tail);
437 }
438 }
439
440 if ((obj = error->ring[i].ringbuffer)) {
441 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
442 dev_priv->ring[i].name,
443 obj->gtt_offset);
ab0e7ff9 444 print_error_obj(m, obj);
84734a04
MK		 445 }
446
362b8af7 447 if ((obj = error->ring[i].hws_page)) {
f3ce3821
CW		 448 err_printf(m, "%s --- HW Status = 0x%08x\n",
449 dev_priv->ring[i].name,
450 obj->gtt_offset);
451 offset = 0;
452 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
453 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
454 offset,
455 obj->pages[0][elt],
456 obj->pages[0][elt+1],
457 obj->pages[0][elt+2],
458 obj->pages[0][elt+3]);
459 offset += 16;
460 }
461 }
462
372fbb8e 463 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 464 err_printf(m, "%s --- HW Context = 0x%08x\n",
465 dev_priv->ring[i].name,
466 obj->gtt_offset);
17d36749 467 print_error_obj(m, obj);
84734a04
MK		 468 }
469 }
470
0ca36d78
BW		 471 if ((obj = error->semaphore_obj)) {
472 err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset);
473 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
474 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
475 elt * 4,
476 obj->pages[0][elt],
477 obj->pages[0][elt+1],
478 obj->pages[0][elt+2],
479 obj->pages[0][elt+3]);
480 }
481 }
482
84734a04
MK		 483 if (error->overlay)
484 intel_overlay_print_error_state(m, error->overlay);
485
486 if (error->display)
487 intel_display_print_error_state(m, dev, error->display);
488
489out:
490 if (m->bytes == 0 && m->err)
491 return m->err;
492
493 return 0;
494}
495
496int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
497 size_t count, loff_t pos)
498{
499 memset(ebuf, 0, sizeof(*ebuf));
500
501 /* We need to have enough room to store any i915_error_state printf
502 * so that we can move it to start position.
503 */
504 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
505 ebuf->buf = kmalloc(ebuf->size,
506 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
507
508 if (ebuf->buf == NULL) {
509 ebuf->size = PAGE_SIZE;
510 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
511 }
512
513 if (ebuf->buf == NULL) {
514 ebuf->size = 128;
515 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
516 }
517
518 if (ebuf->buf == NULL)
519 return -ENOMEM;
520
521 ebuf->start = pos;
522
523 return 0;
524}
525
526static void i915_error_object_free(struct drm_i915_error_object *obj)
527{
528 int page;
529
530 if (obj == NULL)
531 return;
532
533 for (page = 0; page < obj->page_count; page++)
534 kfree(obj->pages[page]);
535
536 kfree(obj);
537}
538
539static void i915_error_state_free(struct kref *error_ref)
540{
541 struct drm_i915_error_state *error = container_of(error_ref,
542 typeof(*error), ref);
543 int i;
544
545 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
546 i915_error_object_free(error->ring[i].batchbuffer);
547 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 548 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 549 i915_error_object_free(error->ring[i].ctx);
550 kfree(error->ring[i].requests);
551 }
552
0ca36d78 553 i915_error_object_free(error->semaphore_obj);
84734a04
MK		 554 kfree(error->active_bo);
555 kfree(error->overlay);
556 kfree(error->display);
557 kfree(error);
558}
559
560static struct drm_i915_error_object *
561i915_error_object_create_sized(struct drm_i915_private *dev_priv,
562 struct drm_i915_gem_object *src,
a7b91078 563 struct i915_address_space *vm,
b3c3f5e6 564 int num_pages)
84734a04
MK		 565{
566 struct drm_i915_error_object *dst;
b3c3f5e6
CW		 567 bool use_ggtt;
568 int i = 0;
84734a04
MK		 569 u32 reloc_offset;
570
571 if (src == NULL || src->pages == NULL)
572 return NULL;
573
574 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
575 if (dst == NULL)
576 return NULL;
577
b3c3f5e6
CW		 578 dst->gtt_offset = i915_gem_obj_offset(src, vm);
579
580 reloc_offset = dst->gtt_offset;
581 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
582 i915_is_ggtt(vm) &&
583 src->has_global_gtt_mapping &&
584 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
585
586 /* Cannot access stolen address directly, try to use the aperture */
587 if (src->stolen) {
588 use_ggtt = true;
589
590 if (!src->has_global_gtt_mapping)
591 goto unwind;
592
593 reloc_offset = i915_gem_obj_ggtt_offset(src);
594 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
595 goto unwind;
596 }
597
598 /* Cannot access snooped pages through the aperture */
599 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
600 goto unwind;
601
602 dst->page_count = num_pages;
603 while (num_pages--) {
84734a04
MK		 604 unsigned long flags;
605 void *d;
606
607 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
608 if (d == NULL)
609 goto unwind;
610
611 local_irq_save(flags);
b3c3f5e6 612 if (use_ggtt) {
84734a04
MK		 613 void __iomem *s;
614
615 /* Simply ignore tiling or any overlapping fence.
616 * It's part of the error state, and this hopefully
617 * captures what the GPU read.
618 */
619
620 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
621 reloc_offset);
622 memcpy_fromio(d, s, PAGE_SIZE);
623 io_mapping_unmap_atomic(s);
84734a04
MK		 624 } else {
625 struct page *page;
626 void *s;
627
628 page = i915_gem_object_get_page(src, i);
629
630 drm_clflush_pages(&page, 1);
631
632 s = kmap_atomic(page);
633 memcpy(d, s, PAGE_SIZE);
634 kunmap_atomic(s);
635
636 drm_clflush_pages(&page, 1);
637 }
638 local_irq_restore(flags);
639
b3c3f5e6 640 dst->pages[i++] = d;
84734a04
MK		 641 reloc_offset += PAGE_SIZE;
642 }
84734a04
MK		 643
644 return dst;
645
646unwind:
647 while (i--)
648 kfree(dst->pages[i]);
649 kfree(dst);
650 return NULL;
651}
a7b91078
BW		 652#define i915_error_object_create(dev_priv, src, vm) \
653 i915_error_object_create_sized((dev_priv), (src), (vm), \
654 (src)->base.size>>PAGE_SHIFT)
655
656#define i915_error_ggtt_object_create(dev_priv, src) \
657 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
84734a04
MK		 658 (src)->base.size>>PAGE_SHIFT)
659
660static void capture_bo(struct drm_i915_error_buffer *err,
3a448734 661 struct i915_vma *vma)
84734a04 662{
3a448734
CW		 663 struct drm_i915_gem_object *obj = vma->obj;
664
84734a04
MK		 665 err->size = obj->base.size;
666 err->name = obj->base.name;
667 err->rseqno = obj->last_read_seqno;
668 err->wseqno = obj->last_write_seqno;
3a448734 669 err->gtt_offset = vma->node.start;
84734a04
MK		 670 err->read_domains = obj->base.read_domains;
671 err->write_domain = obj->base.write_domain;
672 err->fence_reg = obj->fence_reg;
673 err->pinned = 0;
d7f46fc4 674 if (i915_gem_obj_is_pinned(obj))
84734a04
MK		 675 err->pinned = 1;
676 if (obj->user_pin_count > 0)
677 err->pinned = -1;
678 err->tiling = obj->tiling_mode;
679 err->dirty = obj->dirty;
680 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 681 err->userptr = obj->userptr.mm != NULL;
84734a04
MK		 682 err->ring = obj->ring ? obj->ring->id : -1;
683 err->cache_level = obj->cache_level;
684}
685
686static u32 capture_active_bo(struct drm_i915_error_buffer *err,
687 int count, struct list_head *head)
688{
ca191b13 689 struct i915_vma *vma;
84734a04
MK		 690 int i = 0;
691
ca191b13 692 list_for_each_entry(vma, head, mm_list) {
3a448734 693 capture_bo(err++, vma);
84734a04
MK		 694 if (++i == count)
695 break;
696 }
697
698 return i;
699}
700
701static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
3a448734
CW		 702 int count, struct list_head *head,
703 struct i915_address_space *vm)
84734a04
MK		 704{
705 struct drm_i915_gem_object *obj;
3a448734
CW		 706 struct drm_i915_error_buffer * const first = err;
707 struct drm_i915_error_buffer * const last = err + count;
84734a04
MK		 708
709 list_for_each_entry(obj, head, global_list) {
3a448734 710 struct i915_vma *vma;
84734a04 711
3a448734 712 if (err == last)
84734a04 713 break;
3a448734
CW		 714
715 list_for_each_entry(vma, &obj->vma_list, vma_link)
716 if (vma->vm == vm && vma->pin_count > 0) {
717 capture_bo(err++, vma);
718 break;
719 }
84734a04
MK		 720 }
721
3a448734 722 return err - first;
84734a04
MK		 723}
724
011cf577
BW		 725/* Generate a semi-unique error code. The code is not meant to have meaning, The
726 * code's only purpose is to try to prevent false duplicated bug reports by
727 * grossly estimating a GPU error state.
728 *
729 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
730 * the hang if we could strip the GTT offset information from it.
731 *
732 * It's only a small step better than a random number in its current form.
733 */
734static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 735 struct drm_i915_error_state *error,
736 int *ring_id)
011cf577
BW		 737{
738 uint32_t error_code = 0;
739 int i;
740
741 /* IPEHR would be an ideal way to detect errors, as it's the gross
742 * measure of "the command that hung." However, has some very common
743 * synchronization commands which almost always appear in the case
744 * strictly a client bug. Use instdone to differentiate those some.
745 */
cb383002
MK		 746 for (i = 0; i < I915_NUM_RINGS; i++) {
747 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
748 if (ring_id)
749 *ring_id = i;
750
011cf577 751 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 752 }
753 }
011cf577
BW		 754
755 return error_code;
756}
757
84734a04
MK		 758static void i915_gem_record_fences(struct drm_device *dev,
759 struct drm_i915_error_state *error)
760{
761 struct drm_i915_private *dev_priv = dev->dev_private;
762 int i;
763
764 /* Fences */
765 switch (INTEL_INFO(dev)->gen) {
5ab31333 766 case 8:
84734a04
MK		 767 case 7:
768 case 6:
769 for (i = 0; i < dev_priv->num_fence_regs; i++)
770 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
771 break;
772 case 5:
773 case 4:
774 for (i = 0; i < 16; i++)
775 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
776 break;
777 case 3:
778 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
779 for (i = 0; i < 8; i++)
780 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
781 case 2:
782 for (i = 0; i < 8; i++)
783 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
784 break;
785
786 default:
787 BUG();
788 }
789}
790
87f85ebc 791
0ca36d78
BW		 792static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
793 struct drm_i915_error_state *error,
794 struct intel_engine_cs *ring,
795 struct drm_i915_error_ring *ering)
796{
b4558b46 797 struct intel_engine_cs *to;
0ca36d78
BW		 798 int i;
799
800 if (!i915_semaphore_is_enabled(dev_priv->dev))
801 return;
802
803 if (!error->semaphore_obj)
804 error->semaphore_obj =
805 i915_error_object_create(dev_priv,
806 dev_priv->semaphore_obj,
807 &dev_priv->gtt.base);
808
b4558b46
RV		 809 for_each_ring(to, dev_priv, i) {
810 int idx;
811 u16 signal_offset;
812 u32 *tmp;
0ca36d78 813
b4558b46
RV		 814 if (ring == to)
815 continue;
816
864c6181
RV		 817 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
818 / 4;
b4558b46
RV		 819 tmp = error->semaphore_obj->pages[0];
820 idx = intel_ring_sync_index(ring, to);
821
822 ering->semaphore_mboxes[idx] = tmp[signal_offset];
823 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
0ca36d78
BW		 824 }
825}
826
87f85ebc
BW		 827static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
828 struct intel_engine_cs *ring,
829 struct drm_i915_error_ring *ering)
830{
831 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
832 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
833 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
834 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
835
836 if (HAS_VEBOX(dev_priv->dev)) {
837 ering->semaphore_mboxes[2] =
838 I915_READ(RING_SYNC_2(ring->mmio_base));
839 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
840 }
841}
842
84734a04 843static void i915_record_ring_state(struct drm_device *dev,
0ca36d78 844 struct drm_i915_error_state *error,
a4872ba6 845 struct intel_engine_cs *ring,
362b8af7 846 struct drm_i915_error_ring *ering)
84734a04
MK		 847{
848 struct drm_i915_private *dev_priv = dev->dev_private;
849
850 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 851 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
852 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
0ca36d78
BW		 853 if (INTEL_INFO(dev)->gen >= 8)
854 gen8_record_semaphore_state(dev_priv, error, ring, ering);
855 else
856 gen6_record_semaphore_state(dev_priv, ring, ering);
4e5aabfd
BW		 857 }
858
84734a04 859 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 860 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
861 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
862 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
863 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
864 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
865 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 866 if (INTEL_INFO(dev)->gen >= 8) {
867 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 868 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 869 }
362b8af7 870 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 871 } else {
362b8af7
BW		 872 ering->faddr = I915_READ(DMA_FADD_I8XX);
873 ering->ipeir = I915_READ(IPEIR);
874 ering->ipehr = I915_READ(IPEHR);
875 ering->instdone = I915_READ(INSTDONE);
84734a04
MK		 876 }
877
362b8af7
BW		 878 ering->waiting = waitqueue_active(&ring->irq_queue);
879 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
880 ering->seqno = ring->get_seqno(ring, false);
881 ering->acthd = intel_ring_get_active_head(ring);
882 ering->head = I915_READ_HEAD(ring);
883 ering->tail = I915_READ_TAIL(ring);
884 ering->ctl = I915_READ_CTL(ring);
84734a04 885
f3ce3821
CW		 886 if (I915_NEED_GFX_HWS(dev)) {
887 int mmio;
888
889 if (IS_GEN7(dev)) {
890 switch (ring->id) {
891 default:
892 case RCS:
893 mmio = RENDER_HWS_PGA_GEN7;
894 break;
895 case BCS:
896 mmio = BLT_HWS_PGA_GEN7;
897 break;
898 case VCS:
899 mmio = BSD_HWS_PGA_GEN7;
900 break;
901 case VECS:
902 mmio = VEBOX_HWS_PGA_GEN7;
903 break;
904 }
905 } else if (IS_GEN6(ring->dev)) {
906 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
907 } else {
908 /* XXX: gen8 returns to sanity */
909 mmio = RING_HWS_PGA(ring->mmio_base);
910 }
911
362b8af7 912 ering->hws = I915_READ(mmio);
f3ce3821
CW		 913 }
914
ee1b1e5e
OM		 915 ering->cpu_ring_head = ring->buffer->head;
916 ering->cpu_ring_tail = ring->buffer->tail;
da661464 917
362b8af7
BW		 918 ering->hangcheck_score = ring->hangcheck.score;
919 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 920
921 if (USES_PPGTT(dev)) {
922 int i;
923
924 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
925
926 switch (INTEL_INFO(dev)->gen) {
927 case 8:
928 for (i = 0; i < 4; i++) {
929 ering->vm_info.pdp[i] =
930 I915_READ(GEN8_RING_PDP_UDW(ring, i));
931 ering->vm_info.pdp[i] <<= 32;
932 ering->vm_info.pdp[i] |=
933 I915_READ(GEN8_RING_PDP_LDW(ring, i));
934 }
935 break;
936 case 7:
ae89f44d
BW		 937 ering->vm_info.pp_dir_base =
938 I915_READ(RING_PP_DIR_BASE(ring));
6c7a01ec
BW		 939 break;
940 case 6:
ae89f44d
BW		 941 ering->vm_info.pp_dir_base =
942 I915_READ(RING_PP_DIR_BASE_READ(ring));
6c7a01ec
BW		 943 break;
944 }
945 }
84734a04
MK		 946}
947
948
a4872ba6 949static void i915_gem_record_active_context(struct intel_engine_cs *ring,
84734a04
MK		 950 struct drm_i915_error_state *error,
951 struct drm_i915_error_ring *ering)
952{
953 struct drm_i915_private *dev_priv = ring->dev->dev_private;
954 struct drm_i915_gem_object *obj;
955
956 /* Currently render ring is the only HW context user */
957 if (ring->id != RCS || !error->ccid)
958 return;
959
960 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
36362ad3
BW		 961 if (!i915_gem_obj_ggtt_bound(obj))
962 continue;
963
84734a04 964 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
17d36749 965 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 966 break;
967 }
968 }
969}
970
971static void i915_gem_record_rings(struct drm_device *dev,
972 struct drm_i915_error_state *error)
973{
974 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 975 struct drm_i915_gem_request *request;
976 int i, count;
977
372fbb8e 978 for (i = 0; i < I915_NUM_RINGS; i++) {
a4872ba6 979 struct intel_engine_cs *ring = &dev_priv->ring[i];
372fbb8e 980
eee73b46
CW		 981 error->ring[i].pid = -1;
982
372fbb8e
CW		 983 if (ring->dev == NULL)
984 continue;
985
986 error->ring[i].valid = true;
987
0ca36d78 988 i915_record_ring_state(dev, error, ring, &error->ring[i]);
84734a04 989
ab0e7ff9
CW		 990 request = i915_gem_find_active_request(ring);
991 if (request) {
ae6c4806
DV		 992 struct i915_address_space *vm;
993
994 vm = request->ctx && request->ctx->ppgtt ?
995 &request->ctx->ppgtt->base :
996 &dev_priv->gtt.base;
997
ab0e7ff9
CW		 998 /* We need to copy these to an anonymous buffer
999 * as the simplest method to avoid being overwritten
1000 * by userspace.
1001 */
1002 error->ring[i].batchbuffer =
1003 i915_error_object_create(dev_priv,
1004 request->batch_obj,
ae6c4806 1005 vm);
ab0e7ff9
CW		 1006
1007 if (HAS_BROKEN_CS_TLB(dev_priv->dev) &&
1008 ring->scratch.obj)
1009 error->ring[i].wa_batchbuffer =
1010 i915_error_ggtt_object_create(dev_priv,
1011 ring->scratch.obj);
1012
1013 if (request->file_priv) {
1014 struct task_struct *task;
1015
1016 rcu_read_lock();
1017 task = pid_task(request->file_priv->file->pid,
1018 PIDTYPE_PID);
1019 if (task) {
1020 strcpy(error->ring[i].comm, task->comm);
1021 error->ring[i].pid = task->pid;
1022 }
1023 rcu_read_unlock();
1024 }
1025 }
84734a04
MK		 1026
1027 error->ring[i].ringbuffer =
ee1b1e5e 1028 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj);
84734a04 1029
f3ce3821 1030 if (ring->status_page.obj)
362b8af7 1031 error->ring[i].hws_page =
f3ce3821 1032 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 1033
1034 i915_gem_record_active_context(ring, error, &error->ring[i]);
1035
1036 count = 0;
1037 list_for_each_entry(request, &ring->request_list, list)
1038 count++;
1039
1040 error->ring[i].num_requests = count;
1041 error->ring[i].requests =
a1e22653 1042 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 1043 GFP_ATOMIC);
1044 if (error->ring[i].requests == NULL) {
1045 error->ring[i].num_requests = 0;
1046 continue;
1047 }
1048
1049 count = 0;
1050 list_for_each_entry(request, &ring->request_list, list) {
1051 struct drm_i915_error_request *erq;
1052
1053 erq = &error->ring[i].requests[count++];
1054 erq->seqno = request->seqno;
1055 erq->jiffies = request->emitted_jiffies;
1056 erq->tail = request->tail;
1057 }
1058 }
1059}
1060
95f5301d
BW		 1061/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1062 * VM.
1063 */
1064static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1065 struct drm_i915_error_state *error,
1066 struct i915_address_space *vm,
1067 const int ndx)
84734a04 1068{
95f5301d 1069 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 1070 struct drm_i915_gem_object *obj;
95f5301d 1071 struct i915_vma *vma;
84734a04
MK		 1072 int i;
1073
1074 i = 0;
ca191b13 1075 list_for_each_entry(vma, &vm->active_list, mm_list)
84734a04 1076 i++;
95f5301d 1077 error->active_bo_count[ndx] = i;
3a448734
CW		 1078
1079 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1080 list_for_each_entry(vma, &obj->vma_list, vma_link)
1081 if (vma->vm == vm && vma->pin_count > 0) {
1082 i++;
1083 break;
1084 }
1085 }
95f5301d 1086 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 1087
1088 if (i) {
a1e22653 1089 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 1090 if (active_bo)
1091 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1092 }
1093
95f5301d
BW		 1094 if (active_bo)
1095 error->active_bo_count[ndx] =
1096 capture_active_bo(active_bo,
1097 error->active_bo_count[ndx],
5cef07e1 1098 &vm->active_list);
84734a04 1099
95f5301d
BW		 1100 if (pinned_bo)
1101 error->pinned_bo_count[ndx] =
1102 capture_pinned_bo(pinned_bo,
1103 error->pinned_bo_count[ndx],
3a448734 1104 &dev_priv->mm.bound_list, vm);
95f5301d
BW		 1105 error->active_bo[ndx] = active_bo;
1106 error->pinned_bo[ndx] = pinned_bo;
1107}
1108
1109static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1110 struct drm_i915_error_state *error)
1111{
1112 struct i915_address_space *vm;
1113 int cnt = 0, i = 0;
1114
1115 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1116 cnt++;
1117
95f5301d
BW		 1118 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1119 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1120 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1121 GFP_ATOMIC);
1122 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1123 GFP_ATOMIC);
1124
3a448734
CW		 1125 if (error->active_bo == NULL ||
1126 error->pinned_bo == NULL ||
1127 error->active_bo_count == NULL ||
1128 error->pinned_bo_count == NULL) {
1129 kfree(error->active_bo);
1130 kfree(error->active_bo_count);
1131 kfree(error->pinned_bo);
1132 kfree(error->pinned_bo_count);
1133
1134 error->active_bo = NULL;
1135 error->active_bo_count = NULL;
1136 error->pinned_bo = NULL;
1137 error->pinned_bo_count = NULL;
1138 } else {
1139 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1140 i915_gem_capture_vm(dev_priv, error, vm, i++);
1141
1142 error->vm_count = cnt;
1143 }
84734a04
MK		 1144}
1145
1d762aad
BW		 1146/* Capture all registers which don't fit into another category. */
1147static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1148 struct drm_i915_error_state *error)
84734a04 1149{
1d762aad 1150 struct drm_device *dev = dev_priv->dev;
885ea5a8 1151 int i;
84734a04 1152
654c90c6
BW		 1153 /* General organization
1154 * 1. Registers specific to a single generation
1155 * 2. Registers which belong to multiple generations
1156 * 3. Feature specific registers.
1157 * 4. Everything else
1158 * Please try to follow the order.
1159 */
84734a04 1160
654c90c6
BW		 1161 /* 1: Registers specific to a single generation */
1162 if (IS_VALLEYVIEW(dev)) {
885ea5a8 1163 error->gtier[0] = I915_READ(GTIER);
843db716 1164 error->ier = I915_READ(VLV_IER);
654c90c6
BW		 1165 error->forcewake = I915_READ(FORCEWAKE_VLV);
1166 }
84734a04 1167
654c90c6
BW		 1168 if (IS_GEN7(dev))
1169 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1170
91ec5d11 1171 if (IS_GEN6(dev)) {
84734a04 1172 error->forcewake = I915_READ(FORCEWAKE);
91ec5d11
BW		 1173 error->gab_ctl = I915_READ(GAB_CTL);
1174 error->gfx_mode = I915_READ(GFX_MODE);
1175 }
84734a04 1176
654c90c6
BW		 1177 /* 2: Registers which belong to multiple generations */
1178 if (INTEL_INFO(dev)->gen >= 7)
1179 error->forcewake = I915_READ(FORCEWAKE_MT);
84734a04
MK		 1180
1181 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1182 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1183 error->error = I915_READ(ERROR_GEN6);
1184 error->done_reg = I915_READ(DONE_REG);
1185 }
1186
654c90c6 1187 /* 3: Feature specific registers */
91ec5d11
BW		 1188 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1189 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1190 error->gac_eco = I915_READ(GAC_ECO_BITS);
1191 }
1192
1193 /* 4: Everything else */
654c90c6
BW		 1194 if (HAS_HW_CONTEXTS(dev))
1195 error->ccid = I915_READ(CCID);
1196
885ea5a8
RV		 1197 if (INTEL_INFO(dev)->gen >= 8) {
1198 error->ier = I915_READ(GEN8_DE_MISC_IER);
1199 for (i = 0; i < 4; i++)
1200 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1201 } else if (HAS_PCH_SPLIT(dev)) {
843db716 1202 error->ier = I915_READ(DEIER);
885ea5a8 1203 error->gtier[0] = I915_READ(GTIER);
843db716
RV		 1204 } else if (IS_GEN2(dev)) {
1205 error->ier = I915_READ16(IER);
1206 } else if (!IS_VALLEYVIEW(dev)) {
1207 error->ier = I915_READ(IER);
654c90c6 1208 }
654c90c6
BW		 1209 error->eir = I915_READ(EIR);
1210 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1211
1212 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1213}
1214
cb383002 1215static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1216 struct drm_i915_error_state *error,
1217 bool wedged,
1218 const char *error_msg)
cb383002
MK		 1219{
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 u32 ecode;
58174462 1222 int ring_id = -1, len;
cb383002
MK		 1223
1224 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1225
58174462
MK		 1226 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1227 "GPU HANG: ecode %d:0x%08x", ring_id, ecode);
1228
1229 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1230 len += scnprintf(error->error_msg + len,
1231 sizeof(error->error_msg) - len,
1232 ", in %s [%d]",
1233 error->ring[ring_id].comm,
1234 error->ring[ring_id].pid);
1235
1236 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1237 ", reason: %s, action: %s",
1238 error_msg,
1239 wedged ? "reset" : "continue");
cb383002
MK		 1240}
1241
48b031e3
MK		 1242static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1243 struct drm_i915_error_state *error)
1244{
1245 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1246 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1247}
1248
1d762aad
BW		 1249/**
1250 * i915_capture_error_state - capture an error record for later analysis
1251 * @dev: drm device
1252 *
1253 * Should be called when an error is detected (either a hang or an error
1254 * interrupt) to capture error state from the time of the error. Fills
1255 * out a structure which becomes available in debugfs for user level tools
1256 * to pick up.
1257 */
58174462
MK		 1258void i915_capture_error_state(struct drm_device *dev, bool wedged,
1259 const char *error_msg)
1d762aad 1260{
53a4c6b2 1261 static bool warned;
1d762aad
BW		 1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263 struct drm_i915_error_state *error;
1264 unsigned long flags;
1d762aad
BW		 1265
1266 /* Account for pipe specific data like PIPE*STAT */
1267 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1268 if (!error) {
1269 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1270 return;
1271 }
1272
011cf577
BW		 1273 kref_init(&error->ref);
1274
48b031e3 1275 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1276 i915_capture_reg_state(dev_priv, error);
1277 i915_gem_capture_buffers(dev_priv, error);
1278 i915_gem_record_fences(dev, error);
1279 i915_gem_record_rings(dev, error);
1d762aad 1280
84734a04
MK		 1281 do_gettimeofday(&error->time);
1282
1283 error->overlay = intel_overlay_capture_error_state(dev);
1284 error->display = intel_display_capture_error_state(dev);
1285
58174462 1286 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1287 DRM_INFO("%s\n", error->error_msg);
1288
84734a04
MK		 1289 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1290 if (dev_priv->gpu_error.first_error == NULL) {
1291 dev_priv->gpu_error.first_error = error;
1292 error = NULL;
1293 }
1294 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1295
cb383002 1296 if (error) {
84734a04 1297 i915_error_state_free(&error->ref);
cb383002
MK		 1298 return;
1299 }
1300
1301 if (!warned) {
1302 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1303 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1304 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1305 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1306 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1307 warned = true;
1308 }
84734a04
MK		 1309}
1310
1311void i915_error_state_get(struct drm_device *dev,
1312 struct i915_error_state_file_priv *error_priv)
1313{
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315 unsigned long flags;
1316
1317 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1318 error_priv->error = dev_priv->gpu_error.first_error;
1319 if (error_priv->error)
1320 kref_get(&error_priv->error->ref);
1321 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1322
1323}
1324
1325void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1326{
1327 if (error_priv->error)
1328 kref_put(&error_priv->error->ref, i915_error_state_free);
1329}
1330
1331void i915_destroy_error_state(struct drm_device *dev)
1332{
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct drm_i915_error_state *error;
1335 unsigned long flags;
1336
1337 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1338 error = dev_priv->gpu_error.first_error;
1339 dev_priv->gpu_error.first_error = NULL;
1340 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1341
1342 if (error)
1343 kref_put(&error->ref, i915_error_state_free);
1344}
1345
1346const char *i915_cache_level_str(int type)
1347{
1348 switch (type) {
1349 case I915_CACHE_NONE: return " uncached";
350ec881
CW		 1350 case I915_CACHE_LLC: return " snooped or LLC";
1351 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1352 case I915_CACHE_WT: return " WT";
84734a04
MK		 1353 default: return "";
1354 }
1355}
1356
1357/* NB: please notice the memset */
1358void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1359{
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1362
1363 switch (INTEL_INFO(dev)->gen) {
1364 case 2:
1365 case 3:
1366 instdone[0] = I915_READ(INSTDONE);
1367 break;
1368 case 4:
1369 case 5:
1370 case 6:
1371 instdone[0] = I915_READ(INSTDONE_I965);
1372 instdone[1] = I915_READ(INSTDONE1);
1373 break;
1374 default:
1375 WARN_ONCE(1, "Unsupported platform\n");
1376 case 7:
d0582ed2 1377 case 8:
84734a04
MK		 1378 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1379 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1380 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1381 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1382 break;
1383 }
1384}
Linux kernel - Deliverables
This page took 0.238762 seconds and 5 git commands to generate.