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drm/i915: Use VMA as the primary object for context state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
6361f4ba 33static const char *engine_str(int engine)
84734a04 34{
6361f4ba 35 switch (engine) {
84734a04
MK		 36 case RCS: return "render";
37 case VCS: return "bsd";
38 case BCS: return "blt";
39 case VECS: return "vebox";
845f74a7 40 case VCS2: return "bsd2";
84734a04
MK		 41 default: return "";
42 }
43}
44
84734a04
MK		 45static const char *tiling_flag(int tiling)
46{
47 switch (tiling) {
48 default:
49 case I915_TILING_NONE: return "";
50 case I915_TILING_X: return " X";
51 case I915_TILING_Y: return " Y";
52 }
53}
54
55static const char *dirty_flag(int dirty)
56{
57 return dirty ? " dirty" : "";
58}
59
60static const char *purgeable_flag(int purgeable)
61{
62 return purgeable ? " purgeable" : "";
63}
64
65static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
66{
67
68 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
69 e->err = -ENOSPC;
70 return false;
71 }
72
73 if (e->bytes == e->size - 1 || e->err)
74 return false;
75
76 return true;
77}
78
79static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
80 unsigned len)
81{
82 if (e->pos + len <= e->start) {
83 e->pos += len;
84 return false;
85 }
86
87 /* First vsnprintf needs to fit in its entirety for memmove */
88 if (len >= e->size) {
89 e->err = -EIO;
90 return false;
91 }
92
93 return true;
94}
95
96static void __i915_error_advance(struct drm_i915_error_state_buf *e,
97 unsigned len)
98{
99 /* If this is first printf in this window, adjust it so that
100 * start position matches start of the buffer
101 */
102
103 if (e->pos < e->start) {
104 const size_t off = e->start - e->pos;
105
106 /* Should not happen but be paranoid */
107 if (off > len || e->bytes) {
108 e->err = -EIO;
109 return;
110 }
111
112 memmove(e->buf, e->buf + off, len - off);
113 e->bytes = len - off;
114 e->pos = e->start;
115 return;
116 }
117
118 e->bytes += len;
119 e->pos += len;
120}
121
122static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
123 const char *f, va_list args)
124{
125 unsigned len;
126
127 if (!__i915_error_ok(e))
128 return;
129
130 /* Seek the first printf which is hits start position */
131 if (e->pos < e->start) {
e29bb4eb
CW		 132 va_list tmp;
133
134 va_copy(tmp, args);
1d2cb9a5
MK		 135 len = vsnprintf(NULL, 0, f, tmp);
136 va_end(tmp);
137
138 if (!__i915_error_seek(e, len))
84734a04
MK		 139 return;
140 }
141
142 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
143 if (len >= e->size - e->bytes)
144 len = e->size - e->bytes - 1;
145
146 __i915_error_advance(e, len);
147}
148
149static void i915_error_puts(struct drm_i915_error_state_buf *e,
150 const char *str)
151{
152 unsigned len;
153
154 if (!__i915_error_ok(e))
155 return;
156
157 len = strlen(str);
158
159 /* Seek the first printf which is hits start position */
160 if (e->pos < e->start) {
161 if (!__i915_error_seek(e, len))
162 return;
163 }
164
165 if (len >= e->size - e->bytes)
166 len = e->size - e->bytes - 1;
167 memcpy(e->buf + e->bytes, str, len);
168
169 __i915_error_advance(e, len);
170}
171
172#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
173#define err_puts(e, s) i915_error_puts(e, s)
174
175static void print_error_buffers(struct drm_i915_error_state_buf *m,
176 const char *name,
177 struct drm_i915_error_buffer *err,
178 int count)
179{
b4716185
CW		 180 int i;
181
c0ce4663 182 err_printf(m, "%s [%d]:\n", name, count);
84734a04
MK		 183
184 while (count--) {
e1f12325
MT		 185 err_printf(m, " %08x_%08x %8u %02x %02x [ ",
186 upper_32_bits(err->gtt_offset),
187 lower_32_bits(err->gtt_offset),
84734a04
MK		 188 err->size,
189 err->read_domains,
b4716185 190 err->write_domain);
666796da 191 for (i = 0; i < I915_NUM_ENGINES; i++)
b4716185
CW		 192 err_printf(m, "%02x ", err->rseqno[i]);
193
194 err_printf(m, "] %02x", err->wseqno);
84734a04
MK		 195 err_puts(m, tiling_flag(err->tiling));
196 err_puts(m, dirty_flag(err->dirty));
197 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 198 err_puts(m, err->userptr ? " userptr" : "");
6361f4ba
CW		 199 err_puts(m, err->engine != -1 ? " " : "");
200 err_puts(m, engine_str(err->engine));
0a4cd7c8 201 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
84734a04
MK		 202
203 if (err->name)
204 err_printf(m, " (name: %d)", err->name);
205 if (err->fence_reg != I915_FENCE_REG_NONE)
206 err_printf(m, " (fence: %d)", err->fence_reg);
207
208 err_puts(m, "\n");
209 err++;
210 }
211}
212
7e37f889 213static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
da661464
MK		 214{
215 switch (a) {
216 case HANGCHECK_IDLE:
217 return "idle";
218 case HANGCHECK_WAIT:
219 return "wait";
220 case HANGCHECK_ACTIVE:
221 return "active";
222 case HANGCHECK_KICK:
223 return "kick";
224 case HANGCHECK_HUNG:
225 return "hung";
226 }
227
228 return "unknown";
229}
230
6361f4ba
CW		 231static void error_print_engine(struct drm_i915_error_state_buf *m,
232 struct drm_i915_error_engine *ee)
84734a04 233{
6361f4ba
CW		 234 err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
235 err_printf(m, " START: 0x%08x\n", ee->start);
236 err_printf(m, " HEAD: 0x%08x\n", ee->head);
237 err_printf(m, " TAIL: 0x%08x\n", ee->tail);
238 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
239 err_printf(m, " HWS: 0x%08x\n", ee->hws);
240 err_printf(m, " ACTHD: 0x%08x %08x\n",
241 (u32)(ee->acthd>>32), (u32)ee->acthd);
242 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
243 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
244 err_printf(m, " INSTDONE: 0x%08x\n", ee->instdone);
245 if (INTEL_GEN(m->i915) >= 4) {
246 err_printf(m, " BBADDR: 0x%08x %08x\n",
247 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
248 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
249 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
3dda20a9 250 }
6361f4ba
CW		 251 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
252 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
253 lower_32_bits(ee->faddr));
254 if (INTEL_GEN(m->i915) >= 6) {
255 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
256 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
84734a04 257 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 258 ee->semaphore_mboxes[0],
259 ee->semaphore_seqno[0]);
84734a04 260 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 261 ee->semaphore_mboxes[1],
262 ee->semaphore_seqno[1]);
263 if (HAS_VEBOX(m->i915)) {
4e5aabfd 264 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
6361f4ba
CW		 265 ee->semaphore_mboxes[2],
266 ee->semaphore_seqno[2]);
4e5aabfd 267 }
84734a04 268 }
6361f4ba
CW		 269 if (USES_PPGTT(m->i915)) {
270 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
6c7a01ec 271
6361f4ba 272 if (INTEL_GEN(m->i915) >= 8) {
6c7a01ec
BW		 273 int i;
274 for (i = 0; i < 4; i++)
275 err_printf(m, " PDP%d: 0x%016llx\n",
6361f4ba 276 i, ee->vm_info.pdp[i]);
6c7a01ec
BW		 277 } else {
278 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
6361f4ba 279 ee->vm_info.pp_dir_base);
6c7a01ec
BW		 280 }
281 }
6361f4ba
CW		 282 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
283 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
284 err_printf(m, " waiting: %s\n", yesno(ee->waiting));
285 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
286 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
da661464 287 err_printf(m, " hangcheck: %s [%d]\n",
6361f4ba
CW		 288 hangcheck_action_to_str(ee->hangcheck_action),
289 ee->hangcheck_score);
84734a04
MK		 290}
291
292void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
293{
294 va_list args;
295
296 va_start(args, f);
297 i915_error_vprintf(e, f, args);
298 va_end(args);
299}
300
ab0e7ff9
CW		 301static void print_error_obj(struct drm_i915_error_state_buf *m,
302 struct drm_i915_error_object *obj)
303{
304 int page, offset, elt;
305
306 for (page = offset = 0; page < obj->page_count; page++) {
307 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
308 err_printf(m, "%08x : %08x\n", offset,
309 obj->pages[page][elt]);
310 offset += 4;
311 }
312 }
313}
314
2bd160a1
CW		 315static void err_print_capabilities(struct drm_i915_error_state_buf *m,
316 const struct intel_device_info *info)
317{
318#define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
319#define SEP_SEMICOLON ;
320 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
321#undef PRINT_FLAG
322#undef SEP_SEMICOLON
323}
324
84734a04
MK		 325int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
326 const struct i915_error_state_file_priv *error_priv)
327{
328 struct drm_device *dev = error_priv->dev;
fac5e23e 329 struct drm_i915_private *dev_priv = to_i915(dev);
84734a04 330 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 331 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 332 int i, j, offset, elt;
333 int max_hangcheck_score;
84734a04
MK		 334
335 if (!error) {
336 err_printf(m, "no error state collected\n");
337 goto out;
338 }
339
cb383002 340 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 341 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
342 error->time.tv_usec);
343 err_printf(m, "Kernel: " UTS_RELEASE "\n");
2bd160a1 344 err_print_capabilities(m, &error->device_info);
ab0e7ff9 345 max_hangcheck_score = 0;
6361f4ba
CW		 346 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
347 if (error->engine[i].hangcheck_score > max_hangcheck_score)
348 max_hangcheck_score = error->engine[i].hangcheck_score;
ab0e7ff9 349 }
6361f4ba
CW		 350 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
351 if (error->engine[i].hangcheck_score == max_hangcheck_score &&
352 error->engine[i].pid != -1) {
ab0e7ff9 353 err_printf(m, "Active process (on ring %s): %s [%d]\n",
6361f4ba
CW		 354 engine_str(i),
355 error->engine[i].comm,
356 error->engine[i].pid);
ab0e7ff9
CW		 357 }
358 }
48b031e3 359 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 360 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 361 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
06e6ff8f
AS		 362 err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
363 err_printf(m, "PCI Subsystem: %04x:%04x\n",
364 dev->pdev->subsystem_vendor,
365 dev->pdev->subsystem_device);
eb5be9d0 366 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
0ac7655c
MK		 367
368 if (HAS_CSR(dev)) {
369 struct intel_csr *csr = &dev_priv->csr;
370
371 err_printf(m, "DMC loaded: %s\n",
372 yesno(csr->dmc_payload != NULL));
373 err_printf(m, "DMC fw version: %d.%d\n",
374 CSR_VERSION_MAJOR(csr->version),
375 CSR_VERSION_MINOR(csr->version));
376 }
377
84734a04
MK		 378 err_printf(m, "EIR: 0x%08x\n", error->eir);
379 err_printf(m, "IER: 0x%08x\n", error->ier);
885ea5a8
RV		 380 if (INTEL_INFO(dev)->gen >= 8) {
381 for (i = 0; i < 4; i++)
382 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
383 error->gtier[i]);
384 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
385 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
84734a04
MK		 386 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
387 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
388 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
389 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 390 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 391
392 for (i = 0; i < dev_priv->num_fence_regs; i++)
393 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
394
395 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
396 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
397 error->extra_instdone[i]);
398
399 if (INTEL_INFO(dev)->gen >= 6) {
400 err_printf(m, "ERROR: 0x%08x\n", error->error);
6c826f34
MK		 401
402 if (INTEL_INFO(dev)->gen >= 8)
403 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
404 error->fault_data1, error->fault_data0);
405
84734a04
MK		 406 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
407 }
408
7e22dbbb 409 if (IS_GEN7(dev))
84734a04
MK		 410 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
411
6361f4ba
CW		 412 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
413 if (error->engine[i].engine_id != -1)
414 error_print_engine(m, &error->engine[i]);
415 }
84734a04 416
c0ce4663
CW		 417 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
418 char buf[128];
419 int len, first = 1;
3a448734 420
c0ce4663
CW		 421 if (!error->active_vm[i])
422 break;
423
424 len = scnprintf(buf, sizeof(buf), "Active (");
425 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
426 if (error->engine[j].vm != error->active_vm[i])
427 continue;
428
429 len += scnprintf(buf + len, sizeof(buf), "%s%s",
430 first ? "" : ", ",
431 dev_priv->engine[j].name);
432 first = 0;
433 }
434 scnprintf(buf + len, sizeof(buf), ")");
435 print_error_buffers(m, buf,
3a448734
CW		 436 error->active_bo[i],
437 error->active_bo_count[i]);
3a448734 438 }
84734a04 439
c0ce4663
CW		 440 print_error_buffers(m, "Pinned (global)",
441 error->pinned_bo,
442 error->pinned_bo_count);
443
6361f4ba
CW		 444 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
445 struct drm_i915_error_engine *ee = &error->engine[i];
446
447 obj = ee->batchbuffer;
ab0e7ff9 448 if (obj) {
4a570db5 449 err_puts(m, dev_priv->engine[i].name);
6361f4ba 450 if (ee->pid != -1)
ab0e7ff9 451 err_printf(m, " (submitted by %s [%d])",
6361f4ba
CW		 452 ee->comm,
453 ee->pid);
e1f12325
MT		 454 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
455 upper_32_bits(obj->gtt_offset),
456 lower_32_bits(obj->gtt_offset));
ab0e7ff9
CW		 457 print_error_obj(m, obj);
458 }
459
6361f4ba 460 obj = ee->wa_batchbuffer;
ab0e7ff9
CW		 461 if (obj) {
462 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
4a570db5 463 dev_priv->engine[i].name,
e1f12325 464 lower_32_bits(obj->gtt_offset));
ab0e7ff9 465 print_error_obj(m, obj);
84734a04
MK		 466 }
467
6361f4ba 468 if (ee->num_requests) {
84734a04 469 err_printf(m, "%s --- %d requests\n",
4a570db5 470 dev_priv->engine[i].name,
6361f4ba
CW		 471 ee->num_requests);
472 for (j = 0; j < ee->num_requests; j++) {
d045446d 473 err_printf(m, " seqno 0x%08x, emitted %ld, head 0x%08x, tail 0x%08x\n",
6361f4ba
CW		 474 ee->requests[j].seqno,
475 ee->requests[j].jiffies,
d045446d 476 ee->requests[j].head,
6361f4ba 477 ee->requests[j].tail);
84734a04
MK		 478 }
479 }
480
6361f4ba 481 if (ee->num_waiters) {
688e6c72
CW		 482 err_printf(m, "%s --- %d waiters\n",
483 dev_priv->engine[i].name,
6361f4ba
CW		 484 ee->num_waiters);
485 for (j = 0; j < ee->num_waiters; j++) {
688e6c72 486 err_printf(m, " seqno 0x%08x for %s [%d]\n",
6361f4ba
CW		 487 ee->waiters[j].seqno,
488 ee->waiters[j].comm,
489 ee->waiters[j].pid);
688e6c72
CW		 490 }
491 }
492
6361f4ba 493 if ((obj = ee->ringbuffer)) {
84734a04 494 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
4a570db5 495 dev_priv->engine[i].name,
e1f12325 496 lower_32_bits(obj->gtt_offset));
ab0e7ff9 497 print_error_obj(m, obj);
84734a04
MK		 498 }
499
6361f4ba 500 if ((obj = ee->hws_page)) {
3a5a0393
JB		 501 u64 hws_offset = obj->gtt_offset;
502 u32 *hws_page = &obj->pages[0][0];
503
504 if (i915.enable_execlists) {
505 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
506 hws_page = &obj->pages[LRC_PPHWSP_PN][0];
507 }
d1675198 508 err_printf(m, "%s --- HW Status = 0x%08llx\n",
4a570db5 509 dev_priv->engine[i].name, hws_offset);
f3ce3821
CW		 510 offset = 0;
511 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
512 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
513 offset,
3a5a0393
JB		 514 hws_page[elt],
515 hws_page[elt+1],
516 hws_page[elt+2],
517 hws_page[elt+3]);
a98b7e58 518 offset += 16;
f3ce3821
CW		 519 }
520 }
521
6361f4ba 522 obj = ee->wa_ctx;
f85db059 523 if (obj) {
524 u64 wa_ctx_offset = obj->gtt_offset;
525 u32 *wa_ctx_page = &obj->pages[0][0];
4a570db5 526 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
e2f80391
TU		 527 u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
528 engine->wa_ctx.per_ctx.size);
f85db059 529
530 err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
4a570db5 531 dev_priv->engine[i].name, wa_ctx_offset);
f85db059 532 offset = 0;
533 for (elt = 0; elt < wa_ctx_size; elt += 4) {
534 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
535 offset,
536 wa_ctx_page[elt + 0],
537 wa_ctx_page[elt + 1],
538 wa_ctx_page[elt + 2],
539 wa_ctx_page[elt + 3]);
540 offset += 16;
541 }
542 }
543
6361f4ba 544 if ((obj = ee->ctx)) {
84734a04 545 err_printf(m, "%s --- HW Context = 0x%08x\n",
4a570db5 546 dev_priv->engine[i].name,
e1f12325 547 lower_32_bits(obj->gtt_offset));
17d36749 548 print_error_obj(m, obj);
84734a04
MK		 549 }
550 }
551
0ca36d78 552 if ((obj = error->semaphore_obj)) {
e1f12325
MT		 553 err_printf(m, "Semaphore page = 0x%08x\n",
554 lower_32_bits(obj->gtt_offset));
0ca36d78
BW		 555 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
556 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
557 elt * 4,
558 obj->pages[0][elt],
559 obj->pages[0][elt+1],
560 obj->pages[0][elt+2],
561 obj->pages[0][elt+3]);
562 }
563 }
564
84734a04
MK		 565 if (error->overlay)
566 intel_overlay_print_error_state(m, error->overlay);
567
568 if (error->display)
569 intel_display_print_error_state(m, dev, error->display);
570
571out:
572 if (m->bytes == 0 && m->err)
573 return m->err;
574
575 return 0;
576}
577
578int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
0a4cd7c8 579 struct drm_i915_private *i915,
84734a04
MK		 580 size_t count, loff_t pos)
581{
582 memset(ebuf, 0, sizeof(*ebuf));
0a4cd7c8 583 ebuf->i915 = i915;
84734a04
MK		 584
585 /* We need to have enough room to store any i915_error_state printf
586 * so that we can move it to start position.
587 */
588 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
589 ebuf->buf = kmalloc(ebuf->size,
590 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
591
592 if (ebuf->buf == NULL) {
593 ebuf->size = PAGE_SIZE;
594 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
595 }
596
597 if (ebuf->buf == NULL) {
598 ebuf->size = 128;
599 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
600 }
601
602 if (ebuf->buf == NULL)
603 return -ENOMEM;
604
605 ebuf->start = pos;
606
607 return 0;
608}
609
610static void i915_error_object_free(struct drm_i915_error_object *obj)
611{
612 int page;
613
614 if (obj == NULL)
615 return;
616
617 for (page = 0; page < obj->page_count; page++)
618 kfree(obj->pages[page]);
619
620 kfree(obj);
621}
622
623static void i915_error_state_free(struct kref *error_ref)
624{
625 struct drm_i915_error_state *error = container_of(error_ref,
626 typeof(*error), ref);
627 int i;
628
6361f4ba
CW		 629 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
630 struct drm_i915_error_engine *ee = &error->engine[i];
631
632 i915_error_object_free(ee->batchbuffer);
633 i915_error_object_free(ee->wa_batchbuffer);
634 i915_error_object_free(ee->ringbuffer);
635 i915_error_object_free(ee->hws_page);
636 i915_error_object_free(ee->ctx);
637 i915_error_object_free(ee->wa_ctx);
638
639 kfree(ee->requests);
640 kfree(ee->waiters);
84734a04
MK		 641 }
642
0ca36d78 643 i915_error_object_free(error->semaphore_obj);
0b37a9a9 644
c0ce4663 645 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
0b37a9a9 646 kfree(error->active_bo[i]);
0b37a9a9 647 kfree(error->pinned_bo);
c0ce4663 648
84734a04
MK		 649 kfree(error->overlay);
650 kfree(error->display);
651 kfree(error);
652}
653
654static struct drm_i915_error_object *
8ae62dc6
CW		 655i915_error_object_create(struct drm_i915_private *dev_priv,
656 struct drm_i915_gem_object *src,
657 struct i915_address_space *vm)
84734a04 658{
72e96d64 659 struct i915_ggtt *ggtt = &dev_priv->ggtt;
84734a04 660 struct drm_i915_error_object *dst;
aff43766 661 struct i915_vma *vma = NULL;
8ae62dc6 662 int num_pages;
b3c3f5e6
CW		 663 bool use_ggtt;
664 int i = 0;
e1f12325 665 u64 reloc_offset;
84734a04
MK		 666
667 if (src == NULL || src->pages == NULL)
668 return NULL;
669
8ae62dc6
CW		 670 num_pages = src->base.size >> PAGE_SHIFT;
671
84734a04
MK		 672 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
673 if (dst == NULL)
674 return NULL;
675
87a01e82
CW		 676 if (i915_gem_obj_bound(src, vm))
677 dst->gtt_offset = i915_gem_obj_offset(src, vm);
678 else
679 dst->gtt_offset = -1;
b3c3f5e6
CW		 680
681 reloc_offset = dst->gtt_offset;
aff43766
TU		 682 if (i915_is_ggtt(vm))
683 vma = i915_gem_obj_to_ggtt(src);
b3c3f5e6 684 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
3272db53 685 vma && (vma->flags & I915_VMA_GLOBAL_BIND) &&
72e96d64 686 reloc_offset + num_pages * PAGE_SIZE <= ggtt->mappable_end);
b3c3f5e6
CW		 687
688 /* Cannot access stolen address directly, try to use the aperture */
689 if (src->stolen) {
690 use_ggtt = true;
691
3272db53 692 if (!(vma && vma->flags & I915_VMA_GLOBAL_BIND))
b3c3f5e6
CW		 693 goto unwind;
694
695 reloc_offset = i915_gem_obj_ggtt_offset(src);
72e96d64 696 if (reloc_offset + num_pages * PAGE_SIZE > ggtt->mappable_end)
b3c3f5e6
CW		 697 goto unwind;
698 }
699
700 /* Cannot access snooped pages through the aperture */
2d1fe073
JL		 701 if (use_ggtt && src->cache_level != I915_CACHE_NONE &&
702 !HAS_LLC(dev_priv))
b3c3f5e6
CW		 703 goto unwind;
704
705 dst->page_count = num_pages;
706 while (num_pages--) {
84734a04
MK		 707 unsigned long flags;
708 void *d;
709
710 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
711 if (d == NULL)
712 goto unwind;
713
714 local_irq_save(flags);
b3c3f5e6 715 if (use_ggtt) {
84734a04
MK		 716 void __iomem *s;
717
718 /* Simply ignore tiling or any overlapping fence.
719 * It's part of the error state, and this hopefully
720 * captures what the GPU read.
721 */
722
72e96d64 723 s = io_mapping_map_atomic_wc(ggtt->mappable,
84734a04
MK		 724 reloc_offset);
725 memcpy_fromio(d, s, PAGE_SIZE);
726 io_mapping_unmap_atomic(s);
84734a04
MK		 727 } else {
728 struct page *page;
729 void *s;
730
731 page = i915_gem_object_get_page(src, i);
732
733 drm_clflush_pages(&page, 1);
734
735 s = kmap_atomic(page);
736 memcpy(d, s, PAGE_SIZE);
737 kunmap_atomic(s);
738
739 drm_clflush_pages(&page, 1);
740 }
741 local_irq_restore(flags);
742
b3c3f5e6 743 dst->pages[i++] = d;
84734a04
MK		 744 reloc_offset += PAGE_SIZE;
745 }
84734a04
MK		 746
747 return dst;
748
749unwind:
750 while (i--)
751 kfree(dst->pages[i]);
752 kfree(dst);
753 return NULL;
754}
a7b91078 755#define i915_error_ggtt_object_create(dev_priv, src) \
62106b4f 756 i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
84734a04 757
d72d908b
CW		 758/* The error capture is special as tries to run underneath the normal
759 * locking rules - so we use the raw version of the i915_gem_active lookup.
760 */
761static inline uint32_t
762__active_get_seqno(struct i915_gem_active *active)
763{
764 return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
765}
766
767static inline int
768__active_get_engine_id(struct i915_gem_active *active)
769{
770 struct intel_engine_cs *engine;
771
772 engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
773 return engine ? engine->id : -1;
774}
775
84734a04 776static void capture_bo(struct drm_i915_error_buffer *err,
3a448734 777 struct i915_vma *vma)
84734a04 778{
3a448734 779 struct drm_i915_gem_object *obj = vma->obj;
b4716185 780 int i;
3a448734 781
84734a04
MK		 782 err->size = obj->base.size;
783 err->name = obj->base.name;
d72d908b 784
666796da 785 for (i = 0; i < I915_NUM_ENGINES; i++)
d72d908b
CW		 786 err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
787 err->wseqno = __active_get_seqno(&obj->last_write);
788 err->engine = __active_get_engine_id(&obj->last_write);
789
3a448734 790 err->gtt_offset = vma->node.start;
84734a04
MK		 791 err->read_domains = obj->base.read_domains;
792 err->write_domain = obj->base.write_domain;
793 err->fence_reg = obj->fence_reg;
3e510a8e 794 err->tiling = i915_gem_object_get_tiling(obj);
84734a04
MK		 795 err->dirty = obj->dirty;
796 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 797 err->userptr = obj->userptr.mm != NULL;
84734a04
MK		 798 err->cache_level = obj->cache_level;
799}
800
c0ce4663
CW		 801static u32 capture_error_bo(struct drm_i915_error_buffer *err,
802 int count, struct list_head *head,
803 bool pinned_only)
84734a04 804{
ca191b13 805 struct i915_vma *vma;
84734a04
MK		 806 int i = 0;
807
1c7f4bca 808 list_for_each_entry(vma, head, vm_link) {
c0ce4663
CW		 809 if (pinned_only && !i915_vma_is_pinned(vma))
810 continue;
811
3a448734 812 capture_bo(err++, vma);
84734a04
MK		 813 if (++i == count)
814 break;
815 }
816
817 return i;
818}
819
011cf577
BW		 820/* Generate a semi-unique error code. The code is not meant to have meaning, The
821 * code's only purpose is to try to prevent false duplicated bug reports by
822 * grossly estimating a GPU error state.
823 *
824 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
825 * the hang if we could strip the GTT offset information from it.
826 *
827 * It's only a small step better than a random number in its current form.
828 */
829static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002 830 struct drm_i915_error_state *error,
6361f4ba 831 int *engine_id)
011cf577
BW		 832{
833 uint32_t error_code = 0;
834 int i;
835
836 /* IPEHR would be an ideal way to detect errors, as it's the gross
837 * measure of "the command that hung." However, has some very common
838 * synchronization commands which almost always appear in the case
839 * strictly a client bug. Use instdone to differentiate those some.
840 */
666796da 841 for (i = 0; i < I915_NUM_ENGINES; i++) {
6361f4ba
CW		 842 if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
843 if (engine_id)
844 *engine_id = i;
cb383002 845
6361f4ba 846 return error->engine[i].ipehr ^ error->engine[i].instdone;
cb383002
MK		 847 }
848 }
011cf577
BW		 849
850 return error_code;
851}
852
c033666a 853static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
84734a04
MK		 854 struct drm_i915_error_state *error)
855{
84734a04
MK		 856 int i;
857
c033666a 858 if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
ce38ab05 859 for (i = 0; i < dev_priv->num_fence_regs; i++)
eecf613a 860 error->fence[i] = I915_READ(FENCE_REG(i));
c033666a 861 } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
eecf613a
VS		 862 for (i = 0; i < dev_priv->num_fence_regs; i++)
863 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
c033666a 864 } else if (INTEL_GEN(dev_priv) >= 6) {
eecf613a
VS		 865 for (i = 0; i < dev_priv->num_fence_regs; i++)
866 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
867 }
84734a04
MK		 868}
869
87f85ebc 870
6361f4ba 871static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
0bc40be8 872 struct intel_engine_cs *engine,
6361f4ba 873 struct drm_i915_error_engine *ee)
0ca36d78 874{
6361f4ba 875 struct drm_i915_private *dev_priv = engine->i915;
b4558b46 876 struct intel_engine_cs *to;
c3232b18 877 enum intel_engine_id id;
0ca36d78 878
0ca36d78 879 if (!error->semaphore_obj)
6361f4ba 880 return;
0ca36d78 881
c3232b18 882 for_each_engine_id(to, dev_priv, id) {
b4558b46
RV		 883 int idx;
884 u16 signal_offset;
885 u32 *tmp;
0ca36d78 886
0bc40be8 887 if (engine == to)
b4558b46
RV		 888 continue;
889
6361f4ba
CW		 890 signal_offset =
891 (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
b4558b46 892 tmp = error->semaphore_obj->pages[0];
7e37f889 893 idx = intel_engine_sync_index(engine, to);
b4558b46 894
6361f4ba
CW		 895 ee->semaphore_mboxes[idx] = tmp[signal_offset];
896 ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
0ca36d78
BW		 897 }
898}
899
6361f4ba
CW		 900static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
901 struct drm_i915_error_engine *ee)
87f85ebc 902{
6361f4ba
CW		 903 struct drm_i915_private *dev_priv = engine->i915;
904
905 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
906 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
907 ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
908 ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
87f85ebc 909
2d1fe073 910 if (HAS_VEBOX(dev_priv)) {
6361f4ba 911 ee->semaphore_mboxes[2] =
0bc40be8 912 I915_READ(RING_SYNC_2(engine->mmio_base));
6361f4ba 913 ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
87f85ebc
BW		 914 }
915}
916
6361f4ba
CW		 917static void error_record_engine_waiters(struct intel_engine_cs *engine,
918 struct drm_i915_error_engine *ee)
688e6c72
CW		 919{
920 struct intel_breadcrumbs *b = &engine->breadcrumbs;
921 struct drm_i915_error_waiter *waiter;
922 struct rb_node *rb;
923 int count;
924
6361f4ba
CW		 925 ee->num_waiters = 0;
926 ee->waiters = NULL;
688e6c72
CW		 927
928 spin_lock(&b->lock);
929 count = 0;
930 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
931 count++;
932 spin_unlock(&b->lock);
933
934 waiter = NULL;
935 if (count)
936 waiter = kmalloc_array(count,
937 sizeof(struct drm_i915_error_waiter),
938 GFP_ATOMIC);
939 if (!waiter)
940 return;
941
6361f4ba 942 ee->waiters = waiter;
688e6c72
CW		 943
944 spin_lock(&b->lock);
945 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
946 struct intel_wait *w = container_of(rb, typeof(*w), node);
947
948 strcpy(waiter->comm, w->tsk->comm);
949 waiter->pid = w->tsk->pid;
950 waiter->seqno = w->seqno;
951 waiter++;
952
6361f4ba 953 if (++ee->num_waiters == count)
688e6c72
CW		 954 break;
955 }
956 spin_unlock(&b->lock);
957}
958
6361f4ba
CW		 959static void error_record_engine_registers(struct drm_i915_error_state *error,
960 struct intel_engine_cs *engine,
961 struct drm_i915_error_engine *ee)
84734a04 962{
6361f4ba
CW		 963 struct drm_i915_private *dev_priv = engine->i915;
964
c033666a 965 if (INTEL_GEN(dev_priv) >= 6) {
6361f4ba
CW		 966 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
967 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
c033666a 968 if (INTEL_GEN(dev_priv) >= 8)
6361f4ba 969 gen8_record_semaphore_state(error, engine, ee);
0ca36d78 970 else
6361f4ba 971 gen6_record_semaphore_state(engine, ee);
4e5aabfd
BW		 972 }
973
c033666a 974 if (INTEL_GEN(dev_priv) >= 4) {
6361f4ba
CW		 975 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
976 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
977 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
978 ee->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
979 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
980 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
c033666a 981 if (INTEL_GEN(dev_priv) >= 8) {
6361f4ba
CW		 982 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
983 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
13ffadd1 984 }
6361f4ba 985 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
84734a04 986 } else {
6361f4ba
CW		 987 ee->faddr = I915_READ(DMA_FADD_I8XX);
988 ee->ipeir = I915_READ(IPEIR);
989 ee->ipehr = I915_READ(IPEHR);
990 ee->instdone = I915_READ(GEN2_INSTDONE);
84734a04
MK		 991 }
992
6361f4ba
CW		 993 ee->waiting = intel_engine_has_waiter(engine);
994 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
7e37f889 995 ee->acthd = intel_engine_get_active_head(engine);
6361f4ba
CW		 996 ee->seqno = intel_engine_get_seqno(engine);
997 ee->last_seqno = engine->last_submitted_seqno;
998 ee->start = I915_READ_START(engine);
999 ee->head = I915_READ_HEAD(engine);
1000 ee->tail = I915_READ_TAIL(engine);
1001 ee->ctl = I915_READ_CTL(engine);
84734a04 1002
c033666a 1003 if (I915_NEED_GFX_HWS(dev_priv)) {
f0f59a00 1004 i915_reg_t mmio;
f3ce3821 1005
c033666a 1006 if (IS_GEN7(dev_priv)) {
0bc40be8 1007 switch (engine->id) {
f3ce3821
CW		 1008 default:
1009 case RCS:
1010 mmio = RENDER_HWS_PGA_GEN7;
1011 break;
1012 case BCS:
1013 mmio = BLT_HWS_PGA_GEN7;
1014 break;
1015 case VCS:
1016 mmio = BSD_HWS_PGA_GEN7;
1017 break;
1018 case VECS:
1019 mmio = VEBOX_HWS_PGA_GEN7;
1020 break;
1021 }
c033666a 1022 } else if (IS_GEN6(engine->i915)) {
0bc40be8 1023 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
f3ce3821
CW		 1024 } else {
1025 /* XXX: gen8 returns to sanity */
0bc40be8 1026 mmio = RING_HWS_PGA(engine->mmio_base);
f3ce3821
CW		 1027 }
1028
6361f4ba 1029 ee->hws = I915_READ(mmio);
f3ce3821
CW		 1030 }
1031
6361f4ba
CW		 1032 ee->hangcheck_score = engine->hangcheck.score;
1033 ee->hangcheck_action = engine->hangcheck.action;
6c7a01ec 1034
c033666a 1035 if (USES_PPGTT(dev_priv)) {
6c7a01ec
BW		 1036 int i;
1037
6361f4ba 1038 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
6c7a01ec 1039
c033666a 1040 if (IS_GEN6(dev_priv))
6361f4ba 1041 ee->vm_info.pp_dir_base =
0bc40be8 1042 I915_READ(RING_PP_DIR_BASE_READ(engine));
c033666a 1043 else if (IS_GEN7(dev_priv))
6361f4ba 1044 ee->vm_info.pp_dir_base =
0bc40be8 1045 I915_READ(RING_PP_DIR_BASE(engine));
c033666a 1046 else if (INTEL_GEN(dev_priv) >= 8)
6c7a01ec 1047 for (i = 0; i < 4; i++) {
6361f4ba 1048 ee->vm_info.pdp[i] =
0bc40be8 1049 I915_READ(GEN8_RING_PDP_UDW(engine, i));
6361f4ba
CW		 1050 ee->vm_info.pdp[i] <<= 32;
1051 ee->vm_info.pdp[i] |=
0bc40be8 1052 I915_READ(GEN8_RING_PDP_LDW(engine, i));
6c7a01ec 1053 }
6c7a01ec 1054 }
84734a04
MK		 1055}
1056
c033666a 1057static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
84734a04
MK		 1058 struct drm_i915_error_state *error)
1059{
72e96d64 1060 struct i915_ggtt *ggtt = &dev_priv->ggtt;
84734a04
MK		 1061 struct drm_i915_gem_request *request;
1062 int i, count;
1063
6361f4ba
CW		 1064 if (dev_priv->semaphore_obj) {
1065 error->semaphore_obj =
1066 i915_error_ggtt_object_create(dev_priv,
1067 dev_priv->semaphore_obj);
1068 }
1069
666796da 1070 for (i = 0; i < I915_NUM_ENGINES; i++) {
4a570db5 1071 struct intel_engine_cs *engine = &dev_priv->engine[i];
6361f4ba 1072 struct drm_i915_error_engine *ee = &error->engine[i];
372fbb8e 1073
6361f4ba
CW		 1074 ee->pid = -1;
1075 ee->engine_id = -1;
eee73b46 1076
c033666a 1077 if (!intel_engine_initialized(engine))
372fbb8e
CW		 1078 continue;
1079
6361f4ba 1080 ee->engine_id = i;
372fbb8e 1081
6361f4ba
CW		 1082 error_record_engine_registers(error, engine, ee);
1083 error_record_engine_waiters(engine, ee);
84734a04 1084
e2f80391 1085 request = i915_gem_find_active_request(engine);
ab0e7ff9 1086 if (request) {
7e37f889 1087 struct intel_ring *ring;
ae6c4806 1088
c0ce4663 1089 ee->vm = request->ctx->ppgtt ?
bc3d6744 1090 &request->ctx->ppgtt->base : &ggtt->base;
ae6c4806 1091
ab0e7ff9
CW		 1092 /* We need to copy these to an anonymous buffer
1093 * as the simplest method to avoid being overwritten
1094 * by userspace.
1095 */
6361f4ba 1096 ee->batchbuffer =
ab0e7ff9
CW		 1097 i915_error_object_create(dev_priv,
1098 request->batch_obj,
c0ce4663 1099 ee->vm);
ab0e7ff9 1100
2d1fe073 1101 if (HAS_BROKEN_CS_TLB(dev_priv))
6361f4ba 1102 ee->wa_batchbuffer =
ab0e7ff9 1103 i915_error_ggtt_object_create(dev_priv,
1dae2dfb 1104 engine->scratch.obj);
ab0e7ff9 1105
bf3783e5
CW		 1106 if (request->ctx->engine[i].state) {
1107 ee->ctx = i915_error_ggtt_object_create(dev_priv,
1108 request->ctx->engine[i].state->obj);
1109 }
546b1b6a 1110
071c92de 1111 if (request->pid) {
ab0e7ff9
CW		 1112 struct task_struct *task;
1113
1114 rcu_read_lock();
071c92de 1115 task = pid_task(request->pid, PIDTYPE_PID);
ab0e7ff9 1116 if (task) {
6361f4ba
CW		 1117 strcpy(ee->comm, task->comm);
1118 ee->pid = task->pid;
ab0e7ff9
CW		 1119 }
1120 rcu_read_unlock();
1121 }
84734a04 1122
bc3d6744
CW		 1123 error->simulated |=
1124 request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;
1125
1dae2dfb
CW		 1126 ring = request->ring;
1127 ee->cpu_ring_head = ring->head;
1128 ee->cpu_ring_tail = ring->tail;
6361f4ba 1129 ee->ringbuffer =
ba6e0418 1130 i915_error_ggtt_object_create(dev_priv,
1dae2dfb 1131 ring->obj);
ba6e0418 1132 }
84734a04 1133
6361f4ba 1134 ee->hws_page =
e2f80391
TU		 1135 i915_error_ggtt_object_create(dev_priv,
1136 engine->status_page.obj);
84734a04 1137
1dae2dfb
CW		 1138 ee->wa_ctx = i915_error_ggtt_object_create(dev_priv,
1139 engine->wa_ctx.obj);
f85db059 1140
84734a04 1141 count = 0;
efdf7c06 1142 list_for_each_entry(request, &engine->request_list, link)
84734a04
MK		 1143 count++;
1144
6361f4ba
CW		 1145 ee->num_requests = count;
1146 ee->requests =
1147 kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1148 if (!ee->requests) {
1149 ee->num_requests = 0;
84734a04
MK		 1150 continue;
1151 }
1152
1153 count = 0;
efdf7c06 1154 list_for_each_entry(request, &engine->request_list, link) {
84734a04
MK		 1155 struct drm_i915_error_request *erq;
1156
6361f4ba 1157 if (count >= ee->num_requests) {
9c8e1bdb
TE		 1158 /*
1159 * If the ring request list was changed in
1160 * between the point where the error request
1161 * list was created and dimensioned and this
1162 * point then just exit early to avoid crashes.
1163 *
1164 * We don't need to communicate that the
1165 * request list changed state during error
1166 * state capture and that the error state is
1167 * slightly incorrect as a consequence since we
1168 * are typically only interested in the request
1169 * list state at the point of error state
1170 * capture, not in any changes happening during
1171 * the capture.
1172 */
1173 break;
1174 }
1175
6361f4ba 1176 erq = &ee->requests[count++];
04769652 1177 erq->seqno = request->fence.seqno;
84734a04 1178 erq->jiffies = request->emitted_jiffies;
d045446d
CW		 1179 erq->head = request->head;
1180 erq->tail = request->tail;
84734a04
MK		 1181 }
1182 }
1183}
1184
95f5301d
BW		 1185static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1186 struct drm_i915_error_state *error,
1187 struct i915_address_space *vm,
c0ce4663 1188 int idx)
84734a04 1189{
c0ce4663 1190 struct drm_i915_error_buffer *active_bo;
95f5301d 1191 struct i915_vma *vma;
c0ce4663 1192 int count;
84734a04 1193
c0ce4663 1194 count = 0;
1c7f4bca 1195 list_for_each_entry(vma, &vm->active_list, vm_link)
c0ce4663 1196 count++;
84734a04 1197
c0ce4663
CW		 1198 active_bo = NULL;
1199 if (count)
1200 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
95f5301d 1201 if (active_bo)
c0ce4663
CW		 1202 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1203 else
1204 count = 0;
1205
1206 error->active_vm[idx] = vm;
1207 error->active_bo[idx] = active_bo;
1208 error->active_bo_count[idx] = count;
95f5301d
BW		 1209}
1210
c0ce4663
CW		 1211static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
1212 struct drm_i915_error_state *error)
95f5301d 1213{
c0ce4663
CW		 1214 int cnt = 0, i, j;
1215
1216 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1217 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1218 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1219
1220 /* Scan each engine looking for unique active contexts/vm */
1221 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1222 struct drm_i915_error_engine *ee = &error->engine[i];
1223 bool found;
1224
1225 if (!ee->vm)
1226 continue;
3a448734 1227
c0ce4663
CW		 1228 found = false;
1229 for (j = 0; j < i && !found; j++)
1230 found = error->engine[j].vm == ee->vm;
1231 if (!found)
1232 i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
3a448734 1233 }
84734a04
MK		 1234}
1235
c0ce4663
CW		 1236static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
1237 struct drm_i915_error_state *error)
1238{
1239 struct i915_address_space *vm = &dev_priv->ggtt.base;
1240 struct drm_i915_error_buffer *bo;
1241 struct i915_vma *vma;
1242 int count_inactive, count_active;
1243
1244 count_inactive = 0;
1245 list_for_each_entry(vma, &vm->active_list, vm_link)
1246 count_inactive++;
1247
1248 count_active = 0;
1249 list_for_each_entry(vma, &vm->inactive_list, vm_link)
1250 count_active++;
1251
1252 bo = NULL;
1253 if (count_inactive + count_active)
1254 bo = kcalloc(count_inactive + count_active,
1255 sizeof(*bo), GFP_ATOMIC);
1256 if (!bo)
1257 return;
1258
1259 count_inactive = capture_error_bo(bo, count_inactive,
1260 &vm->active_list, true);
1261 count_active = capture_error_bo(bo + count_inactive, count_active,
1262 &vm->inactive_list, true);
1263 error->pinned_bo_count = count_inactive + count_active;
1264 error->pinned_bo = bo;
1265}
1266
1d762aad
BW		 1267/* Capture all registers which don't fit into another category. */
1268static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1269 struct drm_i915_error_state *error)
84734a04 1270{
91c8a326 1271 struct drm_device *dev = &dev_priv->drm;
885ea5a8 1272 int i;
84734a04 1273
654c90c6
BW		 1274 /* General organization
1275 * 1. Registers specific to a single generation
1276 * 2. Registers which belong to multiple generations
1277 * 3. Feature specific registers.
1278 * 4. Everything else
1279 * Please try to follow the order.
1280 */
84734a04 1281
654c90c6
BW		 1282 /* 1: Registers specific to a single generation */
1283 if (IS_VALLEYVIEW(dev)) {
885ea5a8 1284 error->gtier[0] = I915_READ(GTIER);
843db716 1285 error->ier = I915_READ(VLV_IER);
40181697 1286 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
654c90c6 1287 }
84734a04 1288
654c90c6
BW		 1289 if (IS_GEN7(dev))
1290 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1291
6c826f34
MK		 1292 if (INTEL_INFO(dev)->gen >= 8) {
1293 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1294 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1295 }
1296
91ec5d11 1297 if (IS_GEN6(dev)) {
40181697 1298 error->forcewake = I915_READ_FW(FORCEWAKE);
91ec5d11
BW		 1299 error->gab_ctl = I915_READ(GAB_CTL);
1300 error->gfx_mode = I915_READ(GFX_MODE);
1301 }
84734a04 1302
654c90c6
BW		 1303 /* 2: Registers which belong to multiple generations */
1304 if (INTEL_INFO(dev)->gen >= 7)
40181697 1305 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
84734a04
MK		 1306
1307 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1308 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1309 error->error = I915_READ(ERROR_GEN6);
1310 error->done_reg = I915_READ(DONE_REG);
1311 }
1312
654c90c6 1313 /* 3: Feature specific registers */
91ec5d11
BW		 1314 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1315 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1316 error->gac_eco = I915_READ(GAC_ECO_BITS);
1317 }
1318
1319 /* 4: Everything else */
654c90c6
BW		 1320 if (HAS_HW_CONTEXTS(dev))
1321 error->ccid = I915_READ(CCID);
1322
885ea5a8
RV		 1323 if (INTEL_INFO(dev)->gen >= 8) {
1324 error->ier = I915_READ(GEN8_DE_MISC_IER);
1325 for (i = 0; i < 4; i++)
1326 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1327 } else if (HAS_PCH_SPLIT(dev)) {
843db716 1328 error->ier = I915_READ(DEIER);
885ea5a8 1329 error->gtier[0] = I915_READ(GTIER);
843db716
RV		 1330 } else if (IS_GEN2(dev)) {
1331 error->ier = I915_READ16(IER);
1332 } else if (!IS_VALLEYVIEW(dev)) {
1333 error->ier = I915_READ(IER);
654c90c6 1334 }
654c90c6
BW		 1335 error->eir = I915_READ(EIR);
1336 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04 1337
c033666a 1338 i915_get_extra_instdone(dev_priv, error->extra_instdone);
1d762aad
BW		 1339}
1340
c033666a 1341static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
58174462 1342 struct drm_i915_error_state *error,
14b730fc 1343 u32 engine_mask,
58174462 1344 const char *error_msg)
cb383002 1345{
cb383002 1346 u32 ecode;
6361f4ba 1347 int engine_id = -1, len;
cb383002 1348
6361f4ba 1349 ecode = i915_error_generate_code(dev_priv, error, &engine_id);
cb383002 1350
58174462 1351 len = scnprintf(error->error_msg, sizeof(error->error_msg),
0b5492d6 1352 "GPU HANG: ecode %d:%d:0x%08x",
6361f4ba 1353 INTEL_GEN(dev_priv), engine_id, ecode);
58174462 1354
6361f4ba 1355 if (engine_id != -1 && error->engine[engine_id].pid != -1)
58174462
MK		 1356 len += scnprintf(error->error_msg + len,
1357 sizeof(error->error_msg) - len,
1358 ", in %s [%d]",
6361f4ba
CW		 1359 error->engine[engine_id].comm,
1360 error->engine[engine_id].pid);
58174462
MK		 1361
1362 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1363 ", reason: %s, action: %s",
1364 error_msg,
14b730fc 1365 engine_mask ? "reset" : "continue");
cb383002
MK		 1366}
1367
48b031e3
MK		 1368static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1369 struct drm_i915_error_state *error)
1370{
eb5be9d0
CW		 1371 error->iommu = -1;
1372#ifdef CONFIG_INTEL_IOMMU
1373 error->iommu = intel_iommu_gfx_mapped;
1374#endif
48b031e3 1375 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1376 error->suspend_count = dev_priv->suspend_count;
2bd160a1
CW		 1377
1378 memcpy(&error->device_info,
1379 INTEL_INFO(dev_priv),
1380 sizeof(error->device_info));
48b031e3
MK		 1381}
1382
1d762aad
BW		 1383/**
1384 * i915_capture_error_state - capture an error record for later analysis
1385 * @dev: drm device
1386 *
1387 * Should be called when an error is detected (either a hang or an error
1388 * interrupt) to capture error state from the time of the error. Fills
1389 * out a structure which becomes available in debugfs for user level tools
1390 * to pick up.
1391 */
c033666a
CW		 1392void i915_capture_error_state(struct drm_i915_private *dev_priv,
1393 u32 engine_mask,
58174462 1394 const char *error_msg)
1d762aad 1395{
53a4c6b2 1396 static bool warned;
1d762aad
BW		 1397 struct drm_i915_error_state *error;
1398 unsigned long flags;
1d762aad 1399
9777cca0
CW		 1400 if (READ_ONCE(dev_priv->gpu_error.first_error))
1401 return;
1402
1d762aad
BW		 1403 /* Account for pipe specific data like PIPE*STAT */
1404 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1405 if (!error) {
1406 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1407 return;
1408 }
1409
011cf577
BW		 1410 kref_init(&error->ref);
1411
48b031e3 1412 i915_capture_gen_state(dev_priv, error);
011cf577 1413 i915_capture_reg_state(dev_priv, error);
c033666a
CW		 1414 i915_gem_record_fences(dev_priv, error);
1415 i915_gem_record_rings(dev_priv, error);
c0ce4663
CW		 1416 i915_capture_active_buffers(dev_priv, error);
1417 i915_capture_pinned_buffers(dev_priv, error);
1d762aad 1418
84734a04
MK		 1419 do_gettimeofday(&error->time);
1420
c033666a
CW		 1421 error->overlay = intel_overlay_capture_error_state(dev_priv);
1422 error->display = intel_display_capture_error_state(dev_priv);
84734a04 1423
c033666a 1424 i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
cb383002
MK		 1425 DRM_INFO("%s\n", error->error_msg);
1426
bc3d6744
CW		 1427 if (!error->simulated) {
1428 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1429 if (!dev_priv->gpu_error.first_error) {
1430 dev_priv->gpu_error.first_error = error;
1431 error = NULL;
1432 }
1433 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
84734a04 1434 }
84734a04 1435
cb383002 1436 if (error) {
84734a04 1437 i915_error_state_free(&error->ref);
cb383002
MK		 1438 return;
1439 }
1440
1441 if (!warned) {
1442 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1443 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1444 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1445 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
91c8a326
CW		 1446 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1447 dev_priv->drm.primary->index);
cb383002
MK		 1448 warned = true;
1449 }
84734a04
MK		 1450}
1451
1452void i915_error_state_get(struct drm_device *dev,
1453 struct i915_error_state_file_priv *error_priv)
1454{
fac5e23e 1455 struct drm_i915_private *dev_priv = to_i915(dev);
84734a04 1456
5b254c59 1457 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1458 error_priv->error = dev_priv->gpu_error.first_error;
1459 if (error_priv->error)
1460 kref_get(&error_priv->error->ref);
5b254c59 1461 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1462
1463}
1464
1465void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1466{
1467 if (error_priv->error)
1468 kref_put(&error_priv->error->ref, i915_error_state_free);
1469}
1470
1471void i915_destroy_error_state(struct drm_device *dev)
1472{
fac5e23e 1473 struct drm_i915_private *dev_priv = to_i915(dev);
84734a04 1474 struct drm_i915_error_state *error;
84734a04 1475
5b254c59 1476 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1477 error = dev_priv->gpu_error.first_error;
1478 dev_priv->gpu_error.first_error = NULL;
5b254c59 1479 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1480
1481 if (error)
1482 kref_put(&error->ref, i915_error_state_free);
1483}
1484
0a4cd7c8 1485const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
84734a04
MK		 1486{
1487 switch (type) {
1488 case I915_CACHE_NONE: return " uncached";
0a4cd7c8 1489 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
350ec881 1490 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1491 case I915_CACHE_WT: return " WT";
84734a04
MK		 1492 default: return "";
1493 }
1494}
1495
1496/* NB: please notice the memset */
c033666a
CW		 1497void i915_get_extra_instdone(struct drm_i915_private *dev_priv,
1498 uint32_t *instdone)
84734a04 1499{
84734a04
MK		 1500 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1501
c033666a 1502 if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
bd93a50e 1503 instdone[0] = I915_READ(GEN2_INSTDONE);
c033666a 1504 else if (IS_GEN4(dev_priv) || IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) {
f1d54348 1505 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
13d70b81 1506 instdone[1] = I915_READ(GEN4_INSTDONE1);
c033666a 1507 } else if (INTEL_GEN(dev_priv) >= 7) {
f1d54348 1508 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
84734a04
MK		 1509 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1510 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1511 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
84734a04
MK		 1512 }
1513}
Linux kernel - Deliverables
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