Commit | Line | Data |
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84734a04 MK |
1 | /* |
2 | * Copyright (c) 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * Mika Kuoppala <mika.kuoppala@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <generated/utsrelease.h> | |
31 | #include "i915_drv.h" | |
32 | ||
33 | static const char *yesno(int v) | |
34 | { | |
35 | return v ? "yes" : "no"; | |
36 | } | |
37 | ||
38 | static const char *ring_str(int ring) | |
39 | { | |
40 | switch (ring) { | |
41 | case RCS: return "render"; | |
42 | case VCS: return "bsd"; | |
43 | case BCS: return "blt"; | |
44 | case VECS: return "vebox"; | |
845f74a7 | 45 | case VCS2: return "bsd2"; |
84734a04 MK |
46 | default: return ""; |
47 | } | |
48 | } | |
49 | ||
50 | static const char *pin_flag(int pinned) | |
51 | { | |
52 | if (pinned > 0) | |
53 | return " P"; | |
54 | else if (pinned < 0) | |
55 | return " p"; | |
56 | else | |
57 | return ""; | |
58 | } | |
59 | ||
60 | static const char *tiling_flag(int tiling) | |
61 | { | |
62 | switch (tiling) { | |
63 | default: | |
64 | case I915_TILING_NONE: return ""; | |
65 | case I915_TILING_X: return " X"; | |
66 | case I915_TILING_Y: return " Y"; | |
67 | } | |
68 | } | |
69 | ||
70 | static const char *dirty_flag(int dirty) | |
71 | { | |
72 | return dirty ? " dirty" : ""; | |
73 | } | |
74 | ||
75 | static const char *purgeable_flag(int purgeable) | |
76 | { | |
77 | return purgeable ? " purgeable" : ""; | |
78 | } | |
79 | ||
80 | static bool __i915_error_ok(struct drm_i915_error_state_buf *e) | |
81 | { | |
82 | ||
83 | if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { | |
84 | e->err = -ENOSPC; | |
85 | return false; | |
86 | } | |
87 | ||
88 | if (e->bytes == e->size - 1 || e->err) | |
89 | return false; | |
90 | ||
91 | return true; | |
92 | } | |
93 | ||
94 | static bool __i915_error_seek(struct drm_i915_error_state_buf *e, | |
95 | unsigned len) | |
96 | { | |
97 | if (e->pos + len <= e->start) { | |
98 | e->pos += len; | |
99 | return false; | |
100 | } | |
101 | ||
102 | /* First vsnprintf needs to fit in its entirety for memmove */ | |
103 | if (len >= e->size) { | |
104 | e->err = -EIO; | |
105 | return false; | |
106 | } | |
107 | ||
108 | return true; | |
109 | } | |
110 | ||
111 | static void __i915_error_advance(struct drm_i915_error_state_buf *e, | |
112 | unsigned len) | |
113 | { | |
114 | /* If this is first printf in this window, adjust it so that | |
115 | * start position matches start of the buffer | |
116 | */ | |
117 | ||
118 | if (e->pos < e->start) { | |
119 | const size_t off = e->start - e->pos; | |
120 | ||
121 | /* Should not happen but be paranoid */ | |
122 | if (off > len || e->bytes) { | |
123 | e->err = -EIO; | |
124 | return; | |
125 | } | |
126 | ||
127 | memmove(e->buf, e->buf + off, len - off); | |
128 | e->bytes = len - off; | |
129 | e->pos = e->start; | |
130 | return; | |
131 | } | |
132 | ||
133 | e->bytes += len; | |
134 | e->pos += len; | |
135 | } | |
136 | ||
137 | static void i915_error_vprintf(struct drm_i915_error_state_buf *e, | |
138 | const char *f, va_list args) | |
139 | { | |
140 | unsigned len; | |
141 | ||
142 | if (!__i915_error_ok(e)) | |
143 | return; | |
144 | ||
145 | /* Seek the first printf which is hits start position */ | |
146 | if (e->pos < e->start) { | |
e29bb4eb CW |
147 | va_list tmp; |
148 | ||
149 | va_copy(tmp, args); | |
1d2cb9a5 MK |
150 | len = vsnprintf(NULL, 0, f, tmp); |
151 | va_end(tmp); | |
152 | ||
153 | if (!__i915_error_seek(e, len)) | |
84734a04 MK |
154 | return; |
155 | } | |
156 | ||
157 | len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); | |
158 | if (len >= e->size - e->bytes) | |
159 | len = e->size - e->bytes - 1; | |
160 | ||
161 | __i915_error_advance(e, len); | |
162 | } | |
163 | ||
164 | static void i915_error_puts(struct drm_i915_error_state_buf *e, | |
165 | const char *str) | |
166 | { | |
167 | unsigned len; | |
168 | ||
169 | if (!__i915_error_ok(e)) | |
170 | return; | |
171 | ||
172 | len = strlen(str); | |
173 | ||
174 | /* Seek the first printf which is hits start position */ | |
175 | if (e->pos < e->start) { | |
176 | if (!__i915_error_seek(e, len)) | |
177 | return; | |
178 | } | |
179 | ||
180 | if (len >= e->size - e->bytes) | |
181 | len = e->size - e->bytes - 1; | |
182 | memcpy(e->buf + e->bytes, str, len); | |
183 | ||
184 | __i915_error_advance(e, len); | |
185 | } | |
186 | ||
187 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) | |
188 | #define err_puts(e, s) i915_error_puts(e, s) | |
189 | ||
190 | static void print_error_buffers(struct drm_i915_error_state_buf *m, | |
191 | const char *name, | |
192 | struct drm_i915_error_buffer *err, | |
193 | int count) | |
194 | { | |
3a448734 | 195 | err_printf(m, " %s [%d]:\n", name, count); |
84734a04 MK |
196 | |
197 | while (count--) { | |
3a448734 | 198 | err_printf(m, " %08x %8u %02x %02x %x %x", |
84734a04 MK |
199 | err->gtt_offset, |
200 | err->size, | |
201 | err->read_domains, | |
202 | err->write_domain, | |
203 | err->rseqno, err->wseqno); | |
204 | err_puts(m, pin_flag(err->pinned)); | |
205 | err_puts(m, tiling_flag(err->tiling)); | |
206 | err_puts(m, dirty_flag(err->dirty)); | |
207 | err_puts(m, purgeable_flag(err->purgeable)); | |
5cc9ed4b | 208 | err_puts(m, err->userptr ? " userptr" : ""); |
84734a04 MK |
209 | err_puts(m, err->ring != -1 ? " " : ""); |
210 | err_puts(m, ring_str(err->ring)); | |
0a4cd7c8 | 211 | err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); |
84734a04 MK |
212 | |
213 | if (err->name) | |
214 | err_printf(m, " (name: %d)", err->name); | |
215 | if (err->fence_reg != I915_FENCE_REG_NONE) | |
216 | err_printf(m, " (fence: %d)", err->fence_reg); | |
217 | ||
218 | err_puts(m, "\n"); | |
219 | err++; | |
220 | } | |
221 | } | |
222 | ||
da661464 MK |
223 | static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) |
224 | { | |
225 | switch (a) { | |
226 | case HANGCHECK_IDLE: | |
227 | return "idle"; | |
228 | case HANGCHECK_WAIT: | |
229 | return "wait"; | |
230 | case HANGCHECK_ACTIVE: | |
231 | return "active"; | |
f260fe7b MK |
232 | case HANGCHECK_ACTIVE_LOOP: |
233 | return "active (loop)"; | |
da661464 MK |
234 | case HANGCHECK_KICK: |
235 | return "kick"; | |
236 | case HANGCHECK_HUNG: | |
237 | return "hung"; | |
238 | } | |
239 | ||
240 | return "unknown"; | |
241 | } | |
242 | ||
84734a04 MK |
243 | static void i915_ring_error_state(struct drm_i915_error_state_buf *m, |
244 | struct drm_device *dev, | |
77c1aa84 DV |
245 | struct drm_i915_error_state *error, |
246 | int ring_idx) | |
84734a04 | 247 | { |
77c1aa84 DV |
248 | struct drm_i915_error_ring *ring = &error->ring[ring_idx]; |
249 | ||
362b8af7 | 250 | if (!ring->valid) |
372fbb8e CW |
251 | return; |
252 | ||
77c1aa84 | 253 | err_printf(m, "%s command stream:\n", ring_str(ring_idx)); |
362b8af7 BW |
254 | err_printf(m, " HEAD: 0x%08x\n", ring->head); |
255 | err_printf(m, " TAIL: 0x%08x\n", ring->tail); | |
256 | err_printf(m, " CTL: 0x%08x\n", ring->ctl); | |
257 | err_printf(m, " HWS: 0x%08x\n", ring->hws); | |
e3243d16 | 258 | err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); |
362b8af7 BW |
259 | err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); |
260 | err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); | |
261 | err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); | |
3dda20a9 | 262 | if (INTEL_INFO(dev)->gen >= 4) { |
e3243d16 | 263 | err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); |
362b8af7 BW |
264 | err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); |
265 | err_printf(m, " INSTPS: 0x%08x\n", ring->instps); | |
3dda20a9 | 266 | } |
362b8af7 | 267 | err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); |
13ffadd1 BW |
268 | err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), |
269 | lower_32_bits(ring->faddr)); | |
84734a04 | 270 | if (INTEL_INFO(dev)->gen >= 6) { |
362b8af7 BW |
271 | err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); |
272 | err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); | |
84734a04 | 273 | err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
274 | ring->semaphore_mboxes[0], |
275 | ring->semaphore_seqno[0]); | |
84734a04 | 276 | err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", |
362b8af7 BW |
277 | ring->semaphore_mboxes[1], |
278 | ring->semaphore_seqno[1]); | |
4e5aabfd BW |
279 | if (HAS_VEBOX(dev)) { |
280 | err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", | |
362b8af7 BW |
281 | ring->semaphore_mboxes[2], |
282 | ring->semaphore_seqno[2]); | |
4e5aabfd | 283 | } |
84734a04 | 284 | } |
6c7a01ec BW |
285 | if (USES_PPGTT(dev)) { |
286 | err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); | |
287 | ||
288 | if (INTEL_INFO(dev)->gen >= 8) { | |
289 | int i; | |
290 | for (i = 0; i < 4; i++) | |
291 | err_printf(m, " PDP%d: 0x%016llx\n", | |
292 | i, ring->vm_info.pdp[i]); | |
293 | } else { | |
294 | err_printf(m, " PP_DIR_BASE: 0x%08x\n", | |
295 | ring->vm_info.pp_dir_base); | |
296 | } | |
297 | } | |
362b8af7 BW |
298 | err_printf(m, " seqno: 0x%08x\n", ring->seqno); |
299 | err_printf(m, " waiting: %s\n", yesno(ring->waiting)); | |
300 | err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); | |
301 | err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); | |
da661464 | 302 | err_printf(m, " hangcheck: %s [%d]\n", |
362b8af7 BW |
303 | hangcheck_action_to_str(ring->hangcheck_action), |
304 | ring->hangcheck_score); | |
84734a04 MK |
305 | } |
306 | ||
307 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) | |
308 | { | |
309 | va_list args; | |
310 | ||
311 | va_start(args, f); | |
312 | i915_error_vprintf(e, f, args); | |
313 | va_end(args); | |
314 | } | |
315 | ||
ab0e7ff9 CW |
316 | static void print_error_obj(struct drm_i915_error_state_buf *m, |
317 | struct drm_i915_error_object *obj) | |
318 | { | |
319 | int page, offset, elt; | |
320 | ||
321 | for (page = offset = 0; page < obj->page_count; page++) { | |
322 | for (elt = 0; elt < PAGE_SIZE/4; elt++) { | |
323 | err_printf(m, "%08x : %08x\n", offset, | |
324 | obj->pages[page][elt]); | |
325 | offset += 4; | |
326 | } | |
327 | } | |
328 | } | |
329 | ||
84734a04 MK |
330 | int i915_error_state_to_str(struct drm_i915_error_state_buf *m, |
331 | const struct i915_error_state_file_priv *error_priv) | |
332 | { | |
333 | struct drm_device *dev = error_priv->dev; | |
50227e1c | 334 | struct drm_i915_private *dev_priv = dev->dev_private; |
84734a04 | 335 | struct drm_i915_error_state *error = error_priv->error; |
0ca36d78 | 336 | struct drm_i915_error_object *obj; |
ab0e7ff9 CW |
337 | int i, j, offset, elt; |
338 | int max_hangcheck_score; | |
84734a04 MK |
339 | |
340 | if (!error) { | |
341 | err_printf(m, "no error state collected\n"); | |
342 | goto out; | |
343 | } | |
344 | ||
cb383002 | 345 | err_printf(m, "%s\n", error->error_msg); |
84734a04 MK |
346 | err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, |
347 | error->time.tv_usec); | |
348 | err_printf(m, "Kernel: " UTS_RELEASE "\n"); | |
ab0e7ff9 CW |
349 | max_hangcheck_score = 0; |
350 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
351 | if (error->ring[i].hangcheck_score > max_hangcheck_score) | |
352 | max_hangcheck_score = error->ring[i].hangcheck_score; | |
353 | } | |
354 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
355 | if (error->ring[i].hangcheck_score == max_hangcheck_score && | |
356 | error->ring[i].pid != -1) { | |
357 | err_printf(m, "Active process (on ring %s): %s [%d]\n", | |
358 | ring_str(i), | |
359 | error->ring[i].comm, | |
360 | error->ring[i].pid); | |
361 | } | |
362 | } | |
48b031e3 | 363 | err_printf(m, "Reset count: %u\n", error->reset_count); |
62d5d69b | 364 | err_printf(m, "Suspend count: %u\n", error->suspend_count); |
ffbab09b | 365 | err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); |
84734a04 MK |
366 | err_printf(m, "EIR: 0x%08x\n", error->eir); |
367 | err_printf(m, "IER: 0x%08x\n", error->ier); | |
885ea5a8 RV |
368 | if (INTEL_INFO(dev)->gen >= 8) { |
369 | for (i = 0; i < 4; i++) | |
370 | err_printf(m, "GTIER gt %d: 0x%08x\n", i, | |
371 | error->gtier[i]); | |
372 | } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) | |
373 | err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); | |
84734a04 MK |
374 | err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); |
375 | err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); | |
376 | err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); | |
377 | err_printf(m, "CCID: 0x%08x\n", error->ccid); | |
094f9a54 | 378 | err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); |
84734a04 MK |
379 | |
380 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
381 | err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); | |
382 | ||
383 | for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) | |
384 | err_printf(m, " INSTDONE_%d: 0x%08x\n", i, | |
385 | error->extra_instdone[i]); | |
386 | ||
387 | if (INTEL_INFO(dev)->gen >= 6) { | |
388 | err_printf(m, "ERROR: 0x%08x\n", error->error); | |
389 | err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); | |
390 | } | |
391 | ||
392 | if (INTEL_INFO(dev)->gen == 7) | |
393 | err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); | |
394 | ||
77c1aa84 DV |
395 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) |
396 | i915_ring_error_state(m, dev, error, i); | |
84734a04 | 397 | |
3a448734 CW |
398 | for (i = 0; i < error->vm_count; i++) { |
399 | err_printf(m, "vm[%d]\n", i); | |
400 | ||
84734a04 | 401 | print_error_buffers(m, "Active", |
3a448734 CW |
402 | error->active_bo[i], |
403 | error->active_bo_count[i]); | |
84734a04 | 404 | |
84734a04 | 405 | print_error_buffers(m, "Pinned", |
3a448734 CW |
406 | error->pinned_bo[i], |
407 | error->pinned_bo_count[i]); | |
408 | } | |
84734a04 MK |
409 | |
410 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
ab0e7ff9 CW |
411 | obj = error->ring[i].batchbuffer; |
412 | if (obj) { | |
413 | err_puts(m, dev_priv->ring[i].name); | |
414 | if (error->ring[i].pid != -1) | |
415 | err_printf(m, " (submitted by %s [%d])", | |
416 | error->ring[i].comm, | |
417 | error->ring[i].pid); | |
418 | err_printf(m, " --- gtt_offset = 0x%08x\n", | |
84734a04 | 419 | obj->gtt_offset); |
ab0e7ff9 CW |
420 | print_error_obj(m, obj); |
421 | } | |
422 | ||
423 | obj = error->ring[i].wa_batchbuffer; | |
424 | if (obj) { | |
425 | err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", | |
426 | dev_priv->ring[i].name, obj->gtt_offset); | |
427 | print_error_obj(m, obj); | |
84734a04 MK |
428 | } |
429 | ||
430 | if (error->ring[i].num_requests) { | |
431 | err_printf(m, "%s --- %d requests\n", | |
432 | dev_priv->ring[i].name, | |
433 | error->ring[i].num_requests); | |
434 | for (j = 0; j < error->ring[i].num_requests; j++) { | |
435 | err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", | |
436 | error->ring[i].requests[j].seqno, | |
437 | error->ring[i].requests[j].jiffies, | |
438 | error->ring[i].requests[j].tail); | |
439 | } | |
440 | } | |
441 | ||
442 | if ((obj = error->ring[i].ringbuffer)) { | |
443 | err_printf(m, "%s --- ringbuffer = 0x%08x\n", | |
444 | dev_priv->ring[i].name, | |
445 | obj->gtt_offset); | |
ab0e7ff9 | 446 | print_error_obj(m, obj); |
84734a04 MK |
447 | } |
448 | ||
362b8af7 | 449 | if ((obj = error->ring[i].hws_page)) { |
f3ce3821 CW |
450 | err_printf(m, "%s --- HW Status = 0x%08x\n", |
451 | dev_priv->ring[i].name, | |
452 | obj->gtt_offset); | |
453 | offset = 0; | |
454 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
455 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
456 | offset, | |
457 | obj->pages[0][elt], | |
458 | obj->pages[0][elt+1], | |
459 | obj->pages[0][elt+2], | |
460 | obj->pages[0][elt+3]); | |
461 | offset += 16; | |
462 | } | |
463 | } | |
464 | ||
372fbb8e | 465 | if ((obj = error->ring[i].ctx)) { |
84734a04 MK |
466 | err_printf(m, "%s --- HW Context = 0x%08x\n", |
467 | dev_priv->ring[i].name, | |
468 | obj->gtt_offset); | |
17d36749 | 469 | print_error_obj(m, obj); |
84734a04 MK |
470 | } |
471 | } | |
472 | ||
0ca36d78 BW |
473 | if ((obj = error->semaphore_obj)) { |
474 | err_printf(m, "Semaphore page = 0x%08x\n", obj->gtt_offset); | |
475 | for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { | |
476 | err_printf(m, "[%04x] %08x %08x %08x %08x\n", | |
477 | elt * 4, | |
478 | obj->pages[0][elt], | |
479 | obj->pages[0][elt+1], | |
480 | obj->pages[0][elt+2], | |
481 | obj->pages[0][elt+3]); | |
482 | } | |
483 | } | |
484 | ||
84734a04 MK |
485 | if (error->overlay) |
486 | intel_overlay_print_error_state(m, error->overlay); | |
487 | ||
488 | if (error->display) | |
489 | intel_display_print_error_state(m, dev, error->display); | |
490 | ||
491 | out: | |
492 | if (m->bytes == 0 && m->err) | |
493 | return m->err; | |
494 | ||
495 | return 0; | |
496 | } | |
497 | ||
498 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, | |
0a4cd7c8 | 499 | struct drm_i915_private *i915, |
84734a04 MK |
500 | size_t count, loff_t pos) |
501 | { | |
502 | memset(ebuf, 0, sizeof(*ebuf)); | |
0a4cd7c8 | 503 | ebuf->i915 = i915; |
84734a04 MK |
504 | |
505 | /* We need to have enough room to store any i915_error_state printf | |
506 | * so that we can move it to start position. | |
507 | */ | |
508 | ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; | |
509 | ebuf->buf = kmalloc(ebuf->size, | |
510 | GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); | |
511 | ||
512 | if (ebuf->buf == NULL) { | |
513 | ebuf->size = PAGE_SIZE; | |
514 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
515 | } | |
516 | ||
517 | if (ebuf->buf == NULL) { | |
518 | ebuf->size = 128; | |
519 | ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); | |
520 | } | |
521 | ||
522 | if (ebuf->buf == NULL) | |
523 | return -ENOMEM; | |
524 | ||
525 | ebuf->start = pos; | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | static void i915_error_object_free(struct drm_i915_error_object *obj) | |
531 | { | |
532 | int page; | |
533 | ||
534 | if (obj == NULL) | |
535 | return; | |
536 | ||
537 | for (page = 0; page < obj->page_count; page++) | |
538 | kfree(obj->pages[page]); | |
539 | ||
540 | kfree(obj); | |
541 | } | |
542 | ||
543 | static void i915_error_state_free(struct kref *error_ref) | |
544 | { | |
545 | struct drm_i915_error_state *error = container_of(error_ref, | |
546 | typeof(*error), ref); | |
547 | int i; | |
548 | ||
549 | for (i = 0; i < ARRAY_SIZE(error->ring); i++) { | |
550 | i915_error_object_free(error->ring[i].batchbuffer); | |
551 | i915_error_object_free(error->ring[i].ringbuffer); | |
362b8af7 | 552 | i915_error_object_free(error->ring[i].hws_page); |
84734a04 MK |
553 | i915_error_object_free(error->ring[i].ctx); |
554 | kfree(error->ring[i].requests); | |
555 | } | |
556 | ||
0ca36d78 | 557 | i915_error_object_free(error->semaphore_obj); |
84734a04 MK |
558 | kfree(error->active_bo); |
559 | kfree(error->overlay); | |
560 | kfree(error->display); | |
561 | kfree(error); | |
562 | } | |
563 | ||
564 | static struct drm_i915_error_object * | |
8ae62dc6 CW |
565 | i915_error_object_create(struct drm_i915_private *dev_priv, |
566 | struct drm_i915_gem_object *src, | |
567 | struct i915_address_space *vm) | |
84734a04 MK |
568 | { |
569 | struct drm_i915_error_object *dst; | |
aff43766 | 570 | struct i915_vma *vma = NULL; |
8ae62dc6 | 571 | int num_pages; |
b3c3f5e6 CW |
572 | bool use_ggtt; |
573 | int i = 0; | |
84734a04 MK |
574 | u32 reloc_offset; |
575 | ||
576 | if (src == NULL || src->pages == NULL) | |
577 | return NULL; | |
578 | ||
8ae62dc6 CW |
579 | num_pages = src->base.size >> PAGE_SHIFT; |
580 | ||
84734a04 MK |
581 | dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); |
582 | if (dst == NULL) | |
583 | return NULL; | |
584 | ||
87a01e82 CW |
585 | if (i915_gem_obj_bound(src, vm)) |
586 | dst->gtt_offset = i915_gem_obj_offset(src, vm); | |
587 | else | |
588 | dst->gtt_offset = -1; | |
b3c3f5e6 CW |
589 | |
590 | reloc_offset = dst->gtt_offset; | |
aff43766 TU |
591 | if (i915_is_ggtt(vm)) |
592 | vma = i915_gem_obj_to_ggtt(src); | |
b3c3f5e6 | 593 | use_ggtt = (src->cache_level == I915_CACHE_NONE && |
aff43766 TU |
594 | vma && (vma->bound & GLOBAL_BIND) && |
595 | reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); | |
b3c3f5e6 CW |
596 | |
597 | /* Cannot access stolen address directly, try to use the aperture */ | |
598 | if (src->stolen) { | |
599 | use_ggtt = true; | |
600 | ||
aff43766 | 601 | if (!(vma && vma->bound & GLOBAL_BIND)) |
b3c3f5e6 CW |
602 | goto unwind; |
603 | ||
604 | reloc_offset = i915_gem_obj_ggtt_offset(src); | |
605 | if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) | |
606 | goto unwind; | |
607 | } | |
608 | ||
609 | /* Cannot access snooped pages through the aperture */ | |
610 | if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) | |
611 | goto unwind; | |
612 | ||
613 | dst->page_count = num_pages; | |
614 | while (num_pages--) { | |
84734a04 MK |
615 | unsigned long flags; |
616 | void *d; | |
617 | ||
618 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); | |
619 | if (d == NULL) | |
620 | goto unwind; | |
621 | ||
622 | local_irq_save(flags); | |
b3c3f5e6 | 623 | if (use_ggtt) { |
84734a04 MK |
624 | void __iomem *s; |
625 | ||
626 | /* Simply ignore tiling or any overlapping fence. | |
627 | * It's part of the error state, and this hopefully | |
628 | * captures what the GPU read. | |
629 | */ | |
630 | ||
631 | s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, | |
632 | reloc_offset); | |
633 | memcpy_fromio(d, s, PAGE_SIZE); | |
634 | io_mapping_unmap_atomic(s); | |
84734a04 MK |
635 | } else { |
636 | struct page *page; | |
637 | void *s; | |
638 | ||
639 | page = i915_gem_object_get_page(src, i); | |
640 | ||
641 | drm_clflush_pages(&page, 1); | |
642 | ||
643 | s = kmap_atomic(page); | |
644 | memcpy(d, s, PAGE_SIZE); | |
645 | kunmap_atomic(s); | |
646 | ||
647 | drm_clflush_pages(&page, 1); | |
648 | } | |
649 | local_irq_restore(flags); | |
650 | ||
b3c3f5e6 | 651 | dst->pages[i++] = d; |
84734a04 MK |
652 | reloc_offset += PAGE_SIZE; |
653 | } | |
84734a04 MK |
654 | |
655 | return dst; | |
656 | ||
657 | unwind: | |
658 | while (i--) | |
659 | kfree(dst->pages[i]); | |
660 | kfree(dst); | |
661 | return NULL; | |
662 | } | |
a7b91078 | 663 | #define i915_error_ggtt_object_create(dev_priv, src) \ |
8ae62dc6 | 664 | i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) |
84734a04 MK |
665 | |
666 | static void capture_bo(struct drm_i915_error_buffer *err, | |
3a448734 | 667 | struct i915_vma *vma) |
84734a04 | 668 | { |
3a448734 CW |
669 | struct drm_i915_gem_object *obj = vma->obj; |
670 | ||
84734a04 MK |
671 | err->size = obj->base.size; |
672 | err->name = obj->base.name; | |
97b2a6a1 JH |
673 | err->rseqno = i915_gem_request_get_seqno(obj->last_read_req); |
674 | err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); | |
3a448734 | 675 | err->gtt_offset = vma->node.start; |
84734a04 MK |
676 | err->read_domains = obj->base.read_domains; |
677 | err->write_domain = obj->base.write_domain; | |
678 | err->fence_reg = obj->fence_reg; | |
679 | err->pinned = 0; | |
d7f46fc4 | 680 | if (i915_gem_obj_is_pinned(obj)) |
84734a04 | 681 | err->pinned = 1; |
84734a04 MK |
682 | err->tiling = obj->tiling_mode; |
683 | err->dirty = obj->dirty; | |
684 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
5cc9ed4b | 685 | err->userptr = obj->userptr.mm != NULL; |
41c52415 JH |
686 | err->ring = obj->last_read_req ? |
687 | i915_gem_request_get_ring(obj->last_read_req)->id : -1; | |
84734a04 MK |
688 | err->cache_level = obj->cache_level; |
689 | } | |
690 | ||
691 | static u32 capture_active_bo(struct drm_i915_error_buffer *err, | |
692 | int count, struct list_head *head) | |
693 | { | |
ca191b13 | 694 | struct i915_vma *vma; |
84734a04 MK |
695 | int i = 0; |
696 | ||
ca191b13 | 697 | list_for_each_entry(vma, head, mm_list) { |
3a448734 | 698 | capture_bo(err++, vma); |
84734a04 MK |
699 | if (++i == count) |
700 | break; | |
701 | } | |
702 | ||
703 | return i; | |
704 | } | |
705 | ||
706 | static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, | |
3a448734 CW |
707 | int count, struct list_head *head, |
708 | struct i915_address_space *vm) | |
84734a04 MK |
709 | { |
710 | struct drm_i915_gem_object *obj; | |
3a448734 CW |
711 | struct drm_i915_error_buffer * const first = err; |
712 | struct drm_i915_error_buffer * const last = err + count; | |
84734a04 MK |
713 | |
714 | list_for_each_entry(obj, head, global_list) { | |
3a448734 | 715 | struct i915_vma *vma; |
84734a04 | 716 | |
3a448734 | 717 | if (err == last) |
84734a04 | 718 | break; |
3a448734 CW |
719 | |
720 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
fe14d5f4 | 721 | if (vma->vm == vm && vma->pin_count > 0) |
3a448734 | 722 | capture_bo(err++, vma); |
84734a04 MK |
723 | } |
724 | ||
3a448734 | 725 | return err - first; |
84734a04 MK |
726 | } |
727 | ||
011cf577 BW |
728 | /* Generate a semi-unique error code. The code is not meant to have meaning, The |
729 | * code's only purpose is to try to prevent false duplicated bug reports by | |
730 | * grossly estimating a GPU error state. | |
731 | * | |
732 | * TODO Ideally, hashing the batchbuffer would be a very nice way to determine | |
733 | * the hang if we could strip the GTT offset information from it. | |
734 | * | |
735 | * It's only a small step better than a random number in its current form. | |
736 | */ | |
737 | static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, | |
cb383002 MK |
738 | struct drm_i915_error_state *error, |
739 | int *ring_id) | |
011cf577 BW |
740 | { |
741 | uint32_t error_code = 0; | |
742 | int i; | |
743 | ||
744 | /* IPEHR would be an ideal way to detect errors, as it's the gross | |
745 | * measure of "the command that hung." However, has some very common | |
746 | * synchronization commands which almost always appear in the case | |
747 | * strictly a client bug. Use instdone to differentiate those some. | |
748 | */ | |
cb383002 MK |
749 | for (i = 0; i < I915_NUM_RINGS; i++) { |
750 | if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { | |
751 | if (ring_id) | |
752 | *ring_id = i; | |
753 | ||
011cf577 | 754 | return error->ring[i].ipehr ^ error->ring[i].instdone; |
cb383002 MK |
755 | } |
756 | } | |
011cf577 BW |
757 | |
758 | return error_code; | |
759 | } | |
760 | ||
84734a04 MK |
761 | static void i915_gem_record_fences(struct drm_device *dev, |
762 | struct drm_i915_error_state *error) | |
763 | { | |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
765 | int i; | |
766 | ||
767 | /* Fences */ | |
768 | switch (INTEL_INFO(dev)->gen) { | |
01209dd5 | 769 | case 9: |
5ab31333 | 770 | case 8: |
84734a04 MK |
771 | case 7: |
772 | case 6: | |
773 | for (i = 0; i < dev_priv->num_fence_regs; i++) | |
774 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
775 | break; | |
776 | case 5: | |
777 | case 4: | |
778 | for (i = 0; i < 16; i++) | |
779 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
780 | break; | |
781 | case 3: | |
782 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
783 | for (i = 0; i < 8; i++) | |
784 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
785 | case 2: | |
786 | for (i = 0; i < 8; i++) | |
787 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
788 | break; | |
789 | ||
790 | default: | |
791 | BUG(); | |
792 | } | |
793 | } | |
794 | ||
87f85ebc | 795 | |
0ca36d78 BW |
796 | static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, |
797 | struct drm_i915_error_state *error, | |
798 | struct intel_engine_cs *ring, | |
799 | struct drm_i915_error_ring *ering) | |
800 | { | |
b4558b46 | 801 | struct intel_engine_cs *to; |
0ca36d78 BW |
802 | int i; |
803 | ||
804 | if (!i915_semaphore_is_enabled(dev_priv->dev)) | |
805 | return; | |
806 | ||
807 | if (!error->semaphore_obj) | |
808 | error->semaphore_obj = | |
cc1df8a3 DV |
809 | i915_error_ggtt_object_create(dev_priv, |
810 | dev_priv->semaphore_obj); | |
0ca36d78 | 811 | |
b4558b46 RV |
812 | for_each_ring(to, dev_priv, i) { |
813 | int idx; | |
814 | u16 signal_offset; | |
815 | u32 *tmp; | |
0ca36d78 | 816 | |
b4558b46 RV |
817 | if (ring == to) |
818 | continue; | |
819 | ||
864c6181 RV |
820 | signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) |
821 | / 4; | |
b4558b46 RV |
822 | tmp = error->semaphore_obj->pages[0]; |
823 | idx = intel_ring_sync_index(ring, to); | |
824 | ||
825 | ering->semaphore_mboxes[idx] = tmp[signal_offset]; | |
826 | ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; | |
0ca36d78 BW |
827 | } |
828 | } | |
829 | ||
87f85ebc BW |
830 | static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, |
831 | struct intel_engine_cs *ring, | |
832 | struct drm_i915_error_ring *ering) | |
833 | { | |
834 | ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); | |
835 | ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); | |
836 | ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; | |
837 | ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; | |
838 | ||
839 | if (HAS_VEBOX(dev_priv->dev)) { | |
840 | ering->semaphore_mboxes[2] = | |
841 | I915_READ(RING_SYNC_2(ring->mmio_base)); | |
842 | ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; | |
843 | } | |
844 | } | |
845 | ||
84734a04 | 846 | static void i915_record_ring_state(struct drm_device *dev, |
0ca36d78 | 847 | struct drm_i915_error_state *error, |
a4872ba6 | 848 | struct intel_engine_cs *ring, |
362b8af7 | 849 | struct drm_i915_error_ring *ering) |
84734a04 MK |
850 | { |
851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
852 | ||
853 | if (INTEL_INFO(dev)->gen >= 6) { | |
362b8af7 BW |
854 | ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); |
855 | ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
0ca36d78 BW |
856 | if (INTEL_INFO(dev)->gen >= 8) |
857 | gen8_record_semaphore_state(dev_priv, error, ring, ering); | |
858 | else | |
859 | gen6_record_semaphore_state(dev_priv, ring, ering); | |
4e5aabfd BW |
860 | } |
861 | ||
84734a04 | 862 | if (INTEL_INFO(dev)->gen >= 4) { |
362b8af7 BW |
863 | ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); |
864 | ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); | |
865 | ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
866 | ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); | |
867 | ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); | |
868 | ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); | |
13ffadd1 BW |
869 | if (INTEL_INFO(dev)->gen >= 8) { |
870 | ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; | |
362b8af7 | 871 | ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; |
13ffadd1 | 872 | } |
362b8af7 | 873 | ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); |
84734a04 | 874 | } else { |
362b8af7 BW |
875 | ering->faddr = I915_READ(DMA_FADD_I8XX); |
876 | ering->ipeir = I915_READ(IPEIR); | |
877 | ering->ipehr = I915_READ(IPEHR); | |
878 | ering->instdone = I915_READ(INSTDONE); | |
84734a04 MK |
879 | } |
880 | ||
362b8af7 BW |
881 | ering->waiting = waitqueue_active(&ring->irq_queue); |
882 | ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); | |
883 | ering->seqno = ring->get_seqno(ring, false); | |
884 | ering->acthd = intel_ring_get_active_head(ring); | |
885 | ering->head = I915_READ_HEAD(ring); | |
886 | ering->tail = I915_READ_TAIL(ring); | |
887 | ering->ctl = I915_READ_CTL(ring); | |
84734a04 | 888 | |
f3ce3821 CW |
889 | if (I915_NEED_GFX_HWS(dev)) { |
890 | int mmio; | |
891 | ||
892 | if (IS_GEN7(dev)) { | |
893 | switch (ring->id) { | |
894 | default: | |
895 | case RCS: | |
896 | mmio = RENDER_HWS_PGA_GEN7; | |
897 | break; | |
898 | case BCS: | |
899 | mmio = BLT_HWS_PGA_GEN7; | |
900 | break; | |
901 | case VCS: | |
902 | mmio = BSD_HWS_PGA_GEN7; | |
903 | break; | |
904 | case VECS: | |
905 | mmio = VEBOX_HWS_PGA_GEN7; | |
906 | break; | |
907 | } | |
908 | } else if (IS_GEN6(ring->dev)) { | |
909 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
910 | } else { | |
911 | /* XXX: gen8 returns to sanity */ | |
912 | mmio = RING_HWS_PGA(ring->mmio_base); | |
913 | } | |
914 | ||
362b8af7 | 915 | ering->hws = I915_READ(mmio); |
f3ce3821 CW |
916 | } |
917 | ||
362b8af7 BW |
918 | ering->hangcheck_score = ring->hangcheck.score; |
919 | ering->hangcheck_action = ring->hangcheck.action; | |
6c7a01ec BW |
920 | |
921 | if (USES_PPGTT(dev)) { | |
922 | int i; | |
923 | ||
924 | ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); | |
925 | ||
926 | switch (INTEL_INFO(dev)->gen) { | |
2a9b7539 | 927 | case 9: |
6c7a01ec BW |
928 | case 8: |
929 | for (i = 0; i < 4; i++) { | |
930 | ering->vm_info.pdp[i] = | |
931 | I915_READ(GEN8_RING_PDP_UDW(ring, i)); | |
932 | ering->vm_info.pdp[i] <<= 32; | |
933 | ering->vm_info.pdp[i] |= | |
934 | I915_READ(GEN8_RING_PDP_LDW(ring, i)); | |
935 | } | |
936 | break; | |
937 | case 7: | |
ae89f44d BW |
938 | ering->vm_info.pp_dir_base = |
939 | I915_READ(RING_PP_DIR_BASE(ring)); | |
6c7a01ec BW |
940 | break; |
941 | case 6: | |
ae89f44d BW |
942 | ering->vm_info.pp_dir_base = |
943 | I915_READ(RING_PP_DIR_BASE_READ(ring)); | |
6c7a01ec BW |
944 | break; |
945 | } | |
946 | } | |
84734a04 MK |
947 | } |
948 | ||
949 | ||
a4872ba6 | 950 | static void i915_gem_record_active_context(struct intel_engine_cs *ring, |
84734a04 MK |
951 | struct drm_i915_error_state *error, |
952 | struct drm_i915_error_ring *ering) | |
953 | { | |
954 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
955 | struct drm_i915_gem_object *obj; | |
956 | ||
957 | /* Currently render ring is the only HW context user */ | |
958 | if (ring->id != RCS || !error->ccid) | |
959 | return; | |
960 | ||
961 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
36362ad3 BW |
962 | if (!i915_gem_obj_ggtt_bound(obj)) |
963 | continue; | |
964 | ||
84734a04 | 965 | if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { |
17d36749 | 966 | ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); |
84734a04 MK |
967 | break; |
968 | } | |
969 | } | |
970 | } | |
971 | ||
972 | static void i915_gem_record_rings(struct drm_device *dev, | |
973 | struct drm_i915_error_state *error) | |
974 | { | |
975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84734a04 MK |
976 | struct drm_i915_gem_request *request; |
977 | int i, count; | |
978 | ||
372fbb8e | 979 | for (i = 0; i < I915_NUM_RINGS; i++) { |
a4872ba6 | 980 | struct intel_engine_cs *ring = &dev_priv->ring[i]; |
9075e52f | 981 | struct intel_ringbuffer *rbuf; |
372fbb8e | 982 | |
eee73b46 CW |
983 | error->ring[i].pid = -1; |
984 | ||
372fbb8e CW |
985 | if (ring->dev == NULL) |
986 | continue; | |
987 | ||
988 | error->ring[i].valid = true; | |
989 | ||
0ca36d78 | 990 | i915_record_ring_state(dev, error, ring, &error->ring[i]); |
84734a04 | 991 | |
ab0e7ff9 CW |
992 | request = i915_gem_find_active_request(ring); |
993 | if (request) { | |
ae6c4806 DV |
994 | struct i915_address_space *vm; |
995 | ||
996 | vm = request->ctx && request->ctx->ppgtt ? | |
997 | &request->ctx->ppgtt->base : | |
998 | &dev_priv->gtt.base; | |
999 | ||
ab0e7ff9 CW |
1000 | /* We need to copy these to an anonymous buffer |
1001 | * as the simplest method to avoid being overwritten | |
1002 | * by userspace. | |
1003 | */ | |
1004 | error->ring[i].batchbuffer = | |
1005 | i915_error_object_create(dev_priv, | |
1006 | request->batch_obj, | |
ae6c4806 | 1007 | vm); |
ab0e7ff9 | 1008 | |
8ae62dc6 | 1009 | if (HAS_BROKEN_CS_TLB(dev_priv->dev)) |
ab0e7ff9 CW |
1010 | error->ring[i].wa_batchbuffer = |
1011 | i915_error_ggtt_object_create(dev_priv, | |
1012 | ring->scratch.obj); | |
1013 | ||
1014 | if (request->file_priv) { | |
1015 | struct task_struct *task; | |
1016 | ||
1017 | rcu_read_lock(); | |
1018 | task = pid_task(request->file_priv->file->pid, | |
1019 | PIDTYPE_PID); | |
1020 | if (task) { | |
1021 | strcpy(error->ring[i].comm, task->comm); | |
1022 | error->ring[i].pid = task->pid; | |
1023 | } | |
1024 | rcu_read_unlock(); | |
1025 | } | |
1026 | } | |
84734a04 | 1027 | |
9075e52f OM |
1028 | if (i915.enable_execlists) { |
1029 | /* TODO: This is only a small fix to keep basic error | |
1030 | * capture working, but we need to add more information | |
1031 | * for it to be useful (e.g. dump the context being | |
1032 | * executed). | |
1033 | */ | |
1034 | if (request) | |
1035 | rbuf = request->ctx->engine[ring->id].ringbuf; | |
1036 | else | |
1037 | rbuf = ring->default_context->engine[ring->id].ringbuf; | |
1038 | } else | |
1039 | rbuf = ring->buffer; | |
1040 | ||
1041 | error->ring[i].cpu_ring_head = rbuf->head; | |
1042 | error->ring[i].cpu_ring_tail = rbuf->tail; | |
1043 | ||
84734a04 | 1044 | error->ring[i].ringbuffer = |
9075e52f | 1045 | i915_error_ggtt_object_create(dev_priv, rbuf->obj); |
84734a04 | 1046 | |
8ae62dc6 CW |
1047 | error->ring[i].hws_page = |
1048 | i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); | |
84734a04 MK |
1049 | |
1050 | i915_gem_record_active_context(ring, error, &error->ring[i]); | |
1051 | ||
1052 | count = 0; | |
1053 | list_for_each_entry(request, &ring->request_list, list) | |
1054 | count++; | |
1055 | ||
1056 | error->ring[i].num_requests = count; | |
1057 | error->ring[i].requests = | |
a1e22653 | 1058 | kcalloc(count, sizeof(*error->ring[i].requests), |
84734a04 MK |
1059 | GFP_ATOMIC); |
1060 | if (error->ring[i].requests == NULL) { | |
1061 | error->ring[i].num_requests = 0; | |
1062 | continue; | |
1063 | } | |
1064 | ||
1065 | count = 0; | |
1066 | list_for_each_entry(request, &ring->request_list, list) { | |
1067 | struct drm_i915_error_request *erq; | |
1068 | ||
1069 | erq = &error->ring[i].requests[count++]; | |
1070 | erq->seqno = request->seqno; | |
1071 | erq->jiffies = request->emitted_jiffies; | |
1072 | erq->tail = request->tail; | |
1073 | } | |
1074 | } | |
1075 | } | |
1076 | ||
95f5301d BW |
1077 | /* FIXME: Since pin count/bound list is global, we duplicate what we capture per |
1078 | * VM. | |
1079 | */ | |
1080 | static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, | |
1081 | struct drm_i915_error_state *error, | |
1082 | struct i915_address_space *vm, | |
1083 | const int ndx) | |
84734a04 | 1084 | { |
95f5301d | 1085 | struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; |
84734a04 | 1086 | struct drm_i915_gem_object *obj; |
95f5301d | 1087 | struct i915_vma *vma; |
84734a04 MK |
1088 | int i; |
1089 | ||
1090 | i = 0; | |
ca191b13 | 1091 | list_for_each_entry(vma, &vm->active_list, mm_list) |
84734a04 | 1092 | i++; |
95f5301d | 1093 | error->active_bo_count[ndx] = i; |
3a448734 CW |
1094 | |
1095 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
1096 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
fe14d5f4 | 1097 | if (vma->vm == vm && vma->pin_count > 0) |
3a448734 | 1098 | i++; |
3a448734 | 1099 | } |
95f5301d | 1100 | error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; |
84734a04 MK |
1101 | |
1102 | if (i) { | |
a1e22653 | 1103 | active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); |
95f5301d BW |
1104 | if (active_bo) |
1105 | pinned_bo = active_bo + error->active_bo_count[ndx]; | |
84734a04 MK |
1106 | } |
1107 | ||
95f5301d BW |
1108 | if (active_bo) |
1109 | error->active_bo_count[ndx] = | |
1110 | capture_active_bo(active_bo, | |
1111 | error->active_bo_count[ndx], | |
5cef07e1 | 1112 | &vm->active_list); |
84734a04 | 1113 | |
95f5301d BW |
1114 | if (pinned_bo) |
1115 | error->pinned_bo_count[ndx] = | |
1116 | capture_pinned_bo(pinned_bo, | |
1117 | error->pinned_bo_count[ndx], | |
3a448734 | 1118 | &dev_priv->mm.bound_list, vm); |
95f5301d BW |
1119 | error->active_bo[ndx] = active_bo; |
1120 | error->pinned_bo[ndx] = pinned_bo; | |
1121 | } | |
1122 | ||
1123 | static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, | |
1124 | struct drm_i915_error_state *error) | |
1125 | { | |
1126 | struct i915_address_space *vm; | |
1127 | int cnt = 0, i = 0; | |
1128 | ||
1129 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1130 | cnt++; | |
1131 | ||
95f5301d BW |
1132 | error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); |
1133 | error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); | |
1134 | error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), | |
1135 | GFP_ATOMIC); | |
1136 | error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), | |
1137 | GFP_ATOMIC); | |
1138 | ||
3a448734 CW |
1139 | if (error->active_bo == NULL || |
1140 | error->pinned_bo == NULL || | |
1141 | error->active_bo_count == NULL || | |
1142 | error->pinned_bo_count == NULL) { | |
1143 | kfree(error->active_bo); | |
1144 | kfree(error->active_bo_count); | |
1145 | kfree(error->pinned_bo); | |
1146 | kfree(error->pinned_bo_count); | |
1147 | ||
1148 | error->active_bo = NULL; | |
1149 | error->active_bo_count = NULL; | |
1150 | error->pinned_bo = NULL; | |
1151 | error->pinned_bo_count = NULL; | |
1152 | } else { | |
1153 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
1154 | i915_gem_capture_vm(dev_priv, error, vm, i++); | |
1155 | ||
1156 | error->vm_count = cnt; | |
1157 | } | |
84734a04 MK |
1158 | } |
1159 | ||
1d762aad BW |
1160 | /* Capture all registers which don't fit into another category. */ |
1161 | static void i915_capture_reg_state(struct drm_i915_private *dev_priv, | |
1162 | struct drm_i915_error_state *error) | |
84734a04 | 1163 | { |
1d762aad | 1164 | struct drm_device *dev = dev_priv->dev; |
885ea5a8 | 1165 | int i; |
84734a04 | 1166 | |
654c90c6 BW |
1167 | /* General organization |
1168 | * 1. Registers specific to a single generation | |
1169 | * 2. Registers which belong to multiple generations | |
1170 | * 3. Feature specific registers. | |
1171 | * 4. Everything else | |
1172 | * Please try to follow the order. | |
1173 | */ | |
84734a04 | 1174 | |
654c90c6 BW |
1175 | /* 1: Registers specific to a single generation */ |
1176 | if (IS_VALLEYVIEW(dev)) { | |
885ea5a8 | 1177 | error->gtier[0] = I915_READ(GTIER); |
843db716 | 1178 | error->ier = I915_READ(VLV_IER); |
654c90c6 BW |
1179 | error->forcewake = I915_READ(FORCEWAKE_VLV); |
1180 | } | |
84734a04 | 1181 | |
654c90c6 BW |
1182 | if (IS_GEN7(dev)) |
1183 | error->err_int = I915_READ(GEN7_ERR_INT); | |
84734a04 | 1184 | |
91ec5d11 | 1185 | if (IS_GEN6(dev)) { |
84734a04 | 1186 | error->forcewake = I915_READ(FORCEWAKE); |
91ec5d11 BW |
1187 | error->gab_ctl = I915_READ(GAB_CTL); |
1188 | error->gfx_mode = I915_READ(GFX_MODE); | |
1189 | } | |
84734a04 | 1190 | |
654c90c6 BW |
1191 | /* 2: Registers which belong to multiple generations */ |
1192 | if (INTEL_INFO(dev)->gen >= 7) | |
1193 | error->forcewake = I915_READ(FORCEWAKE_MT); | |
84734a04 MK |
1194 | |
1195 | if (INTEL_INFO(dev)->gen >= 6) { | |
654c90c6 | 1196 | error->derrmr = I915_READ(DERRMR); |
84734a04 MK |
1197 | error->error = I915_READ(ERROR_GEN6); |
1198 | error->done_reg = I915_READ(DONE_REG); | |
1199 | } | |
1200 | ||
654c90c6 | 1201 | /* 3: Feature specific registers */ |
91ec5d11 BW |
1202 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1203 | error->gam_ecochk = I915_READ(GAM_ECOCHK); | |
1204 | error->gac_eco = I915_READ(GAC_ECO_BITS); | |
1205 | } | |
1206 | ||
1207 | /* 4: Everything else */ | |
654c90c6 BW |
1208 | if (HAS_HW_CONTEXTS(dev)) |
1209 | error->ccid = I915_READ(CCID); | |
1210 | ||
885ea5a8 RV |
1211 | if (INTEL_INFO(dev)->gen >= 8) { |
1212 | error->ier = I915_READ(GEN8_DE_MISC_IER); | |
1213 | for (i = 0; i < 4; i++) | |
1214 | error->gtier[i] = I915_READ(GEN8_GT_IER(i)); | |
1215 | } else if (HAS_PCH_SPLIT(dev)) { | |
843db716 | 1216 | error->ier = I915_READ(DEIER); |
885ea5a8 | 1217 | error->gtier[0] = I915_READ(GTIER); |
843db716 RV |
1218 | } else if (IS_GEN2(dev)) { |
1219 | error->ier = I915_READ16(IER); | |
1220 | } else if (!IS_VALLEYVIEW(dev)) { | |
1221 | error->ier = I915_READ(IER); | |
654c90c6 | 1222 | } |
654c90c6 BW |
1223 | error->eir = I915_READ(EIR); |
1224 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
84734a04 MK |
1225 | |
1226 | i915_get_extra_instdone(dev, error->extra_instdone); | |
1d762aad BW |
1227 | } |
1228 | ||
cb383002 | 1229 | static void i915_error_capture_msg(struct drm_device *dev, |
58174462 MK |
1230 | struct drm_i915_error_state *error, |
1231 | bool wedged, | |
1232 | const char *error_msg) | |
cb383002 MK |
1233 | { |
1234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1235 | u32 ecode; | |
58174462 | 1236 | int ring_id = -1, len; |
cb383002 MK |
1237 | |
1238 | ecode = i915_error_generate_code(dev_priv, error, &ring_id); | |
1239 | ||
58174462 | 1240 | len = scnprintf(error->error_msg, sizeof(error->error_msg), |
0b5492d6 MK |
1241 | "GPU HANG: ecode %d:%d:0x%08x", |
1242 | INTEL_INFO(dev)->gen, ring_id, ecode); | |
58174462 MK |
1243 | |
1244 | if (ring_id != -1 && error->ring[ring_id].pid != -1) | |
1245 | len += scnprintf(error->error_msg + len, | |
1246 | sizeof(error->error_msg) - len, | |
1247 | ", in %s [%d]", | |
1248 | error->ring[ring_id].comm, | |
1249 | error->ring[ring_id].pid); | |
1250 | ||
1251 | scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, | |
1252 | ", reason: %s, action: %s", | |
1253 | error_msg, | |
1254 | wedged ? "reset" : "continue"); | |
cb383002 MK |
1255 | } |
1256 | ||
48b031e3 MK |
1257 | static void i915_capture_gen_state(struct drm_i915_private *dev_priv, |
1258 | struct drm_i915_error_state *error) | |
1259 | { | |
1260 | error->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
62d5d69b | 1261 | error->suspend_count = dev_priv->suspend_count; |
48b031e3 MK |
1262 | } |
1263 | ||
1d762aad BW |
1264 | /** |
1265 | * i915_capture_error_state - capture an error record for later analysis | |
1266 | * @dev: drm device | |
1267 | * | |
1268 | * Should be called when an error is detected (either a hang or an error | |
1269 | * interrupt) to capture error state from the time of the error. Fills | |
1270 | * out a structure which becomes available in debugfs for user level tools | |
1271 | * to pick up. | |
1272 | */ | |
58174462 MK |
1273 | void i915_capture_error_state(struct drm_device *dev, bool wedged, |
1274 | const char *error_msg) | |
1d762aad | 1275 | { |
53a4c6b2 | 1276 | static bool warned; |
1d762aad BW |
1277 | struct drm_i915_private *dev_priv = dev->dev_private; |
1278 | struct drm_i915_error_state *error; | |
1279 | unsigned long flags; | |
1d762aad BW |
1280 | |
1281 | /* Account for pipe specific data like PIPE*STAT */ | |
1282 | error = kzalloc(sizeof(*error), GFP_ATOMIC); | |
1283 | if (!error) { | |
1284 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); | |
1285 | return; | |
1286 | } | |
1287 | ||
011cf577 BW |
1288 | kref_init(&error->ref); |
1289 | ||
48b031e3 | 1290 | i915_capture_gen_state(dev_priv, error); |
011cf577 BW |
1291 | i915_capture_reg_state(dev_priv, error); |
1292 | i915_gem_capture_buffers(dev_priv, error); | |
1293 | i915_gem_record_fences(dev, error); | |
1294 | i915_gem_record_rings(dev, error); | |
1d762aad | 1295 | |
84734a04 MK |
1296 | do_gettimeofday(&error->time); |
1297 | ||
1298 | error->overlay = intel_overlay_capture_error_state(dev); | |
1299 | error->display = intel_display_capture_error_state(dev); | |
1300 | ||
58174462 | 1301 | i915_error_capture_msg(dev, error, wedged, error_msg); |
cb383002 MK |
1302 | DRM_INFO("%s\n", error->error_msg); |
1303 | ||
84734a04 MK |
1304 | spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); |
1305 | if (dev_priv->gpu_error.first_error == NULL) { | |
1306 | dev_priv->gpu_error.first_error = error; | |
1307 | error = NULL; | |
1308 | } | |
1309 | spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); | |
1310 | ||
cb383002 | 1311 | if (error) { |
84734a04 | 1312 | i915_error_state_free(&error->ref); |
cb383002 MK |
1313 | return; |
1314 | } | |
1315 | ||
1316 | if (!warned) { | |
1317 | DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); | |
1318 | DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); | |
1319 | DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); | |
1320 | DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); | |
1321 | DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); | |
1322 | warned = true; | |
1323 | } | |
84734a04 MK |
1324 | } |
1325 | ||
1326 | void i915_error_state_get(struct drm_device *dev, | |
1327 | struct i915_error_state_file_priv *error_priv) | |
1328 | { | |
1329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84734a04 | 1330 | |
5b254c59 | 1331 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1332 | error_priv->error = dev_priv->gpu_error.first_error; |
1333 | if (error_priv->error) | |
1334 | kref_get(&error_priv->error->ref); | |
5b254c59 | 1335 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1336 | |
1337 | } | |
1338 | ||
1339 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv) | |
1340 | { | |
1341 | if (error_priv->error) | |
1342 | kref_put(&error_priv->error->ref, i915_error_state_free); | |
1343 | } | |
1344 | ||
1345 | void i915_destroy_error_state(struct drm_device *dev) | |
1346 | { | |
1347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1348 | struct drm_i915_error_state *error; | |
84734a04 | 1349 | |
5b254c59 | 1350 | spin_lock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1351 | error = dev_priv->gpu_error.first_error; |
1352 | dev_priv->gpu_error.first_error = NULL; | |
5b254c59 | 1353 | spin_unlock_irq(&dev_priv->gpu_error.lock); |
84734a04 MK |
1354 | |
1355 | if (error) | |
1356 | kref_put(&error->ref, i915_error_state_free); | |
1357 | } | |
1358 | ||
0a4cd7c8 | 1359 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type) |
84734a04 MK |
1360 | { |
1361 | switch (type) { | |
1362 | case I915_CACHE_NONE: return " uncached"; | |
0a4cd7c8 | 1363 | case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; |
350ec881 | 1364 | case I915_CACHE_L3_LLC: return " L3+LLC"; |
f56383cb | 1365 | case I915_CACHE_WT: return " WT"; |
84734a04 MK |
1366 | default: return ""; |
1367 | } | |
1368 | } | |
1369 | ||
1370 | /* NB: please notice the memset */ | |
1371 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) | |
1372 | { | |
1373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1374 | memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); | |
1375 | ||
1376 | switch (INTEL_INFO(dev)->gen) { | |
1377 | case 2: | |
1378 | case 3: | |
1379 | instdone[0] = I915_READ(INSTDONE); | |
1380 | break; | |
1381 | case 4: | |
1382 | case 5: | |
1383 | case 6: | |
1384 | instdone[0] = I915_READ(INSTDONE_I965); | |
1385 | instdone[1] = I915_READ(INSTDONE1); | |
1386 | break; | |
1387 | default: | |
1388 | WARN_ONCE(1, "Unsupported platform\n"); | |
1389 | case 7: | |
d0582ed2 | 1390 | case 8: |
2fcdcd8a | 1391 | case 9: |
84734a04 MK |
1392 | instdone[0] = I915_READ(GEN7_INSTDONE_1); |
1393 | instdone[1] = I915_READ(GEN7_SC_INSTDONE); | |
1394 | instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); | |
1395 | instdone[3] = I915_READ(GEN7_ROW_INSTDONE); | |
1396 | break; | |
1397 | } | |
1398 | } |