[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_guc_reg.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */
#ifndef _I915_GUC_REG_H_
#define _I915_GUC_REG_H_

/* Definitions of GuC H/W registers, bits, etc */

#define GUC_STATUS			_MMIO(0xc000)
#define   GS_RESET_SHIFT		0
#define   GS_MIA_IN_RESET		  (0x01 << GS_RESET_SHIFT)
#define   GS_BOOTROM_SHIFT		1
#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
#define   GS_BOOTROM_JUMP_PASSED	  (0x76 << GS_BOOTROM_SHIFT)
#define   GS_UKERNEL_SHIFT		8
#define   GS_UKERNEL_MASK		  (0xFF << GS_UKERNEL_SHIFT)
#define   GS_UKERNEL_LAPIC_DONE		  (0x30 << GS_UKERNEL_SHIFT)
#define   GS_UKERNEL_DPC_ERROR		  (0x60 << GS_UKERNEL_SHIFT)
#define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
#define   GS_MIA_SHIFT			16
#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
#define   GS_MIA_CORE_STATE		  (0x01 << GS_MIA_SHIFT)
#define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
#define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
#define   GS_AUTH_STATUS_SHIFT		30
#define   GS_AUTH_STATUS_MASK		  (0x03 << GS_AUTH_STATUS_SHIFT)
#define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
#define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)

#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
#define SOFT_SCRATCH_COUNT		16

#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
#define   UOS_RSA_SCRATCH_MAX_COUNT	  64
#define DMA_ADDR_0_LOW			_MMIO(0xc300)
#define DMA_ADDR_0_HIGH			_MMIO(0xc304)
#define DMA_ADDR_1_LOW			_MMIO(0xc308)
#define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
#define DMA_COPY_SIZE			_MMIO(0xc310)
#define DMA_CTRL			_MMIO(0xc314)
#define   UOS_MOVE			  (1<<4)
#define   START_DMA			  (1<<0)
#define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
#define   GUC_WOPCM_OFFSET_VALUE	  0x80000	/* 512KB */
#define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)

#define GUC_WOPCM_SIZE			_MMIO(0xc050)
#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */

/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)

#define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
#define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
#define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
#define   GT_DOORBELL_ENABLE		  (1<<0)

#define GEN8_GTCR			_MMIO(0x4274)
#define   GEN8_GTCR_INVALIDATE		  (1<<0)

#define GUC_ARAT_C6DIS			_MMIO(0xA178)

#define GUC_SHIM_CONTROL		_MMIO(0xc064)
#define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
#define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
#define   GUC_ENABLE_MIA_CACHING		(1<<2)
#define   GUC_GEN10_MSGCH_ENABLE		(1<<4)
#define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	(1<<9)
#define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	(1<<10)
#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)

#define GUC_SHIM_CONTROL_VALUE	(GUC_DISABLE_SRAM_INIT_TO_ZEROES	| \
				 GUC_ENABLE_READ_CACHE_LOGIC		| \
				 GUC_ENABLE_MIA_CACHING			| \
				 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	| \
				 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	| \
				 GUC_ENABLE_MIA_CLOCK_GATING)

#define HOST2GUC_INTERRUPT		_MMIO(0xc4c8)
#define   HOST2GUC_TRIGGER		  (1<<0)

#define DRBMISC1			0x1984
#define   DOORBELL_ENABLE		  (1<<0)

#define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
#define   GEN8_DRB_VALID		  (1<<0)
#define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)

#define DE_GUCRMR			_MMIO(0x44054)

#define GUC_BCS_RCS_IER			_MMIO(0xC550)
#define GUC_VCS2_VCS1_IER		_MMIO(0xC554)
#define GUC_WD_VECS_IER			_MMIO(0xC558)
#define GUC_PM_P24C_IER			_MMIO(0xC55C)

#endif
Commit	Line	Data
2617268f DG	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24	#ifndef _I915_GUC_REG_H_
	25	#define _I915_GUC_REG_H_
	26
	27	/* Definitions of GuC H/W registers, bits, etc */
	28
f0f59a00	29	#define GUC_STATUS _MMIO(0xc000)
d761701c DG	30	#define GS_RESET_SHIFT 0
d761701c DG	31	#define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
2617268f DG	32	#define GS_BOOTROM_SHIFT 1
	33	#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
	34	#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
d761701c	35	#define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT)
2617268f DG	36	#define GS_UKERNEL_SHIFT 8
	37	#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
	38	#define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
	39	#define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
	40	#define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
	41	#define GS_MIA_SHIFT 16
	42	#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
d761701c DG	43	#define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
	44	#define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
	45	#define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
	46	#define GS_AUTH_STATUS_SHIFT 30
	47	#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT)
	48	#define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
	49	#define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
2617268f	50
f0f59a00	51	#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
68371a95	52	#define SOFT_SCRATCH_COUNT 16
2617268f	53
f0f59a00	54	#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
feda33ef	55	#define UOS_RSA_SCRATCH_MAX_COUNT 64
f0f59a00 VS	56	#define DMA_ADDR_0_LOW _MMIO(0xc300)
	57	#define DMA_ADDR_0_HIGH _MMIO(0xc304)
	58	#define DMA_ADDR_1_LOW _MMIO(0xc308)
	59	#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
2617268f DG	60	#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
2617268f DG	61	#define DMA_ADDRESS_SPACE_GTT (8 << 16)
f0f59a00 VS	62	#define DMA_COPY_SIZE _MMIO(0xc310)
f0f59a00 VS	63	#define DMA_CTRL _MMIO(0xc314)
2617268f DG	64	#define UOS_MOVE (1<<4)
2617268f DG	65	#define START_DMA (1<<0)
f0f59a00	66	#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
33a732f4	67	#define GUC_WOPCM_OFFSET_VALUE 0x80000 /* 512KB */
f0f59a00	68	#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
33a732f4	69
f0f59a00	70	#define GUC_WOPCM_SIZE _MMIO(0xc050)
33a732f4 AD	71	#define GUC_WOPCM_SIZE_VALUE (0x80 << 12) /* 512KB */
	72
	73	/* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
	74	#define GUC_WOPCM_TOP (GUC_WOPCM_SIZE_VALUE)
2617268f	75
f0f59a00 VS	76	#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
	77	#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
	78	#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
33a732f4	79	#define GT_DOORBELL_ENABLE (1<<0)
2617268f	80
f0f59a00	81	#define GEN8_GTCR _MMIO(0x4274)
2617268f DG	82	#define GEN8_GTCR_INVALIDATE (1<<0)
2617268f DG	83
f0f59a00	84	#define GUC_ARAT_C6DIS _MMIO(0xA178)
2617268f	85
f0f59a00	86	#define GUC_SHIM_CONTROL _MMIO(0xc064)
2617268f DG	87	#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
	88	#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
	89	#define GUC_ENABLE_MIA_CACHING (1<<2)
	90	#define GUC_GEN10_MSGCH_ENABLE (1<<4)
	91	#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
	92	#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
	93	#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
	94	#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
	95
	96	#define GUC_SHIM_CONTROL_VALUE (GUC_DISABLE_SRAM_INIT_TO_ZEROES \| \
	97	GUC_ENABLE_READ_CACHE_LOGIC \| \
	98	GUC_ENABLE_MIA_CACHING \| \
	99	GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA \| \
33a732f4 AD	100	GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA \| \
33a732f4 AD	101	GUC_ENABLE_MIA_CLOCK_GATING)
2617268f	102
f0f59a00	103	#define HOST2GUC_INTERRUPT _MMIO(0xc4c8)
2617268f DG	104	#define HOST2GUC_TRIGGER (1<<0)
	105
	106	#define DRBMISC1 0x1984
	107	#define DOORBELL_ENABLE (1<<0)
	108
f0f59a00	109	#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
2617268f	110	#define GEN8_DRB_VALID (1<<0)
f0f59a00	111	#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
2617268f	112
f0f59a00	113	#define DE_GUCRMR _MMIO(0x44054)
2617268f	114
f0f59a00 VS	115	#define GUC_BCS_RCS_IER _MMIO(0xC550)
	116	#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
	117	#define GUC_WD_VECS_IER _MMIO(0xC558)
	118	#define GUC_PM_P24C_IER _MMIO(0xC55C)
2617268f DG	119
2617268f DG	120	#endif