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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
26 | #include "i915_drv.h" | |
27 | #include "intel_guc.h" | |
28 | ||
44a28b1d | 29 | /** |
feda33ef | 30 | * DOC: GuC-based command submission |
44a28b1d DG |
31 | * |
32 | * i915_guc_client: | |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
37 | * is mapped to client space. So the client can write Work Item then ring the | |
38 | * doorbell. | |
39 | * | |
40 | * To simplify the implementation, we allocate one gem object that contains all | |
41 | * pages for doorbell, process descriptor and workqueue. | |
42 | * | |
43 | * The Scratch registers: | |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
47 | * Firmware writes a success/fail code back to the action register after | |
48 | * processes the request. The kernel driver polls waiting for this update and | |
49 | * then proceeds. | |
50 | * See host2guc_action() | |
51 | * | |
52 | * Doorbells: | |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
54 | * mapped into process space. | |
55 | * | |
56 | * Work Items: | |
57 | * There are several types of work items that the host may place into a | |
58 | * workqueue, each with its own requirements and limitations. Currently only | |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
61 | * ELSP context descriptor dword into Work Item. | |
62 | * See guc_add_workqueue_item() | |
63 | * | |
64 | */ | |
65 | ||
66 | /* | |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) | |
68 | * Return true if it contains a response rather than a command | |
69 | */ | |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, | |
71 | u32 *status) | |
72 | { | |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); | |
74 | *status = val; | |
75 | return GUC2HOST_IS_RESPONSE(val); | |
76 | } | |
77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
81 | u32 status; | |
82 | int i; | |
83 | int ret; | |
84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) | |
86 | return -EINVAL; | |
87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
44a28b1d DG |
89 | |
90 | dev_priv->guc.action_count += 1; | |
91 | dev_priv->guc.action_cmd = data[0]; | |
92 | ||
93 | for (i = 0; i < len; i++) | |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); | |
95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); | |
97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); | |
99 | ||
100 | /* No HOST2GUC command should take longer than 10ms */ | |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); | |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { | |
103 | /* | |
104 | * Either the GuC explicitly returned an error (which | |
105 | * we convert to -EIO here) or no response at all was | |
106 | * received within the timeout limit (-ETIMEDOUT) | |
107 | */ | |
108 | if (ret != -ETIMEDOUT) | |
109 | ret = -EIO; | |
110 | ||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " | |
112 | "status=0x%08X response=0x%08X\n", | |
113 | data[0], ret, status, | |
114 | I915_READ(SOFT_SCRATCH(15))); | |
115 | ||
116 | dev_priv->guc.action_fail += 1; | |
117 | dev_priv->guc.action_err = ret; | |
118 | } | |
119 | dev_priv->guc.action_status = status; | |
120 | ||
44a28b1d DG |
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | /* | |
127 | * Tell the GuC to allocate or deallocate a specific doorbell | |
128 | */ | |
129 | ||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, | |
131 | struct i915_guc_client *client) | |
132 | { | |
133 | u32 data[2]; | |
134 | ||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; | |
136 | data[1] = client->ctx_index; | |
137 | ||
138 | return host2guc_action(guc, data, 2); | |
139 | } | |
140 | ||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, | |
142 | struct i915_guc_client *client) | |
143 | { | |
144 | u32 data[2]; | |
145 | ||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; | |
147 | data[1] = client->ctx_index; | |
148 | ||
149 | return host2guc_action(guc, data, 2); | |
150 | } | |
151 | ||
f5d3c3ea AD |
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
153 | struct i915_guc_client *client) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
156 | u32 data[2]; | |
157 | ||
158 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; | |
93f25318 | 159 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
61251512 | 160 | if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
93f25318 AD |
161 | data[1] = 0; |
162 | else | |
163 | /* bit 0 and 1 are for Render and Media domain separately */ | |
164 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; | |
165 | ||
166 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
f5d3c3ea AD |
167 | } |
168 | ||
44a28b1d DG |
169 | /* |
170 | * Initialise, update, or clear doorbell data shared with the GuC | |
171 | * | |
172 | * These functions modify shared data and so need access to the mapped | |
173 | * client object which contains the page being used for the doorbell | |
174 | */ | |
175 | ||
a667429b DG |
176 | static int guc_update_doorbell_id(struct intel_guc *guc, |
177 | struct i915_guc_client *client, | |
178 | u16 new_id) | |
44a28b1d | 179 | { |
a667429b DG |
180 | struct sg_table *sg = guc->ctx_pool_obj->pages; |
181 | void *doorbell_bitmap = guc->doorbell_bitmap; | |
44a28b1d | 182 | struct guc_doorbell_info *doorbell; |
a667429b DG |
183 | struct guc_context_desc desc; |
184 | size_t len; | |
44a28b1d | 185 | |
0d92a6a4 | 186 | doorbell = client->client_base + client->doorbell_offset; |
44a28b1d | 187 | |
a667429b DG |
188 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID && |
189 | test_bit(client->doorbell_id, doorbell_bitmap)) { | |
190 | /* Deactivate the old doorbell */ | |
191 | doorbell->db_status = GUC_DOORBELL_DISABLED; | |
192 | (void)host2guc_release_doorbell(guc, client); | |
193 | __clear_bit(client->doorbell_id, doorbell_bitmap); | |
194 | } | |
195 | ||
196 | /* Update the GuC's idea of the doorbell ID */ | |
197 | len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
198 | sizeof(desc) * client->ctx_index); | |
199 | if (len != sizeof(desc)) | |
200 | return -EFAULT; | |
201 | desc.db_id = new_id; | |
202 | len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
203 | sizeof(desc) * client->ctx_index); | |
204 | if (len != sizeof(desc)) | |
205 | return -EFAULT; | |
206 | ||
207 | client->doorbell_id = new_id; | |
208 | if (new_id == GUC_INVALID_DOORBELL_ID) | |
209 | return 0; | |
210 | ||
211 | /* Activate the new doorbell */ | |
212 | __set_bit(new_id, doorbell_bitmap); | |
44a28b1d | 213 | doorbell->cookie = 0; |
a667429b DG |
214 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
215 | return host2guc_allocate_doorbell(guc, client); | |
216 | } | |
217 | ||
218 | static int guc_init_doorbell(struct intel_guc *guc, | |
219 | struct i915_guc_client *client, | |
220 | uint16_t db_id) | |
221 | { | |
222 | return guc_update_doorbell_id(guc, client, db_id); | |
44a28b1d DG |
223 | } |
224 | ||
44a28b1d DG |
225 | static void guc_disable_doorbell(struct intel_guc *guc, |
226 | struct i915_guc_client *client) | |
227 | { | |
a667429b | 228 | (void)guc_update_doorbell_id(guc, client, GUC_INVALID_DOORBELL_ID); |
44a28b1d | 229 | |
44a28b1d DG |
230 | /* XXX: wait for any interrupts */ |
231 | /* XXX: wait for workqueue to drain */ | |
232 | } | |
233 | ||
f10d69a7 DG |
234 | static uint16_t |
235 | select_doorbell_register(struct intel_guc *guc, uint32_t priority) | |
236 | { | |
237 | /* | |
238 | * The bitmap tracks which doorbell registers are currently in use. | |
239 | * It is split into two halves; the first half is used for normal | |
240 | * priority contexts, the second half for high-priority ones. | |
241 | * Note that logically higher priorities are numerically less than | |
242 | * normal ones, so the test below means "is it high-priority?" | |
243 | */ | |
244 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
245 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
246 | const uint16_t start = hi_pri ? half : 0; | |
247 | const uint16_t end = start + half; | |
248 | uint16_t id; | |
249 | ||
250 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); | |
251 | if (id == end) | |
252 | id = GUC_INVALID_DOORBELL_ID; | |
253 | ||
254 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
255 | hi_pri ? "high" : "normal", id); | |
256 | ||
257 | return id; | |
258 | } | |
259 | ||
44a28b1d DG |
260 | /* |
261 | * Select, assign and relase doorbell cachelines | |
262 | * | |
263 | * These functions track which doorbell cachelines are in use. | |
264 | * The data they manipulate is protected by the host2guc lock. | |
265 | */ | |
266 | ||
267 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
268 | { | |
269 | const uint32_t cacheline_size = cache_line_size(); | |
270 | uint32_t offset; | |
271 | ||
44a28b1d DG |
272 | /* Doorbell uses a single cache line within a page */ |
273 | offset = offset_in_page(guc->db_cacheline); | |
274 | ||
275 | /* Moving to next cache line to reduce contention */ | |
276 | guc->db_cacheline += cacheline_size; | |
277 | ||
44a28b1d DG |
278 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
279 | offset, guc->db_cacheline, cacheline_size); | |
280 | ||
281 | return offset; | |
282 | } | |
283 | ||
44a28b1d DG |
284 | /* |
285 | * Initialise the process descriptor shared with the GuC firmware. | |
286 | */ | |
287 | static void guc_init_proc_desc(struct intel_guc *guc, | |
288 | struct i915_guc_client *client) | |
289 | { | |
290 | struct guc_process_desc *desc; | |
44a28b1d | 291 | |
0d92a6a4 | 292 | desc = client->client_base + client->proc_desc_offset; |
44a28b1d DG |
293 | |
294 | memset(desc, 0, sizeof(*desc)); | |
295 | ||
296 | /* | |
297 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
298 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
299 | * space for kernel clients (map on demand instead? May make debug | |
300 | * easier to have it mapped). | |
301 | */ | |
302 | desc->wq_base_addr = 0; | |
303 | desc->db_base_addr = 0; | |
304 | ||
305 | desc->context_id = client->ctx_index; | |
306 | desc->wq_size_bytes = client->wq_size; | |
307 | desc->wq_status = WQ_STATUS_ACTIVE; | |
308 | desc->priority = client->priority; | |
44a28b1d DG |
309 | } |
310 | ||
311 | /* | |
312 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
313 | * | |
314 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
315 | * data structures relating to this client (doorbell, process descriptor, | |
316 | * write queue, etc). | |
317 | */ | |
318 | ||
319 | static void guc_init_ctx_desc(struct intel_guc *guc, | |
320 | struct i915_guc_client *client) | |
321 | { | |
86e06cc0 | 322 | struct drm_i915_gem_object *client_obj = client->client_obj; |
397097b0 | 323 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 324 | struct intel_engine_cs *engine; |
e2efd130 | 325 | struct i915_gem_context *ctx = client->owner; |
44a28b1d DG |
326 | struct guc_context_desc desc; |
327 | struct sg_table *sg; | |
86e06cc0 | 328 | u32 gfx_addr; |
44a28b1d DG |
329 | |
330 | memset(&desc, 0, sizeof(desc)); | |
331 | ||
332 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
333 | desc.context_id = client->ctx_index; | |
334 | desc.priority = client->priority; | |
44a28b1d DG |
335 | desc.db_id = client->doorbell_id; |
336 | ||
9021ad03 CW |
337 | for_each_engine(engine, dev_priv) { |
338 | struct intel_context *ce = &ctx->engine[engine->id]; | |
e2f80391 | 339 | struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id]; |
d1675198 | 340 | struct drm_i915_gem_object *obj; |
d1675198 AD |
341 | |
342 | /* TODO: We have a design issue to be solved here. Only when we | |
343 | * receive the first batch, we know which engine is used by the | |
344 | * user. But here GuC expects the lrc and ring to be pinned. It | |
345 | * is not an issue for default context, which is the only one | |
346 | * for now who owns a GuC client. But for future owner of GuC | |
347 | * client, need to make sure lrc is pinned prior to enter here. | |
348 | */ | |
9021ad03 | 349 | if (!ce->state) |
d1675198 AD |
350 | break; /* XXX: continue? */ |
351 | ||
9021ad03 | 352 | lrc->context_desc = lower_32_bits(ce->lrc_desc); |
d1675198 AD |
353 | |
354 | /* The state page is after PPHWSP */ | |
9021ad03 | 355 | gfx_addr = i915_gem_obj_ggtt_offset(ce->state); |
86e06cc0 | 356 | lrc->ring_lcra = gfx_addr + LRC_STATE_PN * PAGE_SIZE; |
d1675198 | 357 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | |
e2f80391 | 358 | (engine->guc_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 359 | |
9021ad03 | 360 | obj = ce->ringbuf->obj; |
86e06cc0 | 361 | gfx_addr = i915_gem_obj_ggtt_offset(obj); |
d1675198 | 362 | |
86e06cc0 DG |
363 | lrc->ring_begin = gfx_addr; |
364 | lrc->ring_end = gfx_addr + obj->base.size - 1; | |
365 | lrc->ring_next_free_location = gfx_addr; | |
d1675198 AD |
366 | lrc->ring_current_tail_pointer_value = 0; |
367 | ||
e2f80391 | 368 | desc.engines_used |= (1 << engine->guc_id); |
d1675198 AD |
369 | } |
370 | ||
371 | WARN_ON(desc.engines_used == 0); | |
372 | ||
44a28b1d | 373 | /* |
86e06cc0 DG |
374 | * The doorbell, process descriptor, and workqueue are all parts |
375 | * of the client object, which the GuC will reference via the GGTT | |
44a28b1d | 376 | */ |
86e06cc0 DG |
377 | gfx_addr = i915_gem_obj_ggtt_offset(client_obj); |
378 | desc.db_trigger_phy = sg_dma_address(client_obj->pages->sgl) + | |
379 | client->doorbell_offset; | |
380 | desc.db_trigger_cpu = (uintptr_t)client->client_base + | |
381 | client->doorbell_offset; | |
382 | desc.db_trigger_uk = gfx_addr + client->doorbell_offset; | |
383 | desc.process_desc = gfx_addr + client->proc_desc_offset; | |
384 | desc.wq_addr = gfx_addr + client->wq_offset; | |
44a28b1d DG |
385 | desc.wq_size = client->wq_size; |
386 | ||
387 | /* | |
e2efd130 | 388 | * XXX: Take LRCs from an existing context if this is not an |
44a28b1d DG |
389 | * IsKMDCreatedContext client |
390 | */ | |
391 | desc.desc_private = (uintptr_t)client; | |
392 | ||
393 | /* Pool context is pinned already */ | |
394 | sg = guc->ctx_pool_obj->pages; | |
395 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
396 | sizeof(desc) * client->ctx_index); | |
397 | } | |
398 | ||
399 | static void guc_fini_ctx_desc(struct intel_guc *guc, | |
400 | struct i915_guc_client *client) | |
401 | { | |
402 | struct guc_context_desc desc; | |
403 | struct sg_table *sg; | |
404 | ||
405 | memset(&desc, 0, sizeof(desc)); | |
406 | ||
407 | sg = guc->ctx_pool_obj->pages; | |
408 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
409 | sizeof(desc) * client->ctx_index); | |
410 | } | |
411 | ||
7c2c270d DG |
412 | /** |
413 | * i915_guc_wq_check_space() - check that the GuC can accept a request | |
414 | * @request: request associated with the commands | |
415 | * | |
416 | * Return: 0 if space is available | |
417 | * -EAGAIN if space is not currently available | |
418 | * | |
419 | * This function must be called (and must return 0) before a request | |
420 | * is submitted to the GuC via i915_guc_submit() below. Once a result | |
421 | * of 0 has been returned, it remains valid until (but only until) | |
422 | * the next call to submit(). | |
423 | * | |
424 | * This precheck allows the caller to determine in advance that space | |
425 | * will be available for the next submission before committing resources | |
426 | * to it, and helps avoid late failures with complicated recovery paths. | |
427 | */ | |
428 | int i915_guc_wq_check_space(struct drm_i915_gem_request *request) | |
44a28b1d | 429 | { |
551aaecd | 430 | const size_t wqi_size = sizeof(struct guc_wq_item); |
7c2c270d | 431 | struct i915_guc_client *gc = request->i915->guc.execbuf_client; |
44a28b1d | 432 | struct guc_process_desc *desc; |
551aaecd | 433 | u32 freespace; |
44a28b1d | 434 | |
7c2c270d | 435 | GEM_BUG_ON(gc == NULL); |
a7e02199 | 436 | |
0d92a6a4 | 437 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d | 438 | |
551aaecd DG |
439 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); |
440 | if (likely(freespace >= wqi_size)) | |
441 | return 0; | |
5a843307 | 442 | |
551aaecd | 443 | gc->no_wq_space += 1; |
44a28b1d | 444 | |
551aaecd | 445 | return -EAGAIN; |
44a28b1d DG |
446 | } |
447 | ||
0a31afbc DG |
448 | static void guc_add_workqueue_item(struct i915_guc_client *gc, |
449 | struct drm_i915_gem_request *rq) | |
44a28b1d | 450 | { |
0a31afbc DG |
451 | /* wqi_len is in DWords, and does not include the one-word header */ |
452 | const size_t wqi_size = sizeof(struct guc_wq_item); | |
453 | const u32 wqi_len = wqi_size/sizeof(u32) - 1; | |
a5916e8f | 454 | struct guc_process_desc *desc; |
44a28b1d DG |
455 | struct guc_wq_item *wqi; |
456 | void *base; | |
0a31afbc | 457 | u32 freespace, tail, wq_off, wq_page; |
a7e02199 | 458 | |
a5916e8f | 459 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d | 460 | |
0a31afbc DG |
461 | /* Free space is guaranteed, see i915_guc_wq_check_space() above */ |
462 | freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); | |
463 | GEM_BUG_ON(freespace < wqi_size); | |
464 | ||
465 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
466 | tail = rq->tail; | |
467 | GEM_BUG_ON(tail & 7); | |
468 | tail >>= 3; | |
469 | GEM_BUG_ON(tail > WQ_RING_TAIL_MAX); | |
44a28b1d DG |
470 | |
471 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
472 | * should not have the case where structure wqi is across page, neither | |
473 | * wrapped to the beginning. This simplifies the implementation below. | |
474 | * | |
475 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
476 | * workqueue buffer dw by dw. | |
477 | */ | |
0a31afbc | 478 | BUILD_BUG_ON(wqi_size != 16); |
44a28b1d | 479 | |
0a31afbc DG |
480 | /* postincrement WQ tail for next time */ |
481 | wq_off = gc->wq_tail; | |
482 | gc->wq_tail += wqi_size; | |
483 | gc->wq_tail &= gc->wq_size - 1; | |
484 | GEM_BUG_ON(wq_off & (wqi_size - 1)); | |
485 | ||
486 | /* WQ starts from the page after doorbell / process_desc */ | |
487 | wq_page = (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT; | |
44a28b1d | 488 | wq_off &= PAGE_SIZE - 1; |
0a31afbc | 489 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, wq_page)); |
44a28b1d DG |
490 | wqi = (struct guc_wq_item *)((char *)base + wq_off); |
491 | ||
0a31afbc | 492 | /* Now fill in the 4-word work queue item */ |
44a28b1d | 493 | wqi->header = WQ_TYPE_INORDER | |
0a31afbc | 494 | (wqi_len << WQ_LEN_SHIFT) | |
4a570db5 | 495 | (rq->engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
496 | WQ_NO_WCFLUSH_WAIT; |
497 | ||
498 | /* The GuC wants only the low-order word of the context descriptor */ | |
4a570db5 TU |
499 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, |
500 | rq->engine); | |
44a28b1d | 501 | |
44a28b1d | 502 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; |
0a31afbc | 503 | wqi->fence_id = rq->seqno; |
44a28b1d DG |
504 | |
505 | kunmap_atomic(base); | |
44a28b1d DG |
506 | } |
507 | ||
10d2c3e2 DG |
508 | static int guc_ring_doorbell(struct i915_guc_client *gc) |
509 | { | |
510 | struct guc_process_desc *desc; | |
511 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
512 | union guc_doorbell_qw *db; | |
513 | int attempt = 2, ret = -EAGAIN; | |
514 | ||
515 | desc = gc->client_base + gc->proc_desc_offset; | |
516 | ||
517 | /* Update the tail so it is visible to GuC */ | |
518 | desc->tail = gc->wq_tail; | |
519 | ||
520 | /* current cookie */ | |
521 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
522 | db_cmp.cookie = gc->cookie; | |
523 | ||
524 | /* cookie to be updated */ | |
525 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
526 | db_exc.cookie = gc->cookie + 1; | |
527 | if (db_exc.cookie == 0) | |
528 | db_exc.cookie = 1; | |
529 | ||
530 | /* pointer of current doorbell cacheline */ | |
531 | db = gc->client_base + gc->doorbell_offset; | |
532 | ||
533 | while (attempt--) { | |
534 | /* lets ring the doorbell */ | |
535 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
536 | db_cmp.value_qw, db_exc.value_qw); | |
537 | ||
538 | /* if the exchange was successfully executed */ | |
539 | if (db_ret.value_qw == db_cmp.value_qw) { | |
540 | /* db was successfully rung */ | |
541 | gc->cookie = db_exc.cookie; | |
542 | ret = 0; | |
543 | break; | |
544 | } | |
545 | ||
546 | /* XXX: doorbell was lost and need to acquire it again */ | |
547 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
548 | break; | |
549 | ||
550 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", | |
551 | db_cmp.cookie, db_ret.cookie); | |
552 | ||
553 | /* update the cookie to newly read cookie from GuC */ | |
554 | db_cmp.cookie = db_ret.cookie; | |
555 | db_exc.cookie = db_ret.cookie + 1; | |
556 | if (db_exc.cookie == 0) | |
557 | db_exc.cookie = 1; | |
558 | } | |
559 | ||
560 | return ret; | |
561 | } | |
562 | ||
44a28b1d DG |
563 | /** |
564 | * i915_guc_submit() - Submit commands through GuC | |
feda33ef | 565 | * @rq: request associated with the commands |
44a28b1d | 566 | * |
7c2c270d DG |
567 | * Return: 0 on success, otherwise an errno. |
568 | * (Note: nonzero really shouldn't happen!) | |
569 | * | |
570 | * The caller must have already called i915_guc_wq_check_space() above | |
571 | * with a result of 0 (success) since the last request submission. This | |
572 | * guarantees that there is space in the work queue for the new request, | |
573 | * so enqueuing the item cannot fail. | |
574 | * | |
575 | * Bad Things Will Happen if the caller violates this protocol e.g. calls | |
576 | * submit() when check() says there's no space, or calls submit() multiple | |
577 | * times with no intervening check(). | |
578 | * | |
579 | * The only error here arises if the doorbell hardware isn't functioning | |
580 | * as expected, which really shouln't happen. | |
44a28b1d | 581 | */ |
7c2c270d | 582 | int i915_guc_submit(struct drm_i915_gem_request *rq) |
44a28b1d | 583 | { |
0b63bb14 | 584 | unsigned int engine_id = rq->engine->id; |
7c2c270d DG |
585 | struct intel_guc *guc = &rq->i915->guc; |
586 | struct i915_guc_client *client = guc->execbuf_client; | |
0a31afbc | 587 | int b_ret; |
44a28b1d | 588 | |
0a31afbc DG |
589 | guc_add_workqueue_item(client, rq); |
590 | b_ret = guc_ring_doorbell(client); | |
44a28b1d | 591 | |
397097b0 | 592 | client->submissions[engine_id] += 1; |
0a31afbc DG |
593 | client->retcode = b_ret; |
594 | if (b_ret) | |
44a28b1d | 595 | client->b_fail += 1; |
0a31afbc | 596 | |
397097b0 AD |
597 | guc->submissions[engine_id] += 1; |
598 | guc->last_seqno[engine_id] = rq->seqno; | |
44a28b1d | 599 | |
0a31afbc | 600 | return b_ret; |
44a28b1d DG |
601 | } |
602 | ||
603 | /* | |
604 | * Everything below here is concerned with setup & teardown, and is | |
605 | * therefore not part of the somewhat time-critical batch-submission | |
606 | * path of i915_guc_submit() above. | |
607 | */ | |
608 | ||
bac427f8 AD |
609 | /** |
610 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage | |
0daf556c | 611 | * @dev_priv: driver private data structure |
bac427f8 AD |
612 | * @size: size of object |
613 | * | |
614 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the | |
615 | * object needs to be pinned lifetime. Also we must pin it to gtt space other | |
616 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. | |
617 | * | |
618 | * Return: A drm_i915_gem_object if successful, otherwise NULL. | |
619 | */ | |
0daf556c DG |
620 | static struct drm_i915_gem_object * |
621 | gem_allocate_guc_obj(struct drm_i915_private *dev_priv, u32 size) | |
bac427f8 | 622 | { |
bac427f8 AD |
623 | struct drm_i915_gem_object *obj; |
624 | ||
0daf556c | 625 | obj = i915_gem_object_create(dev_priv->dev, size); |
fe3db79b | 626 | if (IS_ERR(obj)) |
bac427f8 AD |
627 | return NULL; |
628 | ||
629 | if (i915_gem_object_get_pages(obj)) { | |
630 | drm_gem_object_unreference(&obj->base); | |
631 | return NULL; | |
632 | } | |
633 | ||
634 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, | |
635 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { | |
636 | drm_gem_object_unreference(&obj->base); | |
637 | return NULL; | |
638 | } | |
639 | ||
640 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
641 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
642 | ||
643 | return obj; | |
644 | } | |
645 | ||
646 | /** | |
647 | * gem_release_guc_obj() - Release gem object allocated for GuC usage | |
648 | * @obj: gem obj to be released | |
81fd874e | 649 | */ |
bac427f8 AD |
650 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
651 | { | |
652 | if (!obj) | |
653 | return; | |
654 | ||
655 | if (i915_gem_obj_is_pinned(obj)) | |
656 | i915_gem_object_ggtt_unpin(obj); | |
657 | ||
658 | drm_gem_object_unreference(&obj->base); | |
659 | } | |
660 | ||
0daf556c DG |
661 | static void |
662 | guc_client_free(struct drm_i915_private *dev_priv, | |
663 | struct i915_guc_client *client) | |
44a28b1d | 664 | { |
44a28b1d DG |
665 | struct intel_guc *guc = &dev_priv->guc; |
666 | ||
667 | if (!client) | |
668 | return; | |
669 | ||
44a28b1d DG |
670 | /* |
671 | * XXX: wait for any outstanding submissions before freeing memory. | |
672 | * Be sure to drop any locks | |
673 | */ | |
674 | ||
0d92a6a4 DG |
675 | if (client->client_base) { |
676 | /* | |
a667429b DG |
677 | * If we got as far as setting up a doorbell, make sure we |
678 | * shut it down before unmapping & deallocating the memory. | |
0d92a6a4 | 679 | */ |
a667429b | 680 | guc_disable_doorbell(guc, client); |
0d92a6a4 DG |
681 | |
682 | kunmap(kmap_to_page(client->client_base)); | |
683 | } | |
684 | ||
44a28b1d DG |
685 | gem_release_guc_obj(client->client_obj); |
686 | ||
687 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
688 | guc_fini_ctx_desc(guc, client); | |
689 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); | |
690 | } | |
691 | ||
692 | kfree(client); | |
693 | } | |
694 | ||
4d75787b DG |
695 | /* |
696 | * Borrow the first client to set up & tear down every doorbell | |
697 | * in turn, to ensure that all doorbell h/w is (re)initialised. | |
698 | */ | |
699 | static void guc_init_doorbell_hw(struct intel_guc *guc) | |
700 | { | |
701 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
702 | struct i915_guc_client *client = guc->execbuf_client; | |
703 | uint16_t db_id, i; | |
704 | int err; | |
705 | ||
706 | db_id = client->doorbell_id; | |
707 | ||
708 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
709 | i915_reg_t drbreg = GEN8_DRBREGL(i); | |
710 | u32 value = I915_READ(drbreg); | |
711 | ||
712 | err = guc_update_doorbell_id(guc, client, i); | |
713 | ||
714 | /* Report update failure or unexpectedly active doorbell */ | |
715 | if (err || (i != db_id && (value & GUC_DOORBELL_ENABLED))) | |
716 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) was 0x%x, err %d\n", | |
717 | i, drbreg.reg, value, err); | |
718 | } | |
719 | ||
720 | /* Restore to original value */ | |
721 | err = guc_update_doorbell_id(guc, client, db_id); | |
722 | if (err) | |
723 | DRM_ERROR("Failed to restore doorbell to %d, err %d\n", | |
724 | db_id, err); | |
725 | ||
726 | for (i = 0; i < GUC_MAX_DOORBELLS; ++i) { | |
727 | i915_reg_t drbreg = GEN8_DRBREGL(i); | |
728 | u32 value = I915_READ(drbreg); | |
729 | ||
730 | if (i != db_id && (value & GUC_DOORBELL_ENABLED)) | |
731 | DRM_DEBUG_DRIVER("Doorbell %d (reg 0x%x) finally 0x%x\n", | |
732 | i, drbreg.reg, value); | |
733 | ||
734 | } | |
735 | } | |
736 | ||
44a28b1d DG |
737 | /** |
738 | * guc_client_alloc() - Allocate an i915_guc_client | |
0daf556c | 739 | * @dev_priv: driver private data structure |
44a28b1d DG |
740 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW |
741 | * The kernel client to replace ExecList submission is created with | |
742 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
743 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
744 | * @ctx: the context that owns the client (we use the default render |
745 | * context) | |
44a28b1d | 746 | * |
0d92a6a4 | 747 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d | 748 | */ |
0daf556c DG |
749 | static struct i915_guc_client * |
750 | guc_client_alloc(struct drm_i915_private *dev_priv, | |
751 | uint32_t priority, | |
752 | struct i915_gem_context *ctx) | |
44a28b1d DG |
753 | { |
754 | struct i915_guc_client *client; | |
44a28b1d DG |
755 | struct intel_guc *guc = &dev_priv->guc; |
756 | struct drm_i915_gem_object *obj; | |
a667429b | 757 | uint16_t db_id; |
44a28b1d DG |
758 | |
759 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
760 | if (!client) | |
761 | return NULL; | |
762 | ||
763 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
764 | client->priority = priority; | |
d1675198 | 765 | client->owner = ctx; |
44a28b1d DG |
766 | client->guc = guc; |
767 | ||
768 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
769 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
770 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
771 | client->ctx_index = GUC_INVALID_CTX_ID; | |
772 | goto err; | |
773 | } | |
774 | ||
775 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
0daf556c | 776 | obj = gem_allocate_guc_obj(dev_priv, GUC_DB_SIZE + GUC_WQ_SIZE); |
44a28b1d DG |
777 | if (!obj) |
778 | goto err; | |
779 | ||
0d92a6a4 | 780 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
44a28b1d | 781 | client->client_obj = obj; |
0d92a6a4 | 782 | client->client_base = kmap(i915_gem_object_get_page(obj, 0)); |
44a28b1d DG |
783 | client->wq_offset = GUC_DB_SIZE; |
784 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d | 785 | |
f10d69a7 DG |
786 | db_id = select_doorbell_register(guc, client->priority); |
787 | if (db_id == GUC_INVALID_DOORBELL_ID) | |
788 | /* XXX: evict a doorbell instead? */ | |
789 | goto err; | |
790 | ||
44a28b1d DG |
791 | client->doorbell_offset = select_doorbell_cacheline(guc); |
792 | ||
793 | /* | |
794 | * Since the doorbell only requires a single cacheline, we can save | |
795 | * space by putting the application process descriptor in the same | |
796 | * page. Use the half of the page that doesn't include the doorbell. | |
797 | */ | |
798 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
799 | client->proc_desc_offset = 0; | |
800 | else | |
801 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
802 | ||
44a28b1d DG |
803 | guc_init_proc_desc(guc, client); |
804 | guc_init_ctx_desc(guc, client); | |
a667429b | 805 | if (guc_init_doorbell(guc, client, db_id)) |
44a28b1d DG |
806 | goto err; |
807 | ||
a667429b DG |
808 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u\n", |
809 | priority, client, client->ctx_index); | |
810 | DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%x\n", | |
811 | client->doorbell_id, client->doorbell_offset); | |
44a28b1d DG |
812 | |
813 | return client; | |
814 | ||
815 | err: | |
816 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); | |
817 | ||
0daf556c | 818 | guc_client_free(dev_priv, client); |
44a28b1d DG |
819 | return NULL; |
820 | } | |
821 | ||
4c7e77fc AD |
822 | static void guc_create_log(struct intel_guc *guc) |
823 | { | |
824 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
825 | struct drm_i915_gem_object *obj; | |
826 | unsigned long offset; | |
827 | uint32_t size, flags; | |
828 | ||
829 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) | |
830 | return; | |
831 | ||
832 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) | |
833 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
834 | ||
835 | /* The first page is to save log buffer state. Allocate one | |
836 | * extra page for others in case for overlap */ | |
837 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
838 | GUC_LOG_ISR_PAGES + 1 + | |
839 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
840 | ||
841 | obj = guc->log_obj; | |
842 | if (!obj) { | |
0daf556c | 843 | obj = gem_allocate_guc_obj(dev_priv, size); |
4c7e77fc AD |
844 | if (!obj) { |
845 | /* logging will be off */ | |
846 | i915.guc_log_level = -1; | |
847 | return; | |
848 | } | |
849 | ||
850 | guc->log_obj = obj; | |
851 | } | |
852 | ||
853 | /* each allocated unit is a page */ | |
854 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
855 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
856 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
857 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
858 | ||
859 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ | |
860 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; | |
861 | } | |
862 | ||
463704d0 AD |
863 | static void init_guc_policies(struct guc_policies *policies) |
864 | { | |
865 | struct guc_policy *policy; | |
866 | u32 p, i; | |
867 | ||
868 | policies->dpc_promote_time = 500000; | |
869 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
870 | ||
871 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 872 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
873 | policy = &policies->policy[p][i]; |
874 | ||
875 | policy->execution_quantum = 1000000; | |
876 | policy->preemption_time = 500000; | |
877 | policy->fault_time = 250000; | |
878 | policy->policy_flags = 0; | |
879 | } | |
880 | } | |
881 | ||
882 | policies->is_valid = 1; | |
883 | } | |
884 | ||
68371a95 AD |
885 | static void guc_create_ads(struct intel_guc *guc) |
886 | { | |
887 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
888 | struct drm_i915_gem_object *obj; | |
889 | struct guc_ads *ads; | |
463704d0 | 890 | struct guc_policies *policies; |
5c148e04 | 891 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 892 | struct intel_engine_cs *engine; |
68371a95 | 893 | struct page *page; |
b4ac5afc | 894 | u32 size; |
68371a95 AD |
895 | |
896 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
897 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
898 | sizeof(struct guc_mmio_reg_state) + | |
899 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 AD |
900 | |
901 | obj = guc->ads_obj; | |
902 | if (!obj) { | |
0daf556c | 903 | obj = gem_allocate_guc_obj(dev_priv, PAGE_ALIGN(size)); |
68371a95 AD |
904 | if (!obj) |
905 | return; | |
906 | ||
907 | guc->ads_obj = obj; | |
908 | } | |
909 | ||
910 | page = i915_gem_object_get_page(obj, 0); | |
911 | ads = kmap(page); | |
912 | ||
913 | /* | |
914 | * The GuC requires a "Golden Context" when it reinitialises | |
915 | * engines after a reset. Here we use the Render ring default | |
916 | * context, which must already exist and be pinned in the GGTT, | |
917 | * so its address won't change after we've told the GuC where | |
918 | * to find it. | |
919 | */ | |
4a570db5 | 920 | engine = &dev_priv->engine[RCS]; |
e2f80391 | 921 | ads->golden_context_lrca = engine->status_page.gfx_addr; |
68371a95 | 922 | |
b4ac5afc | 923 | for_each_engine(engine, dev_priv) |
e2f80391 | 924 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 925 | |
463704d0 AD |
926 | /* GuC scheduling policies */ |
927 | policies = (void *)ads + sizeof(struct guc_ads); | |
928 | init_guc_policies(policies); | |
929 | ||
930 | ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + | |
931 | sizeof(struct guc_ads); | |
932 | ||
5c148e04 AD |
933 | /* MMIO reg state */ |
934 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
935 | ||
b4ac5afc | 936 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
937 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
938 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
939 | |
940 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 941 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
942 | } |
943 | ||
944 | ads->reg_state_addr = ads->scheduler_policies + | |
945 | sizeof(struct guc_policies); | |
946 | ||
947 | ads->reg_state_buffer = ads->reg_state_addr + | |
948 | sizeof(struct guc_mmio_reg_state); | |
949 | ||
68371a95 AD |
950 | kunmap(page); |
951 | } | |
952 | ||
bac427f8 AD |
953 | /* |
954 | * Set up the memory resources to be shared with the GuC. At this point, | |
955 | * we require just one object that can be mapped through the GGTT. | |
956 | */ | |
beffa517 | 957 | int i915_guc_submission_init(struct drm_i915_private *dev_priv) |
bac427f8 | 958 | { |
bac427f8 AD |
959 | const size_t ctxsize = sizeof(struct guc_context_desc); |
960 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
961 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
962 | struct intel_guc *guc = &dev_priv->guc; | |
963 | ||
29fb72c7 DG |
964 | /* Wipe bitmap & delete client in case of reinitialisation */ |
965 | bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); | |
beffa517 | 966 | i915_guc_submission_disable(dev_priv); |
29fb72c7 | 967 | |
bac427f8 AD |
968 | if (!i915.enable_guc_submission) |
969 | return 0; /* not enabled */ | |
970 | ||
971 | if (guc->ctx_pool_obj) | |
972 | return 0; /* already allocated */ | |
973 | ||
0daf556c | 974 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv, gemsize); |
bac427f8 AD |
975 | if (!guc->ctx_pool_obj) |
976 | return -ENOMEM; | |
977 | ||
978 | ida_init(&guc->ctx_ids); | |
4c7e77fc | 979 | guc_create_log(guc); |
68371a95 AD |
980 | guc_create_ads(guc); |
981 | ||
bac427f8 AD |
982 | return 0; |
983 | } | |
984 | ||
beffa517 | 985 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv) |
44a28b1d | 986 | { |
44a28b1d DG |
987 | struct intel_guc *guc = &dev_priv->guc; |
988 | struct i915_guc_client *client; | |
989 | ||
990 | /* client for execbuf submission */ | |
0daf556c | 991 | client = guc_client_alloc(dev_priv, |
0ca5fa3a CW |
992 | GUC_CTX_PRIORITY_KMD_NORMAL, |
993 | dev_priv->kernel_context); | |
44a28b1d DG |
994 | if (!client) { |
995 | DRM_ERROR("Failed to create execbuf guc_client\n"); | |
996 | return -ENOMEM; | |
997 | } | |
998 | ||
999 | guc->execbuf_client = client; | |
f5d3c3ea | 1000 | host2guc_sample_forcewake(guc, client); |
4d75787b | 1001 | guc_init_doorbell_hw(guc); |
f5d3c3ea | 1002 | |
44a28b1d DG |
1003 | return 0; |
1004 | } | |
1005 | ||
beffa517 | 1006 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv) |
44a28b1d | 1007 | { |
44a28b1d DG |
1008 | struct intel_guc *guc = &dev_priv->guc; |
1009 | ||
0daf556c | 1010 | guc_client_free(dev_priv, guc->execbuf_client); |
44a28b1d DG |
1011 | guc->execbuf_client = NULL; |
1012 | } | |
1013 | ||
beffa517 | 1014 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv) |
bac427f8 | 1015 | { |
bac427f8 AD |
1016 | struct intel_guc *guc = &dev_priv->guc; |
1017 | ||
68371a95 AD |
1018 | gem_release_guc_obj(dev_priv->guc.ads_obj); |
1019 | guc->ads_obj = NULL; | |
1020 | ||
4c7e77fc AD |
1021 | gem_release_guc_obj(dev_priv->guc.log_obj); |
1022 | guc->log_obj = NULL; | |
1023 | ||
bac427f8 AD |
1024 | if (guc->ctx_pool_obj) |
1025 | ida_destroy(&guc->ctx_ids); | |
1026 | gem_release_guc_obj(guc->ctx_pool_obj); | |
1027 | guc->ctx_pool_obj = NULL; | |
1028 | } | |
a1c41994 AD |
1029 | |
1030 | /** | |
1031 | * intel_guc_suspend() - notify GuC entering suspend state | |
1032 | * @dev: drm device | |
1033 | */ | |
1034 | int intel_guc_suspend(struct drm_device *dev) | |
1035 | { | |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1037 | struct intel_guc *guc = &dev_priv->guc; | |
e2efd130 | 1038 | struct i915_gem_context *ctx; |
a1c41994 AD |
1039 | u32 data[3]; |
1040 | ||
fce91f22 | 1041 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1042 | return 0; |
1043 | ||
ed54c1a1 | 1044 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1045 | |
1046 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; | |
1047 | /* any value greater than GUC_POWER_D0 */ | |
1048 | data[1] = GUC_POWER_D1; | |
1049 | /* first page is shared data with GuC */ | |
1050 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
1051 | ||
1052 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1053 | } | |
1054 | ||
1055 | ||
1056 | /** | |
1057 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1058 | * @dev: drm device | |
1059 | */ | |
1060 | int intel_guc_resume(struct drm_device *dev) | |
1061 | { | |
1062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1063 | struct intel_guc *guc = &dev_priv->guc; | |
e2efd130 | 1064 | struct i915_gem_context *ctx; |
a1c41994 AD |
1065 | u32 data[3]; |
1066 | ||
fce91f22 | 1067 | if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS) |
a1c41994 AD |
1068 | return 0; |
1069 | ||
ed54c1a1 | 1070 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1071 | |
1072 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; | |
1073 | data[1] = GUC_POWER_D0; | |
1074 | /* first page is shared data with GuC */ | |
1075 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
1076 | ||
1077 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1078 | } |