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bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
26 | #include "i915_drv.h" | |
27 | #include "intel_guc.h" | |
28 | ||
44a28b1d | 29 | /** |
feda33ef | 30 | * DOC: GuC-based command submission |
44a28b1d DG |
31 | * |
32 | * i915_guc_client: | |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
37 | * is mapped to client space. So the client can write Work Item then ring the | |
38 | * doorbell. | |
39 | * | |
40 | * To simplify the implementation, we allocate one gem object that contains all | |
41 | * pages for doorbell, process descriptor and workqueue. | |
42 | * | |
43 | * The Scratch registers: | |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
47 | * Firmware writes a success/fail code back to the action register after | |
48 | * processes the request. The kernel driver polls waiting for this update and | |
49 | * then proceeds. | |
50 | * See host2guc_action() | |
51 | * | |
52 | * Doorbells: | |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
54 | * mapped into process space. | |
55 | * | |
56 | * Work Items: | |
57 | * There are several types of work items that the host may place into a | |
58 | * workqueue, each with its own requirements and limitations. Currently only | |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
61 | * ELSP context descriptor dword into Work Item. | |
62 | * See guc_add_workqueue_item() | |
63 | * | |
64 | */ | |
65 | ||
66 | /* | |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) | |
68 | * Return true if it contains a response rather than a command | |
69 | */ | |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, | |
71 | u32 *status) | |
72 | { | |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); | |
74 | *status = val; | |
75 | return GUC2HOST_IS_RESPONSE(val); | |
76 | } | |
77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
81 | u32 status; | |
82 | int i; | |
83 | int ret; | |
84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) | |
86 | return -EINVAL; | |
87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
44a28b1d DG |
89 | |
90 | dev_priv->guc.action_count += 1; | |
91 | dev_priv->guc.action_cmd = data[0]; | |
92 | ||
93 | for (i = 0; i < len; i++) | |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); | |
95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); | |
97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); | |
99 | ||
100 | /* No HOST2GUC command should take longer than 10ms */ | |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); | |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { | |
103 | /* | |
104 | * Either the GuC explicitly returned an error (which | |
105 | * we convert to -EIO here) or no response at all was | |
106 | * received within the timeout limit (-ETIMEDOUT) | |
107 | */ | |
108 | if (ret != -ETIMEDOUT) | |
109 | ret = -EIO; | |
110 | ||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " | |
112 | "status=0x%08X response=0x%08X\n", | |
113 | data[0], ret, status, | |
114 | I915_READ(SOFT_SCRATCH(15))); | |
115 | ||
116 | dev_priv->guc.action_fail += 1; | |
117 | dev_priv->guc.action_err = ret; | |
118 | } | |
119 | dev_priv->guc.action_status = status; | |
120 | ||
44a28b1d DG |
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | /* | |
127 | * Tell the GuC to allocate or deallocate a specific doorbell | |
128 | */ | |
129 | ||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, | |
131 | struct i915_guc_client *client) | |
132 | { | |
133 | u32 data[2]; | |
134 | ||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; | |
136 | data[1] = client->ctx_index; | |
137 | ||
138 | return host2guc_action(guc, data, 2); | |
139 | } | |
140 | ||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, | |
142 | struct i915_guc_client *client) | |
143 | { | |
144 | u32 data[2]; | |
145 | ||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; | |
147 | data[1] = client->ctx_index; | |
148 | ||
149 | return host2guc_action(guc, data, 2); | |
150 | } | |
151 | ||
f5d3c3ea AD |
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
153 | struct i915_guc_client *client) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
93f25318 | 156 | struct drm_device *dev = dev_priv->dev; |
f5d3c3ea AD |
157 | u32 data[2]; |
158 | ||
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; | |
93f25318 | 160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
06e668ac MK |
161 | if (!intel_enable_rc6(dev) || |
162 | NEEDS_WaRsDisableCoarsePowerGating(dev)) | |
93f25318 AD |
163 | data[1] = 0; |
164 | else | |
165 | /* bit 0 and 1 are for Render and Media domain separately */ | |
166 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; | |
167 | ||
168 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
f5d3c3ea AD |
169 | } |
170 | ||
44a28b1d DG |
171 | /* |
172 | * Initialise, update, or clear doorbell data shared with the GuC | |
173 | * | |
174 | * These functions modify shared data and so need access to the mapped | |
175 | * client object which contains the page being used for the doorbell | |
176 | */ | |
177 | ||
178 | static void guc_init_doorbell(struct intel_guc *guc, | |
179 | struct i915_guc_client *client) | |
180 | { | |
181 | struct guc_doorbell_info *doorbell; | |
44a28b1d | 182 | |
0d92a6a4 | 183 | doorbell = client->client_base + client->doorbell_offset; |
44a28b1d | 184 | |
0d92a6a4 | 185 | doorbell->db_status = GUC_DOORBELL_ENABLED; |
44a28b1d | 186 | doorbell->cookie = 0; |
44a28b1d DG |
187 | } |
188 | ||
189 | static int guc_ring_doorbell(struct i915_guc_client *gc) | |
190 | { | |
191 | struct guc_process_desc *desc; | |
192 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
193 | union guc_doorbell_qw *db; | |
44a28b1d DG |
194 | int attempt = 2, ret = -EAGAIN; |
195 | ||
0d92a6a4 | 196 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d DG |
197 | |
198 | /* Update the tail so it is visible to GuC */ | |
199 | desc->tail = gc->wq_tail; | |
200 | ||
201 | /* current cookie */ | |
202 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
203 | db_cmp.cookie = gc->cookie; | |
204 | ||
205 | /* cookie to be updated */ | |
206 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
207 | db_exc.cookie = gc->cookie + 1; | |
208 | if (db_exc.cookie == 0) | |
209 | db_exc.cookie = 1; | |
210 | ||
211 | /* pointer of current doorbell cacheline */ | |
0d92a6a4 | 212 | db = gc->client_base + gc->doorbell_offset; |
44a28b1d DG |
213 | |
214 | while (attempt--) { | |
215 | /* lets ring the doorbell */ | |
216 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
217 | db_cmp.value_qw, db_exc.value_qw); | |
218 | ||
219 | /* if the exchange was successfully executed */ | |
220 | if (db_ret.value_qw == db_cmp.value_qw) { | |
221 | /* db was successfully rung */ | |
222 | gc->cookie = db_exc.cookie; | |
223 | ret = 0; | |
224 | break; | |
225 | } | |
226 | ||
227 | /* XXX: doorbell was lost and need to acquire it again */ | |
228 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
229 | break; | |
230 | ||
231 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", | |
232 | db_cmp.cookie, db_ret.cookie); | |
233 | ||
234 | /* update the cookie to newly read cookie from GuC */ | |
235 | db_cmp.cookie = db_ret.cookie; | |
236 | db_exc.cookie = db_ret.cookie + 1; | |
237 | if (db_exc.cookie == 0) | |
238 | db_exc.cookie = 1; | |
239 | } | |
240 | ||
a7e02199 AD |
241 | /* Finally, update the cached copy of the GuC's WQ head */ |
242 | gc->wq_head = desc->head; | |
243 | ||
44a28b1d DG |
244 | return ret; |
245 | } | |
246 | ||
247 | static void guc_disable_doorbell(struct intel_guc *guc, | |
248 | struct i915_guc_client *client) | |
249 | { | |
250 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
251 | struct guc_doorbell_info *doorbell; | |
f0f59a00 | 252 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
44a28b1d DG |
253 | int value; |
254 | ||
0d92a6a4 | 255 | doorbell = client->client_base + client->doorbell_offset; |
44a28b1d | 256 | |
0d92a6a4 | 257 | doorbell->db_status = GUC_DOORBELL_DISABLED; |
44a28b1d DG |
258 | |
259 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); | |
260 | ||
261 | value = I915_READ(drbreg); | |
262 | WARN_ON((value & GEN8_DRB_VALID) != 0); | |
263 | ||
264 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); | |
265 | I915_WRITE(drbreg, 0); | |
266 | ||
267 | /* XXX: wait for any interrupts */ | |
268 | /* XXX: wait for workqueue to drain */ | |
269 | } | |
270 | ||
271 | /* | |
272 | * Select, assign and relase doorbell cachelines | |
273 | * | |
274 | * These functions track which doorbell cachelines are in use. | |
275 | * The data they manipulate is protected by the host2guc lock. | |
276 | */ | |
277 | ||
278 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
279 | { | |
280 | const uint32_t cacheline_size = cache_line_size(); | |
281 | uint32_t offset; | |
282 | ||
44a28b1d DG |
283 | /* Doorbell uses a single cache line within a page */ |
284 | offset = offset_in_page(guc->db_cacheline); | |
285 | ||
286 | /* Moving to next cache line to reduce contention */ | |
287 | guc->db_cacheline += cacheline_size; | |
288 | ||
44a28b1d DG |
289 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
290 | offset, guc->db_cacheline, cacheline_size); | |
291 | ||
292 | return offset; | |
293 | } | |
294 | ||
295 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) | |
296 | { | |
297 | /* | |
298 | * The bitmap is split into two halves; the first half is used for | |
299 | * normal priority contexts, the second half for high-priority ones. | |
300 | * Note that logically higher priorities are numerically less than | |
301 | * normal ones, so the test below means "is it high-priority?" | |
302 | */ | |
303 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
304 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
305 | const uint16_t start = hi_pri ? half : 0; | |
306 | const uint16_t end = start + half; | |
307 | uint16_t id; | |
308 | ||
44a28b1d DG |
309 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
310 | if (id == end) | |
311 | id = GUC_INVALID_DOORBELL_ID; | |
312 | else | |
313 | bitmap_set(guc->doorbell_bitmap, id, 1); | |
44a28b1d DG |
314 | |
315 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
316 | hi_pri ? "high" : "normal", id); | |
317 | ||
318 | return id; | |
319 | } | |
320 | ||
321 | static void release_doorbell(struct intel_guc *guc, uint16_t id) | |
322 | { | |
44a28b1d | 323 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
44a28b1d DG |
324 | } |
325 | ||
326 | /* | |
327 | * Initialise the process descriptor shared with the GuC firmware. | |
328 | */ | |
329 | static void guc_init_proc_desc(struct intel_guc *guc, | |
330 | struct i915_guc_client *client) | |
331 | { | |
332 | struct guc_process_desc *desc; | |
44a28b1d | 333 | |
0d92a6a4 | 334 | desc = client->client_base + client->proc_desc_offset; |
44a28b1d DG |
335 | |
336 | memset(desc, 0, sizeof(*desc)); | |
337 | ||
338 | /* | |
339 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
340 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
341 | * space for kernel clients (map on demand instead? May make debug | |
342 | * easier to have it mapped). | |
343 | */ | |
344 | desc->wq_base_addr = 0; | |
345 | desc->db_base_addr = 0; | |
346 | ||
347 | desc->context_id = client->ctx_index; | |
348 | desc->wq_size_bytes = client->wq_size; | |
349 | desc->wq_status = WQ_STATUS_ACTIVE; | |
350 | desc->priority = client->priority; | |
44a28b1d DG |
351 | } |
352 | ||
353 | /* | |
354 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
355 | * | |
356 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
357 | * data structures relating to this client (doorbell, process descriptor, | |
358 | * write queue, etc). | |
359 | */ | |
360 | ||
361 | static void guc_init_ctx_desc(struct intel_guc *guc, | |
362 | struct i915_guc_client *client) | |
363 | { | |
397097b0 | 364 | struct drm_i915_private *dev_priv = guc_to_i915(guc); |
e2f80391 | 365 | struct intel_engine_cs *engine; |
d1675198 | 366 | struct intel_context *ctx = client->owner; |
44a28b1d DG |
367 | struct guc_context_desc desc; |
368 | struct sg_table *sg; | |
c3232b18 | 369 | enum intel_engine_id id; |
44a28b1d DG |
370 | |
371 | memset(&desc, 0, sizeof(desc)); | |
372 | ||
373 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
374 | desc.context_id = client->ctx_index; | |
375 | desc.priority = client->priority; | |
44a28b1d DG |
376 | desc.db_id = client->doorbell_id; |
377 | ||
c3232b18 | 378 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 379 | struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id]; |
d1675198 AD |
380 | struct drm_i915_gem_object *obj; |
381 | uint64_t ctx_desc; | |
382 | ||
383 | /* TODO: We have a design issue to be solved here. Only when we | |
384 | * receive the first batch, we know which engine is used by the | |
385 | * user. But here GuC expects the lrc and ring to be pinned. It | |
386 | * is not an issue for default context, which is the only one | |
387 | * for now who owns a GuC client. But for future owner of GuC | |
388 | * client, need to make sure lrc is pinned prior to enter here. | |
389 | */ | |
c3232b18 | 390 | obj = ctx->engine[id].state; |
d1675198 AD |
391 | if (!obj) |
392 | break; /* XXX: continue? */ | |
393 | ||
e2f80391 | 394 | ctx_desc = intel_lr_context_descriptor(ctx, engine); |
d1675198 AD |
395 | lrc->context_desc = (u32)ctx_desc; |
396 | ||
397 | /* The state page is after PPHWSP */ | |
398 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + | |
399 | LRC_STATE_PN * PAGE_SIZE; | |
400 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | | |
e2f80391 | 401 | (engine->guc_id << GUC_ELC_ENGINE_OFFSET); |
d1675198 | 402 | |
c3232b18 | 403 | obj = ctx->engine[id].ringbuf->obj; |
d1675198 AD |
404 | |
405 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); | |
406 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; | |
407 | lrc->ring_next_free_location = lrc->ring_begin; | |
408 | lrc->ring_current_tail_pointer_value = 0; | |
409 | ||
e2f80391 | 410 | desc.engines_used |= (1 << engine->guc_id); |
d1675198 AD |
411 | } |
412 | ||
413 | WARN_ON(desc.engines_used == 0); | |
414 | ||
44a28b1d DG |
415 | /* |
416 | * The CPU address is only needed at certain points, so kmap_atomic on | |
417 | * demand instead of storing it in the ctx descriptor. | |
418 | * XXX: May make debug easier to have it mapped | |
419 | */ | |
420 | desc.db_trigger_cpu = 0; | |
421 | desc.db_trigger_uk = client->doorbell_offset + | |
422 | i915_gem_obj_ggtt_offset(client->client_obj); | |
423 | desc.db_trigger_phy = client->doorbell_offset + | |
424 | sg_dma_address(client->client_obj->pages->sgl); | |
425 | ||
426 | desc.process_desc = client->proc_desc_offset + | |
427 | i915_gem_obj_ggtt_offset(client->client_obj); | |
428 | ||
429 | desc.wq_addr = client->wq_offset + | |
430 | i915_gem_obj_ggtt_offset(client->client_obj); | |
431 | ||
432 | desc.wq_size = client->wq_size; | |
433 | ||
434 | /* | |
435 | * XXX: Take LRCs from an existing intel_context if this is not an | |
436 | * IsKMDCreatedContext client | |
437 | */ | |
438 | desc.desc_private = (uintptr_t)client; | |
439 | ||
440 | /* Pool context is pinned already */ | |
441 | sg = guc->ctx_pool_obj->pages; | |
442 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
443 | sizeof(desc) * client->ctx_index); | |
444 | } | |
445 | ||
446 | static void guc_fini_ctx_desc(struct intel_guc *guc, | |
447 | struct i915_guc_client *client) | |
448 | { | |
449 | struct guc_context_desc desc; | |
450 | struct sg_table *sg; | |
451 | ||
452 | memset(&desc, 0, sizeof(desc)); | |
453 | ||
454 | sg = guc->ctx_pool_obj->pages; | |
455 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
456 | sizeof(desc) * client->ctx_index); | |
457 | } | |
458 | ||
a7e02199 | 459 | int i915_guc_wq_check_space(struct i915_guc_client *gc) |
44a28b1d DG |
460 | { |
461 | struct guc_process_desc *desc; | |
44a28b1d | 462 | u32 size = sizeof(struct guc_wq_item); |
5a843307 | 463 | int ret = -ETIMEDOUT, timeout_counter = 200; |
44a28b1d | 464 | |
a7e02199 AD |
465 | if (!gc) |
466 | return 0; | |
467 | ||
468 | /* Quickly return if wq space is available since last time we cache the | |
469 | * head position. */ | |
470 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) | |
471 | return 0; | |
472 | ||
0d92a6a4 | 473 | desc = gc->client_base + gc->proc_desc_offset; |
44a28b1d DG |
474 | |
475 | while (timeout_counter-- > 0) { | |
a7e02199 | 476 | gc->wq_head = desc->head; |
44a28b1d | 477 | |
a7e02199 | 478 | if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) { |
5a843307 | 479 | ret = 0; |
a7e02199 | 480 | break; |
44a28b1d | 481 | } |
5a843307 AD |
482 | |
483 | if (timeout_counter) | |
484 | usleep_range(1000, 2000); | |
44a28b1d DG |
485 | }; |
486 | ||
44a28b1d DG |
487 | return ret; |
488 | } | |
489 | ||
490 | static int guc_add_workqueue_item(struct i915_guc_client *gc, | |
491 | struct drm_i915_gem_request *rq) | |
492 | { | |
44a28b1d DG |
493 | struct guc_wq_item *wqi; |
494 | void *base; | |
a7e02199 AD |
495 | u32 tail, wq_len, wq_off, space; |
496 | ||
497 | space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size); | |
498 | if (WARN_ON(space < sizeof(struct guc_wq_item))) | |
499 | return -ENOSPC; /* shouldn't happen */ | |
44a28b1d | 500 | |
a7e02199 AD |
501 | /* postincrement WQ tail for next time */ |
502 | wq_off = gc->wq_tail; | |
503 | gc->wq_tail += sizeof(struct guc_wq_item); | |
504 | gc->wq_tail &= gc->wq_size - 1; | |
44a28b1d DG |
505 | |
506 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
507 | * should not have the case where structure wqi is across page, neither | |
508 | * wrapped to the beginning. This simplifies the implementation below. | |
509 | * | |
510 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
511 | * workqueue buffer dw by dw. | |
512 | */ | |
513 | WARN_ON(sizeof(struct guc_wq_item) != 16); | |
514 | WARN_ON(wq_off & 3); | |
515 | ||
516 | /* wq starts from the page after doorbell / process_desc */ | |
517 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, | |
518 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); | |
519 | wq_off &= PAGE_SIZE - 1; | |
520 | wqi = (struct guc_wq_item *)((char *)base + wq_off); | |
521 | ||
522 | /* len does not include the header */ | |
523 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; | |
524 | wqi->header = WQ_TYPE_INORDER | | |
525 | (wq_len << WQ_LEN_SHIFT) | | |
4a570db5 | 526 | (rq->engine->guc_id << WQ_TARGET_SHIFT) | |
44a28b1d DG |
527 | WQ_NO_WCFLUSH_WAIT; |
528 | ||
529 | /* The GuC wants only the low-order word of the context descriptor */ | |
4a570db5 TU |
530 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, |
531 | rq->engine); | |
44a28b1d DG |
532 | |
533 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
534 | tail = rq->ringbuf->tail >> 3; | |
535 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; | |
536 | wqi->fence_id = 0; /*XXX: what fence to be here */ | |
537 | ||
538 | kunmap_atomic(base); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | /** | |
544 | * i915_guc_submit() - Submit commands through GuC | |
545 | * @client: the guc client where commands will go through | |
feda33ef | 546 | * @rq: request associated with the commands |
44a28b1d DG |
547 | * |
548 | * Return: 0 if succeed | |
549 | */ | |
550 | int i915_guc_submit(struct i915_guc_client *client, | |
551 | struct drm_i915_gem_request *rq) | |
552 | { | |
553 | struct intel_guc *guc = client->guc; | |
4a570db5 | 554 | unsigned int engine_id = rq->engine->guc_id; |
44a28b1d DG |
555 | int q_ret, b_ret; |
556 | ||
44a28b1d DG |
557 | q_ret = guc_add_workqueue_item(client, rq); |
558 | if (q_ret == 0) | |
559 | b_ret = guc_ring_doorbell(client); | |
560 | ||
397097b0 | 561 | client->submissions[engine_id] += 1; |
44a28b1d DG |
562 | if (q_ret) { |
563 | client->q_fail += 1; | |
564 | client->retcode = q_ret; | |
565 | } else if (b_ret) { | |
566 | client->b_fail += 1; | |
567 | client->retcode = q_ret = b_ret; | |
568 | } else { | |
569 | client->retcode = 0; | |
570 | } | |
397097b0 AD |
571 | guc->submissions[engine_id] += 1; |
572 | guc->last_seqno[engine_id] = rq->seqno; | |
44a28b1d DG |
573 | |
574 | return q_ret; | |
575 | } | |
576 | ||
577 | /* | |
578 | * Everything below here is concerned with setup & teardown, and is | |
579 | * therefore not part of the somewhat time-critical batch-submission | |
580 | * path of i915_guc_submit() above. | |
581 | */ | |
582 | ||
bac427f8 AD |
583 | /** |
584 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage | |
585 | * @dev: drm device | |
586 | * @size: size of object | |
587 | * | |
588 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the | |
589 | * object needs to be pinned lifetime. Also we must pin it to gtt space other | |
590 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. | |
591 | * | |
592 | * Return: A drm_i915_gem_object if successful, otherwise NULL. | |
593 | */ | |
594 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, | |
595 | u32 size) | |
596 | { | |
597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
598 | struct drm_i915_gem_object *obj; | |
599 | ||
600 | obj = i915_gem_alloc_object(dev, size); | |
601 | if (!obj) | |
602 | return NULL; | |
603 | ||
604 | if (i915_gem_object_get_pages(obj)) { | |
605 | drm_gem_object_unreference(&obj->base); | |
606 | return NULL; | |
607 | } | |
608 | ||
609 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, | |
610 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { | |
611 | drm_gem_object_unreference(&obj->base); | |
612 | return NULL; | |
613 | } | |
614 | ||
615 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
616 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
617 | ||
618 | return obj; | |
619 | } | |
620 | ||
621 | /** | |
622 | * gem_release_guc_obj() - Release gem object allocated for GuC usage | |
623 | * @obj: gem obj to be released | |
81fd874e | 624 | */ |
bac427f8 AD |
625 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
626 | { | |
627 | if (!obj) | |
628 | return; | |
629 | ||
630 | if (i915_gem_obj_is_pinned(obj)) | |
631 | i915_gem_object_ggtt_unpin(obj); | |
632 | ||
633 | drm_gem_object_unreference(&obj->base); | |
634 | } | |
635 | ||
44a28b1d DG |
636 | static void guc_client_free(struct drm_device *dev, |
637 | struct i915_guc_client *client) | |
638 | { | |
639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
640 | struct intel_guc *guc = &dev_priv->guc; | |
641 | ||
642 | if (!client) | |
643 | return; | |
644 | ||
44a28b1d DG |
645 | /* |
646 | * XXX: wait for any outstanding submissions before freeing memory. | |
647 | * Be sure to drop any locks | |
648 | */ | |
649 | ||
0d92a6a4 DG |
650 | if (client->client_base) { |
651 | /* | |
652 | * If we got as far as setting up a doorbell, make sure | |
653 | * we shut it down before unmapping & deallocating the | |
654 | * memory. So first disable the doorbell, then tell the | |
655 | * GuC that we've finished with it, finally deallocate | |
656 | * it in our bitmap | |
657 | */ | |
658 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { | |
659 | guc_disable_doorbell(guc, client); | |
660 | host2guc_release_doorbell(guc, client); | |
661 | release_doorbell(guc, client->doorbell_id); | |
662 | } | |
663 | ||
664 | kunmap(kmap_to_page(client->client_base)); | |
665 | } | |
666 | ||
44a28b1d DG |
667 | gem_release_guc_obj(client->client_obj); |
668 | ||
669 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
670 | guc_fini_ctx_desc(guc, client); | |
671 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); | |
672 | } | |
673 | ||
674 | kfree(client); | |
675 | } | |
676 | ||
677 | /** | |
678 | * guc_client_alloc() - Allocate an i915_guc_client | |
679 | * @dev: drm device | |
680 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW | |
681 | * The kernel client to replace ExecList submission is created with | |
682 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
683 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
684 | * @ctx: the context that owns the client (we use the default render |
685 | * context) | |
44a28b1d | 686 | * |
0d92a6a4 | 687 | * Return: An i915_guc_client object if success, else NULL. |
44a28b1d DG |
688 | */ |
689 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, | |
d1675198 AD |
690 | uint32_t priority, |
691 | struct intel_context *ctx) | |
44a28b1d DG |
692 | { |
693 | struct i915_guc_client *client; | |
694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
695 | struct intel_guc *guc = &dev_priv->guc; | |
696 | struct drm_i915_gem_object *obj; | |
697 | ||
698 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
699 | if (!client) | |
700 | return NULL; | |
701 | ||
702 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
703 | client->priority = priority; | |
d1675198 | 704 | client->owner = ctx; |
44a28b1d DG |
705 | client->guc = guc; |
706 | ||
707 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
708 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
709 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
710 | client->ctx_index = GUC_INVALID_CTX_ID; | |
711 | goto err; | |
712 | } | |
713 | ||
714 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
715 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); | |
716 | if (!obj) | |
717 | goto err; | |
718 | ||
0d92a6a4 | 719 | /* We'll keep just the first (doorbell/proc) page permanently kmap'd. */ |
44a28b1d | 720 | client->client_obj = obj; |
0d92a6a4 | 721 | client->client_base = kmap(i915_gem_object_get_page(obj, 0)); |
44a28b1d DG |
722 | client->wq_offset = GUC_DB_SIZE; |
723 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d DG |
724 | |
725 | client->doorbell_offset = select_doorbell_cacheline(guc); | |
726 | ||
727 | /* | |
728 | * Since the doorbell only requires a single cacheline, we can save | |
729 | * space by putting the application process descriptor in the same | |
730 | * page. Use the half of the page that doesn't include the doorbell. | |
731 | */ | |
732 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
733 | client->proc_desc_offset = 0; | |
734 | else | |
735 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
736 | ||
737 | client->doorbell_id = assign_doorbell(guc, client->priority); | |
738 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) | |
739 | /* XXX: evict a doorbell instead */ | |
740 | goto err; | |
741 | ||
742 | guc_init_proc_desc(guc, client); | |
743 | guc_init_ctx_desc(guc, client); | |
744 | guc_init_doorbell(guc, client); | |
745 | ||
746 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ | |
747 | ||
748 | if (host2guc_allocate_doorbell(guc, client)) | |
749 | goto err; | |
750 | ||
751 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", | |
752 | priority, client, client->ctx_index, client->doorbell_id); | |
753 | ||
754 | return client; | |
755 | ||
756 | err: | |
757 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); | |
758 | ||
759 | guc_client_free(dev, client); | |
760 | return NULL; | |
761 | } | |
762 | ||
4c7e77fc AD |
763 | static void guc_create_log(struct intel_guc *guc) |
764 | { | |
765 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
766 | struct drm_i915_gem_object *obj; | |
767 | unsigned long offset; | |
768 | uint32_t size, flags; | |
769 | ||
770 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) | |
771 | return; | |
772 | ||
773 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) | |
774 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
775 | ||
776 | /* The first page is to save log buffer state. Allocate one | |
777 | * extra page for others in case for overlap */ | |
778 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
779 | GUC_LOG_ISR_PAGES + 1 + | |
780 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
781 | ||
782 | obj = guc->log_obj; | |
783 | if (!obj) { | |
784 | obj = gem_allocate_guc_obj(dev_priv->dev, size); | |
785 | if (!obj) { | |
786 | /* logging will be off */ | |
787 | i915.guc_log_level = -1; | |
788 | return; | |
789 | } | |
790 | ||
791 | guc->log_obj = obj; | |
792 | } | |
793 | ||
794 | /* each allocated unit is a page */ | |
795 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
796 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
797 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
798 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
799 | ||
800 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ | |
801 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; | |
802 | } | |
803 | ||
463704d0 AD |
804 | static void init_guc_policies(struct guc_policies *policies) |
805 | { | |
806 | struct guc_policy *policy; | |
807 | u32 p, i; | |
808 | ||
809 | policies->dpc_promote_time = 500000; | |
810 | policies->max_num_work_items = POLICY_MAX_NUM_WI; | |
811 | ||
812 | for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) { | |
397097b0 | 813 | for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { |
463704d0 AD |
814 | policy = &policies->policy[p][i]; |
815 | ||
816 | policy->execution_quantum = 1000000; | |
817 | policy->preemption_time = 500000; | |
818 | policy->fault_time = 250000; | |
819 | policy->policy_flags = 0; | |
820 | } | |
821 | } | |
822 | ||
823 | policies->is_valid = 1; | |
824 | } | |
825 | ||
68371a95 AD |
826 | static void guc_create_ads(struct intel_guc *guc) |
827 | { | |
828 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
829 | struct drm_i915_gem_object *obj; | |
830 | struct guc_ads *ads; | |
463704d0 | 831 | struct guc_policies *policies; |
5c148e04 | 832 | struct guc_mmio_reg_state *reg_state; |
e2f80391 | 833 | struct intel_engine_cs *engine; |
68371a95 | 834 | struct page *page; |
b4ac5afc | 835 | u32 size; |
68371a95 AD |
836 | |
837 | /* The ads obj includes the struct itself and buffers passed to GuC */ | |
5c148e04 AD |
838 | size = sizeof(struct guc_ads) + sizeof(struct guc_policies) + |
839 | sizeof(struct guc_mmio_reg_state) + | |
840 | GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE; | |
68371a95 AD |
841 | |
842 | obj = guc->ads_obj; | |
843 | if (!obj) { | |
844 | obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size)); | |
845 | if (!obj) | |
846 | return; | |
847 | ||
848 | guc->ads_obj = obj; | |
849 | } | |
850 | ||
851 | page = i915_gem_object_get_page(obj, 0); | |
852 | ads = kmap(page); | |
853 | ||
854 | /* | |
855 | * The GuC requires a "Golden Context" when it reinitialises | |
856 | * engines after a reset. Here we use the Render ring default | |
857 | * context, which must already exist and be pinned in the GGTT, | |
858 | * so its address won't change after we've told the GuC where | |
859 | * to find it. | |
860 | */ | |
4a570db5 | 861 | engine = &dev_priv->engine[RCS]; |
e2f80391 | 862 | ads->golden_context_lrca = engine->status_page.gfx_addr; |
68371a95 | 863 | |
b4ac5afc | 864 | for_each_engine(engine, dev_priv) |
e2f80391 | 865 | ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine); |
68371a95 | 866 | |
463704d0 AD |
867 | /* GuC scheduling policies */ |
868 | policies = (void *)ads + sizeof(struct guc_ads); | |
869 | init_guc_policies(policies); | |
870 | ||
871 | ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) + | |
872 | sizeof(struct guc_ads); | |
873 | ||
5c148e04 AD |
874 | /* MMIO reg state */ |
875 | reg_state = (void *)policies + sizeof(struct guc_policies); | |
876 | ||
b4ac5afc | 877 | for_each_engine(engine, dev_priv) { |
e2f80391 TU |
878 | reg_state->mmio_white_list[engine->guc_id].mmio_start = |
879 | engine->mmio_base + GUC_MMIO_WHITE_LIST_START; | |
5c148e04 AD |
880 | |
881 | /* Nothing to be saved or restored for now. */ | |
e2f80391 | 882 | reg_state->mmio_white_list[engine->guc_id].count = 0; |
5c148e04 AD |
883 | } |
884 | ||
885 | ads->reg_state_addr = ads->scheduler_policies + | |
886 | sizeof(struct guc_policies); | |
887 | ||
888 | ads->reg_state_buffer = ads->reg_state_addr + | |
889 | sizeof(struct guc_mmio_reg_state); | |
890 | ||
68371a95 AD |
891 | kunmap(page); |
892 | } | |
893 | ||
bac427f8 AD |
894 | /* |
895 | * Set up the memory resources to be shared with the GuC. At this point, | |
896 | * we require just one object that can be mapped through the GGTT. | |
897 | */ | |
898 | int i915_guc_submission_init(struct drm_device *dev) | |
899 | { | |
900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
901 | const size_t ctxsize = sizeof(struct guc_context_desc); | |
902 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
903 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
904 | struct intel_guc *guc = &dev_priv->guc; | |
905 | ||
906 | if (!i915.enable_guc_submission) | |
907 | return 0; /* not enabled */ | |
908 | ||
909 | if (guc->ctx_pool_obj) | |
910 | return 0; /* already allocated */ | |
911 | ||
912 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); | |
913 | if (!guc->ctx_pool_obj) | |
914 | return -ENOMEM; | |
915 | ||
916 | ida_init(&guc->ctx_ids); | |
917 | ||
4c7e77fc AD |
918 | guc_create_log(guc); |
919 | ||
68371a95 AD |
920 | guc_create_ads(guc); |
921 | ||
bac427f8 AD |
922 | return 0; |
923 | } | |
924 | ||
44a28b1d DG |
925 | int i915_guc_submission_enable(struct drm_device *dev) |
926 | { | |
927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
928 | struct intel_guc *guc = &dev_priv->guc; | |
ed54c1a1 | 929 | struct intel_context *ctx = dev_priv->kernel_context; |
44a28b1d DG |
930 | struct i915_guc_client *client; |
931 | ||
932 | /* client for execbuf submission */ | |
d1675198 | 933 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
44a28b1d DG |
934 | if (!client) { |
935 | DRM_ERROR("Failed to create execbuf guc_client\n"); | |
936 | return -ENOMEM; | |
937 | } | |
938 | ||
939 | guc->execbuf_client = client; | |
f5d3c3ea AD |
940 | |
941 | host2guc_sample_forcewake(guc, client); | |
942 | ||
44a28b1d DG |
943 | return 0; |
944 | } | |
945 | ||
946 | void i915_guc_submission_disable(struct drm_device *dev) | |
947 | { | |
948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
949 | struct intel_guc *guc = &dev_priv->guc; | |
950 | ||
951 | guc_client_free(dev, guc->execbuf_client); | |
952 | guc->execbuf_client = NULL; | |
953 | } | |
954 | ||
bac427f8 AD |
955 | void i915_guc_submission_fini(struct drm_device *dev) |
956 | { | |
957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
958 | struct intel_guc *guc = &dev_priv->guc; | |
959 | ||
68371a95 AD |
960 | gem_release_guc_obj(dev_priv->guc.ads_obj); |
961 | guc->ads_obj = NULL; | |
962 | ||
4c7e77fc AD |
963 | gem_release_guc_obj(dev_priv->guc.log_obj); |
964 | guc->log_obj = NULL; | |
965 | ||
bac427f8 AD |
966 | if (guc->ctx_pool_obj) |
967 | ida_destroy(&guc->ctx_ids); | |
968 | gem_release_guc_obj(guc->ctx_pool_obj); | |
969 | guc->ctx_pool_obj = NULL; | |
970 | } | |
a1c41994 AD |
971 | |
972 | /** | |
973 | * intel_guc_suspend() - notify GuC entering suspend state | |
974 | * @dev: drm device | |
975 | */ | |
976 | int intel_guc_suspend(struct drm_device *dev) | |
977 | { | |
978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
979 | struct intel_guc *guc = &dev_priv->guc; | |
980 | struct intel_context *ctx; | |
981 | u32 data[3]; | |
982 | ||
983 | if (!i915.enable_guc_submission) | |
984 | return 0; | |
985 | ||
ed54c1a1 | 986 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
987 | |
988 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; | |
989 | /* any value greater than GUC_POWER_D0 */ | |
990 | data[1] = GUC_POWER_D1; | |
991 | /* first page is shared data with GuC */ | |
992 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
993 | ||
994 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
995 | } | |
996 | ||
997 | ||
998 | /** | |
999 | * intel_guc_resume() - notify GuC resuming from suspend state | |
1000 | * @dev: drm device | |
1001 | */ | |
1002 | int intel_guc_resume(struct drm_device *dev) | |
1003 | { | |
1004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1005 | struct intel_guc *guc = &dev_priv->guc; | |
1006 | struct intel_context *ctx; | |
1007 | u32 data[3]; | |
1008 | ||
1009 | if (!i915.enable_guc_submission) | |
1010 | return 0; | |
1011 | ||
ed54c1a1 | 1012 | ctx = dev_priv->kernel_context; |
a1c41994 AD |
1013 | |
1014 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; | |
1015 | data[1] = GUC_POWER_D0; | |
1016 | /* first page is shared data with GuC */ | |
1017 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
1018 | ||
1019 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
1020 | } |