Commit | Line | Data |
---|---|---|
bac427f8 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/circ_buf.h> | |
26 | #include "i915_drv.h" | |
27 | #include "intel_guc.h" | |
28 | ||
44a28b1d | 29 | /** |
feda33ef | 30 | * DOC: GuC-based command submission |
44a28b1d DG |
31 | * |
32 | * i915_guc_client: | |
33 | * We use the term client to avoid confusion with contexts. A i915_guc_client is | |
34 | * equivalent to GuC object guc_context_desc. This context descriptor is | |
35 | * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell | |
36 | * and workqueue for it. Also the process descriptor (guc_process_desc), which | |
37 | * is mapped to client space. So the client can write Work Item then ring the | |
38 | * doorbell. | |
39 | * | |
40 | * To simplify the implementation, we allocate one gem object that contains all | |
41 | * pages for doorbell, process descriptor and workqueue. | |
42 | * | |
43 | * The Scratch registers: | |
44 | * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes | |
45 | * a value to the action register (SOFT_SCRATCH_0) along with any data. It then | |
46 | * triggers an interrupt on the GuC via another register write (0xC4C8). | |
47 | * Firmware writes a success/fail code back to the action register after | |
48 | * processes the request. The kernel driver polls waiting for this update and | |
49 | * then proceeds. | |
50 | * See host2guc_action() | |
51 | * | |
52 | * Doorbells: | |
53 | * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) | |
54 | * mapped into process space. | |
55 | * | |
56 | * Work Items: | |
57 | * There are several types of work items that the host may place into a | |
58 | * workqueue, each with its own requirements and limitations. Currently only | |
59 | * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which | |
60 | * represents in-order queue. The kernel driver packs ring tail pointer and an | |
61 | * ELSP context descriptor dword into Work Item. | |
62 | * See guc_add_workqueue_item() | |
63 | * | |
64 | */ | |
65 | ||
66 | /* | |
67 | * Read GuC command/status register (SOFT_SCRATCH_0) | |
68 | * Return true if it contains a response rather than a command | |
69 | */ | |
70 | static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, | |
71 | u32 *status) | |
72 | { | |
73 | u32 val = I915_READ(SOFT_SCRATCH(0)); | |
74 | *status = val; | |
75 | return GUC2HOST_IS_RESPONSE(val); | |
76 | } | |
77 | ||
78 | static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
81 | u32 status; | |
82 | int i; | |
83 | int ret; | |
84 | ||
85 | if (WARN_ON(len < 1 || len > 15)) | |
86 | return -EINVAL; | |
87 | ||
88 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
44a28b1d DG |
89 | |
90 | dev_priv->guc.action_count += 1; | |
91 | dev_priv->guc.action_cmd = data[0]; | |
92 | ||
93 | for (i = 0; i < len; i++) | |
94 | I915_WRITE(SOFT_SCRATCH(i), data[i]); | |
95 | ||
96 | POSTING_READ(SOFT_SCRATCH(i - 1)); | |
97 | ||
98 | I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER); | |
99 | ||
100 | /* No HOST2GUC command should take longer than 10ms */ | |
101 | ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10); | |
102 | if (status != GUC2HOST_STATUS_SUCCESS) { | |
103 | /* | |
104 | * Either the GuC explicitly returned an error (which | |
105 | * we convert to -EIO here) or no response at all was | |
106 | * received within the timeout limit (-ETIMEDOUT) | |
107 | */ | |
108 | if (ret != -ETIMEDOUT) | |
109 | ret = -EIO; | |
110 | ||
111 | DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d " | |
112 | "status=0x%08X response=0x%08X\n", | |
113 | data[0], ret, status, | |
114 | I915_READ(SOFT_SCRATCH(15))); | |
115 | ||
116 | dev_priv->guc.action_fail += 1; | |
117 | dev_priv->guc.action_err = ret; | |
118 | } | |
119 | dev_priv->guc.action_status = status; | |
120 | ||
44a28b1d DG |
121 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | /* | |
127 | * Tell the GuC to allocate or deallocate a specific doorbell | |
128 | */ | |
129 | ||
130 | static int host2guc_allocate_doorbell(struct intel_guc *guc, | |
131 | struct i915_guc_client *client) | |
132 | { | |
133 | u32 data[2]; | |
134 | ||
135 | data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; | |
136 | data[1] = client->ctx_index; | |
137 | ||
138 | return host2guc_action(guc, data, 2); | |
139 | } | |
140 | ||
141 | static int host2guc_release_doorbell(struct intel_guc *guc, | |
142 | struct i915_guc_client *client) | |
143 | { | |
144 | u32 data[2]; | |
145 | ||
146 | data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; | |
147 | data[1] = client->ctx_index; | |
148 | ||
149 | return host2guc_action(guc, data, 2); | |
150 | } | |
151 | ||
f5d3c3ea AD |
152 | static int host2guc_sample_forcewake(struct intel_guc *guc, |
153 | struct i915_guc_client *client) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
93f25318 | 156 | struct drm_device *dev = dev_priv->dev; |
f5d3c3ea AD |
157 | u32 data[2]; |
158 | ||
159 | data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE; | |
93f25318 AD |
160 | /* WaRsDisableCoarsePowerGating:skl,bxt */ |
161 | if (!intel_enable_rc6(dev_priv->dev) || | |
e87a005d JN |
162 | IS_BXT_REVID(dev, 0, BXT_REVID_A1) || |
163 | (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) || | |
164 | (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0))) | |
93f25318 AD |
165 | data[1] = 0; |
166 | else | |
167 | /* bit 0 and 1 are for Render and Media domain separately */ | |
168 | data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; | |
169 | ||
170 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
f5d3c3ea AD |
171 | } |
172 | ||
44a28b1d DG |
173 | /* |
174 | * Initialise, update, or clear doorbell data shared with the GuC | |
175 | * | |
176 | * These functions modify shared data and so need access to the mapped | |
177 | * client object which contains the page being used for the doorbell | |
178 | */ | |
179 | ||
180 | static void guc_init_doorbell(struct intel_guc *guc, | |
181 | struct i915_guc_client *client) | |
182 | { | |
183 | struct guc_doorbell_info *doorbell; | |
184 | void *base; | |
185 | ||
186 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
187 | doorbell = base + client->doorbell_offset; | |
188 | ||
189 | doorbell->db_status = 1; | |
190 | doorbell->cookie = 0; | |
191 | ||
192 | kunmap_atomic(base); | |
193 | } | |
194 | ||
195 | static int guc_ring_doorbell(struct i915_guc_client *gc) | |
196 | { | |
197 | struct guc_process_desc *desc; | |
198 | union guc_doorbell_qw db_cmp, db_exc, db_ret; | |
199 | union guc_doorbell_qw *db; | |
200 | void *base; | |
201 | int attempt = 2, ret = -EAGAIN; | |
202 | ||
203 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); | |
204 | desc = base + gc->proc_desc_offset; | |
205 | ||
206 | /* Update the tail so it is visible to GuC */ | |
207 | desc->tail = gc->wq_tail; | |
208 | ||
209 | /* current cookie */ | |
210 | db_cmp.db_status = GUC_DOORBELL_ENABLED; | |
211 | db_cmp.cookie = gc->cookie; | |
212 | ||
213 | /* cookie to be updated */ | |
214 | db_exc.db_status = GUC_DOORBELL_ENABLED; | |
215 | db_exc.cookie = gc->cookie + 1; | |
216 | if (db_exc.cookie == 0) | |
217 | db_exc.cookie = 1; | |
218 | ||
219 | /* pointer of current doorbell cacheline */ | |
220 | db = base + gc->doorbell_offset; | |
221 | ||
222 | while (attempt--) { | |
223 | /* lets ring the doorbell */ | |
224 | db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db, | |
225 | db_cmp.value_qw, db_exc.value_qw); | |
226 | ||
227 | /* if the exchange was successfully executed */ | |
228 | if (db_ret.value_qw == db_cmp.value_qw) { | |
229 | /* db was successfully rung */ | |
230 | gc->cookie = db_exc.cookie; | |
231 | ret = 0; | |
232 | break; | |
233 | } | |
234 | ||
235 | /* XXX: doorbell was lost and need to acquire it again */ | |
236 | if (db_ret.db_status == GUC_DOORBELL_DISABLED) | |
237 | break; | |
238 | ||
239 | DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n", | |
240 | db_cmp.cookie, db_ret.cookie); | |
241 | ||
242 | /* update the cookie to newly read cookie from GuC */ | |
243 | db_cmp.cookie = db_ret.cookie; | |
244 | db_exc.cookie = db_ret.cookie + 1; | |
245 | if (db_exc.cookie == 0) | |
246 | db_exc.cookie = 1; | |
247 | } | |
248 | ||
249 | kunmap_atomic(base); | |
250 | return ret; | |
251 | } | |
252 | ||
253 | static void guc_disable_doorbell(struct intel_guc *guc, | |
254 | struct i915_guc_client *client) | |
255 | { | |
256 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
257 | struct guc_doorbell_info *doorbell; | |
258 | void *base; | |
f0f59a00 | 259 | i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id); |
44a28b1d DG |
260 | int value; |
261 | ||
262 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
263 | doorbell = base + client->doorbell_offset; | |
264 | ||
265 | doorbell->db_status = 0; | |
266 | ||
267 | kunmap_atomic(base); | |
268 | ||
269 | I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID); | |
270 | ||
271 | value = I915_READ(drbreg); | |
272 | WARN_ON((value & GEN8_DRB_VALID) != 0); | |
273 | ||
274 | I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0); | |
275 | I915_WRITE(drbreg, 0); | |
276 | ||
277 | /* XXX: wait for any interrupts */ | |
278 | /* XXX: wait for workqueue to drain */ | |
279 | } | |
280 | ||
281 | /* | |
282 | * Select, assign and relase doorbell cachelines | |
283 | * | |
284 | * These functions track which doorbell cachelines are in use. | |
285 | * The data they manipulate is protected by the host2guc lock. | |
286 | */ | |
287 | ||
288 | static uint32_t select_doorbell_cacheline(struct intel_guc *guc) | |
289 | { | |
290 | const uint32_t cacheline_size = cache_line_size(); | |
291 | uint32_t offset; | |
292 | ||
44a28b1d DG |
293 | /* Doorbell uses a single cache line within a page */ |
294 | offset = offset_in_page(guc->db_cacheline); | |
295 | ||
296 | /* Moving to next cache line to reduce contention */ | |
297 | guc->db_cacheline += cacheline_size; | |
298 | ||
44a28b1d DG |
299 | DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n", |
300 | offset, guc->db_cacheline, cacheline_size); | |
301 | ||
302 | return offset; | |
303 | } | |
304 | ||
305 | static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority) | |
306 | { | |
307 | /* | |
308 | * The bitmap is split into two halves; the first half is used for | |
309 | * normal priority contexts, the second half for high-priority ones. | |
310 | * Note that logically higher priorities are numerically less than | |
311 | * normal ones, so the test below means "is it high-priority?" | |
312 | */ | |
313 | const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH); | |
314 | const uint16_t half = GUC_MAX_DOORBELLS / 2; | |
315 | const uint16_t start = hi_pri ? half : 0; | |
316 | const uint16_t end = start + half; | |
317 | uint16_t id; | |
318 | ||
44a28b1d DG |
319 | id = find_next_zero_bit(guc->doorbell_bitmap, end, start); |
320 | if (id == end) | |
321 | id = GUC_INVALID_DOORBELL_ID; | |
322 | else | |
323 | bitmap_set(guc->doorbell_bitmap, id, 1); | |
44a28b1d DG |
324 | |
325 | DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n", | |
326 | hi_pri ? "high" : "normal", id); | |
327 | ||
328 | return id; | |
329 | } | |
330 | ||
331 | static void release_doorbell(struct intel_guc *guc, uint16_t id) | |
332 | { | |
44a28b1d | 333 | bitmap_clear(guc->doorbell_bitmap, id, 1); |
44a28b1d DG |
334 | } |
335 | ||
336 | /* | |
337 | * Initialise the process descriptor shared with the GuC firmware. | |
338 | */ | |
339 | static void guc_init_proc_desc(struct intel_guc *guc, | |
340 | struct i915_guc_client *client) | |
341 | { | |
342 | struct guc_process_desc *desc; | |
343 | void *base; | |
344 | ||
345 | base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0)); | |
346 | desc = base + client->proc_desc_offset; | |
347 | ||
348 | memset(desc, 0, sizeof(*desc)); | |
349 | ||
350 | /* | |
351 | * XXX: pDoorbell and WQVBaseAddress are pointers in process address | |
352 | * space for ring3 clients (set them as in mmap_ioctl) or kernel | |
353 | * space for kernel clients (map on demand instead? May make debug | |
354 | * easier to have it mapped). | |
355 | */ | |
356 | desc->wq_base_addr = 0; | |
357 | desc->db_base_addr = 0; | |
358 | ||
359 | desc->context_id = client->ctx_index; | |
360 | desc->wq_size_bytes = client->wq_size; | |
361 | desc->wq_status = WQ_STATUS_ACTIVE; | |
362 | desc->priority = client->priority; | |
363 | ||
364 | kunmap_atomic(base); | |
365 | } | |
366 | ||
367 | /* | |
368 | * Initialise/clear the context descriptor shared with the GuC firmware. | |
369 | * | |
370 | * This descriptor tells the GuC where (in GGTT space) to find the important | |
371 | * data structures relating to this client (doorbell, process descriptor, | |
372 | * write queue, etc). | |
373 | */ | |
374 | ||
375 | static void guc_init_ctx_desc(struct intel_guc *guc, | |
376 | struct i915_guc_client *client) | |
377 | { | |
d1675198 | 378 | struct intel_context *ctx = client->owner; |
44a28b1d DG |
379 | struct guc_context_desc desc; |
380 | struct sg_table *sg; | |
d1675198 | 381 | int i; |
44a28b1d DG |
382 | |
383 | memset(&desc, 0, sizeof(desc)); | |
384 | ||
385 | desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL; | |
386 | desc.context_id = client->ctx_index; | |
387 | desc.priority = client->priority; | |
44a28b1d DG |
388 | desc.db_id = client->doorbell_id; |
389 | ||
d1675198 AD |
390 | for (i = 0; i < I915_NUM_RINGS; i++) { |
391 | struct guc_execlist_context *lrc = &desc.lrc[i]; | |
392 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; | |
393 | struct intel_engine_cs *ring; | |
394 | struct drm_i915_gem_object *obj; | |
395 | uint64_t ctx_desc; | |
396 | ||
397 | /* TODO: We have a design issue to be solved here. Only when we | |
398 | * receive the first batch, we know which engine is used by the | |
399 | * user. But here GuC expects the lrc and ring to be pinned. It | |
400 | * is not an issue for default context, which is the only one | |
401 | * for now who owns a GuC client. But for future owner of GuC | |
402 | * client, need to make sure lrc is pinned prior to enter here. | |
403 | */ | |
404 | obj = ctx->engine[i].state; | |
405 | if (!obj) | |
406 | break; /* XXX: continue? */ | |
407 | ||
408 | ring = ringbuf->ring; | |
409 | ctx_desc = intel_lr_context_descriptor(ctx, ring); | |
410 | lrc->context_desc = (u32)ctx_desc; | |
411 | ||
412 | /* The state page is after PPHWSP */ | |
413 | lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) + | |
414 | LRC_STATE_PN * PAGE_SIZE; | |
415 | lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | | |
416 | (ring->id << GUC_ELC_ENGINE_OFFSET); | |
417 | ||
418 | obj = ringbuf->obj; | |
419 | ||
420 | lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); | |
421 | lrc->ring_end = lrc->ring_begin + obj->base.size - 1; | |
422 | lrc->ring_next_free_location = lrc->ring_begin; | |
423 | lrc->ring_current_tail_pointer_value = 0; | |
424 | ||
425 | desc.engines_used |= (1 << ring->id); | |
426 | } | |
427 | ||
428 | WARN_ON(desc.engines_used == 0); | |
429 | ||
44a28b1d DG |
430 | /* |
431 | * The CPU address is only needed at certain points, so kmap_atomic on | |
432 | * demand instead of storing it in the ctx descriptor. | |
433 | * XXX: May make debug easier to have it mapped | |
434 | */ | |
435 | desc.db_trigger_cpu = 0; | |
436 | desc.db_trigger_uk = client->doorbell_offset + | |
437 | i915_gem_obj_ggtt_offset(client->client_obj); | |
438 | desc.db_trigger_phy = client->doorbell_offset + | |
439 | sg_dma_address(client->client_obj->pages->sgl); | |
440 | ||
441 | desc.process_desc = client->proc_desc_offset + | |
442 | i915_gem_obj_ggtt_offset(client->client_obj); | |
443 | ||
444 | desc.wq_addr = client->wq_offset + | |
445 | i915_gem_obj_ggtt_offset(client->client_obj); | |
446 | ||
447 | desc.wq_size = client->wq_size; | |
448 | ||
449 | /* | |
450 | * XXX: Take LRCs from an existing intel_context if this is not an | |
451 | * IsKMDCreatedContext client | |
452 | */ | |
453 | desc.desc_private = (uintptr_t)client; | |
454 | ||
455 | /* Pool context is pinned already */ | |
456 | sg = guc->ctx_pool_obj->pages; | |
457 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
458 | sizeof(desc) * client->ctx_index); | |
459 | } | |
460 | ||
461 | static void guc_fini_ctx_desc(struct intel_guc *guc, | |
462 | struct i915_guc_client *client) | |
463 | { | |
464 | struct guc_context_desc desc; | |
465 | struct sg_table *sg; | |
466 | ||
467 | memset(&desc, 0, sizeof(desc)); | |
468 | ||
469 | sg = guc->ctx_pool_obj->pages; | |
470 | sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc), | |
471 | sizeof(desc) * client->ctx_index); | |
472 | } | |
473 | ||
474 | /* Get valid workqueue item and return it back to offset */ | |
475 | static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset) | |
476 | { | |
477 | struct guc_process_desc *desc; | |
478 | void *base; | |
479 | u32 size = sizeof(struct guc_wq_item); | |
5a843307 | 480 | int ret = -ETIMEDOUT, timeout_counter = 200; |
44a28b1d DG |
481 | |
482 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0)); | |
483 | desc = base + gc->proc_desc_offset; | |
484 | ||
485 | while (timeout_counter-- > 0) { | |
5a843307 | 486 | if (CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size) >= size) { |
44a28b1d DG |
487 | *offset = gc->wq_tail; |
488 | ||
489 | /* advance the tail for next workqueue item */ | |
490 | gc->wq_tail += size; | |
491 | gc->wq_tail &= gc->wq_size - 1; | |
492 | ||
493 | /* this will break the loop */ | |
494 | timeout_counter = 0; | |
5a843307 | 495 | ret = 0; |
44a28b1d | 496 | } |
5a843307 AD |
497 | |
498 | if (timeout_counter) | |
499 | usleep_range(1000, 2000); | |
44a28b1d DG |
500 | }; |
501 | ||
502 | kunmap_atomic(base); | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
507 | static int guc_add_workqueue_item(struct i915_guc_client *gc, | |
508 | struct drm_i915_gem_request *rq) | |
509 | { | |
510 | enum intel_ring_id ring_id = rq->ring->id; | |
511 | struct guc_wq_item *wqi; | |
512 | void *base; | |
513 | u32 tail, wq_len, wq_off = 0; | |
514 | int ret; | |
515 | ||
516 | ret = guc_get_workqueue_space(gc, &wq_off); | |
517 | if (ret) | |
518 | return ret; | |
519 | ||
520 | /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we | |
521 | * should not have the case where structure wqi is across page, neither | |
522 | * wrapped to the beginning. This simplifies the implementation below. | |
523 | * | |
524 | * XXX: if not the case, we need save data to a temp wqi and copy it to | |
525 | * workqueue buffer dw by dw. | |
526 | */ | |
527 | WARN_ON(sizeof(struct guc_wq_item) != 16); | |
528 | WARN_ON(wq_off & 3); | |
529 | ||
530 | /* wq starts from the page after doorbell / process_desc */ | |
531 | base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, | |
532 | (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT)); | |
533 | wq_off &= PAGE_SIZE - 1; | |
534 | wqi = (struct guc_wq_item *)((char *)base + wq_off); | |
535 | ||
536 | /* len does not include the header */ | |
537 | wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1; | |
538 | wqi->header = WQ_TYPE_INORDER | | |
539 | (wq_len << WQ_LEN_SHIFT) | | |
540 | (ring_id << WQ_TARGET_SHIFT) | | |
541 | WQ_NO_WCFLUSH_WAIT; | |
542 | ||
543 | /* The GuC wants only the low-order word of the context descriptor */ | |
544 | wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring); | |
545 | ||
546 | /* The GuC firmware wants the tail index in QWords, not bytes */ | |
547 | tail = rq->ringbuf->tail >> 3; | |
548 | wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT; | |
549 | wqi->fence_id = 0; /*XXX: what fence to be here */ | |
550 | ||
551 | kunmap_atomic(base); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
d1675198 AD |
556 | #define CTX_RING_BUFFER_START 0x08 |
557 | ||
558 | /* Update the ringbuffer pointer in a saved context image */ | |
559 | static void lr_context_update(struct drm_i915_gem_request *rq) | |
560 | { | |
561 | enum intel_ring_id ring_id = rq->ring->id; | |
562 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state; | |
563 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; | |
564 | struct page *page; | |
565 | uint32_t *reg_state; | |
566 | ||
567 | BUG_ON(!ctx_obj); | |
568 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); | |
569 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); | |
570 | ||
571 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); | |
572 | reg_state = kmap_atomic(page); | |
573 | ||
574 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); | |
575 | ||
576 | kunmap_atomic(reg_state); | |
577 | } | |
578 | ||
44a28b1d DG |
579 | /** |
580 | * i915_guc_submit() - Submit commands through GuC | |
581 | * @client: the guc client where commands will go through | |
feda33ef | 582 | * @rq: request associated with the commands |
44a28b1d DG |
583 | * |
584 | * Return: 0 if succeed | |
585 | */ | |
586 | int i915_guc_submit(struct i915_guc_client *client, | |
587 | struct drm_i915_gem_request *rq) | |
588 | { | |
589 | struct intel_guc *guc = client->guc; | |
590 | enum intel_ring_id ring_id = rq->ring->id; | |
44a28b1d DG |
591 | int q_ret, b_ret; |
592 | ||
d1675198 AD |
593 | /* Need this because of the deferred pin ctx and ring */ |
594 | /* Shall we move this right after ring is pinned? */ | |
595 | lr_context_update(rq); | |
596 | ||
44a28b1d DG |
597 | q_ret = guc_add_workqueue_item(client, rq); |
598 | if (q_ret == 0) | |
599 | b_ret = guc_ring_doorbell(client); | |
600 | ||
601 | client->submissions[ring_id] += 1; | |
602 | if (q_ret) { | |
603 | client->q_fail += 1; | |
604 | client->retcode = q_ret; | |
605 | } else if (b_ret) { | |
606 | client->b_fail += 1; | |
607 | client->retcode = q_ret = b_ret; | |
608 | } else { | |
609 | client->retcode = 0; | |
610 | } | |
44a28b1d DG |
611 | guc->submissions[ring_id] += 1; |
612 | guc->last_seqno[ring_id] = rq->seqno; | |
44a28b1d DG |
613 | |
614 | return q_ret; | |
615 | } | |
616 | ||
617 | /* | |
618 | * Everything below here is concerned with setup & teardown, and is | |
619 | * therefore not part of the somewhat time-critical batch-submission | |
620 | * path of i915_guc_submit() above. | |
621 | */ | |
622 | ||
bac427f8 AD |
623 | /** |
624 | * gem_allocate_guc_obj() - Allocate gem object for GuC usage | |
625 | * @dev: drm device | |
626 | * @size: size of object | |
627 | * | |
628 | * This is a wrapper to create a gem obj. In order to use it inside GuC, the | |
629 | * object needs to be pinned lifetime. Also we must pin it to gtt space other | |
630 | * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC. | |
631 | * | |
632 | * Return: A drm_i915_gem_object if successful, otherwise NULL. | |
633 | */ | |
634 | static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev, | |
635 | u32 size) | |
636 | { | |
637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
638 | struct drm_i915_gem_object *obj; | |
639 | ||
640 | obj = i915_gem_alloc_object(dev, size); | |
641 | if (!obj) | |
642 | return NULL; | |
643 | ||
644 | if (i915_gem_object_get_pages(obj)) { | |
645 | drm_gem_object_unreference(&obj->base); | |
646 | return NULL; | |
647 | } | |
648 | ||
649 | if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, | |
650 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) { | |
651 | drm_gem_object_unreference(&obj->base); | |
652 | return NULL; | |
653 | } | |
654 | ||
655 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
656 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
657 | ||
658 | return obj; | |
659 | } | |
660 | ||
661 | /** | |
662 | * gem_release_guc_obj() - Release gem object allocated for GuC usage | |
663 | * @obj: gem obj to be released | |
81fd874e | 664 | */ |
bac427f8 AD |
665 | static void gem_release_guc_obj(struct drm_i915_gem_object *obj) |
666 | { | |
667 | if (!obj) | |
668 | return; | |
669 | ||
670 | if (i915_gem_obj_is_pinned(obj)) | |
671 | i915_gem_object_ggtt_unpin(obj); | |
672 | ||
673 | drm_gem_object_unreference(&obj->base); | |
674 | } | |
675 | ||
44a28b1d DG |
676 | static void guc_client_free(struct drm_device *dev, |
677 | struct i915_guc_client *client) | |
678 | { | |
679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
680 | struct intel_guc *guc = &dev_priv->guc; | |
681 | ||
682 | if (!client) | |
683 | return; | |
684 | ||
685 | if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) { | |
686 | /* | |
687 | * First disable the doorbell, then tell the GuC we've | |
688 | * finished with it, finally deallocate it in our bitmap | |
689 | */ | |
690 | guc_disable_doorbell(guc, client); | |
691 | host2guc_release_doorbell(guc, client); | |
692 | release_doorbell(guc, client->doorbell_id); | |
693 | } | |
694 | ||
695 | /* | |
696 | * XXX: wait for any outstanding submissions before freeing memory. | |
697 | * Be sure to drop any locks | |
698 | */ | |
699 | ||
700 | gem_release_guc_obj(client->client_obj); | |
701 | ||
702 | if (client->ctx_index != GUC_INVALID_CTX_ID) { | |
703 | guc_fini_ctx_desc(guc, client); | |
704 | ida_simple_remove(&guc->ctx_ids, client->ctx_index); | |
705 | } | |
706 | ||
707 | kfree(client); | |
708 | } | |
709 | ||
710 | /** | |
711 | * guc_client_alloc() - Allocate an i915_guc_client | |
712 | * @dev: drm device | |
713 | * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW | |
714 | * The kernel client to replace ExecList submission is created with | |
715 | * NORMAL priority. Priority of a client for scheduler can be HIGH, | |
716 | * while a preemption context can use CRITICAL. | |
feda33ef AD |
717 | * @ctx: the context that owns the client (we use the default render |
718 | * context) | |
44a28b1d DG |
719 | * |
720 | * Return: An i915_guc_client object if success. | |
721 | */ | |
722 | static struct i915_guc_client *guc_client_alloc(struct drm_device *dev, | |
d1675198 AD |
723 | uint32_t priority, |
724 | struct intel_context *ctx) | |
44a28b1d DG |
725 | { |
726 | struct i915_guc_client *client; | |
727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
728 | struct intel_guc *guc = &dev_priv->guc; | |
729 | struct drm_i915_gem_object *obj; | |
730 | ||
731 | client = kzalloc(sizeof(*client), GFP_KERNEL); | |
732 | if (!client) | |
733 | return NULL; | |
734 | ||
735 | client->doorbell_id = GUC_INVALID_DOORBELL_ID; | |
736 | client->priority = priority; | |
d1675198 | 737 | client->owner = ctx; |
44a28b1d DG |
738 | client->guc = guc; |
739 | ||
740 | client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0, | |
741 | GUC_MAX_GPU_CONTEXTS, GFP_KERNEL); | |
742 | if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) { | |
743 | client->ctx_index = GUC_INVALID_CTX_ID; | |
744 | goto err; | |
745 | } | |
746 | ||
747 | /* The first page is doorbell/proc_desc. Two followed pages are wq. */ | |
748 | obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE); | |
749 | if (!obj) | |
750 | goto err; | |
751 | ||
752 | client->client_obj = obj; | |
753 | client->wq_offset = GUC_DB_SIZE; | |
754 | client->wq_size = GUC_WQ_SIZE; | |
44a28b1d DG |
755 | |
756 | client->doorbell_offset = select_doorbell_cacheline(guc); | |
757 | ||
758 | /* | |
759 | * Since the doorbell only requires a single cacheline, we can save | |
760 | * space by putting the application process descriptor in the same | |
761 | * page. Use the half of the page that doesn't include the doorbell. | |
762 | */ | |
763 | if (client->doorbell_offset >= (GUC_DB_SIZE / 2)) | |
764 | client->proc_desc_offset = 0; | |
765 | else | |
766 | client->proc_desc_offset = (GUC_DB_SIZE / 2); | |
767 | ||
768 | client->doorbell_id = assign_doorbell(guc, client->priority); | |
769 | if (client->doorbell_id == GUC_INVALID_DOORBELL_ID) | |
770 | /* XXX: evict a doorbell instead */ | |
771 | goto err; | |
772 | ||
773 | guc_init_proc_desc(guc, client); | |
774 | guc_init_ctx_desc(guc, client); | |
775 | guc_init_doorbell(guc, client); | |
776 | ||
777 | /* XXX: Any cache flushes needed? General domain mgmt calls? */ | |
778 | ||
779 | if (host2guc_allocate_doorbell(guc, client)) | |
780 | goto err; | |
781 | ||
782 | DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n", | |
783 | priority, client, client->ctx_index, client->doorbell_id); | |
784 | ||
785 | return client; | |
786 | ||
787 | err: | |
788 | DRM_ERROR("FAILED to create priority %u GuC client!\n", priority); | |
789 | ||
790 | guc_client_free(dev, client); | |
791 | return NULL; | |
792 | } | |
793 | ||
4c7e77fc AD |
794 | static void guc_create_log(struct intel_guc *guc) |
795 | { | |
796 | struct drm_i915_private *dev_priv = guc_to_i915(guc); | |
797 | struct drm_i915_gem_object *obj; | |
798 | unsigned long offset; | |
799 | uint32_t size, flags; | |
800 | ||
801 | if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN) | |
802 | return; | |
803 | ||
804 | if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX) | |
805 | i915.guc_log_level = GUC_LOG_VERBOSITY_MAX; | |
806 | ||
807 | /* The first page is to save log buffer state. Allocate one | |
808 | * extra page for others in case for overlap */ | |
809 | size = (1 + GUC_LOG_DPC_PAGES + 1 + | |
810 | GUC_LOG_ISR_PAGES + 1 + | |
811 | GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT; | |
812 | ||
813 | obj = guc->log_obj; | |
814 | if (!obj) { | |
815 | obj = gem_allocate_guc_obj(dev_priv->dev, size); | |
816 | if (!obj) { | |
817 | /* logging will be off */ | |
818 | i915.guc_log_level = -1; | |
819 | return; | |
820 | } | |
821 | ||
822 | guc->log_obj = obj; | |
823 | } | |
824 | ||
825 | /* each allocated unit is a page */ | |
826 | flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL | | |
827 | (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) | | |
828 | (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) | | |
829 | (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT); | |
830 | ||
831 | offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */ | |
832 | guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags; | |
833 | } | |
834 | ||
bac427f8 AD |
835 | /* |
836 | * Set up the memory resources to be shared with the GuC. At this point, | |
837 | * we require just one object that can be mapped through the GGTT. | |
838 | */ | |
839 | int i915_guc_submission_init(struct drm_device *dev) | |
840 | { | |
841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
842 | const size_t ctxsize = sizeof(struct guc_context_desc); | |
843 | const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize; | |
844 | const size_t gemsize = round_up(poolsize, PAGE_SIZE); | |
845 | struct intel_guc *guc = &dev_priv->guc; | |
846 | ||
847 | if (!i915.enable_guc_submission) | |
848 | return 0; /* not enabled */ | |
849 | ||
850 | if (guc->ctx_pool_obj) | |
851 | return 0; /* already allocated */ | |
852 | ||
853 | guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize); | |
854 | if (!guc->ctx_pool_obj) | |
855 | return -ENOMEM; | |
856 | ||
857 | ida_init(&guc->ctx_ids); | |
858 | ||
4c7e77fc AD |
859 | guc_create_log(guc); |
860 | ||
bac427f8 AD |
861 | return 0; |
862 | } | |
863 | ||
44a28b1d DG |
864 | int i915_guc_submission_enable(struct drm_device *dev) |
865 | { | |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
867 | struct intel_guc *guc = &dev_priv->guc; | |
d1675198 | 868 | struct intel_context *ctx = dev_priv->ring[RCS].default_context; |
44a28b1d DG |
869 | struct i915_guc_client *client; |
870 | ||
871 | /* client for execbuf submission */ | |
d1675198 | 872 | client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx); |
44a28b1d DG |
873 | if (!client) { |
874 | DRM_ERROR("Failed to create execbuf guc_client\n"); | |
875 | return -ENOMEM; | |
876 | } | |
877 | ||
878 | guc->execbuf_client = client; | |
f5d3c3ea AD |
879 | |
880 | host2guc_sample_forcewake(guc, client); | |
881 | ||
44a28b1d DG |
882 | return 0; |
883 | } | |
884 | ||
885 | void i915_guc_submission_disable(struct drm_device *dev) | |
886 | { | |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
888 | struct intel_guc *guc = &dev_priv->guc; | |
889 | ||
890 | guc_client_free(dev, guc->execbuf_client); | |
891 | guc->execbuf_client = NULL; | |
892 | } | |
893 | ||
bac427f8 AD |
894 | void i915_guc_submission_fini(struct drm_device *dev) |
895 | { | |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
897 | struct intel_guc *guc = &dev_priv->guc; | |
898 | ||
4c7e77fc AD |
899 | gem_release_guc_obj(dev_priv->guc.log_obj); |
900 | guc->log_obj = NULL; | |
901 | ||
bac427f8 AD |
902 | if (guc->ctx_pool_obj) |
903 | ida_destroy(&guc->ctx_ids); | |
904 | gem_release_guc_obj(guc->ctx_pool_obj); | |
905 | guc->ctx_pool_obj = NULL; | |
906 | } | |
a1c41994 AD |
907 | |
908 | /** | |
909 | * intel_guc_suspend() - notify GuC entering suspend state | |
910 | * @dev: drm device | |
911 | */ | |
912 | int intel_guc_suspend(struct drm_device *dev) | |
913 | { | |
914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
915 | struct intel_guc *guc = &dev_priv->guc; | |
916 | struct intel_context *ctx; | |
917 | u32 data[3]; | |
918 | ||
919 | if (!i915.enable_guc_submission) | |
920 | return 0; | |
921 | ||
922 | ctx = dev_priv->ring[RCS].default_context; | |
923 | ||
924 | data[0] = HOST2GUC_ACTION_ENTER_S_STATE; | |
925 | /* any value greater than GUC_POWER_D0 */ | |
926 | data[1] = GUC_POWER_D1; | |
927 | /* first page is shared data with GuC */ | |
928 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
929 | ||
930 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
931 | } | |
932 | ||
933 | ||
934 | /** | |
935 | * intel_guc_resume() - notify GuC resuming from suspend state | |
936 | * @dev: drm device | |
937 | */ | |
938 | int intel_guc_resume(struct drm_device *dev) | |
939 | { | |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | struct intel_guc *guc = &dev_priv->guc; | |
942 | struct intel_context *ctx; | |
943 | u32 data[3]; | |
944 | ||
945 | if (!i915.enable_guc_submission) | |
946 | return 0; | |
947 | ||
948 | ctx = dev_priv->ring[RCS].default_context; | |
949 | ||
950 | data[0] = HOST2GUC_ACTION_EXIT_S_STATE; | |
951 | data[1] = GUC_POWER_D0; | |
952 | /* first page is shared data with GuC */ | |
953 | data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); | |
954 | ||
955 | return host2guc_action(guc, data, ARRAY_SIZE(data)); | |
956 | } |