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drm/i915: Fix VLV DP RBR/HDMI/DAC PLL LPF coefficients
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
8664281b
PZ		 107static bool ivb_can_enable_err_int(struct drm_device *dev)
108{
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
4bc9d430
DV		 113 assert_spin_locked(&dev_priv->irq_lock);
114
8664281b
PZ		 115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123}
124
125static bool cpt_can_enable_serr_int(struct drm_device *dev)
126{
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
131 for_each_pipe(pipe) {
132 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
133
134 if (crtc->pch_fifo_underrun_disabled)
135 return false;
136 }
137
138 return true;
139}
140
141static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
142 enum pipe pipe, bool enable)
143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
146 DE_PIPEB_FIFO_UNDERRUN;
147
148 if (enable)
149 ironlake_enable_display_irq(dev_priv, bit);
150 else
151 ironlake_disable_display_irq(dev_priv, bit);
152}
153
154static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
155 bool enable)
156{
157 struct drm_i915_private *dev_priv = dev->dev_private;
158
159 if (enable) {
160 if (!ivb_can_enable_err_int(dev))
161 return;
162
163 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
164 ERR_INT_FIFO_UNDERRUN_B |
165 ERR_INT_FIFO_UNDERRUN_C);
166
167 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
168 } else {
169 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
170 }
171}
172
173static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
174 bool enable)
175{
176 struct drm_device *dev = crtc->base.dev;
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
179 SDE_TRANSB_FIFO_UNDER;
180
181 if (enable)
182 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
183 else
184 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
185
186 POSTING_READ(SDEIMR);
187}
188
189static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
190 enum transcoder pch_transcoder,
191 bool enable)
192{
193 struct drm_i915_private *dev_priv = dev->dev_private;
194
195 if (enable) {
196 if (!cpt_can_enable_serr_int(dev))
197 return;
198
199 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
200 SERR_INT_TRANS_B_FIFO_UNDERRUN |
201 SERR_INT_TRANS_C_FIFO_UNDERRUN);
202
203 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
204 } else {
205 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
206 }
207
208 POSTING_READ(SDEIMR);
209}
210
211/**
212 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
213 * @dev: drm device
214 * @pipe: pipe
215 * @enable: true if we want to report FIFO underrun errors, false otherwise
216 *
217 * This function makes us disable or enable CPU fifo underruns for a specific
218 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
219 * reporting for one pipe may also disable all the other CPU error interruts for
220 * the other pipes, due to the fact that there's just one interrupt mask/enable
221 * bit for all the pipes.
222 *
223 * Returns the previous state of underrun reporting.
224 */
225bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
226 enum pipe pipe, bool enable)
227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
231 unsigned long flags;
232 bool ret;
233
234 spin_lock_irqsave(&dev_priv->irq_lock, flags);
235
236 ret = !intel_crtc->cpu_fifo_underrun_disabled;
237
238 if (enable == ret)
239 goto done;
240
241 intel_crtc->cpu_fifo_underrun_disabled = !enable;
242
243 if (IS_GEN5(dev) || IS_GEN6(dev))
244 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
245 else if (IS_GEN7(dev))
246 ivybridge_set_fifo_underrun_reporting(dev, enable);
247
248done:
249 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
250 return ret;
251}
252
253/**
254 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
255 * @dev: drm device
256 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
257 * @enable: true if we want to report FIFO underrun errors, false otherwise
258 *
259 * This function makes us disable or enable PCH fifo underruns for a specific
260 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
261 * underrun reporting for one transcoder may also disable all the other PCH
262 * error interruts for the other transcoders, due to the fact that there's just
263 * one interrupt mask/enable bit for all the transcoders.
264 *
265 * Returns the previous state of underrun reporting.
266 */
267bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
268 enum transcoder pch_transcoder,
269 bool enable)
270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 enum pipe p;
273 struct drm_crtc *crtc;
274 struct intel_crtc *intel_crtc;
275 unsigned long flags;
276 bool ret;
277
278 if (HAS_PCH_LPT(dev)) {
279 crtc = NULL;
280 for_each_pipe(p) {
281 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
282 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
283 crtc = c;
284 break;
285 }
286 }
287 if (!crtc) {
288 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
289 return false;
290 }
291 } else {
292 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
293 }
294 intel_crtc = to_intel_crtc(crtc);
295
296 spin_lock_irqsave(&dev_priv->irq_lock, flags);
297
298 ret = !intel_crtc->pch_fifo_underrun_disabled;
299
300 if (enable == ret)
301 goto done;
302
303 intel_crtc->pch_fifo_underrun_disabled = !enable;
304
305 if (HAS_PCH_IBX(dev))
306 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
307 else
308 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
309
310done:
311 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
312 return ret;
313}
314
315
7c463586
KP		 316void
317i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
318{
46c06a30
VS		 319 u32 reg = PIPESTAT(pipe);
320 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 321
b79480ba
DV		 322 assert_spin_locked(&dev_priv->irq_lock);
323
46c06a30
VS		 324 if ((pipestat & mask) == mask)
325 return;
326
327 /* Enable the interrupt, clear any pending status */
328 pipestat |= mask | (mask >> 16);
329 I915_WRITE(reg, pipestat);
330 POSTING_READ(reg);
7c463586
KP		 331}
332
333void
334i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
335{
46c06a30
VS		 336 u32 reg = PIPESTAT(pipe);
337 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 338
b79480ba
DV		 339 assert_spin_locked(&dev_priv->irq_lock);
340
46c06a30
VS		 341 if ((pipestat & mask) == 0)
342 return;
343
344 pipestat &= ~mask;
345 I915_WRITE(reg, pipestat);
346 POSTING_READ(reg);
7c463586
KP		 347}
348
01c66889 349/**
f49e38dd 350 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 351 */
f49e38dd 352static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 353{
1ec14ad3
CW		 354 drm_i915_private_t *dev_priv = dev->dev_private;
355 unsigned long irqflags;
356
f49e38dd
JN		 357 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
358 return;
359
1ec14ad3 360 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 361
f898780b
JN		 362 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
363 if (INTEL_INFO(dev)->gen >= 4)
364 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 365
366 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 367}
368
0a3e67a4
JB		 369/**
370 * i915_pipe_enabled - check if a pipe is enabled
371 * @dev: DRM device
372 * @pipe: pipe to check
373 *
374 * Reading certain registers when the pipe is disabled can hang the chip.
375 * Use this routine to make sure the PLL is running and the pipe is active
376 * before reading such registers if unsure.
377 */
378static int
379i915_pipe_enabled(struct drm_device *dev, int pipe)
380{
381 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 382
a01025af
DV		 383 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
384 /* Locking is horribly broken here, but whatever. */
385 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 387
a01025af
DV		 388 return intel_crtc->active;
389 } else {
390 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
391 }
0a3e67a4
JB		 392}
393
42f52ef8
KP		 394/* Called from drm generic code, passed a 'crtc', which
395 * we use as a pipe index
396 */
f71d4af4 397static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 398{
399 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
400 unsigned long high_frame;
401 unsigned long low_frame;
5eddb70b 402 u32 high1, high2, low;
0a3e67a4
JB		 403
404 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 405 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 406 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 407 return 0;
408 }
409
9db4a9c7
JB		 410 high_frame = PIPEFRAME(pipe);
411 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 412
0a3e67a4
JB		 413 /*
414 * High & low register fields aren't synchronized, so make sure
415 * we get a low value that's stable across two reads of the high
416 * register.
417 */
418 do {
5eddb70b
CW		 419 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
420 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
421 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 422 } while (high1 != high2);
423
5eddb70b
CW		 424 high1 >>= PIPE_FRAME_HIGH_SHIFT;
425 low >>= PIPE_FRAME_LOW_SHIFT;
426 return (high1 << 8) | low;
0a3e67a4
JB		 427}
428
f71d4af4 429static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 430{
431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 432 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 433
434 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 435 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 436 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 437 return 0;
438 }
439
440 return I915_READ(reg);
441}
442
f71d4af4 443static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 444 int *vpos, int *hpos)
445{
446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
447 u32 vbl = 0, position = 0;
448 int vbl_start, vbl_end, htotal, vtotal;
449 bool in_vbl = true;
450 int ret = 0;
fe2b8f9d
PZ		 451 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
452 pipe);
0af7e4df
MK		 453
454 if (!i915_pipe_enabled(dev, pipe)) {
455 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 456 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 457 return 0;
458 }
459
460 /* Get vtotal. */
fe2b8f9d 461 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 462
463 if (INTEL_INFO(dev)->gen >= 4) {
464 /* No obvious pixelcount register. Only query vertical
465 * scanout position from Display scan line register.
466 */
467 position = I915_READ(PIPEDSL(pipe));
468
469 /* Decode into vertical scanout position. Don't have
470 * horizontal scanout position.
471 */
472 *vpos = position & 0x1fff;
473 *hpos = 0;
474 } else {
475 /* Have access to pixelcount since start of frame.
476 * We can split this into vertical and horizontal
477 * scanout position.
478 */
479 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
480
fe2b8f9d 481 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 482 *vpos = position / htotal;
483 *hpos = position - (*vpos * htotal);
484 }
485
486 /* Query vblank area. */
fe2b8f9d 487 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 488
489 /* Test position against vblank region. */
490 vbl_start = vbl & 0x1fff;
491 vbl_end = (vbl >> 16) & 0x1fff;
492
493 if ((*vpos < vbl_start) || (*vpos > vbl_end))
494 in_vbl = false;
495
496 /* Inside "upper part" of vblank area? Apply corrective offset: */
497 if (in_vbl && (*vpos >= vbl_start))
498 *vpos = *vpos - vtotal;
499
500 /* Readouts valid? */
501 if (vbl > 0)
502 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
503
504 /* In vblank? */
505 if (in_vbl)
506 ret |= DRM_SCANOUTPOS_INVBL;
507
508 return ret;
509}
510
f71d4af4 511static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 512 int *max_error,
513 struct timeval *vblank_time,
514 unsigned flags)
515{
4041b853 516 struct drm_crtc *crtc;
0af7e4df 517
7eb552ae 518 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 519 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 520 return -EINVAL;
521 }
522
523 /* Get drm_crtc to timestamp: */
4041b853
CW		 524 crtc = intel_get_crtc_for_pipe(dev, pipe);
525 if (crtc == NULL) {
526 DRM_ERROR("Invalid crtc %d\n", pipe);
527 return -EINVAL;
528 }
529
530 if (!crtc->enabled) {
531 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
532 return -EBUSY;
533 }
0af7e4df
MK		 534
535 /* Helper routine in DRM core does all the work: */
4041b853
CW		 536 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
537 vblank_time, flags,
538 crtc);
0af7e4df
MK		 539}
540
321a1b30
EE		 541static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
542{
543 enum drm_connector_status old_status;
544
545 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
546 old_status = connector->status;
547
548 connector->status = connector->funcs->detect(connector, false);
549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
550 connector->base.id,
551 drm_get_connector_name(connector),
552 old_status, connector->status);
553 return (old_status != connector->status);
554}
555
5ca58282
JB		 556/*
557 * Handle hotplug events outside the interrupt handler proper.
558 */
ac4c16c5
EE		 559#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
560
5ca58282
JB		 561static void i915_hotplug_work_func(struct work_struct *work)
562{
563 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
564 hotplug_work);
565 struct drm_device *dev = dev_priv->dev;
c31c4ba3 566 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 567 struct intel_connector *intel_connector;
568 struct intel_encoder *intel_encoder;
569 struct drm_connector *connector;
570 unsigned long irqflags;
571 bool hpd_disabled = false;
321a1b30 572 bool changed = false;
142e2398 573 u32 hpd_event_bits;
4ef69c7a 574
52d7eced
DV		 575 /* HPD irq before everything is fully set up. */
576 if (!dev_priv->enable_hotplug_processing)
577 return;
578
a65e34c7 579 mutex_lock(&mode_config->mutex);
e67189ab
JB		 580 DRM_DEBUG_KMS("running encoder hotplug functions\n");
581
cd569aed 582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 583
584 hpd_event_bits = dev_priv->hpd_event_bits;
585 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 586 list_for_each_entry(connector, &mode_config->connector_list, head) {
587 intel_connector = to_intel_connector(connector);
588 intel_encoder = intel_connector->encoder;
589 if (intel_encoder->hpd_pin > HPD_NONE &&
590 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
591 connector->polled == DRM_CONNECTOR_POLL_HPD) {
592 DRM_INFO("HPD interrupt storm detected on connector %s: "
593 "switching from hotplug detection to polling\n",
594 drm_get_connector_name(connector));
595 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
596 connector->polled = DRM_CONNECTOR_POLL_CONNECT
597 | DRM_CONNECTOR_POLL_DISCONNECT;
598 hpd_disabled = true;
599 }
142e2398
EE		 600 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
601 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
602 drm_get_connector_name(connector), intel_encoder->hpd_pin);
603 }
cd569aed
EE		 604 }
605 /* if there were no outputs to poll, poll was disabled,
606 * therefore make sure it's enabled when disabling HPD on
607 * some connectors */
ac4c16c5 608 if (hpd_disabled) {
cd569aed 609 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 610 mod_timer(&dev_priv->hotplug_reenable_timer,
611 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
612 }
cd569aed
EE		 613
614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
615
321a1b30
EE		 616 list_for_each_entry(connector, &mode_config->connector_list, head) {
617 intel_connector = to_intel_connector(connector);
618 intel_encoder = intel_connector->encoder;
619 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
620 if (intel_encoder->hot_plug)
621 intel_encoder->hot_plug(intel_encoder);
622 if (intel_hpd_irq_event(dev, connector))
623 changed = true;
624 }
625 }
40ee3381
KP		 626 mutex_unlock(&mode_config->mutex);
627
321a1b30
EE		 628 if (changed)
629 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 630}
631
73edd18f 632static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 633{
634 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 635 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 636 u8 new_delay;
637 unsigned long flags;
638
639 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 640
73edd18f
DV		 641 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
642
20e4d407 643 new_delay = dev_priv->ips.cur_delay;
9270388e 644
7648fa99 645 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 646 busy_up = I915_READ(RCPREVBSYTUPAVG);
647 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 648 max_avg = I915_READ(RCBMAXAVG);
649 min_avg = I915_READ(RCBMINAVG);
650
651 /* Handle RCS change request from hw */
b5b72e89 652 if (busy_up > max_avg) {
20e4d407
DV		 653 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
654 new_delay = dev_priv->ips.cur_delay - 1;
655 if (new_delay < dev_priv->ips.max_delay)
656 new_delay = dev_priv->ips.max_delay;
b5b72e89 657 } else if (busy_down < min_avg) {
20e4d407
DV		 658 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
659 new_delay = dev_priv->ips.cur_delay + 1;
660 if (new_delay > dev_priv->ips.min_delay)
661 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 662 }
663
7648fa99 664 if (ironlake_set_drps(dev, new_delay))
20e4d407 665 dev_priv->ips.cur_delay = new_delay;
f97108d1 666
9270388e
DV		 667 spin_unlock_irqrestore(&mchdev_lock, flags);
668
f97108d1
JB		 669 return;
670}
671
549f7365
CW		 672static void notify_ring(struct drm_device *dev,
673 struct intel_ring_buffer *ring)
674{
675 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 676
475553de
CW		 677 if (ring->obj == NULL)
678 return;
679
b2eadbc8 680 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 681
549f7365 682 wake_up_all(&ring->irq_queue);
3e0dc6b0 683 if (i915_enable_hangcheck) {
99584db3 684 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 685 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 686 }
549f7365
CW		 687}
688
4912d041 689static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 690{
4912d041 691 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 692 rps.work);
4912d041 693 u32 pm_iir, pm_imr;
7b9e0ae6 694 u8 new_delay;
4912d041 695
c6a828d3
DV		 696 spin_lock_irq(&dev_priv->rps.lock);
697 pm_iir = dev_priv->rps.pm_iir;
698 dev_priv->rps.pm_iir = 0;
4912d041 699 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 700 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
701 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 702 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 703
4848405c 704 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 705 return;
706
4fc688ce 707 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 708
7425034a 709 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 710 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 711
712 /*
713 * For better performance, jump directly
714 * to RPe if we're below it.
715 */
716 if (IS_VALLEYVIEW(dev_priv->dev) &&
717 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
718 new_delay = dev_priv->rps.rpe_delay;
719 } else
c6a828d3 720 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 721
79249636
BW		 722 /* sysfs frequency interfaces may have snuck in while servicing the
723 * interrupt
724 */
d8289c9e
VS		 725 if (new_delay >= dev_priv->rps.min_delay &&
726 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 727 if (IS_VALLEYVIEW(dev_priv->dev))
728 valleyview_set_rps(dev_priv->dev, new_delay);
729 else
730 gen6_set_rps(dev_priv->dev, new_delay);
79249636 731 }
3b8d8d91 732
52ceb908
JB		 733 if (IS_VALLEYVIEW(dev_priv->dev)) {
734 /*
735 * On VLV, when we enter RC6 we may not be at the minimum
736 * voltage level, so arm a timer to check. It should only
737 * fire when there's activity or once after we've entered
738 * RC6, and then won't be re-armed until the next RPS interrupt.
739 */
740 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
741 msecs_to_jiffies(100));
742 }
743
4fc688ce 744 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 745}
746
e3689190
BW		 747
748/**
749 * ivybridge_parity_work - Workqueue called when a parity error interrupt
750 * occurred.
751 * @work: workqueue struct
752 *
753 * Doesn't actually do anything except notify userspace. As a consequence of
754 * this event, userspace should try to remap the bad rows since statistically
755 * it is likely the same row is more likely to go bad again.
756 */
757static void ivybridge_parity_work(struct work_struct *work)
758{
759 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 760 l3_parity.error_work);
e3689190
BW		 761 u32 error_status, row, bank, subbank;
762 char *parity_event[5];
763 uint32_t misccpctl;
764 unsigned long flags;
765
766 /* We must turn off DOP level clock gating to access the L3 registers.
767 * In order to prevent a get/put style interface, acquire struct mutex
768 * any time we access those registers.
769 */
770 mutex_lock(&dev_priv->dev->struct_mutex);
771
772 misccpctl = I915_READ(GEN7_MISCCPCTL);
773 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
774 POSTING_READ(GEN7_MISCCPCTL);
775
776 error_status = I915_READ(GEN7_L3CDERRST1);
777 row = GEN7_PARITY_ERROR_ROW(error_status);
778 bank = GEN7_PARITY_ERROR_BANK(error_status);
779 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
780
781 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
782 GEN7_L3CDERRST1_ENABLE);
783 POSTING_READ(GEN7_L3CDERRST1);
784
785 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
786
787 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 788 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 789 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
790 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
791
792 mutex_unlock(&dev_priv->dev->struct_mutex);
793
794 parity_event[0] = "L3_PARITY_ERROR=1";
795 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
796 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
797 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
798 parity_event[4] = NULL;
799
800 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
801 KOBJ_CHANGE, parity_event);
802
803 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
804 row, bank, subbank);
805
806 kfree(parity_event[3]);
807 kfree(parity_event[2]);
808 kfree(parity_event[1]);
809}
810
d2ba8470 811static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 812{
813 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
814 unsigned long flags;
815
e1ef7cc2 816 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 817 return;
818
819 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 820 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 821 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
822 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
823
a4da4fa4 824 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 825}
826
e7b4c6b1
DV		 827static void snb_gt_irq_handler(struct drm_device *dev,
828 struct drm_i915_private *dev_priv,
829 u32 gt_iir)
830{
831
cc609d5d
BW		 832 if (gt_iir &
833 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 834 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 835 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 836 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 837 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 838 notify_ring(dev, &dev_priv->ring[BCS]);
839
cc609d5d
BW		 840 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
841 GT_BSD_CS_ERROR_INTERRUPT |
842 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 843 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
844 i915_handle_error(dev, false);
845 }
e3689190 846
cc609d5d 847 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
e3689190 848 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 849}
850
baf02a1f 851/* Legacy way of handling PM interrupts */
fc6826d1
CW		 852static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
853 u32 pm_iir)
854{
855 unsigned long flags;
856
857 /*
858 * IIR bits should never already be set because IMR should
859 * prevent an interrupt from being shown in IIR. The warning
860 * displays a case where we've unsafely cleared
c6a828d3 861 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 862 * type is not a problem, it displays a problem in the logic.
863 *
c6a828d3 864 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 865 */
866
c6a828d3 867 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 868 dev_priv->rps.pm_iir |= pm_iir;
869 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 870 POSTING_READ(GEN6_PMIMR);
c6a828d3 871 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 872
c6a828d3 873 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 874}
875
b543fb04
EE		 876#define HPD_STORM_DETECT_PERIOD 1000
877#define HPD_STORM_THRESHOLD 5
878
10a504de 879static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 880 u32 hotplug_trigger,
881 const u32 *hpd)
b543fb04
EE		 882{
883 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 884 int i;
10a504de 885 bool storm_detected = false;
b543fb04 886
91d131d2
DV		 887 if (!hotplug_trigger)
888 return;
889
b5ea2d56 890 spin_lock(&dev_priv->irq_lock);
b543fb04 891 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 892
b543fb04
EE		 893 if (!(hpd[i] & hotplug_trigger) ||
894 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
895 continue;
896
bc5ead8c 897 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 898 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
899 dev_priv->hpd_stats[i].hpd_last_jiffies
900 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
901 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
902 dev_priv->hpd_stats[i].hpd_cnt = 0;
903 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
904 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 905 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 906 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 907 storm_detected = true;
b543fb04
EE		 908 } else {
909 dev_priv->hpd_stats[i].hpd_cnt++;
910 }
911 }
912
10a504de
DV		 913 if (storm_detected)
914 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 915 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 916
917 queue_work(dev_priv->wq,
918 &dev_priv->hotplug_work);
b543fb04
EE		 919}
920
515ac2bb
DV		 921static void gmbus_irq_handler(struct drm_device *dev)
922{
28c70f16
DV		 923 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
924
28c70f16 925 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 926}
927
ce99c256
DV		 928static void dp_aux_irq_handler(struct drm_device *dev)
929{
9ee32fea
DV		 930 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
931
9ee32fea 932 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 933}
934
baf02a1f
BW		 935/* Unlike gen6_queue_rps_work() from which this function is originally derived,
936 * we must be able to deal with other PM interrupts. This is complicated because
937 * of the way in which we use the masks to defer the RPS work (which for
938 * posterity is necessary because of forcewake).
939 */
940static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
941 u32 pm_iir)
942{
943 unsigned long flags;
944
945 spin_lock_irqsave(&dev_priv->rps.lock, flags);
4848405c 946 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 947 if (dev_priv->rps.pm_iir) {
948 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
949 /* never want to mask useful interrupts. (also posting read) */
4848405c 950 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 951 /* TODO: if queue_work is slow, move it out of the spinlock */
952 queue_work(dev_priv->wq, &dev_priv->rps.work);
953 }
954 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
955
12638c57
BW		 956 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
957 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
958 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
959
960 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
961 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
962 i915_handle_error(dev_priv->dev, false);
963 }
964 }
baf02a1f
BW		 965}
966
ff1f525e 967static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 968{
969 struct drm_device *dev = (struct drm_device *) arg;
970 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
971 u32 iir, gt_iir, pm_iir;
972 irqreturn_t ret = IRQ_NONE;
973 unsigned long irqflags;
974 int pipe;
975 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 976
977 atomic_inc(&dev_priv->irq_received);
978
7e231dbe
JB		 979 while (true) {
980 iir = I915_READ(VLV_IIR);
981 gt_iir = I915_READ(GTIIR);
982 pm_iir = I915_READ(GEN6_PMIIR);
983
984 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
985 goto out;
986
987 ret = IRQ_HANDLED;
988
e7b4c6b1 989 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 990
991 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
992 for_each_pipe(pipe) {
993 int reg = PIPESTAT(pipe);
994 pipe_stats[pipe] = I915_READ(reg);
995
996 /*
997 * Clear the PIPE*STAT regs before the IIR
998 */
999 if (pipe_stats[pipe] & 0x8000ffff) {
1000 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1001 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1002 pipe_name(pipe));
1003 I915_WRITE(reg, pipe_stats[pipe]);
1004 }
1005 }
1006 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1007
31acc7f5
JB		 1008 for_each_pipe(pipe) {
1009 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1010 drm_handle_vblank(dev, pipe);
1011
1012 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1013 intel_prepare_page_flip(dev, pipe);
1014 intel_finish_page_flip(dev, pipe);
1015 }
1016 }
1017
7e231dbe
JB		 1018 /* Consume port. Then clear IIR or we'll miss events */
1019 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1020 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1021 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1022
1023 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1024 hotplug_status);
91d131d2
DV		 1025
1026 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1027
7e231dbe
JB		 1028 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1029 I915_READ(PORT_HOTPLUG_STAT);
1030 }
1031
515ac2bb
DV		 1032 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1033 gmbus_irq_handler(dev);
7e231dbe 1034
4848405c 1035 if (pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1036 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 1037
1038 I915_WRITE(GTIIR, gt_iir);
1039 I915_WRITE(GEN6_PMIIR, pm_iir);
1040 I915_WRITE(VLV_IIR, iir);
1041 }
1042
1043out:
1044 return ret;
1045}
1046
23e81d69 1047static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1048{
1049 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1050 int pipe;
b543fb04 1051 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1052
91d131d2
DV		 1053 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1054
cfc33bf7
VS		 1055 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1056 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1057 SDE_AUDIO_POWER_SHIFT);
776ad806 1058 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1059 port_name(port));
1060 }
776ad806 1061
ce99c256
DV		 1062 if (pch_iir & SDE_AUX_MASK)
1063 dp_aux_irq_handler(dev);
1064
776ad806 1065 if (pch_iir & SDE_GMBUS)
515ac2bb 1066 gmbus_irq_handler(dev);
776ad806
JB		 1067
1068 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1069 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1070
1071 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1072 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1073
1074 if (pch_iir & SDE_POISON)
1075 DRM_ERROR("PCH poison interrupt\n");
1076
9db4a9c7
JB		 1077 if (pch_iir & SDE_FDI_MASK)
1078 for_each_pipe(pipe)
1079 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1080 pipe_name(pipe),
1081 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1082
1083 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1084 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1085
1086 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1087 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1088
776ad806 1089 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1090 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1091 false))
1092 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1093
1094 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1095 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1096 false))
1097 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1098}
1099
1100static void ivb_err_int_handler(struct drm_device *dev)
1101{
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 u32 err_int = I915_READ(GEN7_ERR_INT);
1104
de032bf4
PZ		 1105 if (err_int & ERR_INT_POISON)
1106 DRM_ERROR("Poison interrupt\n");
1107
8664281b
PZ		 1108 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1109 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1110 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1111
1112 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1113 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1114 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1115
1116 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1117 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1118 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1119
1120 I915_WRITE(GEN7_ERR_INT, err_int);
1121}
1122
1123static void cpt_serr_int_handler(struct drm_device *dev)
1124{
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 u32 serr_int = I915_READ(SERR_INT);
1127
de032bf4
PZ		 1128 if (serr_int & SERR_INT_POISON)
1129 DRM_ERROR("PCH poison interrupt\n");
1130
8664281b
PZ		 1131 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1132 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1133 false))
1134 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1135
1136 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1137 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1138 false))
1139 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1140
1141 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1142 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1143 false))
1144 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1145
1146 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1147}
1148
23e81d69
AJ		 1149static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1150{
1151 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1152 int pipe;
b543fb04 1153 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1154
91d131d2
DV		 1155 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1156
cfc33bf7
VS		 1157 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1158 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1159 SDE_AUDIO_POWER_SHIFT_CPT);
1160 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1161 port_name(port));
1162 }
23e81d69
AJ		 1163
1164 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1165 dp_aux_irq_handler(dev);
23e81d69
AJ		 1166
1167 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1168 gmbus_irq_handler(dev);
23e81d69
AJ		 1169
1170 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1171 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1172
1173 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1174 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1175
1176 if (pch_iir & SDE_FDI_MASK_CPT)
1177 for_each_pipe(pipe)
1178 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1179 pipe_name(pipe),
1180 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1181
1182 if (pch_iir & SDE_ERROR_CPT)
1183 cpt_serr_int_handler(dev);
23e81d69
AJ		 1184}
1185
ff1f525e 1186static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1187{
1188 struct drm_device *dev = (struct drm_device *) arg;
1189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1190 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1191 irqreturn_t ret = IRQ_NONE;
1192 int i;
b1f14ad0
JB		 1193
1194 atomic_inc(&dev_priv->irq_received);
1195
8664281b
PZ		 1196 /* We get interrupts on unclaimed registers, so check for this before we
1197 * do any I915_{READ,WRITE}. */
1198 if (IS_HASWELL(dev) &&
1199 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1200 DRM_ERROR("Unclaimed register before interrupt\n");
1201 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1202 }
1203
b1f14ad0
JB		 1204 /* disable master interrupt before clearing iir */
1205 de_ier = I915_READ(DEIER);
1206 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1207
44498aea
PZ		 1208 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1209 * interrupts will will be stored on its back queue, and then we'll be
1210 * able to process them after we restore SDEIER (as soon as we restore
1211 * it, we'll get an interrupt if SDEIIR still has something to process
1212 * due to its back queue). */
ab5c608b
BW		 1213 if (!HAS_PCH_NOP(dev)) {
1214 sde_ier = I915_READ(SDEIER);
1215 I915_WRITE(SDEIER, 0);
1216 POSTING_READ(SDEIER);
1217 }
44498aea 1218
8664281b
PZ		 1219 /* On Haswell, also mask ERR_INT because we don't want to risk
1220 * generating "unclaimed register" interrupts from inside the interrupt
1221 * handler. */
4bc9d430
DV		 1222 if (IS_HASWELL(dev)) {
1223 spin_lock(&dev_priv->irq_lock);
8664281b 1224 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1225 spin_unlock(&dev_priv->irq_lock);
1226 }
8664281b 1227
b1f14ad0 1228 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1229 if (gt_iir) {
1230 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1231 I915_WRITE(GTIIR, gt_iir);
1232 ret = IRQ_HANDLED;
b1f14ad0
JB		 1233 }
1234
0e43406b
CW		 1235 de_iir = I915_READ(DEIIR);
1236 if (de_iir) {
8664281b
PZ		 1237 if (de_iir & DE_ERR_INT_IVB)
1238 ivb_err_int_handler(dev);
1239
ce99c256
DV		 1240 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1241 dp_aux_irq_handler(dev);
1242
0e43406b 1243 if (de_iir & DE_GSE_IVB)
81a07809 1244 intel_opregion_asle_intr(dev);
0e43406b
CW		 1245
1246 for (i = 0; i < 3; i++) {
74d44445
DV		 1247 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1248 drm_handle_vblank(dev, i);
0e43406b
CW		 1249 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1250 intel_prepare_page_flip(dev, i);
1251 intel_finish_page_flip_plane(dev, i);
1252 }
0e43406b 1253 }
b615b57a 1254
0e43406b 1255 /* check event from PCH */
ab5c608b 1256 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1257 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1258
23e81d69 1259 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1260
0e43406b
CW		 1261 /* clear PCH hotplug event before clear CPU irq */
1262 I915_WRITE(SDEIIR, pch_iir);
1263 }
b615b57a 1264
0e43406b
CW		 1265 I915_WRITE(DEIIR, de_iir);
1266 ret = IRQ_HANDLED;
b1f14ad0
JB		 1267 }
1268
0e43406b
CW		 1269 pm_iir = I915_READ(GEN6_PMIIR);
1270 if (pm_iir) {
baf02a1f
BW		 1271 if (IS_HASWELL(dev))
1272 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1273 else if (pm_iir & GEN6_PM_RPS_EVENTS)
0e43406b
CW		 1274 gen6_queue_rps_work(dev_priv, pm_iir);
1275 I915_WRITE(GEN6_PMIIR, pm_iir);
1276 ret = IRQ_HANDLED;
1277 }
b1f14ad0 1278
4bc9d430
DV		 1279 if (IS_HASWELL(dev)) {
1280 spin_lock(&dev_priv->irq_lock);
1281 if (ivb_can_enable_err_int(dev))
1282 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1283 spin_unlock(&dev_priv->irq_lock);
1284 }
8664281b 1285
b1f14ad0
JB		 1286 I915_WRITE(DEIER, de_ier);
1287 POSTING_READ(DEIER);
ab5c608b
BW		 1288 if (!HAS_PCH_NOP(dev)) {
1289 I915_WRITE(SDEIER, sde_ier);
1290 POSTING_READ(SDEIER);
1291 }
b1f14ad0
JB		 1292
1293 return ret;
1294}
1295
e7b4c6b1
DV		 1296static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299{
cc609d5d
BW		 1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1302 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305}
1306
ff1f525e 1307static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1308{
4697995b 1309 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1311 int ret = IRQ_NONE;
44498aea 1312 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1313
4697995b
JB		 1314 atomic_inc(&dev_priv->irq_received);
1315
2d109a84
ZN		 1316 /* disable master interrupt before clearing iir */
1317 de_ier = I915_READ(DEIER);
1318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1319 POSTING_READ(DEIER);
2d109a84 1320
44498aea
PZ		 1321 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1322 * interrupts will will be stored on its back queue, and then we'll be
1323 * able to process them after we restore SDEIER (as soon as we restore
1324 * it, we'll get an interrupt if SDEIIR still has something to process
1325 * due to its back queue). */
1326 sde_ier = I915_READ(SDEIER);
1327 I915_WRITE(SDEIER, 0);
1328 POSTING_READ(SDEIER);
1329
036a4a7d
ZW		 1330 de_iir = I915_READ(DEIIR);
1331 gt_iir = I915_READ(GTIIR);
3b8d8d91 1332 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1333
acd15b6c 1334 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1335 goto done;
036a4a7d 1336
c7c85101 1337 ret = IRQ_HANDLED;
036a4a7d 1338
e7b4c6b1
DV		 1339 if (IS_GEN5(dev))
1340 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1341 else
1342 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1343
ce99c256
DV		 1344 if (de_iir & DE_AUX_CHANNEL_A)
1345 dp_aux_irq_handler(dev);
1346
c7c85101 1347 if (de_iir & DE_GSE)
81a07809 1348 intel_opregion_asle_intr(dev);
c650156a 1349
74d44445
DV		 1350 if (de_iir & DE_PIPEA_VBLANK)
1351 drm_handle_vblank(dev, 0);
1352
1353 if (de_iir & DE_PIPEB_VBLANK)
1354 drm_handle_vblank(dev, 1);
1355
de032bf4
PZ		 1356 if (de_iir & DE_POISON)
1357 DRM_ERROR("Poison interrupt\n");
1358
8664281b
PZ		 1359 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1360 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1361 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1362
1363 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1364 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1365 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1366
f072d2e7 1367 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1368 intel_prepare_page_flip(dev, 0);
2bbda389 1369 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1370 }
013d5aa2 1371
f072d2e7 1372 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1373 intel_prepare_page_flip(dev, 1);
2bbda389 1374 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1375 }
013d5aa2 1376
c7c85101 1377 /* check event from PCH */
776ad806 1378 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1379 u32 pch_iir = I915_READ(SDEIIR);
1380
23e81d69
AJ		 1381 if (HAS_PCH_CPT(dev))
1382 cpt_irq_handler(dev, pch_iir);
1383 else
1384 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1385
1386 /* should clear PCH hotplug event before clear CPU irq */
1387 I915_WRITE(SDEIIR, pch_iir);
776ad806 1388 }
036a4a7d 1389
73edd18f
DV		 1390 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1391 ironlake_handle_rps_change(dev);
f97108d1 1392
4848405c 1393 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1394 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1395
c7c85101
ZN		 1396 I915_WRITE(GTIIR, gt_iir);
1397 I915_WRITE(DEIIR, de_iir);
4912d041 1398 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1399
1400done:
2d109a84 1401 I915_WRITE(DEIER, de_ier);
3143a2bf 1402 POSTING_READ(DEIER);
44498aea
PZ		 1403 I915_WRITE(SDEIER, sde_ier);
1404 POSTING_READ(SDEIER);
2d109a84 1405
036a4a7d
ZW		 1406 return ret;
1407}
1408
8a905236
JB		 1409/**
1410 * i915_error_work_func - do process context error handling work
1411 * @work: work struct
1412 *
1413 * Fire an error uevent so userspace can see that a hang or error
1414 * was detected.
1415 */
1416static void i915_error_work_func(struct work_struct *work)
1417{
1f83fee0
DV		 1418 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1419 work);
1420 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1421 gpu_error);
8a905236 1422 struct drm_device *dev = dev_priv->dev;
f69061be 1423 struct intel_ring_buffer *ring;
f316a42c
BG		 1424 char *error_event[] = { "ERROR=1", NULL };
1425 char *reset_event[] = { "RESET=1", NULL };
1426 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1427 int i, ret;
8a905236 1428
f316a42c
BG		 1429 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1430
7db0ba24
DV		 1431 /*
1432 * Note that there's only one work item which does gpu resets, so we
1433 * need not worry about concurrent gpu resets potentially incrementing
1434 * error->reset_counter twice. We only need to take care of another
1435 * racing irq/hangcheck declaring the gpu dead for a second time. A
1436 * quick check for that is good enough: schedule_work ensures the
1437 * correct ordering between hang detection and this work item, and since
1438 * the reset in-progress bit is only ever set by code outside of this
1439 * work we don't need to worry about any other races.
1440 */
1441 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1442 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1443 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1444 reset_event);
1f83fee0 1445
f69061be
DV		 1446 ret = i915_reset(dev);
1447
1448 if (ret == 0) {
1449 /*
1450 * After all the gem state is reset, increment the reset
1451 * counter and wake up everyone waiting for the reset to
1452 * complete.
1453 *
1454 * Since unlock operations are a one-sided barrier only,
1455 * we need to insert a barrier here to order any seqno
1456 * updates before
1457 * the counter increment.
1458 */
1459 smp_mb__before_atomic_inc();
1460 atomic_inc(&dev_priv->gpu_error.reset_counter);
1461
1462 kobject_uevent_env(&dev->primary->kdev.kobj,
1463 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1464 } else {
1465 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1466 }
1f83fee0 1467
f69061be
DV		 1468 for_each_ring(ring, dev_priv, i)
1469 wake_up_all(&ring->irq_queue);
1470
96a02917
VS		 1471 intel_display_handle_reset(dev);
1472
1f83fee0 1473 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1474 }
8a905236
JB		 1475}
1476
85f9e50d
DV		 1477/* NB: please notice the memset */
1478static void i915_get_extra_instdone(struct drm_device *dev,
1479 uint32_t *instdone)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1483
1484 switch(INTEL_INFO(dev)->gen) {
1485 case 2:
1486 case 3:
1487 instdone[0] = I915_READ(INSTDONE);
1488 break;
1489 case 4:
1490 case 5:
1491 case 6:
1492 instdone[0] = I915_READ(INSTDONE_I965);
1493 instdone[1] = I915_READ(INSTDONE1);
1494 break;
1495 default:
1496 WARN_ONCE(1, "Unsupported platform\n");
1497 case 7:
1498 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1499 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1500 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1501 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1502 break;
1503 }
1504}
1505
3bd3c932 1506#ifdef CONFIG_DEBUG_FS
9df30794 1507static struct drm_i915_error_object *
d0d045e8
BW		 1508i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1509 struct drm_i915_gem_object *src,
1510 const int num_pages)
9df30794
CW		 1511{
1512 struct drm_i915_error_object *dst;
d0d045e8 1513 int i;
e56660dd 1514 u32 reloc_offset;
9df30794 1515
05394f39 1516 if (src == NULL || src->pages == NULL)
9df30794
CW		 1517 return NULL;
1518
d0d045e8 1519 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1520 if (dst == NULL)
1521 return NULL;
1522
f343c5f6 1523 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
d0d045e8 1524 for (i = 0; i < num_pages; i++) {
788885ae 1525 unsigned long flags;
e56660dd 1526 void *d;
788885ae 1527
e56660dd 1528 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1529 if (d == NULL)
1530 goto unwind;
e56660dd 1531
788885ae 1532 local_irq_save(flags);
5d4545ae 1533 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1534 src->has_global_gtt_mapping) {
172975aa
CW		 1535 void __iomem *s;
1536
1537 /* Simply ignore tiling or any overlapping fence.
1538 * It's part of the error state, and this hopefully
1539 * captures what the GPU read.
1540 */
1541
5d4545ae 1542 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1543 reloc_offset);
1544 memcpy_fromio(d, s, PAGE_SIZE);
1545 io_mapping_unmap_atomic(s);
960e3564
CW		 1546 } else if (src->stolen) {
1547 unsigned long offset;
1548
1549 offset = dev_priv->mm.stolen_base;
1550 offset += src->stolen->start;
1551 offset += i << PAGE_SHIFT;
1552
1a240d4d 1553 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1554 } else {
9da3da66 1555 struct page *page;
172975aa
CW		 1556 void *s;
1557
9da3da66 1558 page = i915_gem_object_get_page(src, i);
172975aa 1559
9da3da66
CW		 1560 drm_clflush_pages(&page, 1);
1561
1562 s = kmap_atomic(page);
172975aa
CW		 1563 memcpy(d, s, PAGE_SIZE);
1564 kunmap_atomic(s);
1565
9da3da66 1566 drm_clflush_pages(&page, 1);
172975aa 1567 }
788885ae 1568 local_irq_restore(flags);
e56660dd 1569
9da3da66 1570 dst->pages[i] = d;
e56660dd
CW		 1571
1572 reloc_offset += PAGE_SIZE;
9df30794 1573 }
d0d045e8 1574 dst->page_count = num_pages;
9df30794
CW		 1575
1576 return dst;
1577
1578unwind:
9da3da66
CW		 1579 while (i--)
1580 kfree(dst->pages[i]);
9df30794
CW		 1581 kfree(dst);
1582 return NULL;
1583}
d0d045e8
BW		 1584#define i915_error_object_create(dev_priv, src) \
1585 i915_error_object_create_sized((dev_priv), (src), \
1586 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1587
1588static void
1589i915_error_object_free(struct drm_i915_error_object *obj)
1590{
1591 int page;
1592
1593 if (obj == NULL)
1594 return;
1595
1596 for (page = 0; page < obj->page_count; page++)
1597 kfree(obj->pages[page]);
1598
1599 kfree(obj);
1600}
1601
742cbee8
DV		 1602void
1603i915_error_state_free(struct kref *error_ref)
9df30794 1604{
742cbee8
DV		 1605 struct drm_i915_error_state *error = container_of(error_ref,
1606 typeof(*error), ref);
e2f973d5
CW		 1607 int i;
1608
52d39a21
CW		 1609 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1610 i915_error_object_free(error->ring[i].batchbuffer);
1611 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1612 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1613 kfree(error->ring[i].requests);
1614 }
e2f973d5 1615
9df30794 1616 kfree(error->active_bo);
6ef3d427 1617 kfree(error->overlay);
7ed73da0 1618 kfree(error->display);
9df30794
CW		 1619 kfree(error);
1620}
1b50247a
CW		 1621static void capture_bo(struct drm_i915_error_buffer *err,
1622 struct drm_i915_gem_object *obj)
1623{
1624 err->size = obj->base.size;
1625 err->name = obj->base.name;
0201f1ec
CW		 1626 err->rseqno = obj->last_read_seqno;
1627 err->wseqno = obj->last_write_seqno;
f343c5f6 1628 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
1b50247a
CW		 1629 err->read_domains = obj->base.read_domains;
1630 err->write_domain = obj->base.write_domain;
1631 err->fence_reg = obj->fence_reg;
1632 err->pinned = 0;
1633 if (obj->pin_count > 0)
1634 err->pinned = 1;
1635 if (obj->user_pin_count > 0)
1636 err->pinned = -1;
1637 err->tiling = obj->tiling_mode;
1638 err->dirty = obj->dirty;
1639 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1640 err->ring = obj->ring ? obj->ring->id : -1;
1641 err->cache_level = obj->cache_level;
1642}
9df30794 1643
1b50247a
CW		 1644static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1645 int count, struct list_head *head)
c724e8a9
CW		 1646{
1647 struct drm_i915_gem_object *obj;
1648 int i = 0;
1649
1650 list_for_each_entry(obj, head, mm_list) {
1b50247a 1651 capture_bo(err++, obj);
c724e8a9
CW		 1652 if (++i == count)
1653 break;
1b50247a
CW		 1654 }
1655
1656 return i;
1657}
1658
1659static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1660 int count, struct list_head *head)
1661{
1662 struct drm_i915_gem_object *obj;
1663 int i = 0;
1664
35c20a60 1665 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1666 if (obj->pin_count == 0)
1667 continue;
c724e8a9 1668
1b50247a
CW		 1669 capture_bo(err++, obj);
1670 if (++i == count)
1671 break;
c724e8a9
CW		 1672 }
1673
1674 return i;
1675}
1676
748ebc60
CW		 1677static void i915_gem_record_fences(struct drm_device *dev,
1678 struct drm_i915_error_state *error)
1679{
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 int i;
1682
1683 /* Fences */
1684 switch (INTEL_INFO(dev)->gen) {
775d17b6 1685 case 7:
748ebc60 1686 case 6:
42b5aeab 1687 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1688 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1689 break;
1690 case 5:
1691 case 4:
1692 for (i = 0; i < 16; i++)
1693 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1694 break;
1695 case 3:
1696 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1697 for (i = 0; i < 8; i++)
1698 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1699 case 2:
1700 for (i = 0; i < 8; i++)
1701 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1702 break;
1703
7dbf9d6e
BW		 1704 default:
1705 BUG();
748ebc60
CW		 1706 }
1707}
1708
bcfb2e28
CW		 1709static struct drm_i915_error_object *
1710i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1711 struct intel_ring_buffer *ring)
1712{
1713 struct drm_i915_gem_object *obj;
1714 u32 seqno;
1715
1716 if (!ring->get_seqno)
1717 return NULL;
1718
b45305fc
DV		 1719 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1720 u32 acthd = I915_READ(ACTHD);
1721
1722 if (WARN_ON(ring->id != RCS))
1723 return NULL;
1724
1725 obj = ring->private;
f343c5f6
BW		 1726 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
1727 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
b45305fc
DV		 1728 return i915_error_object_create(dev_priv, obj);
1729 }
1730
b2eadbc8 1731 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1732 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1733 if (obj->ring != ring)
1734 continue;
1735
0201f1ec 1736 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1737 continue;
1738
1739 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1740 continue;
1741
1742 /* We need to copy these to an anonymous buffer as the simplest
1743 * method to avoid being overwritten by userspace.
1744 */
1745 return i915_error_object_create(dev_priv, obj);
1746 }
1747
1748 return NULL;
1749}
1750
d27b1e0e
DV		 1751static void i915_record_ring_state(struct drm_device *dev,
1752 struct drm_i915_error_state *error,
1753 struct intel_ring_buffer *ring)
1754{
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1756
33f3f518 1757 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1758 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1759 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1760 error->semaphore_mboxes[ring->id][0]
1761 = I915_READ(RING_SYNC_0(ring->mmio_base));
1762 error->semaphore_mboxes[ring->id][1]
1763 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1764 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1765 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1766 }
c1cd90ed 1767
d27b1e0e 1768 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1769 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1770 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1771 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1772 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1773 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1774 if (ring->id == RCS)
d27b1e0e 1775 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1776 } else {
9d2f41fa 1777 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1778 error->ipeir[ring->id] = I915_READ(IPEIR);
1779 error->ipehr[ring->id] = I915_READ(IPEHR);
1780 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1781 }
1782
9574b3fe 1783 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1784 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1785 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1786 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1787 error->head[ring->id] = I915_READ_HEAD(ring);
1788 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1789 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1790
1791 error->cpu_ring_head[ring->id] = ring->head;
1792 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1793}
1794
8c123e54
BW		 1795
1796static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1797 struct drm_i915_error_state *error,
1798 struct drm_i915_error_ring *ering)
1799{
1800 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1801 struct drm_i915_gem_object *obj;
1802
1803 /* Currently render ring is the only HW context user */
1804 if (ring->id != RCS || !error->ccid)
1805 return;
1806
35c20a60 1807 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
f343c5f6 1808 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
8c123e54
BW		 1809 ering->ctx = i915_error_object_create_sized(dev_priv,
1810 obj, 1);
3ef8fb5a 1811 break;
8c123e54
BW		 1812 }
1813 }
1814}
1815
52d39a21
CW		 1816static void i915_gem_record_rings(struct drm_device *dev,
1817 struct drm_i915_error_state *error)
1818{
1819 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1820 struct intel_ring_buffer *ring;
52d39a21
CW		 1821 struct drm_i915_gem_request *request;
1822 int i, count;
1823
b4519513 1824 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1825 i915_record_ring_state(dev, error, ring);
1826
1827 error->ring[i].batchbuffer =
1828 i915_error_first_batchbuffer(dev_priv, ring);
1829
1830 error->ring[i].ringbuffer =
1831 i915_error_object_create(dev_priv, ring->obj);
1832
8c123e54
BW		 1833
1834 i915_gem_record_active_context(ring, error, &error->ring[i]);
1835
52d39a21
CW		 1836 count = 0;
1837 list_for_each_entry(request, &ring->request_list, list)
1838 count++;
1839
1840 error->ring[i].num_requests = count;
1841 error->ring[i].requests =
1842 kmalloc(count*sizeof(struct drm_i915_error_request),
1843 GFP_ATOMIC);
1844 if (error->ring[i].requests == NULL) {
1845 error->ring[i].num_requests = 0;
1846 continue;
1847 }
1848
1849 count = 0;
1850 list_for_each_entry(request, &ring->request_list, list) {
1851 struct drm_i915_error_request *erq;
1852
1853 erq = &error->ring[i].requests[count++];
1854 erq->seqno = request->seqno;
1855 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1856 erq->tail = request->tail;
52d39a21
CW		 1857 }
1858 }
1859}
1860
26b7c224
BW		 1861static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1862 struct drm_i915_error_state *error)
1863{
1864 struct drm_i915_gem_object *obj;
1865 int i;
1866
1867 i = 0;
1868 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1869 i++;
1870 error->active_bo_count = i;
1871 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1872 if (obj->pin_count)
1873 i++;
1874 error->pinned_bo_count = i - error->active_bo_count;
1875
1876 if (i) {
1877 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1878 GFP_ATOMIC);
1879 if (error->active_bo)
1880 error->pinned_bo =
1881 error->active_bo + error->active_bo_count;
1882 }
1883
1884 if (error->active_bo)
1885 error->active_bo_count =
1886 capture_active_bo(error->active_bo,
1887 error->active_bo_count,
1888 &dev_priv->mm.active_list);
1889
1890 if (error->pinned_bo)
1891 error->pinned_bo_count =
1892 capture_pinned_bo(error->pinned_bo,
1893 error->pinned_bo_count,
1894 &dev_priv->mm.bound_list);
1895}
1896
8a905236
JB		 1897/**
1898 * i915_capture_error_state - capture an error record for later analysis
1899 * @dev: drm device
1900 *
1901 * Should be called when an error is detected (either a hang or an error
1902 * interrupt) to capture error state from the time of the error. Fills
1903 * out a structure which becomes available in debugfs for user level tools
1904 * to pick up.
1905 */
63eeaf38
JB		 1906static void i915_capture_error_state(struct drm_device *dev)
1907{
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 struct drm_i915_error_state *error;
1910 unsigned long flags;
26b7c224 1911 int pipe;
63eeaf38 1912
99584db3
DV		 1913 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1914 error = dev_priv->gpu_error.first_error;
1915 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1916 if (error)
1917 return;
63eeaf38 1918
9db4a9c7 1919 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1920 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1921 if (!error) {
9df30794
CW		 1922 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1923 return;
63eeaf38
JB		 1924 }
1925
5d83d294 1926 DRM_INFO("capturing error event; look for more information in "
ef86ddce 1927 "/sys/class/drm/card%d/error\n", dev->primary->index);
2fa772f3 1928
742cbee8 1929 kref_init(&error->ref);
63eeaf38
JB		 1930 error->eir = I915_READ(EIR);
1931 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1932 if (HAS_HW_CONTEXTS(dev))
1933 error->ccid = I915_READ(CCID);
be998e2e
BW		 1934
1935 if (HAS_PCH_SPLIT(dev))
1936 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1937 else if (IS_VALLEYVIEW(dev))
1938 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1939 else if (IS_GEN2(dev))
1940 error->ier = I915_READ16(IER);
1941 else
1942 error->ier = I915_READ(IER);
1943
0f3b6849
CW		 1944 if (INTEL_INFO(dev)->gen >= 6)
1945 error->derrmr = I915_READ(DERRMR);
1946
1947 if (IS_VALLEYVIEW(dev))
1948 error->forcewake = I915_READ(FORCEWAKE_VLV);
1949 else if (INTEL_INFO(dev)->gen >= 7)
1950 error->forcewake = I915_READ(FORCEWAKE_MT);
1951 else if (INTEL_INFO(dev)->gen == 6)
1952 error->forcewake = I915_READ(FORCEWAKE);
1953
4f3308b9
PZ		 1954 if (!HAS_PCH_SPLIT(dev))
1955 for_each_pipe(pipe)
1956 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1957
33f3f518 1958 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1959 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1960 error->done_reg = I915_READ(DONE_REG);
1961 }
d27b1e0e 1962
71e172e8
BW		 1963 if (INTEL_INFO(dev)->gen == 7)
1964 error->err_int = I915_READ(GEN7_ERR_INT);
1965
050ee91f
BW		 1966 i915_get_extra_instdone(dev, error->extra_instdone);
1967
26b7c224 1968 i915_gem_capture_buffers(dev_priv, error);
748ebc60 1969 i915_gem_record_fences(dev, error);
52d39a21 1970 i915_gem_record_rings(dev, error);
9df30794 1971
9df30794
CW		 1972 do_gettimeofday(&error->time);
1973
6ef3d427 1974 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1975 error->display = intel_display_capture_error_state(dev);
6ef3d427 1976
99584db3
DV		 1977 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1978 if (dev_priv->gpu_error.first_error == NULL) {
1979 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1980 error = NULL;
1981 }
99584db3 1982 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1983
1984 if (error)
742cbee8 1985 i915_error_state_free(&error->ref);
9df30794
CW		 1986}
1987
1988void i915_destroy_error_state(struct drm_device *dev)
1989{
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct drm_i915_error_state *error;
6dc0e816 1992 unsigned long flags;
9df30794 1993
99584db3
DV		 1994 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1995 error = dev_priv->gpu_error.first_error;
1996 dev_priv->gpu_error.first_error = NULL;
1997 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1998
1999 if (error)
742cbee8 2000 kref_put(&error->ref, i915_error_state_free);
63eeaf38 2001}
3bd3c932
CW		 2002#else
2003#define i915_capture_error_state(x)
2004#endif
63eeaf38 2005
35aed2e6 2006static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2007{
2008 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2009 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2010 u32 eir = I915_READ(EIR);
050ee91f 2011 int pipe, i;
8a905236 2012
35aed2e6
CW		 2013 if (!eir)
2014 return;
8a905236 2015
a70491cc 2016 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2017
bd9854f9
BW		 2018 i915_get_extra_instdone(dev, instdone);
2019
8a905236
JB		 2020 if (IS_G4X(dev)) {
2021 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2022 u32 ipeir = I915_READ(IPEIR_I965);
2023
a70491cc
JP		 2024 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2025 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2026 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2027 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2028 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2029 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2030 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2031 POSTING_READ(IPEIR_I965);
8a905236
JB		 2032 }
2033 if (eir & GM45_ERROR_PAGE_TABLE) {
2034 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2035 pr_err("page table error\n");
2036 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2037 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2038 POSTING_READ(PGTBL_ER);
8a905236
JB		 2039 }
2040 }
2041
a6c45cf0 2042 if (!IS_GEN2(dev)) {
8a905236
JB		 2043 if (eir & I915_ERROR_PAGE_TABLE) {
2044 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2045 pr_err("page table error\n");
2046 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2047 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2048 POSTING_READ(PGTBL_ER);
8a905236
JB		 2049 }
2050 }
2051
2052 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2053 pr_err("memory refresh error:\n");
9db4a9c7 2054 for_each_pipe(pipe)
a70491cc 2055 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2056 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2057 /* pipestat has already been acked */
2058 }
2059 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2060 pr_err("instruction error\n");
2061 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2062 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2063 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2064 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2065 u32 ipeir = I915_READ(IPEIR);
2066
a70491cc
JP		 2067 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2068 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2069 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2070 I915_WRITE(IPEIR, ipeir);
3143a2bf 2071 POSTING_READ(IPEIR);
8a905236
JB		 2072 } else {
2073 u32 ipeir = I915_READ(IPEIR_I965);
2074
a70491cc
JP		 2075 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2076 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2077 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2078 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2079 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2080 POSTING_READ(IPEIR_I965);
8a905236
JB		 2081 }
2082 }
2083
2084 I915_WRITE(EIR, eir);
3143a2bf 2085 POSTING_READ(EIR);
8a905236
JB		 2086 eir = I915_READ(EIR);
2087 if (eir) {
2088 /*
2089 * some errors might have become stuck,
2090 * mask them.
2091 */
2092 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2093 I915_WRITE(EMR, I915_READ(EMR) | eir);
2094 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2095 }
35aed2e6
CW		 2096}
2097
2098/**
2099 * i915_handle_error - handle an error interrupt
2100 * @dev: drm device
2101 *
2102 * Do some basic checking of regsiter state at error interrupt time and
2103 * dump it to the syslog. Also call i915_capture_error_state() to make
2104 * sure we get a record and make it available in debugfs. Fire a uevent
2105 * so userspace knows something bad happened (should trigger collection
2106 * of a ring dump etc.).
2107 */
527f9e90 2108void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2109{
2110 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2111 struct intel_ring_buffer *ring;
2112 int i;
35aed2e6
CW		 2113
2114 i915_capture_error_state(dev);
2115 i915_report_and_clear_eir(dev);
8a905236 2116
ba1234d1 2117 if (wedged) {
f69061be
DV		 2118 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2119 &dev_priv->gpu_error.reset_counter);
ba1234d1 2120
11ed50ec 2121 /*
1f83fee0
DV		 2122 * Wakeup waiting processes so that the reset work item
2123 * doesn't deadlock trying to grab various locks.
11ed50ec 2124 */
b4519513
CW		 2125 for_each_ring(ring, dev_priv, i)
2126 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2127 }
2128
99584db3 2129 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2130}
2131
21ad8330 2132static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2133{
2134 drm_i915_private_t *dev_priv = dev->dev_private;
2135 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2137 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2138 struct intel_unpin_work *work;
2139 unsigned long flags;
2140 bool stall_detected;
2141
2142 /* Ignore early vblank irqs */
2143 if (intel_crtc == NULL)
2144 return;
2145
2146 spin_lock_irqsave(&dev->event_lock, flags);
2147 work = intel_crtc->unpin_work;
2148
e7d841ca
CW		 2149 if (work == NULL ||
2150 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2151 !work->enable_stall_check) {
4e5359cd
SF		 2152 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2153 spin_unlock_irqrestore(&dev->event_lock, flags);
2154 return;
2155 }
2156
2157 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2158 obj = work->pending_flip_obj;
a6c45cf0 2159 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2160 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2161 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2162 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2163 } else {
9db4a9c7 2164 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2165 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2166 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2167 crtc->x * crtc->fb->bits_per_pixel/8);
2168 }
2169
2170 spin_unlock_irqrestore(&dev->event_lock, flags);
2171
2172 if (stall_detected) {
2173 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2174 intel_prepare_page_flip(dev, intel_crtc->plane);
2175 }
2176}
2177
42f52ef8
KP		 2178/* Called from drm generic code, passed 'crtc' which
2179 * we use as a pipe index
2180 */
f71d4af4 2181static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2182{
2183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2184 unsigned long irqflags;
71e0ffa5 2185
5eddb70b 2186 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2187 return -EINVAL;
0a3e67a4 2188
1ec14ad3 2189 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2190 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2191 i915_enable_pipestat(dev_priv, pipe,
2192 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2193 else
7c463586
KP		 2194 i915_enable_pipestat(dev_priv, pipe,
2195 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2196
2197 /* maintain vblank delivery even in deep C-states */
2198 if (dev_priv->info->gen == 3)
6b26c86d 2199 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2200 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2201
0a3e67a4
JB		 2202 return 0;
2203}
2204
f71d4af4 2205static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2206{
2207 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2208 unsigned long irqflags;
2209
2210 if (!i915_pipe_enabled(dev, pipe))
2211 return -EINVAL;
2212
2213 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2214 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2215 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2216 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2217
2218 return 0;
2219}
2220
f71d4af4 2221static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2222{
2223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2224 unsigned long irqflags;
2225
2226 if (!i915_pipe_enabled(dev, pipe))
2227 return -EINVAL;
2228
2229 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2230 ironlake_enable_display_irq(dev_priv,
2231 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2232 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2233
2234 return 0;
2235}
2236
7e231dbe
JB		 2237static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2238{
2239 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2240 unsigned long irqflags;
31acc7f5 2241 u32 imr;
7e231dbe
JB		 2242
2243 if (!i915_pipe_enabled(dev, pipe))
2244 return -EINVAL;
2245
2246 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2247 imr = I915_READ(VLV_IMR);
31acc7f5 2248 if (pipe == 0)
7e231dbe 2249 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2250 else
7e231dbe 2251 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2252 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2253 i915_enable_pipestat(dev_priv, pipe,
2254 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2255 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2256
2257 return 0;
2258}
2259
42f52ef8
KP		 2260/* Called from drm generic code, passed 'crtc' which
2261 * we use as a pipe index
2262 */
f71d4af4 2263static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2264{
2265 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2266 unsigned long irqflags;
0a3e67a4 2267
1ec14ad3 2268 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2269 if (dev_priv->info->gen == 3)
6b26c86d 2270 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2271
f796cf8f
JB		 2272 i915_disable_pipestat(dev_priv, pipe,
2273 PIPE_VBLANK_INTERRUPT_ENABLE |
2274 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2275 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2276}
2277
f71d4af4 2278static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2279{
2280 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2281 unsigned long irqflags;
2282
2283 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2284 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2285 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2286 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2287}
2288
f71d4af4 2289static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2290{
2291 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2292 unsigned long irqflags;
2293
2294 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2295 ironlake_disable_display_irq(dev_priv,
2296 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2297 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2298}
2299
7e231dbe
JB		 2300static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2301{
2302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2303 unsigned long irqflags;
31acc7f5 2304 u32 imr;
7e231dbe
JB		 2305
2306 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2307 i915_disable_pipestat(dev_priv, pipe,
2308 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2309 imr = I915_READ(VLV_IMR);
31acc7f5 2310 if (pipe == 0)
7e231dbe 2311 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2312 else
7e231dbe 2313 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2314 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2315 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2316}
2317
893eead0
CW		 2318static u32
2319ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2320{
893eead0
CW		 2321 return list_entry(ring->request_list.prev,
2322 struct drm_i915_gem_request, list)->seqno;
2323}
2324
9107e9d2
CW		 2325static bool
2326ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2327{
2328 return (list_empty(&ring->request_list) ||
2329 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2330}
2331
6274f212
CW		 2332static struct intel_ring_buffer *
2333semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2334{
2335 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2336 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2337
2338 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2339 if ((ipehr & ~(0x3 << 16)) !=
2340 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2341 return NULL;
a24a11e6
CW		 2342
2343 /* ACTHD is likely pointing to the dword after the actual command,
2344 * so scan backwards until we find the MBOX.
2345 */
6274f212 2346 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2347 acthd_min = max((int)acthd - 3 * 4, 0);
2348 do {
2349 cmd = ioread32(ring->virtual_start + acthd);
2350 if (cmd == ipehr)
2351 break;
2352
2353 acthd -= 4;
2354 if (acthd < acthd_min)
6274f212 2355 return NULL;
a24a11e6
CW		 2356 } while (1);
2357
6274f212
CW		 2358 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2359 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2360}
2361
6274f212
CW		 2362static int semaphore_passed(struct intel_ring_buffer *ring)
2363{
2364 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2365 struct intel_ring_buffer *signaller;
2366 u32 seqno, ctl;
2367
2368 ring->hangcheck.deadlock = true;
2369
2370 signaller = semaphore_waits_for(ring, &seqno);
2371 if (signaller == NULL || signaller->hangcheck.deadlock)
2372 return -1;
2373
2374 /* cursory check for an unkickable deadlock */
2375 ctl = I915_READ_CTL(signaller);
2376 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2377 return -1;
2378
2379 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2380}
2381
2382static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2383{
2384 struct intel_ring_buffer *ring;
2385 int i;
2386
2387 for_each_ring(ring, dev_priv, i)
2388 ring->hangcheck.deadlock = false;
2389}
2390
ad8beaea
MK		 2391static enum intel_ring_hangcheck_action
2392ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2393{
2394 struct drm_device *dev = ring->dev;
2395 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2396 u32 tmp;
2397
6274f212
CW		 2398 if (ring->hangcheck.acthd != acthd)
2399 return active;
2400
9107e9d2 2401 if (IS_GEN2(dev))
6274f212 2402 return hung;
9107e9d2
CW		 2403
2404 /* Is the chip hanging on a WAIT_FOR_EVENT?
2405 * If so we can simply poke the RB_WAIT bit
2406 * and break the hang. This should work on
2407 * all but the second generation chipsets.
2408 */
2409 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2410 if (tmp & RING_WAIT) {
2411 DRM_ERROR("Kicking stuck wait on %s\n",
2412 ring->name);
2413 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2414 return kick;
2415 }
2416
2417 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2418 switch (semaphore_passed(ring)) {
2419 default:
2420 return hung;
2421 case 1:
2422 DRM_ERROR("Kicking stuck semaphore on %s\n",
2423 ring->name);
2424 I915_WRITE_CTL(ring, tmp);
2425 return kick;
2426 case 0:
2427 return wait;
2428 }
9107e9d2 2429 }
ed5cbb03 2430
6274f212 2431 return hung;
ed5cbb03
MK		 2432}
2433
f65d9421
BG		 2434/**
2435 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2436 * batchbuffers in a long time. We keep track per ring seqno progress and
2437 * if there are no progress, hangcheck score for that ring is increased.
2438 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2439 * we kick the ring. If we see no progress on three subsequent calls
2440 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2441 */
2442void i915_hangcheck_elapsed(unsigned long data)
2443{
2444 struct drm_device *dev = (struct drm_device *)data;
2445 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2446 struct intel_ring_buffer *ring;
b4519513 2447 int i;
05407ff8 2448 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2449 bool stuck[I915_NUM_RINGS] = { 0 };
2450#define BUSY 1
2451#define KICK 5
2452#define HUNG 20
2453#define FIRE 30
893eead0 2454
3e0dc6b0
BW		 2455 if (!i915_enable_hangcheck)
2456 return;
2457
b4519513 2458 for_each_ring(ring, dev_priv, i) {
05407ff8 2459 u32 seqno, acthd;
9107e9d2 2460 bool busy = true;
05407ff8 2461
6274f212
CW		 2462 semaphore_clear_deadlocks(dev_priv);
2463
05407ff8
MK		 2464 seqno = ring->get_seqno(ring, false);
2465 acthd = intel_ring_get_active_head(ring);
b4519513 2466
9107e9d2
CW		 2467 if (ring->hangcheck.seqno == seqno) {
2468 if (ring_idle(ring, seqno)) {
2469 if (waitqueue_active(&ring->irq_queue)) {
2470 /* Issue a wake-up to catch stuck h/w. */
2471 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2472 ring->name);
2473 wake_up_all(&ring->irq_queue);
2474 ring->hangcheck.score += HUNG;
2475 } else
2476 busy = false;
05407ff8 2477 } else {
9107e9d2
CW		 2478 int score;
2479
6274f212
CW		 2480 /* We always increment the hangcheck score
2481 * if the ring is busy and still processing
2482 * the same request, so that no single request
2483 * can run indefinitely (such as a chain of
2484 * batches). The only time we do not increment
2485 * the hangcheck score on this ring, if this
2486 * ring is in a legitimate wait for another
2487 * ring. In that case the waiting ring is a
2488 * victim and we want to be sure we catch the
2489 * right culprit. Then every time we do kick
2490 * the ring, add a small increment to the
2491 * score so that we can catch a batch that is
2492 * being repeatedly kicked and so responsible
2493 * for stalling the machine.
2494 */
ad8beaea
MK		 2495 ring->hangcheck.action = ring_stuck(ring,
2496 acthd);
2497
2498 switch (ring->hangcheck.action) {
6274f212
CW		 2499 case wait:
2500 score = 0;
2501 break;
2502 case active:
9107e9d2 2503 score = BUSY;
6274f212
CW		 2504 break;
2505 case kick:
2506 score = KICK;
2507 break;
2508 case hung:
2509 score = HUNG;
2510 stuck[i] = true;
2511 break;
2512 }
9107e9d2 2513 ring->hangcheck.score += score;
05407ff8 2514 }
9107e9d2
CW		 2515 } else {
2516 /* Gradually reduce the count so that we catch DoS
2517 * attempts across multiple batches.
2518 */
2519 if (ring->hangcheck.score > 0)
2520 ring->hangcheck.score--;
d1e61e7f
CW		 2521 }
2522
05407ff8
MK		 2523 ring->hangcheck.seqno = seqno;
2524 ring->hangcheck.acthd = acthd;
9107e9d2 2525 busy_count += busy;
893eead0 2526 }
b9201c14 2527
92cab734 2528 for_each_ring(ring, dev_priv, i) {
9107e9d2 2529 if (ring->hangcheck.score > FIRE) {
acd78c11 2530 DRM_ERROR("%s on %s\n",
05407ff8 2531 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2532 ring->name);
2533 rings_hung++;
92cab734
MK		 2534 }
2535 }
2536
05407ff8
MK		 2537 if (rings_hung)
2538 return i915_handle_error(dev, true);
f65d9421 2539
05407ff8
MK		 2540 if (busy_count)
2541 /* Reset timer case chip hangs without another request
2542 * being added */
2543 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2544 round_jiffies_up(jiffies +
2545 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2546}
2547
91738a95
PZ		 2548static void ibx_irq_preinstall(struct drm_device *dev)
2549{
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551
2552 if (HAS_PCH_NOP(dev))
2553 return;
2554
2555 /* south display irq */
2556 I915_WRITE(SDEIMR, 0xffffffff);
2557 /*
2558 * SDEIER is also touched by the interrupt handler to work around missed
2559 * PCH interrupts. Hence we can't update it after the interrupt handler
2560 * is enabled - instead we unconditionally enable all PCH interrupt
2561 * sources here, but then only unmask them as needed with SDEIMR.
2562 */
2563 I915_WRITE(SDEIER, 0xffffffff);
2564 POSTING_READ(SDEIER);
2565}
2566
1da177e4
LT		 2567/* drm_dma.h hooks
2568*/
f71d4af4 2569static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2570{
2571 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2572
4697995b
JB		 2573 atomic_set(&dev_priv->irq_received, 0);
2574
036a4a7d 2575 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2576
036a4a7d
ZW		 2577 /* XXX hotplug from PCH */
2578
2579 I915_WRITE(DEIMR, 0xffffffff);
2580 I915_WRITE(DEIER, 0x0);
3143a2bf 2581 POSTING_READ(DEIER);
036a4a7d
ZW		 2582
2583 /* and GT */
2584 I915_WRITE(GTIMR, 0xffffffff);
2585 I915_WRITE(GTIER, 0x0);
3143a2bf 2586 POSTING_READ(GTIER);
c650156a 2587
91738a95 2588 ibx_irq_preinstall(dev);
7d99163d
BW		 2589}
2590
2591static void ivybridge_irq_preinstall(struct drm_device *dev)
2592{
2593 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2594
2595 atomic_set(&dev_priv->irq_received, 0);
2596
2597 I915_WRITE(HWSTAM, 0xeffe);
2598
2599 /* XXX hotplug from PCH */
2600
2601 I915_WRITE(DEIMR, 0xffffffff);
2602 I915_WRITE(DEIER, 0x0);
2603 POSTING_READ(DEIER);
2604
2605 /* and GT */
2606 I915_WRITE(GTIMR, 0xffffffff);
2607 I915_WRITE(GTIER, 0x0);
2608 POSTING_READ(GTIER);
2609
eda63ffb
BW		 2610 /* Power management */
2611 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2612 I915_WRITE(GEN6_PMIER, 0x0);
2613 POSTING_READ(GEN6_PMIER);
2614
91738a95 2615 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2616}
2617
7e231dbe
JB		 2618static void valleyview_irq_preinstall(struct drm_device *dev)
2619{
2620 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2621 int pipe;
2622
2623 atomic_set(&dev_priv->irq_received, 0);
2624
7e231dbe
JB		 2625 /* VLV magic */
2626 I915_WRITE(VLV_IMR, 0);
2627 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2628 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2629 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2630
7e231dbe
JB		 2631 /* and GT */
2632 I915_WRITE(GTIIR, I915_READ(GTIIR));
2633 I915_WRITE(GTIIR, I915_READ(GTIIR));
2634 I915_WRITE(GTIMR, 0xffffffff);
2635 I915_WRITE(GTIER, 0x0);
2636 POSTING_READ(GTIER);
2637
2638 I915_WRITE(DPINVGTT, 0xff);
2639
2640 I915_WRITE(PORT_HOTPLUG_EN, 0);
2641 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2642 for_each_pipe(pipe)
2643 I915_WRITE(PIPESTAT(pipe), 0xffff);
2644 I915_WRITE(VLV_IIR, 0xffffffff);
2645 I915_WRITE(VLV_IMR, 0xffffffff);
2646 I915_WRITE(VLV_IER, 0x0);
2647 POSTING_READ(VLV_IER);
2648}
2649
82a28bcf 2650static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2651{
2652 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2653 struct drm_mode_config *mode_config = &dev->mode_config;
2654 struct intel_encoder *intel_encoder;
2655 u32 mask = ~I915_READ(SDEIMR);
2656 u32 hotplug;
2657
2658 if (HAS_PCH_IBX(dev)) {
995e6b3d 2659 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2660 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2661 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2662 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2663 } else {
995e6b3d 2664 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2665 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2666 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2667 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2668 }
7fe0b973 2669
82a28bcf
DV		 2670 I915_WRITE(SDEIMR, ~mask);
2671
2672 /*
2673 * Enable digital hotplug on the PCH, and configure the DP short pulse
2674 * duration to 2ms (which is the minimum in the Display Port spec)
2675 *
2676 * This register is the same on all known PCH chips.
2677 */
7fe0b973
KP		 2678 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2679 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2680 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2681 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2682 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2683 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2684}
2685
d46da437
PZ		 2686static void ibx_irq_postinstall(struct drm_device *dev)
2687{
2688 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2689 u32 mask;
e5868a31 2690
692a04cf
DV		 2691 if (HAS_PCH_NOP(dev))
2692 return;
2693
8664281b
PZ		 2694 if (HAS_PCH_IBX(dev)) {
2695 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2696 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2697 } else {
2698 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2699
2700 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2701 }
ab5c608b 2702
d46da437
PZ		 2703 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2704 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2705}
2706
f71d4af4 2707static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2708{
4bc9d430
DV		 2709 unsigned long irqflags;
2710
036a4a7d
ZW		 2711 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2712 /* enable kind of interrupts always enabled */
013d5aa2 2713 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2714 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2715 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2716 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2717 u32 gt_irqs;
036a4a7d 2718
1ec14ad3 2719 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2720
2721 /* should always can generate irq */
2722 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2723 I915_WRITE(DEIMR, dev_priv->irq_mask);
6005ce42
DV		 2724 I915_WRITE(DEIER, display_mask |
2725 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
3143a2bf 2726 POSTING_READ(DEIER);
036a4a7d 2727
1ec14ad3 2728 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2729
2730 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2731 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2732
cc609d5d
BW		 2733 gt_irqs = GT_RENDER_USER_INTERRUPT;
2734
1ec14ad3 2735 if (IS_GEN6(dev))
cc609d5d 2736 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2737 else
cc609d5d
BW		 2738 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2739 ILK_BSD_USER_INTERRUPT;
2740
2741 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2742 POSTING_READ(GTIER);
036a4a7d 2743
d46da437 2744 ibx_irq_postinstall(dev);
7fe0b973 2745
f97108d1 2746 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2747 /* Enable PCU event interrupts
2748 *
2749 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2750 * setup is guaranteed to run in single-threaded context. But we
2751 * need it to make the assert_spin_locked happy. */
2752 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2753 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2754 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2755 }
2756
036a4a7d
ZW		 2757 return 0;
2758}
2759
f71d4af4 2760static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2761{
2762 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2763 /* enable kind of interrupts always enabled */
b615b57a
CW		 2764 u32 display_mask =
2765 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2766 DE_PLANEC_FLIP_DONE_IVB |
2767 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2768 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2769 DE_AUX_CHANNEL_A_IVB |
2770 DE_ERR_INT_IVB;
12638c57 2771 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2772 u32 gt_irqs;
b1f14ad0 2773
b1f14ad0
JB		 2774 dev_priv->irq_mask = ~display_mask;
2775
2776 /* should always can generate irq */
8664281b 2777 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2778 I915_WRITE(DEIIR, I915_READ(DEIIR));
2779 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2780 I915_WRITE(DEIER,
2781 display_mask |
2782 DE_PIPEC_VBLANK_IVB |
2783 DE_PIPEB_VBLANK_IVB |
2784 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2785 POSTING_READ(DEIER);
2786
cc609d5d 2787 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2788
2789 I915_WRITE(GTIIR, I915_READ(GTIIR));
2790 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2791
cc609d5d
BW		 2792 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2793 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2794 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2795 POSTING_READ(GTIER);
2796
12638c57
BW		 2797 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2798 if (HAS_VEBOX(dev))
2799 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2800 PM_VEBOX_CS_ERROR_INTERRUPT;
2801
2802 /* Our enable/disable rps functions may touch these registers so
2803 * make sure to set a known state for only the non-RPS bits.
2804 * The RMW is extra paranoia since this should be called after being set
2805 * to a known state in preinstall.
2806 * */
2807 I915_WRITE(GEN6_PMIMR,
2808 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2809 I915_WRITE(GEN6_PMIER,
2810 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2811 POSTING_READ(GEN6_PMIER);
eda63ffb 2812
d46da437 2813 ibx_irq_postinstall(dev);
7fe0b973 2814
b1f14ad0
JB		 2815 return 0;
2816}
2817
7e231dbe
JB		 2818static int valleyview_irq_postinstall(struct drm_device *dev)
2819{
2820 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2821 u32 gt_irqs;
7e231dbe 2822 u32 enable_mask;
31acc7f5 2823 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2824 unsigned long irqflags;
7e231dbe
JB		 2825
2826 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2827 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2828 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2829 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2830 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2831
31acc7f5
JB		 2832 /*
2833 *Leave vblank interrupts masked initially. enable/disable will
2834 * toggle them based on usage.
2835 */
2836 dev_priv->irq_mask = (~enable_mask) |
2837 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2838 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2839
20afbda2
DV		 2840 I915_WRITE(PORT_HOTPLUG_EN, 0);
2841 POSTING_READ(PORT_HOTPLUG_EN);
2842
7e231dbe
JB		 2843 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2844 I915_WRITE(VLV_IER, enable_mask);
2845 I915_WRITE(VLV_IIR, 0xffffffff);
2846 I915_WRITE(PIPESTAT(0), 0xffff);
2847 I915_WRITE(PIPESTAT(1), 0xffff);
2848 POSTING_READ(VLV_IER);
2849
b79480ba
DV		 2850 /* Interrupt setup is already guaranteed to be single-threaded, this is
2851 * just to make the assert_spin_locked check happy. */
2852 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2853 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2854 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2855 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2856 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2857
7e231dbe
JB		 2858 I915_WRITE(VLV_IIR, 0xffffffff);
2859 I915_WRITE(VLV_IIR, 0xffffffff);
2860
7e231dbe 2861 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2862 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2863
cc609d5d
BW		 2864 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2865 GT_BLT_USER_INTERRUPT;
2866 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2867 POSTING_READ(GTIER);
2868
2869 /* ack & enable invalid PTE error interrupts */
2870#if 0 /* FIXME: add support to irq handler for checking these bits */
2871 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2872 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2873#endif
2874
2875 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2876
2877 return 0;
2878}
2879
7e231dbe
JB		 2880static void valleyview_irq_uninstall(struct drm_device *dev)
2881{
2882 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2883 int pipe;
2884
2885 if (!dev_priv)
2886 return;
2887
ac4c16c5
EE		 2888 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2889
7e231dbe
JB		 2890 for_each_pipe(pipe)
2891 I915_WRITE(PIPESTAT(pipe), 0xffff);
2892
2893 I915_WRITE(HWSTAM, 0xffffffff);
2894 I915_WRITE(PORT_HOTPLUG_EN, 0);
2895 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2896 for_each_pipe(pipe)
2897 I915_WRITE(PIPESTAT(pipe), 0xffff);
2898 I915_WRITE(VLV_IIR, 0xffffffff);
2899 I915_WRITE(VLV_IMR, 0xffffffff);
2900 I915_WRITE(VLV_IER, 0x0);
2901 POSTING_READ(VLV_IER);
2902}
2903
f71d4af4 2904static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2905{
2906 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2907
2908 if (!dev_priv)
2909 return;
2910
ac4c16c5
EE		 2911 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2912
036a4a7d
ZW		 2913 I915_WRITE(HWSTAM, 0xffffffff);
2914
2915 I915_WRITE(DEIMR, 0xffffffff);
2916 I915_WRITE(DEIER, 0x0);
2917 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2918 if (IS_GEN7(dev))
2919 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2920
2921 I915_WRITE(GTIMR, 0xffffffff);
2922 I915_WRITE(GTIER, 0x0);
2923 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2924
ab5c608b
BW		 2925 if (HAS_PCH_NOP(dev))
2926 return;
2927
192aac1f
KP		 2928 I915_WRITE(SDEIMR, 0xffffffff);
2929 I915_WRITE(SDEIER, 0x0);
2930 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2931 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2932 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2933}
2934
a266c7d5 2935static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2936{
2937 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2938 int pipe;
91e3738e 2939
a266c7d5 2940 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2941
9db4a9c7
JB		 2942 for_each_pipe(pipe)
2943 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2944 I915_WRITE16(IMR, 0xffff);
2945 I915_WRITE16(IER, 0x0);
2946 POSTING_READ16(IER);
c2798b19
CW		 2947}
2948
2949static int i8xx_irq_postinstall(struct drm_device *dev)
2950{
2951 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2952
c2798b19
CW		 2953 I915_WRITE16(EMR,
2954 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2955
2956 /* Unmask the interrupts that we always want on. */
2957 dev_priv->irq_mask =
2958 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2959 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2960 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2961 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2962 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2963 I915_WRITE16(IMR, dev_priv->irq_mask);
2964
2965 I915_WRITE16(IER,
2966 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2967 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2968 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2969 I915_USER_INTERRUPT);
2970 POSTING_READ16(IER);
2971
2972 return 0;
2973}
2974
90a72f87
VS		 2975/*
2976 * Returns true when a page flip has completed.
2977 */
2978static bool i8xx_handle_vblank(struct drm_device *dev,
2979 int pipe, u16 iir)
2980{
2981 drm_i915_private_t *dev_priv = dev->dev_private;
2982 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2983
2984 if (!drm_handle_vblank(dev, pipe))
2985 return false;
2986
2987 if ((iir & flip_pending) == 0)
2988 return false;
2989
2990 intel_prepare_page_flip(dev, pipe);
2991
2992 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2993 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2994 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2995 * the flip is completed (no longer pending). Since this doesn't raise
2996 * an interrupt per se, we watch for the change at vblank.
2997 */
2998 if (I915_READ16(ISR) & flip_pending)
2999 return false;
3000
3001 intel_finish_page_flip(dev, pipe);
3002
3003 return true;
3004}
3005
ff1f525e 3006static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3007{
3008 struct drm_device *dev = (struct drm_device *) arg;
3009 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3010 u16 iir, new_iir;
3011 u32 pipe_stats[2];
3012 unsigned long irqflags;
3013 int irq_received;
3014 int pipe;
3015 u16 flip_mask =
3016 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3017 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3018
3019 atomic_inc(&dev_priv->irq_received);
3020
3021 iir = I915_READ16(IIR);
3022 if (iir == 0)
3023 return IRQ_NONE;
3024
3025 while (iir & ~flip_mask) {
3026 /* Can't rely on pipestat interrupt bit in iir as it might
3027 * have been cleared after the pipestat interrupt was received.
3028 * It doesn't set the bit in iir again, but it still produces
3029 * interrupts (for non-MSI).
3030 */
3031 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3032 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3033 i915_handle_error(dev, false);
3034
3035 for_each_pipe(pipe) {
3036 int reg = PIPESTAT(pipe);
3037 pipe_stats[pipe] = I915_READ(reg);
3038
3039 /*
3040 * Clear the PIPE*STAT regs before the IIR
3041 */
3042 if (pipe_stats[pipe] & 0x8000ffff) {
3043 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3044 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3045 pipe_name(pipe));
3046 I915_WRITE(reg, pipe_stats[pipe]);
3047 irq_received = 1;
3048 }
3049 }
3050 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3051
3052 I915_WRITE16(IIR, iir & ~flip_mask);
3053 new_iir = I915_READ16(IIR); /* Flush posted writes */
3054
d05c617e 3055 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3056
3057 if (iir & I915_USER_INTERRUPT)
3058 notify_ring(dev, &dev_priv->ring[RCS]);
3059
3060 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3061 i8xx_handle_vblank(dev, 0, iir))
3062 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3063
3064 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3065 i8xx_handle_vblank(dev, 1, iir))
3066 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3067
3068 iir = new_iir;
3069 }
3070
3071 return IRQ_HANDLED;
3072}
3073
3074static void i8xx_irq_uninstall(struct drm_device * dev)
3075{
3076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3077 int pipe;
3078
c2798b19
CW		 3079 for_each_pipe(pipe) {
3080 /* Clear enable bits; then clear status bits */
3081 I915_WRITE(PIPESTAT(pipe), 0);
3082 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3083 }
3084 I915_WRITE16(IMR, 0xffff);
3085 I915_WRITE16(IER, 0x0);
3086 I915_WRITE16(IIR, I915_READ16(IIR));
3087}
3088
a266c7d5
CW		 3089static void i915_irq_preinstall(struct drm_device * dev)
3090{
3091 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3092 int pipe;
3093
3094 atomic_set(&dev_priv->irq_received, 0);
3095
3096 if (I915_HAS_HOTPLUG(dev)) {
3097 I915_WRITE(PORT_HOTPLUG_EN, 0);
3098 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3099 }
3100
00d98ebd 3101 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3102 for_each_pipe(pipe)
3103 I915_WRITE(PIPESTAT(pipe), 0);
3104 I915_WRITE(IMR, 0xffffffff);
3105 I915_WRITE(IER, 0x0);
3106 POSTING_READ(IER);
3107}
3108
3109static int i915_irq_postinstall(struct drm_device *dev)
3110{
3111 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3112 u32 enable_mask;
a266c7d5 3113
38bde180
CW		 3114 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3115
3116 /* Unmask the interrupts that we always want on. */
3117 dev_priv->irq_mask =
3118 ~(I915_ASLE_INTERRUPT |
3119 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3120 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3121 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3122 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3123 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3124
3125 enable_mask =
3126 I915_ASLE_INTERRUPT |
3127 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3128 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3129 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3130 I915_USER_INTERRUPT;
3131
a266c7d5 3132 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3133 I915_WRITE(PORT_HOTPLUG_EN, 0);
3134 POSTING_READ(PORT_HOTPLUG_EN);
3135
a266c7d5
CW		 3136 /* Enable in IER... */
3137 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3138 /* and unmask in IMR */
3139 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3140 }
3141
a266c7d5
CW		 3142 I915_WRITE(IMR, dev_priv->irq_mask);
3143 I915_WRITE(IER, enable_mask);
3144 POSTING_READ(IER);
3145
f49e38dd 3146 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3147
3148 return 0;
3149}
3150
90a72f87
VS		 3151/*
3152 * Returns true when a page flip has completed.
3153 */
3154static bool i915_handle_vblank(struct drm_device *dev,
3155 int plane, int pipe, u32 iir)
3156{
3157 drm_i915_private_t *dev_priv = dev->dev_private;
3158 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3159
3160 if (!drm_handle_vblank(dev, pipe))
3161 return false;
3162
3163 if ((iir & flip_pending) == 0)
3164 return false;
3165
3166 intel_prepare_page_flip(dev, plane);
3167
3168 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3169 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3170 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3171 * the flip is completed (no longer pending). Since this doesn't raise
3172 * an interrupt per se, we watch for the change at vblank.
3173 */
3174 if (I915_READ(ISR) & flip_pending)
3175 return false;
3176
3177 intel_finish_page_flip(dev, pipe);
3178
3179 return true;
3180}
3181
ff1f525e 3182static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3183{
3184 struct drm_device *dev = (struct drm_device *) arg;
3185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3186 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3187 unsigned long irqflags;
38bde180
CW		 3188 u32 flip_mask =
3189 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3190 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3191 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3192
3193 atomic_inc(&dev_priv->irq_received);
3194
3195 iir = I915_READ(IIR);
38bde180
CW		 3196 do {
3197 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3198 bool blc_event = false;
a266c7d5
CW		 3199
3200 /* Can't rely on pipestat interrupt bit in iir as it might
3201 * have been cleared after the pipestat interrupt was received.
3202 * It doesn't set the bit in iir again, but it still produces
3203 * interrupts (for non-MSI).
3204 */
3205 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3206 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3207 i915_handle_error(dev, false);
3208
3209 for_each_pipe(pipe) {
3210 int reg = PIPESTAT(pipe);
3211 pipe_stats[pipe] = I915_READ(reg);
3212
38bde180 3213 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3214 if (pipe_stats[pipe] & 0x8000ffff) {
3215 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3216 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3217 pipe_name(pipe));
3218 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3219 irq_received = true;
a266c7d5
CW		 3220 }
3221 }
3222 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3223
3224 if (!irq_received)
3225 break;
3226
a266c7d5
CW		 3227 /* Consume port. Then clear IIR or we'll miss events */
3228 if ((I915_HAS_HOTPLUG(dev)) &&
3229 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3230 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3231 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3232
3233 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3234 hotplug_status);
91d131d2
DV		 3235
3236 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3237
a266c7d5 3238 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3239 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3240 }
3241
38bde180 3242 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3243 new_iir = I915_READ(IIR); /* Flush posted writes */
3244
a266c7d5
CW		 3245 if (iir & I915_USER_INTERRUPT)
3246 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3247
a266c7d5 3248 for_each_pipe(pipe) {
38bde180
CW		 3249 int plane = pipe;
3250 if (IS_MOBILE(dev))
3251 plane = !plane;
90a72f87 3252
8291ee90 3253 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3254 i915_handle_vblank(dev, plane, pipe, iir))
3255 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3256
3257 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3258 blc_event = true;
3259 }
3260
a266c7d5
CW		 3261 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3262 intel_opregion_asle_intr(dev);
3263
3264 /* With MSI, interrupts are only generated when iir
3265 * transitions from zero to nonzero. If another bit got
3266 * set while we were handling the existing iir bits, then
3267 * we would never get another interrupt.
3268 *
3269 * This is fine on non-MSI as well, as if we hit this path
3270 * we avoid exiting the interrupt handler only to generate
3271 * another one.
3272 *
3273 * Note that for MSI this could cause a stray interrupt report
3274 * if an interrupt landed in the time between writing IIR and
3275 * the posting read. This should be rare enough to never
3276 * trigger the 99% of 100,000 interrupts test for disabling
3277 * stray interrupts.
3278 */
38bde180 3279 ret = IRQ_HANDLED;
a266c7d5 3280 iir = new_iir;
38bde180 3281 } while (iir & ~flip_mask);
a266c7d5 3282
d05c617e 3283 i915_update_dri1_breadcrumb(dev);
8291ee90 3284
a266c7d5
CW		 3285 return ret;
3286}
3287
3288static void i915_irq_uninstall(struct drm_device * dev)
3289{
3290 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3291 int pipe;
3292
ac4c16c5
EE		 3293 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3294
a266c7d5
CW		 3295 if (I915_HAS_HOTPLUG(dev)) {
3296 I915_WRITE(PORT_HOTPLUG_EN, 0);
3297 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3298 }
3299
00d98ebd 3300 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3301 for_each_pipe(pipe) {
3302 /* Clear enable bits; then clear status bits */
a266c7d5 3303 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3304 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3305 }
a266c7d5
CW		 3306 I915_WRITE(IMR, 0xffffffff);
3307 I915_WRITE(IER, 0x0);
3308
a266c7d5
CW		 3309 I915_WRITE(IIR, I915_READ(IIR));
3310}
3311
3312static void i965_irq_preinstall(struct drm_device * dev)
3313{
3314 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3315 int pipe;
3316
3317 atomic_set(&dev_priv->irq_received, 0);
3318
adca4730
CW		 3319 I915_WRITE(PORT_HOTPLUG_EN, 0);
3320 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3321
3322 I915_WRITE(HWSTAM, 0xeffe);
3323 for_each_pipe(pipe)
3324 I915_WRITE(PIPESTAT(pipe), 0);
3325 I915_WRITE(IMR, 0xffffffff);
3326 I915_WRITE(IER, 0x0);
3327 POSTING_READ(IER);
3328}
3329
3330static int i965_irq_postinstall(struct drm_device *dev)
3331{
3332 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3333 u32 enable_mask;
a266c7d5 3334 u32 error_mask;
b79480ba 3335 unsigned long irqflags;
a266c7d5 3336
a266c7d5 3337 /* Unmask the interrupts that we always want on. */
bbba0a97 3338 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3339 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3340 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3341 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3342 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3343 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3344 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3345
3346 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3347 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3348 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3349 enable_mask |= I915_USER_INTERRUPT;
3350
3351 if (IS_G4X(dev))
3352 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3353
b79480ba
DV		 3354 /* Interrupt setup is already guaranteed to be single-threaded, this is
3355 * just to make the assert_spin_locked check happy. */
3356 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3357 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3358 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3359
a266c7d5
CW		 3360 /*
3361 * Enable some error detection, note the instruction error mask
3362 * bit is reserved, so we leave it masked.
3363 */
3364 if (IS_G4X(dev)) {
3365 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3366 GM45_ERROR_MEM_PRIV |
3367 GM45_ERROR_CP_PRIV |
3368 I915_ERROR_MEMORY_REFRESH);
3369 } else {
3370 error_mask = ~(I915_ERROR_PAGE_TABLE |
3371 I915_ERROR_MEMORY_REFRESH);
3372 }
3373 I915_WRITE(EMR, error_mask);
3374
3375 I915_WRITE(IMR, dev_priv->irq_mask);
3376 I915_WRITE(IER, enable_mask);
3377 POSTING_READ(IER);
3378
20afbda2
DV		 3379 I915_WRITE(PORT_HOTPLUG_EN, 0);
3380 POSTING_READ(PORT_HOTPLUG_EN);
3381
f49e38dd 3382 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3383
3384 return 0;
3385}
3386
bac56d5b 3387static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3388{
3389 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3390 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3391 struct intel_encoder *intel_encoder;
20afbda2
DV		 3392 u32 hotplug_en;
3393
b5ea2d56
DV		 3394 assert_spin_locked(&dev_priv->irq_lock);
3395
bac56d5b
EE		 3396 if (I915_HAS_HOTPLUG(dev)) {
3397 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3398 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3399 /* Note HDMI and DP share hotplug bits */
e5868a31 3400 /* enable bits are the same for all generations */
cd569aed
EE		 3401 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3402 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3403 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3404 /* Programming the CRT detection parameters tends
3405 to generate a spurious hotplug event about three
3406 seconds later. So just do it once.
3407 */
3408 if (IS_G4X(dev))
3409 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3410 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3411 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3412
bac56d5b
EE		 3413 /* Ignore TV since it's buggy */
3414 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3415 }
a266c7d5
CW		 3416}
3417
ff1f525e 3418static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3419{
3420 struct drm_device *dev = (struct drm_device *) arg;
3421 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3422 u32 iir, new_iir;
3423 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3424 unsigned long irqflags;
3425 int irq_received;
3426 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3427 u32 flip_mask =
3428 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3429 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3430
3431 atomic_inc(&dev_priv->irq_received);
3432
3433 iir = I915_READ(IIR);
3434
a266c7d5 3435 for (;;) {
2c8ba29f
CW		 3436 bool blc_event = false;
3437
21ad8330 3438 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3439
3440 /* Can't rely on pipestat interrupt bit in iir as it might
3441 * have been cleared after the pipestat interrupt was received.
3442 * It doesn't set the bit in iir again, but it still produces
3443 * interrupts (for non-MSI).
3444 */
3445 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3446 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3447 i915_handle_error(dev, false);
3448
3449 for_each_pipe(pipe) {
3450 int reg = PIPESTAT(pipe);
3451 pipe_stats[pipe] = I915_READ(reg);
3452
3453 /*
3454 * Clear the PIPE*STAT regs before the IIR
3455 */
3456 if (pipe_stats[pipe] & 0x8000ffff) {
3457 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3458 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3459 pipe_name(pipe));
3460 I915_WRITE(reg, pipe_stats[pipe]);
3461 irq_received = 1;
3462 }
3463 }
3464 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3465
3466 if (!irq_received)
3467 break;
3468
3469 ret = IRQ_HANDLED;
3470
3471 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3472 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3473 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3474 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3475 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3476 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3477
3478 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3479 hotplug_status);
91d131d2
DV		 3480
3481 intel_hpd_irq_handler(dev, hotplug_trigger,
3482 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3483
a266c7d5
CW		 3484 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3485 I915_READ(PORT_HOTPLUG_STAT);
3486 }
3487
21ad8330 3488 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3489 new_iir = I915_READ(IIR); /* Flush posted writes */
3490
a266c7d5
CW		 3491 if (iir & I915_USER_INTERRUPT)
3492 notify_ring(dev, &dev_priv->ring[RCS]);
3493 if (iir & I915_BSD_USER_INTERRUPT)
3494 notify_ring(dev, &dev_priv->ring[VCS]);
3495
a266c7d5 3496 for_each_pipe(pipe) {
2c8ba29f 3497 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3498 i915_handle_vblank(dev, pipe, pipe, iir))
3499 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3500
3501 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3502 blc_event = true;
3503 }
3504
3505
3506 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3507 intel_opregion_asle_intr(dev);
3508
515ac2bb
DV		 3509 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3510 gmbus_irq_handler(dev);
3511
a266c7d5
CW		 3512 /* With MSI, interrupts are only generated when iir
3513 * transitions from zero to nonzero. If another bit got
3514 * set while we were handling the existing iir bits, then
3515 * we would never get another interrupt.
3516 *
3517 * This is fine on non-MSI as well, as if we hit this path
3518 * we avoid exiting the interrupt handler only to generate
3519 * another one.
3520 *
3521 * Note that for MSI this could cause a stray interrupt report
3522 * if an interrupt landed in the time between writing IIR and
3523 * the posting read. This should be rare enough to never
3524 * trigger the 99% of 100,000 interrupts test for disabling
3525 * stray interrupts.
3526 */
3527 iir = new_iir;
3528 }
3529
d05c617e 3530 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3531
a266c7d5
CW		 3532 return ret;
3533}
3534
3535static void i965_irq_uninstall(struct drm_device * dev)
3536{
3537 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3538 int pipe;
3539
3540 if (!dev_priv)
3541 return;
3542
ac4c16c5
EE		 3543 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3544
adca4730
CW		 3545 I915_WRITE(PORT_HOTPLUG_EN, 0);
3546 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3547
3548 I915_WRITE(HWSTAM, 0xffffffff);
3549 for_each_pipe(pipe)
3550 I915_WRITE(PIPESTAT(pipe), 0);
3551 I915_WRITE(IMR, 0xffffffff);
3552 I915_WRITE(IER, 0x0);
3553
3554 for_each_pipe(pipe)
3555 I915_WRITE(PIPESTAT(pipe),
3556 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3557 I915_WRITE(IIR, I915_READ(IIR));
3558}
3559
ac4c16c5
EE		 3560static void i915_reenable_hotplug_timer_func(unsigned long data)
3561{
3562 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3563 struct drm_device *dev = dev_priv->dev;
3564 struct drm_mode_config *mode_config = &dev->mode_config;
3565 unsigned long irqflags;
3566 int i;
3567
3568 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3569 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3570 struct drm_connector *connector;
3571
3572 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3573 continue;
3574
3575 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3576
3577 list_for_each_entry(connector, &mode_config->connector_list, head) {
3578 struct intel_connector *intel_connector = to_intel_connector(connector);
3579
3580 if (intel_connector->encoder->hpd_pin == i) {
3581 if (connector->polled != intel_connector->polled)
3582 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3583 drm_get_connector_name(connector));
3584 connector->polled = intel_connector->polled;
3585 if (!connector->polled)
3586 connector->polled = DRM_CONNECTOR_POLL_HPD;
3587 }
3588 }
3589 }
3590 if (dev_priv->display.hpd_irq_setup)
3591 dev_priv->display.hpd_irq_setup(dev);
3592 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3593}
3594
f71d4af4
JB		 3595void intel_irq_init(struct drm_device *dev)
3596{
8b2e326d
CW		 3597 struct drm_i915_private *dev_priv = dev->dev_private;
3598
3599 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3600 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3601 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3602 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3603
99584db3
DV		 3604 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3605 i915_hangcheck_elapsed,
61bac78e 3606 (unsigned long) dev);
ac4c16c5
EE		 3607 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3608 (unsigned long) dev_priv);
61bac78e 3609
97a19a24 3610 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3611
f71d4af4
JB		 3612 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3613 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3614 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3615 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3616 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3617 }
3618
c3613de9
KP		 3619 if (drm_core_check_feature(dev, DRIVER_MODESET))
3620 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3621 else
3622 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3623 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3624
7e231dbe
JB		 3625 if (IS_VALLEYVIEW(dev)) {
3626 dev->driver->irq_handler = valleyview_irq_handler;
3627 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3628 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3629 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3630 dev->driver->enable_vblank = valleyview_enable_vblank;
3631 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3632 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3633 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3634 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3635 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3636 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3637 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3638 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3639 dev->driver->enable_vblank = ivybridge_enable_vblank;
3640 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3641 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3642 } else if (HAS_PCH_SPLIT(dev)) {
3643 dev->driver->irq_handler = ironlake_irq_handler;
3644 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3645 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3646 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3647 dev->driver->enable_vblank = ironlake_enable_vblank;
3648 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3649 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3650 } else {
c2798b19
CW		 3651 if (INTEL_INFO(dev)->gen == 2) {
3652 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3653 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3654 dev->driver->irq_handler = i8xx_irq_handler;
3655 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3656 } else if (INTEL_INFO(dev)->gen == 3) {
3657 dev->driver->irq_preinstall = i915_irq_preinstall;
3658 dev->driver->irq_postinstall = i915_irq_postinstall;
3659 dev->driver->irq_uninstall = i915_irq_uninstall;
3660 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3661 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3662 } else {
a266c7d5
CW		 3663 dev->driver->irq_preinstall = i965_irq_preinstall;
3664 dev->driver->irq_postinstall = i965_irq_postinstall;
3665 dev->driver->irq_uninstall = i965_irq_uninstall;
3666 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3667 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3668 }
f71d4af4
JB		 3669 dev->driver->enable_vblank = i915_enable_vblank;
3670 dev->driver->disable_vblank = i915_disable_vblank;
3671 }
3672}
20afbda2
DV		 3673
3674void intel_hpd_init(struct drm_device *dev)
3675{
3676 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3677 struct drm_mode_config *mode_config = &dev->mode_config;
3678 struct drm_connector *connector;
b5ea2d56 3679 unsigned long irqflags;
821450c6 3680 int i;
20afbda2 3681
821450c6
EE		 3682 for (i = 1; i < HPD_NUM_PINS; i++) {
3683 dev_priv->hpd_stats[i].hpd_cnt = 0;
3684 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3685 }
3686 list_for_each_entry(connector, &mode_config->connector_list, head) {
3687 struct intel_connector *intel_connector = to_intel_connector(connector);
3688 connector->polled = intel_connector->polled;
3689 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3690 connector->polled = DRM_CONNECTOR_POLL_HPD;
3691 }
b5ea2d56
DV		 3692
3693 /* Interrupt setup is already guaranteed to be single-threaded, this is
3694 * just to make the assert_spin_locked checks happy. */
3695 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3696 if (dev_priv->display.hpd_irq_setup)
3697 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3698 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3699}
Linux kernel - Deliverables
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