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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
7c7e10db | 48 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
54 | }; | |
55 | ||
7c7e10db | 56 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 57 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 58 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
59 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
60 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
61 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
62 | }; | |
63 | ||
7c7e10db | 64 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
71 | }; | |
72 | ||
7c7e10db | 73 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
4bca26d0 | 82 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
83 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
84 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
85 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
86 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
87 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
88 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
89 | }; | |
90 | ||
e0a20ad7 SS |
91 | /* BXT hpd list */ |
92 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
93 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, | |
94 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
95 | }; | |
96 | ||
5c502442 | 97 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 98 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
99 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
100 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
101 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
102 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
103 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
104 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
105 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
106 | } while (0) | |
107 | ||
f86f3fb0 | 108 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 109 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 110 | POSTING_READ(type##IMR); \ |
a9d356a6 | 111 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
112 | I915_WRITE(type##IIR, 0xffffffff); \ |
113 | POSTING_READ(type##IIR); \ | |
114 | I915_WRITE(type##IIR, 0xffffffff); \ | |
115 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
116 | } while (0) |
117 | ||
337ba017 PZ |
118 | /* |
119 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
120 | */ | |
121 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
122 | u32 val = I915_READ(reg); \ | |
123 | if (val) { \ | |
124 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
125 | (reg), val); \ | |
126 | I915_WRITE((reg), 0xffffffff); \ | |
127 | POSTING_READ(reg); \ | |
128 | I915_WRITE((reg), 0xffffffff); \ | |
129 | POSTING_READ(reg); \ | |
130 | } \ | |
131 | } while (0) | |
132 | ||
35079899 | 133 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 134 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 135 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
136 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
137 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
138 | } while (0) |
139 | ||
140 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 141 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 142 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
143 | I915_WRITE(type##IMR, (imr_val)); \ |
144 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
145 | } while (0) |
146 | ||
c9a9a268 ID |
147 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
148 | ||
036a4a7d | 149 | /* For display hotplug interrupt */ |
47339cd9 | 150 | void |
2d1013dd | 151 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 152 | { |
4bc9d430 DV |
153 | assert_spin_locked(&dev_priv->irq_lock); |
154 | ||
9df7575f | 155 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 156 | return; |
c67a470b | 157 | |
1ec14ad3 CW |
158 | if ((dev_priv->irq_mask & mask) != 0) { |
159 | dev_priv->irq_mask &= ~mask; | |
160 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 161 | POSTING_READ(DEIMR); |
036a4a7d ZW |
162 | } |
163 | } | |
164 | ||
47339cd9 | 165 | void |
2d1013dd | 166 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 167 | { |
4bc9d430 DV |
168 | assert_spin_locked(&dev_priv->irq_lock); |
169 | ||
06ffc778 | 170 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 171 | return; |
c67a470b | 172 | |
1ec14ad3 CW |
173 | if ((dev_priv->irq_mask & mask) != mask) { |
174 | dev_priv->irq_mask |= mask; | |
175 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 176 | POSTING_READ(DEIMR); |
036a4a7d ZW |
177 | } |
178 | } | |
179 | ||
43eaea13 PZ |
180 | /** |
181 | * ilk_update_gt_irq - update GTIMR | |
182 | * @dev_priv: driver private | |
183 | * @interrupt_mask: mask of interrupt bits to update | |
184 | * @enabled_irq_mask: mask of interrupt bits to enable | |
185 | */ | |
186 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
187 | uint32_t interrupt_mask, | |
188 | uint32_t enabled_irq_mask) | |
189 | { | |
190 | assert_spin_locked(&dev_priv->irq_lock); | |
191 | ||
15a17aae DV |
192 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
193 | ||
9df7575f | 194 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 195 | return; |
c67a470b | 196 | |
43eaea13 PZ |
197 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
198 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
199 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
200 | POSTING_READ(GTIMR); | |
201 | } | |
202 | ||
480c8033 | 203 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
204 | { |
205 | ilk_update_gt_irq(dev_priv, mask, mask); | |
206 | } | |
207 | ||
480c8033 | 208 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
209 | { |
210 | ilk_update_gt_irq(dev_priv, mask, 0); | |
211 | } | |
212 | ||
b900b949 ID |
213 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
214 | { | |
215 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
216 | } | |
217 | ||
a72fbc3a ID |
218 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
219 | { | |
220 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
221 | } | |
222 | ||
b900b949 ID |
223 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
224 | { | |
225 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
226 | } | |
227 | ||
edbfdb45 PZ |
228 | /** |
229 | * snb_update_pm_irq - update GEN6_PMIMR | |
230 | * @dev_priv: driver private | |
231 | * @interrupt_mask: mask of interrupt bits to update | |
232 | * @enabled_irq_mask: mask of interrupt bits to enable | |
233 | */ | |
234 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
235 | uint32_t interrupt_mask, | |
236 | uint32_t enabled_irq_mask) | |
237 | { | |
605cd25b | 238 | uint32_t new_val; |
edbfdb45 | 239 | |
15a17aae DV |
240 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
241 | ||
edbfdb45 PZ |
242 | assert_spin_locked(&dev_priv->irq_lock); |
243 | ||
605cd25b | 244 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
245 | new_val &= ~interrupt_mask; |
246 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
247 | ||
605cd25b PZ |
248 | if (new_val != dev_priv->pm_irq_mask) { |
249 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
250 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
251 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 252 | } |
edbfdb45 PZ |
253 | } |
254 | ||
480c8033 | 255 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 256 | { |
9939fba2 ID |
257 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
258 | return; | |
259 | ||
edbfdb45 PZ |
260 | snb_update_pm_irq(dev_priv, mask, mask); |
261 | } | |
262 | ||
9939fba2 ID |
263 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
264 | uint32_t mask) | |
edbfdb45 PZ |
265 | { |
266 | snb_update_pm_irq(dev_priv, mask, 0); | |
267 | } | |
268 | ||
9939fba2 ID |
269 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
270 | { | |
271 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
272 | return; | |
273 | ||
274 | __gen6_disable_pm_irq(dev_priv, mask); | |
275 | } | |
276 | ||
3cc134e3 ID |
277 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
278 | { | |
279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
280 | uint32_t reg = gen6_pm_iir(dev_priv); | |
281 | ||
282 | spin_lock_irq(&dev_priv->irq_lock); | |
283 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
284 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
285 | POSTING_READ(reg); | |
096fad9e | 286 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
287 | spin_unlock_irq(&dev_priv->irq_lock); |
288 | } | |
289 | ||
b900b949 ID |
290 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
291 | { | |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | ||
294 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 295 | |
b900b949 | 296 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 297 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 298 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
299 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
300 | dev_priv->pm_rps_events); | |
b900b949 | 301 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 302 | |
b900b949 ID |
303 | spin_unlock_irq(&dev_priv->irq_lock); |
304 | } | |
305 | ||
59d02a1f ID |
306 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
307 | { | |
308 | /* | |
f24eeb19 | 309 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 310 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
311 | * |
312 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
313 | */ |
314 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
315 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
316 | ||
317 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
318 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
319 | ||
320 | return mask; | |
321 | } | |
322 | ||
b900b949 ID |
323 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
324 | { | |
325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
326 | ||
d4d70aa5 ID |
327 | spin_lock_irq(&dev_priv->irq_lock); |
328 | dev_priv->rps.interrupts_enabled = false; | |
329 | spin_unlock_irq(&dev_priv->irq_lock); | |
330 | ||
331 | cancel_work_sync(&dev_priv->rps.work); | |
332 | ||
9939fba2 ID |
333 | spin_lock_irq(&dev_priv->irq_lock); |
334 | ||
59d02a1f | 335 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
336 | |
337 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
338 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
339 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
340 | |
341 | spin_unlock_irq(&dev_priv->irq_lock); | |
342 | ||
343 | synchronize_irq(dev->irq); | |
b900b949 ID |
344 | } |
345 | ||
fee884ed DV |
346 | /** |
347 | * ibx_display_interrupt_update - update SDEIMR | |
348 | * @dev_priv: driver private | |
349 | * @interrupt_mask: mask of interrupt bits to update | |
350 | * @enabled_irq_mask: mask of interrupt bits to enable | |
351 | */ | |
47339cd9 DV |
352 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
353 | uint32_t interrupt_mask, | |
354 | uint32_t enabled_irq_mask) | |
fee884ed DV |
355 | { |
356 | uint32_t sdeimr = I915_READ(SDEIMR); | |
357 | sdeimr &= ~interrupt_mask; | |
358 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
359 | ||
15a17aae DV |
360 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
361 | ||
fee884ed DV |
362 | assert_spin_locked(&dev_priv->irq_lock); |
363 | ||
9df7575f | 364 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 365 | return; |
c67a470b | 366 | |
fee884ed DV |
367 | I915_WRITE(SDEIMR, sdeimr); |
368 | POSTING_READ(SDEIMR); | |
369 | } | |
8664281b | 370 | |
b5ea642a | 371 | static void |
755e9019 ID |
372 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
373 | u32 enable_mask, u32 status_mask) | |
7c463586 | 374 | { |
46c06a30 | 375 | u32 reg = PIPESTAT(pipe); |
755e9019 | 376 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 377 | |
b79480ba | 378 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 379 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 380 | |
04feced9 VS |
381 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
382 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
383 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
384 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
385 | return; |
386 | ||
387 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
388 | return; |
389 | ||
91d181dd ID |
390 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
391 | ||
46c06a30 | 392 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 393 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
394 | I915_WRITE(reg, pipestat); |
395 | POSTING_READ(reg); | |
7c463586 KP |
396 | } |
397 | ||
b5ea642a | 398 | static void |
755e9019 ID |
399 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
400 | u32 enable_mask, u32 status_mask) | |
7c463586 | 401 | { |
46c06a30 | 402 | u32 reg = PIPESTAT(pipe); |
755e9019 | 403 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 404 | |
b79480ba | 405 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 406 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 407 | |
04feced9 VS |
408 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
409 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
410 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
411 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
412 | return; |
413 | ||
755e9019 ID |
414 | if ((pipestat & enable_mask) == 0) |
415 | return; | |
416 | ||
91d181dd ID |
417 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
418 | ||
755e9019 | 419 | pipestat &= ~enable_mask; |
46c06a30 VS |
420 | I915_WRITE(reg, pipestat); |
421 | POSTING_READ(reg); | |
7c463586 KP |
422 | } |
423 | ||
10c59c51 ID |
424 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
425 | { | |
426 | u32 enable_mask = status_mask << 16; | |
427 | ||
428 | /* | |
724a6905 VS |
429 | * On pipe A we don't support the PSR interrupt yet, |
430 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
431 | */ |
432 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
433 | return 0; | |
724a6905 VS |
434 | /* |
435 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
436 | * A the same bit is for perf counters which we don't use either. | |
437 | */ | |
438 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
439 | return 0; | |
10c59c51 ID |
440 | |
441 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
442 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
443 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
444 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
445 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
446 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
447 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
448 | ||
449 | return enable_mask; | |
450 | } | |
451 | ||
755e9019 ID |
452 | void |
453 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
454 | u32 status_mask) | |
455 | { | |
456 | u32 enable_mask; | |
457 | ||
10c59c51 ID |
458 | if (IS_VALLEYVIEW(dev_priv->dev)) |
459 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
460 | status_mask); | |
461 | else | |
462 | enable_mask = status_mask << 16; | |
755e9019 ID |
463 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
464 | } | |
465 | ||
466 | void | |
467 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
468 | u32 status_mask) | |
469 | { | |
470 | u32 enable_mask; | |
471 | ||
10c59c51 ID |
472 | if (IS_VALLEYVIEW(dev_priv->dev)) |
473 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
474 | status_mask); | |
475 | else | |
476 | enable_mask = status_mask << 16; | |
755e9019 ID |
477 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
478 | } | |
479 | ||
01c66889 | 480 | /** |
f49e38dd | 481 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 482 | */ |
f49e38dd | 483 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 484 | { |
2d1013dd | 485 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 486 | |
f49e38dd JN |
487 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
488 | return; | |
489 | ||
13321786 | 490 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 491 | |
755e9019 | 492 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 493 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 494 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 495 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 496 | |
13321786 | 497 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
498 | } |
499 | ||
f75f3746 VS |
500 | /* |
501 | * This timing diagram depicts the video signal in and | |
502 | * around the vertical blanking period. | |
503 | * | |
504 | * Assumptions about the fictitious mode used in this example: | |
505 | * vblank_start >= 3 | |
506 | * vsync_start = vblank_start + 1 | |
507 | * vsync_end = vblank_start + 2 | |
508 | * vtotal = vblank_start + 3 | |
509 | * | |
510 | * start of vblank: | |
511 | * latch double buffered registers | |
512 | * increment frame counter (ctg+) | |
513 | * generate start of vblank interrupt (gen4+) | |
514 | * | | |
515 | * | frame start: | |
516 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
517 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
518 | * | | | |
519 | * | | start of vsync: | |
520 | * | | generate vsync interrupt | |
521 | * | | | | |
522 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
523 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
524 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
525 | * | | <----vs-----> | | |
526 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
527 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
528 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
529 | * | | | | |
530 | * last visible pixel first visible pixel | |
531 | * | increment frame counter (gen3/4) | |
532 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
533 | * | |
534 | * x = horizontal active | |
535 | * _ = horizontal blanking | |
536 | * hs = horizontal sync | |
537 | * va = vertical active | |
538 | * vb = vertical blanking | |
539 | * vs = vertical sync | |
540 | * vbs = vblank_start (number) | |
541 | * | |
542 | * Summary: | |
543 | * - most events happen at the start of horizontal sync | |
544 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
545 | * (depending on PIPECONF settings) after the start of vblank | |
546 | * - gen3/4 pixel and frame counter are synchronized with the start | |
547 | * of horizontal active on the first line of vertical active | |
548 | */ | |
549 | ||
4cdb83ec VS |
550 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
551 | { | |
552 | /* Gen2 doesn't have a hardware frame counter */ | |
553 | return 0; | |
554 | } | |
555 | ||
42f52ef8 KP |
556 | /* Called from drm generic code, passed a 'crtc', which |
557 | * we use as a pipe index | |
558 | */ | |
f71d4af4 | 559 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 560 | { |
2d1013dd | 561 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
562 | unsigned long high_frame; |
563 | unsigned long low_frame; | |
0b2a8e09 | 564 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
565 | struct intel_crtc *intel_crtc = |
566 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 567 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 568 | |
f3a5c3f6 DV |
569 | htotal = mode->crtc_htotal; |
570 | hsync_start = mode->crtc_hsync_start; | |
571 | vbl_start = mode->crtc_vblank_start; | |
572 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
573 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 574 | |
0b2a8e09 VS |
575 | /* Convert to pixel count */ |
576 | vbl_start *= htotal; | |
577 | ||
578 | /* Start of vblank event occurs at start of hsync */ | |
579 | vbl_start -= htotal - hsync_start; | |
580 | ||
9db4a9c7 JB |
581 | high_frame = PIPEFRAME(pipe); |
582 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 583 | |
0a3e67a4 JB |
584 | /* |
585 | * High & low register fields aren't synchronized, so make sure | |
586 | * we get a low value that's stable across two reads of the high | |
587 | * register. | |
588 | */ | |
589 | do { | |
5eddb70b | 590 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 591 | low = I915_READ(low_frame); |
5eddb70b | 592 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
593 | } while (high1 != high2); |
594 | ||
5eddb70b | 595 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 596 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 597 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
598 | |
599 | /* | |
600 | * The frame counter increments at beginning of active. | |
601 | * Cook up a vblank counter by also checking the pixel | |
602 | * counter against vblank start. | |
603 | */ | |
edc08d0a | 604 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
605 | } |
606 | ||
f71d4af4 | 607 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 608 | { |
2d1013dd | 609 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 610 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 | 611 | |
9880b7a5 JB |
612 | return I915_READ(reg); |
613 | } | |
614 | ||
ad3543ed MK |
615 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
616 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 617 | |
a225f079 VS |
618 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
619 | { | |
620 | struct drm_device *dev = crtc->base.dev; | |
621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 622 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 623 | enum pipe pipe = crtc->pipe; |
80715b2f | 624 | int position, vtotal; |
a225f079 | 625 | |
80715b2f | 626 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
627 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
628 | vtotal /= 2; | |
629 | ||
630 | if (IS_GEN2(dev)) | |
631 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
632 | else | |
633 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
634 | ||
635 | /* | |
80715b2f VS |
636 | * See update_scanline_offset() for the details on the |
637 | * scanline_offset adjustment. | |
a225f079 | 638 | */ |
80715b2f | 639 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
640 | } |
641 | ||
f71d4af4 | 642 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
643 | unsigned int flags, int *vpos, int *hpos, |
644 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 645 | { |
c2baf4b7 VS |
646 | struct drm_i915_private *dev_priv = dev->dev_private; |
647 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fc467a22 | 649 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
3aa18df8 | 650 | int position; |
78e8fc6b | 651 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
652 | bool in_vbl = true; |
653 | int ret = 0; | |
ad3543ed | 654 | unsigned long irqflags; |
0af7e4df | 655 | |
fc467a22 | 656 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 657 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 658 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
659 | return 0; |
660 | } | |
661 | ||
c2baf4b7 | 662 | htotal = mode->crtc_htotal; |
78e8fc6b | 663 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
664 | vtotal = mode->crtc_vtotal; |
665 | vbl_start = mode->crtc_vblank_start; | |
666 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 667 | |
d31faf65 VS |
668 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
669 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
670 | vbl_end /= 2; | |
671 | vtotal /= 2; | |
672 | } | |
673 | ||
c2baf4b7 VS |
674 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
675 | ||
ad3543ed MK |
676 | /* |
677 | * Lock uncore.lock, as we will do multiple timing critical raw | |
678 | * register reads, potentially with preemption disabled, so the | |
679 | * following code must not block on uncore.lock. | |
680 | */ | |
681 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 682 | |
ad3543ed MK |
683 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
684 | ||
685 | /* Get optional system timestamp before query. */ | |
686 | if (stime) | |
687 | *stime = ktime_get(); | |
688 | ||
7c06b08a | 689 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
690 | /* No obvious pixelcount register. Only query vertical |
691 | * scanout position from Display scan line register. | |
692 | */ | |
a225f079 | 693 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
694 | } else { |
695 | /* Have access to pixelcount since start of frame. | |
696 | * We can split this into vertical and horizontal | |
697 | * scanout position. | |
698 | */ | |
ad3543ed | 699 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 700 | |
3aa18df8 VS |
701 | /* convert to pixel counts */ |
702 | vbl_start *= htotal; | |
703 | vbl_end *= htotal; | |
704 | vtotal *= htotal; | |
78e8fc6b | 705 | |
7e78f1cb VS |
706 | /* |
707 | * In interlaced modes, the pixel counter counts all pixels, | |
708 | * so one field will have htotal more pixels. In order to avoid | |
709 | * the reported position from jumping backwards when the pixel | |
710 | * counter is beyond the length of the shorter field, just | |
711 | * clamp the position the length of the shorter field. This | |
712 | * matches how the scanline counter based position works since | |
713 | * the scanline counter doesn't count the two half lines. | |
714 | */ | |
715 | if (position >= vtotal) | |
716 | position = vtotal - 1; | |
717 | ||
78e8fc6b VS |
718 | /* |
719 | * Start of vblank interrupt is triggered at start of hsync, | |
720 | * just prior to the first active line of vblank. However we | |
721 | * consider lines to start at the leading edge of horizontal | |
722 | * active. So, should we get here before we've crossed into | |
723 | * the horizontal active of the first line in vblank, we would | |
724 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
725 | * always add htotal-hsync_start to the current pixel position. | |
726 | */ | |
727 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
728 | } |
729 | ||
ad3543ed MK |
730 | /* Get optional system timestamp after query. */ |
731 | if (etime) | |
732 | *etime = ktime_get(); | |
733 | ||
734 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
735 | ||
736 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
737 | ||
3aa18df8 VS |
738 | in_vbl = position >= vbl_start && position < vbl_end; |
739 | ||
740 | /* | |
741 | * While in vblank, position will be negative | |
742 | * counting up towards 0 at vbl_end. And outside | |
743 | * vblank, position will be positive counting | |
744 | * up since vbl_end. | |
745 | */ | |
746 | if (position >= vbl_start) | |
747 | position -= vbl_end; | |
748 | else | |
749 | position += vtotal - vbl_end; | |
0af7e4df | 750 | |
7c06b08a | 751 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
752 | *vpos = position; |
753 | *hpos = 0; | |
754 | } else { | |
755 | *vpos = position / htotal; | |
756 | *hpos = position - (*vpos * htotal); | |
757 | } | |
0af7e4df | 758 | |
0af7e4df MK |
759 | /* In vblank? */ |
760 | if (in_vbl) | |
3d3cbd84 | 761 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
762 | |
763 | return ret; | |
764 | } | |
765 | ||
a225f079 VS |
766 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
767 | { | |
768 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
769 | unsigned long irqflags; | |
770 | int position; | |
771 | ||
772 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
773 | position = __intel_get_crtc_scanline(crtc); | |
774 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
775 | ||
776 | return position; | |
777 | } | |
778 | ||
f71d4af4 | 779 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
780 | int *max_error, |
781 | struct timeval *vblank_time, | |
782 | unsigned flags) | |
783 | { | |
4041b853 | 784 | struct drm_crtc *crtc; |
0af7e4df | 785 | |
7eb552ae | 786 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 787 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
788 | return -EINVAL; |
789 | } | |
790 | ||
791 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
792 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
793 | if (crtc == NULL) { | |
794 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
795 | return -EINVAL; | |
796 | } | |
797 | ||
fc467a22 | 798 | if (!crtc->hwmode.crtc_clock) { |
4041b853 CW |
799 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
800 | return -EBUSY; | |
801 | } | |
0af7e4df MK |
802 | |
803 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
804 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
805 | vblank_time, flags, | |
7da903ef | 806 | crtc, |
fc467a22 | 807 | &crtc->hwmode); |
0af7e4df MK |
808 | } |
809 | ||
d0ecd7e2 | 810 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 811 | { |
2d1013dd | 812 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 813 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 814 | u8 new_delay; |
9270388e | 815 | |
d0ecd7e2 | 816 | spin_lock(&mchdev_lock); |
f97108d1 | 817 | |
73edd18f DV |
818 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
819 | ||
20e4d407 | 820 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 821 | |
7648fa99 | 822 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
823 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
824 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
825 | max_avg = I915_READ(RCBMAXAVG); |
826 | min_avg = I915_READ(RCBMINAVG); | |
827 | ||
828 | /* Handle RCS change request from hw */ | |
b5b72e89 | 829 | if (busy_up > max_avg) { |
20e4d407 DV |
830 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
831 | new_delay = dev_priv->ips.cur_delay - 1; | |
832 | if (new_delay < dev_priv->ips.max_delay) | |
833 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 834 | } else if (busy_down < min_avg) { |
20e4d407 DV |
835 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
836 | new_delay = dev_priv->ips.cur_delay + 1; | |
837 | if (new_delay > dev_priv->ips.min_delay) | |
838 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
839 | } |
840 | ||
7648fa99 | 841 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 842 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 843 | |
d0ecd7e2 | 844 | spin_unlock(&mchdev_lock); |
9270388e | 845 | |
f97108d1 JB |
846 | return; |
847 | } | |
848 | ||
74cdb337 | 849 | static void notify_ring(struct intel_engine_cs *ring) |
549f7365 | 850 | { |
93b0a4e0 | 851 | if (!intel_ring_initialized(ring)) |
475553de CW |
852 | return; |
853 | ||
bcfcc8ba | 854 | trace_i915_gem_request_notify(ring); |
9862e600 | 855 | |
549f7365 | 856 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
857 | } |
858 | ||
43cf3bf0 CW |
859 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
860 | struct intel_rps_ei *ei) | |
31685c25 | 861 | { |
43cf3bf0 CW |
862 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
863 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
864 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
865 | } | |
31685c25 | 866 | |
43cf3bf0 CW |
867 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
868 | const struct intel_rps_ei *old, | |
869 | const struct intel_rps_ei *now, | |
870 | int threshold) | |
871 | { | |
872 | u64 time, c0; | |
31685c25 | 873 | |
43cf3bf0 CW |
874 | if (old->cz_clock == 0) |
875 | return false; | |
31685c25 | 876 | |
43cf3bf0 CW |
877 | time = now->cz_clock - old->cz_clock; |
878 | time *= threshold * dev_priv->mem_freq; | |
31685c25 | 879 | |
43cf3bf0 CW |
880 | /* Workload can be split between render + media, e.g. SwapBuffers |
881 | * being blitted in X after being rendered in mesa. To account for | |
882 | * this we need to combine both engines into our activity counter. | |
31685c25 | 883 | */ |
43cf3bf0 CW |
884 | c0 = now->render_c0 - old->render_c0; |
885 | c0 += now->media_c0 - old->media_c0; | |
886 | c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; | |
31685c25 | 887 | |
43cf3bf0 | 888 | return c0 >= time; |
31685c25 D |
889 | } |
890 | ||
43cf3bf0 | 891 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 892 | { |
43cf3bf0 CW |
893 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
894 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 895 | } |
31685c25 | 896 | |
43cf3bf0 CW |
897 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
898 | { | |
899 | struct intel_rps_ei now; | |
900 | u32 events = 0; | |
31685c25 | 901 | |
6f4b12f8 | 902 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 903 | return 0; |
31685c25 | 904 | |
43cf3bf0 CW |
905 | vlv_c0_read(dev_priv, &now); |
906 | if (now.cz_clock == 0) | |
907 | return 0; | |
31685c25 | 908 | |
43cf3bf0 CW |
909 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
910 | if (!vlv_c0_above(dev_priv, | |
911 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 912 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
913 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
914 | dev_priv->rps.down_ei = now; | |
915 | } | |
31685c25 | 916 | |
43cf3bf0 CW |
917 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
918 | if (vlv_c0_above(dev_priv, | |
919 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 920 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
921 | events |= GEN6_PM_RP_UP_THRESHOLD; |
922 | dev_priv->rps.up_ei = now; | |
31685c25 D |
923 | } |
924 | ||
43cf3bf0 | 925 | return events; |
31685c25 D |
926 | } |
927 | ||
f5a4c67d CW |
928 | static bool any_waiters(struct drm_i915_private *dev_priv) |
929 | { | |
930 | struct intel_engine_cs *ring; | |
931 | int i; | |
932 | ||
933 | for_each_ring(ring, dev_priv, i) | |
934 | if (ring->irq_refcount) | |
935 | return true; | |
936 | ||
937 | return false; | |
938 | } | |
939 | ||
4912d041 | 940 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 941 | { |
2d1013dd JN |
942 | struct drm_i915_private *dev_priv = |
943 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
944 | bool client_boost; |
945 | int new_delay, adj, min, max; | |
edbfdb45 | 946 | u32 pm_iir; |
4912d041 | 947 | |
59cdb63d | 948 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
949 | /* Speed up work cancelation during disabling rps interrupts. */ |
950 | if (!dev_priv->rps.interrupts_enabled) { | |
951 | spin_unlock_irq(&dev_priv->irq_lock); | |
952 | return; | |
953 | } | |
c6a828d3 DV |
954 | pm_iir = dev_priv->rps.pm_iir; |
955 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
956 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
957 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
958 | client_boost = dev_priv->rps.client_boost; |
959 | dev_priv->rps.client_boost = false; | |
59cdb63d | 960 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 961 | |
60611c13 | 962 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 963 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 964 | |
8d3afd7d | 965 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
3b8d8d91 JB |
966 | return; |
967 | ||
4fc688ce | 968 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 969 | |
43cf3bf0 CW |
970 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
971 | ||
dd75fdc8 | 972 | adj = dev_priv->rps.last_adj; |
edcf284b | 973 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
974 | min = dev_priv->rps.min_freq_softlimit; |
975 | max = dev_priv->rps.max_freq_softlimit; | |
976 | ||
977 | if (client_boost) { | |
978 | new_delay = dev_priv->rps.max_freq_softlimit; | |
979 | adj = 0; | |
980 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
981 | if (adj > 0) |
982 | adj *= 2; | |
edcf284b CW |
983 | else /* CHV needs even encode values */ |
984 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
985 | /* |
986 | * For better performance, jump directly | |
987 | * to RPe if we're below it. | |
988 | */ | |
edcf284b | 989 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 990 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
991 | adj = 0; |
992 | } | |
f5a4c67d CW |
993 | } else if (any_waiters(dev_priv)) { |
994 | adj = 0; | |
dd75fdc8 | 995 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
996 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
997 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 998 | else |
b39fb297 | 999 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1000 | adj = 0; |
1001 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1002 | if (adj < 0) | |
1003 | adj *= 2; | |
edcf284b CW |
1004 | else /* CHV needs even encode values */ |
1005 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1006 | } else { /* unknown event */ |
edcf284b | 1007 | adj = 0; |
dd75fdc8 | 1008 | } |
3b8d8d91 | 1009 | |
edcf284b CW |
1010 | dev_priv->rps.last_adj = adj; |
1011 | ||
79249636 BW |
1012 | /* sysfs frequency interfaces may have snuck in while servicing the |
1013 | * interrupt | |
1014 | */ | |
edcf284b | 1015 | new_delay += adj; |
8d3afd7d | 1016 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1017 | |
ffe02b40 | 1018 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1019 | |
4fc688ce | 1020 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1021 | } |
1022 | ||
e3689190 BW |
1023 | |
1024 | /** | |
1025 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1026 | * occurred. | |
1027 | * @work: workqueue struct | |
1028 | * | |
1029 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1030 | * this event, userspace should try to remap the bad rows since statistically | |
1031 | * it is likely the same row is more likely to go bad again. | |
1032 | */ | |
1033 | static void ivybridge_parity_work(struct work_struct *work) | |
1034 | { | |
2d1013dd JN |
1035 | struct drm_i915_private *dev_priv = |
1036 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1037 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1038 | char *parity_event[6]; |
e3689190 | 1039 | uint32_t misccpctl; |
35a85ac6 | 1040 | uint8_t slice = 0; |
e3689190 BW |
1041 | |
1042 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1043 | * In order to prevent a get/put style interface, acquire struct mutex | |
1044 | * any time we access those registers. | |
1045 | */ | |
1046 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1047 | ||
35a85ac6 BW |
1048 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1049 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1050 | goto out; | |
1051 | ||
e3689190 BW |
1052 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1053 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1054 | POSTING_READ(GEN7_MISCCPCTL); | |
1055 | ||
35a85ac6 BW |
1056 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1057 | u32 reg; | |
e3689190 | 1058 | |
35a85ac6 BW |
1059 | slice--; |
1060 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1061 | break; | |
e3689190 | 1062 | |
35a85ac6 | 1063 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1064 | |
35a85ac6 | 1065 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1066 | |
35a85ac6 BW |
1067 | error_status = I915_READ(reg); |
1068 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1069 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1070 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1071 | ||
1072 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1073 | POSTING_READ(reg); | |
1074 | ||
1075 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1076 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1077 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1078 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1079 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1080 | parity_event[5] = NULL; | |
1081 | ||
5bdebb18 | 1082 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1083 | KOBJ_CHANGE, parity_event); |
e3689190 | 1084 | |
35a85ac6 BW |
1085 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1086 | slice, row, bank, subbank); | |
e3689190 | 1087 | |
35a85ac6 BW |
1088 | kfree(parity_event[4]); |
1089 | kfree(parity_event[3]); | |
1090 | kfree(parity_event[2]); | |
1091 | kfree(parity_event[1]); | |
1092 | } | |
e3689190 | 1093 | |
35a85ac6 | 1094 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1095 | |
35a85ac6 BW |
1096 | out: |
1097 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1098 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1099 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1100 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1101 | |
1102 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1103 | } |
1104 | ||
35a85ac6 | 1105 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1106 | { |
2d1013dd | 1107 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1108 | |
040d2baa | 1109 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1110 | return; |
1111 | ||
d0ecd7e2 | 1112 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1113 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1114 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1115 | |
35a85ac6 BW |
1116 | iir &= GT_PARITY_ERROR(dev); |
1117 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1118 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1119 | ||
1120 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1121 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1122 | ||
a4da4fa4 | 1123 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1124 | } |
1125 | ||
f1af8fc1 PZ |
1126 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1127 | struct drm_i915_private *dev_priv, | |
1128 | u32 gt_iir) | |
1129 | { | |
1130 | if (gt_iir & | |
1131 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1132 | notify_ring(&dev_priv->ring[RCS]); |
f1af8fc1 | 1133 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
74cdb337 | 1134 | notify_ring(&dev_priv->ring[VCS]); |
f1af8fc1 PZ |
1135 | } |
1136 | ||
e7b4c6b1 DV |
1137 | static void snb_gt_irq_handler(struct drm_device *dev, |
1138 | struct drm_i915_private *dev_priv, | |
1139 | u32 gt_iir) | |
1140 | { | |
1141 | ||
cc609d5d BW |
1142 | if (gt_iir & |
1143 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1144 | notify_ring(&dev_priv->ring[RCS]); |
cc609d5d | 1145 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
74cdb337 | 1146 | notify_ring(&dev_priv->ring[VCS]); |
cc609d5d | 1147 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
74cdb337 | 1148 | notify_ring(&dev_priv->ring[BCS]); |
e7b4c6b1 | 1149 | |
cc609d5d BW |
1150 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1151 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1152 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1153 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1154 | |
35a85ac6 BW |
1155 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1156 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1157 | } |
1158 | ||
74cdb337 | 1159 | static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
abd58f01 BW |
1160 | u32 master_ctl) |
1161 | { | |
abd58f01 BW |
1162 | irqreturn_t ret = IRQ_NONE; |
1163 | ||
1164 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
74cdb337 | 1165 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(0)); |
abd58f01 | 1166 | if (tmp) { |
cb0d205e | 1167 | I915_WRITE_FW(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1168 | ret = IRQ_HANDLED; |
e981e7b1 | 1169 | |
74cdb337 CW |
1170 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) |
1171 | intel_lrc_irq_handler(&dev_priv->ring[RCS]); | |
1172 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) | |
1173 | notify_ring(&dev_priv->ring[RCS]); | |
1174 | ||
1175 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1176 | intel_lrc_irq_handler(&dev_priv->ring[BCS]); | |
1177 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1178 | notify_ring(&dev_priv->ring[BCS]); | |
abd58f01 BW |
1179 | } else |
1180 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1181 | } | |
1182 | ||
85f9b5f9 | 1183 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
74cdb337 | 1184 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(1)); |
abd58f01 | 1185 | if (tmp) { |
cb0d205e | 1186 | I915_WRITE_FW(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1187 | ret = IRQ_HANDLED; |
e981e7b1 | 1188 | |
74cdb337 CW |
1189 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) |
1190 | intel_lrc_irq_handler(&dev_priv->ring[VCS]); | |
1191 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) | |
1192 | notify_ring(&dev_priv->ring[VCS]); | |
abd58f01 | 1193 | |
74cdb337 CW |
1194 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) |
1195 | intel_lrc_irq_handler(&dev_priv->ring[VCS2]); | |
1196 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) | |
1197 | notify_ring(&dev_priv->ring[VCS2]); | |
0961021a | 1198 | } else |
abd58f01 | 1199 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1200 | } |
1201 | ||
abd58f01 | 1202 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
74cdb337 | 1203 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(3)); |
abd58f01 | 1204 | if (tmp) { |
74cdb337 | 1205 | I915_WRITE_FW(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1206 | ret = IRQ_HANDLED; |
e981e7b1 | 1207 | |
74cdb337 CW |
1208 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) |
1209 | intel_lrc_irq_handler(&dev_priv->ring[VECS]); | |
1210 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) | |
1211 | notify_ring(&dev_priv->ring[VECS]); | |
abd58f01 BW |
1212 | } else |
1213 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1214 | } | |
1215 | ||
0961021a | 1216 | if (master_ctl & GEN8_GT_PM_IRQ) { |
74cdb337 | 1217 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(2)); |
0961021a | 1218 | if (tmp & dev_priv->pm_rps_events) { |
cb0d205e CW |
1219 | I915_WRITE_FW(GEN8_GT_IIR(2), |
1220 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1221 | ret = IRQ_HANDLED; |
c9a9a268 | 1222 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1223 | } else |
1224 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1225 | } | |
1226 | ||
abd58f01 BW |
1227 | return ret; |
1228 | } | |
1229 | ||
676574df | 1230 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1231 | { |
1232 | switch (port) { | |
13cf5504 | 1233 | case PORT_B: |
676574df | 1234 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1235 | case PORT_C: |
676574df | 1236 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1237 | case PORT_D: |
676574df JN |
1238 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1239 | default: | |
1240 | return false; | |
13cf5504 DA |
1241 | } |
1242 | } | |
1243 | ||
676574df | 1244 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1245 | { |
1246 | switch (port) { | |
13cf5504 | 1247 | case PORT_B: |
676574df | 1248 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1249 | case PORT_C: |
676574df | 1250 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1251 | case PORT_D: |
676574df JN |
1252 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1253 | default: | |
1254 | return false; | |
13cf5504 DA |
1255 | } |
1256 | } | |
1257 | ||
676574df JN |
1258 | /* Get a bit mask of pins that have triggered, and which ones may be long. */ |
1259 | static void pch_get_hpd_pins(u32 *pin_mask, u32 *long_mask, | |
8c841e57 JN |
1260 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
1261 | const u32 hpd[HPD_NUM_PINS]) | |
676574df | 1262 | { |
8c841e57 | 1263 | enum port port; |
676574df JN |
1264 | int i; |
1265 | ||
1266 | *pin_mask = 0; | |
1267 | *long_mask = 0; | |
1268 | ||
1269 | if (!hotplug_trigger) | |
1270 | return; | |
1271 | ||
1272 | for_each_hpd_pin(i) { | |
8c841e57 JN |
1273 | if ((hpd[i] & hotplug_trigger) == 0) |
1274 | continue; | |
676574df | 1275 | |
8c841e57 JN |
1276 | *pin_mask |= BIT(i); |
1277 | ||
1278 | port = intel_hpd_pin_to_port(i); | |
1279 | if (pch_port_hotplug_long_detect(port, dig_hotplug_reg)) | |
1280 | *long_mask |= BIT(i); | |
676574df JN |
1281 | } |
1282 | ||
1283 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1284 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1285 | ||
1286 | } | |
1287 | ||
1288 | /* Get a bit mask of pins that have triggered, and which ones may be long. */ | |
1289 | static void i9xx_get_hpd_pins(u32 *pin_mask, u32 *long_mask, | |
1290 | u32 hotplug_trigger, const u32 hpd[HPD_NUM_PINS]) | |
1291 | { | |
8c841e57 | 1292 | enum port port; |
676574df JN |
1293 | int i; |
1294 | ||
1295 | *pin_mask = 0; | |
1296 | *long_mask = 0; | |
1297 | ||
1298 | if (!hotplug_trigger) | |
1299 | return; | |
1300 | ||
1301 | for_each_hpd_pin(i) { | |
8c841e57 JN |
1302 | if ((hpd[i] & hotplug_trigger) == 0) |
1303 | continue; | |
676574df | 1304 | |
8c841e57 JN |
1305 | *pin_mask |= BIT(i); |
1306 | ||
1307 | port = intel_hpd_pin_to_port(i); | |
1308 | if (i9xx_port_hotplug_long_detect(port, hotplug_trigger)) | |
1309 | *long_mask |= BIT(i); | |
676574df JN |
1310 | } |
1311 | ||
1312 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, pins 0x%08x\n", | |
1313 | hotplug_trigger, *pin_mask); | |
1314 | } | |
1315 | ||
515ac2bb DV |
1316 | static void gmbus_irq_handler(struct drm_device *dev) |
1317 | { | |
2d1013dd | 1318 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1319 | |
28c70f16 | 1320 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1321 | } |
1322 | ||
ce99c256 DV |
1323 | static void dp_aux_irq_handler(struct drm_device *dev) |
1324 | { | |
2d1013dd | 1325 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1326 | |
9ee32fea | 1327 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1328 | } |
1329 | ||
8bf1e9f1 | 1330 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1331 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1332 | uint32_t crc0, uint32_t crc1, | |
1333 | uint32_t crc2, uint32_t crc3, | |
1334 | uint32_t crc4) | |
8bf1e9f1 SH |
1335 | { |
1336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1337 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1338 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1339 | int head, tail; |
b2c88f5b | 1340 | |
d538bbdf DL |
1341 | spin_lock(&pipe_crc->lock); |
1342 | ||
0c912c79 | 1343 | if (!pipe_crc->entries) { |
d538bbdf | 1344 | spin_unlock(&pipe_crc->lock); |
34273620 | 1345 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1346 | return; |
1347 | } | |
1348 | ||
d538bbdf DL |
1349 | head = pipe_crc->head; |
1350 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1351 | |
1352 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1353 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1354 | DRM_ERROR("CRC buffer overflowing\n"); |
1355 | return; | |
1356 | } | |
1357 | ||
1358 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1359 | |
8bc5e955 | 1360 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1361 | entry->crc[0] = crc0; |
1362 | entry->crc[1] = crc1; | |
1363 | entry->crc[2] = crc2; | |
1364 | entry->crc[3] = crc3; | |
1365 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1366 | |
1367 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1368 | pipe_crc->head = head; |
1369 | ||
1370 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1371 | |
1372 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1373 | } |
277de95e DV |
1374 | #else |
1375 | static inline void | |
1376 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1377 | uint32_t crc0, uint32_t crc1, | |
1378 | uint32_t crc2, uint32_t crc3, | |
1379 | uint32_t crc4) {} | |
1380 | #endif | |
1381 | ||
eba94eb9 | 1382 | |
277de95e | 1383 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1384 | { |
1385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1386 | ||
277de95e DV |
1387 | display_pipe_crc_irq_handler(dev, pipe, |
1388 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1389 | 0, 0, 0, 0); | |
5a69b89f DV |
1390 | } |
1391 | ||
277de95e | 1392 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1393 | { |
1394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1395 | ||
277de95e DV |
1396 | display_pipe_crc_irq_handler(dev, pipe, |
1397 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1398 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1399 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1400 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1401 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1402 | } |
5b3a856b | 1403 | |
277de95e | 1404 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1405 | { |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1407 | uint32_t res1, res2; |
1408 | ||
1409 | if (INTEL_INFO(dev)->gen >= 3) | |
1410 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1411 | else | |
1412 | res1 = 0; | |
1413 | ||
1414 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1415 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1416 | else | |
1417 | res2 = 0; | |
5b3a856b | 1418 | |
277de95e DV |
1419 | display_pipe_crc_irq_handler(dev, pipe, |
1420 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1421 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1422 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1423 | res1, res2); | |
5b3a856b | 1424 | } |
8bf1e9f1 | 1425 | |
1403c0d4 PZ |
1426 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1427 | * IMR bits until the work is done. Other interrupts can be processed without | |
1428 | * the work queue. */ | |
1429 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1430 | { |
a6706b45 | 1431 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1432 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1433 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1434 | if (dev_priv->rps.interrupts_enabled) { |
1435 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1436 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1437 | } | |
59cdb63d | 1438 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1439 | } |
baf02a1f | 1440 | |
c9a9a268 ID |
1441 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1442 | return; | |
1443 | ||
1403c0d4 PZ |
1444 | if (HAS_VEBOX(dev_priv->dev)) { |
1445 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
74cdb337 | 1446 | notify_ring(&dev_priv->ring[VECS]); |
12638c57 | 1447 | |
aaecdf61 DV |
1448 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1449 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1450 | } |
baf02a1f BW |
1451 | } |
1452 | ||
8d7849db VS |
1453 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1454 | { | |
8d7849db VS |
1455 | if (!drm_handle_vblank(dev, pipe)) |
1456 | return false; | |
1457 | ||
8d7849db VS |
1458 | return true; |
1459 | } | |
1460 | ||
c1874ed7 ID |
1461 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1462 | { | |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1464 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1465 | int pipe; |
1466 | ||
58ead0d7 | 1467 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1468 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1469 | int reg; |
bbb5eebf | 1470 | u32 mask, iir_bit = 0; |
91d181dd | 1471 | |
bbb5eebf DV |
1472 | /* |
1473 | * PIPESTAT bits get signalled even when the interrupt is | |
1474 | * disabled with the mask bits, and some of the status bits do | |
1475 | * not generate interrupts at all (like the underrun bit). Hence | |
1476 | * we need to be careful that we only handle what we want to | |
1477 | * handle. | |
1478 | */ | |
0f239f4c DV |
1479 | |
1480 | /* fifo underruns are filterered in the underrun handler. */ | |
1481 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1482 | |
1483 | switch (pipe) { | |
1484 | case PIPE_A: | |
1485 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1486 | break; | |
1487 | case PIPE_B: | |
1488 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1489 | break; | |
3278f67f VS |
1490 | case PIPE_C: |
1491 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1492 | break; | |
bbb5eebf DV |
1493 | } |
1494 | if (iir & iir_bit) | |
1495 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1496 | ||
1497 | if (!mask) | |
91d181dd ID |
1498 | continue; |
1499 | ||
1500 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1501 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1502 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1503 | |
1504 | /* | |
1505 | * Clear the PIPE*STAT regs before the IIR | |
1506 | */ | |
91d181dd ID |
1507 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1508 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1509 | I915_WRITE(reg, pipe_stats[pipe]); |
1510 | } | |
58ead0d7 | 1511 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1512 | |
055e393f | 1513 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1514 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1515 | intel_pipe_handle_vblank(dev, pipe)) | |
1516 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1517 | |
579a9b0e | 1518 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1519 | intel_prepare_page_flip(dev, pipe); |
1520 | intel_finish_page_flip(dev, pipe); | |
1521 | } | |
1522 | ||
1523 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1524 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1525 | ||
1f7247c0 DV |
1526 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1527 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1528 | } |
1529 | ||
1530 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1531 | gmbus_irq_handler(dev); | |
1532 | } | |
1533 | ||
16c6c56b VS |
1534 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1535 | { | |
1536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1537 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
676574df | 1538 | u32 pin_mask, long_mask; |
16c6c56b | 1539 | |
0d2e4297 JN |
1540 | if (!hotplug_status) |
1541 | return; | |
16c6c56b | 1542 | |
0d2e4297 JN |
1543 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1544 | /* | |
1545 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1546 | * may miss hotplug events. | |
1547 | */ | |
1548 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1549 | |
0d2e4297 JN |
1550 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
1551 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1552 | |
676574df JN |
1553 | i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_g4x); |
1554 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
369712e8 JN |
1555 | |
1556 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1557 | dp_aux_irq_handler(dev); | |
0d2e4297 JN |
1558 | } else { |
1559 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1560 | |
676574df JN |
1561 | i9xx_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, hpd_status_i915); |
1562 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
3ff60f89 | 1563 | } |
16c6c56b VS |
1564 | } |
1565 | ||
ff1f525e | 1566 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1567 | { |
45a83f84 | 1568 | struct drm_device *dev = arg; |
2d1013dd | 1569 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1570 | u32 iir, gt_iir, pm_iir; |
1571 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1572 | |
2dd2a883 ID |
1573 | if (!intel_irqs_enabled(dev_priv)) |
1574 | return IRQ_NONE; | |
1575 | ||
7e231dbe | 1576 | while (true) { |
3ff60f89 OM |
1577 | /* Find, clear, then process each source of interrupt */ |
1578 | ||
7e231dbe | 1579 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1580 | if (gt_iir) |
1581 | I915_WRITE(GTIIR, gt_iir); | |
1582 | ||
7e231dbe | 1583 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1584 | if (pm_iir) |
1585 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1586 | ||
1587 | iir = I915_READ(VLV_IIR); | |
1588 | if (iir) { | |
1589 | /* Consume port before clearing IIR or we'll miss events */ | |
1590 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1591 | i9xx_hpd_irq_handler(dev); | |
1592 | I915_WRITE(VLV_IIR, iir); | |
1593 | } | |
7e231dbe JB |
1594 | |
1595 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1596 | goto out; | |
1597 | ||
1598 | ret = IRQ_HANDLED; | |
1599 | ||
3ff60f89 OM |
1600 | if (gt_iir) |
1601 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1602 | if (pm_iir) |
d0ecd7e2 | 1603 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1604 | /* Call regardless, as some status bits might not be |
1605 | * signalled in iir */ | |
1606 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1607 | } |
1608 | ||
1609 | out: | |
1610 | return ret; | |
1611 | } | |
1612 | ||
43f328d7 VS |
1613 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1614 | { | |
45a83f84 | 1615 | struct drm_device *dev = arg; |
43f328d7 VS |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
1617 | u32 master_ctl, iir; | |
1618 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1619 | |
2dd2a883 ID |
1620 | if (!intel_irqs_enabled(dev_priv)) |
1621 | return IRQ_NONE; | |
1622 | ||
8e5fd599 VS |
1623 | for (;;) { |
1624 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1625 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1626 | |
8e5fd599 VS |
1627 | if (master_ctl == 0 && iir == 0) |
1628 | break; | |
43f328d7 | 1629 | |
27b6c122 OM |
1630 | ret = IRQ_HANDLED; |
1631 | ||
8e5fd599 | 1632 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1633 | |
27b6c122 | 1634 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1635 | |
27b6c122 OM |
1636 | if (iir) { |
1637 | /* Consume port before clearing IIR or we'll miss events */ | |
1638 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1639 | i9xx_hpd_irq_handler(dev); | |
1640 | I915_WRITE(VLV_IIR, iir); | |
1641 | } | |
43f328d7 | 1642 | |
74cdb337 | 1643 | gen8_gt_irq_handler(dev_priv, master_ctl); |
43f328d7 | 1644 | |
27b6c122 OM |
1645 | /* Call regardless, as some status bits might not be |
1646 | * signalled in iir */ | |
1647 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1648 | |
8e5fd599 VS |
1649 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1650 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1651 | } |
3278f67f | 1652 | |
43f328d7 VS |
1653 | return ret; |
1654 | } | |
1655 | ||
23e81d69 | 1656 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1657 | { |
2d1013dd | 1658 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1659 | int pipe; |
b543fb04 | 1660 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1661 | u32 dig_hotplug_reg; |
676574df | 1662 | u32 pin_mask, long_mask; |
13cf5504 DA |
1663 | |
1664 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1665 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
776ad806 | 1666 | |
676574df JN |
1667 | pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_ibx); |
1668 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
91d131d2 | 1669 | |
cfc33bf7 VS |
1670 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1671 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1672 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1673 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1674 | port_name(port)); |
1675 | } | |
776ad806 | 1676 | |
ce99c256 DV |
1677 | if (pch_iir & SDE_AUX_MASK) |
1678 | dp_aux_irq_handler(dev); | |
1679 | ||
776ad806 | 1680 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1681 | gmbus_irq_handler(dev); |
776ad806 JB |
1682 | |
1683 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1684 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1685 | ||
1686 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1687 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1688 | ||
1689 | if (pch_iir & SDE_POISON) | |
1690 | DRM_ERROR("PCH poison interrupt\n"); | |
1691 | ||
9db4a9c7 | 1692 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1693 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1694 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1695 | pipe_name(pipe), | |
1696 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1697 | |
1698 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1699 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1700 | ||
1701 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1702 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1703 | ||
776ad806 | 1704 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1705 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1706 | |
1707 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1708 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1709 | } |
1710 | ||
1711 | static void ivb_err_int_handler(struct drm_device *dev) | |
1712 | { | |
1713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1714 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1715 | enum pipe pipe; |
8664281b | 1716 | |
de032bf4 PZ |
1717 | if (err_int & ERR_INT_POISON) |
1718 | DRM_ERROR("Poison interrupt\n"); | |
1719 | ||
055e393f | 1720 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1721 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1722 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1723 | |
5a69b89f DV |
1724 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1725 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1726 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1727 | else |
277de95e | 1728 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1729 | } |
1730 | } | |
8bf1e9f1 | 1731 | |
8664281b PZ |
1732 | I915_WRITE(GEN7_ERR_INT, err_int); |
1733 | } | |
1734 | ||
1735 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1736 | { | |
1737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1738 | u32 serr_int = I915_READ(SERR_INT); | |
1739 | ||
de032bf4 PZ |
1740 | if (serr_int & SERR_INT_POISON) |
1741 | DRM_ERROR("PCH poison interrupt\n"); | |
1742 | ||
8664281b | 1743 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1744 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1745 | |
1746 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1747 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1748 | |
1749 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1750 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1751 | |
1752 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1753 | } |
1754 | ||
23e81d69 AJ |
1755 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1756 | { | |
2d1013dd | 1757 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1758 | int pipe; |
b543fb04 | 1759 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 1760 | u32 dig_hotplug_reg; |
676574df | 1761 | u32 pin_mask, long_mask; |
13cf5504 DA |
1762 | |
1763 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1764 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
23e81d69 | 1765 | |
676574df JN |
1766 | pch_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, dig_hotplug_reg, hpd_cpt); |
1767 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
91d131d2 | 1768 | |
cfc33bf7 VS |
1769 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1770 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1771 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1772 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1773 | port_name(port)); | |
1774 | } | |
23e81d69 AJ |
1775 | |
1776 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1777 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1778 | |
1779 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1780 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1781 | |
1782 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1783 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1784 | ||
1785 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1786 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1787 | ||
1788 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1789 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1790 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1791 | pipe_name(pipe), | |
1792 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1793 | |
1794 | if (pch_iir & SDE_ERROR_CPT) | |
1795 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1796 | } |
1797 | ||
c008bc6e PZ |
1798 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1799 | { | |
1800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1801 | enum pipe pipe; |
c008bc6e PZ |
1802 | |
1803 | if (de_iir & DE_AUX_CHANNEL_A) | |
1804 | dp_aux_irq_handler(dev); | |
1805 | ||
1806 | if (de_iir & DE_GSE) | |
1807 | intel_opregion_asle_intr(dev); | |
1808 | ||
c008bc6e PZ |
1809 | if (de_iir & DE_POISON) |
1810 | DRM_ERROR("Poison interrupt\n"); | |
1811 | ||
055e393f | 1812 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1813 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
1814 | intel_pipe_handle_vblank(dev, pipe)) | |
1815 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 1816 | |
40da17c2 | 1817 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 1818 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 1819 | |
40da17c2 DV |
1820 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1821 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1822 | |
40da17c2 DV |
1823 | /* plane/pipes map 1:1 on ilk+ */ |
1824 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1825 | intel_prepare_page_flip(dev, pipe); | |
1826 | intel_finish_page_flip_plane(dev, pipe); | |
1827 | } | |
c008bc6e PZ |
1828 | } |
1829 | ||
1830 | /* check event from PCH */ | |
1831 | if (de_iir & DE_PCH_EVENT) { | |
1832 | u32 pch_iir = I915_READ(SDEIIR); | |
1833 | ||
1834 | if (HAS_PCH_CPT(dev)) | |
1835 | cpt_irq_handler(dev, pch_iir); | |
1836 | else | |
1837 | ibx_irq_handler(dev, pch_iir); | |
1838 | ||
1839 | /* should clear PCH hotplug event before clear CPU irq */ | |
1840 | I915_WRITE(SDEIIR, pch_iir); | |
1841 | } | |
1842 | ||
1843 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1844 | ironlake_rps_change_irq_handler(dev); | |
1845 | } | |
1846 | ||
9719fb98 PZ |
1847 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1848 | { | |
1849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 1850 | enum pipe pipe; |
9719fb98 PZ |
1851 | |
1852 | if (de_iir & DE_ERR_INT_IVB) | |
1853 | ivb_err_int_handler(dev); | |
1854 | ||
1855 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1856 | dp_aux_irq_handler(dev); | |
1857 | ||
1858 | if (de_iir & DE_GSE_IVB) | |
1859 | intel_opregion_asle_intr(dev); | |
1860 | ||
055e393f | 1861 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1862 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
1863 | intel_pipe_handle_vblank(dev, pipe)) | |
1864 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
1865 | |
1866 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
1867 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
1868 | intel_prepare_page_flip(dev, pipe); | |
1869 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
1870 | } |
1871 | } | |
1872 | ||
1873 | /* check event from PCH */ | |
1874 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1875 | u32 pch_iir = I915_READ(SDEIIR); | |
1876 | ||
1877 | cpt_irq_handler(dev, pch_iir); | |
1878 | ||
1879 | /* clear PCH hotplug event before clear CPU irq */ | |
1880 | I915_WRITE(SDEIIR, pch_iir); | |
1881 | } | |
1882 | } | |
1883 | ||
72c90f62 OM |
1884 | /* |
1885 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
1886 | * 1 - Disable Master Interrupt Control. | |
1887 | * 2 - Find the source(s) of the interrupt. | |
1888 | * 3 - Clear the Interrupt Identity bits (IIR). | |
1889 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
1890 | * 5 - Re-enable Master Interrupt Control. | |
1891 | */ | |
f1af8fc1 | 1892 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 1893 | { |
45a83f84 | 1894 | struct drm_device *dev = arg; |
2d1013dd | 1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 1896 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1897 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 1898 | |
2dd2a883 ID |
1899 | if (!intel_irqs_enabled(dev_priv)) |
1900 | return IRQ_NONE; | |
1901 | ||
8664281b PZ |
1902 | /* We get interrupts on unclaimed registers, so check for this before we |
1903 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1904 | intel_uncore_check_errors(dev); |
8664281b | 1905 | |
b1f14ad0 JB |
1906 | /* disable master interrupt before clearing iir */ |
1907 | de_ier = I915_READ(DEIER); | |
1908 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1909 | POSTING_READ(DEIER); |
b1f14ad0 | 1910 | |
44498aea PZ |
1911 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1912 | * interrupts will will be stored on its back queue, and then we'll be | |
1913 | * able to process them after we restore SDEIER (as soon as we restore | |
1914 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1915 | * due to its back queue). */ | |
ab5c608b BW |
1916 | if (!HAS_PCH_NOP(dev)) { |
1917 | sde_ier = I915_READ(SDEIER); | |
1918 | I915_WRITE(SDEIER, 0); | |
1919 | POSTING_READ(SDEIER); | |
1920 | } | |
44498aea | 1921 | |
72c90f62 OM |
1922 | /* Find, clear, then process each source of interrupt */ |
1923 | ||
b1f14ad0 | 1924 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1925 | if (gt_iir) { |
72c90f62 OM |
1926 | I915_WRITE(GTIIR, gt_iir); |
1927 | ret = IRQ_HANDLED; | |
d8fc8a47 | 1928 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1929 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1930 | else |
1931 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
1932 | } |
1933 | ||
0e43406b CW |
1934 | de_iir = I915_READ(DEIIR); |
1935 | if (de_iir) { | |
72c90f62 OM |
1936 | I915_WRITE(DEIIR, de_iir); |
1937 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
1938 | if (INTEL_INFO(dev)->gen >= 7) |
1939 | ivb_display_irq_handler(dev, de_iir); | |
1940 | else | |
1941 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
1942 | } |
1943 | ||
f1af8fc1 PZ |
1944 | if (INTEL_INFO(dev)->gen >= 6) { |
1945 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1946 | if (pm_iir) { | |
f1af8fc1 PZ |
1947 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1948 | ret = IRQ_HANDLED; | |
72c90f62 | 1949 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 1950 | } |
0e43406b | 1951 | } |
b1f14ad0 | 1952 | |
b1f14ad0 JB |
1953 | I915_WRITE(DEIER, de_ier); |
1954 | POSTING_READ(DEIER); | |
ab5c608b BW |
1955 | if (!HAS_PCH_NOP(dev)) { |
1956 | I915_WRITE(SDEIER, sde_ier); | |
1957 | POSTING_READ(SDEIER); | |
1958 | } | |
b1f14ad0 JB |
1959 | |
1960 | return ret; | |
1961 | } | |
1962 | ||
d04a492d SS |
1963 | static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status) |
1964 | { | |
1965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
676574df JN |
1966 | u32 hp_control, hp_trigger; |
1967 | u32 pin_mask, long_mask; | |
d04a492d SS |
1968 | |
1969 | /* Get the status */ | |
1970 | hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK; | |
1971 | hp_control = I915_READ(BXT_HOTPLUG_CTL); | |
1972 | ||
1973 | /* Hotplug not enabled ? */ | |
1974 | if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) { | |
1975 | DRM_ERROR("Interrupt when HPD disabled\n"); | |
1976 | return; | |
1977 | } | |
1978 | ||
475c2e3b JN |
1979 | /* Clear sticky bits in hpd status */ |
1980 | I915_WRITE(BXT_HOTPLUG_CTL, hp_control); | |
d04a492d | 1981 | |
676574df JN |
1982 | pch_get_hpd_pins(&pin_mask, &long_mask, hp_trigger, hp_control, hpd_bxt); |
1983 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
d04a492d SS |
1984 | } |
1985 | ||
abd58f01 BW |
1986 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1987 | { | |
1988 | struct drm_device *dev = arg; | |
1989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1990 | u32 master_ctl; | |
1991 | irqreturn_t ret = IRQ_NONE; | |
1992 | uint32_t tmp = 0; | |
c42664cc | 1993 | enum pipe pipe; |
88e04703 JB |
1994 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
1995 | ||
2dd2a883 ID |
1996 | if (!intel_irqs_enabled(dev_priv)) |
1997 | return IRQ_NONE; | |
1998 | ||
88e04703 JB |
1999 | if (IS_GEN9(dev)) |
2000 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | | |
2001 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2002 | |
cb0d205e | 2003 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
abd58f01 BW |
2004 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
2005 | if (!master_ctl) | |
2006 | return IRQ_NONE; | |
2007 | ||
cb0d205e | 2008 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
abd58f01 | 2009 | |
38cc46d7 OM |
2010 | /* Find, clear, then process each source of interrupt */ |
2011 | ||
74cdb337 | 2012 | ret = gen8_gt_irq_handler(dev_priv, master_ctl); |
abd58f01 BW |
2013 | |
2014 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2015 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2016 | if (tmp) { |
2017 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2018 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2019 | if (tmp & GEN8_DE_MISC_GSE) |
2020 | intel_opregion_asle_intr(dev); | |
2021 | else | |
2022 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2023 | } |
38cc46d7 OM |
2024 | else |
2025 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2026 | } |
2027 | ||
6d766f02 DV |
2028 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2029 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 | 2030 | if (tmp) { |
d04a492d SS |
2031 | bool found = false; |
2032 | ||
6d766f02 DV |
2033 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
2034 | ret = IRQ_HANDLED; | |
88e04703 | 2035 | |
d04a492d | 2036 | if (tmp & aux_mask) { |
38cc46d7 | 2037 | dp_aux_irq_handler(dev); |
d04a492d SS |
2038 | found = true; |
2039 | } | |
2040 | ||
2041 | if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) { | |
2042 | bxt_hpd_handler(dev, tmp); | |
2043 | found = true; | |
2044 | } | |
2045 | ||
9e63743e SS |
2046 | if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) { |
2047 | gmbus_irq_handler(dev); | |
2048 | found = true; | |
2049 | } | |
2050 | ||
d04a492d | 2051 | if (!found) |
38cc46d7 | 2052 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2053 | } |
38cc46d7 OM |
2054 | else |
2055 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2056 | } |
2057 | ||
055e393f | 2058 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2059 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2060 | |
c42664cc DV |
2061 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2062 | continue; | |
abd58f01 | 2063 | |
c42664cc | 2064 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2065 | if (pipe_iir) { |
2066 | ret = IRQ_HANDLED; | |
2067 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2068 | |
d6bbafa1 CW |
2069 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2070 | intel_pipe_handle_vblank(dev, pipe)) | |
2071 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2072 | |
770de83d DL |
2073 | if (IS_GEN9(dev)) |
2074 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; | |
2075 | else | |
2076 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2077 | ||
2078 | if (flip_done) { | |
38cc46d7 OM |
2079 | intel_prepare_page_flip(dev, pipe); |
2080 | intel_finish_page_flip_plane(dev, pipe); | |
2081 | } | |
2082 | ||
2083 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2084 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2085 | ||
1f7247c0 DV |
2086 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2087 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2088 | pipe); | |
38cc46d7 | 2089 | |
770de83d DL |
2090 | |
2091 | if (IS_GEN9(dev)) | |
2092 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2093 | else | |
2094 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2095 | ||
2096 | if (fault_errors) | |
38cc46d7 OM |
2097 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2098 | pipe_name(pipe), | |
2099 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2100 | } else |
abd58f01 BW |
2101 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2102 | } | |
2103 | ||
266ea3d9 SS |
2104 | if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && |
2105 | master_ctl & GEN8_DE_PCH_IRQ) { | |
92d03a80 DV |
2106 | /* |
2107 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2108 | * scheme also closed the SDE interrupt handling race we've seen | |
2109 | * on older pch-split platforms. But this needs testing. | |
2110 | */ | |
2111 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2112 | if (pch_iir) { |
2113 | I915_WRITE(SDEIIR, pch_iir); | |
2114 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2115 | cpt_irq_handler(dev, pch_iir); |
2116 | } else | |
2117 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2118 | ||
92d03a80 DV |
2119 | } |
2120 | ||
cb0d205e CW |
2121 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2122 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 BW |
2123 | |
2124 | return ret; | |
2125 | } | |
2126 | ||
17e1df07 DV |
2127 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2128 | bool reset_completed) | |
2129 | { | |
a4872ba6 | 2130 | struct intel_engine_cs *ring; |
17e1df07 DV |
2131 | int i; |
2132 | ||
2133 | /* | |
2134 | * Notify all waiters for GPU completion events that reset state has | |
2135 | * been changed, and that they need to restart their wait after | |
2136 | * checking for potential errors (and bail out to drop locks if there is | |
2137 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2138 | */ | |
2139 | ||
2140 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2141 | for_each_ring(ring, dev_priv, i) | |
2142 | wake_up_all(&ring->irq_queue); | |
2143 | ||
2144 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2145 | wake_up_all(&dev_priv->pending_flip_queue); | |
2146 | ||
2147 | /* | |
2148 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2149 | * reset state is cleared. | |
2150 | */ | |
2151 | if (reset_completed) | |
2152 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2153 | } | |
2154 | ||
8a905236 | 2155 | /** |
b8d24a06 | 2156 | * i915_reset_and_wakeup - do process context error handling work |
8a905236 JB |
2157 | * |
2158 | * Fire an error uevent so userspace can see that a hang or error | |
2159 | * was detected. | |
2160 | */ | |
b8d24a06 | 2161 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2162 | { |
b8d24a06 MK |
2163 | struct drm_i915_private *dev_priv = to_i915(dev); |
2164 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2165 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2166 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2167 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2168 | int ret; |
8a905236 | 2169 | |
5bdebb18 | 2170 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2171 | |
7db0ba24 DV |
2172 | /* |
2173 | * Note that there's only one work item which does gpu resets, so we | |
2174 | * need not worry about concurrent gpu resets potentially incrementing | |
2175 | * error->reset_counter twice. We only need to take care of another | |
2176 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2177 | * quick check for that is good enough: schedule_work ensures the | |
2178 | * correct ordering between hang detection and this work item, and since | |
2179 | * the reset in-progress bit is only ever set by code outside of this | |
2180 | * work we don't need to worry about any other races. | |
2181 | */ | |
2182 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2183 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2184 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2185 | reset_event); |
1f83fee0 | 2186 | |
f454c694 ID |
2187 | /* |
2188 | * In most cases it's guaranteed that we get here with an RPM | |
2189 | * reference held, for example because there is a pending GPU | |
2190 | * request that won't finish until the reset is done. This | |
2191 | * isn't the case at least when we get here by doing a | |
2192 | * simulated reset via debugs, so get an RPM reference. | |
2193 | */ | |
2194 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2195 | |
2196 | intel_prepare_reset(dev); | |
2197 | ||
17e1df07 DV |
2198 | /* |
2199 | * All state reset _must_ be completed before we update the | |
2200 | * reset counter, for otherwise waiters might miss the reset | |
2201 | * pending state and not properly drop locks, resulting in | |
2202 | * deadlocks with the reset work. | |
2203 | */ | |
f69061be DV |
2204 | ret = i915_reset(dev); |
2205 | ||
7514747d | 2206 | intel_finish_reset(dev); |
17e1df07 | 2207 | |
f454c694 ID |
2208 | intel_runtime_pm_put(dev_priv); |
2209 | ||
f69061be DV |
2210 | if (ret == 0) { |
2211 | /* | |
2212 | * After all the gem state is reset, increment the reset | |
2213 | * counter and wake up everyone waiting for the reset to | |
2214 | * complete. | |
2215 | * | |
2216 | * Since unlock operations are a one-sided barrier only, | |
2217 | * we need to insert a barrier here to order any seqno | |
2218 | * updates before | |
2219 | * the counter increment. | |
2220 | */ | |
4e857c58 | 2221 | smp_mb__before_atomic(); |
f69061be DV |
2222 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2223 | ||
5bdebb18 | 2224 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2225 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2226 | } else { |
2ac0f450 | 2227 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2228 | } |
1f83fee0 | 2229 | |
17e1df07 DV |
2230 | /* |
2231 | * Note: The wake_up also serves as a memory barrier so that | |
2232 | * waiters see the update value of the reset counter atomic_t. | |
2233 | */ | |
2234 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2235 | } |
8a905236 JB |
2236 | } |
2237 | ||
35aed2e6 | 2238 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2239 | { |
2240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2241 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2242 | u32 eir = I915_READ(EIR); |
050ee91f | 2243 | int pipe, i; |
8a905236 | 2244 | |
35aed2e6 CW |
2245 | if (!eir) |
2246 | return; | |
8a905236 | 2247 | |
a70491cc | 2248 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2249 | |
bd9854f9 BW |
2250 | i915_get_extra_instdone(dev, instdone); |
2251 | ||
8a905236 JB |
2252 | if (IS_G4X(dev)) { |
2253 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2254 | u32 ipeir = I915_READ(IPEIR_I965); | |
2255 | ||
a70491cc JP |
2256 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2257 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2258 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2259 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2260 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2261 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2262 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2263 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2264 | } |
2265 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2266 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2267 | pr_err("page table error\n"); |
2268 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2269 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2270 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2271 | } |
2272 | } | |
2273 | ||
a6c45cf0 | 2274 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2275 | if (eir & I915_ERROR_PAGE_TABLE) { |
2276 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2277 | pr_err("page table error\n"); |
2278 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2279 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2280 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2281 | } |
2282 | } | |
2283 | ||
2284 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2285 | pr_err("memory refresh error:\n"); |
055e393f | 2286 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2287 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2288 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2289 | /* pipestat has already been acked */ |
2290 | } | |
2291 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2292 | pr_err("instruction error\n"); |
2293 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2294 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2295 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2296 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2297 | u32 ipeir = I915_READ(IPEIR); |
2298 | ||
a70491cc JP |
2299 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2300 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2301 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2302 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2303 | POSTING_READ(IPEIR); |
8a905236 JB |
2304 | } else { |
2305 | u32 ipeir = I915_READ(IPEIR_I965); | |
2306 | ||
a70491cc JP |
2307 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2308 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2309 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2310 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2311 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2312 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2313 | } |
2314 | } | |
2315 | ||
2316 | I915_WRITE(EIR, eir); | |
3143a2bf | 2317 | POSTING_READ(EIR); |
8a905236 JB |
2318 | eir = I915_READ(EIR); |
2319 | if (eir) { | |
2320 | /* | |
2321 | * some errors might have become stuck, | |
2322 | * mask them. | |
2323 | */ | |
2324 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2325 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2326 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2327 | } | |
35aed2e6 CW |
2328 | } |
2329 | ||
2330 | /** | |
b8d24a06 | 2331 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2332 | * @dev: drm device |
2333 | * | |
b8d24a06 | 2334 | * Do some basic checking of regsiter state at error time and |
35aed2e6 CW |
2335 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2336 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2337 | * so userspace knows something bad happened (should trigger collection | |
2338 | * of a ring dump etc.). | |
2339 | */ | |
58174462 MK |
2340 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2341 | const char *fmt, ...) | |
35aed2e6 CW |
2342 | { |
2343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2344 | va_list args; |
2345 | char error_msg[80]; | |
35aed2e6 | 2346 | |
58174462 MK |
2347 | va_start(args, fmt); |
2348 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2349 | va_end(args); | |
2350 | ||
2351 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2352 | i915_report_and_clear_eir(dev); |
8a905236 | 2353 | |
ba1234d1 | 2354 | if (wedged) { |
f69061be DV |
2355 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2356 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2357 | |
11ed50ec | 2358 | /* |
b8d24a06 MK |
2359 | * Wakeup waiting processes so that the reset function |
2360 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2361 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2362 | * processes will see a reset in progress and back off, |
2363 | * releasing their locks and then wait for the reset completion. | |
2364 | * We must do this for _all_ gpu waiters that might hold locks | |
2365 | * that the reset work needs to acquire. | |
2366 | * | |
2367 | * Note: The wake_up serves as the required memory barrier to | |
2368 | * ensure that the waiters see the updated value of the reset | |
2369 | * counter atomic_t. | |
11ed50ec | 2370 | */ |
17e1df07 | 2371 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2372 | } |
2373 | ||
b8d24a06 | 2374 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2375 | } |
2376 | ||
42f52ef8 KP |
2377 | /* Called from drm generic code, passed 'crtc' which |
2378 | * we use as a pipe index | |
2379 | */ | |
f71d4af4 | 2380 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2381 | { |
2d1013dd | 2382 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2383 | unsigned long irqflags; |
71e0ffa5 | 2384 | |
1ec14ad3 | 2385 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2386 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2387 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2388 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2389 | else |
7c463586 | 2390 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2391 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2392 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2393 | |
0a3e67a4 JB |
2394 | return 0; |
2395 | } | |
2396 | ||
f71d4af4 | 2397 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2398 | { |
2d1013dd | 2399 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2400 | unsigned long irqflags; |
b518421f | 2401 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2402 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2403 | |
f796cf8f | 2404 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2405 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2406 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
7e231dbe JB |
2411 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2412 | { | |
2d1013dd | 2413 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2414 | unsigned long irqflags; |
7e231dbe | 2415 | |
7e231dbe | 2416 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2417 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2418 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2419 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2420 | ||
2421 | return 0; | |
2422 | } | |
2423 | ||
abd58f01 BW |
2424 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2425 | { | |
2426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2427 | unsigned long irqflags; | |
abd58f01 | 2428 | |
abd58f01 | 2429 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2430 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2431 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2432 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2433 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2434 | return 0; | |
2435 | } | |
2436 | ||
42f52ef8 KP |
2437 | /* Called from drm generic code, passed 'crtc' which |
2438 | * we use as a pipe index | |
2439 | */ | |
f71d4af4 | 2440 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2441 | { |
2d1013dd | 2442 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2443 | unsigned long irqflags; |
0a3e67a4 | 2444 | |
1ec14ad3 | 2445 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2446 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2447 | PIPE_VBLANK_INTERRUPT_STATUS | |
2448 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2449 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2450 | } | |
2451 | ||
f71d4af4 | 2452 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2453 | { |
2d1013dd | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2455 | unsigned long irqflags; |
b518421f | 2456 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2457 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2458 | |
2459 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2460 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2461 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2462 | } | |
2463 | ||
7e231dbe JB |
2464 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2465 | { | |
2d1013dd | 2466 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2467 | unsigned long irqflags; |
7e231dbe JB |
2468 | |
2469 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2470 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2471 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2472 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2473 | } | |
2474 | ||
abd58f01 BW |
2475 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2476 | { | |
2477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2478 | unsigned long irqflags; | |
abd58f01 | 2479 | |
abd58f01 | 2480 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2481 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2482 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2483 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2484 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2485 | } | |
2486 | ||
44cdd6d2 JH |
2487 | static struct drm_i915_gem_request * |
2488 | ring_last_request(struct intel_engine_cs *ring) | |
852835f3 | 2489 | { |
893eead0 | 2490 | return list_entry(ring->request_list.prev, |
44cdd6d2 | 2491 | struct drm_i915_gem_request, list); |
893eead0 CW |
2492 | } |
2493 | ||
9107e9d2 | 2494 | static bool |
44cdd6d2 | 2495 | ring_idle(struct intel_engine_cs *ring) |
9107e9d2 CW |
2496 | { |
2497 | return (list_empty(&ring->request_list) || | |
1b5a433a | 2498 | i915_gem_request_completed(ring_last_request(ring), false)); |
f65d9421 BG |
2499 | } |
2500 | ||
a028c4b0 DV |
2501 | static bool |
2502 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2503 | { | |
2504 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2505 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2506 | } else { |
2507 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2508 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2509 | MI_SEMAPHORE_REGISTER); | |
2510 | } | |
2511 | } | |
2512 | ||
a4872ba6 | 2513 | static struct intel_engine_cs * |
a6cdb93a | 2514 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2515 | { |
2516 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2517 | struct intel_engine_cs *signaller; |
921d42ea DV |
2518 | int i; |
2519 | ||
2520 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2521 | for_each_ring(signaller, dev_priv, i) { |
2522 | if (ring == signaller) | |
2523 | continue; | |
2524 | ||
2525 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2526 | return signaller; | |
2527 | } | |
921d42ea DV |
2528 | } else { |
2529 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2530 | ||
2531 | for_each_ring(signaller, dev_priv, i) { | |
2532 | if(ring == signaller) | |
2533 | continue; | |
2534 | ||
ebc348b2 | 2535 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2536 | return signaller; |
2537 | } | |
2538 | } | |
2539 | ||
a6cdb93a RV |
2540 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2541 | ring->id, ipehr, offset); | |
921d42ea DV |
2542 | |
2543 | return NULL; | |
2544 | } | |
2545 | ||
a4872ba6 OM |
2546 | static struct intel_engine_cs * |
2547 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2548 | { |
2549 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2550 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2551 | u64 offset = 0; |
2552 | int i, backwards; | |
a24a11e6 CW |
2553 | |
2554 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2555 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2556 | return NULL; |
a24a11e6 | 2557 | |
88fe429d DV |
2558 | /* |
2559 | * HEAD is likely pointing to the dword after the actual command, | |
2560 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2561 | * or 4 dwords depending on the semaphore wait command size. |
2562 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2563 | * point at at batch, and semaphores are always emitted into the |
2564 | * ringbuffer itself. | |
a24a11e6 | 2565 | */ |
88fe429d | 2566 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2567 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2568 | |
a6cdb93a | 2569 | for (i = backwards; i; --i) { |
88fe429d DV |
2570 | /* |
2571 | * Be paranoid and presume the hw has gone off into the wild - | |
2572 | * our ring is smaller than what the hardware (and hence | |
2573 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2574 | */ | |
ee1b1e5e | 2575 | head &= ring->buffer->size - 1; |
88fe429d DV |
2576 | |
2577 | /* This here seems to blow up */ | |
ee1b1e5e | 2578 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2579 | if (cmd == ipehr) |
2580 | break; | |
2581 | ||
88fe429d DV |
2582 | head -= 4; |
2583 | } | |
a24a11e6 | 2584 | |
88fe429d DV |
2585 | if (!i) |
2586 | return NULL; | |
a24a11e6 | 2587 | |
ee1b1e5e | 2588 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2589 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2590 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2591 | offset <<= 32; | |
2592 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2593 | } | |
2594 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2595 | } |
2596 | ||
a4872ba6 | 2597 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2598 | { |
2599 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2600 | struct intel_engine_cs *signaller; |
a0d036b0 | 2601 | u32 seqno; |
6274f212 | 2602 | |
4be17381 | 2603 | ring->hangcheck.deadlock++; |
6274f212 CW |
2604 | |
2605 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2606 | if (signaller == NULL) |
2607 | return -1; | |
2608 | ||
2609 | /* Prevent pathological recursion due to driver bugs */ | |
2610 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2611 | return -1; |
2612 | ||
4be17381 CW |
2613 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2614 | return 1; | |
2615 | ||
a0d036b0 CW |
2616 | /* cursory check for an unkickable deadlock */ |
2617 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2618 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2619 | return -1; |
2620 | ||
2621 | return 0; | |
6274f212 CW |
2622 | } |
2623 | ||
2624 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2625 | { | |
a4872ba6 | 2626 | struct intel_engine_cs *ring; |
6274f212 CW |
2627 | int i; |
2628 | ||
2629 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2630 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2631 | } |
2632 | ||
ad8beaea | 2633 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2634 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2635 | { |
2636 | struct drm_device *dev = ring->dev; | |
2637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2638 | u32 tmp; |
2639 | ||
f260fe7b MK |
2640 | if (acthd != ring->hangcheck.acthd) { |
2641 | if (acthd > ring->hangcheck.max_acthd) { | |
2642 | ring->hangcheck.max_acthd = acthd; | |
2643 | return HANGCHECK_ACTIVE; | |
2644 | } | |
2645 | ||
2646 | return HANGCHECK_ACTIVE_LOOP; | |
2647 | } | |
6274f212 | 2648 | |
9107e9d2 | 2649 | if (IS_GEN2(dev)) |
f2f4d82f | 2650 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2651 | |
2652 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2653 | * If so we can simply poke the RB_WAIT bit | |
2654 | * and break the hang. This should work on | |
2655 | * all but the second generation chipsets. | |
2656 | */ | |
2657 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2658 | if (tmp & RING_WAIT) { |
58174462 MK |
2659 | i915_handle_error(dev, false, |
2660 | "Kicking stuck wait on %s", | |
2661 | ring->name); | |
1ec14ad3 | 2662 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2663 | return HANGCHECK_KICK; |
6274f212 CW |
2664 | } |
2665 | ||
2666 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2667 | switch (semaphore_passed(ring)) { | |
2668 | default: | |
f2f4d82f | 2669 | return HANGCHECK_HUNG; |
6274f212 | 2670 | case 1: |
58174462 MK |
2671 | i915_handle_error(dev, false, |
2672 | "Kicking stuck semaphore on %s", | |
2673 | ring->name); | |
6274f212 | 2674 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2675 | return HANGCHECK_KICK; |
6274f212 | 2676 | case 0: |
f2f4d82f | 2677 | return HANGCHECK_WAIT; |
6274f212 | 2678 | } |
9107e9d2 | 2679 | } |
ed5cbb03 | 2680 | |
f2f4d82f | 2681 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2682 | } |
2683 | ||
737b1506 | 2684 | /* |
f65d9421 | 2685 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2686 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2687 | * if there are no progress, hangcheck score for that ring is increased. | |
2688 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2689 | * we kick the ring. If we see no progress on three subsequent calls | |
2690 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2691 | */ |
737b1506 | 2692 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2693 | { |
737b1506 CW |
2694 | struct drm_i915_private *dev_priv = |
2695 | container_of(work, typeof(*dev_priv), | |
2696 | gpu_error.hangcheck_work.work); | |
2697 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2698 | struct intel_engine_cs *ring; |
b4519513 | 2699 | int i; |
05407ff8 | 2700 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2701 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2702 | #define BUSY 1 | |
2703 | #define KICK 5 | |
2704 | #define HUNG 20 | |
893eead0 | 2705 | |
d330a953 | 2706 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2707 | return; |
2708 | ||
b4519513 | 2709 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2710 | u64 acthd; |
2711 | u32 seqno; | |
9107e9d2 | 2712 | bool busy = true; |
05407ff8 | 2713 | |
6274f212 CW |
2714 | semaphore_clear_deadlocks(dev_priv); |
2715 | ||
05407ff8 MK |
2716 | seqno = ring->get_seqno(ring, false); |
2717 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2718 | |
9107e9d2 | 2719 | if (ring->hangcheck.seqno == seqno) { |
44cdd6d2 | 2720 | if (ring_idle(ring)) { |
da661464 MK |
2721 | ring->hangcheck.action = HANGCHECK_IDLE; |
2722 | ||
9107e9d2 CW |
2723 | if (waitqueue_active(&ring->irq_queue)) { |
2724 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2725 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2726 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2727 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2728 | ring->name); | |
2729 | else | |
2730 | DRM_INFO("Fake missed irq on %s\n", | |
2731 | ring->name); | |
094f9a54 CW |
2732 | wake_up_all(&ring->irq_queue); |
2733 | } | |
2734 | /* Safeguard against driver failure */ | |
2735 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2736 | } else |
2737 | busy = false; | |
05407ff8 | 2738 | } else { |
6274f212 CW |
2739 | /* We always increment the hangcheck score |
2740 | * if the ring is busy and still processing | |
2741 | * the same request, so that no single request | |
2742 | * can run indefinitely (such as a chain of | |
2743 | * batches). The only time we do not increment | |
2744 | * the hangcheck score on this ring, if this | |
2745 | * ring is in a legitimate wait for another | |
2746 | * ring. In that case the waiting ring is a | |
2747 | * victim and we want to be sure we catch the | |
2748 | * right culprit. Then every time we do kick | |
2749 | * the ring, add a small increment to the | |
2750 | * score so that we can catch a batch that is | |
2751 | * being repeatedly kicked and so responsible | |
2752 | * for stalling the machine. | |
2753 | */ | |
ad8beaea MK |
2754 | ring->hangcheck.action = ring_stuck(ring, |
2755 | acthd); | |
2756 | ||
2757 | switch (ring->hangcheck.action) { | |
da661464 | 2758 | case HANGCHECK_IDLE: |
f2f4d82f | 2759 | case HANGCHECK_WAIT: |
f2f4d82f | 2760 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2761 | break; |
2762 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2763 | ring->hangcheck.score += BUSY; |
6274f212 | 2764 | break; |
f2f4d82f | 2765 | case HANGCHECK_KICK: |
ea04cb31 | 2766 | ring->hangcheck.score += KICK; |
6274f212 | 2767 | break; |
f2f4d82f | 2768 | case HANGCHECK_HUNG: |
ea04cb31 | 2769 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2770 | stuck[i] = true; |
2771 | break; | |
2772 | } | |
05407ff8 | 2773 | } |
9107e9d2 | 2774 | } else { |
da661464 MK |
2775 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2776 | ||
9107e9d2 CW |
2777 | /* Gradually reduce the count so that we catch DoS |
2778 | * attempts across multiple batches. | |
2779 | */ | |
2780 | if (ring->hangcheck.score > 0) | |
2781 | ring->hangcheck.score--; | |
f260fe7b MK |
2782 | |
2783 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
2784 | } |
2785 | ||
05407ff8 MK |
2786 | ring->hangcheck.seqno = seqno; |
2787 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2788 | busy_count += busy; |
893eead0 | 2789 | } |
b9201c14 | 2790 | |
92cab734 | 2791 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2792 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2793 | DRM_INFO("%s on %s\n", |
2794 | stuck[i] ? "stuck" : "no progress", | |
2795 | ring->name); | |
a43adf07 | 2796 | rings_hung++; |
92cab734 MK |
2797 | } |
2798 | } | |
2799 | ||
05407ff8 | 2800 | if (rings_hung) |
58174462 | 2801 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2802 | |
05407ff8 MK |
2803 | if (busy_count) |
2804 | /* Reset timer case chip hangs without another request | |
2805 | * being added */ | |
10cd45b6 MK |
2806 | i915_queue_hangcheck(dev); |
2807 | } | |
2808 | ||
2809 | void i915_queue_hangcheck(struct drm_device *dev) | |
2810 | { | |
737b1506 | 2811 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 2812 | |
d330a953 | 2813 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2814 | return; |
2815 | ||
737b1506 CW |
2816 | /* Don't continually defer the hangcheck so that it is always run at |
2817 | * least once after work has been scheduled on any ring. Otherwise, | |
2818 | * we will ignore a hung ring if a second ring is kept busy. | |
2819 | */ | |
2820 | ||
2821 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
2822 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2823 | } |
2824 | ||
1c69eb42 | 2825 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
2826 | { |
2827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2828 | ||
2829 | if (HAS_PCH_NOP(dev)) | |
2830 | return; | |
2831 | ||
f86f3fb0 | 2832 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
2833 | |
2834 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
2835 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 2836 | } |
105b122e | 2837 | |
622364b6 PZ |
2838 | /* |
2839 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
2840 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
2841 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
2842 | * only unmask them as needed with SDEIMR. | |
2843 | * | |
2844 | * This function needs to be called before interrupts are enabled. | |
2845 | */ | |
2846 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
2847 | { | |
2848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2849 | ||
2850 | if (HAS_PCH_NOP(dev)) | |
2851 | return; | |
2852 | ||
2853 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
2854 | I915_WRITE(SDEIER, 0xffffffff); |
2855 | POSTING_READ(SDEIER); | |
2856 | } | |
2857 | ||
7c4d664e | 2858 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
2859 | { |
2860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2861 | ||
f86f3fb0 | 2862 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 2863 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 2864 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
2865 | } |
2866 | ||
1da177e4 LT |
2867 | /* drm_dma.h hooks |
2868 | */ | |
be30b29f | 2869 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 2870 | { |
2d1013dd | 2871 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 2872 | |
0c841212 | 2873 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 2874 | |
f86f3fb0 | 2875 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
2876 | if (IS_GEN7(dev)) |
2877 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 2878 | |
7c4d664e | 2879 | gen5_gt_irq_reset(dev); |
c650156a | 2880 | |
1c69eb42 | 2881 | ibx_irq_reset(dev); |
7d99163d | 2882 | } |
c650156a | 2883 | |
70591a41 VS |
2884 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
2885 | { | |
2886 | enum pipe pipe; | |
2887 | ||
2888 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2889 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2890 | ||
2891 | for_each_pipe(dev_priv, pipe) | |
2892 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2893 | ||
2894 | GEN5_IRQ_RESET(VLV_); | |
2895 | } | |
2896 | ||
7e231dbe JB |
2897 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2898 | { | |
2d1013dd | 2899 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2900 | |
7e231dbe JB |
2901 | /* VLV magic */ |
2902 | I915_WRITE(VLV_IMR, 0); | |
2903 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2904 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2905 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2906 | ||
7c4d664e | 2907 | gen5_gt_irq_reset(dev); |
7e231dbe | 2908 | |
7c4cde39 | 2909 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 2910 | |
70591a41 | 2911 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
2912 | } |
2913 | ||
d6e3cca3 DV |
2914 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
2915 | { | |
2916 | GEN8_IRQ_RESET_NDX(GT, 0); | |
2917 | GEN8_IRQ_RESET_NDX(GT, 1); | |
2918 | GEN8_IRQ_RESET_NDX(GT, 2); | |
2919 | GEN8_IRQ_RESET_NDX(GT, 3); | |
2920 | } | |
2921 | ||
823f6b38 | 2922 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
2923 | { |
2924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2925 | int pipe; | |
2926 | ||
abd58f01 BW |
2927 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2928 | POSTING_READ(GEN8_MASTER_IRQ); | |
2929 | ||
d6e3cca3 | 2930 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 2931 | |
055e393f | 2932 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
2933 | if (intel_display_power_is_enabled(dev_priv, |
2934 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 2935 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 2936 | |
f86f3fb0 PZ |
2937 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
2938 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
2939 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 2940 | |
266ea3d9 SS |
2941 | if (HAS_PCH_SPLIT(dev)) |
2942 | ibx_irq_reset(dev); | |
abd58f01 | 2943 | } |
09f2344d | 2944 | |
4c6c03be DL |
2945 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
2946 | unsigned int pipe_mask) | |
d49bdb0e | 2947 | { |
1180e206 | 2948 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 2949 | |
13321786 | 2950 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
2951 | if (pipe_mask & 1 << PIPE_A) |
2952 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
2953 | dev_priv->de_irq_mask[PIPE_A], | |
2954 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
2955 | if (pipe_mask & 1 << PIPE_B) |
2956 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
2957 | dev_priv->de_irq_mask[PIPE_B], | |
2958 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
2959 | if (pipe_mask & 1 << PIPE_C) | |
2960 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
2961 | dev_priv->de_irq_mask[PIPE_C], | |
2962 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 2963 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
2964 | } |
2965 | ||
43f328d7 VS |
2966 | static void cherryview_irq_preinstall(struct drm_device *dev) |
2967 | { | |
2968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
2969 | |
2970 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
2971 | POSTING_READ(GEN8_MASTER_IRQ); | |
2972 | ||
d6e3cca3 | 2973 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
2974 | |
2975 | GEN5_IRQ_RESET(GEN8_PCU_); | |
2976 | ||
43f328d7 VS |
2977 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
2978 | ||
70591a41 | 2979 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
2980 | } |
2981 | ||
82a28bcf | 2982 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 2983 | { |
2d1013dd | 2984 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 2985 | struct intel_encoder *intel_encoder; |
fee884ed | 2986 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2987 | |
2988 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2989 | hotplug_irqs = SDE_HOTPLUG_MASK; |
b2784e15 | 2990 | for_each_intel_encoder(dev, intel_encoder) |
5fcece80 | 2991 | if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED) |
fee884ed | 2992 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2993 | } else { |
fee884ed | 2994 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
b2784e15 | 2995 | for_each_intel_encoder(dev, intel_encoder) |
5fcece80 | 2996 | if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED) |
fee884ed | 2997 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2998 | } |
7fe0b973 | 2999 | |
fee884ed | 3000 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3001 | |
3002 | /* | |
3003 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
3004 | * duration to 2ms (which is the minimum in the Display Port spec) | |
3005 | * | |
3006 | * This register is the same on all known PCH chips. | |
3007 | */ | |
7fe0b973 KP |
3008 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3009 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3010 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3011 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3012 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
3013 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
3014 | } | |
3015 | ||
e0a20ad7 SS |
3016 | static void bxt_hpd_irq_setup(struct drm_device *dev) |
3017 | { | |
3018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3019 | struct intel_encoder *intel_encoder; | |
3020 | u32 hotplug_port = 0; | |
3021 | u32 hotplug_ctrl; | |
3022 | ||
3023 | /* Now, enable HPD */ | |
3024 | for_each_intel_encoder(dev, intel_encoder) { | |
5fcece80 | 3025 | if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state |
e0a20ad7 SS |
3026 | == HPD_ENABLED) |
3027 | hotplug_port |= hpd_bxt[intel_encoder->hpd_pin]; | |
3028 | } | |
3029 | ||
3030 | /* Mask all HPD control bits */ | |
3031 | hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK; | |
3032 | ||
3033 | /* Enable requested port in hotplug control */ | |
3034 | /* TODO: implement (short) HPD support on port A */ | |
3035 | WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA); | |
3036 | if (hotplug_port & BXT_DE_PORT_HP_DDIB) | |
3037 | hotplug_ctrl |= BXT_DDIB_HPD_ENABLE; | |
3038 | if (hotplug_port & BXT_DE_PORT_HP_DDIC) | |
3039 | hotplug_ctrl |= BXT_DDIC_HPD_ENABLE; | |
3040 | I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl); | |
3041 | ||
3042 | /* Unmask DDI hotplug in IMR */ | |
3043 | hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port; | |
3044 | I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl); | |
3045 | ||
3046 | /* Enable DDI hotplug in IER */ | |
3047 | hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port; | |
3048 | I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl); | |
3049 | POSTING_READ(GEN8_DE_PORT_IER); | |
3050 | } | |
3051 | ||
d46da437 PZ |
3052 | static void ibx_irq_postinstall(struct drm_device *dev) |
3053 | { | |
2d1013dd | 3054 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3055 | u32 mask; |
e5868a31 | 3056 | |
692a04cf DV |
3057 | if (HAS_PCH_NOP(dev)) |
3058 | return; | |
3059 | ||
105b122e | 3060 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3061 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3062 | else |
5c673b60 | 3063 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3064 | |
337ba017 | 3065 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3066 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3067 | } |
3068 | ||
0a9a8c91 DV |
3069 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3070 | { | |
3071 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3072 | u32 pm_irqs, gt_irqs; | |
3073 | ||
3074 | pm_irqs = gt_irqs = 0; | |
3075 | ||
3076 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3077 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3078 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3079 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3080 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3081 | } |
3082 | ||
3083 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3084 | if (IS_GEN5(dev)) { | |
3085 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3086 | ILK_BSD_USER_INTERRUPT; | |
3087 | } else { | |
3088 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3089 | } | |
3090 | ||
35079899 | 3091 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3092 | |
3093 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3094 | /* |
3095 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3096 | * itself is enabled/disabled. | |
3097 | */ | |
0a9a8c91 DV |
3098 | if (HAS_VEBOX(dev)) |
3099 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3100 | ||
605cd25b | 3101 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3102 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3103 | } |
3104 | } | |
3105 | ||
f71d4af4 | 3106 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3107 | { |
2d1013dd | 3108 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3109 | u32 display_mask, extra_mask; |
3110 | ||
3111 | if (INTEL_INFO(dev)->gen >= 7) { | |
3112 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3113 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3114 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3115 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3116 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 3117 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
3118 | } else { |
3119 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3120 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3121 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3122 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3123 | DE_POISON); | |
5c673b60 DV |
3124 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3125 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3126 | } |
036a4a7d | 3127 | |
1ec14ad3 | 3128 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3129 | |
0c841212 PZ |
3130 | I915_WRITE(HWSTAM, 0xeffe); |
3131 | ||
622364b6 PZ |
3132 | ibx_irq_pre_postinstall(dev); |
3133 | ||
35079899 | 3134 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3135 | |
0a9a8c91 | 3136 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3137 | |
d46da437 | 3138 | ibx_irq_postinstall(dev); |
7fe0b973 | 3139 | |
f97108d1 | 3140 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3141 | /* Enable PCU event interrupts |
3142 | * | |
3143 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3144 | * setup is guaranteed to run in single-threaded context. But we |
3145 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3146 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3147 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3148 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3149 | } |
3150 | ||
036a4a7d ZW |
3151 | return 0; |
3152 | } | |
3153 | ||
f8b79e58 ID |
3154 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3155 | { | |
3156 | u32 pipestat_mask; | |
3157 | u32 iir_mask; | |
120dda4f | 3158 | enum pipe pipe; |
f8b79e58 ID |
3159 | |
3160 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3161 | PIPE_FIFO_UNDERRUN_STATUS; | |
3162 | ||
120dda4f VS |
3163 | for_each_pipe(dev_priv, pipe) |
3164 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3165 | POSTING_READ(PIPESTAT(PIPE_A)); |
3166 | ||
3167 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3168 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3169 | ||
120dda4f VS |
3170 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3171 | for_each_pipe(dev_priv, pipe) | |
3172 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3173 | |
3174 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3175 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3176 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3177 | if (IS_CHERRYVIEW(dev_priv)) |
3178 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3179 | dev_priv->irq_mask &= ~iir_mask; |
3180 | ||
3181 | I915_WRITE(VLV_IIR, iir_mask); | |
3182 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3183 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3184 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3185 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3186 | } |
3187 | ||
3188 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3189 | { | |
3190 | u32 pipestat_mask; | |
3191 | u32 iir_mask; | |
120dda4f | 3192 | enum pipe pipe; |
f8b79e58 ID |
3193 | |
3194 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3195 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3196 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3197 | if (IS_CHERRYVIEW(dev_priv)) |
3198 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3199 | |
3200 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3201 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3202 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3203 | I915_WRITE(VLV_IIR, iir_mask); |
3204 | I915_WRITE(VLV_IIR, iir_mask); | |
3205 | POSTING_READ(VLV_IIR); | |
3206 | ||
3207 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3208 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3209 | ||
120dda4f VS |
3210 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3211 | for_each_pipe(dev_priv, pipe) | |
3212 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3213 | |
3214 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3215 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3216 | |
3217 | for_each_pipe(dev_priv, pipe) | |
3218 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3219 | POSTING_READ(PIPESTAT(PIPE_A)); |
3220 | } | |
3221 | ||
3222 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3223 | { | |
3224 | assert_spin_locked(&dev_priv->irq_lock); | |
3225 | ||
3226 | if (dev_priv->display_irqs_enabled) | |
3227 | return; | |
3228 | ||
3229 | dev_priv->display_irqs_enabled = true; | |
3230 | ||
950eabaf | 3231 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3232 | valleyview_display_irqs_install(dev_priv); |
3233 | } | |
3234 | ||
3235 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3236 | { | |
3237 | assert_spin_locked(&dev_priv->irq_lock); | |
3238 | ||
3239 | if (!dev_priv->display_irqs_enabled) | |
3240 | return; | |
3241 | ||
3242 | dev_priv->display_irqs_enabled = false; | |
3243 | ||
950eabaf | 3244 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3245 | valleyview_display_irqs_uninstall(dev_priv); |
3246 | } | |
3247 | ||
0e6c9a9e | 3248 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3249 | { |
f8b79e58 | 3250 | dev_priv->irq_mask = ~0; |
7e231dbe | 3251 | |
20afbda2 DV |
3252 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3253 | POSTING_READ(PORT_HOTPLUG_EN); | |
3254 | ||
7e231dbe | 3255 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3256 | I915_WRITE(VLV_IIR, 0xffffffff); |
3257 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3258 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3259 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3260 | |
b79480ba DV |
3261 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3262 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3263 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3264 | if (dev_priv->display_irqs_enabled) |
3265 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3266 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3267 | } |
3268 | ||
3269 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3270 | { | |
3271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3272 | ||
3273 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3274 | |
0a9a8c91 | 3275 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3276 | |
3277 | /* ack & enable invalid PTE error interrupts */ | |
3278 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3279 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3280 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3281 | #endif | |
3282 | ||
3283 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3284 | |
3285 | return 0; | |
3286 | } | |
3287 | ||
abd58f01 BW |
3288 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3289 | { | |
abd58f01 BW |
3290 | /* These are interrupts we'll toggle with the ring mask register */ |
3291 | uint32_t gt_interrupts[] = { | |
3292 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3293 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3294 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3295 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3296 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3297 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3298 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3299 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3300 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3301 | 0, |
73d477f6 OM |
3302 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3303 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3304 | }; |
3305 | ||
0961021a | 3306 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3307 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3308 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3309 | /* |
3310 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3311 | * is enabled/disabled. | |
3312 | */ | |
3313 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3314 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3315 | } |
3316 | ||
3317 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3318 | { | |
770de83d DL |
3319 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3320 | uint32_t de_pipe_enables; | |
abd58f01 | 3321 | int pipe; |
9e63743e | 3322 | u32 de_port_en = GEN8_AUX_CHANNEL_A; |
770de83d | 3323 | |
88e04703 | 3324 | if (IS_GEN9(dev_priv)) { |
770de83d DL |
3325 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3326 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
9e63743e | 3327 | de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
88e04703 | 3328 | GEN9_AUX_CHANNEL_D; |
9e63743e SS |
3329 | |
3330 | if (IS_BROXTON(dev_priv)) | |
3331 | de_port_en |= BXT_DE_PORT_GMBUS; | |
88e04703 | 3332 | } else |
770de83d DL |
3333 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3334 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3335 | ||
3336 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3337 | GEN8_PIPE_FIFO_UNDERRUN; | |
3338 | ||
13b3a0a7 DV |
3339 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3340 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3341 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3342 | |
055e393f | 3343 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3344 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3345 | POWER_DOMAIN_PIPE(pipe))) |
3346 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3347 | dev_priv->de_irq_mask[pipe], | |
3348 | de_pipe_enables); | |
abd58f01 | 3349 | |
9e63743e | 3350 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en); |
abd58f01 BW |
3351 | } |
3352 | ||
3353 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3354 | { | |
3355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3356 | ||
266ea3d9 SS |
3357 | if (HAS_PCH_SPLIT(dev)) |
3358 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3359 | |
abd58f01 BW |
3360 | gen8_gt_irq_postinstall(dev_priv); |
3361 | gen8_de_irq_postinstall(dev_priv); | |
3362 | ||
266ea3d9 SS |
3363 | if (HAS_PCH_SPLIT(dev)) |
3364 | ibx_irq_postinstall(dev); | |
abd58f01 BW |
3365 | |
3366 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3367 | POSTING_READ(GEN8_MASTER_IRQ); | |
3368 | ||
3369 | return 0; | |
3370 | } | |
3371 | ||
43f328d7 VS |
3372 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3373 | { | |
3374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3375 | |
c2b66797 | 3376 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3377 | |
3378 | gen8_gt_irq_postinstall(dev_priv); | |
3379 | ||
3380 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3381 | POSTING_READ(GEN8_MASTER_IRQ); | |
3382 | ||
3383 | return 0; | |
3384 | } | |
3385 | ||
abd58f01 BW |
3386 | static void gen8_irq_uninstall(struct drm_device *dev) |
3387 | { | |
3388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3389 | |
3390 | if (!dev_priv) | |
3391 | return; | |
3392 | ||
823f6b38 | 3393 | gen8_irq_reset(dev); |
abd58f01 BW |
3394 | } |
3395 | ||
8ea0be4f VS |
3396 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3397 | { | |
3398 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3399 | * just to make the assert_spin_locked check happy. */ | |
3400 | spin_lock_irq(&dev_priv->irq_lock); | |
3401 | if (dev_priv->display_irqs_enabled) | |
3402 | valleyview_display_irqs_uninstall(dev_priv); | |
3403 | spin_unlock_irq(&dev_priv->irq_lock); | |
3404 | ||
3405 | vlv_display_irq_reset(dev_priv); | |
3406 | ||
c352d1ba | 3407 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3408 | } |
3409 | ||
7e231dbe JB |
3410 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3411 | { | |
2d1013dd | 3412 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3413 | |
3414 | if (!dev_priv) | |
3415 | return; | |
3416 | ||
843d0e7d ID |
3417 | I915_WRITE(VLV_MASTER_IER, 0); |
3418 | ||
893fce8e VS |
3419 | gen5_gt_irq_reset(dev); |
3420 | ||
7e231dbe | 3421 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3422 | |
8ea0be4f | 3423 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3424 | } |
3425 | ||
43f328d7 VS |
3426 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3427 | { | |
3428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3429 | |
3430 | if (!dev_priv) | |
3431 | return; | |
3432 | ||
3433 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3434 | POSTING_READ(GEN8_MASTER_IRQ); | |
3435 | ||
a2c30fba | 3436 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3437 | |
a2c30fba | 3438 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3439 | |
c2b66797 | 3440 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3441 | } |
3442 | ||
f71d4af4 | 3443 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3444 | { |
2d1013dd | 3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3446 | |
3447 | if (!dev_priv) | |
3448 | return; | |
3449 | ||
be30b29f | 3450 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3451 | } |
3452 | ||
a266c7d5 | 3453 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3454 | { |
2d1013dd | 3455 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3456 | int pipe; |
91e3738e | 3457 | |
055e393f | 3458 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3459 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3460 | I915_WRITE16(IMR, 0xffff); |
3461 | I915_WRITE16(IER, 0x0); | |
3462 | POSTING_READ16(IER); | |
c2798b19 CW |
3463 | } |
3464 | ||
3465 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3466 | { | |
2d1013dd | 3467 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3468 | |
c2798b19 CW |
3469 | I915_WRITE16(EMR, |
3470 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3471 | ||
3472 | /* Unmask the interrupts that we always want on. */ | |
3473 | dev_priv->irq_mask = | |
3474 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3475 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3476 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3477 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3478 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3479 | ||
3480 | I915_WRITE16(IER, | |
3481 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3482 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3483 | I915_USER_INTERRUPT); |
3484 | POSTING_READ16(IER); | |
3485 | ||
379ef82d DV |
3486 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3487 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3488 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3489 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3490 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3491 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3492 | |
c2798b19 CW |
3493 | return 0; |
3494 | } | |
3495 | ||
90a72f87 VS |
3496 | /* |
3497 | * Returns true when a page flip has completed. | |
3498 | */ | |
3499 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3500 | int plane, int pipe, u32 iir) |
90a72f87 | 3501 | { |
2d1013dd | 3502 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3503 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3504 | |
8d7849db | 3505 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3506 | return false; |
3507 | ||
3508 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3509 | goto check_page_flip; |
90a72f87 | 3510 | |
90a72f87 VS |
3511 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3512 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3513 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3514 | * the flip is completed (no longer pending). Since this doesn't raise | |
3515 | * an interrupt per se, we watch for the change at vblank. | |
3516 | */ | |
3517 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3518 | goto check_page_flip; |
90a72f87 | 3519 | |
7d47559e | 3520 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3521 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3522 | return true; |
d6bbafa1 CW |
3523 | |
3524 | check_page_flip: | |
3525 | intel_check_page_flip(dev, pipe); | |
3526 | return false; | |
90a72f87 VS |
3527 | } |
3528 | ||
ff1f525e | 3529 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3530 | { |
45a83f84 | 3531 | struct drm_device *dev = arg; |
2d1013dd | 3532 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3533 | u16 iir, new_iir; |
3534 | u32 pipe_stats[2]; | |
c2798b19 CW |
3535 | int pipe; |
3536 | u16 flip_mask = | |
3537 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3538 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3539 | ||
2dd2a883 ID |
3540 | if (!intel_irqs_enabled(dev_priv)) |
3541 | return IRQ_NONE; | |
3542 | ||
c2798b19 CW |
3543 | iir = I915_READ16(IIR); |
3544 | if (iir == 0) | |
3545 | return IRQ_NONE; | |
3546 | ||
3547 | while (iir & ~flip_mask) { | |
3548 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3549 | * have been cleared after the pipestat interrupt was received. | |
3550 | * It doesn't set the bit in iir again, but it still produces | |
3551 | * interrupts (for non-MSI). | |
3552 | */ | |
222c7f51 | 3553 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3554 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3555 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3556 | |
055e393f | 3557 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3558 | int reg = PIPESTAT(pipe); |
3559 | pipe_stats[pipe] = I915_READ(reg); | |
3560 | ||
3561 | /* | |
3562 | * Clear the PIPE*STAT regs before the IIR | |
3563 | */ | |
2d9d2b0b | 3564 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3565 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3566 | } |
222c7f51 | 3567 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3568 | |
3569 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3570 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3571 | ||
c2798b19 | 3572 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3573 | notify_ring(&dev_priv->ring[RCS]); |
c2798b19 | 3574 | |
055e393f | 3575 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3576 | int plane = pipe; |
3a77c4c4 | 3577 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3578 | plane = !plane; |
3579 | ||
4356d586 | 3580 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3581 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3582 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3583 | |
4356d586 | 3584 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3585 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3586 | |
1f7247c0 DV |
3587 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3588 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3589 | pipe); | |
4356d586 | 3590 | } |
c2798b19 CW |
3591 | |
3592 | iir = new_iir; | |
3593 | } | |
3594 | ||
3595 | return IRQ_HANDLED; | |
3596 | } | |
3597 | ||
3598 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3599 | { | |
2d1013dd | 3600 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3601 | int pipe; |
3602 | ||
055e393f | 3603 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3604 | /* Clear enable bits; then clear status bits */ |
3605 | I915_WRITE(PIPESTAT(pipe), 0); | |
3606 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3607 | } | |
3608 | I915_WRITE16(IMR, 0xffff); | |
3609 | I915_WRITE16(IER, 0x0); | |
3610 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3611 | } | |
3612 | ||
a266c7d5 CW |
3613 | static void i915_irq_preinstall(struct drm_device * dev) |
3614 | { | |
2d1013dd | 3615 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3616 | int pipe; |
3617 | ||
a266c7d5 CW |
3618 | if (I915_HAS_HOTPLUG(dev)) { |
3619 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3620 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3621 | } | |
3622 | ||
00d98ebd | 3623 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3624 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3625 | I915_WRITE(PIPESTAT(pipe), 0); |
3626 | I915_WRITE(IMR, 0xffffffff); | |
3627 | I915_WRITE(IER, 0x0); | |
3628 | POSTING_READ(IER); | |
3629 | } | |
3630 | ||
3631 | static int i915_irq_postinstall(struct drm_device *dev) | |
3632 | { | |
2d1013dd | 3633 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3634 | u32 enable_mask; |
a266c7d5 | 3635 | |
38bde180 CW |
3636 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3637 | ||
3638 | /* Unmask the interrupts that we always want on. */ | |
3639 | dev_priv->irq_mask = | |
3640 | ~(I915_ASLE_INTERRUPT | | |
3641 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3642 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3643 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3644 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3645 | |
3646 | enable_mask = | |
3647 | I915_ASLE_INTERRUPT | | |
3648 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3649 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3650 | I915_USER_INTERRUPT; |
3651 | ||
a266c7d5 | 3652 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3653 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3654 | POSTING_READ(PORT_HOTPLUG_EN); | |
3655 | ||
a266c7d5 CW |
3656 | /* Enable in IER... */ |
3657 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3658 | /* and unmask in IMR */ | |
3659 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3660 | } | |
3661 | ||
a266c7d5 CW |
3662 | I915_WRITE(IMR, dev_priv->irq_mask); |
3663 | I915_WRITE(IER, enable_mask); | |
3664 | POSTING_READ(IER); | |
3665 | ||
f49e38dd | 3666 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3667 | |
379ef82d DV |
3668 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3669 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3670 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3671 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3672 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3673 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3674 | |
20afbda2 DV |
3675 | return 0; |
3676 | } | |
3677 | ||
90a72f87 VS |
3678 | /* |
3679 | * Returns true when a page flip has completed. | |
3680 | */ | |
3681 | static bool i915_handle_vblank(struct drm_device *dev, | |
3682 | int plane, int pipe, u32 iir) | |
3683 | { | |
2d1013dd | 3684 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3685 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3686 | ||
8d7849db | 3687 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3688 | return false; |
3689 | ||
3690 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3691 | goto check_page_flip; |
90a72f87 | 3692 | |
90a72f87 VS |
3693 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3694 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3695 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3696 | * the flip is completed (no longer pending). Since this doesn't raise | |
3697 | * an interrupt per se, we watch for the change at vblank. | |
3698 | */ | |
3699 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3700 | goto check_page_flip; |
90a72f87 | 3701 | |
7d47559e | 3702 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3703 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3704 | return true; |
d6bbafa1 CW |
3705 | |
3706 | check_page_flip: | |
3707 | intel_check_page_flip(dev, pipe); | |
3708 | return false; | |
90a72f87 VS |
3709 | } |
3710 | ||
ff1f525e | 3711 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3712 | { |
45a83f84 | 3713 | struct drm_device *dev = arg; |
2d1013dd | 3714 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3715 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3716 | u32 flip_mask = |
3717 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3718 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3719 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3720 | |
2dd2a883 ID |
3721 | if (!intel_irqs_enabled(dev_priv)) |
3722 | return IRQ_NONE; | |
3723 | ||
a266c7d5 | 3724 | iir = I915_READ(IIR); |
38bde180 CW |
3725 | do { |
3726 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3727 | bool blc_event = false; |
a266c7d5 CW |
3728 | |
3729 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3730 | * have been cleared after the pipestat interrupt was received. | |
3731 | * It doesn't set the bit in iir again, but it still produces | |
3732 | * interrupts (for non-MSI). | |
3733 | */ | |
222c7f51 | 3734 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3735 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3736 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3737 | |
055e393f | 3738 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3739 | int reg = PIPESTAT(pipe); |
3740 | pipe_stats[pipe] = I915_READ(reg); | |
3741 | ||
38bde180 | 3742 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3743 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3744 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3745 | irq_received = true; |
a266c7d5 CW |
3746 | } |
3747 | } | |
222c7f51 | 3748 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3749 | |
3750 | if (!irq_received) | |
3751 | break; | |
3752 | ||
a266c7d5 | 3753 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
3754 | if (I915_HAS_HOTPLUG(dev) && |
3755 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
3756 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3757 | |
38bde180 | 3758 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3759 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3760 | ||
a266c7d5 | 3761 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3762 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 3763 | |
055e393f | 3764 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 3765 | int plane = pipe; |
3a77c4c4 | 3766 | if (HAS_FBC(dev)) |
38bde180 | 3767 | plane = !plane; |
90a72f87 | 3768 | |
8291ee90 | 3769 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3770 | i915_handle_vblank(dev, plane, pipe, iir)) |
3771 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3772 | |
3773 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3774 | blc_event = true; | |
4356d586 DV |
3775 | |
3776 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3777 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3778 | |
1f7247c0 DV |
3779 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3780 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3781 | pipe); | |
a266c7d5 CW |
3782 | } |
3783 | ||
a266c7d5 CW |
3784 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3785 | intel_opregion_asle_intr(dev); | |
3786 | ||
3787 | /* With MSI, interrupts are only generated when iir | |
3788 | * transitions from zero to nonzero. If another bit got | |
3789 | * set while we were handling the existing iir bits, then | |
3790 | * we would never get another interrupt. | |
3791 | * | |
3792 | * This is fine on non-MSI as well, as if we hit this path | |
3793 | * we avoid exiting the interrupt handler only to generate | |
3794 | * another one. | |
3795 | * | |
3796 | * Note that for MSI this could cause a stray interrupt report | |
3797 | * if an interrupt landed in the time between writing IIR and | |
3798 | * the posting read. This should be rare enough to never | |
3799 | * trigger the 99% of 100,000 interrupts test for disabling | |
3800 | * stray interrupts. | |
3801 | */ | |
38bde180 | 3802 | ret = IRQ_HANDLED; |
a266c7d5 | 3803 | iir = new_iir; |
38bde180 | 3804 | } while (iir & ~flip_mask); |
a266c7d5 CW |
3805 | |
3806 | return ret; | |
3807 | } | |
3808 | ||
3809 | static void i915_irq_uninstall(struct drm_device * dev) | |
3810 | { | |
2d1013dd | 3811 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3812 | int pipe; |
3813 | ||
a266c7d5 CW |
3814 | if (I915_HAS_HOTPLUG(dev)) { |
3815 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3816 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3817 | } | |
3818 | ||
00d98ebd | 3819 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 3820 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 3821 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 3822 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3823 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3824 | } | |
a266c7d5 CW |
3825 | I915_WRITE(IMR, 0xffffffff); |
3826 | I915_WRITE(IER, 0x0); | |
3827 | ||
a266c7d5 CW |
3828 | I915_WRITE(IIR, I915_READ(IIR)); |
3829 | } | |
3830 | ||
3831 | static void i965_irq_preinstall(struct drm_device * dev) | |
3832 | { | |
2d1013dd | 3833 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3834 | int pipe; |
3835 | ||
adca4730 CW |
3836 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3837 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3838 | |
3839 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 3840 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3841 | I915_WRITE(PIPESTAT(pipe), 0); |
3842 | I915_WRITE(IMR, 0xffffffff); | |
3843 | I915_WRITE(IER, 0x0); | |
3844 | POSTING_READ(IER); | |
3845 | } | |
3846 | ||
3847 | static int i965_irq_postinstall(struct drm_device *dev) | |
3848 | { | |
2d1013dd | 3849 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3850 | u32 enable_mask; |
a266c7d5 CW |
3851 | u32 error_mask; |
3852 | ||
a266c7d5 | 3853 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3854 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3855 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3856 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3857 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3858 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3859 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3860 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3861 | ||
3862 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3863 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3864 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3865 | enable_mask |= I915_USER_INTERRUPT; |
3866 | ||
3867 | if (IS_G4X(dev)) | |
3868 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3869 | |
b79480ba DV |
3870 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3871 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3872 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3873 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3874 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3875 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3876 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 3877 | |
a266c7d5 CW |
3878 | /* |
3879 | * Enable some error detection, note the instruction error mask | |
3880 | * bit is reserved, so we leave it masked. | |
3881 | */ | |
3882 | if (IS_G4X(dev)) { | |
3883 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3884 | GM45_ERROR_MEM_PRIV | | |
3885 | GM45_ERROR_CP_PRIV | | |
3886 | I915_ERROR_MEMORY_REFRESH); | |
3887 | } else { | |
3888 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3889 | I915_ERROR_MEMORY_REFRESH); | |
3890 | } | |
3891 | I915_WRITE(EMR, error_mask); | |
3892 | ||
3893 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3894 | I915_WRITE(IER, enable_mask); | |
3895 | POSTING_READ(IER); | |
3896 | ||
20afbda2 DV |
3897 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3898 | POSTING_READ(PORT_HOTPLUG_EN); | |
3899 | ||
f49e38dd | 3900 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3901 | |
3902 | return 0; | |
3903 | } | |
3904 | ||
bac56d5b | 3905 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 3906 | { |
2d1013dd | 3907 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd569aed | 3908 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3909 | u32 hotplug_en; |
3910 | ||
b5ea2d56 DV |
3911 | assert_spin_locked(&dev_priv->irq_lock); |
3912 | ||
778eb334 VS |
3913 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
3914 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3915 | /* Note HDMI and DP share hotplug bits */ | |
3916 | /* enable bits are the same for all generations */ | |
3917 | for_each_intel_encoder(dev, intel_encoder) | |
5fcece80 | 3918 | if (dev_priv->hotplug.stats[intel_encoder->hpd_pin].state == HPD_ENABLED) |
778eb334 VS |
3919 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; |
3920 | /* Programming the CRT detection parameters tends | |
3921 | to generate a spurious hotplug event about three | |
3922 | seconds later. So just do it once. | |
3923 | */ | |
3924 | if (IS_G4X(dev)) | |
3925 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
3926 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; | |
3927 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
3928 | ||
3929 | /* Ignore TV since it's buggy */ | |
3930 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
a266c7d5 CW |
3931 | } |
3932 | ||
ff1f525e | 3933 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 3934 | { |
45a83f84 | 3935 | struct drm_device *dev = arg; |
2d1013dd | 3936 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3937 | u32 iir, new_iir; |
3938 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 3939 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
3940 | u32 flip_mask = |
3941 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3942 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 3943 | |
2dd2a883 ID |
3944 | if (!intel_irqs_enabled(dev_priv)) |
3945 | return IRQ_NONE; | |
3946 | ||
a266c7d5 CW |
3947 | iir = I915_READ(IIR); |
3948 | ||
a266c7d5 | 3949 | for (;;) { |
501e01d7 | 3950 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
3951 | bool blc_event = false; |
3952 | ||
a266c7d5 CW |
3953 | /* Can't rely on pipestat interrupt bit in iir as it might |
3954 | * have been cleared after the pipestat interrupt was received. | |
3955 | * It doesn't set the bit in iir again, but it still produces | |
3956 | * interrupts (for non-MSI). | |
3957 | */ | |
222c7f51 | 3958 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3959 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3960 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3961 | |
055e393f | 3962 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
3963 | int reg = PIPESTAT(pipe); |
3964 | pipe_stats[pipe] = I915_READ(reg); | |
3965 | ||
3966 | /* | |
3967 | * Clear the PIPE*STAT regs before the IIR | |
3968 | */ | |
3969 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 3970 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 3971 | irq_received = true; |
a266c7d5 CW |
3972 | } |
3973 | } | |
222c7f51 | 3974 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
3975 | |
3976 | if (!irq_received) | |
3977 | break; | |
3978 | ||
3979 | ret = IRQ_HANDLED; | |
3980 | ||
3981 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
3982 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
3983 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 3984 | |
21ad8330 | 3985 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3986 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3987 | ||
a266c7d5 | 3988 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3989 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 3990 | if (iir & I915_BSD_USER_INTERRUPT) |
74cdb337 | 3991 | notify_ring(&dev_priv->ring[VCS]); |
a266c7d5 | 3992 | |
055e393f | 3993 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 3994 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3995 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3996 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3997 | |
3998 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3999 | blc_event = true; | |
4356d586 DV |
4000 | |
4001 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4002 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4003 | |
1f7247c0 DV |
4004 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4005 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4006 | } |
a266c7d5 CW |
4007 | |
4008 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4009 | intel_opregion_asle_intr(dev); | |
4010 | ||
515ac2bb DV |
4011 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4012 | gmbus_irq_handler(dev); | |
4013 | ||
a266c7d5 CW |
4014 | /* With MSI, interrupts are only generated when iir |
4015 | * transitions from zero to nonzero. If another bit got | |
4016 | * set while we were handling the existing iir bits, then | |
4017 | * we would never get another interrupt. | |
4018 | * | |
4019 | * This is fine on non-MSI as well, as if we hit this path | |
4020 | * we avoid exiting the interrupt handler only to generate | |
4021 | * another one. | |
4022 | * | |
4023 | * Note that for MSI this could cause a stray interrupt report | |
4024 | * if an interrupt landed in the time between writing IIR and | |
4025 | * the posting read. This should be rare enough to never | |
4026 | * trigger the 99% of 100,000 interrupts test for disabling | |
4027 | * stray interrupts. | |
4028 | */ | |
4029 | iir = new_iir; | |
4030 | } | |
4031 | ||
4032 | return ret; | |
4033 | } | |
4034 | ||
4035 | static void i965_irq_uninstall(struct drm_device * dev) | |
4036 | { | |
2d1013dd | 4037 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4038 | int pipe; |
4039 | ||
4040 | if (!dev_priv) | |
4041 | return; | |
4042 | ||
adca4730 CW |
4043 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
4044 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
4045 | |
4046 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4047 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4048 | I915_WRITE(PIPESTAT(pipe), 0); |
4049 | I915_WRITE(IMR, 0xffffffff); | |
4050 | I915_WRITE(IER, 0x0); | |
4051 | ||
055e393f | 4052 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4053 | I915_WRITE(PIPESTAT(pipe), |
4054 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4055 | I915_WRITE(IIR, I915_READ(IIR)); | |
4056 | } | |
4057 | ||
fca52a55 DV |
4058 | /** |
4059 | * intel_irq_init - initializes irq support | |
4060 | * @dev_priv: i915 device instance | |
4061 | * | |
4062 | * This function initializes all the irq support including work items, timers | |
4063 | * and all the vtables. It does not setup the interrupt itself though. | |
4064 | */ | |
b963291c | 4065 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4066 | { |
b963291c | 4067 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4068 | |
77913b39 JN |
4069 | intel_hpd_init_work(dev_priv); |
4070 | ||
c6a828d3 | 4071 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4072 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4073 | |
a6706b45 | 4074 | /* Let's track the enabled rps events */ |
b963291c | 4075 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4076 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4077 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4078 | else |
4079 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4080 | |
737b1506 CW |
4081 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4082 | i915_hangcheck_elapsed); | |
61bac78e | 4083 | |
97a19a24 | 4084 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4085 | |
b963291c | 4086 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4087 | dev->max_vblank_count = 0; |
4088 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4089 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4090 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4091 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4092 | } else { |
4093 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4094 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4095 | } |
4096 | ||
21da2700 VS |
4097 | /* |
4098 | * Opt out of the vblank disable timer on everything except gen2. | |
4099 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4100 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4101 | */ | |
b963291c | 4102 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4103 | dev->vblank_disable_immediate = true; |
4104 | ||
f3a5c3f6 DV |
4105 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4106 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4107 | |
b963291c | 4108 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4109 | dev->driver->irq_handler = cherryview_irq_handler; |
4110 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4111 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4112 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4113 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4114 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4115 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4116 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4117 | dev->driver->irq_handler = valleyview_irq_handler; |
4118 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4119 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4120 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4121 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4122 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4123 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4124 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4125 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4126 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4127 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4128 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4129 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4130 | dev->driver->disable_vblank = gen8_disable_vblank; | |
e0a20ad7 SS |
4131 | if (HAS_PCH_SPLIT(dev)) |
4132 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
4133 | else | |
4134 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; | |
f71d4af4 JB |
4135 | } else if (HAS_PCH_SPLIT(dev)) { |
4136 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4137 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4138 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4139 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4140 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4141 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4142 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4143 | } else { |
b963291c | 4144 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4145 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4146 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4147 | dev->driver->irq_handler = i8xx_irq_handler; | |
4148 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4149 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4150 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4151 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4152 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4153 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4154 | } else { |
a266c7d5 CW |
4155 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4156 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4157 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4158 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4159 | } |
778eb334 VS |
4160 | if (I915_HAS_HOTPLUG(dev_priv)) |
4161 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4162 | dev->driver->enable_vblank = i915_enable_vblank; |
4163 | dev->driver->disable_vblank = i915_disable_vblank; | |
4164 | } | |
4165 | } | |
20afbda2 | 4166 | |
fca52a55 DV |
4167 | /** |
4168 | * intel_irq_install - enables the hardware interrupt | |
4169 | * @dev_priv: i915 device instance | |
4170 | * | |
4171 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4172 | * handling still disabled. It is called after intel_irq_init(). | |
4173 | * | |
4174 | * In the driver load and resume code we need working interrupts in a few places | |
4175 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4176 | * workers. Hence the split into this two-stage approach. | |
4177 | */ | |
2aeb7d3a DV |
4178 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4179 | { | |
4180 | /* | |
4181 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4182 | * interrupts as enabled _before_ actually enabling them to avoid | |
4183 | * special cases in our ordering checks. | |
4184 | */ | |
4185 | dev_priv->pm.irqs_enabled = true; | |
4186 | ||
4187 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4188 | } | |
4189 | ||
fca52a55 DV |
4190 | /** |
4191 | * intel_irq_uninstall - finilizes all irq handling | |
4192 | * @dev_priv: i915 device instance | |
4193 | * | |
4194 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4195 | * resources acquired in the init functions. | |
4196 | */ | |
2aeb7d3a DV |
4197 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4198 | { | |
4199 | drm_irq_uninstall(dev_priv->dev); | |
4200 | intel_hpd_cancel_work(dev_priv); | |
4201 | dev_priv->pm.irqs_enabled = false; | |
4202 | } | |
4203 | ||
fca52a55 DV |
4204 | /** |
4205 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4206 | * @dev_priv: i915 device instance | |
4207 | * | |
4208 | * This function is used to disable interrupts at runtime, both in the runtime | |
4209 | * pm and the system suspend/resume code. | |
4210 | */ | |
b963291c | 4211 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4212 | { |
b963291c | 4213 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4214 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4215 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4216 | } |
4217 | ||
fca52a55 DV |
4218 | /** |
4219 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4220 | * @dev_priv: i915 device instance | |
4221 | * | |
4222 | * This function is used to enable interrupts at runtime, both in the runtime | |
4223 | * pm and the system suspend/resume code. | |
4224 | */ | |
b963291c | 4225 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4226 | { |
2aeb7d3a | 4227 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4228 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4229 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4230 | } |