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drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
cd569aed
EE		 91static void ibx_hpd_irq_setup(struct drm_device *dev);
92static void i915_hpd_irq_setup(struct drm_device *dev);
e5868a31 93
036a4a7d 94/* For display hotplug interrupt */
995b6762 95static void
f2b115e6 96ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
1ec14ad3
CW		 98 if ((dev_priv->irq_mask & mask) != 0) {
99 dev_priv->irq_mask &= ~mask;
100 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 101 POSTING_READ(DEIMR);
036a4a7d
ZW		 102 }
103}
104
0ff9800a 105static void
f2b115e6 106ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 107{
1ec14ad3
CW		 108 if ((dev_priv->irq_mask & mask) != mask) {
109 dev_priv->irq_mask |= mask;
110 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 111 POSTING_READ(DEIMR);
036a4a7d
ZW		 112 }
113}
114
8664281b
PZ		 115static bool ivb_can_enable_err_int(struct drm_device *dev)
116{
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct intel_crtc *crtc;
119 enum pipe pipe;
120
121 for_each_pipe(pipe) {
122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
123
124 if (crtc->cpu_fifo_underrun_disabled)
125 return false;
126 }
127
128 return true;
129}
130
131static bool cpt_can_enable_serr_int(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 enum pipe pipe;
135 struct intel_crtc *crtc;
136
137 for_each_pipe(pipe) {
138 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
139
140 if (crtc->pch_fifo_underrun_disabled)
141 return false;
142 }
143
144 return true;
145}
146
147static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
148 enum pipe pipe, bool enable)
149{
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
152 DE_PIPEB_FIFO_UNDERRUN;
153
154 if (enable)
155 ironlake_enable_display_irq(dev_priv, bit);
156 else
157 ironlake_disable_display_irq(dev_priv, bit);
158}
159
160static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
161 bool enable)
162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 if (enable) {
166 if (!ivb_can_enable_err_int(dev))
167 return;
168
169 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
170 ERR_INT_FIFO_UNDERRUN_B |
171 ERR_INT_FIFO_UNDERRUN_C);
172
173 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
174 } else {
175 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
176 }
177}
178
179static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
180 bool enable)
181{
182 struct drm_device *dev = crtc->base.dev;
183 struct drm_i915_private *dev_priv = dev->dev_private;
184 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
185 SDE_TRANSB_FIFO_UNDER;
186
187 if (enable)
188 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
189 else
190 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
191
192 POSTING_READ(SDEIMR);
193}
194
195static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
196 enum transcoder pch_transcoder,
197 bool enable)
198{
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
201 if (enable) {
202 if (!cpt_can_enable_serr_int(dev))
203 return;
204
205 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
206 SERR_INT_TRANS_B_FIFO_UNDERRUN |
207 SERR_INT_TRANS_C_FIFO_UNDERRUN);
208
209 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
210 } else {
211 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
212 }
213
214 POSTING_READ(SDEIMR);
215}
216
217/**
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
219 * @dev: drm device
220 * @pipe: pipe
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
222 *
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
228 *
229 * Returns the previous state of underrun reporting.
230 */
231bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
232 enum pipe pipe, bool enable)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
237 unsigned long flags;
238 bool ret;
239
240 spin_lock_irqsave(&dev_priv->irq_lock, flags);
241
242 ret = !intel_crtc->cpu_fifo_underrun_disabled;
243
244 if (enable == ret)
245 goto done;
246
247 intel_crtc->cpu_fifo_underrun_disabled = !enable;
248
249 if (IS_GEN5(dev) || IS_GEN6(dev))
250 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
251 else if (IS_GEN7(dev))
252 ivybridge_set_fifo_underrun_reporting(dev, enable);
253
254done:
255 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
256 return ret;
257}
258
259/**
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
261 * @dev: drm device
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
264 *
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
270 *
271 * Returns the previous state of underrun reporting.
272 */
273bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
275 bool enable)
276{
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 enum pipe p;
279 struct drm_crtc *crtc;
280 struct intel_crtc *intel_crtc;
281 unsigned long flags;
282 bool ret;
283
284 if (HAS_PCH_LPT(dev)) {
285 crtc = NULL;
286 for_each_pipe(p) {
287 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
288 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
289 crtc = c;
290 break;
291 }
292 }
293 if (!crtc) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
295 return false;
296 }
297 } else {
298 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
299 }
300 intel_crtc = to_intel_crtc(crtc);
301
302 spin_lock_irqsave(&dev_priv->irq_lock, flags);
303
304 ret = !intel_crtc->pch_fifo_underrun_disabled;
305
306 if (enable == ret)
307 goto done;
308
309 intel_crtc->pch_fifo_underrun_disabled = !enable;
310
311 if (HAS_PCH_IBX(dev))
312 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
313 else
314 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
315
316done:
317 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318 return ret;
319}
320
321
7c463586
KP		 322void
323i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
324{
46c06a30
VS		 325 u32 reg = PIPESTAT(pipe);
326 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 327
46c06a30
VS		 328 if ((pipestat & mask) == mask)
329 return;
330
331 /* Enable the interrupt, clear any pending status */
332 pipestat |= mask | (mask >> 16);
333 I915_WRITE(reg, pipestat);
334 POSTING_READ(reg);
7c463586
KP		 335}
336
337void
338i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
339{
46c06a30
VS		 340 u32 reg = PIPESTAT(pipe);
341 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 342
46c06a30
VS		 343 if ((pipestat & mask) == 0)
344 return;
345
346 pipestat &= ~mask;
347 I915_WRITE(reg, pipestat);
348 POSTING_READ(reg);
7c463586
KP		 349}
350
01c66889 351/**
f49e38dd 352 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 353 */
f49e38dd 354static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 355{
1ec14ad3
CW		 356 drm_i915_private_t *dev_priv = dev->dev_private;
357 unsigned long irqflags;
358
f49e38dd
JN		 359 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
360 return;
361
1ec14ad3 362 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 363
f898780b
JN		 364 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
365 if (INTEL_INFO(dev)->gen >= 4)
366 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 367
368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 369}
370
0a3e67a4
JB		 371/**
372 * i915_pipe_enabled - check if a pipe is enabled
373 * @dev: DRM device
374 * @pipe: pipe to check
375 *
376 * Reading certain registers when the pipe is disabled can hang the chip.
377 * Use this routine to make sure the PLL is running and the pipe is active
378 * before reading such registers if unsure.
379 */
380static int
381i915_pipe_enabled(struct drm_device *dev, int pipe)
382{
383 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 384 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
385 pipe);
386
387 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 388}
389
42f52ef8
KP		 390/* Called from drm generic code, passed a 'crtc', which
391 * we use as a pipe index
392 */
f71d4af4 393static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 394{
395 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
396 unsigned long high_frame;
397 unsigned long low_frame;
5eddb70b 398 u32 high1, high2, low;
0a3e67a4
JB		 399
400 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 401 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 402 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 403 return 0;
404 }
405
9db4a9c7
JB		 406 high_frame = PIPEFRAME(pipe);
407 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 408
0a3e67a4
JB		 409 /*
410 * High & low register fields aren't synchronized, so make sure
411 * we get a low value that's stable across two reads of the high
412 * register.
413 */
414 do {
5eddb70b
CW		 415 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
416 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
417 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 418 } while (high1 != high2);
419
5eddb70b
CW		 420 high1 >>= PIPE_FRAME_HIGH_SHIFT;
421 low >>= PIPE_FRAME_LOW_SHIFT;
422 return (high1 << 8) | low;
0a3e67a4
JB		 423}
424
f71d4af4 425static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 426{
427 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 428 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 429
430 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 431 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 432 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 433 return 0;
434 }
435
436 return I915_READ(reg);
437}
438
f71d4af4 439static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 440 int *vpos, int *hpos)
441{
442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
443 u32 vbl = 0, position = 0;
444 int vbl_start, vbl_end, htotal, vtotal;
445 bool in_vbl = true;
446 int ret = 0;
fe2b8f9d
PZ		 447 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
448 pipe);
0af7e4df
MK		 449
450 if (!i915_pipe_enabled(dev, pipe)) {
451 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 452 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 453 return 0;
454 }
455
456 /* Get vtotal. */
fe2b8f9d 457 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 458
459 if (INTEL_INFO(dev)->gen >= 4) {
460 /* No obvious pixelcount register. Only query vertical
461 * scanout position from Display scan line register.
462 */
463 position = I915_READ(PIPEDSL(pipe));
464
465 /* Decode into vertical scanout position. Don't have
466 * horizontal scanout position.
467 */
468 *vpos = position & 0x1fff;
469 *hpos = 0;
470 } else {
471 /* Have access to pixelcount since start of frame.
472 * We can split this into vertical and horizontal
473 * scanout position.
474 */
475 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
476
fe2b8f9d 477 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 478 *vpos = position / htotal;
479 *hpos = position - (*vpos * htotal);
480 }
481
482 /* Query vblank area. */
fe2b8f9d 483 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 484
485 /* Test position against vblank region. */
486 vbl_start = vbl & 0x1fff;
487 vbl_end = (vbl >> 16) & 0x1fff;
488
489 if ((*vpos < vbl_start) || (*vpos > vbl_end))
490 in_vbl = false;
491
492 /* Inside "upper part" of vblank area? Apply corrective offset: */
493 if (in_vbl && (*vpos >= vbl_start))
494 *vpos = *vpos - vtotal;
495
496 /* Readouts valid? */
497 if (vbl > 0)
498 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
499
500 /* In vblank? */
501 if (in_vbl)
502 ret |= DRM_SCANOUTPOS_INVBL;
503
504 return ret;
505}
506
f71d4af4 507static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 508 int *max_error,
509 struct timeval *vblank_time,
510 unsigned flags)
511{
4041b853 512 struct drm_crtc *crtc;
0af7e4df 513
7eb552ae 514 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 515 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 516 return -EINVAL;
517 }
518
519 /* Get drm_crtc to timestamp: */
4041b853
CW		 520 crtc = intel_get_crtc_for_pipe(dev, pipe);
521 if (crtc == NULL) {
522 DRM_ERROR("Invalid crtc %d\n", pipe);
523 return -EINVAL;
524 }
525
526 if (!crtc->enabled) {
527 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
528 return -EBUSY;
529 }
0af7e4df
MK		 530
531 /* Helper routine in DRM core does all the work: */
4041b853
CW		 532 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
533 vblank_time, flags,
534 crtc);
0af7e4df
MK		 535}
536
321a1b30
EE		 537static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
538{
539 enum drm_connector_status old_status;
540
541 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
542 old_status = connector->status;
543
544 connector->status = connector->funcs->detect(connector, false);
545 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
546 connector->base.id,
547 drm_get_connector_name(connector),
548 old_status, connector->status);
549 return (old_status != connector->status);
550}
551
5ca58282
JB		 552/*
553 * Handle hotplug events outside the interrupt handler proper.
554 */
ac4c16c5
EE		 555#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
556
5ca58282
JB		 557static void i915_hotplug_work_func(struct work_struct *work)
558{
559 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
560 hotplug_work);
561 struct drm_device *dev = dev_priv->dev;
c31c4ba3 562 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 563 struct intel_connector *intel_connector;
564 struct intel_encoder *intel_encoder;
565 struct drm_connector *connector;
566 unsigned long irqflags;
567 bool hpd_disabled = false;
321a1b30 568 bool changed = false;
142e2398 569 u32 hpd_event_bits;
4ef69c7a 570
52d7eced
DV		 571 /* HPD irq before everything is fully set up. */
572 if (!dev_priv->enable_hotplug_processing)
573 return;
574
a65e34c7 575 mutex_lock(&mode_config->mutex);
e67189ab
JB		 576 DRM_DEBUG_KMS("running encoder hotplug functions\n");
577
cd569aed 578 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 579
580 hpd_event_bits = dev_priv->hpd_event_bits;
581 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 582 list_for_each_entry(connector, &mode_config->connector_list, head) {
583 intel_connector = to_intel_connector(connector);
584 intel_encoder = intel_connector->encoder;
585 if (intel_encoder->hpd_pin > HPD_NONE &&
586 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
587 connector->polled == DRM_CONNECTOR_POLL_HPD) {
588 DRM_INFO("HPD interrupt storm detected on connector %s: "
589 "switching from hotplug detection to polling\n",
590 drm_get_connector_name(connector));
591 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
592 connector->polled = DRM_CONNECTOR_POLL_CONNECT
593 | DRM_CONNECTOR_POLL_DISCONNECT;
594 hpd_disabled = true;
595 }
142e2398
EE		 596 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
597 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
598 drm_get_connector_name(connector), intel_encoder->hpd_pin);
599 }
cd569aed
EE		 600 }
601 /* if there were no outputs to poll, poll was disabled,
602 * therefore make sure it's enabled when disabling HPD on
603 * some connectors */
ac4c16c5 604 if (hpd_disabled) {
cd569aed 605 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 606 mod_timer(&dev_priv->hotplug_reenable_timer,
607 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
608 }
cd569aed
EE		 609
610 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
611
321a1b30
EE		 612 list_for_each_entry(connector, &mode_config->connector_list, head) {
613 intel_connector = to_intel_connector(connector);
614 intel_encoder = intel_connector->encoder;
615 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
616 if (intel_encoder->hot_plug)
617 intel_encoder->hot_plug(intel_encoder);
618 if (intel_hpd_irq_event(dev, connector))
619 changed = true;
620 }
621 }
40ee3381
KP		 622 mutex_unlock(&mode_config->mutex);
623
321a1b30
EE		 624 if (changed)
625 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 626}
627
73edd18f 628static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 629{
630 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 631 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 632 u8 new_delay;
633 unsigned long flags;
634
635 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 636
73edd18f
DV		 637 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
638
20e4d407 639 new_delay = dev_priv->ips.cur_delay;
9270388e 640
7648fa99 641 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 642 busy_up = I915_READ(RCPREVBSYTUPAVG);
643 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 644 max_avg = I915_READ(RCBMAXAVG);
645 min_avg = I915_READ(RCBMINAVG);
646
647 /* Handle RCS change request from hw */
b5b72e89 648 if (busy_up > max_avg) {
20e4d407
DV		 649 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
650 new_delay = dev_priv->ips.cur_delay - 1;
651 if (new_delay < dev_priv->ips.max_delay)
652 new_delay = dev_priv->ips.max_delay;
b5b72e89 653 } else if (busy_down < min_avg) {
20e4d407
DV		 654 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
655 new_delay = dev_priv->ips.cur_delay + 1;
656 if (new_delay > dev_priv->ips.min_delay)
657 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 658 }
659
7648fa99 660 if (ironlake_set_drps(dev, new_delay))
20e4d407 661 dev_priv->ips.cur_delay = new_delay;
f97108d1 662
9270388e
DV		 663 spin_unlock_irqrestore(&mchdev_lock, flags);
664
f97108d1
JB		 665 return;
666}
667
549f7365
CW		 668static void notify_ring(struct drm_device *dev,
669 struct intel_ring_buffer *ring)
670{
671 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 672
475553de
CW		 673 if (ring->obj == NULL)
674 return;
675
b2eadbc8 676 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 677
549f7365 678 wake_up_all(&ring->irq_queue);
3e0dc6b0 679 if (i915_enable_hangcheck) {
99584db3
DV		 680 dev_priv->gpu_error.hangcheck_count = 0;
681 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 682 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 683 }
549f7365
CW		 684}
685
4912d041 686static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 687{
4912d041 688 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 689 rps.work);
4912d041 690 u32 pm_iir, pm_imr;
7b9e0ae6 691 u8 new_delay;
4912d041 692
c6a828d3
DV		 693 spin_lock_irq(&dev_priv->rps.lock);
694 pm_iir = dev_priv->rps.pm_iir;
695 dev_priv->rps.pm_iir = 0;
4912d041 696 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 697 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 698 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 699
7b9e0ae6 700 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 701 return;
702
4fc688ce 703 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 704
705 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 706 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 707 else
c6a828d3 708 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 709
79249636
BW		 710 /* sysfs frequency interfaces may have snuck in while servicing the
711 * interrupt
712 */
713 if (!(new_delay > dev_priv->rps.max_delay ||
714 new_delay < dev_priv->rps.min_delay)) {
0a073b84
JB		 715 if (IS_VALLEYVIEW(dev_priv->dev))
716 valleyview_set_rps(dev_priv->dev, new_delay);
717 else
718 gen6_set_rps(dev_priv->dev, new_delay);
79249636 719 }
3b8d8d91 720
52ceb908
JB		 721 if (IS_VALLEYVIEW(dev_priv->dev)) {
722 /*
723 * On VLV, when we enter RC6 we may not be at the minimum
724 * voltage level, so arm a timer to check. It should only
725 * fire when there's activity or once after we've entered
726 * RC6, and then won't be re-armed until the next RPS interrupt.
727 */
728 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
729 msecs_to_jiffies(100));
730 }
731
4fc688ce 732 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 733}
734
e3689190
BW		 735
736/**
737 * ivybridge_parity_work - Workqueue called when a parity error interrupt
738 * occurred.
739 * @work: workqueue struct
740 *
741 * Doesn't actually do anything except notify userspace. As a consequence of
742 * this event, userspace should try to remap the bad rows since statistically
743 * it is likely the same row is more likely to go bad again.
744 */
745static void ivybridge_parity_work(struct work_struct *work)
746{
747 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 748 l3_parity.error_work);
e3689190
BW		 749 u32 error_status, row, bank, subbank;
750 char *parity_event[5];
751 uint32_t misccpctl;
752 unsigned long flags;
753
754 /* We must turn off DOP level clock gating to access the L3 registers.
755 * In order to prevent a get/put style interface, acquire struct mutex
756 * any time we access those registers.
757 */
758 mutex_lock(&dev_priv->dev->struct_mutex);
759
760 misccpctl = I915_READ(GEN7_MISCCPCTL);
761 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
762 POSTING_READ(GEN7_MISCCPCTL);
763
764 error_status = I915_READ(GEN7_L3CDERRST1);
765 row = GEN7_PARITY_ERROR_ROW(error_status);
766 bank = GEN7_PARITY_ERROR_BANK(error_status);
767 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
768
769 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
770 GEN7_L3CDERRST1_ENABLE);
771 POSTING_READ(GEN7_L3CDERRST1);
772
773 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
774
775 spin_lock_irqsave(&dev_priv->irq_lock, flags);
776 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
777 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
778 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
779
780 mutex_unlock(&dev_priv->dev->struct_mutex);
781
782 parity_event[0] = "L3_PARITY_ERROR=1";
783 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
784 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
785 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
786 parity_event[4] = NULL;
787
788 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
789 KOBJ_CHANGE, parity_event);
790
791 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
792 row, bank, subbank);
793
794 kfree(parity_event[3]);
795 kfree(parity_event[2]);
796 kfree(parity_event[1]);
797}
798
d2ba8470 799static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 800{
801 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
802 unsigned long flags;
803
e1ef7cc2 804 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 805 return;
806
807 spin_lock_irqsave(&dev_priv->irq_lock, flags);
808 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
809 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
810 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
811
a4da4fa4 812 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 813}
814
e7b4c6b1
DV		 815static void snb_gt_irq_handler(struct drm_device *dev,
816 struct drm_i915_private *dev_priv,
817 u32 gt_iir)
818{
819
820 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
821 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
822 notify_ring(dev, &dev_priv->ring[RCS]);
823 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
824 notify_ring(dev, &dev_priv->ring[VCS]);
825 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
826 notify_ring(dev, &dev_priv->ring[BCS]);
827
828 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
829 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
830 GT_RENDER_CS_ERROR_INTERRUPT)) {
831 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
832 i915_handle_error(dev, false);
833 }
e3689190
BW		 834
835 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
836 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 837}
838
fc6826d1
CW		 839static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
840 u32 pm_iir)
841{
842 unsigned long flags;
843
844 /*
845 * IIR bits should never already be set because IMR should
846 * prevent an interrupt from being shown in IIR. The warning
847 * displays a case where we've unsafely cleared
c6a828d3 848 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 849 * type is not a problem, it displays a problem in the logic.
850 *
c6a828d3 851 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 852 */
853
c6a828d3 854 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 855 dev_priv->rps.pm_iir |= pm_iir;
856 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 857 POSTING_READ(GEN6_PMIMR);
c6a828d3 858 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 859
c6a828d3 860 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 861}
862
b543fb04
EE		 863#define HPD_STORM_DETECT_PERIOD 1000
864#define HPD_STORM_THRESHOLD 5
865
cd569aed 866static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
b543fb04
EE		 867 u32 hotplug_trigger,
868 const u32 *hpd)
869{
870 drm_i915_private_t *dev_priv = dev->dev_private;
871 unsigned long irqflags;
872 int i;
cd569aed 873 bool ret = false;
b543fb04
EE		 874
875 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
876
877 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 878
b543fb04
EE		 879 if (!(hpd[i] & hotplug_trigger) ||
880 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
142e2398 881 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 882 continue;
883
884 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
885 dev_priv->hpd_stats[i].hpd_last_jiffies
886 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
887 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
888 dev_priv->hpd_stats[i].hpd_cnt = 0;
889 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
890 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 891 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 892 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
cd569aed 893 ret = true;
b543fb04
EE		 894 } else {
895 dev_priv->hpd_stats[i].hpd_cnt++;
896 }
897 }
898
899 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
cd569aed
EE		 900
901 return ret;
b543fb04
EE		 902}
903
515ac2bb
DV		 904static void gmbus_irq_handler(struct drm_device *dev)
905{
28c70f16
DV		 906 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
907
28c70f16 908 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 909}
910
ce99c256
DV		 911static void dp_aux_irq_handler(struct drm_device *dev)
912{
9ee32fea
DV		 913 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
914
9ee32fea 915 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 916}
917
ff1f525e 918static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 919{
920 struct drm_device *dev = (struct drm_device *) arg;
921 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
922 u32 iir, gt_iir, pm_iir;
923 irqreturn_t ret = IRQ_NONE;
924 unsigned long irqflags;
925 int pipe;
926 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 927
928 atomic_inc(&dev_priv->irq_received);
929
7e231dbe
JB		 930 while (true) {
931 iir = I915_READ(VLV_IIR);
932 gt_iir = I915_READ(GTIIR);
933 pm_iir = I915_READ(GEN6_PMIIR);
934
935 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
936 goto out;
937
938 ret = IRQ_HANDLED;
939
e7b4c6b1 940 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 941
942 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
943 for_each_pipe(pipe) {
944 int reg = PIPESTAT(pipe);
945 pipe_stats[pipe] = I915_READ(reg);
946
947 /*
948 * Clear the PIPE*STAT regs before the IIR
949 */
950 if (pipe_stats[pipe] & 0x8000ffff) {
951 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
952 DRM_DEBUG_DRIVER("pipe %c underrun\n",
953 pipe_name(pipe));
954 I915_WRITE(reg, pipe_stats[pipe]);
955 }
956 }
957 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
958
31acc7f5
JB		 959 for_each_pipe(pipe) {
960 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
961 drm_handle_vblank(dev, pipe);
962
963 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
964 intel_prepare_page_flip(dev, pipe);
965 intel_finish_page_flip(dev, pipe);
966 }
967 }
968
7e231dbe
JB		 969 /* Consume port. Then clear IIR or we'll miss events */
970 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
971 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 972 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 973
974 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
975 hotplug_status);
b543fb04 976 if (hotplug_trigger) {
cd569aed
EE		 977 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
978 i915_hpd_irq_setup(dev);
7e231dbe
JB		 979 queue_work(dev_priv->wq,
980 &dev_priv->hotplug_work);
b543fb04 981 }
7e231dbe
JB		 982 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
983 I915_READ(PORT_HOTPLUG_STAT);
984 }
985
515ac2bb
DV		 986 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
987 gmbus_irq_handler(dev);
7e231dbe 988
fc6826d1
CW		 989 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
990 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 991
992 I915_WRITE(GTIIR, gt_iir);
993 I915_WRITE(GEN6_PMIIR, pm_iir);
994 I915_WRITE(VLV_IIR, iir);
995 }
996
997out:
998 return ret;
999}
1000
23e81d69 1001static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1002{
1003 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1004 int pipe;
b543fb04 1005 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1006
b543fb04 1007 if (hotplug_trigger) {
cd569aed
EE		 1008 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
1009 ibx_hpd_irq_setup(dev);
76e43830 1010 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1011 }
cfc33bf7
VS		 1012 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1013 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1014 SDE_AUDIO_POWER_SHIFT);
776ad806 1015 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1016 port_name(port));
1017 }
776ad806 1018
ce99c256
DV		 1019 if (pch_iir & SDE_AUX_MASK)
1020 dp_aux_irq_handler(dev);
1021
776ad806 1022 if (pch_iir & SDE_GMBUS)
515ac2bb 1023 gmbus_irq_handler(dev);
776ad806
JB		 1024
1025 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1026 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1027
1028 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1029 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1030
1031 if (pch_iir & SDE_POISON)
1032 DRM_ERROR("PCH poison interrupt\n");
1033
9db4a9c7
JB		 1034 if (pch_iir & SDE_FDI_MASK)
1035 for_each_pipe(pipe)
1036 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1037 pipe_name(pipe),
1038 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1039
1040 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1041 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1042
1043 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1044 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1045
776ad806 1046 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1047 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1048 false))
1049 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1050
1051 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1052 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1053 false))
1054 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1055}
1056
1057static void ivb_err_int_handler(struct drm_device *dev)
1058{
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 u32 err_int = I915_READ(GEN7_ERR_INT);
1061
de032bf4
PZ		 1062 if (err_int & ERR_INT_POISON)
1063 DRM_ERROR("Poison interrupt\n");
1064
8664281b
PZ		 1065 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1066 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1067 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1068
1069 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1070 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1071 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1072
1073 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1074 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1075 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1076
1077 I915_WRITE(GEN7_ERR_INT, err_int);
1078}
1079
1080static void cpt_serr_int_handler(struct drm_device *dev)
1081{
1082 struct drm_i915_private *dev_priv = dev->dev_private;
1083 u32 serr_int = I915_READ(SERR_INT);
1084
de032bf4
PZ		 1085 if (serr_int & SERR_INT_POISON)
1086 DRM_ERROR("PCH poison interrupt\n");
1087
8664281b
PZ		 1088 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1089 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1090 false))
1091 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1092
1093 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1094 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1095 false))
1096 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1097
1098 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1099 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1100 false))
1101 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1102
1103 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1104}
1105
23e81d69
AJ		 1106static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1107{
1108 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1109 int pipe;
b543fb04 1110 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1111
b543fb04 1112 if (hotplug_trigger) {
cd569aed
EE		 1113 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1114 ibx_hpd_irq_setup(dev);
76e43830 1115 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1116 }
cfc33bf7
VS		 1117 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1118 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1119 SDE_AUDIO_POWER_SHIFT_CPT);
1120 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1121 port_name(port));
1122 }
23e81d69
AJ		 1123
1124 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1125 dp_aux_irq_handler(dev);
23e81d69
AJ		 1126
1127 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1128 gmbus_irq_handler(dev);
23e81d69
AJ		 1129
1130 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1131 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1132
1133 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1134 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1135
1136 if (pch_iir & SDE_FDI_MASK_CPT)
1137 for_each_pipe(pipe)
1138 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1139 pipe_name(pipe),
1140 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1141
1142 if (pch_iir & SDE_ERROR_CPT)
1143 cpt_serr_int_handler(dev);
23e81d69
AJ		 1144}
1145
ff1f525e 1146static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1147{
1148 struct drm_device *dev = (struct drm_device *) arg;
1149 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1150 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1151 irqreturn_t ret = IRQ_NONE;
1152 int i;
b1f14ad0
JB		 1153
1154 atomic_inc(&dev_priv->irq_received);
1155
8664281b
PZ		 1156 /* We get interrupts on unclaimed registers, so check for this before we
1157 * do any I915_{READ,WRITE}. */
1158 if (IS_HASWELL(dev) &&
1159 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1160 DRM_ERROR("Unclaimed register before interrupt\n");
1161 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1162 }
1163
b1f14ad0
JB		 1164 /* disable master interrupt before clearing iir */
1165 de_ier = I915_READ(DEIER);
1166 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1167
44498aea
PZ		 1168 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1169 * interrupts will will be stored on its back queue, and then we'll be
1170 * able to process them after we restore SDEIER (as soon as we restore
1171 * it, we'll get an interrupt if SDEIIR still has something to process
1172 * due to its back queue). */
ab5c608b
BW		 1173 if (!HAS_PCH_NOP(dev)) {
1174 sde_ier = I915_READ(SDEIER);
1175 I915_WRITE(SDEIER, 0);
1176 POSTING_READ(SDEIER);
1177 }
44498aea 1178
8664281b
PZ		 1179 /* On Haswell, also mask ERR_INT because we don't want to risk
1180 * generating "unclaimed register" interrupts from inside the interrupt
1181 * handler. */
1182 if (IS_HASWELL(dev))
1183 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1184
b1f14ad0 1185 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1186 if (gt_iir) {
1187 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1188 I915_WRITE(GTIIR, gt_iir);
1189 ret = IRQ_HANDLED;
b1f14ad0
JB		 1190 }
1191
0e43406b
CW		 1192 de_iir = I915_READ(DEIIR);
1193 if (de_iir) {
8664281b
PZ		 1194 if (de_iir & DE_ERR_INT_IVB)
1195 ivb_err_int_handler(dev);
1196
ce99c256
DV		 1197 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1198 dp_aux_irq_handler(dev);
1199
0e43406b 1200 if (de_iir & DE_GSE_IVB)
81a07809 1201 intel_opregion_asle_intr(dev);
0e43406b
CW		 1202
1203 for (i = 0; i < 3; i++) {
74d44445
DV		 1204 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1205 drm_handle_vblank(dev, i);
0e43406b
CW		 1206 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1207 intel_prepare_page_flip(dev, i);
1208 intel_finish_page_flip_plane(dev, i);
1209 }
0e43406b 1210 }
b615b57a 1211
0e43406b 1212 /* check event from PCH */
ab5c608b 1213 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1214 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1215
23e81d69 1216 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1217
0e43406b
CW		 1218 /* clear PCH hotplug event before clear CPU irq */
1219 I915_WRITE(SDEIIR, pch_iir);
1220 }
b615b57a 1221
0e43406b
CW		 1222 I915_WRITE(DEIIR, de_iir);
1223 ret = IRQ_HANDLED;
b1f14ad0
JB		 1224 }
1225
0e43406b
CW		 1226 pm_iir = I915_READ(GEN6_PMIIR);
1227 if (pm_iir) {
1228 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
1229 gen6_queue_rps_work(dev_priv, pm_iir);
1230 I915_WRITE(GEN6_PMIIR, pm_iir);
1231 ret = IRQ_HANDLED;
1232 }
b1f14ad0 1233
8664281b
PZ		 1234 if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1235 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1236
b1f14ad0
JB		 1237 I915_WRITE(DEIER, de_ier);
1238 POSTING_READ(DEIER);
ab5c608b
BW		 1239 if (!HAS_PCH_NOP(dev)) {
1240 I915_WRITE(SDEIER, sde_ier);
1241 POSTING_READ(SDEIER);
1242 }
b1f14ad0
JB		 1243
1244 return ret;
1245}
1246
e7b4c6b1
DV		 1247static void ilk_gt_irq_handler(struct drm_device *dev,
1248 struct drm_i915_private *dev_priv,
1249 u32 gt_iir)
1250{
1251 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
1252 notify_ring(dev, &dev_priv->ring[RCS]);
1253 if (gt_iir & GT_BSD_USER_INTERRUPT)
1254 notify_ring(dev, &dev_priv->ring[VCS]);
1255}
1256
ff1f525e 1257static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1258{
4697995b 1259 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1260 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1261 int ret = IRQ_NONE;
44498aea 1262 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1263
4697995b
JB		 1264 atomic_inc(&dev_priv->irq_received);
1265
2d109a84
ZN		 1266 /* disable master interrupt before clearing iir */
1267 de_ier = I915_READ(DEIER);
1268 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1269 POSTING_READ(DEIER);
2d109a84 1270
44498aea
PZ		 1271 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1272 * interrupts will will be stored on its back queue, and then we'll be
1273 * able to process them after we restore SDEIER (as soon as we restore
1274 * it, we'll get an interrupt if SDEIIR still has something to process
1275 * due to its back queue). */
1276 sde_ier = I915_READ(SDEIER);
1277 I915_WRITE(SDEIER, 0);
1278 POSTING_READ(SDEIER);
1279
036a4a7d
ZW		 1280 de_iir = I915_READ(DEIIR);
1281 gt_iir = I915_READ(GTIIR);
3b8d8d91 1282 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1283
acd15b6c 1284 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1285 goto done;
036a4a7d 1286
c7c85101 1287 ret = IRQ_HANDLED;
036a4a7d 1288
e7b4c6b1
DV		 1289 if (IS_GEN5(dev))
1290 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1291 else
1292 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1293
ce99c256
DV		 1294 if (de_iir & DE_AUX_CHANNEL_A)
1295 dp_aux_irq_handler(dev);
1296
c7c85101 1297 if (de_iir & DE_GSE)
81a07809 1298 intel_opregion_asle_intr(dev);
c650156a 1299
74d44445
DV		 1300 if (de_iir & DE_PIPEA_VBLANK)
1301 drm_handle_vblank(dev, 0);
1302
1303 if (de_iir & DE_PIPEB_VBLANK)
1304 drm_handle_vblank(dev, 1);
1305
de032bf4
PZ		 1306 if (de_iir & DE_POISON)
1307 DRM_ERROR("Poison interrupt\n");
1308
8664281b
PZ		 1309 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1310 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1311 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1312
1313 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1314 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1315 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1316
f072d2e7 1317 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1318 intel_prepare_page_flip(dev, 0);
2bbda389 1319 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1320 }
013d5aa2 1321
f072d2e7 1322 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1323 intel_prepare_page_flip(dev, 1);
2bbda389 1324 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1325 }
013d5aa2 1326
c7c85101 1327 /* check event from PCH */
776ad806 1328 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1329 u32 pch_iir = I915_READ(SDEIIR);
1330
23e81d69
AJ		 1331 if (HAS_PCH_CPT(dev))
1332 cpt_irq_handler(dev, pch_iir);
1333 else
1334 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1335
1336 /* should clear PCH hotplug event before clear CPU irq */
1337 I915_WRITE(SDEIIR, pch_iir);
776ad806 1338 }
036a4a7d 1339
73edd18f
DV		 1340 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1341 ironlake_handle_rps_change(dev);
f97108d1 1342
fc6826d1
CW		 1343 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
1344 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1345
c7c85101
ZN		 1346 I915_WRITE(GTIIR, gt_iir);
1347 I915_WRITE(DEIIR, de_iir);
4912d041 1348 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1349
1350done:
2d109a84 1351 I915_WRITE(DEIER, de_ier);
3143a2bf 1352 POSTING_READ(DEIER);
44498aea
PZ		 1353 I915_WRITE(SDEIER, sde_ier);
1354 POSTING_READ(SDEIER);
2d109a84 1355
036a4a7d
ZW		 1356 return ret;
1357}
1358
8a905236
JB		 1359/**
1360 * i915_error_work_func - do process context error handling work
1361 * @work: work struct
1362 *
1363 * Fire an error uevent so userspace can see that a hang or error
1364 * was detected.
1365 */
1366static void i915_error_work_func(struct work_struct *work)
1367{
1f83fee0
DV		 1368 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1369 work);
1370 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1371 gpu_error);
8a905236 1372 struct drm_device *dev = dev_priv->dev;
f69061be 1373 struct intel_ring_buffer *ring;
f316a42c
BG		 1374 char *error_event[] = { "ERROR=1", NULL };
1375 char *reset_event[] = { "RESET=1", NULL };
1376 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1377 int i, ret;
8a905236 1378
f316a42c
BG		 1379 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1380
7db0ba24
DV		 1381 /*
1382 * Note that there's only one work item which does gpu resets, so we
1383 * need not worry about concurrent gpu resets potentially incrementing
1384 * error->reset_counter twice. We only need to take care of another
1385 * racing irq/hangcheck declaring the gpu dead for a second time. A
1386 * quick check for that is good enough: schedule_work ensures the
1387 * correct ordering between hang detection and this work item, and since
1388 * the reset in-progress bit is only ever set by code outside of this
1389 * work we don't need to worry about any other races.
1390 */
1391 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1392 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1393 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1394 reset_event);
1f83fee0 1395
f69061be
DV		 1396 ret = i915_reset(dev);
1397
1398 if (ret == 0) {
1399 /*
1400 * After all the gem state is reset, increment the reset
1401 * counter and wake up everyone waiting for the reset to
1402 * complete.
1403 *
1404 * Since unlock operations are a one-sided barrier only,
1405 * we need to insert a barrier here to order any seqno
1406 * updates before
1407 * the counter increment.
1408 */
1409 smp_mb__before_atomic_inc();
1410 atomic_inc(&dev_priv->gpu_error.reset_counter);
1411
1412 kobject_uevent_env(&dev->primary->kdev.kobj,
1413 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1414 } else {
1415 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1416 }
1f83fee0 1417
f69061be
DV		 1418 for_each_ring(ring, dev_priv, i)
1419 wake_up_all(&ring->irq_queue);
1420
96a02917
VS		 1421 intel_display_handle_reset(dev);
1422
1f83fee0 1423 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1424 }
8a905236
JB		 1425}
1426
85f9e50d
DV		 1427/* NB: please notice the memset */
1428static void i915_get_extra_instdone(struct drm_device *dev,
1429 uint32_t *instdone)
1430{
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1433
1434 switch(INTEL_INFO(dev)->gen) {
1435 case 2:
1436 case 3:
1437 instdone[0] = I915_READ(INSTDONE);
1438 break;
1439 case 4:
1440 case 5:
1441 case 6:
1442 instdone[0] = I915_READ(INSTDONE_I965);
1443 instdone[1] = I915_READ(INSTDONE1);
1444 break;
1445 default:
1446 WARN_ONCE(1, "Unsupported platform\n");
1447 case 7:
1448 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1449 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1450 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1451 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1452 break;
1453 }
1454}
1455
3bd3c932 1456#ifdef CONFIG_DEBUG_FS
9df30794 1457static struct drm_i915_error_object *
d0d045e8
BW		 1458i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1459 struct drm_i915_gem_object *src,
1460 const int num_pages)
9df30794
CW		 1461{
1462 struct drm_i915_error_object *dst;
d0d045e8 1463 int i;
e56660dd 1464 u32 reloc_offset;
9df30794 1465
05394f39 1466 if (src == NULL || src->pages == NULL)
9df30794
CW		 1467 return NULL;
1468
d0d045e8 1469 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1470 if (dst == NULL)
1471 return NULL;
1472
05394f39 1473 reloc_offset = src->gtt_offset;
d0d045e8 1474 for (i = 0; i < num_pages; i++) {
788885ae 1475 unsigned long flags;
e56660dd 1476 void *d;
788885ae 1477
e56660dd 1478 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1479 if (d == NULL)
1480 goto unwind;
e56660dd 1481
788885ae 1482 local_irq_save(flags);
5d4545ae 1483 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1484 src->has_global_gtt_mapping) {
172975aa
CW		 1485 void __iomem *s;
1486
1487 /* Simply ignore tiling or any overlapping fence.
1488 * It's part of the error state, and this hopefully
1489 * captures what the GPU read.
1490 */
1491
5d4545ae 1492 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1493 reloc_offset);
1494 memcpy_fromio(d, s, PAGE_SIZE);
1495 io_mapping_unmap_atomic(s);
960e3564
CW		 1496 } else if (src->stolen) {
1497 unsigned long offset;
1498
1499 offset = dev_priv->mm.stolen_base;
1500 offset += src->stolen->start;
1501 offset += i << PAGE_SHIFT;
1502
1a240d4d 1503 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1504 } else {
9da3da66 1505 struct page *page;
172975aa
CW		 1506 void *s;
1507
9da3da66 1508 page = i915_gem_object_get_page(src, i);
172975aa 1509
9da3da66
CW		 1510 drm_clflush_pages(&page, 1);
1511
1512 s = kmap_atomic(page);
172975aa
CW		 1513 memcpy(d, s, PAGE_SIZE);
1514 kunmap_atomic(s);
1515
9da3da66 1516 drm_clflush_pages(&page, 1);
172975aa 1517 }
788885ae 1518 local_irq_restore(flags);
e56660dd 1519
9da3da66 1520 dst->pages[i] = d;
e56660dd
CW		 1521
1522 reloc_offset += PAGE_SIZE;
9df30794 1523 }
d0d045e8 1524 dst->page_count = num_pages;
05394f39 1525 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1526
1527 return dst;
1528
1529unwind:
9da3da66
CW		 1530 while (i--)
1531 kfree(dst->pages[i]);
9df30794
CW		 1532 kfree(dst);
1533 return NULL;
1534}
d0d045e8
BW		 1535#define i915_error_object_create(dev_priv, src) \
1536 i915_error_object_create_sized((dev_priv), (src), \
1537 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1538
1539static void
1540i915_error_object_free(struct drm_i915_error_object *obj)
1541{
1542 int page;
1543
1544 if (obj == NULL)
1545 return;
1546
1547 for (page = 0; page < obj->page_count; page++)
1548 kfree(obj->pages[page]);
1549
1550 kfree(obj);
1551}
1552
742cbee8
DV		 1553void
1554i915_error_state_free(struct kref *error_ref)
9df30794 1555{
742cbee8
DV		 1556 struct drm_i915_error_state *error = container_of(error_ref,
1557 typeof(*error), ref);
e2f973d5
CW		 1558 int i;
1559
52d39a21
CW		 1560 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1561 i915_error_object_free(error->ring[i].batchbuffer);
1562 i915_error_object_free(error->ring[i].ringbuffer);
1563 kfree(error->ring[i].requests);
1564 }
e2f973d5 1565
9df30794 1566 kfree(error->active_bo);
6ef3d427 1567 kfree(error->overlay);
9df30794
CW		 1568 kfree(error);
1569}
1b50247a
CW		 1570static void capture_bo(struct drm_i915_error_buffer *err,
1571 struct drm_i915_gem_object *obj)
1572{
1573 err->size = obj->base.size;
1574 err->name = obj->base.name;
0201f1ec
CW		 1575 err->rseqno = obj->last_read_seqno;
1576 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1577 err->gtt_offset = obj->gtt_offset;
1578 err->read_domains = obj->base.read_domains;
1579 err->write_domain = obj->base.write_domain;
1580 err->fence_reg = obj->fence_reg;
1581 err->pinned = 0;
1582 if (obj->pin_count > 0)
1583 err->pinned = 1;
1584 if (obj->user_pin_count > 0)
1585 err->pinned = -1;
1586 err->tiling = obj->tiling_mode;
1587 err->dirty = obj->dirty;
1588 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1589 err->ring = obj->ring ? obj->ring->id : -1;
1590 err->cache_level = obj->cache_level;
1591}
9df30794 1592
1b50247a
CW		 1593static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1594 int count, struct list_head *head)
c724e8a9
CW		 1595{
1596 struct drm_i915_gem_object *obj;
1597 int i = 0;
1598
1599 list_for_each_entry(obj, head, mm_list) {
1b50247a 1600 capture_bo(err++, obj);
c724e8a9
CW		 1601 if (++i == count)
1602 break;
1b50247a
CW		 1603 }
1604
1605 return i;
1606}
1607
1608static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1609 int count, struct list_head *head)
1610{
1611 struct drm_i915_gem_object *obj;
1612 int i = 0;
1613
1614 list_for_each_entry(obj, head, gtt_list) {
1615 if (obj->pin_count == 0)
1616 continue;
c724e8a9 1617
1b50247a
CW		 1618 capture_bo(err++, obj);
1619 if (++i == count)
1620 break;
c724e8a9
CW		 1621 }
1622
1623 return i;
1624}
1625
748ebc60
CW		 1626static void i915_gem_record_fences(struct drm_device *dev,
1627 struct drm_i915_error_state *error)
1628{
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 int i;
1631
1632 /* Fences */
1633 switch (INTEL_INFO(dev)->gen) {
775d17b6 1634 case 7:
748ebc60 1635 case 6:
42b5aeab 1636 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1637 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1638 break;
1639 case 5:
1640 case 4:
1641 for (i = 0; i < 16; i++)
1642 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1643 break;
1644 case 3:
1645 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1646 for (i = 0; i < 8; i++)
1647 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1648 case 2:
1649 for (i = 0; i < 8; i++)
1650 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1651 break;
1652
7dbf9d6e
BW		 1653 default:
1654 BUG();
748ebc60
CW		 1655 }
1656}
1657
bcfb2e28
CW		 1658static struct drm_i915_error_object *
1659i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1660 struct intel_ring_buffer *ring)
1661{
1662 struct drm_i915_gem_object *obj;
1663 u32 seqno;
1664
1665 if (!ring->get_seqno)
1666 return NULL;
1667
b45305fc
DV		 1668 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1669 u32 acthd = I915_READ(ACTHD);
1670
1671 if (WARN_ON(ring->id != RCS))
1672 return NULL;
1673
1674 obj = ring->private;
1675 if (acthd >= obj->gtt_offset &&
1676 acthd < obj->gtt_offset + obj->base.size)
1677 return i915_error_object_create(dev_priv, obj);
1678 }
1679
b2eadbc8 1680 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1681 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1682 if (obj->ring != ring)
1683 continue;
1684
0201f1ec 1685 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1686 continue;
1687
1688 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1689 continue;
1690
1691 /* We need to copy these to an anonymous buffer as the simplest
1692 * method to avoid being overwritten by userspace.
1693 */
1694 return i915_error_object_create(dev_priv, obj);
1695 }
1696
1697 return NULL;
1698}
1699
d27b1e0e
DV		 1700static void i915_record_ring_state(struct drm_device *dev,
1701 struct drm_i915_error_state *error,
1702 struct intel_ring_buffer *ring)
1703{
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705
33f3f518 1706 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1707 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1708 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1709 error->semaphore_mboxes[ring->id][0]
1710 = I915_READ(RING_SYNC_0(ring->mmio_base));
1711 error->semaphore_mboxes[ring->id][1]
1712 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1713 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1714 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1715 }
c1cd90ed 1716
d27b1e0e 1717 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1718 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1719 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1720 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1721 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1722 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1723 if (ring->id == RCS)
d27b1e0e 1724 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1725 } else {
9d2f41fa 1726 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1727 error->ipeir[ring->id] = I915_READ(IPEIR);
1728 error->ipehr[ring->id] = I915_READ(IPEHR);
1729 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1730 }
1731
9574b3fe 1732 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1733 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1734 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1735 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1736 error->head[ring->id] = I915_READ_HEAD(ring);
1737 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1738 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1739
1740 error->cpu_ring_head[ring->id] = ring->head;
1741 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1742}
1743
8c123e54
BW		 1744
1745static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1746 struct drm_i915_error_state *error,
1747 struct drm_i915_error_ring *ering)
1748{
1749 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1750 struct drm_i915_gem_object *obj;
1751
1752 /* Currently render ring is the only HW context user */
1753 if (ring->id != RCS || !error->ccid)
1754 return;
1755
1756 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1757 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1758 ering->ctx = i915_error_object_create_sized(dev_priv,
1759 obj, 1);
1760 }
1761 }
1762}
1763
52d39a21
CW		 1764static void i915_gem_record_rings(struct drm_device *dev,
1765 struct drm_i915_error_state *error)
1766{
1767 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1768 struct intel_ring_buffer *ring;
52d39a21
CW		 1769 struct drm_i915_gem_request *request;
1770 int i, count;
1771
b4519513 1772 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1773 i915_record_ring_state(dev, error, ring);
1774
1775 error->ring[i].batchbuffer =
1776 i915_error_first_batchbuffer(dev_priv, ring);
1777
1778 error->ring[i].ringbuffer =
1779 i915_error_object_create(dev_priv, ring->obj);
1780
8c123e54
BW		 1781
1782 i915_gem_record_active_context(ring, error, &error->ring[i]);
1783
52d39a21
CW		 1784 count = 0;
1785 list_for_each_entry(request, &ring->request_list, list)
1786 count++;
1787
1788 error->ring[i].num_requests = count;
1789 error->ring[i].requests =
1790 kmalloc(count*sizeof(struct drm_i915_error_request),
1791 GFP_ATOMIC);
1792 if (error->ring[i].requests == NULL) {
1793 error->ring[i].num_requests = 0;
1794 continue;
1795 }
1796
1797 count = 0;
1798 list_for_each_entry(request, &ring->request_list, list) {
1799 struct drm_i915_error_request *erq;
1800
1801 erq = &error->ring[i].requests[count++];
1802 erq->seqno = request->seqno;
1803 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1804 erq->tail = request->tail;
52d39a21
CW		 1805 }
1806 }
1807}
1808
8a905236
JB		 1809/**
1810 * i915_capture_error_state - capture an error record for later analysis
1811 * @dev: drm device
1812 *
1813 * Should be called when an error is detected (either a hang or an error
1814 * interrupt) to capture error state from the time of the error. Fills
1815 * out a structure which becomes available in debugfs for user level tools
1816 * to pick up.
1817 */
63eeaf38
JB		 1818static void i915_capture_error_state(struct drm_device *dev)
1819{
1820 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1821 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1822 struct drm_i915_error_state *error;
1823 unsigned long flags;
9db4a9c7 1824 int i, pipe;
63eeaf38 1825
99584db3
DV		 1826 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1827 error = dev_priv->gpu_error.first_error;
1828 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1829 if (error)
1830 return;
63eeaf38 1831
9db4a9c7 1832 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1833 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1834 if (!error) {
9df30794
CW		 1835 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1836 return;
63eeaf38
JB		 1837 }
1838
5d83d294 1839 DRM_INFO("capturing error event; look for more information in "
2f86f191 1840 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1841 dev->primary->index);
2fa772f3 1842
742cbee8 1843 kref_init(&error->ref);
63eeaf38
JB		 1844 error->eir = I915_READ(EIR);
1845 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1846 if (HAS_HW_CONTEXTS(dev))
1847 error->ccid = I915_READ(CCID);
be998e2e
BW		 1848
1849 if (HAS_PCH_SPLIT(dev))
1850 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1851 else if (IS_VALLEYVIEW(dev))
1852 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1853 else if (IS_GEN2(dev))
1854 error->ier = I915_READ16(IER);
1855 else
1856 error->ier = I915_READ(IER);
1857
0f3b6849
CW		 1858 if (INTEL_INFO(dev)->gen >= 6)
1859 error->derrmr = I915_READ(DERRMR);
1860
1861 if (IS_VALLEYVIEW(dev))
1862 error->forcewake = I915_READ(FORCEWAKE_VLV);
1863 else if (INTEL_INFO(dev)->gen >= 7)
1864 error->forcewake = I915_READ(FORCEWAKE_MT);
1865 else if (INTEL_INFO(dev)->gen == 6)
1866 error->forcewake = I915_READ(FORCEWAKE);
1867
4f3308b9
PZ		 1868 if (!HAS_PCH_SPLIT(dev))
1869 for_each_pipe(pipe)
1870 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1871
33f3f518 1872 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1873 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1874 error->done_reg = I915_READ(DONE_REG);
1875 }
d27b1e0e 1876
71e172e8
BW		 1877 if (INTEL_INFO(dev)->gen == 7)
1878 error->err_int = I915_READ(GEN7_ERR_INT);
1879
050ee91f
BW		 1880 i915_get_extra_instdone(dev, error->extra_instdone);
1881
748ebc60 1882 i915_gem_record_fences(dev, error);
52d39a21 1883 i915_gem_record_rings(dev, error);
9df30794 1884
c724e8a9 1885 /* Record buffers on the active and pinned lists. */
9df30794 1886 error->active_bo = NULL;
c724e8a9 1887 error->pinned_bo = NULL;
9df30794 1888
bcfb2e28
CW		 1889 i = 0;
1890 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1891 i++;
1892 error->active_bo_count = i;
6c085a72 1893 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1894 if (obj->pin_count)
1895 i++;
bcfb2e28 1896 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1897
8e934dbf
CW		 1898 error->active_bo = NULL;
1899 error->pinned_bo = NULL;
bcfb2e28
CW		 1900 if (i) {
1901 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1902 GFP_ATOMIC);
c724e8a9
CW		 1903 if (error->active_bo)
1904 error->pinned_bo =
1905 error->active_bo + error->active_bo_count;
9df30794
CW		 1906 }
1907
c724e8a9
CW		 1908 if (error->active_bo)
1909 error->active_bo_count =
1b50247a
CW		 1910 capture_active_bo(error->active_bo,
1911 error->active_bo_count,
1912 &dev_priv->mm.active_list);
c724e8a9
CW		 1913
1914 if (error->pinned_bo)
1915 error->pinned_bo_count =
1b50247a
CW		 1916 capture_pinned_bo(error->pinned_bo,
1917 error->pinned_bo_count,
6c085a72 1918 &dev_priv->mm.bound_list);
c724e8a9 1919
9df30794
CW		 1920 do_gettimeofday(&error->time);
1921
6ef3d427 1922 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1923 error->display = intel_display_capture_error_state(dev);
6ef3d427 1924
99584db3
DV		 1925 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1926 if (dev_priv->gpu_error.first_error == NULL) {
1927 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1928 error = NULL;
1929 }
99584db3 1930 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1931
1932 if (error)
742cbee8 1933 i915_error_state_free(&error->ref);
9df30794
CW		 1934}
1935
1936void i915_destroy_error_state(struct drm_device *dev)
1937{
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939 struct drm_i915_error_state *error;
6dc0e816 1940 unsigned long flags;
9df30794 1941
99584db3
DV		 1942 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1943 error = dev_priv->gpu_error.first_error;
1944 dev_priv->gpu_error.first_error = NULL;
1945 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1946
1947 if (error)
742cbee8 1948 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1949}
3bd3c932
CW		 1950#else
1951#define i915_capture_error_state(x)
1952#endif
63eeaf38 1953
35aed2e6 1954static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1955{
1956 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1957 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1958 u32 eir = I915_READ(EIR);
050ee91f 1959 int pipe, i;
8a905236 1960
35aed2e6
CW		 1961 if (!eir)
1962 return;
8a905236 1963
a70491cc 1964 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1965
bd9854f9
BW		 1966 i915_get_extra_instdone(dev, instdone);
1967
8a905236
JB		 1968 if (IS_G4X(dev)) {
1969 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1970 u32 ipeir = I915_READ(IPEIR_I965);
1971
a70491cc
JP		 1972 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1973 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1974 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1975 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1976 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1977 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1978 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1979 POSTING_READ(IPEIR_I965);
8a905236
JB		 1980 }
1981 if (eir & GM45_ERROR_PAGE_TABLE) {
1982 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1983 pr_err("page table error\n");
1984 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1985 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1986 POSTING_READ(PGTBL_ER);
8a905236
JB		 1987 }
1988 }
1989
a6c45cf0 1990 if (!IS_GEN2(dev)) {
8a905236
JB		 1991 if (eir & I915_ERROR_PAGE_TABLE) {
1992 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1993 pr_err("page table error\n");
1994 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1995 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1996 POSTING_READ(PGTBL_ER);
8a905236
JB		 1997 }
1998 }
1999
2000 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2001 pr_err("memory refresh error:\n");
9db4a9c7 2002 for_each_pipe(pipe)
a70491cc 2003 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2004 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2005 /* pipestat has already been acked */
2006 }
2007 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2008 pr_err("instruction error\n");
2009 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2010 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2011 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2012 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2013 u32 ipeir = I915_READ(IPEIR);
2014
a70491cc
JP		 2015 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2016 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2017 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2018 I915_WRITE(IPEIR, ipeir);
3143a2bf 2019 POSTING_READ(IPEIR);
8a905236
JB		 2020 } else {
2021 u32 ipeir = I915_READ(IPEIR_I965);
2022
a70491cc
JP		 2023 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2024 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2025 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2026 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2027 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2028 POSTING_READ(IPEIR_I965);
8a905236
JB		 2029 }
2030 }
2031
2032 I915_WRITE(EIR, eir);
3143a2bf 2033 POSTING_READ(EIR);
8a905236
JB		 2034 eir = I915_READ(EIR);
2035 if (eir) {
2036 /*
2037 * some errors might have become stuck,
2038 * mask them.
2039 */
2040 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2041 I915_WRITE(EMR, I915_READ(EMR) | eir);
2042 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2043 }
35aed2e6
CW		 2044}
2045
2046/**
2047 * i915_handle_error - handle an error interrupt
2048 * @dev: drm device
2049 *
2050 * Do some basic checking of regsiter state at error interrupt time and
2051 * dump it to the syslog. Also call i915_capture_error_state() to make
2052 * sure we get a record and make it available in debugfs. Fire a uevent
2053 * so userspace knows something bad happened (should trigger collection
2054 * of a ring dump etc.).
2055 */
527f9e90 2056void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2057{
2058 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2059 struct intel_ring_buffer *ring;
2060 int i;
35aed2e6
CW		 2061
2062 i915_capture_error_state(dev);
2063 i915_report_and_clear_eir(dev);
8a905236 2064
ba1234d1 2065 if (wedged) {
f69061be
DV		 2066 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2067 &dev_priv->gpu_error.reset_counter);
ba1234d1 2068
11ed50ec 2069 /*
1f83fee0
DV		 2070 * Wakeup waiting processes so that the reset work item
2071 * doesn't deadlock trying to grab various locks.
11ed50ec 2072 */
b4519513
CW		 2073 for_each_ring(ring, dev_priv, i)
2074 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2075 }
2076
99584db3 2077 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2078}
2079
21ad8330 2080static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2081{
2082 drm_i915_private_t *dev_priv = dev->dev_private;
2083 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2085 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2086 struct intel_unpin_work *work;
2087 unsigned long flags;
2088 bool stall_detected;
2089
2090 /* Ignore early vblank irqs */
2091 if (intel_crtc == NULL)
2092 return;
2093
2094 spin_lock_irqsave(&dev->event_lock, flags);
2095 work = intel_crtc->unpin_work;
2096
e7d841ca
CW		 2097 if (work == NULL ||
2098 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2099 !work->enable_stall_check) {
4e5359cd
SF		 2100 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2101 spin_unlock_irqrestore(&dev->event_lock, flags);
2102 return;
2103 }
2104
2105 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2106 obj = work->pending_flip_obj;
a6c45cf0 2107 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2108 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 2109 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2110 obj->gtt_offset;
4e5359cd 2111 } else {
9db4a9c7 2112 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 2113 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 2114 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2115 crtc->x * crtc->fb->bits_per_pixel/8);
2116 }
2117
2118 spin_unlock_irqrestore(&dev->event_lock, flags);
2119
2120 if (stall_detected) {
2121 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2122 intel_prepare_page_flip(dev, intel_crtc->plane);
2123 }
2124}
2125
42f52ef8
KP		 2126/* Called from drm generic code, passed 'crtc' which
2127 * we use as a pipe index
2128 */
f71d4af4 2129static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2130{
2131 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2132 unsigned long irqflags;
71e0ffa5 2133
5eddb70b 2134 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2135 return -EINVAL;
0a3e67a4 2136
1ec14ad3 2137 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2138 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2139 i915_enable_pipestat(dev_priv, pipe,
2140 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2141 else
7c463586
KP		 2142 i915_enable_pipestat(dev_priv, pipe,
2143 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2144
2145 /* maintain vblank delivery even in deep C-states */
2146 if (dev_priv->info->gen == 3)
6b26c86d 2147 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2148 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2149
0a3e67a4
JB		 2150 return 0;
2151}
2152
f71d4af4 2153static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2154{
2155 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2156 unsigned long irqflags;
2157
2158 if (!i915_pipe_enabled(dev, pipe))
2159 return -EINVAL;
2160
2161 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2162 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2163 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2164 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2165
2166 return 0;
2167}
2168
f71d4af4 2169static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2170{
2171 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2172 unsigned long irqflags;
2173
2174 if (!i915_pipe_enabled(dev, pipe))
2175 return -EINVAL;
2176
2177 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2178 ironlake_enable_display_irq(dev_priv,
2179 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2180 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2181
2182 return 0;
2183}
2184
7e231dbe
JB		 2185static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2186{
2187 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2188 unsigned long irqflags;
31acc7f5 2189 u32 imr;
7e231dbe
JB		 2190
2191 if (!i915_pipe_enabled(dev, pipe))
2192 return -EINVAL;
2193
2194 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2195 imr = I915_READ(VLV_IMR);
31acc7f5 2196 if (pipe == 0)
7e231dbe 2197 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2198 else
7e231dbe 2199 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2200 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2201 i915_enable_pipestat(dev_priv, pipe,
2202 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2203 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2204
2205 return 0;
2206}
2207
42f52ef8
KP		 2208/* Called from drm generic code, passed 'crtc' which
2209 * we use as a pipe index
2210 */
f71d4af4 2211static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2212{
2213 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2214 unsigned long irqflags;
0a3e67a4 2215
1ec14ad3 2216 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2217 if (dev_priv->info->gen == 3)
6b26c86d 2218 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2219
f796cf8f
JB		 2220 i915_disable_pipestat(dev_priv, pipe,
2221 PIPE_VBLANK_INTERRUPT_ENABLE |
2222 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2223 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2224}
2225
f71d4af4 2226static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2227{
2228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2229 unsigned long irqflags;
2230
2231 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2232 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2233 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2234 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2235}
2236
f71d4af4 2237static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2238{
2239 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2240 unsigned long irqflags;
2241
2242 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2243 ironlake_disable_display_irq(dev_priv,
2244 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2245 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2246}
2247
7e231dbe
JB		 2248static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2249{
2250 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2251 unsigned long irqflags;
31acc7f5 2252 u32 imr;
7e231dbe
JB		 2253
2254 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2255 i915_disable_pipestat(dev_priv, pipe,
2256 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2257 imr = I915_READ(VLV_IMR);
31acc7f5 2258 if (pipe == 0)
7e231dbe 2259 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2260 else
7e231dbe 2261 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2262 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2263 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2264}
2265
893eead0
CW		 2266static u32
2267ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2268{
893eead0
CW		 2269 return list_entry(ring->request_list.prev,
2270 struct drm_i915_gem_request, list)->seqno;
2271}
2272
2273static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
2274{
2275 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 2276 i915_seqno_passed(ring->get_seqno(ring, false),
2277 ring_last_seqno(ring))) {
893eead0 2278 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 2279 if (waitqueue_active(&ring->irq_queue)) {
2280 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2281 ring->name);
893eead0
CW		 2282 wake_up_all(&ring->irq_queue);
2283 *err = true;
2284 }
2285 return true;
2286 }
2287 return false;
f65d9421
BG		 2288}
2289
a24a11e6
CW		 2290static bool semaphore_passed(struct intel_ring_buffer *ring)
2291{
2292 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2293 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2294 struct intel_ring_buffer *signaller;
2295 u32 cmd, ipehr, acthd_min;
2296
2297 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2298 if ((ipehr & ~(0x3 << 16)) !=
2299 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2300 return false;
2301
2302 /* ACTHD is likely pointing to the dword after the actual command,
2303 * so scan backwards until we find the MBOX.
2304 */
2305 acthd_min = max((int)acthd - 3 * 4, 0);
2306 do {
2307 cmd = ioread32(ring->virtual_start + acthd);
2308 if (cmd == ipehr)
2309 break;
2310
2311 acthd -= 4;
2312 if (acthd < acthd_min)
2313 return false;
2314 } while (1);
2315
2316 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2317 return i915_seqno_passed(signaller->get_seqno(signaller, false),
2318 ioread32(ring->virtual_start+acthd+4)+1);
2319}
2320
1ec14ad3
CW		 2321static bool kick_ring(struct intel_ring_buffer *ring)
2322{
2323 struct drm_device *dev = ring->dev;
2324 struct drm_i915_private *dev_priv = dev->dev_private;
2325 u32 tmp = I915_READ_CTL(ring);
2326 if (tmp & RING_WAIT) {
2327 DRM_ERROR("Kicking stuck wait on %s\n",
2328 ring->name);
2329 I915_WRITE_CTL(ring, tmp);
2330 return true;
2331 }
a24a11e6
CW		 2332
2333 if (INTEL_INFO(dev)->gen >= 6 &&
2334 tmp & RING_WAIT_SEMAPHORE &&
2335 semaphore_passed(ring)) {
2336 DRM_ERROR("Kicking stuck semaphore on %s\n",
2337 ring->name);
2338 I915_WRITE_CTL(ring, tmp);
2339 return true;
2340 }
1ec14ad3
CW		 2341 return false;
2342}
2343
d1e61e7f
CW		 2344static bool i915_hangcheck_hung(struct drm_device *dev)
2345{
2346 drm_i915_private_t *dev_priv = dev->dev_private;
2347
99584db3 2348 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 2349 bool hung = true;
2350
d1e61e7f
CW		 2351 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2352 i915_handle_error(dev, true);
2353
2354 if (!IS_GEN2(dev)) {
b4519513
CW		 2355 struct intel_ring_buffer *ring;
2356 int i;
2357
d1e61e7f
CW		 2358 /* Is the chip hanging on a WAIT_FOR_EVENT?
2359 * If so we can simply poke the RB_WAIT bit
2360 * and break the hang. This should work on
2361 * all but the second generation chipsets.
2362 */
b4519513
CW		 2363 for_each_ring(ring, dev_priv, i)
2364 hung &= !kick_ring(ring);
d1e61e7f
CW		 2365 }
2366
b4519513 2367 return hung;
d1e61e7f
CW		 2368 }
2369
2370 return false;
2371}
2372
f65d9421
BG		 2373/**
2374 * This is called when the chip hasn't reported back with completed
2375 * batchbuffers in a long time. The first time this is called we simply record
2376 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2377 * again, we assume the chip is wedged and try to fix it.
2378 */
2379void i915_hangcheck_elapsed(unsigned long data)
2380{
2381 struct drm_device *dev = (struct drm_device *)data;
2382 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 2383 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 2384 struct intel_ring_buffer *ring;
2385 bool err = false, idle;
2386 int i;
893eead0 2387
3e0dc6b0
BW		 2388 if (!i915_enable_hangcheck)
2389 return;
2390
b4519513
CW		 2391 memset(acthd, 0, sizeof(acthd));
2392 idle = true;
2393 for_each_ring(ring, dev_priv, i) {
2394 idle &= i915_hangcheck_ring_idle(ring, &err);
2395 acthd[i] = intel_ring_get_active_head(ring);
2396 }
2397
893eead0 2398 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 2399 if (idle) {
d1e61e7f
CW		 2400 if (err) {
2401 if (i915_hangcheck_hung(dev))
2402 return;
2403
893eead0 2404 goto repeat;
d1e61e7f
CW		 2405 }
2406
99584db3 2407 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 2408 return;
2409 }
b9201c14 2410
bd9854f9 2411 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 2412 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
2413 sizeof(acthd)) == 0 &&
2414 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
2415 sizeof(instdone)) == 0) {
d1e61e7f 2416 if (i915_hangcheck_hung(dev))
cbb465e7 2417 return;
cbb465e7 2418 } else {
99584db3 2419 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 2420
99584db3
DV		 2421 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2422 sizeof(acthd));
2423 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2424 sizeof(instdone));
cbb465e7 2425 }
f65d9421 2426
893eead0 2427repeat:
f65d9421 2428 /* Reset timer case chip hangs without another request being added */
99584db3 2429 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 2430 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2431}
2432
1da177e4
LT		 2433/* drm_dma.h hooks
2434*/
f71d4af4 2435static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2436{
2437 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2438
4697995b
JB		 2439 atomic_set(&dev_priv->irq_received, 0);
2440
036a4a7d 2441 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2442
036a4a7d
ZW		 2443 /* XXX hotplug from PCH */
2444
2445 I915_WRITE(DEIMR, 0xffffffff);
2446 I915_WRITE(DEIER, 0x0);
3143a2bf 2447 POSTING_READ(DEIER);
036a4a7d
ZW		 2448
2449 /* and GT */
2450 I915_WRITE(GTIMR, 0xffffffff);
2451 I915_WRITE(GTIER, 0x0);
3143a2bf 2452 POSTING_READ(GTIER);
c650156a 2453
ab5c608b
BW		 2454 if (HAS_PCH_NOP(dev))
2455 return;
2456
c650156a
ZW		 2457 /* south display irq */
2458 I915_WRITE(SDEIMR, 0xffffffff);
82a28bcf
DV		 2459 /*
2460 * SDEIER is also touched by the interrupt handler to work around missed
2461 * PCH interrupts. Hence we can't update it after the interrupt handler
2462 * is enabled - instead we unconditionally enable all PCH interrupt
2463 * sources here, but then only unmask them as needed with SDEIMR.
2464 */
2465 I915_WRITE(SDEIER, 0xffffffff);
3143a2bf 2466 POSTING_READ(SDEIER);
036a4a7d
ZW		 2467}
2468
7e231dbe
JB		 2469static void valleyview_irq_preinstall(struct drm_device *dev)
2470{
2471 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2472 int pipe;
2473
2474 atomic_set(&dev_priv->irq_received, 0);
2475
7e231dbe
JB		 2476 /* VLV magic */
2477 I915_WRITE(VLV_IMR, 0);
2478 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2479 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2480 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2481
7e231dbe
JB		 2482 /* and GT */
2483 I915_WRITE(GTIIR, I915_READ(GTIIR));
2484 I915_WRITE(GTIIR, I915_READ(GTIIR));
2485 I915_WRITE(GTIMR, 0xffffffff);
2486 I915_WRITE(GTIER, 0x0);
2487 POSTING_READ(GTIER);
2488
2489 I915_WRITE(DPINVGTT, 0xff);
2490
2491 I915_WRITE(PORT_HOTPLUG_EN, 0);
2492 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2493 for_each_pipe(pipe)
2494 I915_WRITE(PIPESTAT(pipe), 0xffff);
2495 I915_WRITE(VLV_IIR, 0xffffffff);
2496 I915_WRITE(VLV_IMR, 0xffffffff);
2497 I915_WRITE(VLV_IER, 0x0);
2498 POSTING_READ(VLV_IER);
2499}
2500
82a28bcf 2501static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2502{
2503 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2504 struct drm_mode_config *mode_config = &dev->mode_config;
2505 struct intel_encoder *intel_encoder;
2506 u32 mask = ~I915_READ(SDEIMR);
2507 u32 hotplug;
2508
2509 if (HAS_PCH_IBX(dev)) {
995e6b3d 2510 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2511 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2512 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2513 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2514 } else {
995e6b3d 2515 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2516 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2517 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2518 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2519 }
7fe0b973 2520
82a28bcf
DV		 2521 I915_WRITE(SDEIMR, ~mask);
2522
2523 /*
2524 * Enable digital hotplug on the PCH, and configure the DP short pulse
2525 * duration to 2ms (which is the minimum in the Display Port spec)
2526 *
2527 * This register is the same on all known PCH chips.
2528 */
7fe0b973
KP		 2529 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2530 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2531 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2532 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2533 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2534 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2535}
2536
d46da437
PZ		 2537static void ibx_irq_postinstall(struct drm_device *dev)
2538{
2539 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2540 u32 mask;
e5868a31 2541
8664281b
PZ		 2542 if (HAS_PCH_IBX(dev)) {
2543 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2544 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2545 } else {
2546 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2547
2548 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2549 }
ab5c608b
BW		 2550
2551 if (HAS_PCH_NOP(dev))
2552 return;
2553
d46da437
PZ		 2554 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2555 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2556}
2557
f71d4af4 2558static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 2559{
2560 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2561 /* enable kind of interrupts always enabled */
013d5aa2 2562 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2563 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2564 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2565 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
1ec14ad3 2566 u32 render_irqs;
036a4a7d 2567
1ec14ad3 2568 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2569
2570 /* should always can generate irq */
2571 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 2572 I915_WRITE(DEIMR, dev_priv->irq_mask);
2573 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 2574 POSTING_READ(DEIER);
036a4a7d 2575
1ec14ad3 2576 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2577
2578 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2579 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2580
1ec14ad3
CW		 2581 if (IS_GEN6(dev))
2582 render_irqs =
2583 GT_USER_INTERRUPT |
e2a1e2f0
BW		 2584 GEN6_BSD_USER_INTERRUPT |
2585 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 2586 else
2587 render_irqs =
88f23b8f 2588 GT_USER_INTERRUPT |
c6df541c 2589 GT_PIPE_NOTIFY |
1ec14ad3
CW		 2590 GT_BSD_USER_INTERRUPT;
2591 I915_WRITE(GTIER, render_irqs);
3143a2bf 2592 POSTING_READ(GTIER);
036a4a7d 2593
d46da437 2594 ibx_irq_postinstall(dev);
7fe0b973 2595
f97108d1
JB		 2596 if (IS_IRONLAKE_M(dev)) {
2597 /* Clear & enable PCU event interrupts */
2598 I915_WRITE(DEIIR, DE_PCU_EVENT);
2599 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2600 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2601 }
2602
036a4a7d
ZW		 2603 return 0;
2604}
2605
f71d4af4 2606static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2607{
2608 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2609 /* enable kind of interrupts always enabled */
b615b57a
CW		 2610 u32 display_mask =
2611 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2612 DE_PLANEC_FLIP_DONE_IVB |
2613 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2614 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2615 DE_AUX_CHANNEL_A_IVB |
2616 DE_ERR_INT_IVB;
b1f14ad0 2617 u32 render_irqs;
b1f14ad0 2618
b1f14ad0
JB		 2619 dev_priv->irq_mask = ~display_mask;
2620
2621 /* should always can generate irq */
8664281b 2622 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2623 I915_WRITE(DEIIR, I915_READ(DEIIR));
2624 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2625 I915_WRITE(DEIER,
2626 display_mask |
2627 DE_PIPEC_VBLANK_IVB |
2628 DE_PIPEB_VBLANK_IVB |
2629 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2630 POSTING_READ(DEIER);
2631
15b9f80e 2632 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2633
2634 I915_WRITE(GTIIR, I915_READ(GTIIR));
2635 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2636
e2a1e2f0 2637 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2638 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2639 I915_WRITE(GTIER, render_irqs);
2640 POSTING_READ(GTIER);
2641
d46da437 2642 ibx_irq_postinstall(dev);
7fe0b973 2643
b1f14ad0
JB		 2644 return 0;
2645}
2646
7e231dbe
JB		 2647static int valleyview_irq_postinstall(struct drm_device *dev)
2648{
2649 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2650 u32 enable_mask;
31acc7f5 2651 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2652 u32 render_irqs;
7e231dbe
JB		 2653
2654 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2655 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2656 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2657 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2658 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2659
31acc7f5
JB		 2660 /*
2661 *Leave vblank interrupts masked initially. enable/disable will
2662 * toggle them based on usage.
2663 */
2664 dev_priv->irq_mask = (~enable_mask) |
2665 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2666 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2667
20afbda2
DV		 2668 I915_WRITE(PORT_HOTPLUG_EN, 0);
2669 POSTING_READ(PORT_HOTPLUG_EN);
2670
7e231dbe
JB		 2671 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2672 I915_WRITE(VLV_IER, enable_mask);
2673 I915_WRITE(VLV_IIR, 0xffffffff);
2674 I915_WRITE(PIPESTAT(0), 0xffff);
2675 I915_WRITE(PIPESTAT(1), 0xffff);
2676 POSTING_READ(VLV_IER);
2677
31acc7f5 2678 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2679 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2680 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2681
7e231dbe
JB		 2682 I915_WRITE(VLV_IIR, 0xffffffff);
2683 I915_WRITE(VLV_IIR, 0xffffffff);
2684
7e231dbe 2685 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2686 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2687
2688 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2689 GEN6_BLITTER_USER_INTERRUPT;
2690 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2691 POSTING_READ(GTIER);
2692
2693 /* ack & enable invalid PTE error interrupts */
2694#if 0 /* FIXME: add support to irq handler for checking these bits */
2695 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2696 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2697#endif
2698
2699 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2700
2701 return 0;
2702}
2703
7e231dbe
JB		 2704static void valleyview_irq_uninstall(struct drm_device *dev)
2705{
2706 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2707 int pipe;
2708
2709 if (!dev_priv)
2710 return;
2711
ac4c16c5
EE		 2712 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2713
7e231dbe
JB		 2714 for_each_pipe(pipe)
2715 I915_WRITE(PIPESTAT(pipe), 0xffff);
2716
2717 I915_WRITE(HWSTAM, 0xffffffff);
2718 I915_WRITE(PORT_HOTPLUG_EN, 0);
2719 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2720 for_each_pipe(pipe)
2721 I915_WRITE(PIPESTAT(pipe), 0xffff);
2722 I915_WRITE(VLV_IIR, 0xffffffff);
2723 I915_WRITE(VLV_IMR, 0xffffffff);
2724 I915_WRITE(VLV_IER, 0x0);
2725 POSTING_READ(VLV_IER);
2726}
2727
f71d4af4 2728static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2729{
2730 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2731
2732 if (!dev_priv)
2733 return;
2734
ac4c16c5
EE		 2735 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2736
036a4a7d
ZW		 2737 I915_WRITE(HWSTAM, 0xffffffff);
2738
2739 I915_WRITE(DEIMR, 0xffffffff);
2740 I915_WRITE(DEIER, 0x0);
2741 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2742 if (IS_GEN7(dev))
2743 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2744
2745 I915_WRITE(GTIMR, 0xffffffff);
2746 I915_WRITE(GTIER, 0x0);
2747 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2748
ab5c608b
BW		 2749 if (HAS_PCH_NOP(dev))
2750 return;
2751
192aac1f
KP		 2752 I915_WRITE(SDEIMR, 0xffffffff);
2753 I915_WRITE(SDEIER, 0x0);
2754 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2755 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2756 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2757}
2758
a266c7d5 2759static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2760{
2761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2762 int pipe;
91e3738e 2763
a266c7d5 2764 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2765
9db4a9c7
JB		 2766 for_each_pipe(pipe)
2767 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2768 I915_WRITE16(IMR, 0xffff);
2769 I915_WRITE16(IER, 0x0);
2770 POSTING_READ16(IER);
c2798b19
CW		 2771}
2772
2773static int i8xx_irq_postinstall(struct drm_device *dev)
2774{
2775 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2776
c2798b19
CW		 2777 I915_WRITE16(EMR,
2778 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2779
2780 /* Unmask the interrupts that we always want on. */
2781 dev_priv->irq_mask =
2782 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2783 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2784 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2785 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2786 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2787 I915_WRITE16(IMR, dev_priv->irq_mask);
2788
2789 I915_WRITE16(IER,
2790 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2791 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2792 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2793 I915_USER_INTERRUPT);
2794 POSTING_READ16(IER);
2795
2796 return 0;
2797}
2798
90a72f87
VS		 2799/*
2800 * Returns true when a page flip has completed.
2801 */
2802static bool i8xx_handle_vblank(struct drm_device *dev,
2803 int pipe, u16 iir)
2804{
2805 drm_i915_private_t *dev_priv = dev->dev_private;
2806 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2807
2808 if (!drm_handle_vblank(dev, pipe))
2809 return false;
2810
2811 if ((iir & flip_pending) == 0)
2812 return false;
2813
2814 intel_prepare_page_flip(dev, pipe);
2815
2816 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2817 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2818 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2819 * the flip is completed (no longer pending). Since this doesn't raise
2820 * an interrupt per se, we watch for the change at vblank.
2821 */
2822 if (I915_READ16(ISR) & flip_pending)
2823 return false;
2824
2825 intel_finish_page_flip(dev, pipe);
2826
2827 return true;
2828}
2829
ff1f525e 2830static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2831{
2832 struct drm_device *dev = (struct drm_device *) arg;
2833 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2834 u16 iir, new_iir;
2835 u32 pipe_stats[2];
2836 unsigned long irqflags;
2837 int irq_received;
2838 int pipe;
2839 u16 flip_mask =
2840 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2841 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2842
2843 atomic_inc(&dev_priv->irq_received);
2844
2845 iir = I915_READ16(IIR);
2846 if (iir == 0)
2847 return IRQ_NONE;
2848
2849 while (iir & ~flip_mask) {
2850 /* Can't rely on pipestat interrupt bit in iir as it might
2851 * have been cleared after the pipestat interrupt was received.
2852 * It doesn't set the bit in iir again, but it still produces
2853 * interrupts (for non-MSI).
2854 */
2855 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2856 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2857 i915_handle_error(dev, false);
2858
2859 for_each_pipe(pipe) {
2860 int reg = PIPESTAT(pipe);
2861 pipe_stats[pipe] = I915_READ(reg);
2862
2863 /*
2864 * Clear the PIPE*STAT regs before the IIR
2865 */
2866 if (pipe_stats[pipe] & 0x8000ffff) {
2867 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2868 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2869 pipe_name(pipe));
2870 I915_WRITE(reg, pipe_stats[pipe]);
2871 irq_received = 1;
2872 }
2873 }
2874 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2875
2876 I915_WRITE16(IIR, iir & ~flip_mask);
2877 new_iir = I915_READ16(IIR); /* Flush posted writes */
2878
d05c617e 2879 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2880
2881 if (iir & I915_USER_INTERRUPT)
2882 notify_ring(dev, &dev_priv->ring[RCS]);
2883
2884 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2885 i8xx_handle_vblank(dev, 0, iir))
2886 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2887
2888 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2889 i8xx_handle_vblank(dev, 1, iir))
2890 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2891
2892 iir = new_iir;
2893 }
2894
2895 return IRQ_HANDLED;
2896}
2897
2898static void i8xx_irq_uninstall(struct drm_device * dev)
2899{
2900 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2901 int pipe;
2902
c2798b19
CW		 2903 for_each_pipe(pipe) {
2904 /* Clear enable bits; then clear status bits */
2905 I915_WRITE(PIPESTAT(pipe), 0);
2906 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2907 }
2908 I915_WRITE16(IMR, 0xffff);
2909 I915_WRITE16(IER, 0x0);
2910 I915_WRITE16(IIR, I915_READ16(IIR));
2911}
2912
a266c7d5
CW		 2913static void i915_irq_preinstall(struct drm_device * dev)
2914{
2915 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2916 int pipe;
2917
2918 atomic_set(&dev_priv->irq_received, 0);
2919
2920 if (I915_HAS_HOTPLUG(dev)) {
2921 I915_WRITE(PORT_HOTPLUG_EN, 0);
2922 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2923 }
2924
00d98ebd 2925 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2926 for_each_pipe(pipe)
2927 I915_WRITE(PIPESTAT(pipe), 0);
2928 I915_WRITE(IMR, 0xffffffff);
2929 I915_WRITE(IER, 0x0);
2930 POSTING_READ(IER);
2931}
2932
2933static int i915_irq_postinstall(struct drm_device *dev)
2934{
2935 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2936 u32 enable_mask;
a266c7d5 2937
38bde180
CW		 2938 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2939
2940 /* Unmask the interrupts that we always want on. */
2941 dev_priv->irq_mask =
2942 ~(I915_ASLE_INTERRUPT |
2943 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2944 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2945 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2946 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2947 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2948
2949 enable_mask =
2950 I915_ASLE_INTERRUPT |
2951 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2952 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2953 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2954 I915_USER_INTERRUPT;
2955
a266c7d5 2956 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2957 I915_WRITE(PORT_HOTPLUG_EN, 0);
2958 POSTING_READ(PORT_HOTPLUG_EN);
2959
a266c7d5
CW		 2960 /* Enable in IER... */
2961 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2962 /* and unmask in IMR */
2963 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2964 }
2965
a266c7d5
CW		 2966 I915_WRITE(IMR, dev_priv->irq_mask);
2967 I915_WRITE(IER, enable_mask);
2968 POSTING_READ(IER);
2969
f49e38dd 2970 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2971
2972 return 0;
2973}
2974
90a72f87
VS		 2975/*
2976 * Returns true when a page flip has completed.
2977 */
2978static bool i915_handle_vblank(struct drm_device *dev,
2979 int plane, int pipe, u32 iir)
2980{
2981 drm_i915_private_t *dev_priv = dev->dev_private;
2982 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2983
2984 if (!drm_handle_vblank(dev, pipe))
2985 return false;
2986
2987 if ((iir & flip_pending) == 0)
2988 return false;
2989
2990 intel_prepare_page_flip(dev, plane);
2991
2992 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2993 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2994 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2995 * the flip is completed (no longer pending). Since this doesn't raise
2996 * an interrupt per se, we watch for the change at vblank.
2997 */
2998 if (I915_READ(ISR) & flip_pending)
2999 return false;
3000
3001 intel_finish_page_flip(dev, pipe);
3002
3003 return true;
3004}
3005
ff1f525e 3006static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3007{
3008 struct drm_device *dev = (struct drm_device *) arg;
3009 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3010 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3011 unsigned long irqflags;
38bde180
CW		 3012 u32 flip_mask =
3013 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3014 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3015 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3016
3017 atomic_inc(&dev_priv->irq_received);
3018
3019 iir = I915_READ(IIR);
38bde180
CW		 3020 do {
3021 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3022 bool blc_event = false;
a266c7d5
CW		 3023
3024 /* Can't rely on pipestat interrupt bit in iir as it might
3025 * have been cleared after the pipestat interrupt was received.
3026 * It doesn't set the bit in iir again, but it still produces
3027 * interrupts (for non-MSI).
3028 */
3029 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3030 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3031 i915_handle_error(dev, false);
3032
3033 for_each_pipe(pipe) {
3034 int reg = PIPESTAT(pipe);
3035 pipe_stats[pipe] = I915_READ(reg);
3036
38bde180 3037 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3038 if (pipe_stats[pipe] & 0x8000ffff) {
3039 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3040 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3041 pipe_name(pipe));
3042 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3043 irq_received = true;
a266c7d5
CW		 3044 }
3045 }
3046 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3047
3048 if (!irq_received)
3049 break;
3050
a266c7d5
CW		 3051 /* Consume port. Then clear IIR or we'll miss events */
3052 if ((I915_HAS_HOTPLUG(dev)) &&
3053 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3054 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3055 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3056
3057 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3058 hotplug_status);
b543fb04 3059 if (hotplug_trigger) {
cd569aed
EE		 3060 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3061 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3062 queue_work(dev_priv->wq,
3063 &dev_priv->hotplug_work);
b543fb04 3064 }
a266c7d5 3065 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3066 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3067 }
3068
38bde180 3069 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3070 new_iir = I915_READ(IIR); /* Flush posted writes */
3071
a266c7d5
CW		 3072 if (iir & I915_USER_INTERRUPT)
3073 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3074
a266c7d5 3075 for_each_pipe(pipe) {
38bde180
CW		 3076 int plane = pipe;
3077 if (IS_MOBILE(dev))
3078 plane = !plane;
90a72f87 3079
8291ee90 3080 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3081 i915_handle_vblank(dev, plane, pipe, iir))
3082 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3083
3084 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3085 blc_event = true;
3086 }
3087
a266c7d5
CW		 3088 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3089 intel_opregion_asle_intr(dev);
3090
3091 /* With MSI, interrupts are only generated when iir
3092 * transitions from zero to nonzero. If another bit got
3093 * set while we were handling the existing iir bits, then
3094 * we would never get another interrupt.
3095 *
3096 * This is fine on non-MSI as well, as if we hit this path
3097 * we avoid exiting the interrupt handler only to generate
3098 * another one.
3099 *
3100 * Note that for MSI this could cause a stray interrupt report
3101 * if an interrupt landed in the time between writing IIR and
3102 * the posting read. This should be rare enough to never
3103 * trigger the 99% of 100,000 interrupts test for disabling
3104 * stray interrupts.
3105 */
38bde180 3106 ret = IRQ_HANDLED;
a266c7d5 3107 iir = new_iir;
38bde180 3108 } while (iir & ~flip_mask);
a266c7d5 3109
d05c617e 3110 i915_update_dri1_breadcrumb(dev);
8291ee90 3111
a266c7d5
CW		 3112 return ret;
3113}
3114
3115static void i915_irq_uninstall(struct drm_device * dev)
3116{
3117 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3118 int pipe;
3119
ac4c16c5
EE		 3120 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3121
a266c7d5
CW		 3122 if (I915_HAS_HOTPLUG(dev)) {
3123 I915_WRITE(PORT_HOTPLUG_EN, 0);
3124 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3125 }
3126
00d98ebd 3127 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3128 for_each_pipe(pipe) {
3129 /* Clear enable bits; then clear status bits */
a266c7d5 3130 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3131 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3132 }
a266c7d5
CW		 3133 I915_WRITE(IMR, 0xffffffff);
3134 I915_WRITE(IER, 0x0);
3135
a266c7d5
CW		 3136 I915_WRITE(IIR, I915_READ(IIR));
3137}
3138
3139static void i965_irq_preinstall(struct drm_device * dev)
3140{
3141 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3142 int pipe;
3143
3144 atomic_set(&dev_priv->irq_received, 0);
3145
adca4730
CW		 3146 I915_WRITE(PORT_HOTPLUG_EN, 0);
3147 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3148
3149 I915_WRITE(HWSTAM, 0xeffe);
3150 for_each_pipe(pipe)
3151 I915_WRITE(PIPESTAT(pipe), 0);
3152 I915_WRITE(IMR, 0xffffffff);
3153 I915_WRITE(IER, 0x0);
3154 POSTING_READ(IER);
3155}
3156
3157static int i965_irq_postinstall(struct drm_device *dev)
3158{
3159 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3160 u32 enable_mask;
a266c7d5
CW		 3161 u32 error_mask;
3162
a266c7d5 3163 /* Unmask the interrupts that we always want on. */
bbba0a97 3164 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3165 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3166 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3167 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3168 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3169 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3170 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3171
3172 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3173 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3174 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3175 enable_mask |= I915_USER_INTERRUPT;
3176
3177 if (IS_G4X(dev))
3178 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3179
515ac2bb 3180 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 3181
a266c7d5
CW		 3182 /*
3183 * Enable some error detection, note the instruction error mask
3184 * bit is reserved, so we leave it masked.
3185 */
3186 if (IS_G4X(dev)) {
3187 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3188 GM45_ERROR_MEM_PRIV |
3189 GM45_ERROR_CP_PRIV |
3190 I915_ERROR_MEMORY_REFRESH);
3191 } else {
3192 error_mask = ~(I915_ERROR_PAGE_TABLE |
3193 I915_ERROR_MEMORY_REFRESH);
3194 }
3195 I915_WRITE(EMR, error_mask);
3196
3197 I915_WRITE(IMR, dev_priv->irq_mask);
3198 I915_WRITE(IER, enable_mask);
3199 POSTING_READ(IER);
3200
20afbda2
DV		 3201 I915_WRITE(PORT_HOTPLUG_EN, 0);
3202 POSTING_READ(PORT_HOTPLUG_EN);
3203
f49e38dd 3204 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3205
3206 return 0;
3207}
3208
bac56d5b 3209static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3210{
3211 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3212 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3213 struct intel_encoder *intel_encoder;
20afbda2
DV		 3214 u32 hotplug_en;
3215
bac56d5b
EE		 3216 if (I915_HAS_HOTPLUG(dev)) {
3217 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3218 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3219 /* Note HDMI and DP share hotplug bits */
e5868a31 3220 /* enable bits are the same for all generations */
cd569aed
EE		 3221 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3222 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3223 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3224 /* Programming the CRT detection parameters tends
3225 to generate a spurious hotplug event about three
3226 seconds later. So just do it once.
3227 */
3228 if (IS_G4X(dev))
3229 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3230 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3231 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3232
bac56d5b
EE		 3233 /* Ignore TV since it's buggy */
3234 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3235 }
a266c7d5
CW		 3236}
3237
ff1f525e 3238static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3239{
3240 struct drm_device *dev = (struct drm_device *) arg;
3241 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3242 u32 iir, new_iir;
3243 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3244 unsigned long irqflags;
3245 int irq_received;
3246 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3247 u32 flip_mask =
3248 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3249 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3250
3251 atomic_inc(&dev_priv->irq_received);
3252
3253 iir = I915_READ(IIR);
3254
a266c7d5 3255 for (;;) {
2c8ba29f
CW		 3256 bool blc_event = false;
3257
21ad8330 3258 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3259
3260 /* Can't rely on pipestat interrupt bit in iir as it might
3261 * have been cleared after the pipestat interrupt was received.
3262 * It doesn't set the bit in iir again, but it still produces
3263 * interrupts (for non-MSI).
3264 */
3265 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3266 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3267 i915_handle_error(dev, false);
3268
3269 for_each_pipe(pipe) {
3270 int reg = PIPESTAT(pipe);
3271 pipe_stats[pipe] = I915_READ(reg);
3272
3273 /*
3274 * Clear the PIPE*STAT regs before the IIR
3275 */
3276 if (pipe_stats[pipe] & 0x8000ffff) {
3277 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3278 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3279 pipe_name(pipe));
3280 I915_WRITE(reg, pipe_stats[pipe]);
3281 irq_received = 1;
3282 }
3283 }
3284 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3285
3286 if (!irq_received)
3287 break;
3288
3289 ret = IRQ_HANDLED;
3290
3291 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3292 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3293 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3294 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3295 HOTPLUG_INT_STATUS_G4X :
3296 HOTPLUG_INT_STATUS_I965);
a266c7d5
CW		 3297
3298 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3299 hotplug_status);
b543fb04 3300 if (hotplug_trigger) {
cd569aed
EE		 3301 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3302 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3303 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3304 queue_work(dev_priv->wq,
3305 &dev_priv->hotplug_work);
b543fb04 3306 }
a266c7d5
CW		 3307 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3308 I915_READ(PORT_HOTPLUG_STAT);
3309 }
3310
21ad8330 3311 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3312 new_iir = I915_READ(IIR); /* Flush posted writes */
3313
a266c7d5
CW		 3314 if (iir & I915_USER_INTERRUPT)
3315 notify_ring(dev, &dev_priv->ring[RCS]);
3316 if (iir & I915_BSD_USER_INTERRUPT)
3317 notify_ring(dev, &dev_priv->ring[VCS]);
3318
a266c7d5 3319 for_each_pipe(pipe) {
2c8ba29f 3320 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3321 i915_handle_vblank(dev, pipe, pipe, iir))
3322 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3323
3324 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3325 blc_event = true;
3326 }
3327
3328
3329 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3330 intel_opregion_asle_intr(dev);
3331
515ac2bb
DV		 3332 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3333 gmbus_irq_handler(dev);
3334
a266c7d5
CW		 3335 /* With MSI, interrupts are only generated when iir
3336 * transitions from zero to nonzero. If another bit got
3337 * set while we were handling the existing iir bits, then
3338 * we would never get another interrupt.
3339 *
3340 * This is fine on non-MSI as well, as if we hit this path
3341 * we avoid exiting the interrupt handler only to generate
3342 * another one.
3343 *
3344 * Note that for MSI this could cause a stray interrupt report
3345 * if an interrupt landed in the time between writing IIR and
3346 * the posting read. This should be rare enough to never
3347 * trigger the 99% of 100,000 interrupts test for disabling
3348 * stray interrupts.
3349 */
3350 iir = new_iir;
3351 }
3352
d05c617e 3353 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3354
a266c7d5
CW		 3355 return ret;
3356}
3357
3358static void i965_irq_uninstall(struct drm_device * dev)
3359{
3360 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3361 int pipe;
3362
3363 if (!dev_priv)
3364 return;
3365
ac4c16c5
EE		 3366 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3367
adca4730
CW		 3368 I915_WRITE(PORT_HOTPLUG_EN, 0);
3369 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3370
3371 I915_WRITE(HWSTAM, 0xffffffff);
3372 for_each_pipe(pipe)
3373 I915_WRITE(PIPESTAT(pipe), 0);
3374 I915_WRITE(IMR, 0xffffffff);
3375 I915_WRITE(IER, 0x0);
3376
3377 for_each_pipe(pipe)
3378 I915_WRITE(PIPESTAT(pipe),
3379 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3380 I915_WRITE(IIR, I915_READ(IIR));
3381}
3382
ac4c16c5
EE		 3383static void i915_reenable_hotplug_timer_func(unsigned long data)
3384{
3385 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3386 struct drm_device *dev = dev_priv->dev;
3387 struct drm_mode_config *mode_config = &dev->mode_config;
3388 unsigned long irqflags;
3389 int i;
3390
3391 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3392 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3393 struct drm_connector *connector;
3394
3395 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3396 continue;
3397
3398 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3399
3400 list_for_each_entry(connector, &mode_config->connector_list, head) {
3401 struct intel_connector *intel_connector = to_intel_connector(connector);
3402
3403 if (intel_connector->encoder->hpd_pin == i) {
3404 if (connector->polled != intel_connector->polled)
3405 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3406 drm_get_connector_name(connector));
3407 connector->polled = intel_connector->polled;
3408 if (!connector->polled)
3409 connector->polled = DRM_CONNECTOR_POLL_HPD;
3410 }
3411 }
3412 }
3413 if (dev_priv->display.hpd_irq_setup)
3414 dev_priv->display.hpd_irq_setup(dev);
3415 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3416}
3417
f71d4af4
JB		 3418void intel_irq_init(struct drm_device *dev)
3419{
8b2e326d
CW		 3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421
3422 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3423 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3424 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3425 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3426
99584db3
DV		 3427 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3428 i915_hangcheck_elapsed,
61bac78e 3429 (unsigned long) dev);
ac4c16c5
EE		 3430 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3431 (unsigned long) dev_priv);
61bac78e 3432
97a19a24 3433 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3434
f71d4af4
JB		 3435 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3436 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3437 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3438 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3439 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3440 }
3441
c3613de9
KP		 3442 if (drm_core_check_feature(dev, DRIVER_MODESET))
3443 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3444 else
3445 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3446 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3447
7e231dbe
JB		 3448 if (IS_VALLEYVIEW(dev)) {
3449 dev->driver->irq_handler = valleyview_irq_handler;
3450 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3451 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3452 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3453 dev->driver->enable_vblank = valleyview_enable_vblank;
3454 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3455 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3456 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 3457 /* Share pre & uninstall handlers with ILK/SNB */
3458 dev->driver->irq_handler = ivybridge_irq_handler;
3459 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3460 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3461 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3462 dev->driver->enable_vblank = ivybridge_enable_vblank;
3463 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3464 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3465 } else if (HAS_PCH_SPLIT(dev)) {
3466 dev->driver->irq_handler = ironlake_irq_handler;
3467 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3468 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3469 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3470 dev->driver->enable_vblank = ironlake_enable_vblank;
3471 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3472 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3473 } else {
c2798b19
CW		 3474 if (INTEL_INFO(dev)->gen == 2) {
3475 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3476 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3477 dev->driver->irq_handler = i8xx_irq_handler;
3478 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3479 } else if (INTEL_INFO(dev)->gen == 3) {
3480 dev->driver->irq_preinstall = i915_irq_preinstall;
3481 dev->driver->irq_postinstall = i915_irq_postinstall;
3482 dev->driver->irq_uninstall = i915_irq_uninstall;
3483 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3484 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3485 } else {
a266c7d5
CW		 3486 dev->driver->irq_preinstall = i965_irq_preinstall;
3487 dev->driver->irq_postinstall = i965_irq_postinstall;
3488 dev->driver->irq_uninstall = i965_irq_uninstall;
3489 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3490 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3491 }
f71d4af4
JB		 3492 dev->driver->enable_vblank = i915_enable_vblank;
3493 dev->driver->disable_vblank = i915_disable_vblank;
3494 }
3495}
20afbda2
DV		 3496
3497void intel_hpd_init(struct drm_device *dev)
3498{
3499 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3500 struct drm_mode_config *mode_config = &dev->mode_config;
3501 struct drm_connector *connector;
3502 int i;
20afbda2 3503
821450c6
EE		 3504 for (i = 1; i < HPD_NUM_PINS; i++) {
3505 dev_priv->hpd_stats[i].hpd_cnt = 0;
3506 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3507 }
3508 list_for_each_entry(connector, &mode_config->connector_list, head) {
3509 struct intel_connector *intel_connector = to_intel_connector(connector);
3510 connector->polled = intel_connector->polled;
3511 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3512 connector->polled = DRM_CONNECTOR_POLL_HPD;
3513 }
20afbda2
DV		 3514 if (dev_priv->display.hpd_irq_setup)
3515 dev_priv->display.hpd_irq_setup(dev);
3516}
Linux kernel - Deliverables
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