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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 ID |
172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
173 | ||
0706f17c EE |
174 | /* For display hotplug interrupt */ |
175 | static inline void | |
176 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
177 | uint32_t mask, | |
178 | uint32_t bits) | |
179 | { | |
180 | uint32_t val; | |
181 | ||
182 | assert_spin_locked(&dev_priv->irq_lock); | |
183 | WARN_ON(bits & ~mask); | |
184 | ||
185 | val = I915_READ(PORT_HOTPLUG_EN); | |
186 | val &= ~mask; | |
187 | val |= bits; | |
188 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
189 | } | |
190 | ||
191 | /** | |
192 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
193 | * @dev_priv: driver private | |
194 | * @mask: bits to update | |
195 | * @bits: bits to enable | |
196 | * NOTE: the HPD enable bits are modified both inside and outside | |
197 | * of an interrupt context. To avoid that read-modify-write cycles | |
198 | * interfer, these bits are protected by a spinlock. Since this | |
199 | * function is usually not called from a context where the lock is | |
200 | * held already, this function acquires the lock itself. A non-locking | |
201 | * version is also available. | |
202 | */ | |
203 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
204 | uint32_t mask, | |
205 | uint32_t bits) | |
206 | { | |
207 | spin_lock_irq(&dev_priv->irq_lock); | |
208 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
209 | spin_unlock_irq(&dev_priv->irq_lock); | |
210 | } | |
211 | ||
d9dc34f1 VS |
212 | /** |
213 | * ilk_update_display_irq - update DEIMR | |
214 | * @dev_priv: driver private | |
215 | * @interrupt_mask: mask of interrupt bits to update | |
216 | * @enabled_irq_mask: mask of interrupt bits to enable | |
217 | */ | |
fbdedaea VS |
218 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
219 | uint32_t interrupt_mask, | |
220 | uint32_t enabled_irq_mask) | |
036a4a7d | 221 | { |
d9dc34f1 VS |
222 | uint32_t new_val; |
223 | ||
4bc9d430 DV |
224 | assert_spin_locked(&dev_priv->irq_lock); |
225 | ||
d9dc34f1 VS |
226 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
227 | ||
9df7575f | 228 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 229 | return; |
c67a470b | 230 | |
d9dc34f1 VS |
231 | new_val = dev_priv->irq_mask; |
232 | new_val &= ~interrupt_mask; | |
233 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
234 | ||
235 | if (new_val != dev_priv->irq_mask) { | |
236 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 237 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 238 | POSTING_READ(DEIMR); |
036a4a7d ZW |
239 | } |
240 | } | |
241 | ||
43eaea13 PZ |
242 | /** |
243 | * ilk_update_gt_irq - update GTIMR | |
244 | * @dev_priv: driver private | |
245 | * @interrupt_mask: mask of interrupt bits to update | |
246 | * @enabled_irq_mask: mask of interrupt bits to enable | |
247 | */ | |
248 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
249 | uint32_t interrupt_mask, | |
250 | uint32_t enabled_irq_mask) | |
251 | { | |
252 | assert_spin_locked(&dev_priv->irq_lock); | |
253 | ||
15a17aae DV |
254 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
255 | ||
9df7575f | 256 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 257 | return; |
c67a470b | 258 | |
43eaea13 PZ |
259 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
260 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
261 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
262 | POSTING_READ(GTIMR); | |
263 | } | |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
268 | } | |
269 | ||
480c8033 | 270 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
271 | { |
272 | ilk_update_gt_irq(dev_priv, mask, 0); | |
273 | } | |
274 | ||
f0f59a00 | 275 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
276 | { |
277 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
278 | } | |
279 | ||
f0f59a00 | 280 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
281 | { |
282 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
283 | } | |
284 | ||
f0f59a00 | 285 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
286 | { |
287 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
288 | } | |
289 | ||
edbfdb45 | 290 | /** |
81fd874e VS |
291 | * snb_update_pm_irq - update GEN6_PMIMR |
292 | * @dev_priv: driver private | |
293 | * @interrupt_mask: mask of interrupt bits to update | |
294 | * @enabled_irq_mask: mask of interrupt bits to enable | |
295 | */ | |
edbfdb45 PZ |
296 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
297 | uint32_t interrupt_mask, | |
298 | uint32_t enabled_irq_mask) | |
299 | { | |
605cd25b | 300 | uint32_t new_val; |
edbfdb45 | 301 | |
15a17aae DV |
302 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
303 | ||
edbfdb45 PZ |
304 | assert_spin_locked(&dev_priv->irq_lock); |
305 | ||
605cd25b | 306 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
307 | new_val &= ~interrupt_mask; |
308 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
309 | ||
605cd25b PZ |
310 | if (new_val != dev_priv->pm_irq_mask) { |
311 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
312 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
313 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 314 | } |
edbfdb45 PZ |
315 | } |
316 | ||
480c8033 | 317 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 318 | { |
9939fba2 ID |
319 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
320 | return; | |
321 | ||
edbfdb45 PZ |
322 | snb_update_pm_irq(dev_priv, mask, mask); |
323 | } | |
324 | ||
9939fba2 ID |
325 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
326 | uint32_t mask) | |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
9939fba2 ID |
331 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
332 | { | |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
336 | __gen6_disable_pm_irq(dev_priv, mask); | |
337 | } | |
338 | ||
dc97997a | 339 | void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) |
3cc134e3 | 340 | { |
f0f59a00 | 341 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 ID |
342 | |
343 | spin_lock_irq(&dev_priv->irq_lock); | |
344 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
345 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
346 | POSTING_READ(reg); | |
096fad9e | 347 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
348 | spin_unlock_irq(&dev_priv->irq_lock); |
349 | } | |
350 | ||
91d14251 | 351 | void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 352 | { |
b900b949 | 353 | spin_lock_irq(&dev_priv->irq_lock); |
78e68d36 | 354 | |
b900b949 | 355 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 356 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 357 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
358 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
359 | dev_priv->pm_rps_events); | |
b900b949 | 360 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 361 | |
b900b949 ID |
362 | spin_unlock_irq(&dev_priv->irq_lock); |
363 | } | |
364 | ||
59d02a1f ID |
365 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
366 | { | |
1800ad25 | 367 | return (mask & ~dev_priv->rps.pm_intr_keep); |
59d02a1f ID |
368 | } |
369 | ||
91d14251 | 370 | void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) |
b900b949 | 371 | { |
d4d70aa5 ID |
372 | spin_lock_irq(&dev_priv->irq_lock); |
373 | dev_priv->rps.interrupts_enabled = false; | |
374 | spin_unlock_irq(&dev_priv->irq_lock); | |
375 | ||
376 | cancel_work_sync(&dev_priv->rps.work); | |
377 | ||
9939fba2 ID |
378 | spin_lock_irq(&dev_priv->irq_lock); |
379 | ||
59d02a1f | 380 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
381 | |
382 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
383 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
384 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
385 | |
386 | spin_unlock_irq(&dev_priv->irq_lock); | |
387 | ||
91d14251 | 388 | synchronize_irq(dev_priv->dev->irq); |
b900b949 ID |
389 | } |
390 | ||
3a3b3c7d | 391 | /** |
81fd874e VS |
392 | * bdw_update_port_irq - update DE port interrupt |
393 | * @dev_priv: driver private | |
394 | * @interrupt_mask: mask of interrupt bits to update | |
395 | * @enabled_irq_mask: mask of interrupt bits to enable | |
396 | */ | |
3a3b3c7d VS |
397 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
398 | uint32_t interrupt_mask, | |
399 | uint32_t enabled_irq_mask) | |
400 | { | |
401 | uint32_t new_val; | |
402 | uint32_t old_val; | |
403 | ||
404 | assert_spin_locked(&dev_priv->irq_lock); | |
405 | ||
406 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
407 | ||
408 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
409 | return; | |
410 | ||
411 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
412 | ||
413 | new_val = old_val; | |
414 | new_val &= ~interrupt_mask; | |
415 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
416 | ||
417 | if (new_val != old_val) { | |
418 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
419 | POSTING_READ(GEN8_DE_PORT_IMR); | |
420 | } | |
421 | } | |
422 | ||
013d3752 VS |
423 | /** |
424 | * bdw_update_pipe_irq - update DE pipe interrupt | |
425 | * @dev_priv: driver private | |
426 | * @pipe: pipe whose interrupt to update | |
427 | * @interrupt_mask: mask of interrupt bits to update | |
428 | * @enabled_irq_mask: mask of interrupt bits to enable | |
429 | */ | |
430 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
431 | enum pipe pipe, | |
432 | uint32_t interrupt_mask, | |
433 | uint32_t enabled_irq_mask) | |
434 | { | |
435 | uint32_t new_val; | |
436 | ||
437 | assert_spin_locked(&dev_priv->irq_lock); | |
438 | ||
439 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
440 | ||
441 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
442 | return; | |
443 | ||
444 | new_val = dev_priv->de_irq_mask[pipe]; | |
445 | new_val &= ~interrupt_mask; | |
446 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
447 | ||
448 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
449 | dev_priv->de_irq_mask[pipe] = new_val; | |
450 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
451 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
452 | } | |
453 | } | |
454 | ||
fee884ed DV |
455 | /** |
456 | * ibx_display_interrupt_update - update SDEIMR | |
457 | * @dev_priv: driver private | |
458 | * @interrupt_mask: mask of interrupt bits to update | |
459 | * @enabled_irq_mask: mask of interrupt bits to enable | |
460 | */ | |
47339cd9 DV |
461 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
462 | uint32_t interrupt_mask, | |
463 | uint32_t enabled_irq_mask) | |
fee884ed DV |
464 | { |
465 | uint32_t sdeimr = I915_READ(SDEIMR); | |
466 | sdeimr &= ~interrupt_mask; | |
467 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
468 | ||
15a17aae DV |
469 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
470 | ||
fee884ed DV |
471 | assert_spin_locked(&dev_priv->irq_lock); |
472 | ||
9df7575f | 473 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 474 | return; |
c67a470b | 475 | |
fee884ed DV |
476 | I915_WRITE(SDEIMR, sdeimr); |
477 | POSTING_READ(SDEIMR); | |
478 | } | |
8664281b | 479 | |
b5ea642a | 480 | static void |
755e9019 ID |
481 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
482 | u32 enable_mask, u32 status_mask) | |
7c463586 | 483 | { |
f0f59a00 | 484 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 485 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 486 | |
b79480ba | 487 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 488 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 489 | |
04feced9 VS |
490 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
491 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
492 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
493 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
494 | return; |
495 | ||
496 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
497 | return; |
498 | ||
91d181dd ID |
499 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
500 | ||
46c06a30 | 501 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 502 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
503 | I915_WRITE(reg, pipestat); |
504 | POSTING_READ(reg); | |
7c463586 KP |
505 | } |
506 | ||
b5ea642a | 507 | static void |
755e9019 ID |
508 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
509 | u32 enable_mask, u32 status_mask) | |
7c463586 | 510 | { |
f0f59a00 | 511 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 512 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 513 | |
b79480ba | 514 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 515 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 516 | |
04feced9 VS |
517 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
518 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
519 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
520 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
521 | return; |
522 | ||
755e9019 ID |
523 | if ((pipestat & enable_mask) == 0) |
524 | return; | |
525 | ||
91d181dd ID |
526 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
527 | ||
755e9019 | 528 | pipestat &= ~enable_mask; |
46c06a30 VS |
529 | I915_WRITE(reg, pipestat); |
530 | POSTING_READ(reg); | |
7c463586 KP |
531 | } |
532 | ||
10c59c51 ID |
533 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
534 | { | |
535 | u32 enable_mask = status_mask << 16; | |
536 | ||
537 | /* | |
724a6905 VS |
538 | * On pipe A we don't support the PSR interrupt yet, |
539 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
540 | */ |
541 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
542 | return 0; | |
724a6905 VS |
543 | /* |
544 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
545 | * A the same bit is for perf counters which we don't use either. | |
546 | */ | |
547 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
548 | return 0; | |
10c59c51 ID |
549 | |
550 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
551 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
552 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
553 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
554 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
555 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
556 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
557 | ||
558 | return enable_mask; | |
559 | } | |
560 | ||
755e9019 ID |
561 | void |
562 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
563 | u32 status_mask) | |
564 | { | |
565 | u32 enable_mask; | |
566 | ||
666a4537 | 567 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
568 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
569 | status_mask); | |
570 | else | |
571 | enable_mask = status_mask << 16; | |
755e9019 ID |
572 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
573 | } | |
574 | ||
575 | void | |
576 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
577 | u32 status_mask) | |
578 | { | |
579 | u32 enable_mask; | |
580 | ||
666a4537 | 581 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
582 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
583 | status_mask); | |
584 | else | |
585 | enable_mask = status_mask << 16; | |
755e9019 ID |
586 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
587 | } | |
588 | ||
01c66889 | 589 | /** |
f49e38dd | 590 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
468f9d29 | 591 | * @dev: drm device |
01c66889 | 592 | */ |
91d14251 | 593 | static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) |
01c66889 | 594 | { |
91d14251 | 595 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv)) |
f49e38dd JN |
596 | return; |
597 | ||
13321786 | 598 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 599 | |
755e9019 | 600 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
91d14251 | 601 | if (INTEL_GEN(dev_priv) >= 4) |
3b6c42e8 | 602 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 603 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 604 | |
13321786 | 605 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
606 | } |
607 | ||
f75f3746 VS |
608 | /* |
609 | * This timing diagram depicts the video signal in and | |
610 | * around the vertical blanking period. | |
611 | * | |
612 | * Assumptions about the fictitious mode used in this example: | |
613 | * vblank_start >= 3 | |
614 | * vsync_start = vblank_start + 1 | |
615 | * vsync_end = vblank_start + 2 | |
616 | * vtotal = vblank_start + 3 | |
617 | * | |
618 | * start of vblank: | |
619 | * latch double buffered registers | |
620 | * increment frame counter (ctg+) | |
621 | * generate start of vblank interrupt (gen4+) | |
622 | * | | |
623 | * | frame start: | |
624 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
625 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
626 | * | | | |
627 | * | | start of vsync: | |
628 | * | | generate vsync interrupt | |
629 | * | | | | |
630 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
631 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
632 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
633 | * | | <----vs-----> | | |
634 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
635 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
636 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
637 | * | | | | |
638 | * last visible pixel first visible pixel | |
639 | * | increment frame counter (gen3/4) | |
640 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
641 | * | |
642 | * x = horizontal active | |
643 | * _ = horizontal blanking | |
644 | * hs = horizontal sync | |
645 | * va = vertical active | |
646 | * vb = vertical blanking | |
647 | * vs = vertical sync | |
648 | * vbs = vblank_start (number) | |
649 | * | |
650 | * Summary: | |
651 | * - most events happen at the start of horizontal sync | |
652 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
653 | * (depending on PIPECONF settings) after the start of vblank | |
654 | * - gen3/4 pixel and frame counter are synchronized with the start | |
655 | * of horizontal active on the first line of vertical active | |
656 | */ | |
657 | ||
88e72717 | 658 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
4cdb83ec VS |
659 | { |
660 | /* Gen2 doesn't have a hardware frame counter */ | |
661 | return 0; | |
662 | } | |
663 | ||
42f52ef8 KP |
664 | /* Called from drm generic code, passed a 'crtc', which |
665 | * we use as a pipe index | |
666 | */ | |
88e72717 | 667 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 668 | { |
2d1013dd | 669 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 670 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 671 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
672 | struct intel_crtc *intel_crtc = |
673 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 674 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 675 | |
f3a5c3f6 DV |
676 | htotal = mode->crtc_htotal; |
677 | hsync_start = mode->crtc_hsync_start; | |
678 | vbl_start = mode->crtc_vblank_start; | |
679 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
680 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 681 | |
0b2a8e09 VS |
682 | /* Convert to pixel count */ |
683 | vbl_start *= htotal; | |
684 | ||
685 | /* Start of vblank event occurs at start of hsync */ | |
686 | vbl_start -= htotal - hsync_start; | |
687 | ||
9db4a9c7 JB |
688 | high_frame = PIPEFRAME(pipe); |
689 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 690 | |
0a3e67a4 JB |
691 | /* |
692 | * High & low register fields aren't synchronized, so make sure | |
693 | * we get a low value that's stable across two reads of the high | |
694 | * register. | |
695 | */ | |
696 | do { | |
5eddb70b | 697 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 698 | low = I915_READ(low_frame); |
5eddb70b | 699 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
700 | } while (high1 != high2); |
701 | ||
5eddb70b | 702 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 703 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 704 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
705 | |
706 | /* | |
707 | * The frame counter increments at beginning of active. | |
708 | * Cook up a vblank counter by also checking the pixel | |
709 | * counter against vblank start. | |
710 | */ | |
edc08d0a | 711 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
712 | } |
713 | ||
974e59ba | 714 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 715 | { |
2d1013dd | 716 | struct drm_i915_private *dev_priv = dev->dev_private; |
9880b7a5 | 717 | |
649636ef | 718 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
719 | } |
720 | ||
75aa3f63 | 721 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
722 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
723 | { | |
724 | struct drm_device *dev = crtc->base.dev; | |
725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 726 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 727 | enum pipe pipe = crtc->pipe; |
80715b2f | 728 | int position, vtotal; |
a225f079 | 729 | |
80715b2f | 730 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
731 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
732 | vtotal /= 2; | |
733 | ||
91d14251 | 734 | if (IS_GEN2(dev_priv)) |
75aa3f63 | 735 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 736 | else |
75aa3f63 | 737 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 738 | |
41b578fb JB |
739 | /* |
740 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
741 | * read it just before the start of vblank. So try it again | |
742 | * so we don't accidentally end up spanning a vblank frame | |
743 | * increment, causing the pipe_update_end() code to squak at us. | |
744 | * | |
745 | * The nature of this problem means we can't simply check the ISR | |
746 | * bit and return the vblank start value; nor can we use the scanline | |
747 | * debug register in the transcoder as it appears to have the same | |
748 | * problem. We may need to extend this to include other platforms, | |
749 | * but so far testing only shows the problem on HSW. | |
750 | */ | |
91d14251 | 751 | if (HAS_DDI(dev_priv) && !position) { |
41b578fb JB |
752 | int i, temp; |
753 | ||
754 | for (i = 0; i < 100; i++) { | |
755 | udelay(1); | |
756 | temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & | |
757 | DSL_LINEMASK_GEN3; | |
758 | if (temp != position) { | |
759 | position = temp; | |
760 | break; | |
761 | } | |
762 | } | |
763 | } | |
764 | ||
a225f079 | 765 | /* |
80715b2f VS |
766 | * See update_scanline_offset() for the details on the |
767 | * scanline_offset adjustment. | |
a225f079 | 768 | */ |
80715b2f | 769 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
770 | } |
771 | ||
88e72717 | 772 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
abca9e45 | 773 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
774 | ktime_t *stime, ktime_t *etime, |
775 | const struct drm_display_mode *mode) | |
0af7e4df | 776 | { |
c2baf4b7 VS |
777 | struct drm_i915_private *dev_priv = dev->dev_private; |
778 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3aa18df8 | 780 | int position; |
78e8fc6b | 781 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
782 | bool in_vbl = true; |
783 | int ret = 0; | |
ad3543ed | 784 | unsigned long irqflags; |
0af7e4df | 785 | |
fc467a22 | 786 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 787 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 788 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
789 | return 0; |
790 | } | |
791 | ||
c2baf4b7 | 792 | htotal = mode->crtc_htotal; |
78e8fc6b | 793 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
794 | vtotal = mode->crtc_vtotal; |
795 | vbl_start = mode->crtc_vblank_start; | |
796 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 797 | |
d31faf65 VS |
798 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
799 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
800 | vbl_end /= 2; | |
801 | vtotal /= 2; | |
802 | } | |
803 | ||
c2baf4b7 VS |
804 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
805 | ||
ad3543ed MK |
806 | /* |
807 | * Lock uncore.lock, as we will do multiple timing critical raw | |
808 | * register reads, potentially with preemption disabled, so the | |
809 | * following code must not block on uncore.lock. | |
810 | */ | |
811 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 812 | |
ad3543ed MK |
813 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
814 | ||
815 | /* Get optional system timestamp before query. */ | |
816 | if (stime) | |
817 | *stime = ktime_get(); | |
818 | ||
91d14251 | 819 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
0af7e4df MK |
820 | /* No obvious pixelcount register. Only query vertical |
821 | * scanout position from Display scan line register. | |
822 | */ | |
a225f079 | 823 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
824 | } else { |
825 | /* Have access to pixelcount since start of frame. | |
826 | * We can split this into vertical and horizontal | |
827 | * scanout position. | |
828 | */ | |
75aa3f63 | 829 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 830 | |
3aa18df8 VS |
831 | /* convert to pixel counts */ |
832 | vbl_start *= htotal; | |
833 | vbl_end *= htotal; | |
834 | vtotal *= htotal; | |
78e8fc6b | 835 | |
7e78f1cb VS |
836 | /* |
837 | * In interlaced modes, the pixel counter counts all pixels, | |
838 | * so one field will have htotal more pixels. In order to avoid | |
839 | * the reported position from jumping backwards when the pixel | |
840 | * counter is beyond the length of the shorter field, just | |
841 | * clamp the position the length of the shorter field. This | |
842 | * matches how the scanline counter based position works since | |
843 | * the scanline counter doesn't count the two half lines. | |
844 | */ | |
845 | if (position >= vtotal) | |
846 | position = vtotal - 1; | |
847 | ||
78e8fc6b VS |
848 | /* |
849 | * Start of vblank interrupt is triggered at start of hsync, | |
850 | * just prior to the first active line of vblank. However we | |
851 | * consider lines to start at the leading edge of horizontal | |
852 | * active. So, should we get here before we've crossed into | |
853 | * the horizontal active of the first line in vblank, we would | |
854 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
855 | * always add htotal-hsync_start to the current pixel position. | |
856 | */ | |
857 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
858 | } |
859 | ||
ad3543ed MK |
860 | /* Get optional system timestamp after query. */ |
861 | if (etime) | |
862 | *etime = ktime_get(); | |
863 | ||
864 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
865 | ||
866 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
867 | ||
3aa18df8 VS |
868 | in_vbl = position >= vbl_start && position < vbl_end; |
869 | ||
870 | /* | |
871 | * While in vblank, position will be negative | |
872 | * counting up towards 0 at vbl_end. And outside | |
873 | * vblank, position will be positive counting | |
874 | * up since vbl_end. | |
875 | */ | |
876 | if (position >= vbl_start) | |
877 | position -= vbl_end; | |
878 | else | |
879 | position += vtotal - vbl_end; | |
0af7e4df | 880 | |
91d14251 | 881 | if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3aa18df8 VS |
882 | *vpos = position; |
883 | *hpos = 0; | |
884 | } else { | |
885 | *vpos = position / htotal; | |
886 | *hpos = position - (*vpos * htotal); | |
887 | } | |
0af7e4df | 888 | |
0af7e4df MK |
889 | /* In vblank? */ |
890 | if (in_vbl) | |
3d3cbd84 | 891 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
892 | |
893 | return ret; | |
894 | } | |
895 | ||
a225f079 VS |
896 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
897 | { | |
898 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
899 | unsigned long irqflags; | |
900 | int position; | |
901 | ||
902 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
903 | position = __intel_get_crtc_scanline(crtc); | |
904 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
905 | ||
906 | return position; | |
907 | } | |
908 | ||
88e72717 | 909 | static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, |
0af7e4df MK |
910 | int *max_error, |
911 | struct timeval *vblank_time, | |
912 | unsigned flags) | |
913 | { | |
4041b853 | 914 | struct drm_crtc *crtc; |
0af7e4df | 915 | |
88e72717 TR |
916 | if (pipe >= INTEL_INFO(dev)->num_pipes) { |
917 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
0af7e4df MK |
918 | return -EINVAL; |
919 | } | |
920 | ||
921 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
922 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
923 | if (crtc == NULL) { | |
88e72717 | 924 | DRM_ERROR("Invalid crtc %u\n", pipe); |
4041b853 CW |
925 | return -EINVAL; |
926 | } | |
927 | ||
fc467a22 | 928 | if (!crtc->hwmode.crtc_clock) { |
88e72717 | 929 | DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); |
4041b853 CW |
930 | return -EBUSY; |
931 | } | |
0af7e4df MK |
932 | |
933 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
934 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
935 | vblank_time, flags, | |
fc467a22 | 936 | &crtc->hwmode); |
0af7e4df MK |
937 | } |
938 | ||
91d14251 | 939 | static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) |
f97108d1 | 940 | { |
b5b72e89 | 941 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 942 | u8 new_delay; |
9270388e | 943 | |
d0ecd7e2 | 944 | spin_lock(&mchdev_lock); |
f97108d1 | 945 | |
73edd18f DV |
946 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
947 | ||
20e4d407 | 948 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 949 | |
7648fa99 | 950 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
951 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
952 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
953 | max_avg = I915_READ(RCBMAXAVG); |
954 | min_avg = I915_READ(RCBMINAVG); | |
955 | ||
956 | /* Handle RCS change request from hw */ | |
b5b72e89 | 957 | if (busy_up > max_avg) { |
20e4d407 DV |
958 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
959 | new_delay = dev_priv->ips.cur_delay - 1; | |
960 | if (new_delay < dev_priv->ips.max_delay) | |
961 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 962 | } else if (busy_down < min_avg) { |
20e4d407 DV |
963 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
964 | new_delay = dev_priv->ips.cur_delay + 1; | |
965 | if (new_delay > dev_priv->ips.min_delay) | |
966 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
967 | } |
968 | ||
91d14251 | 969 | if (ironlake_set_drps(dev_priv, new_delay)) |
20e4d407 | 970 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 971 | |
d0ecd7e2 | 972 | spin_unlock(&mchdev_lock); |
9270388e | 973 | |
f97108d1 JB |
974 | return; |
975 | } | |
976 | ||
0bc40be8 | 977 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 978 | { |
117897f4 | 979 | if (!intel_engine_initialized(engine)) |
475553de CW |
980 | return; |
981 | ||
0bc40be8 | 982 | trace_i915_gem_request_notify(engine); |
12471ba8 | 983 | engine->user_interrupts++; |
9862e600 | 984 | |
0bc40be8 | 985 | wake_up_all(&engine->irq_queue); |
549f7365 CW |
986 | } |
987 | ||
43cf3bf0 CW |
988 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
989 | struct intel_rps_ei *ei) | |
31685c25 | 990 | { |
43cf3bf0 CW |
991 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
992 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
993 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
994 | } | |
31685c25 | 995 | |
43cf3bf0 CW |
996 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
997 | const struct intel_rps_ei *old, | |
998 | const struct intel_rps_ei *now, | |
999 | int threshold) | |
1000 | { | |
1001 | u64 time, c0; | |
7bad74d5 | 1002 | unsigned int mul = 100; |
31685c25 | 1003 | |
43cf3bf0 CW |
1004 | if (old->cz_clock == 0) |
1005 | return false; | |
31685c25 | 1006 | |
7bad74d5 VS |
1007 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
1008 | mul <<= 8; | |
1009 | ||
43cf3bf0 | 1010 | time = now->cz_clock - old->cz_clock; |
7bad74d5 | 1011 | time *= threshold * dev_priv->czclk_freq; |
31685c25 | 1012 | |
43cf3bf0 CW |
1013 | /* Workload can be split between render + media, e.g. SwapBuffers |
1014 | * being blitted in X after being rendered in mesa. To account for | |
1015 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1016 | */ |
43cf3bf0 CW |
1017 | c0 = now->render_c0 - old->render_c0; |
1018 | c0 += now->media_c0 - old->media_c0; | |
7bad74d5 | 1019 | c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
31685c25 | 1020 | |
43cf3bf0 | 1021 | return c0 >= time; |
31685c25 D |
1022 | } |
1023 | ||
43cf3bf0 | 1024 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1025 | { |
43cf3bf0 CW |
1026 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1027 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1028 | } |
31685c25 | 1029 | |
43cf3bf0 CW |
1030 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1031 | { | |
1032 | struct intel_rps_ei now; | |
1033 | u32 events = 0; | |
31685c25 | 1034 | |
6f4b12f8 | 1035 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1036 | return 0; |
31685c25 | 1037 | |
43cf3bf0 CW |
1038 | vlv_c0_read(dev_priv, &now); |
1039 | if (now.cz_clock == 0) | |
1040 | return 0; | |
31685c25 | 1041 | |
43cf3bf0 CW |
1042 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1043 | if (!vlv_c0_above(dev_priv, | |
1044 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1045 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1046 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1047 | dev_priv->rps.down_ei = now; | |
1048 | } | |
31685c25 | 1049 | |
43cf3bf0 CW |
1050 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1051 | if (vlv_c0_above(dev_priv, | |
1052 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1053 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1054 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1055 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1056 | } |
1057 | ||
43cf3bf0 | 1058 | return events; |
31685c25 D |
1059 | } |
1060 | ||
f5a4c67d CW |
1061 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1062 | { | |
e2f80391 | 1063 | struct intel_engine_cs *engine; |
f5a4c67d | 1064 | |
b4ac5afc | 1065 | for_each_engine(engine, dev_priv) |
e2f80391 | 1066 | if (engine->irq_refcount) |
f5a4c67d CW |
1067 | return true; |
1068 | ||
1069 | return false; | |
1070 | } | |
1071 | ||
4912d041 | 1072 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1073 | { |
2d1013dd JN |
1074 | struct drm_i915_private *dev_priv = |
1075 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1076 | bool client_boost; |
1077 | int new_delay, adj, min, max; | |
edbfdb45 | 1078 | u32 pm_iir; |
4912d041 | 1079 | |
59cdb63d | 1080 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1081 | /* Speed up work cancelation during disabling rps interrupts. */ |
1082 | if (!dev_priv->rps.interrupts_enabled) { | |
1083 | spin_unlock_irq(&dev_priv->irq_lock); | |
1084 | return; | |
1085 | } | |
1f814dac ID |
1086 | |
1087 | /* | |
1088 | * The RPS work is synced during runtime suspend, we don't require a | |
1089 | * wakeref. TODO: instead of disabling the asserts make sure that we | |
1090 | * always hold an RPM reference while the work is running. | |
1091 | */ | |
1092 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
1093 | ||
c6a828d3 DV |
1094 | pm_iir = dev_priv->rps.pm_iir; |
1095 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1096 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1097 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1098 | client_boost = dev_priv->rps.client_boost; |
1099 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1100 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1101 | |
60611c13 | 1102 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1103 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1104 | |
8d3afd7d | 1105 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
1f814dac | 1106 | goto out; |
3b8d8d91 | 1107 | |
4fc688ce | 1108 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1109 | |
43cf3bf0 CW |
1110 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1111 | ||
dd75fdc8 | 1112 | adj = dev_priv->rps.last_adj; |
edcf284b | 1113 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1114 | min = dev_priv->rps.min_freq_softlimit; |
1115 | max = dev_priv->rps.max_freq_softlimit; | |
1116 | ||
1117 | if (client_boost) { | |
1118 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1119 | adj = 0; | |
1120 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1121 | if (adj > 0) |
1122 | adj *= 2; | |
edcf284b CW |
1123 | else /* CHV needs even encode values */ |
1124 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1125 | /* |
1126 | * For better performance, jump directly | |
1127 | * to RPe if we're below it. | |
1128 | */ | |
edcf284b | 1129 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1130 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1131 | adj = 0; |
1132 | } | |
f5a4c67d CW |
1133 | } else if (any_waiters(dev_priv)) { |
1134 | adj = 0; | |
dd75fdc8 | 1135 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1136 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1137 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1138 | else |
b39fb297 | 1139 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1140 | adj = 0; |
1141 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1142 | if (adj < 0) | |
1143 | adj *= 2; | |
edcf284b CW |
1144 | else /* CHV needs even encode values */ |
1145 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1146 | } else { /* unknown event */ |
edcf284b | 1147 | adj = 0; |
dd75fdc8 | 1148 | } |
3b8d8d91 | 1149 | |
edcf284b CW |
1150 | dev_priv->rps.last_adj = adj; |
1151 | ||
79249636 BW |
1152 | /* sysfs frequency interfaces may have snuck in while servicing the |
1153 | * interrupt | |
1154 | */ | |
edcf284b | 1155 | new_delay += adj; |
8d3afd7d | 1156 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1157 | |
dc97997a | 1158 | intel_set_rps(dev_priv, new_delay); |
3b8d8d91 | 1159 | |
4fc688ce | 1160 | mutex_unlock(&dev_priv->rps.hw_lock); |
1f814dac ID |
1161 | out: |
1162 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3b8d8d91 JB |
1163 | } |
1164 | ||
e3689190 BW |
1165 | |
1166 | /** | |
1167 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1168 | * occurred. | |
1169 | * @work: workqueue struct | |
1170 | * | |
1171 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1172 | * this event, userspace should try to remap the bad rows since statistically | |
1173 | * it is likely the same row is more likely to go bad again. | |
1174 | */ | |
1175 | static void ivybridge_parity_work(struct work_struct *work) | |
1176 | { | |
2d1013dd JN |
1177 | struct drm_i915_private *dev_priv = |
1178 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1179 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1180 | char *parity_event[6]; |
e3689190 | 1181 | uint32_t misccpctl; |
35a85ac6 | 1182 | uint8_t slice = 0; |
e3689190 BW |
1183 | |
1184 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1185 | * In order to prevent a get/put style interface, acquire struct mutex | |
1186 | * any time we access those registers. | |
1187 | */ | |
1188 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1189 | ||
35a85ac6 BW |
1190 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1191 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1192 | goto out; | |
1193 | ||
e3689190 BW |
1194 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1195 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1196 | POSTING_READ(GEN7_MISCCPCTL); | |
1197 | ||
35a85ac6 | 1198 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1199 | i915_reg_t reg; |
e3689190 | 1200 | |
35a85ac6 | 1201 | slice--; |
2d1fe073 | 1202 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1203 | break; |
e3689190 | 1204 | |
35a85ac6 | 1205 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1206 | |
6fa1c5f1 | 1207 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1208 | |
35a85ac6 BW |
1209 | error_status = I915_READ(reg); |
1210 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1211 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1212 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1213 | ||
1214 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1215 | POSTING_READ(reg); | |
1216 | ||
1217 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1218 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1219 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1220 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1221 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1222 | parity_event[5] = NULL; | |
1223 | ||
5bdebb18 | 1224 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1225 | KOBJ_CHANGE, parity_event); |
e3689190 | 1226 | |
35a85ac6 BW |
1227 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1228 | slice, row, bank, subbank); | |
e3689190 | 1229 | |
35a85ac6 BW |
1230 | kfree(parity_event[4]); |
1231 | kfree(parity_event[3]); | |
1232 | kfree(parity_event[2]); | |
1233 | kfree(parity_event[1]); | |
1234 | } | |
e3689190 | 1235 | |
35a85ac6 | 1236 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1237 | |
35a85ac6 BW |
1238 | out: |
1239 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1240 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1241 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1242 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1243 | |
1244 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1245 | } |
1246 | ||
261e40b8 VS |
1247 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1248 | u32 iir) | |
e3689190 | 1249 | { |
261e40b8 | 1250 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1251 | return; |
1252 | ||
d0ecd7e2 | 1253 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1254 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1255 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1256 | |
261e40b8 | 1257 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1258 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1259 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1260 | ||
1261 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1262 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1263 | ||
a4da4fa4 | 1264 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1265 | } |
1266 | ||
261e40b8 | 1267 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1268 | u32 gt_iir) |
1269 | { | |
1270 | if (gt_iir & | |
1271 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1272 | notify_ring(&dev_priv->engine[RCS]); |
f1af8fc1 | 1273 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
4a570db5 | 1274 | notify_ring(&dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1275 | } |
1276 | ||
261e40b8 | 1277 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1278 | u32 gt_iir) |
1279 | { | |
1280 | ||
cc609d5d BW |
1281 | if (gt_iir & |
1282 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1283 | notify_ring(&dev_priv->engine[RCS]); |
cc609d5d | 1284 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
4a570db5 | 1285 | notify_ring(&dev_priv->engine[VCS]); |
cc609d5d | 1286 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
4a570db5 | 1287 | notify_ring(&dev_priv->engine[BCS]); |
e7b4c6b1 | 1288 | |
cc609d5d BW |
1289 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1290 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1291 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1292 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1293 | |
261e40b8 VS |
1294 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1295 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1296 | } |
1297 | ||
fbcc1a0c | 1298 | static __always_inline void |
0bc40be8 | 1299 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c NH |
1300 | { |
1301 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) | |
0bc40be8 | 1302 | notify_ring(engine); |
fbcc1a0c | 1303 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) |
27af5eea | 1304 | tasklet_schedule(&engine->irq_tasklet); |
fbcc1a0c NH |
1305 | } |
1306 | ||
e30e251a VS |
1307 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1308 | u32 master_ctl, | |
1309 | u32 gt_iir[4]) | |
abd58f01 | 1310 | { |
abd58f01 BW |
1311 | irqreturn_t ret = IRQ_NONE; |
1312 | ||
1313 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1314 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1315 | if (gt_iir[0]) { | |
1316 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1317 | ret = IRQ_HANDLED; |
abd58f01 BW |
1318 | } else |
1319 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1320 | } | |
1321 | ||
85f9b5f9 | 1322 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1323 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1324 | if (gt_iir[1]) { | |
1325 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1326 | ret = IRQ_HANDLED; |
0961021a | 1327 | } else |
abd58f01 | 1328 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1329 | } |
1330 | ||
abd58f01 | 1331 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1332 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1333 | if (gt_iir[3]) { | |
1334 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1335 | ret = IRQ_HANDLED; |
abd58f01 BW |
1336 | } else |
1337 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1338 | } | |
1339 | ||
0961021a | 1340 | if (master_ctl & GEN8_GT_PM_IRQ) { |
e30e251a VS |
1341 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
1342 | if (gt_iir[2] & dev_priv->pm_rps_events) { | |
cb0d205e | 1343 | I915_WRITE_FW(GEN8_GT_IIR(2), |
e30e251a | 1344 | gt_iir[2] & dev_priv->pm_rps_events); |
38cc46d7 | 1345 | ret = IRQ_HANDLED; |
0961021a BW |
1346 | } else |
1347 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1348 | } | |
1349 | ||
abd58f01 BW |
1350 | return ret; |
1351 | } | |
1352 | ||
e30e251a VS |
1353 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1354 | u32 gt_iir[4]) | |
1355 | { | |
1356 | if (gt_iir[0]) { | |
1357 | gen8_cs_irq_handler(&dev_priv->engine[RCS], | |
1358 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); | |
1359 | gen8_cs_irq_handler(&dev_priv->engine[BCS], | |
1360 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); | |
1361 | } | |
1362 | ||
1363 | if (gt_iir[1]) { | |
1364 | gen8_cs_irq_handler(&dev_priv->engine[VCS], | |
1365 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); | |
1366 | gen8_cs_irq_handler(&dev_priv->engine[VCS2], | |
1367 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); | |
1368 | } | |
1369 | ||
1370 | if (gt_iir[3]) | |
1371 | gen8_cs_irq_handler(&dev_priv->engine[VECS], | |
1372 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); | |
1373 | ||
1374 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1375 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
1376 | } | |
1377 | ||
63c88d22 ID |
1378 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1379 | { | |
1380 | switch (port) { | |
1381 | case PORT_A: | |
195baa06 | 1382 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1383 | case PORT_B: |
1384 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1385 | case PORT_C: | |
1386 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1387 | default: |
1388 | return false; | |
1389 | } | |
1390 | } | |
1391 | ||
6dbf30ce VS |
1392 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1393 | { | |
1394 | switch (port) { | |
1395 | case PORT_E: | |
1396 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1397 | default: | |
1398 | return false; | |
1399 | } | |
1400 | } | |
1401 | ||
74c0b395 VS |
1402 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1403 | { | |
1404 | switch (port) { | |
1405 | case PORT_A: | |
1406 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1407 | case PORT_B: | |
1408 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1409 | case PORT_C: | |
1410 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1411 | case PORT_D: | |
1412 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1413 | default: | |
1414 | return false; | |
1415 | } | |
1416 | } | |
1417 | ||
e4ce95aa VS |
1418 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1419 | { | |
1420 | switch (port) { | |
1421 | case PORT_A: | |
1422 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1423 | default: | |
1424 | return false; | |
1425 | } | |
1426 | } | |
1427 | ||
676574df | 1428 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1429 | { |
1430 | switch (port) { | |
13cf5504 | 1431 | case PORT_B: |
676574df | 1432 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1433 | case PORT_C: |
676574df | 1434 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1435 | case PORT_D: |
676574df JN |
1436 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1437 | default: | |
1438 | return false; | |
13cf5504 DA |
1439 | } |
1440 | } | |
1441 | ||
676574df | 1442 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1443 | { |
1444 | switch (port) { | |
13cf5504 | 1445 | case PORT_B: |
676574df | 1446 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1447 | case PORT_C: |
676574df | 1448 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1449 | case PORT_D: |
676574df JN |
1450 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1451 | default: | |
1452 | return false; | |
13cf5504 DA |
1453 | } |
1454 | } | |
1455 | ||
42db67d6 VS |
1456 | /* |
1457 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1458 | * This can be called multiple times with the same masks to accumulate | |
1459 | * hotplug detection results from several registers. | |
1460 | * | |
1461 | * Note that the caller is expected to zero out the masks initially. | |
1462 | */ | |
fd63e2a9 | 1463 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1464 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1465 | const u32 hpd[HPD_NUM_PINS], |
1466 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1467 | { |
8c841e57 | 1468 | enum port port; |
676574df JN |
1469 | int i; |
1470 | ||
676574df | 1471 | for_each_hpd_pin(i) { |
8c841e57 JN |
1472 | if ((hpd[i] & hotplug_trigger) == 0) |
1473 | continue; | |
676574df | 1474 | |
8c841e57 JN |
1475 | *pin_mask |= BIT(i); |
1476 | ||
cc24fcdc ID |
1477 | if (!intel_hpd_pin_to_port(i, &port)) |
1478 | continue; | |
1479 | ||
fd63e2a9 | 1480 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1481 | *long_mask |= BIT(i); |
676574df JN |
1482 | } |
1483 | ||
1484 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1485 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1486 | ||
1487 | } | |
1488 | ||
91d14251 | 1489 | static void gmbus_irq_handler(struct drm_i915_private *dev_priv) |
515ac2bb | 1490 | { |
28c70f16 | 1491 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1492 | } |
1493 | ||
91d14251 | 1494 | static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) |
ce99c256 | 1495 | { |
9ee32fea | 1496 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1497 | } |
1498 | ||
8bf1e9f1 | 1499 | #if defined(CONFIG_DEBUG_FS) |
91d14251 TU |
1500 | static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1501 | enum pipe pipe, | |
277de95e DV |
1502 | uint32_t crc0, uint32_t crc1, |
1503 | uint32_t crc2, uint32_t crc3, | |
1504 | uint32_t crc4) | |
8bf1e9f1 | 1505 | { |
8bf1e9f1 SH |
1506 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
1507 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1508 | int head, tail; |
b2c88f5b | 1509 | |
d538bbdf DL |
1510 | spin_lock(&pipe_crc->lock); |
1511 | ||
0c912c79 | 1512 | if (!pipe_crc->entries) { |
d538bbdf | 1513 | spin_unlock(&pipe_crc->lock); |
34273620 | 1514 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1515 | return; |
1516 | } | |
1517 | ||
d538bbdf DL |
1518 | head = pipe_crc->head; |
1519 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1520 | |
1521 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1522 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1523 | DRM_ERROR("CRC buffer overflowing\n"); |
1524 | return; | |
1525 | } | |
1526 | ||
1527 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1528 | |
91d14251 TU |
1529 | entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev, |
1530 | pipe); | |
eba94eb9 DV |
1531 | entry->crc[0] = crc0; |
1532 | entry->crc[1] = crc1; | |
1533 | entry->crc[2] = crc2; | |
1534 | entry->crc[3] = crc3; | |
1535 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1536 | |
1537 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1538 | pipe_crc->head = head; |
1539 | ||
1540 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1541 | |
1542 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1543 | } |
277de95e DV |
1544 | #else |
1545 | static inline void | |
91d14251 TU |
1546 | display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1547 | enum pipe pipe, | |
277de95e DV |
1548 | uint32_t crc0, uint32_t crc1, |
1549 | uint32_t crc2, uint32_t crc3, | |
1550 | uint32_t crc4) {} | |
1551 | #endif | |
1552 | ||
eba94eb9 | 1553 | |
91d14251 TU |
1554 | static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1555 | enum pipe pipe) | |
5a69b89f | 1556 | { |
91d14251 | 1557 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1558 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1559 | 0, 0, 0, 0); | |
5a69b89f DV |
1560 | } |
1561 | ||
91d14251 TU |
1562 | static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1563 | enum pipe pipe) | |
eba94eb9 | 1564 | { |
91d14251 | 1565 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1566 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), |
1567 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1568 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1569 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1570 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1571 | } |
5b3a856b | 1572 | |
91d14251 TU |
1573 | static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, |
1574 | enum pipe pipe) | |
5b3a856b | 1575 | { |
0b5c5ed0 DV |
1576 | uint32_t res1, res2; |
1577 | ||
91d14251 | 1578 | if (INTEL_GEN(dev_priv) >= 3) |
0b5c5ed0 DV |
1579 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); |
1580 | else | |
1581 | res1 = 0; | |
1582 | ||
91d14251 | 1583 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
0b5c5ed0 DV |
1584 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); |
1585 | else | |
1586 | res2 = 0; | |
5b3a856b | 1587 | |
91d14251 | 1588 | display_pipe_crc_irq_handler(dev_priv, pipe, |
277de95e DV |
1589 | I915_READ(PIPE_CRC_RES_RED(pipe)), |
1590 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1591 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1592 | res1, res2); | |
5b3a856b | 1593 | } |
8bf1e9f1 | 1594 | |
1403c0d4 PZ |
1595 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1596 | * IMR bits until the work is done. Other interrupts can be processed without | |
1597 | * the work queue. */ | |
1598 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1599 | { |
a6706b45 | 1600 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1601 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1602 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1603 | if (dev_priv->rps.interrupts_enabled) { |
1604 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1605 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1606 | } | |
59cdb63d | 1607 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1608 | } |
baf02a1f | 1609 | |
c9a9a268 ID |
1610 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1611 | return; | |
1612 | ||
2d1fe073 | 1613 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1614 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
4a570db5 | 1615 | notify_ring(&dev_priv->engine[VECS]); |
12638c57 | 1616 | |
aaecdf61 DV |
1617 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1618 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1619 | } |
baf02a1f BW |
1620 | } |
1621 | ||
5a21b665 | 1622 | static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, |
91d14251 | 1623 | enum pipe pipe) |
8d7849db | 1624 | { |
5a21b665 DV |
1625 | bool ret; |
1626 | ||
1627 | ret = drm_handle_vblank(dev_priv->dev, pipe); | |
1628 | if (ret) | |
51cbaf01 | 1629 | intel_finish_page_flip_mmio(dev_priv, pipe); |
5a21b665 DV |
1630 | |
1631 | return ret; | |
8d7849db VS |
1632 | } |
1633 | ||
91d14251 TU |
1634 | static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, |
1635 | u32 iir, u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 | 1636 | { |
c1874ed7 ID |
1637 | int pipe; |
1638 | ||
58ead0d7 | 1639 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1640 | |
1641 | if (!dev_priv->display_irqs_enabled) { | |
1642 | spin_unlock(&dev_priv->irq_lock); | |
1643 | return; | |
1644 | } | |
1645 | ||
055e393f | 1646 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1647 | i915_reg_t reg; |
bbb5eebf | 1648 | u32 mask, iir_bit = 0; |
91d181dd | 1649 | |
bbb5eebf DV |
1650 | /* |
1651 | * PIPESTAT bits get signalled even when the interrupt is | |
1652 | * disabled with the mask bits, and some of the status bits do | |
1653 | * not generate interrupts at all (like the underrun bit). Hence | |
1654 | * we need to be careful that we only handle what we want to | |
1655 | * handle. | |
1656 | */ | |
0f239f4c DV |
1657 | |
1658 | /* fifo underruns are filterered in the underrun handler. */ | |
1659 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1660 | |
1661 | switch (pipe) { | |
1662 | case PIPE_A: | |
1663 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1664 | break; | |
1665 | case PIPE_B: | |
1666 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1667 | break; | |
3278f67f VS |
1668 | case PIPE_C: |
1669 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1670 | break; | |
bbb5eebf DV |
1671 | } |
1672 | if (iir & iir_bit) | |
1673 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1674 | ||
1675 | if (!mask) | |
91d181dd ID |
1676 | continue; |
1677 | ||
1678 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1679 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1680 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1681 | |
1682 | /* | |
1683 | * Clear the PIPE*STAT regs before the IIR | |
1684 | */ | |
91d181dd ID |
1685 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1686 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1687 | I915_WRITE(reg, pipe_stats[pipe]); |
1688 | } | |
58ead0d7 | 1689 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1690 | } |
1691 | ||
91d14251 | 1692 | static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, |
2ecb8ca4 VS |
1693 | u32 pipe_stats[I915_MAX_PIPES]) |
1694 | { | |
2ecb8ca4 | 1695 | enum pipe pipe; |
c1874ed7 | 1696 | |
055e393f | 1697 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
1698 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1699 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
1700 | intel_check_page_flip(dev_priv, pipe); | |
c1874ed7 | 1701 | |
5251f04e | 1702 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) |
51cbaf01 | 1703 | intel_finish_page_flip_cs(dev_priv, pipe); |
c1874ed7 ID |
1704 | |
1705 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 1706 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c1874ed7 | 1707 | |
1f7247c0 DV |
1708 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1709 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1710 | } |
1711 | ||
1712 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
91d14251 | 1713 | gmbus_irq_handler(dev_priv); |
c1874ed7 ID |
1714 | } |
1715 | ||
1ae3c34c | 1716 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1717 | { |
16c6c56b VS |
1718 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1719 | ||
1ae3c34c VS |
1720 | if (hotplug_status) |
1721 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1722 | |
1ae3c34c VS |
1723 | return hotplug_status; |
1724 | } | |
1725 | ||
91d14251 | 1726 | static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1ae3c34c VS |
1727 | u32 hotplug_status) |
1728 | { | |
1729 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1730 | |
91d14251 TU |
1731 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
1732 | IS_CHERRYVIEW(dev_priv)) { | |
0d2e4297 | 1733 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1734 | |
58f2cf24 VS |
1735 | if (hotplug_trigger) { |
1736 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1737 | hotplug_trigger, hpd_status_g4x, | |
1738 | i9xx_port_hotplug_long_detect); | |
1739 | ||
91d14251 | 1740 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1741 | } |
369712e8 JN |
1742 | |
1743 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
91d14251 | 1744 | dp_aux_irq_handler(dev_priv); |
0d2e4297 JN |
1745 | } else { |
1746 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1747 | |
58f2cf24 VS |
1748 | if (hotplug_trigger) { |
1749 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1750 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1751 | i9xx_port_hotplug_long_detect); |
91d14251 | 1752 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
58f2cf24 | 1753 | } |
3ff60f89 | 1754 | } |
16c6c56b VS |
1755 | } |
1756 | ||
ff1f525e | 1757 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1758 | { |
45a83f84 | 1759 | struct drm_device *dev = arg; |
2d1013dd | 1760 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 1761 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1762 | |
2dd2a883 ID |
1763 | if (!intel_irqs_enabled(dev_priv)) |
1764 | return IRQ_NONE; | |
1765 | ||
1f814dac ID |
1766 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1767 | disable_rpm_wakeref_asserts(dev_priv); | |
1768 | ||
1e1cace9 | 1769 | do { |
6e814800 | 1770 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1771 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1772 | u32 hotplug_status = 0; |
a5e485a9 | 1773 | u32 ier = 0; |
3ff60f89 | 1774 | |
7e231dbe JB |
1775 | gt_iir = I915_READ(GTIIR); |
1776 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1777 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1778 | |
1779 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1780 | break; |
7e231dbe JB |
1781 | |
1782 | ret = IRQ_HANDLED; | |
1783 | ||
a5e485a9 VS |
1784 | /* |
1785 | * Theory on interrupt generation, based on empirical evidence: | |
1786 | * | |
1787 | * x = ((VLV_IIR & VLV_IER) || | |
1788 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1789 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1790 | * | |
1791 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1792 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1793 | * guarantee the CPU interrupt will be raised again even if we | |
1794 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1795 | * bits this time around. | |
1796 | */ | |
4a0a0202 | 1797 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1798 | ier = I915_READ(VLV_IER); |
1799 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1800 | |
1801 | if (gt_iir) | |
1802 | I915_WRITE(GTIIR, gt_iir); | |
1803 | if (pm_iir) | |
1804 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1805 | ||
7ce4d1f2 | 1806 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1807 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1808 | |
3ff60f89 OM |
1809 | /* Call regardless, as some status bits might not be |
1810 | * signalled in iir */ | |
91d14251 | 1811 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
7ce4d1f2 VS |
1812 | |
1813 | /* | |
1814 | * VLV_IIR is single buffered, and reflects the level | |
1815 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1816 | */ | |
1817 | if (iir) | |
1818 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1819 | |
a5e485a9 | 1820 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1821 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1822 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1823 | |
52894874 | 1824 | if (gt_iir) |
261e40b8 | 1825 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1826 | if (pm_iir) |
1827 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1828 | ||
1ae3c34c | 1829 | if (hotplug_status) |
91d14251 | 1830 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1831 | |
91d14251 | 1832 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
1e1cace9 | 1833 | } while (0); |
7e231dbe | 1834 | |
1f814dac ID |
1835 | enable_rpm_wakeref_asserts(dev_priv); |
1836 | ||
7e231dbe JB |
1837 | return ret; |
1838 | } | |
1839 | ||
43f328d7 VS |
1840 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1841 | { | |
45a83f84 | 1842 | struct drm_device *dev = arg; |
43f328d7 | 1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
43f328d7 | 1844 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1845 | |
2dd2a883 ID |
1846 | if (!intel_irqs_enabled(dev_priv)) |
1847 | return IRQ_NONE; | |
1848 | ||
1f814dac ID |
1849 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1850 | disable_rpm_wakeref_asserts(dev_priv); | |
1851 | ||
579de73b | 1852 | do { |
6e814800 | 1853 | u32 master_ctl, iir; |
e30e251a | 1854 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1855 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1856 | u32 hotplug_status = 0; |
a5e485a9 VS |
1857 | u32 ier = 0; |
1858 | ||
8e5fd599 VS |
1859 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1860 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1861 | |
8e5fd599 VS |
1862 | if (master_ctl == 0 && iir == 0) |
1863 | break; | |
43f328d7 | 1864 | |
27b6c122 OM |
1865 | ret = IRQ_HANDLED; |
1866 | ||
a5e485a9 VS |
1867 | /* |
1868 | * Theory on interrupt generation, based on empirical evidence: | |
1869 | * | |
1870 | * x = ((VLV_IIR & VLV_IER) || | |
1871 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
1872 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
1873 | * | |
1874 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1875 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
1876 | * guarantee the CPU interrupt will be raised again even if we | |
1877 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
1878 | * bits this time around. | |
1879 | */ | |
8e5fd599 | 1880 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
1881 | ier = I915_READ(VLV_IER); |
1882 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 1883 | |
e30e251a | 1884 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 1885 | |
7ce4d1f2 | 1886 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1887 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1888 | |
27b6c122 OM |
1889 | /* Call regardless, as some status bits might not be |
1890 | * signalled in iir */ | |
91d14251 | 1891 | valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); |
43f328d7 | 1892 | |
7ce4d1f2 VS |
1893 | /* |
1894 | * VLV_IIR is single buffered, and reflects the level | |
1895 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1896 | */ | |
1897 | if (iir) | |
1898 | I915_WRITE(VLV_IIR, iir); | |
1899 | ||
a5e485a9 | 1900 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 1901 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 1902 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 1903 | |
e30e251a VS |
1904 | gen8_gt_irq_handler(dev_priv, gt_iir); |
1905 | ||
1ae3c34c | 1906 | if (hotplug_status) |
91d14251 | 1907 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
2ecb8ca4 | 1908 | |
91d14251 | 1909 | valleyview_pipestat_irq_handler(dev_priv, pipe_stats); |
579de73b | 1910 | } while (0); |
3278f67f | 1911 | |
1f814dac ID |
1912 | enable_rpm_wakeref_asserts(dev_priv); |
1913 | ||
43f328d7 VS |
1914 | return ret; |
1915 | } | |
1916 | ||
91d14251 TU |
1917 | static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, |
1918 | u32 hotplug_trigger, | |
40e56410 VS |
1919 | const u32 hpd[HPD_NUM_PINS]) |
1920 | { | |
40e56410 VS |
1921 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
1922 | ||
6a39d7c9 JN |
1923 | /* |
1924 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
1925 | * unless we touch the hotplug register, even if hotplug_trigger is | |
1926 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
1927 | * errors. | |
1928 | */ | |
40e56410 | 1929 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
1930 | if (!hotplug_trigger) { |
1931 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
1932 | PORTD_HOTPLUG_STATUS_MASK | | |
1933 | PORTC_HOTPLUG_STATUS_MASK | | |
1934 | PORTB_HOTPLUG_STATUS_MASK; | |
1935 | dig_hotplug_reg &= ~mask; | |
1936 | } | |
1937 | ||
40e56410 | 1938 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
1939 | if (!hotplug_trigger) |
1940 | return; | |
40e56410 VS |
1941 | |
1942 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1943 | dig_hotplug_reg, hpd, | |
1944 | pch_port_hotplug_long_detect); | |
1945 | ||
91d14251 | 1946 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
1947 | } |
1948 | ||
91d14251 | 1949 | static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
776ad806 | 1950 | { |
9db4a9c7 | 1951 | int pipe; |
b543fb04 | 1952 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1953 | |
91d14251 | 1954 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx); |
91d131d2 | 1955 | |
cfc33bf7 VS |
1956 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1957 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1958 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1959 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1960 | port_name(port)); |
1961 | } | |
776ad806 | 1962 | |
ce99c256 | 1963 | if (pch_iir & SDE_AUX_MASK) |
91d14251 | 1964 | dp_aux_irq_handler(dev_priv); |
ce99c256 | 1965 | |
776ad806 | 1966 | if (pch_iir & SDE_GMBUS) |
91d14251 | 1967 | gmbus_irq_handler(dev_priv); |
776ad806 JB |
1968 | |
1969 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1970 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1971 | ||
1972 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1973 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1974 | ||
1975 | if (pch_iir & SDE_POISON) | |
1976 | DRM_ERROR("PCH poison interrupt\n"); | |
1977 | ||
9db4a9c7 | 1978 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1979 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1980 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1981 | pipe_name(pipe), | |
1982 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1983 | |
1984 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1985 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1986 | ||
1987 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1988 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1989 | ||
776ad806 | 1990 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1991 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1992 | |
1993 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1994 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1995 | } |
1996 | ||
91d14251 | 1997 | static void ivb_err_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 1998 | { |
8664281b | 1999 | u32 err_int = I915_READ(GEN7_ERR_INT); |
5a69b89f | 2000 | enum pipe pipe; |
8664281b | 2001 | |
de032bf4 PZ |
2002 | if (err_int & ERR_INT_POISON) |
2003 | DRM_ERROR("Poison interrupt\n"); | |
2004 | ||
055e393f | 2005 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2006 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2007 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2008 | |
5a69b89f | 2009 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
91d14251 TU |
2010 | if (IS_IVYBRIDGE(dev_priv)) |
2011 | ivb_pipe_crc_irq_handler(dev_priv, pipe); | |
5a69b89f | 2012 | else |
91d14251 | 2013 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
5a69b89f DV |
2014 | } |
2015 | } | |
8bf1e9f1 | 2016 | |
8664281b PZ |
2017 | I915_WRITE(GEN7_ERR_INT, err_int); |
2018 | } | |
2019 | ||
91d14251 | 2020 | static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) |
8664281b | 2021 | { |
8664281b PZ |
2022 | u32 serr_int = I915_READ(SERR_INT); |
2023 | ||
de032bf4 PZ |
2024 | if (serr_int & SERR_INT_POISON) |
2025 | DRM_ERROR("PCH poison interrupt\n"); | |
2026 | ||
8664281b | 2027 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2028 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2029 | |
2030 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2031 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2032 | |
2033 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2034 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2035 | |
2036 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2037 | } |
2038 | ||
91d14251 | 2039 | static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
23e81d69 | 2040 | { |
23e81d69 | 2041 | int pipe; |
6dbf30ce | 2042 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2043 | |
91d14251 | 2044 | ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt); |
91d131d2 | 2045 | |
cfc33bf7 VS |
2046 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2047 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2048 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2049 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2050 | port_name(port)); | |
2051 | } | |
23e81d69 AJ |
2052 | |
2053 | if (pch_iir & SDE_AUX_MASK_CPT) | |
91d14251 | 2054 | dp_aux_irq_handler(dev_priv); |
23e81d69 AJ |
2055 | |
2056 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2057 | gmbus_irq_handler(dev_priv); |
23e81d69 AJ |
2058 | |
2059 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2060 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2061 | ||
2062 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2063 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2064 | ||
2065 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2066 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2067 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2068 | pipe_name(pipe), | |
2069 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2070 | |
2071 | if (pch_iir & SDE_ERROR_CPT) | |
91d14251 | 2072 | cpt_serr_int_handler(dev_priv); |
23e81d69 AJ |
2073 | } |
2074 | ||
91d14251 | 2075 | static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) |
6dbf30ce | 2076 | { |
6dbf30ce VS |
2077 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & |
2078 | ~SDE_PORTE_HOTPLUG_SPT; | |
2079 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2080 | u32 pin_mask = 0, long_mask = 0; | |
2081 | ||
2082 | if (hotplug_trigger) { | |
2083 | u32 dig_hotplug_reg; | |
2084 | ||
2085 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2086 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2087 | ||
2088 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2089 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2090 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2091 | } |
2092 | ||
2093 | if (hotplug2_trigger) { | |
2094 | u32 dig_hotplug_reg; | |
2095 | ||
2096 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2097 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2098 | ||
2099 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2100 | dig_hotplug_reg, hpd_spt, | |
2101 | spt_port_hotplug2_long_detect); | |
2102 | } | |
2103 | ||
2104 | if (pin_mask) | |
91d14251 | 2105 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
6dbf30ce VS |
2106 | |
2107 | if (pch_iir & SDE_GMBUS_CPT) | |
91d14251 | 2108 | gmbus_irq_handler(dev_priv); |
6dbf30ce VS |
2109 | } |
2110 | ||
91d14251 TU |
2111 | static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2112 | u32 hotplug_trigger, | |
40e56410 VS |
2113 | const u32 hpd[HPD_NUM_PINS]) |
2114 | { | |
40e56410 VS |
2115 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
2116 | ||
2117 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2118 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2119 | ||
2120 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2121 | dig_hotplug_reg, hpd, | |
2122 | ilk_port_hotplug_long_detect); | |
2123 | ||
91d14251 | 2124 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
40e56410 VS |
2125 | } |
2126 | ||
91d14251 TU |
2127 | static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, |
2128 | u32 de_iir) | |
c008bc6e | 2129 | { |
40da17c2 | 2130 | enum pipe pipe; |
e4ce95aa VS |
2131 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2132 | ||
40e56410 | 2133 | if (hotplug_trigger) |
91d14251 | 2134 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); |
c008bc6e PZ |
2135 | |
2136 | if (de_iir & DE_AUX_CHANNEL_A) | |
91d14251 | 2137 | dp_aux_irq_handler(dev_priv); |
c008bc6e PZ |
2138 | |
2139 | if (de_iir & DE_GSE) | |
91d14251 | 2140 | intel_opregion_asle_intr(dev_priv); |
c008bc6e | 2141 | |
c008bc6e PZ |
2142 | if (de_iir & DE_POISON) |
2143 | DRM_ERROR("Poison interrupt\n"); | |
2144 | ||
055e393f | 2145 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2146 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2147 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2148 | intel_check_page_flip(dev_priv, pipe); | |
5b3a856b | 2149 | |
40da17c2 | 2150 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2151 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2152 | |
40da17c2 | 2153 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
91d14251 | 2154 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
c008bc6e | 2155 | |
40da17c2 | 2156 | /* plane/pipes map 1:1 on ilk+ */ |
5251f04e | 2157 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) |
51cbaf01 | 2158 | intel_finish_page_flip_cs(dev_priv, pipe); |
c008bc6e PZ |
2159 | } |
2160 | ||
2161 | /* check event from PCH */ | |
2162 | if (de_iir & DE_PCH_EVENT) { | |
2163 | u32 pch_iir = I915_READ(SDEIIR); | |
2164 | ||
91d14251 TU |
2165 | if (HAS_PCH_CPT(dev_priv)) |
2166 | cpt_irq_handler(dev_priv, pch_iir); | |
c008bc6e | 2167 | else |
91d14251 | 2168 | ibx_irq_handler(dev_priv, pch_iir); |
c008bc6e PZ |
2169 | |
2170 | /* should clear PCH hotplug event before clear CPU irq */ | |
2171 | I915_WRITE(SDEIIR, pch_iir); | |
2172 | } | |
2173 | ||
91d14251 TU |
2174 | if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) |
2175 | ironlake_rps_change_irq_handler(dev_priv); | |
c008bc6e PZ |
2176 | } |
2177 | ||
91d14251 TU |
2178 | static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, |
2179 | u32 de_iir) | |
9719fb98 | 2180 | { |
07d27e20 | 2181 | enum pipe pipe; |
23bb4cb5 VS |
2182 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2183 | ||
40e56410 | 2184 | if (hotplug_trigger) |
91d14251 | 2185 | ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); |
9719fb98 PZ |
2186 | |
2187 | if (de_iir & DE_ERR_INT_IVB) | |
91d14251 | 2188 | ivb_err_int_handler(dev_priv); |
9719fb98 PZ |
2189 | |
2190 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
91d14251 | 2191 | dp_aux_irq_handler(dev_priv); |
9719fb98 PZ |
2192 | |
2193 | if (de_iir & DE_GSE_IVB) | |
91d14251 | 2194 | intel_opregion_asle_intr(dev_priv); |
9719fb98 | 2195 | |
055e393f | 2196 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
2197 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2198 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2199 | intel_check_page_flip(dev_priv, pipe); | |
40da17c2 DV |
2200 | |
2201 | /* plane/pipes map 1:1 on ilk+ */ | |
5251f04e | 2202 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) |
51cbaf01 | 2203 | intel_finish_page_flip_cs(dev_priv, pipe); |
9719fb98 PZ |
2204 | } |
2205 | ||
2206 | /* check event from PCH */ | |
91d14251 | 2207 | if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { |
9719fb98 PZ |
2208 | u32 pch_iir = I915_READ(SDEIIR); |
2209 | ||
91d14251 | 2210 | cpt_irq_handler(dev_priv, pch_iir); |
9719fb98 PZ |
2211 | |
2212 | /* clear PCH hotplug event before clear CPU irq */ | |
2213 | I915_WRITE(SDEIIR, pch_iir); | |
2214 | } | |
2215 | } | |
2216 | ||
72c90f62 OM |
2217 | /* |
2218 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2219 | * 1 - Disable Master Interrupt Control. | |
2220 | * 2 - Find the source(s) of the interrupt. | |
2221 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2222 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2223 | * 5 - Re-enable Master Interrupt Control. | |
2224 | */ | |
f1af8fc1 | 2225 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2226 | { |
45a83f84 | 2227 | struct drm_device *dev = arg; |
2d1013dd | 2228 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2229 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2230 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2231 | |
2dd2a883 ID |
2232 | if (!intel_irqs_enabled(dev_priv)) |
2233 | return IRQ_NONE; | |
2234 | ||
1f814dac ID |
2235 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2236 | disable_rpm_wakeref_asserts(dev_priv); | |
2237 | ||
b1f14ad0 JB |
2238 | /* disable master interrupt before clearing iir */ |
2239 | de_ier = I915_READ(DEIER); | |
2240 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2241 | POSTING_READ(DEIER); |
b1f14ad0 | 2242 | |
44498aea PZ |
2243 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2244 | * interrupts will will be stored on its back queue, and then we'll be | |
2245 | * able to process them after we restore SDEIER (as soon as we restore | |
2246 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2247 | * due to its back queue). */ | |
91d14251 | 2248 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2249 | sde_ier = I915_READ(SDEIER); |
2250 | I915_WRITE(SDEIER, 0); | |
2251 | POSTING_READ(SDEIER); | |
2252 | } | |
44498aea | 2253 | |
72c90f62 OM |
2254 | /* Find, clear, then process each source of interrupt */ |
2255 | ||
b1f14ad0 | 2256 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2257 | if (gt_iir) { |
72c90f62 OM |
2258 | I915_WRITE(GTIIR, gt_iir); |
2259 | ret = IRQ_HANDLED; | |
91d14251 | 2260 | if (INTEL_GEN(dev_priv) >= 6) |
261e40b8 | 2261 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2262 | else |
261e40b8 | 2263 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2264 | } |
2265 | ||
0e43406b CW |
2266 | de_iir = I915_READ(DEIIR); |
2267 | if (de_iir) { | |
72c90f62 OM |
2268 | I915_WRITE(DEIIR, de_iir); |
2269 | ret = IRQ_HANDLED; | |
91d14251 TU |
2270 | if (INTEL_GEN(dev_priv) >= 7) |
2271 | ivb_display_irq_handler(dev_priv, de_iir); | |
f1af8fc1 | 2272 | else |
91d14251 | 2273 | ilk_display_irq_handler(dev_priv, de_iir); |
b1f14ad0 JB |
2274 | } |
2275 | ||
91d14251 | 2276 | if (INTEL_GEN(dev_priv) >= 6) { |
f1af8fc1 PZ |
2277 | u32 pm_iir = I915_READ(GEN6_PMIIR); |
2278 | if (pm_iir) { | |
f1af8fc1 PZ |
2279 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2280 | ret = IRQ_HANDLED; | |
72c90f62 | 2281 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2282 | } |
0e43406b | 2283 | } |
b1f14ad0 | 2284 | |
b1f14ad0 JB |
2285 | I915_WRITE(DEIER, de_ier); |
2286 | POSTING_READ(DEIER); | |
91d14251 | 2287 | if (!HAS_PCH_NOP(dev_priv)) { |
ab5c608b BW |
2288 | I915_WRITE(SDEIER, sde_ier); |
2289 | POSTING_READ(SDEIER); | |
2290 | } | |
b1f14ad0 | 2291 | |
1f814dac ID |
2292 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2293 | enable_rpm_wakeref_asserts(dev_priv); | |
2294 | ||
b1f14ad0 JB |
2295 | return ret; |
2296 | } | |
2297 | ||
91d14251 TU |
2298 | static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2299 | u32 hotplug_trigger, | |
40e56410 | 2300 | const u32 hpd[HPD_NUM_PINS]) |
d04a492d | 2301 | { |
cebd87a0 | 2302 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; |
d04a492d | 2303 | |
a52bb15b VS |
2304 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2305 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2306 | |
cebd87a0 | 2307 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2308 | dig_hotplug_reg, hpd, |
cebd87a0 | 2309 | bxt_port_hotplug_long_detect); |
40e56410 | 2310 | |
91d14251 | 2311 | intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); |
d04a492d SS |
2312 | } |
2313 | ||
f11a0f46 TU |
2314 | static irqreturn_t |
2315 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2316 | { |
abd58f01 | 2317 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2318 | u32 iir; |
c42664cc | 2319 | enum pipe pipe; |
88e04703 | 2320 | |
abd58f01 | 2321 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2322 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2323 | if (iir) { | |
2324 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2325 | ret = IRQ_HANDLED; |
e32192e1 | 2326 | if (iir & GEN8_DE_MISC_GSE) |
91d14251 | 2327 | intel_opregion_asle_intr(dev_priv); |
38cc46d7 OM |
2328 | else |
2329 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2330 | } |
38cc46d7 OM |
2331 | else |
2332 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2333 | } |
2334 | ||
6d766f02 | 2335 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2336 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2337 | if (iir) { | |
2338 | u32 tmp_mask; | |
d04a492d | 2339 | bool found = false; |
cebd87a0 | 2340 | |
e32192e1 | 2341 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2342 | ret = IRQ_HANDLED; |
88e04703 | 2343 | |
e32192e1 TU |
2344 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2345 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2346 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2347 | GEN9_AUX_CHANNEL_C | | |
2348 | GEN9_AUX_CHANNEL_D; | |
2349 | ||
2350 | if (iir & tmp_mask) { | |
91d14251 | 2351 | dp_aux_irq_handler(dev_priv); |
d04a492d SS |
2352 | found = true; |
2353 | } | |
2354 | ||
e32192e1 TU |
2355 | if (IS_BROXTON(dev_priv)) { |
2356 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; | |
2357 | if (tmp_mask) { | |
91d14251 TU |
2358 | bxt_hpd_irq_handler(dev_priv, tmp_mask, |
2359 | hpd_bxt); | |
e32192e1 TU |
2360 | found = true; |
2361 | } | |
2362 | } else if (IS_BROADWELL(dev_priv)) { | |
2363 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2364 | if (tmp_mask) { | |
91d14251 TU |
2365 | ilk_hpd_irq_handler(dev_priv, |
2366 | tmp_mask, hpd_bdw); | |
e32192e1 TU |
2367 | found = true; |
2368 | } | |
d04a492d SS |
2369 | } |
2370 | ||
91d14251 TU |
2371 | if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { |
2372 | gmbus_irq_handler(dev_priv); | |
9e63743e SS |
2373 | found = true; |
2374 | } | |
2375 | ||
d04a492d | 2376 | if (!found) |
38cc46d7 | 2377 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2378 | } |
38cc46d7 OM |
2379 | else |
2380 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2381 | } |
2382 | ||
055e393f | 2383 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2384 | u32 flip_done, fault_errors; |
abd58f01 | 2385 | |
c42664cc DV |
2386 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2387 | continue; | |
abd58f01 | 2388 | |
e32192e1 TU |
2389 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2390 | if (!iir) { | |
2391 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2392 | continue; | |
2393 | } | |
770de83d | 2394 | |
e32192e1 TU |
2395 | ret = IRQ_HANDLED; |
2396 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2397 | |
5a21b665 DV |
2398 | if (iir & GEN8_PIPE_VBLANK && |
2399 | intel_pipe_handle_vblank(dev_priv, pipe)) | |
2400 | intel_check_page_flip(dev_priv, pipe); | |
770de83d | 2401 | |
e32192e1 TU |
2402 | flip_done = iir; |
2403 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2404 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2405 | else | |
2406 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2407 | |
5251f04e | 2408 | if (flip_done) |
51cbaf01 | 2409 | intel_finish_page_flip_cs(dev_priv, pipe); |
38cc46d7 | 2410 | |
e32192e1 | 2411 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
91d14251 | 2412 | hsw_pipe_crc_irq_handler(dev_priv, pipe); |
38cc46d7 | 2413 | |
e32192e1 TU |
2414 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2415 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2416 | |
e32192e1 TU |
2417 | fault_errors = iir; |
2418 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2419 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2420 | else | |
2421 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2422 | |
e32192e1 TU |
2423 | if (fault_errors) |
2424 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2425 | pipe_name(pipe), | |
2426 | fault_errors); | |
abd58f01 BW |
2427 | } |
2428 | ||
91d14251 | 2429 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && |
266ea3d9 | 2430 | master_ctl & GEN8_DE_PCH_IRQ) { |
92d03a80 DV |
2431 | /* |
2432 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2433 | * scheme also closed the SDE interrupt handling race we've seen | |
2434 | * on older pch-split platforms. But this needs testing. | |
2435 | */ | |
e32192e1 TU |
2436 | iir = I915_READ(SDEIIR); |
2437 | if (iir) { | |
2438 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2439 | ret = IRQ_HANDLED; |
6dbf30ce VS |
2440 | |
2441 | if (HAS_PCH_SPT(dev_priv)) | |
91d14251 | 2442 | spt_irq_handler(dev_priv, iir); |
6dbf30ce | 2443 | else |
91d14251 | 2444 | cpt_irq_handler(dev_priv, iir); |
2dfb0b81 JN |
2445 | } else { |
2446 | /* | |
2447 | * Like on previous PCH there seems to be something | |
2448 | * fishy going on with forwarding PCH interrupts. | |
2449 | */ | |
2450 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2451 | } | |
92d03a80 DV |
2452 | } |
2453 | ||
f11a0f46 TU |
2454 | return ret; |
2455 | } | |
2456 | ||
2457 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2458 | { | |
2459 | struct drm_device *dev = arg; | |
2460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2461 | u32 master_ctl; | |
e30e251a | 2462 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2463 | irqreturn_t ret; |
2464 | ||
2465 | if (!intel_irqs_enabled(dev_priv)) | |
2466 | return IRQ_NONE; | |
2467 | ||
2468 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2469 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2470 | if (!master_ctl) | |
2471 | return IRQ_NONE; | |
2472 | ||
2473 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2474 | ||
2475 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2476 | disable_rpm_wakeref_asserts(dev_priv); | |
2477 | ||
2478 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2479 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2480 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2481 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2482 | ||
cb0d205e CW |
2483 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2484 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2485 | |
1f814dac ID |
2486 | enable_rpm_wakeref_asserts(dev_priv); |
2487 | ||
abd58f01 BW |
2488 | return ret; |
2489 | } | |
2490 | ||
17e1df07 DV |
2491 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2492 | bool reset_completed) | |
2493 | { | |
e2f80391 | 2494 | struct intel_engine_cs *engine; |
17e1df07 DV |
2495 | |
2496 | /* | |
2497 | * Notify all waiters for GPU completion events that reset state has | |
2498 | * been changed, and that they need to restart their wait after | |
2499 | * checking for potential errors (and bail out to drop locks if there is | |
2500 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2501 | */ | |
2502 | ||
2503 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
b4ac5afc | 2504 | for_each_engine(engine, dev_priv) |
e2f80391 | 2505 | wake_up_all(&engine->irq_queue); |
17e1df07 DV |
2506 | |
2507 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2508 | wake_up_all(&dev_priv->pending_flip_queue); | |
2509 | ||
2510 | /* | |
2511 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2512 | * reset state is cleared. | |
2513 | */ | |
2514 | if (reset_completed) | |
2515 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2516 | } | |
2517 | ||
8a905236 | 2518 | /** |
b8d24a06 | 2519 | * i915_reset_and_wakeup - do process context error handling work |
468f9d29 | 2520 | * @dev: drm device |
8a905236 JB |
2521 | * |
2522 | * Fire an error uevent so userspace can see that a hang or error | |
2523 | * was detected. | |
2524 | */ | |
c033666a | 2525 | static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv) |
8a905236 | 2526 | { |
c033666a | 2527 | struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj; |
cce723ed BW |
2528 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2529 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2530 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2531 | int ret; |
8a905236 | 2532 | |
c033666a | 2533 | kobject_uevent_env(kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2534 | |
7db0ba24 DV |
2535 | /* |
2536 | * Note that there's only one work item which does gpu resets, so we | |
2537 | * need not worry about concurrent gpu resets potentially incrementing | |
2538 | * error->reset_counter twice. We only need to take care of another | |
2539 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2540 | * quick check for that is good enough: schedule_work ensures the | |
2541 | * correct ordering between hang detection and this work item, and since | |
2542 | * the reset in-progress bit is only ever set by code outside of this | |
2543 | * work we don't need to worry about any other races. | |
2544 | */ | |
d98c52cf | 2545 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
f803aa55 | 2546 | DRM_DEBUG_DRIVER("resetting chip\n"); |
c033666a | 2547 | kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event); |
1f83fee0 | 2548 | |
f454c694 ID |
2549 | /* |
2550 | * In most cases it's guaranteed that we get here with an RPM | |
2551 | * reference held, for example because there is a pending GPU | |
2552 | * request that won't finish until the reset is done. This | |
2553 | * isn't the case at least when we get here by doing a | |
2554 | * simulated reset via debugs, so get an RPM reference. | |
2555 | */ | |
2556 | intel_runtime_pm_get(dev_priv); | |
7514747d | 2557 | |
c033666a | 2558 | intel_prepare_reset(dev_priv); |
7514747d | 2559 | |
17e1df07 DV |
2560 | /* |
2561 | * All state reset _must_ be completed before we update the | |
2562 | * reset counter, for otherwise waiters might miss the reset | |
2563 | * pending state and not properly drop locks, resulting in | |
2564 | * deadlocks with the reset work. | |
2565 | */ | |
c033666a | 2566 | ret = i915_reset(dev_priv); |
f69061be | 2567 | |
c033666a | 2568 | intel_finish_reset(dev_priv); |
17e1df07 | 2569 | |
f454c694 ID |
2570 | intel_runtime_pm_put(dev_priv); |
2571 | ||
d98c52cf | 2572 | if (ret == 0) |
c033666a | 2573 | kobject_uevent_env(kobj, |
f69061be | 2574 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2575 | |
17e1df07 DV |
2576 | /* |
2577 | * Note: The wake_up also serves as a memory barrier so that | |
2578 | * waiters see the update value of the reset counter atomic_t. | |
2579 | */ | |
2580 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2581 | } |
8a905236 JB |
2582 | } |
2583 | ||
c033666a | 2584 | static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv) |
8a905236 | 2585 | { |
bd9854f9 | 2586 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2587 | u32 eir = I915_READ(EIR); |
050ee91f | 2588 | int pipe, i; |
8a905236 | 2589 | |
35aed2e6 CW |
2590 | if (!eir) |
2591 | return; | |
8a905236 | 2592 | |
a70491cc | 2593 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2594 | |
c033666a | 2595 | i915_get_extra_instdone(dev_priv, instdone); |
bd9854f9 | 2596 | |
c033666a | 2597 | if (IS_G4X(dev_priv)) { |
8a905236 JB |
2598 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { |
2599 | u32 ipeir = I915_READ(IPEIR_I965); | |
2600 | ||
a70491cc JP |
2601 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2602 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2603 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2604 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2605 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2606 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2607 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2608 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2609 | } |
2610 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2611 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2612 | pr_err("page table error\n"); |
2613 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2614 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2615 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2616 | } |
2617 | } | |
2618 | ||
c033666a | 2619 | if (!IS_GEN2(dev_priv)) { |
8a905236 JB |
2620 | if (eir & I915_ERROR_PAGE_TABLE) { |
2621 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2622 | pr_err("page table error\n"); |
2623 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2624 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2625 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2626 | } |
2627 | } | |
2628 | ||
2629 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2630 | pr_err("memory refresh error:\n"); |
055e393f | 2631 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2632 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2633 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2634 | /* pipestat has already been acked */ |
2635 | } | |
2636 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2637 | pr_err("instruction error\n"); |
2638 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2639 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2640 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
c033666a | 2641 | if (INTEL_GEN(dev_priv) < 4) { |
8a905236 JB |
2642 | u32 ipeir = I915_READ(IPEIR); |
2643 | ||
a70491cc JP |
2644 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2645 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2646 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2647 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2648 | POSTING_READ(IPEIR); |
8a905236 JB |
2649 | } else { |
2650 | u32 ipeir = I915_READ(IPEIR_I965); | |
2651 | ||
a70491cc JP |
2652 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2653 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2654 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2655 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2656 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2657 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2658 | } |
2659 | } | |
2660 | ||
2661 | I915_WRITE(EIR, eir); | |
3143a2bf | 2662 | POSTING_READ(EIR); |
8a905236 JB |
2663 | eir = I915_READ(EIR); |
2664 | if (eir) { | |
2665 | /* | |
2666 | * some errors might have become stuck, | |
2667 | * mask them. | |
2668 | */ | |
2669 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2670 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2671 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2672 | } | |
35aed2e6 CW |
2673 | } |
2674 | ||
2675 | /** | |
b8d24a06 | 2676 | * i915_handle_error - handle a gpu error |
35aed2e6 | 2677 | * @dev: drm device |
14b730fc | 2678 | * @engine_mask: mask representing engines that are hung |
aafd8581 | 2679 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2680 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2681 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2682 | * so userspace knows something bad happened (should trigger collection | |
2683 | * of a ring dump etc.). | |
2684 | */ | |
c033666a CW |
2685 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2686 | u32 engine_mask, | |
58174462 | 2687 | const char *fmt, ...) |
35aed2e6 | 2688 | { |
58174462 MK |
2689 | va_list args; |
2690 | char error_msg[80]; | |
35aed2e6 | 2691 | |
58174462 MK |
2692 | va_start(args, fmt); |
2693 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2694 | va_end(args); | |
2695 | ||
c033666a CW |
2696 | i915_capture_error_state(dev_priv, engine_mask, error_msg); |
2697 | i915_report_and_clear_eir(dev_priv); | |
8a905236 | 2698 | |
14b730fc | 2699 | if (engine_mask) { |
805de8f4 | 2700 | atomic_or(I915_RESET_IN_PROGRESS_FLAG, |
f69061be | 2701 | &dev_priv->gpu_error.reset_counter); |
ba1234d1 | 2702 | |
11ed50ec | 2703 | /* |
b8d24a06 MK |
2704 | * Wakeup waiting processes so that the reset function |
2705 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2706 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2707 | * processes will see a reset in progress and back off, |
2708 | * releasing their locks and then wait for the reset completion. | |
2709 | * We must do this for _all_ gpu waiters that might hold locks | |
2710 | * that the reset work needs to acquire. | |
2711 | * | |
2712 | * Note: The wake_up serves as the required memory barrier to | |
2713 | * ensure that the waiters see the updated value of the reset | |
2714 | * counter atomic_t. | |
11ed50ec | 2715 | */ |
17e1df07 | 2716 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2717 | } |
2718 | ||
c033666a | 2719 | i915_reset_and_wakeup(dev_priv); |
8a905236 JB |
2720 | } |
2721 | ||
42f52ef8 KP |
2722 | /* Called from drm generic code, passed 'crtc' which |
2723 | * we use as a pipe index | |
2724 | */ | |
88e72717 | 2725 | static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2726 | { |
2d1013dd | 2727 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2728 | unsigned long irqflags; |
71e0ffa5 | 2729 | |
1ec14ad3 | 2730 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2731 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2732 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2733 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2734 | else |
7c463586 | 2735 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2736 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2737 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2738 | |
0a3e67a4 JB |
2739 | return 0; |
2740 | } | |
2741 | ||
88e72717 | 2742 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2743 | { |
2d1013dd | 2744 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2745 | unsigned long irqflags; |
b518421f | 2746 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2747 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2748 | |
f796cf8f | 2749 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
fbdedaea | 2750 | ilk_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2751 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2752 | ||
2753 | return 0; | |
2754 | } | |
2755 | ||
88e72717 | 2756 | static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2757 | { |
2d1013dd | 2758 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2759 | unsigned long irqflags; |
7e231dbe | 2760 | |
7e231dbe | 2761 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2762 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2763 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2764 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2765 | ||
2766 | return 0; | |
2767 | } | |
2768 | ||
88e72717 | 2769 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2770 | { |
2771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2772 | unsigned long irqflags; | |
abd58f01 | 2773 | |
abd58f01 | 2774 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2775 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2776 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2777 | |
abd58f01 BW |
2778 | return 0; |
2779 | } | |
2780 | ||
42f52ef8 KP |
2781 | /* Called from drm generic code, passed 'crtc' which |
2782 | * we use as a pipe index | |
2783 | */ | |
88e72717 | 2784 | static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2785 | { |
2d1013dd | 2786 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2787 | unsigned long irqflags; |
0a3e67a4 | 2788 | |
1ec14ad3 | 2789 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2790 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2791 | PIPE_VBLANK_INTERRUPT_STATUS | |
2792 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2793 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2794 | } | |
2795 | ||
88e72717 | 2796 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2797 | { |
2d1013dd | 2798 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2799 | unsigned long irqflags; |
b518421f | 2800 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2801 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2802 | |
2803 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
fbdedaea | 2804 | ilk_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2805 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2806 | } | |
2807 | ||
88e72717 | 2808 | static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2809 | { |
2d1013dd | 2810 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2811 | unsigned long irqflags; |
7e231dbe JB |
2812 | |
2813 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2814 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2815 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2816 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2817 | } | |
2818 | ||
88e72717 | 2819 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2820 | { |
2821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2822 | unsigned long irqflags; | |
abd58f01 | 2823 | |
abd58f01 | 2824 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2825 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2826 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2827 | } | |
2828 | ||
9107e9d2 | 2829 | static bool |
0bc40be8 | 2830 | ring_idle(struct intel_engine_cs *engine, u32 seqno) |
9107e9d2 | 2831 | { |
cffa781e CW |
2832 | return i915_seqno_passed(seqno, |
2833 | READ_ONCE(engine->last_submitted_seqno)); | |
f65d9421 BG |
2834 | } |
2835 | ||
a028c4b0 | 2836 | static bool |
c033666a | 2837 | ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr) |
a028c4b0 | 2838 | { |
c033666a | 2839 | if (INTEL_GEN(dev_priv) >= 8) { |
a6cdb93a | 2840 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2841 | } else { |
2842 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2843 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2844 | MI_SEMAPHORE_REGISTER); | |
2845 | } | |
2846 | } | |
2847 | ||
a4872ba6 | 2848 | static struct intel_engine_cs * |
0bc40be8 TU |
2849 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, |
2850 | u64 offset) | |
921d42ea | 2851 | { |
c033666a | 2852 | struct drm_i915_private *dev_priv = engine->i915; |
a4872ba6 | 2853 | struct intel_engine_cs *signaller; |
921d42ea | 2854 | |
c033666a | 2855 | if (INTEL_GEN(dev_priv) >= 8) { |
b4ac5afc | 2856 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2857 | if (engine == signaller) |
a6cdb93a RV |
2858 | continue; |
2859 | ||
0bc40be8 | 2860 | if (offset == signaller->semaphore.signal_ggtt[engine->id]) |
a6cdb93a RV |
2861 | return signaller; |
2862 | } | |
921d42ea DV |
2863 | } else { |
2864 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2865 | ||
b4ac5afc | 2866 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2867 | if(engine == signaller) |
921d42ea DV |
2868 | continue; |
2869 | ||
0bc40be8 | 2870 | if (sync_bits == signaller->semaphore.mbox.wait[engine->id]) |
921d42ea DV |
2871 | return signaller; |
2872 | } | |
2873 | } | |
2874 | ||
a6cdb93a | 2875 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
0bc40be8 | 2876 | engine->id, ipehr, offset); |
921d42ea DV |
2877 | |
2878 | return NULL; | |
2879 | } | |
2880 | ||
a4872ba6 | 2881 | static struct intel_engine_cs * |
0bc40be8 | 2882 | semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) |
a24a11e6 | 2883 | { |
c033666a | 2884 | struct drm_i915_private *dev_priv = engine->i915; |
88fe429d | 2885 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2886 | u64 offset = 0; |
2887 | int i, backwards; | |
a24a11e6 | 2888 | |
381e8ae3 TE |
2889 | /* |
2890 | * This function does not support execlist mode - any attempt to | |
2891 | * proceed further into this function will result in a kernel panic | |
2892 | * when dereferencing ring->buffer, which is not set up in execlist | |
2893 | * mode. | |
2894 | * | |
2895 | * The correct way of doing it would be to derive the currently | |
2896 | * executing ring buffer from the current context, which is derived | |
2897 | * from the currently running request. Unfortunately, to get the | |
2898 | * current request we would have to grab the struct_mutex before doing | |
2899 | * anything else, which would be ill-advised since some other thread | |
2900 | * might have grabbed it already and managed to hang itself, causing | |
2901 | * the hang checker to deadlock. | |
2902 | * | |
2903 | * Therefore, this function does not support execlist mode in its | |
2904 | * current form. Just return NULL and move on. | |
2905 | */ | |
0bc40be8 | 2906 | if (engine->buffer == NULL) |
381e8ae3 TE |
2907 | return NULL; |
2908 | ||
0bc40be8 | 2909 | ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); |
c033666a | 2910 | if (!ipehr_is_semaphore_wait(engine->i915, ipehr)) |
6274f212 | 2911 | return NULL; |
a24a11e6 | 2912 | |
88fe429d DV |
2913 | /* |
2914 | * HEAD is likely pointing to the dword after the actual command, | |
2915 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2916 | * or 4 dwords depending on the semaphore wait command size. |
2917 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2918 | * point at at batch, and semaphores are always emitted into the |
2919 | * ringbuffer itself. | |
a24a11e6 | 2920 | */ |
0bc40be8 | 2921 | head = I915_READ_HEAD(engine) & HEAD_ADDR; |
c033666a | 2922 | backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4; |
88fe429d | 2923 | |
a6cdb93a | 2924 | for (i = backwards; i; --i) { |
88fe429d DV |
2925 | /* |
2926 | * Be paranoid and presume the hw has gone off into the wild - | |
2927 | * our ring is smaller than what the hardware (and hence | |
2928 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2929 | */ | |
0bc40be8 | 2930 | head &= engine->buffer->size - 1; |
88fe429d DV |
2931 | |
2932 | /* This here seems to blow up */ | |
0bc40be8 | 2933 | cmd = ioread32(engine->buffer->virtual_start + head); |
a24a11e6 CW |
2934 | if (cmd == ipehr) |
2935 | break; | |
2936 | ||
88fe429d DV |
2937 | head -= 4; |
2938 | } | |
a24a11e6 | 2939 | |
88fe429d DV |
2940 | if (!i) |
2941 | return NULL; | |
a24a11e6 | 2942 | |
0bc40be8 | 2943 | *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1; |
c033666a | 2944 | if (INTEL_GEN(dev_priv) >= 8) { |
0bc40be8 | 2945 | offset = ioread32(engine->buffer->virtual_start + head + 12); |
a6cdb93a | 2946 | offset <<= 32; |
0bc40be8 | 2947 | offset = ioread32(engine->buffer->virtual_start + head + 8); |
a6cdb93a | 2948 | } |
0bc40be8 | 2949 | return semaphore_wait_to_signaller_ring(engine, ipehr, offset); |
a24a11e6 CW |
2950 | } |
2951 | ||
0bc40be8 | 2952 | static int semaphore_passed(struct intel_engine_cs *engine) |
6274f212 | 2953 | { |
c033666a | 2954 | struct drm_i915_private *dev_priv = engine->i915; |
a4872ba6 | 2955 | struct intel_engine_cs *signaller; |
a0d036b0 | 2956 | u32 seqno; |
6274f212 | 2957 | |
0bc40be8 | 2958 | engine->hangcheck.deadlock++; |
6274f212 | 2959 | |
0bc40be8 | 2960 | signaller = semaphore_waits_for(engine, &seqno); |
4be17381 CW |
2961 | if (signaller == NULL) |
2962 | return -1; | |
2963 | ||
2964 | /* Prevent pathological recursion due to driver bugs */ | |
666796da | 2965 | if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) |
6274f212 CW |
2966 | return -1; |
2967 | ||
c04e0f3b | 2968 | if (i915_seqno_passed(signaller->get_seqno(signaller), seqno)) |
4be17381 CW |
2969 | return 1; |
2970 | ||
a0d036b0 CW |
2971 | /* cursory check for an unkickable deadlock */ |
2972 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2973 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2974 | return -1; |
2975 | ||
2976 | return 0; | |
6274f212 CW |
2977 | } |
2978 | ||
2979 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2980 | { | |
e2f80391 | 2981 | struct intel_engine_cs *engine; |
6274f212 | 2982 | |
b4ac5afc | 2983 | for_each_engine(engine, dev_priv) |
e2f80391 | 2984 | engine->hangcheck.deadlock = 0; |
6274f212 CW |
2985 | } |
2986 | ||
0bc40be8 | 2987 | static bool subunits_stuck(struct intel_engine_cs *engine) |
1ec14ad3 | 2988 | { |
61642ff0 MK |
2989 | u32 instdone[I915_NUM_INSTDONE_REG]; |
2990 | bool stuck; | |
2991 | int i; | |
2992 | ||
0bc40be8 | 2993 | if (engine->id != RCS) |
61642ff0 MK |
2994 | return true; |
2995 | ||
c033666a | 2996 | i915_get_extra_instdone(engine->i915, instdone); |
9107e9d2 | 2997 | |
61642ff0 MK |
2998 | /* There might be unstable subunit states even when |
2999 | * actual head is not moving. Filter out the unstable ones by | |
3000 | * accumulating the undone -> done transitions and only | |
3001 | * consider those as progress. | |
3002 | */ | |
3003 | stuck = true; | |
3004 | for (i = 0; i < I915_NUM_INSTDONE_REG; i++) { | |
0bc40be8 | 3005 | const u32 tmp = instdone[i] | engine->hangcheck.instdone[i]; |
61642ff0 | 3006 | |
0bc40be8 | 3007 | if (tmp != engine->hangcheck.instdone[i]) |
61642ff0 MK |
3008 | stuck = false; |
3009 | ||
0bc40be8 | 3010 | engine->hangcheck.instdone[i] |= tmp; |
61642ff0 MK |
3011 | } |
3012 | ||
3013 | return stuck; | |
3014 | } | |
3015 | ||
3016 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3017 | head_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3018 | { |
0bc40be8 | 3019 | if (acthd != engine->hangcheck.acthd) { |
61642ff0 MK |
3020 | |
3021 | /* Clear subunit states on head movement */ | |
0bc40be8 TU |
3022 | memset(engine->hangcheck.instdone, 0, |
3023 | sizeof(engine->hangcheck.instdone)); | |
61642ff0 | 3024 | |
24a65e62 | 3025 | return HANGCHECK_ACTIVE; |
f260fe7b | 3026 | } |
6274f212 | 3027 | |
0bc40be8 | 3028 | if (!subunits_stuck(engine)) |
61642ff0 MK |
3029 | return HANGCHECK_ACTIVE; |
3030 | ||
3031 | return HANGCHECK_HUNG; | |
3032 | } | |
3033 | ||
3034 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3035 | ring_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3036 | { |
c033666a | 3037 | struct drm_i915_private *dev_priv = engine->i915; |
61642ff0 MK |
3038 | enum intel_ring_hangcheck_action ha; |
3039 | u32 tmp; | |
3040 | ||
0bc40be8 | 3041 | ha = head_stuck(engine, acthd); |
61642ff0 MK |
3042 | if (ha != HANGCHECK_HUNG) |
3043 | return ha; | |
3044 | ||
c033666a | 3045 | if (IS_GEN2(dev_priv)) |
f2f4d82f | 3046 | return HANGCHECK_HUNG; |
9107e9d2 CW |
3047 | |
3048 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
3049 | * If so we can simply poke the RB_WAIT bit | |
3050 | * and break the hang. This should work on | |
3051 | * all but the second generation chipsets. | |
3052 | */ | |
0bc40be8 | 3053 | tmp = I915_READ_CTL(engine); |
1ec14ad3 | 3054 | if (tmp & RING_WAIT) { |
c033666a | 3055 | i915_handle_error(dev_priv, 0, |
58174462 | 3056 | "Kicking stuck wait on %s", |
0bc40be8 TU |
3057 | engine->name); |
3058 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3059 | return HANGCHECK_KICK; |
6274f212 CW |
3060 | } |
3061 | ||
c033666a | 3062 | if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) { |
0bc40be8 | 3063 | switch (semaphore_passed(engine)) { |
6274f212 | 3064 | default: |
f2f4d82f | 3065 | return HANGCHECK_HUNG; |
6274f212 | 3066 | case 1: |
c033666a | 3067 | i915_handle_error(dev_priv, 0, |
58174462 | 3068 | "Kicking stuck semaphore on %s", |
0bc40be8 TU |
3069 | engine->name); |
3070 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3071 | return HANGCHECK_KICK; |
6274f212 | 3072 | case 0: |
f2f4d82f | 3073 | return HANGCHECK_WAIT; |
6274f212 | 3074 | } |
9107e9d2 | 3075 | } |
ed5cbb03 | 3076 | |
f2f4d82f | 3077 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
3078 | } |
3079 | ||
12471ba8 CW |
3080 | static unsigned kick_waiters(struct intel_engine_cs *engine) |
3081 | { | |
c033666a | 3082 | struct drm_i915_private *i915 = engine->i915; |
12471ba8 CW |
3083 | unsigned user_interrupts = READ_ONCE(engine->user_interrupts); |
3084 | ||
3085 | if (engine->hangcheck.user_interrupts == user_interrupts && | |
3086 | !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) { | |
3087 | if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine))) | |
3088 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
3089 | engine->name); | |
3090 | else | |
3091 | DRM_INFO("Fake missed irq on %s\n", | |
3092 | engine->name); | |
3093 | wake_up_all(&engine->irq_queue); | |
3094 | } | |
3095 | ||
3096 | return user_interrupts; | |
3097 | } | |
737b1506 | 3098 | /* |
f65d9421 | 3099 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
3100 | * batchbuffers in a long time. We keep track per ring seqno progress and |
3101 | * if there are no progress, hangcheck score for that ring is increased. | |
3102 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
3103 | * we kick the ring. If we see no progress on three subsequent calls | |
3104 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 3105 | */ |
737b1506 | 3106 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 3107 | { |
737b1506 CW |
3108 | struct drm_i915_private *dev_priv = |
3109 | container_of(work, typeof(*dev_priv), | |
3110 | gpu_error.hangcheck_work.work); | |
e2f80391 | 3111 | struct intel_engine_cs *engine; |
c3232b18 | 3112 | enum intel_engine_id id; |
05407ff8 | 3113 | int busy_count = 0, rings_hung = 0; |
666796da | 3114 | bool stuck[I915_NUM_ENGINES] = { 0 }; |
9107e9d2 CW |
3115 | #define BUSY 1 |
3116 | #define KICK 5 | |
3117 | #define HUNG 20 | |
24a65e62 | 3118 | #define ACTIVE_DECAY 15 |
893eead0 | 3119 | |
d330a953 | 3120 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
3121 | return; |
3122 | ||
1f814dac ID |
3123 | /* |
3124 | * The hangcheck work is synced during runtime suspend, we don't | |
3125 | * require a wakeref. TODO: instead of disabling the asserts make | |
3126 | * sure that we hold a reference when this work is running. | |
3127 | */ | |
3128 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3129 | ||
75714940 MK |
3130 | /* As enabling the GPU requires fairly extensive mmio access, |
3131 | * periodically arm the mmio checker to see if we are triggering | |
3132 | * any invalid access. | |
3133 | */ | |
3134 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
3135 | ||
c3232b18 | 3136 | for_each_engine_id(engine, dev_priv, id) { |
50877445 CW |
3137 | u64 acthd; |
3138 | u32 seqno; | |
12471ba8 | 3139 | unsigned user_interrupts; |
9107e9d2 | 3140 | bool busy = true; |
05407ff8 | 3141 | |
6274f212 CW |
3142 | semaphore_clear_deadlocks(dev_priv); |
3143 | ||
c04e0f3b CW |
3144 | /* We don't strictly need an irq-barrier here, as we are not |
3145 | * serving an interrupt request, be paranoid in case the | |
3146 | * barrier has side-effects (such as preventing a broken | |
3147 | * cacheline snoop) and so be sure that we can see the seqno | |
3148 | * advance. If the seqno should stick, due to a stale | |
3149 | * cacheline, we would erroneously declare the GPU hung. | |
3150 | */ | |
3151 | if (engine->irq_seqno_barrier) | |
3152 | engine->irq_seqno_barrier(engine); | |
3153 | ||
e2f80391 | 3154 | acthd = intel_ring_get_active_head(engine); |
c04e0f3b | 3155 | seqno = engine->get_seqno(engine); |
b4519513 | 3156 | |
12471ba8 CW |
3157 | /* Reset stuck interrupts between batch advances */ |
3158 | user_interrupts = 0; | |
3159 | ||
e2f80391 TU |
3160 | if (engine->hangcheck.seqno == seqno) { |
3161 | if (ring_idle(engine, seqno)) { | |
3162 | engine->hangcheck.action = HANGCHECK_IDLE; | |
e2f80391 | 3163 | if (waitqueue_active(&engine->irq_queue)) { |
094f9a54 | 3164 | /* Safeguard against driver failure */ |
12471ba8 | 3165 | user_interrupts = kick_waiters(engine); |
e2f80391 | 3166 | engine->hangcheck.score += BUSY; |
9107e9d2 CW |
3167 | } else |
3168 | busy = false; | |
05407ff8 | 3169 | } else { |
6274f212 CW |
3170 | /* We always increment the hangcheck score |
3171 | * if the ring is busy and still processing | |
3172 | * the same request, so that no single request | |
3173 | * can run indefinitely (such as a chain of | |
3174 | * batches). The only time we do not increment | |
3175 | * the hangcheck score on this ring, if this | |
3176 | * ring is in a legitimate wait for another | |
3177 | * ring. In that case the waiting ring is a | |
3178 | * victim and we want to be sure we catch the | |
3179 | * right culprit. Then every time we do kick | |
3180 | * the ring, add a small increment to the | |
3181 | * score so that we can catch a batch that is | |
3182 | * being repeatedly kicked and so responsible | |
3183 | * for stalling the machine. | |
3184 | */ | |
e2f80391 TU |
3185 | engine->hangcheck.action = ring_stuck(engine, |
3186 | acthd); | |
ad8beaea | 3187 | |
e2f80391 | 3188 | switch (engine->hangcheck.action) { |
da661464 | 3189 | case HANGCHECK_IDLE: |
f2f4d82f | 3190 | case HANGCHECK_WAIT: |
f260fe7b | 3191 | break; |
24a65e62 | 3192 | case HANGCHECK_ACTIVE: |
e2f80391 | 3193 | engine->hangcheck.score += BUSY; |
6274f212 | 3194 | break; |
f2f4d82f | 3195 | case HANGCHECK_KICK: |
e2f80391 | 3196 | engine->hangcheck.score += KICK; |
6274f212 | 3197 | break; |
f2f4d82f | 3198 | case HANGCHECK_HUNG: |
e2f80391 | 3199 | engine->hangcheck.score += HUNG; |
c3232b18 | 3200 | stuck[id] = true; |
6274f212 CW |
3201 | break; |
3202 | } | |
05407ff8 | 3203 | } |
9107e9d2 | 3204 | } else { |
e2f80391 | 3205 | engine->hangcheck.action = HANGCHECK_ACTIVE; |
da661464 | 3206 | |
9107e9d2 CW |
3207 | /* Gradually reduce the count so that we catch DoS |
3208 | * attempts across multiple batches. | |
3209 | */ | |
e2f80391 TU |
3210 | if (engine->hangcheck.score > 0) |
3211 | engine->hangcheck.score -= ACTIVE_DECAY; | |
3212 | if (engine->hangcheck.score < 0) | |
3213 | engine->hangcheck.score = 0; | |
f260fe7b | 3214 | |
61642ff0 | 3215 | /* Clear head and subunit states on seqno movement */ |
12471ba8 | 3216 | acthd = 0; |
61642ff0 | 3217 | |
e2f80391 TU |
3218 | memset(engine->hangcheck.instdone, 0, |
3219 | sizeof(engine->hangcheck.instdone)); | |
d1e61e7f CW |
3220 | } |
3221 | ||
e2f80391 TU |
3222 | engine->hangcheck.seqno = seqno; |
3223 | engine->hangcheck.acthd = acthd; | |
12471ba8 | 3224 | engine->hangcheck.user_interrupts = user_interrupts; |
9107e9d2 | 3225 | busy_count += busy; |
893eead0 | 3226 | } |
b9201c14 | 3227 | |
c3232b18 | 3228 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 3229 | if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d | 3230 | DRM_INFO("%s on %s\n", |
c3232b18 | 3231 | stuck[id] ? "stuck" : "no progress", |
e2f80391 | 3232 | engine->name); |
14b730fc | 3233 | rings_hung |= intel_engine_flag(engine); |
92cab734 MK |
3234 | } |
3235 | } | |
3236 | ||
1f814dac | 3237 | if (rings_hung) { |
c033666a | 3238 | i915_handle_error(dev_priv, rings_hung, "Engine(s) hung"); |
1f814dac ID |
3239 | goto out; |
3240 | } | |
f65d9421 | 3241 | |
05407ff8 MK |
3242 | if (busy_count) |
3243 | /* Reset timer case chip hangs without another request | |
3244 | * being added */ | |
c033666a | 3245 | i915_queue_hangcheck(dev_priv); |
1f814dac ID |
3246 | |
3247 | out: | |
3248 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
10cd45b6 MK |
3249 | } |
3250 | ||
c033666a | 3251 | void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
10cd45b6 | 3252 | { |
c033666a | 3253 | struct i915_gpu_error *e = &dev_priv->gpu_error; |
672e7b7c | 3254 | |
d330a953 | 3255 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3256 | return; |
3257 | ||
737b1506 CW |
3258 | /* Don't continually defer the hangcheck so that it is always run at |
3259 | * least once after work has been scheduled on any ring. Otherwise, | |
3260 | * we will ignore a hung ring if a second ring is kept busy. | |
3261 | */ | |
3262 | ||
3263 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
3264 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3265 | } |
3266 | ||
1c69eb42 | 3267 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3268 | { |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3270 | ||
3271 | if (HAS_PCH_NOP(dev)) | |
3272 | return; | |
3273 | ||
f86f3fb0 | 3274 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3275 | |
3276 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3277 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3278 | } |
105b122e | 3279 | |
622364b6 PZ |
3280 | /* |
3281 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3282 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3283 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3284 | * only unmask them as needed with SDEIMR. | |
3285 | * | |
3286 | * This function needs to be called before interrupts are enabled. | |
3287 | */ | |
3288 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3289 | { | |
3290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3291 | ||
3292 | if (HAS_PCH_NOP(dev)) | |
3293 | return; | |
3294 | ||
3295 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3296 | I915_WRITE(SDEIER, 0xffffffff); |
3297 | POSTING_READ(SDEIER); | |
3298 | } | |
3299 | ||
7c4d664e | 3300 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3301 | { |
3302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3303 | ||
f86f3fb0 | 3304 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3305 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3306 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3307 | } |
3308 | ||
70591a41 VS |
3309 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3310 | { | |
3311 | enum pipe pipe; | |
3312 | ||
71b8b41d VS |
3313 | if (IS_CHERRYVIEW(dev_priv)) |
3314 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3315 | else | |
3316 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3317 | ||
ad22d106 | 3318 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
3319 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3320 | ||
ad22d106 VS |
3321 | for_each_pipe(dev_priv, pipe) { |
3322 | I915_WRITE(PIPESTAT(pipe), | |
3323 | PIPE_FIFO_UNDERRUN_STATUS | | |
3324 | PIPESTAT_INT_STATUS_MASK); | |
3325 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
3326 | } | |
70591a41 VS |
3327 | |
3328 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 3329 | dev_priv->irq_mask = ~0; |
70591a41 VS |
3330 | } |
3331 | ||
8bb61306 VS |
3332 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
3333 | { | |
3334 | u32 pipestat_mask; | |
9ab981f2 | 3335 | u32 enable_mask; |
8bb61306 VS |
3336 | enum pipe pipe; |
3337 | ||
8bb61306 VS |
3338 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
3339 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3340 | ||
3341 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
3342 | for_each_pipe(dev_priv, pipe) | |
3343 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
3344 | ||
9ab981f2 VS |
3345 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
3346 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3347 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
8bb61306 | 3348 | if (IS_CHERRYVIEW(dev_priv)) |
9ab981f2 | 3349 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
6b7eafc1 VS |
3350 | |
3351 | WARN_ON(dev_priv->irq_mask != ~0); | |
3352 | ||
9ab981f2 VS |
3353 | dev_priv->irq_mask = ~enable_mask; |
3354 | ||
3355 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
3356 | } |
3357 | ||
3358 | /* drm_dma.h hooks | |
3359 | */ | |
3360 | static void ironlake_irq_reset(struct drm_device *dev) | |
3361 | { | |
3362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3363 | ||
3364 | I915_WRITE(HWSTAM, 0xffffffff); | |
3365 | ||
3366 | GEN5_IRQ_RESET(DE); | |
3367 | if (IS_GEN7(dev)) | |
3368 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
3369 | ||
3370 | gen5_gt_irq_reset(dev); | |
3371 | ||
3372 | ibx_irq_reset(dev); | |
3373 | } | |
3374 | ||
7e231dbe JB |
3375 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3376 | { | |
2d1013dd | 3377 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3378 | |
34c7b8a7 VS |
3379 | I915_WRITE(VLV_MASTER_IER, 0); |
3380 | POSTING_READ(VLV_MASTER_IER); | |
3381 | ||
7c4d664e | 3382 | gen5_gt_irq_reset(dev); |
7e231dbe | 3383 | |
ad22d106 | 3384 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3385 | if (dev_priv->display_irqs_enabled) |
3386 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3387 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3388 | } |
3389 | ||
d6e3cca3 DV |
3390 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3391 | { | |
3392 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3393 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3394 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3395 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3396 | } | |
3397 | ||
823f6b38 | 3398 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3399 | { |
3400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3401 | int pipe; | |
3402 | ||
abd58f01 BW |
3403 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3404 | POSTING_READ(GEN8_MASTER_IRQ); | |
3405 | ||
d6e3cca3 | 3406 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3407 | |
055e393f | 3408 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3409 | if (intel_display_power_is_enabled(dev_priv, |
3410 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3411 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3412 | |
f86f3fb0 PZ |
3413 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3414 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3415 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3416 | |
266ea3d9 SS |
3417 | if (HAS_PCH_SPLIT(dev)) |
3418 | ibx_irq_reset(dev); | |
abd58f01 | 3419 | } |
09f2344d | 3420 | |
4c6c03be DL |
3421 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3422 | unsigned int pipe_mask) | |
d49bdb0e | 3423 | { |
1180e206 | 3424 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3425 | enum pipe pipe; |
d49bdb0e | 3426 | |
13321786 | 3427 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3428 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3429 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3430 | dev_priv->de_irq_mask[pipe], | |
3431 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3432 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3433 | } |
3434 | ||
aae8ba84 VS |
3435 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3436 | unsigned int pipe_mask) | |
3437 | { | |
6831f3e3 VS |
3438 | enum pipe pipe; |
3439 | ||
aae8ba84 | 3440 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3441 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3442 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3443 | spin_unlock_irq(&dev_priv->irq_lock); |
3444 | ||
3445 | /* make sure we're done processing display irqs */ | |
3446 | synchronize_irq(dev_priv->dev->irq); | |
3447 | } | |
3448 | ||
43f328d7 VS |
3449 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3450 | { | |
3451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3452 | |
3453 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3454 | POSTING_READ(GEN8_MASTER_IRQ); | |
3455 | ||
d6e3cca3 | 3456 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3457 | |
3458 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3459 | ||
ad22d106 | 3460 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3461 | if (dev_priv->display_irqs_enabled) |
3462 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3463 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3464 | } |
3465 | ||
91d14251 | 3466 | static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, |
87a02106 VS |
3467 | const u32 hpd[HPD_NUM_PINS]) |
3468 | { | |
87a02106 VS |
3469 | struct intel_encoder *encoder; |
3470 | u32 enabled_irqs = 0; | |
3471 | ||
91d14251 | 3472 | for_each_intel_encoder(dev_priv->dev, encoder) |
87a02106 VS |
3473 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) |
3474 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3475 | ||
3476 | return enabled_irqs; | |
3477 | } | |
3478 | ||
91d14251 | 3479 | static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) |
7fe0b973 | 3480 | { |
87a02106 | 3481 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf | 3482 | |
91d14251 | 3483 | if (HAS_PCH_IBX(dev_priv)) { |
fee884ed | 3484 | hotplug_irqs = SDE_HOTPLUG_MASK; |
91d14251 | 3485 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx); |
82a28bcf | 3486 | } else { |
fee884ed | 3487 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
91d14251 | 3488 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt); |
82a28bcf | 3489 | } |
7fe0b973 | 3490 | |
fee884ed | 3491 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3492 | |
3493 | /* | |
3494 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3495 | * duration to 2ms (which is the minimum in the Display Port spec). |
3496 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3497 | */ |
7fe0b973 KP |
3498 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3499 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3500 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3501 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3502 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3503 | /* |
3504 | * When CPU and PCH are on the same package, port A | |
3505 | * HPD must be enabled in both north and south. | |
3506 | */ | |
91d14251 | 3507 | if (HAS_PCH_LPT_LP(dev_priv)) |
0b2eb33e | 3508 | hotplug |= PORTA_HOTPLUG_ENABLE; |
7fe0b973 | 3509 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3510 | } |
26951caf | 3511 | |
91d14251 | 3512 | static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
6dbf30ce | 3513 | { |
6dbf30ce VS |
3514 | u32 hotplug_irqs, hotplug, enabled_irqs; |
3515 | ||
3516 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
91d14251 | 3517 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); |
6dbf30ce VS |
3518 | |
3519 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3520 | ||
3521 | /* Enable digital hotplug on the PCH */ | |
3522 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3523 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
74c0b395 | 3524 | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; |
6dbf30ce VS |
3525 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3526 | ||
3527 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3528 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3529 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3530 | } |
3531 | ||
91d14251 | 3532 | static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e4ce95aa | 3533 | { |
e4ce95aa VS |
3534 | u32 hotplug_irqs, hotplug, enabled_irqs; |
3535 | ||
91d14251 | 3536 | if (INTEL_GEN(dev_priv) >= 8) { |
3a3b3c7d | 3537 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; |
91d14251 | 3538 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); |
3a3b3c7d VS |
3539 | |
3540 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
91d14251 | 3541 | } else if (INTEL_GEN(dev_priv) >= 7) { |
23bb4cb5 | 3542 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
91d14251 | 3543 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); |
3a3b3c7d VS |
3544 | |
3545 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3546 | } else { |
3547 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
91d14251 | 3548 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk); |
e4ce95aa | 3549 | |
3a3b3c7d VS |
3550 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3551 | } | |
e4ce95aa VS |
3552 | |
3553 | /* | |
3554 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3555 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3556 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3557 | */ |
3558 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3559 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3560 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3561 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3562 | ||
91d14251 | 3563 | ibx_hpd_irq_setup(dev_priv); |
e4ce95aa VS |
3564 | } |
3565 | ||
91d14251 | 3566 | static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) |
e0a20ad7 | 3567 | { |
a52bb15b | 3568 | u32 hotplug_irqs, hotplug, enabled_irqs; |
e0a20ad7 | 3569 | |
91d14251 | 3570 | enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); |
a52bb15b | 3571 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; |
e0a20ad7 | 3572 | |
a52bb15b | 3573 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
e0a20ad7 | 3574 | |
a52bb15b VS |
3575 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3576 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | | |
3577 | PORTA_HOTPLUG_ENABLE; | |
d252bf68 SS |
3578 | |
3579 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3580 | hotplug, enabled_irqs); | |
3581 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3582 | ||
3583 | /* | |
3584 | * For BXT invert bit has to be set based on AOB design | |
3585 | * for HPD detection logic, update it based on VBT fields. | |
3586 | */ | |
3587 | ||
3588 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && | |
3589 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3590 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3591 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3592 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3593 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3594 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3595 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3596 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3597 | ||
a52bb15b | 3598 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3599 | } |
3600 | ||
d46da437 PZ |
3601 | static void ibx_irq_postinstall(struct drm_device *dev) |
3602 | { | |
2d1013dd | 3603 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3604 | u32 mask; |
e5868a31 | 3605 | |
692a04cf DV |
3606 | if (HAS_PCH_NOP(dev)) |
3607 | return; | |
3608 | ||
105b122e | 3609 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3610 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3611 | else |
5c673b60 | 3612 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3613 | |
b51a2842 | 3614 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3615 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3616 | } |
3617 | ||
0a9a8c91 DV |
3618 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3619 | { | |
3620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3621 | u32 pm_irqs, gt_irqs; | |
3622 | ||
3623 | pm_irqs = gt_irqs = 0; | |
3624 | ||
3625 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3626 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3627 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3628 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3629 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3630 | } |
3631 | ||
3632 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3633 | if (IS_GEN5(dev)) { | |
3634 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3635 | ILK_BSD_USER_INTERRUPT; | |
3636 | } else { | |
3637 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3638 | } | |
3639 | ||
35079899 | 3640 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3641 | |
3642 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3643 | /* |
3644 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3645 | * itself is enabled/disabled. | |
3646 | */ | |
0a9a8c91 DV |
3647 | if (HAS_VEBOX(dev)) |
3648 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3649 | ||
605cd25b | 3650 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3651 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3652 | } |
3653 | } | |
3654 | ||
f71d4af4 | 3655 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3656 | { |
2d1013dd | 3657 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3658 | u32 display_mask, extra_mask; |
3659 | ||
3660 | if (INTEL_INFO(dev)->gen >= 7) { | |
3661 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3662 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3663 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3664 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3665 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3666 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3667 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3668 | } else { |
3669 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3670 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3671 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3672 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3673 | DE_POISON); | |
e4ce95aa VS |
3674 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3675 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3676 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3677 | } |
036a4a7d | 3678 | |
1ec14ad3 | 3679 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3680 | |
0c841212 PZ |
3681 | I915_WRITE(HWSTAM, 0xeffe); |
3682 | ||
622364b6 PZ |
3683 | ibx_irq_pre_postinstall(dev); |
3684 | ||
35079899 | 3685 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3686 | |
0a9a8c91 | 3687 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3688 | |
d46da437 | 3689 | ibx_irq_postinstall(dev); |
7fe0b973 | 3690 | |
f97108d1 | 3691 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3692 | /* Enable PCU event interrupts |
3693 | * | |
3694 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3695 | * setup is guaranteed to run in single-threaded context. But we |
3696 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3697 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3698 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3699 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3700 | } |
3701 | ||
036a4a7d ZW |
3702 | return 0; |
3703 | } | |
3704 | ||
f8b79e58 ID |
3705 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3706 | { | |
3707 | assert_spin_locked(&dev_priv->irq_lock); | |
3708 | ||
3709 | if (dev_priv->display_irqs_enabled) | |
3710 | return; | |
3711 | ||
3712 | dev_priv->display_irqs_enabled = true; | |
3713 | ||
d6c69803 VS |
3714 | if (intel_irqs_enabled(dev_priv)) { |
3715 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3716 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3717 | } |
f8b79e58 ID |
3718 | } |
3719 | ||
3720 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3721 | { | |
3722 | assert_spin_locked(&dev_priv->irq_lock); | |
3723 | ||
3724 | if (!dev_priv->display_irqs_enabled) | |
3725 | return; | |
3726 | ||
3727 | dev_priv->display_irqs_enabled = false; | |
3728 | ||
950eabaf | 3729 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3730 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3731 | } |
3732 | ||
0e6c9a9e VS |
3733 | |
3734 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3735 | { | |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3737 | ||
0a9a8c91 | 3738 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3739 | |
ad22d106 | 3740 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3741 | if (dev_priv->display_irqs_enabled) |
3742 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3743 | spin_unlock_irq(&dev_priv->irq_lock); |
3744 | ||
7e231dbe | 3745 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3746 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3747 | |
3748 | return 0; | |
3749 | } | |
3750 | ||
abd58f01 BW |
3751 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3752 | { | |
abd58f01 BW |
3753 | /* These are interrupts we'll toggle with the ring mask register */ |
3754 | uint32_t gt_interrupts[] = { | |
3755 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3756 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3757 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3758 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3759 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3760 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3761 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3762 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3763 | 0, |
73d477f6 OM |
3764 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3765 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3766 | }; |
3767 | ||
98735739 TU |
3768 | if (HAS_L3_DPF(dev_priv)) |
3769 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3770 | ||
0961021a | 3771 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3772 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3773 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3774 | /* |
3775 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3776 | * is enabled/disabled. | |
3777 | */ | |
3778 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3779 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3780 | } |
3781 | ||
3782 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3783 | { | |
770de83d DL |
3784 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3785 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3786 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3787 | u32 de_port_enables; | |
11825b0d | 3788 | u32 de_misc_masked = GEN8_DE_MISC_GSE; |
3a3b3c7d | 3789 | enum pipe pipe; |
770de83d | 3790 | |
b4834a50 | 3791 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3792 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3793 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3794 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3795 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3796 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3797 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3798 | } else { | |
770de83d DL |
3799 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3800 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3801 | } |
770de83d DL |
3802 | |
3803 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3804 | GEN8_PIPE_FIFO_UNDERRUN; | |
3805 | ||
3a3b3c7d | 3806 | de_port_enables = de_port_masked; |
a52bb15b VS |
3807 | if (IS_BROXTON(dev_priv)) |
3808 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3809 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3810 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3811 | ||
13b3a0a7 DV |
3812 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3813 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3814 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3815 | |
055e393f | 3816 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3817 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3818 | POWER_DOMAIN_PIPE(pipe))) |
3819 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3820 | dev_priv->de_irq_mask[pipe], | |
3821 | de_pipe_enables); | |
abd58f01 | 3822 | |
3a3b3c7d | 3823 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
11825b0d | 3824 | GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); |
abd58f01 BW |
3825 | } |
3826 | ||
3827 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3828 | { | |
3829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3830 | ||
266ea3d9 SS |
3831 | if (HAS_PCH_SPLIT(dev)) |
3832 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3833 | |
abd58f01 BW |
3834 | gen8_gt_irq_postinstall(dev_priv); |
3835 | gen8_de_irq_postinstall(dev_priv); | |
3836 | ||
266ea3d9 SS |
3837 | if (HAS_PCH_SPLIT(dev)) |
3838 | ibx_irq_postinstall(dev); | |
abd58f01 | 3839 | |
e5328c43 | 3840 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3841 | POSTING_READ(GEN8_MASTER_IRQ); |
3842 | ||
3843 | return 0; | |
3844 | } | |
3845 | ||
43f328d7 VS |
3846 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3847 | { | |
3848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3849 | |
43f328d7 VS |
3850 | gen8_gt_irq_postinstall(dev_priv); |
3851 | ||
ad22d106 | 3852 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3853 | if (dev_priv->display_irqs_enabled) |
3854 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3855 | spin_unlock_irq(&dev_priv->irq_lock); |
3856 | ||
e5328c43 | 3857 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3858 | POSTING_READ(GEN8_MASTER_IRQ); |
3859 | ||
3860 | return 0; | |
3861 | } | |
3862 | ||
abd58f01 BW |
3863 | static void gen8_irq_uninstall(struct drm_device *dev) |
3864 | { | |
3865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3866 | |
3867 | if (!dev_priv) | |
3868 | return; | |
3869 | ||
823f6b38 | 3870 | gen8_irq_reset(dev); |
abd58f01 BW |
3871 | } |
3872 | ||
7e231dbe JB |
3873 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3874 | { | |
2d1013dd | 3875 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3876 | |
3877 | if (!dev_priv) | |
3878 | return; | |
3879 | ||
843d0e7d | 3880 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3881 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3882 | |
893fce8e VS |
3883 | gen5_gt_irq_reset(dev); |
3884 | ||
7e231dbe | 3885 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3886 | |
ad22d106 | 3887 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3888 | if (dev_priv->display_irqs_enabled) |
3889 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3890 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3891 | } |
3892 | ||
43f328d7 VS |
3893 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3894 | { | |
3895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3896 | |
3897 | if (!dev_priv) | |
3898 | return; | |
3899 | ||
3900 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3901 | POSTING_READ(GEN8_MASTER_IRQ); | |
3902 | ||
a2c30fba | 3903 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3904 | |
a2c30fba | 3905 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3906 | |
ad22d106 | 3907 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3908 | if (dev_priv->display_irqs_enabled) |
3909 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3910 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3911 | } |
3912 | ||
f71d4af4 | 3913 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3914 | { |
2d1013dd | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3916 | |
3917 | if (!dev_priv) | |
3918 | return; | |
3919 | ||
be30b29f | 3920 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3921 | } |
3922 | ||
a266c7d5 | 3923 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3924 | { |
2d1013dd | 3925 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3926 | int pipe; |
91e3738e | 3927 | |
055e393f | 3928 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3929 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3930 | I915_WRITE16(IMR, 0xffff); |
3931 | I915_WRITE16(IER, 0x0); | |
3932 | POSTING_READ16(IER); | |
c2798b19 CW |
3933 | } |
3934 | ||
3935 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3936 | { | |
2d1013dd | 3937 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3938 | |
c2798b19 CW |
3939 | I915_WRITE16(EMR, |
3940 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3941 | ||
3942 | /* Unmask the interrupts that we always want on. */ | |
3943 | dev_priv->irq_mask = | |
3944 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3945 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3946 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3947 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3948 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3949 | ||
3950 | I915_WRITE16(IER, | |
3951 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3952 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3953 | I915_USER_INTERRUPT); |
3954 | POSTING_READ16(IER); | |
3955 | ||
379ef82d DV |
3956 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3957 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3958 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3959 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3960 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3961 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3962 | |
c2798b19 CW |
3963 | return 0; |
3964 | } | |
3965 | ||
5a21b665 DV |
3966 | /* |
3967 | * Returns true when a page flip has completed. | |
3968 | */ | |
3969 | static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv, | |
3970 | int plane, int pipe, u32 iir) | |
3971 | { | |
3972 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
3973 | ||
3974 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
3975 | return false; | |
3976 | ||
3977 | if ((iir & flip_pending) == 0) | |
3978 | goto check_page_flip; | |
3979 | ||
3980 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3981 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3982 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3983 | * the flip is completed (no longer pending). Since this doesn't raise | |
3984 | * an interrupt per se, we watch for the change at vblank. | |
3985 | */ | |
3986 | if (I915_READ16(ISR) & flip_pending) | |
3987 | goto check_page_flip; | |
3988 | ||
3989 | intel_finish_page_flip_cs(dev_priv, pipe); | |
3990 | return true; | |
3991 | ||
3992 | check_page_flip: | |
3993 | intel_check_page_flip(dev_priv, pipe); | |
3994 | return false; | |
3995 | } | |
3996 | ||
ff1f525e | 3997 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3998 | { |
45a83f84 | 3999 | struct drm_device *dev = arg; |
2d1013dd | 4000 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4001 | u16 iir, new_iir; |
4002 | u32 pipe_stats[2]; | |
c2798b19 CW |
4003 | int pipe; |
4004 | u16 flip_mask = | |
4005 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4006 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 4007 | irqreturn_t ret; |
c2798b19 | 4008 | |
2dd2a883 ID |
4009 | if (!intel_irqs_enabled(dev_priv)) |
4010 | return IRQ_NONE; | |
4011 | ||
1f814dac ID |
4012 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4013 | disable_rpm_wakeref_asserts(dev_priv); | |
4014 | ||
4015 | ret = IRQ_NONE; | |
c2798b19 CW |
4016 | iir = I915_READ16(IIR); |
4017 | if (iir == 0) | |
1f814dac | 4018 | goto out; |
c2798b19 CW |
4019 | |
4020 | while (iir & ~flip_mask) { | |
4021 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4022 | * have been cleared after the pipestat interrupt was received. | |
4023 | * It doesn't set the bit in iir again, but it still produces | |
4024 | * interrupts (for non-MSI). | |
4025 | */ | |
222c7f51 | 4026 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 4027 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4028 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 4029 | |
055e393f | 4030 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4031 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
4032 | pipe_stats[pipe] = I915_READ(reg); |
4033 | ||
4034 | /* | |
4035 | * Clear the PIPE*STAT regs before the IIR | |
4036 | */ | |
2d9d2b0b | 4037 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 4038 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 4039 | } |
222c7f51 | 4040 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
4041 | |
4042 | I915_WRITE16(IIR, iir & ~flip_mask); | |
4043 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
4044 | ||
c2798b19 | 4045 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4046 | notify_ring(&dev_priv->engine[RCS]); |
c2798b19 | 4047 | |
055e393f | 4048 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4049 | int plane = pipe; |
4050 | if (HAS_FBC(dev_priv)) | |
4051 | plane = !plane; | |
4052 | ||
4053 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
4054 | i8xx_handle_vblank(dev_priv, plane, pipe, iir)) | |
4055 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 4056 | |
4356d586 | 4057 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
91d14251 | 4058 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 4059 | |
1f7247c0 DV |
4060 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4061 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4062 | pipe); | |
4356d586 | 4063 | } |
c2798b19 CW |
4064 | |
4065 | iir = new_iir; | |
4066 | } | |
1f814dac ID |
4067 | ret = IRQ_HANDLED; |
4068 | ||
4069 | out: | |
4070 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 4071 | |
1f814dac | 4072 | return ret; |
c2798b19 CW |
4073 | } |
4074 | ||
4075 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
4076 | { | |
2d1013dd | 4077 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4078 | int pipe; |
4079 | ||
055e393f | 4080 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
4081 | /* Clear enable bits; then clear status bits */ |
4082 | I915_WRITE(PIPESTAT(pipe), 0); | |
4083 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
4084 | } | |
4085 | I915_WRITE16(IMR, 0xffff); | |
4086 | I915_WRITE16(IER, 0x0); | |
4087 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
4088 | } | |
4089 | ||
a266c7d5 CW |
4090 | static void i915_irq_preinstall(struct drm_device * dev) |
4091 | { | |
2d1013dd | 4092 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4093 | int pipe; |
4094 | ||
a266c7d5 | 4095 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4096 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4097 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4098 | } | |
4099 | ||
00d98ebd | 4100 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 4101 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4102 | I915_WRITE(PIPESTAT(pipe), 0); |
4103 | I915_WRITE(IMR, 0xffffffff); | |
4104 | I915_WRITE(IER, 0x0); | |
4105 | POSTING_READ(IER); | |
4106 | } | |
4107 | ||
4108 | static int i915_irq_postinstall(struct drm_device *dev) | |
4109 | { | |
2d1013dd | 4110 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 4111 | u32 enable_mask; |
a266c7d5 | 4112 | |
38bde180 CW |
4113 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
4114 | ||
4115 | /* Unmask the interrupts that we always want on. */ | |
4116 | dev_priv->irq_mask = | |
4117 | ~(I915_ASLE_INTERRUPT | | |
4118 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4119 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4120 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 4121 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
4122 | |
4123 | enable_mask = | |
4124 | I915_ASLE_INTERRUPT | | |
4125 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4126 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
4127 | I915_USER_INTERRUPT; |
4128 | ||
a266c7d5 | 4129 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4130 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4131 | POSTING_READ(PORT_HOTPLUG_EN); |
4132 | ||
a266c7d5 CW |
4133 | /* Enable in IER... */ |
4134 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
4135 | /* and unmask in IMR */ | |
4136 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
4137 | } | |
4138 | ||
a266c7d5 CW |
4139 | I915_WRITE(IMR, dev_priv->irq_mask); |
4140 | I915_WRITE(IER, enable_mask); | |
4141 | POSTING_READ(IER); | |
4142 | ||
91d14251 | 4143 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 | 4144 | |
379ef82d DV |
4145 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4146 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4147 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4148 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4149 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4150 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4151 | |
20afbda2 DV |
4152 | return 0; |
4153 | } | |
4154 | ||
5a21b665 DV |
4155 | /* |
4156 | * Returns true when a page flip has completed. | |
4157 | */ | |
4158 | static bool i915_handle_vblank(struct drm_i915_private *dev_priv, | |
4159 | int plane, int pipe, u32 iir) | |
4160 | { | |
4161 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
4162 | ||
4163 | if (!intel_pipe_handle_vblank(dev_priv, pipe)) | |
4164 | return false; | |
4165 | ||
4166 | if ((iir & flip_pending) == 0) | |
4167 | goto check_page_flip; | |
4168 | ||
4169 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
4170 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4171 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4172 | * the flip is completed (no longer pending). Since this doesn't raise | |
4173 | * an interrupt per se, we watch for the change at vblank. | |
4174 | */ | |
4175 | if (I915_READ(ISR) & flip_pending) | |
4176 | goto check_page_flip; | |
4177 | ||
4178 | intel_finish_page_flip_cs(dev_priv, pipe); | |
4179 | return true; | |
4180 | ||
4181 | check_page_flip: | |
4182 | intel_check_page_flip(dev_priv, pipe); | |
4183 | return false; | |
4184 | } | |
4185 | ||
ff1f525e | 4186 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 4187 | { |
45a83f84 | 4188 | struct drm_device *dev = arg; |
2d1013dd | 4189 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 4190 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
4191 | u32 flip_mask = |
4192 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4193 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 4194 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 4195 | |
2dd2a883 ID |
4196 | if (!intel_irqs_enabled(dev_priv)) |
4197 | return IRQ_NONE; | |
4198 | ||
1f814dac ID |
4199 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4200 | disable_rpm_wakeref_asserts(dev_priv); | |
4201 | ||
a266c7d5 | 4202 | iir = I915_READ(IIR); |
38bde180 CW |
4203 | do { |
4204 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 4205 | bool blc_event = false; |
a266c7d5 CW |
4206 | |
4207 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4208 | * have been cleared after the pipestat interrupt was received. | |
4209 | * It doesn't set the bit in iir again, but it still produces | |
4210 | * interrupts (for non-MSI). | |
4211 | */ | |
222c7f51 | 4212 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4213 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4214 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4215 | |
055e393f | 4216 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4217 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4218 | pipe_stats[pipe] = I915_READ(reg); |
4219 | ||
38bde180 | 4220 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4221 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4222 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4223 | irq_received = true; |
a266c7d5 CW |
4224 | } |
4225 | } | |
222c7f51 | 4226 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4227 | |
4228 | if (!irq_received) | |
4229 | break; | |
4230 | ||
a266c7d5 | 4231 | /* Consume port. Then clear IIR or we'll miss events */ |
91d14251 | 4232 | if (I915_HAS_HOTPLUG(dev_priv) && |
1ae3c34c VS |
4233 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
4234 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4235 | if (hotplug_status) | |
91d14251 | 4236 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4237 | } |
a266c7d5 | 4238 | |
38bde180 | 4239 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4240 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4241 | ||
a266c7d5 | 4242 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4243 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4244 | |
055e393f | 4245 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4246 | int plane = pipe; |
4247 | if (HAS_FBC(dev_priv)) | |
4248 | plane = !plane; | |
4249 | ||
4250 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && | |
4251 | i915_handle_vblank(dev_priv, plane, pipe, iir)) | |
4252 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4253 | |
4254 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4255 | blc_event = true; | |
4356d586 DV |
4256 | |
4257 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4258 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
2d9d2b0b | 4259 | |
1f7247c0 DV |
4260 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4261 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4262 | pipe); | |
a266c7d5 CW |
4263 | } |
4264 | ||
a266c7d5 | 4265 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
91d14251 | 4266 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 CW |
4267 | |
4268 | /* With MSI, interrupts are only generated when iir | |
4269 | * transitions from zero to nonzero. If another bit got | |
4270 | * set while we were handling the existing iir bits, then | |
4271 | * we would never get another interrupt. | |
4272 | * | |
4273 | * This is fine on non-MSI as well, as if we hit this path | |
4274 | * we avoid exiting the interrupt handler only to generate | |
4275 | * another one. | |
4276 | * | |
4277 | * Note that for MSI this could cause a stray interrupt report | |
4278 | * if an interrupt landed in the time between writing IIR and | |
4279 | * the posting read. This should be rare enough to never | |
4280 | * trigger the 99% of 100,000 interrupts test for disabling | |
4281 | * stray interrupts. | |
4282 | */ | |
38bde180 | 4283 | ret = IRQ_HANDLED; |
a266c7d5 | 4284 | iir = new_iir; |
38bde180 | 4285 | } while (iir & ~flip_mask); |
a266c7d5 | 4286 | |
1f814dac ID |
4287 | enable_rpm_wakeref_asserts(dev_priv); |
4288 | ||
a266c7d5 CW |
4289 | return ret; |
4290 | } | |
4291 | ||
4292 | static void i915_irq_uninstall(struct drm_device * dev) | |
4293 | { | |
2d1013dd | 4294 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4295 | int pipe; |
4296 | ||
a266c7d5 | 4297 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4298 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4299 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4300 | } | |
4301 | ||
00d98ebd | 4302 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4303 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4304 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4305 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4306 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4307 | } | |
a266c7d5 CW |
4308 | I915_WRITE(IMR, 0xffffffff); |
4309 | I915_WRITE(IER, 0x0); | |
4310 | ||
a266c7d5 CW |
4311 | I915_WRITE(IIR, I915_READ(IIR)); |
4312 | } | |
4313 | ||
4314 | static void i965_irq_preinstall(struct drm_device * dev) | |
4315 | { | |
2d1013dd | 4316 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4317 | int pipe; |
4318 | ||
0706f17c | 4319 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4320 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4321 | |
4322 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4323 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4324 | I915_WRITE(PIPESTAT(pipe), 0); |
4325 | I915_WRITE(IMR, 0xffffffff); | |
4326 | I915_WRITE(IER, 0x0); | |
4327 | POSTING_READ(IER); | |
4328 | } | |
4329 | ||
4330 | static int i965_irq_postinstall(struct drm_device *dev) | |
4331 | { | |
2d1013dd | 4332 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4333 | u32 enable_mask; |
a266c7d5 CW |
4334 | u32 error_mask; |
4335 | ||
a266c7d5 | 4336 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4337 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4338 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4339 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4340 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4341 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4342 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4343 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4344 | ||
4345 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4346 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4347 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4348 | enable_mask |= I915_USER_INTERRUPT; |
4349 | ||
91d14251 | 4350 | if (IS_G4X(dev_priv)) |
bbba0a97 | 4351 | enable_mask |= I915_BSD_USER_INTERRUPT; |
a266c7d5 | 4352 | |
b79480ba DV |
4353 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4354 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4355 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4356 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4357 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4358 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4359 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4360 | |
a266c7d5 CW |
4361 | /* |
4362 | * Enable some error detection, note the instruction error mask | |
4363 | * bit is reserved, so we leave it masked. | |
4364 | */ | |
91d14251 | 4365 | if (IS_G4X(dev_priv)) { |
a266c7d5 CW |
4366 | error_mask = ~(GM45_ERROR_PAGE_TABLE | |
4367 | GM45_ERROR_MEM_PRIV | | |
4368 | GM45_ERROR_CP_PRIV | | |
4369 | I915_ERROR_MEMORY_REFRESH); | |
4370 | } else { | |
4371 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4372 | I915_ERROR_MEMORY_REFRESH); | |
4373 | } | |
4374 | I915_WRITE(EMR, error_mask); | |
4375 | ||
4376 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4377 | I915_WRITE(IER, enable_mask); | |
4378 | POSTING_READ(IER); | |
4379 | ||
0706f17c | 4380 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4381 | POSTING_READ(PORT_HOTPLUG_EN); |
4382 | ||
91d14251 | 4383 | i915_enable_asle_pipestat(dev_priv); |
20afbda2 DV |
4384 | |
4385 | return 0; | |
4386 | } | |
4387 | ||
91d14251 | 4388 | static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) |
20afbda2 | 4389 | { |
20afbda2 DV |
4390 | u32 hotplug_en; |
4391 | ||
b5ea2d56 DV |
4392 | assert_spin_locked(&dev_priv->irq_lock); |
4393 | ||
778eb334 VS |
4394 | /* Note HDMI and DP share hotplug bits */ |
4395 | /* enable bits are the same for all generations */ | |
91d14251 | 4396 | hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); |
778eb334 VS |
4397 | /* Programming the CRT detection parameters tends |
4398 | to generate a spurious hotplug event about three | |
4399 | seconds later. So just do it once. | |
4400 | */ | |
91d14251 | 4401 | if (IS_G4X(dev_priv)) |
778eb334 | 4402 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
778eb334 VS |
4403 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4404 | ||
4405 | /* Ignore TV since it's buggy */ | |
0706f17c | 4406 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4407 | HOTPLUG_INT_EN_MASK | |
4408 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4409 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4410 | hotplug_en); | |
a266c7d5 CW |
4411 | } |
4412 | ||
ff1f525e | 4413 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4414 | { |
45a83f84 | 4415 | struct drm_device *dev = arg; |
2d1013dd | 4416 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4417 | u32 iir, new_iir; |
4418 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4419 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4420 | u32 flip_mask = |
4421 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4422 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4423 | |
2dd2a883 ID |
4424 | if (!intel_irqs_enabled(dev_priv)) |
4425 | return IRQ_NONE; | |
4426 | ||
1f814dac ID |
4427 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4428 | disable_rpm_wakeref_asserts(dev_priv); | |
4429 | ||
a266c7d5 CW |
4430 | iir = I915_READ(IIR); |
4431 | ||
a266c7d5 | 4432 | for (;;) { |
501e01d7 | 4433 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4434 | bool blc_event = false; |
4435 | ||
a266c7d5 CW |
4436 | /* Can't rely on pipestat interrupt bit in iir as it might |
4437 | * have been cleared after the pipestat interrupt was received. | |
4438 | * It doesn't set the bit in iir again, but it still produces | |
4439 | * interrupts (for non-MSI). | |
4440 | */ | |
222c7f51 | 4441 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4442 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4443 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4444 | |
055e393f | 4445 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4446 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4447 | pipe_stats[pipe] = I915_READ(reg); |
4448 | ||
4449 | /* | |
4450 | * Clear the PIPE*STAT regs before the IIR | |
4451 | */ | |
4452 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4453 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4454 | irq_received = true; |
a266c7d5 CW |
4455 | } |
4456 | } | |
222c7f51 | 4457 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4458 | |
4459 | if (!irq_received) | |
4460 | break; | |
4461 | ||
4462 | ret = IRQ_HANDLED; | |
4463 | ||
4464 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4465 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4466 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4467 | if (hotplug_status) | |
91d14251 | 4468 | i9xx_hpd_irq_handler(dev_priv, hotplug_status); |
1ae3c34c | 4469 | } |
a266c7d5 | 4470 | |
21ad8330 | 4471 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4472 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4473 | ||
a266c7d5 | 4474 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4475 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4476 | if (iir & I915_BSD_USER_INTERRUPT) |
4a570db5 | 4477 | notify_ring(&dev_priv->engine[VCS]); |
a266c7d5 | 4478 | |
055e393f | 4479 | for_each_pipe(dev_priv, pipe) { |
5a21b665 DV |
4480 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
4481 | i915_handle_vblank(dev_priv, pipe, pipe, iir)) | |
4482 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4483 | |
4484 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4485 | blc_event = true; | |
4356d586 DV |
4486 | |
4487 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
91d14251 | 4488 | i9xx_pipe_crc_irq_handler(dev_priv, pipe); |
a266c7d5 | 4489 | |
1f7247c0 DV |
4490 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4491 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4492 | } |
a266c7d5 CW |
4493 | |
4494 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
91d14251 | 4495 | intel_opregion_asle_intr(dev_priv); |
a266c7d5 | 4496 | |
515ac2bb | 4497 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
91d14251 | 4498 | gmbus_irq_handler(dev_priv); |
515ac2bb | 4499 | |
a266c7d5 CW |
4500 | /* With MSI, interrupts are only generated when iir |
4501 | * transitions from zero to nonzero. If another bit got | |
4502 | * set while we were handling the existing iir bits, then | |
4503 | * we would never get another interrupt. | |
4504 | * | |
4505 | * This is fine on non-MSI as well, as if we hit this path | |
4506 | * we avoid exiting the interrupt handler only to generate | |
4507 | * another one. | |
4508 | * | |
4509 | * Note that for MSI this could cause a stray interrupt report | |
4510 | * if an interrupt landed in the time between writing IIR and | |
4511 | * the posting read. This should be rare enough to never | |
4512 | * trigger the 99% of 100,000 interrupts test for disabling | |
4513 | * stray interrupts. | |
4514 | */ | |
4515 | iir = new_iir; | |
4516 | } | |
4517 | ||
1f814dac ID |
4518 | enable_rpm_wakeref_asserts(dev_priv); |
4519 | ||
a266c7d5 CW |
4520 | return ret; |
4521 | } | |
4522 | ||
4523 | static void i965_irq_uninstall(struct drm_device * dev) | |
4524 | { | |
2d1013dd | 4525 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4526 | int pipe; |
4527 | ||
4528 | if (!dev_priv) | |
4529 | return; | |
4530 | ||
0706f17c | 4531 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4532 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4533 | |
4534 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4535 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4536 | I915_WRITE(PIPESTAT(pipe), 0); |
4537 | I915_WRITE(IMR, 0xffffffff); | |
4538 | I915_WRITE(IER, 0x0); | |
4539 | ||
055e393f | 4540 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4541 | I915_WRITE(PIPESTAT(pipe), |
4542 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4543 | I915_WRITE(IIR, I915_READ(IIR)); | |
4544 | } | |
4545 | ||
fca52a55 DV |
4546 | /** |
4547 | * intel_irq_init - initializes irq support | |
4548 | * @dev_priv: i915 device instance | |
4549 | * | |
4550 | * This function initializes all the irq support including work items, timers | |
4551 | * and all the vtables. It does not setup the interrupt itself though. | |
4552 | */ | |
b963291c | 4553 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4554 | { |
b963291c | 4555 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4556 | |
77913b39 JN |
4557 | intel_hpd_init_work(dev_priv); |
4558 | ||
c6a828d3 | 4559 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4560 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4561 | |
a6706b45 | 4562 | /* Let's track the enabled rps events */ |
666a4537 | 4563 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4564 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4565 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4566 | else |
4567 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4568 | |
1800ad25 SAK |
4569 | dev_priv->rps.pm_intr_keep = 0; |
4570 | ||
4571 | /* | |
4572 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer | |
4573 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
4574 | * | |
4575 | * TODO: verify if this can be reproduced on VLV,CHV. | |
4576 | */ | |
4577 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
4578 | dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED; | |
4579 | ||
4580 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
4581 | dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
4582 | ||
737b1506 CW |
4583 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4584 | i915_hangcheck_elapsed); | |
61bac78e | 4585 | |
b963291c | 4586 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4587 | dev->max_vblank_count = 0; |
4588 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4589 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4590 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4591 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4592 | } else { |
4593 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4594 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4595 | } |
4596 | ||
21da2700 VS |
4597 | /* |
4598 | * Opt out of the vblank disable timer on everything except gen2. | |
4599 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4600 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4601 | */ | |
b963291c | 4602 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4603 | dev->vblank_disable_immediate = true; |
4604 | ||
f3a5c3f6 DV |
4605 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4606 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4607 | |
b963291c | 4608 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4609 | dev->driver->irq_handler = cherryview_irq_handler; |
4610 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4611 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4612 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4613 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4614 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4615 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4616 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4617 | dev->driver->irq_handler = valleyview_irq_handler; |
4618 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4619 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4620 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4621 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4622 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4623 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4624 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4625 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4626 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4627 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4628 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4629 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4630 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4631 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4632 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6dbf30ce VS |
4633 | else if (HAS_PCH_SPT(dev)) |
4634 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; | |
4635 | else | |
3a3b3c7d | 4636 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4637 | } else if (HAS_PCH_SPLIT(dev)) { |
4638 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4639 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4640 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4641 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4642 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4643 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4644 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4645 | } else { |
7e22dbbb | 4646 | if (IS_GEN2(dev_priv)) { |
c2798b19 CW |
4647 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4648 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4649 | dev->driver->irq_handler = i8xx_irq_handler; | |
4650 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
7e22dbbb | 4651 | } else if (IS_GEN3(dev_priv)) { |
a266c7d5 CW |
4652 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4653 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4654 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4655 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4656 | } else { |
a266c7d5 CW |
4657 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4658 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4659 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4660 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4661 | } |
778eb334 VS |
4662 | if (I915_HAS_HOTPLUG(dev_priv)) |
4663 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4664 | dev->driver->enable_vblank = i915_enable_vblank; |
4665 | dev->driver->disable_vblank = i915_disable_vblank; | |
4666 | } | |
4667 | } | |
20afbda2 | 4668 | |
fca52a55 DV |
4669 | /** |
4670 | * intel_irq_install - enables the hardware interrupt | |
4671 | * @dev_priv: i915 device instance | |
4672 | * | |
4673 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4674 | * handling still disabled. It is called after intel_irq_init(). | |
4675 | * | |
4676 | * In the driver load and resume code we need working interrupts in a few places | |
4677 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4678 | * workers. Hence the split into this two-stage approach. | |
4679 | */ | |
2aeb7d3a DV |
4680 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4681 | { | |
4682 | /* | |
4683 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4684 | * interrupts as enabled _before_ actually enabling them to avoid | |
4685 | * special cases in our ordering checks. | |
4686 | */ | |
4687 | dev_priv->pm.irqs_enabled = true; | |
4688 | ||
4689 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4690 | } | |
4691 | ||
fca52a55 DV |
4692 | /** |
4693 | * intel_irq_uninstall - finilizes all irq handling | |
4694 | * @dev_priv: i915 device instance | |
4695 | * | |
4696 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4697 | * resources acquired in the init functions. | |
4698 | */ | |
2aeb7d3a DV |
4699 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4700 | { | |
4701 | drm_irq_uninstall(dev_priv->dev); | |
4702 | intel_hpd_cancel_work(dev_priv); | |
4703 | dev_priv->pm.irqs_enabled = false; | |
4704 | } | |
4705 | ||
fca52a55 DV |
4706 | /** |
4707 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4708 | * @dev_priv: i915 device instance | |
4709 | * | |
4710 | * This function is used to disable interrupts at runtime, both in the runtime | |
4711 | * pm and the system suspend/resume code. | |
4712 | */ | |
b963291c | 4713 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4714 | { |
b963291c | 4715 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4716 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4717 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4718 | } |
4719 | ||
fca52a55 DV |
4720 | /** |
4721 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4722 | * @dev_priv: i915 device instance | |
4723 | * | |
4724 | * This function is used to enable interrupts at runtime, both in the runtime | |
4725 | * pm and the system suspend/resume code. | |
4726 | */ | |
b963291c | 4727 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4728 | { |
2aeb7d3a | 4729 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4730 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4731 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4732 | } |