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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
f0f59a00 VS |
142 | static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, |
143 | i915_reg_t reg) | |
b51a2842 VS |
144 | { |
145 | u32 val = I915_READ(reg); | |
146 | ||
147 | if (val == 0) | |
148 | return; | |
149 | ||
150 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", | |
f0f59a00 | 151 | i915_mmio_reg_offset(reg), val); |
b51a2842 VS |
152 | I915_WRITE(reg, 0xffffffff); |
153 | POSTING_READ(reg); | |
154 | I915_WRITE(reg, 0xffffffff); | |
155 | POSTING_READ(reg); | |
156 | } | |
337ba017 | 157 | |
35079899 | 158 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
b51a2842 | 159 | gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ |
35079899 | 160 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
161 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
162 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
163 | } while (0) |
164 | ||
165 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
b51a2842 | 166 | gen5_assert_iir_is_zero(dev_priv, type##IIR); \ |
35079899 | 167 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
168 | I915_WRITE(type##IMR, (imr_val)); \ |
169 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
170 | } while (0) |
171 | ||
c9a9a268 ID |
172 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
173 | ||
0706f17c EE |
174 | /* For display hotplug interrupt */ |
175 | static inline void | |
176 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
177 | uint32_t mask, | |
178 | uint32_t bits) | |
179 | { | |
180 | uint32_t val; | |
181 | ||
182 | assert_spin_locked(&dev_priv->irq_lock); | |
183 | WARN_ON(bits & ~mask); | |
184 | ||
185 | val = I915_READ(PORT_HOTPLUG_EN); | |
186 | val &= ~mask; | |
187 | val |= bits; | |
188 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
189 | } | |
190 | ||
191 | /** | |
192 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
193 | * @dev_priv: driver private | |
194 | * @mask: bits to update | |
195 | * @bits: bits to enable | |
196 | * NOTE: the HPD enable bits are modified both inside and outside | |
197 | * of an interrupt context. To avoid that read-modify-write cycles | |
198 | * interfer, these bits are protected by a spinlock. Since this | |
199 | * function is usually not called from a context where the lock is | |
200 | * held already, this function acquires the lock itself. A non-locking | |
201 | * version is also available. | |
202 | */ | |
203 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
204 | uint32_t mask, | |
205 | uint32_t bits) | |
206 | { | |
207 | spin_lock_irq(&dev_priv->irq_lock); | |
208 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
209 | spin_unlock_irq(&dev_priv->irq_lock); | |
210 | } | |
211 | ||
d9dc34f1 VS |
212 | /** |
213 | * ilk_update_display_irq - update DEIMR | |
214 | * @dev_priv: driver private | |
215 | * @interrupt_mask: mask of interrupt bits to update | |
216 | * @enabled_irq_mask: mask of interrupt bits to enable | |
217 | */ | |
fbdedaea VS |
218 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
219 | uint32_t interrupt_mask, | |
220 | uint32_t enabled_irq_mask) | |
036a4a7d | 221 | { |
d9dc34f1 VS |
222 | uint32_t new_val; |
223 | ||
4bc9d430 DV |
224 | assert_spin_locked(&dev_priv->irq_lock); |
225 | ||
d9dc34f1 VS |
226 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
227 | ||
9df7575f | 228 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 229 | return; |
c67a470b | 230 | |
d9dc34f1 VS |
231 | new_val = dev_priv->irq_mask; |
232 | new_val &= ~interrupt_mask; | |
233 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
234 | ||
235 | if (new_val != dev_priv->irq_mask) { | |
236 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 237 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 238 | POSTING_READ(DEIMR); |
036a4a7d ZW |
239 | } |
240 | } | |
241 | ||
43eaea13 PZ |
242 | /** |
243 | * ilk_update_gt_irq - update GTIMR | |
244 | * @dev_priv: driver private | |
245 | * @interrupt_mask: mask of interrupt bits to update | |
246 | * @enabled_irq_mask: mask of interrupt bits to enable | |
247 | */ | |
248 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
249 | uint32_t interrupt_mask, | |
250 | uint32_t enabled_irq_mask) | |
251 | { | |
252 | assert_spin_locked(&dev_priv->irq_lock); | |
253 | ||
15a17aae DV |
254 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
255 | ||
9df7575f | 256 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 257 | return; |
c67a470b | 258 | |
43eaea13 PZ |
259 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
260 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
261 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
262 | POSTING_READ(GTIMR); | |
263 | } | |
264 | ||
480c8033 | 265 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
266 | { |
267 | ilk_update_gt_irq(dev_priv, mask, mask); | |
268 | } | |
269 | ||
480c8033 | 270 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
271 | { |
272 | ilk_update_gt_irq(dev_priv, mask, 0); | |
273 | } | |
274 | ||
f0f59a00 | 275 | static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) |
b900b949 ID |
276 | { |
277 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
278 | } | |
279 | ||
f0f59a00 | 280 | static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) |
a72fbc3a ID |
281 | { |
282 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
283 | } | |
284 | ||
f0f59a00 | 285 | static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) |
b900b949 ID |
286 | { |
287 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
288 | } | |
289 | ||
edbfdb45 | 290 | /** |
81fd874e VS |
291 | * snb_update_pm_irq - update GEN6_PMIMR |
292 | * @dev_priv: driver private | |
293 | * @interrupt_mask: mask of interrupt bits to update | |
294 | * @enabled_irq_mask: mask of interrupt bits to enable | |
295 | */ | |
edbfdb45 PZ |
296 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, |
297 | uint32_t interrupt_mask, | |
298 | uint32_t enabled_irq_mask) | |
299 | { | |
605cd25b | 300 | uint32_t new_val; |
edbfdb45 | 301 | |
15a17aae DV |
302 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
303 | ||
edbfdb45 PZ |
304 | assert_spin_locked(&dev_priv->irq_lock); |
305 | ||
605cd25b | 306 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
307 | new_val &= ~interrupt_mask; |
308 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
309 | ||
605cd25b PZ |
310 | if (new_val != dev_priv->pm_irq_mask) { |
311 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
312 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
313 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 314 | } |
edbfdb45 PZ |
315 | } |
316 | ||
480c8033 | 317 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 318 | { |
9939fba2 ID |
319 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
320 | return; | |
321 | ||
edbfdb45 PZ |
322 | snb_update_pm_irq(dev_priv, mask, mask); |
323 | } | |
324 | ||
9939fba2 ID |
325 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
326 | uint32_t mask) | |
edbfdb45 PZ |
327 | { |
328 | snb_update_pm_irq(dev_priv, mask, 0); | |
329 | } | |
330 | ||
9939fba2 ID |
331 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
332 | { | |
333 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
334 | return; | |
335 | ||
336 | __gen6_disable_pm_irq(dev_priv, mask); | |
337 | } | |
338 | ||
3cc134e3 ID |
339 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
340 | { | |
341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 342 | i915_reg_t reg = gen6_pm_iir(dev_priv); |
3cc134e3 ID |
343 | |
344 | spin_lock_irq(&dev_priv->irq_lock); | |
345 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
346 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
347 | POSTING_READ(reg); | |
096fad9e | 348 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
349 | spin_unlock_irq(&dev_priv->irq_lock); |
350 | } | |
351 | ||
b900b949 ID |
352 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
353 | { | |
354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
355 | ||
356 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 357 | |
b900b949 | 358 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 359 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 360 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
361 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
362 | dev_priv->pm_rps_events); | |
b900b949 | 363 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 364 | |
b900b949 ID |
365 | spin_unlock_irq(&dev_priv->irq_lock); |
366 | } | |
367 | ||
59d02a1f ID |
368 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
369 | { | |
370 | /* | |
f24eeb19 | 371 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 372 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
373 | * |
374 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
375 | */ |
376 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
377 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
378 | ||
379 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
380 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
381 | ||
382 | return mask; | |
383 | } | |
384 | ||
b900b949 ID |
385 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
386 | { | |
387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
388 | ||
d4d70aa5 ID |
389 | spin_lock_irq(&dev_priv->irq_lock); |
390 | dev_priv->rps.interrupts_enabled = false; | |
391 | spin_unlock_irq(&dev_priv->irq_lock); | |
392 | ||
393 | cancel_work_sync(&dev_priv->rps.work); | |
394 | ||
9939fba2 ID |
395 | spin_lock_irq(&dev_priv->irq_lock); |
396 | ||
59d02a1f | 397 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
398 | |
399 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
400 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
401 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
402 | |
403 | spin_unlock_irq(&dev_priv->irq_lock); | |
404 | ||
405 | synchronize_irq(dev->irq); | |
b900b949 ID |
406 | } |
407 | ||
3a3b3c7d | 408 | /** |
81fd874e VS |
409 | * bdw_update_port_irq - update DE port interrupt |
410 | * @dev_priv: driver private | |
411 | * @interrupt_mask: mask of interrupt bits to update | |
412 | * @enabled_irq_mask: mask of interrupt bits to enable | |
413 | */ | |
3a3b3c7d VS |
414 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, |
415 | uint32_t interrupt_mask, | |
416 | uint32_t enabled_irq_mask) | |
417 | { | |
418 | uint32_t new_val; | |
419 | uint32_t old_val; | |
420 | ||
421 | assert_spin_locked(&dev_priv->irq_lock); | |
422 | ||
423 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
424 | ||
425 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
426 | return; | |
427 | ||
428 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
429 | ||
430 | new_val = old_val; | |
431 | new_val &= ~interrupt_mask; | |
432 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
433 | ||
434 | if (new_val != old_val) { | |
435 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
436 | POSTING_READ(GEN8_DE_PORT_IMR); | |
437 | } | |
438 | } | |
439 | ||
013d3752 VS |
440 | /** |
441 | * bdw_update_pipe_irq - update DE pipe interrupt | |
442 | * @dev_priv: driver private | |
443 | * @pipe: pipe whose interrupt to update | |
444 | * @interrupt_mask: mask of interrupt bits to update | |
445 | * @enabled_irq_mask: mask of interrupt bits to enable | |
446 | */ | |
447 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, | |
448 | enum pipe pipe, | |
449 | uint32_t interrupt_mask, | |
450 | uint32_t enabled_irq_mask) | |
451 | { | |
452 | uint32_t new_val; | |
453 | ||
454 | assert_spin_locked(&dev_priv->irq_lock); | |
455 | ||
456 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
457 | ||
458 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
459 | return; | |
460 | ||
461 | new_val = dev_priv->de_irq_mask[pipe]; | |
462 | new_val &= ~interrupt_mask; | |
463 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
464 | ||
465 | if (new_val != dev_priv->de_irq_mask[pipe]) { | |
466 | dev_priv->de_irq_mask[pipe] = new_val; | |
467 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
468 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
469 | } | |
470 | } | |
471 | ||
fee884ed DV |
472 | /** |
473 | * ibx_display_interrupt_update - update SDEIMR | |
474 | * @dev_priv: driver private | |
475 | * @interrupt_mask: mask of interrupt bits to update | |
476 | * @enabled_irq_mask: mask of interrupt bits to enable | |
477 | */ | |
47339cd9 DV |
478 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
479 | uint32_t interrupt_mask, | |
480 | uint32_t enabled_irq_mask) | |
fee884ed DV |
481 | { |
482 | uint32_t sdeimr = I915_READ(SDEIMR); | |
483 | sdeimr &= ~interrupt_mask; | |
484 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
485 | ||
15a17aae DV |
486 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
487 | ||
fee884ed DV |
488 | assert_spin_locked(&dev_priv->irq_lock); |
489 | ||
9df7575f | 490 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 491 | return; |
c67a470b | 492 | |
fee884ed DV |
493 | I915_WRITE(SDEIMR, sdeimr); |
494 | POSTING_READ(SDEIMR); | |
495 | } | |
8664281b | 496 | |
b5ea642a | 497 | static void |
755e9019 ID |
498 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
499 | u32 enable_mask, u32 status_mask) | |
7c463586 | 500 | { |
f0f59a00 | 501 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 502 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 503 | |
b79480ba | 504 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 505 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 506 | |
04feced9 VS |
507 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
508 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
509 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
510 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
511 | return; |
512 | ||
513 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
514 | return; |
515 | ||
91d181dd ID |
516 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
517 | ||
46c06a30 | 518 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 519 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
520 | I915_WRITE(reg, pipestat); |
521 | POSTING_READ(reg); | |
7c463586 KP |
522 | } |
523 | ||
b5ea642a | 524 | static void |
755e9019 ID |
525 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
526 | u32 enable_mask, u32 status_mask) | |
7c463586 | 527 | { |
f0f59a00 | 528 | i915_reg_t reg = PIPESTAT(pipe); |
755e9019 | 529 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 530 | |
b79480ba | 531 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 532 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 533 | |
04feced9 VS |
534 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
535 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
536 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
537 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
538 | return; |
539 | ||
755e9019 ID |
540 | if ((pipestat & enable_mask) == 0) |
541 | return; | |
542 | ||
91d181dd ID |
543 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
544 | ||
755e9019 | 545 | pipestat &= ~enable_mask; |
46c06a30 VS |
546 | I915_WRITE(reg, pipestat); |
547 | POSTING_READ(reg); | |
7c463586 KP |
548 | } |
549 | ||
10c59c51 ID |
550 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
551 | { | |
552 | u32 enable_mask = status_mask << 16; | |
553 | ||
554 | /* | |
724a6905 VS |
555 | * On pipe A we don't support the PSR interrupt yet, |
556 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
557 | */ |
558 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
559 | return 0; | |
724a6905 VS |
560 | /* |
561 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
562 | * A the same bit is for perf counters which we don't use either. | |
563 | */ | |
564 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
565 | return 0; | |
10c59c51 ID |
566 | |
567 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
568 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
569 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
570 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
571 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
572 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
573 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
574 | ||
575 | return enable_mask; | |
576 | } | |
577 | ||
755e9019 ID |
578 | void |
579 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
580 | u32 status_mask) | |
581 | { | |
582 | u32 enable_mask; | |
583 | ||
666a4537 | 584 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
585 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
586 | status_mask); | |
587 | else | |
588 | enable_mask = status_mask << 16; | |
755e9019 ID |
589 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
590 | } | |
591 | ||
592 | void | |
593 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
594 | u32 status_mask) | |
595 | { | |
596 | u32 enable_mask; | |
597 | ||
666a4537 | 598 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
10c59c51 ID |
599 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, |
600 | status_mask); | |
601 | else | |
602 | enable_mask = status_mask << 16; | |
755e9019 ID |
603 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
604 | } | |
605 | ||
01c66889 | 606 | /** |
f49e38dd | 607 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
468f9d29 | 608 | * @dev: drm device |
01c66889 | 609 | */ |
f49e38dd | 610 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 611 | { |
2d1013dd | 612 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 613 | |
f49e38dd JN |
614 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
615 | return; | |
616 | ||
13321786 | 617 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 618 | |
755e9019 | 619 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 620 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 621 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 622 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 623 | |
13321786 | 624 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
625 | } |
626 | ||
f75f3746 VS |
627 | /* |
628 | * This timing diagram depicts the video signal in and | |
629 | * around the vertical blanking period. | |
630 | * | |
631 | * Assumptions about the fictitious mode used in this example: | |
632 | * vblank_start >= 3 | |
633 | * vsync_start = vblank_start + 1 | |
634 | * vsync_end = vblank_start + 2 | |
635 | * vtotal = vblank_start + 3 | |
636 | * | |
637 | * start of vblank: | |
638 | * latch double buffered registers | |
639 | * increment frame counter (ctg+) | |
640 | * generate start of vblank interrupt (gen4+) | |
641 | * | | |
642 | * | frame start: | |
643 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
644 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
645 | * | | | |
646 | * | | start of vsync: | |
647 | * | | generate vsync interrupt | |
648 | * | | | | |
649 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
650 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
651 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
652 | * | | <----vs-----> | | |
653 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
654 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
655 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
656 | * | | | | |
657 | * last visible pixel first visible pixel | |
658 | * | increment frame counter (gen3/4) | |
659 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
660 | * | |
661 | * x = horizontal active | |
662 | * _ = horizontal blanking | |
663 | * hs = horizontal sync | |
664 | * va = vertical active | |
665 | * vb = vertical blanking | |
666 | * vs = vertical sync | |
667 | * vbs = vblank_start (number) | |
668 | * | |
669 | * Summary: | |
670 | * - most events happen at the start of horizontal sync | |
671 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
672 | * (depending on PIPECONF settings) after the start of vblank | |
673 | * - gen3/4 pixel and frame counter are synchronized with the start | |
674 | * of horizontal active on the first line of vertical active | |
675 | */ | |
676 | ||
88e72717 | 677 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
4cdb83ec VS |
678 | { |
679 | /* Gen2 doesn't have a hardware frame counter */ | |
680 | return 0; | |
681 | } | |
682 | ||
42f52ef8 KP |
683 | /* Called from drm generic code, passed a 'crtc', which |
684 | * we use as a pipe index | |
685 | */ | |
88e72717 | 686 | static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 687 | { |
2d1013dd | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 689 | i915_reg_t high_frame, low_frame; |
0b2a8e09 | 690 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
691 | struct intel_crtc *intel_crtc = |
692 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 693 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 694 | |
f3a5c3f6 DV |
695 | htotal = mode->crtc_htotal; |
696 | hsync_start = mode->crtc_hsync_start; | |
697 | vbl_start = mode->crtc_vblank_start; | |
698 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
699 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 700 | |
0b2a8e09 VS |
701 | /* Convert to pixel count */ |
702 | vbl_start *= htotal; | |
703 | ||
704 | /* Start of vblank event occurs at start of hsync */ | |
705 | vbl_start -= htotal - hsync_start; | |
706 | ||
9db4a9c7 JB |
707 | high_frame = PIPEFRAME(pipe); |
708 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 709 | |
0a3e67a4 JB |
710 | /* |
711 | * High & low register fields aren't synchronized, so make sure | |
712 | * we get a low value that's stable across two reads of the high | |
713 | * register. | |
714 | */ | |
715 | do { | |
5eddb70b | 716 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 717 | low = I915_READ(low_frame); |
5eddb70b | 718 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
719 | } while (high1 != high2); |
720 | ||
5eddb70b | 721 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 722 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 723 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
724 | |
725 | /* | |
726 | * The frame counter increments at beginning of active. | |
727 | * Cook up a vblank counter by also checking the pixel | |
728 | * counter against vblank start. | |
729 | */ | |
edc08d0a | 730 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
731 | } |
732 | ||
974e59ba | 733 | static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) |
9880b7a5 | 734 | { |
2d1013dd | 735 | struct drm_i915_private *dev_priv = dev->dev_private; |
9880b7a5 | 736 | |
649636ef | 737 | return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); |
9880b7a5 JB |
738 | } |
739 | ||
75aa3f63 | 740 | /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */ |
a225f079 VS |
741 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
742 | { | |
743 | struct drm_device *dev = crtc->base.dev; | |
744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 745 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 746 | enum pipe pipe = crtc->pipe; |
80715b2f | 747 | int position, vtotal; |
a225f079 | 748 | |
80715b2f | 749 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
750 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
751 | vtotal /= 2; | |
752 | ||
753 | if (IS_GEN2(dev)) | |
75aa3f63 | 754 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
a225f079 | 755 | else |
75aa3f63 | 756 | position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
a225f079 | 757 | |
41b578fb JB |
758 | /* |
759 | * On HSW, the DSL reg (0x70000) appears to return 0 if we | |
760 | * read it just before the start of vblank. So try it again | |
761 | * so we don't accidentally end up spanning a vblank frame | |
762 | * increment, causing the pipe_update_end() code to squak at us. | |
763 | * | |
764 | * The nature of this problem means we can't simply check the ISR | |
765 | * bit and return the vblank start value; nor can we use the scanline | |
766 | * debug register in the transcoder as it appears to have the same | |
767 | * problem. We may need to extend this to include other platforms, | |
768 | * but so far testing only shows the problem on HSW. | |
769 | */ | |
b2916819 | 770 | if (HAS_DDI(dev) && !position) { |
41b578fb JB |
771 | int i, temp; |
772 | ||
773 | for (i = 0; i < 100; i++) { | |
774 | udelay(1); | |
775 | temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & | |
776 | DSL_LINEMASK_GEN3; | |
777 | if (temp != position) { | |
778 | position = temp; | |
779 | break; | |
780 | } | |
781 | } | |
782 | } | |
783 | ||
a225f079 | 784 | /* |
80715b2f VS |
785 | * See update_scanline_offset() for the details on the |
786 | * scanline_offset adjustment. | |
a225f079 | 787 | */ |
80715b2f | 788 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
789 | } |
790 | ||
88e72717 | 791 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
abca9e45 | 792 | unsigned int flags, int *vpos, int *hpos, |
3bb403bf VS |
793 | ktime_t *stime, ktime_t *etime, |
794 | const struct drm_display_mode *mode) | |
0af7e4df | 795 | { |
c2baf4b7 VS |
796 | struct drm_i915_private *dev_priv = dev->dev_private; |
797 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
798 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3aa18df8 | 799 | int position; |
78e8fc6b | 800 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
801 | bool in_vbl = true; |
802 | int ret = 0; | |
ad3543ed | 803 | unsigned long irqflags; |
0af7e4df | 804 | |
fc467a22 | 805 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 806 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 807 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
808 | return 0; |
809 | } | |
810 | ||
c2baf4b7 | 811 | htotal = mode->crtc_htotal; |
78e8fc6b | 812 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
813 | vtotal = mode->crtc_vtotal; |
814 | vbl_start = mode->crtc_vblank_start; | |
815 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 816 | |
d31faf65 VS |
817 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
818 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
819 | vbl_end /= 2; | |
820 | vtotal /= 2; | |
821 | } | |
822 | ||
c2baf4b7 VS |
823 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
824 | ||
ad3543ed MK |
825 | /* |
826 | * Lock uncore.lock, as we will do multiple timing critical raw | |
827 | * register reads, potentially with preemption disabled, so the | |
828 | * following code must not block on uncore.lock. | |
829 | */ | |
830 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 831 | |
ad3543ed MK |
832 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
833 | ||
834 | /* Get optional system timestamp before query. */ | |
835 | if (stime) | |
836 | *stime = ktime_get(); | |
837 | ||
7c06b08a | 838 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
839 | /* No obvious pixelcount register. Only query vertical |
840 | * scanout position from Display scan line register. | |
841 | */ | |
a225f079 | 842 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
843 | } else { |
844 | /* Have access to pixelcount since start of frame. | |
845 | * We can split this into vertical and horizontal | |
846 | * scanout position. | |
847 | */ | |
75aa3f63 | 848 | position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 849 | |
3aa18df8 VS |
850 | /* convert to pixel counts */ |
851 | vbl_start *= htotal; | |
852 | vbl_end *= htotal; | |
853 | vtotal *= htotal; | |
78e8fc6b | 854 | |
7e78f1cb VS |
855 | /* |
856 | * In interlaced modes, the pixel counter counts all pixels, | |
857 | * so one field will have htotal more pixels. In order to avoid | |
858 | * the reported position from jumping backwards when the pixel | |
859 | * counter is beyond the length of the shorter field, just | |
860 | * clamp the position the length of the shorter field. This | |
861 | * matches how the scanline counter based position works since | |
862 | * the scanline counter doesn't count the two half lines. | |
863 | */ | |
864 | if (position >= vtotal) | |
865 | position = vtotal - 1; | |
866 | ||
78e8fc6b VS |
867 | /* |
868 | * Start of vblank interrupt is triggered at start of hsync, | |
869 | * just prior to the first active line of vblank. However we | |
870 | * consider lines to start at the leading edge of horizontal | |
871 | * active. So, should we get here before we've crossed into | |
872 | * the horizontal active of the first line in vblank, we would | |
873 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
874 | * always add htotal-hsync_start to the current pixel position. | |
875 | */ | |
876 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
877 | } |
878 | ||
ad3543ed MK |
879 | /* Get optional system timestamp after query. */ |
880 | if (etime) | |
881 | *etime = ktime_get(); | |
882 | ||
883 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
884 | ||
885 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
886 | ||
3aa18df8 VS |
887 | in_vbl = position >= vbl_start && position < vbl_end; |
888 | ||
889 | /* | |
890 | * While in vblank, position will be negative | |
891 | * counting up towards 0 at vbl_end. And outside | |
892 | * vblank, position will be positive counting | |
893 | * up since vbl_end. | |
894 | */ | |
895 | if (position >= vbl_start) | |
896 | position -= vbl_end; | |
897 | else | |
898 | position += vtotal - vbl_end; | |
0af7e4df | 899 | |
7c06b08a | 900 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
901 | *vpos = position; |
902 | *hpos = 0; | |
903 | } else { | |
904 | *vpos = position / htotal; | |
905 | *hpos = position - (*vpos * htotal); | |
906 | } | |
0af7e4df | 907 | |
0af7e4df MK |
908 | /* In vblank? */ |
909 | if (in_vbl) | |
3d3cbd84 | 910 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
911 | |
912 | return ret; | |
913 | } | |
914 | ||
a225f079 VS |
915 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
916 | { | |
917 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
918 | unsigned long irqflags; | |
919 | int position; | |
920 | ||
921 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
922 | position = __intel_get_crtc_scanline(crtc); | |
923 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
924 | ||
925 | return position; | |
926 | } | |
927 | ||
88e72717 | 928 | static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, |
0af7e4df MK |
929 | int *max_error, |
930 | struct timeval *vblank_time, | |
931 | unsigned flags) | |
932 | { | |
4041b853 | 933 | struct drm_crtc *crtc; |
0af7e4df | 934 | |
88e72717 TR |
935 | if (pipe >= INTEL_INFO(dev)->num_pipes) { |
936 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
0af7e4df MK |
937 | return -EINVAL; |
938 | } | |
939 | ||
940 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
941 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
942 | if (crtc == NULL) { | |
88e72717 | 943 | DRM_ERROR("Invalid crtc %u\n", pipe); |
4041b853 CW |
944 | return -EINVAL; |
945 | } | |
946 | ||
fc467a22 | 947 | if (!crtc->hwmode.crtc_clock) { |
88e72717 | 948 | DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); |
4041b853 CW |
949 | return -EBUSY; |
950 | } | |
0af7e4df MK |
951 | |
952 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
953 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
954 | vblank_time, flags, | |
fc467a22 | 955 | &crtc->hwmode); |
0af7e4df MK |
956 | } |
957 | ||
d0ecd7e2 | 958 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 959 | { |
2d1013dd | 960 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 961 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 962 | u8 new_delay; |
9270388e | 963 | |
d0ecd7e2 | 964 | spin_lock(&mchdev_lock); |
f97108d1 | 965 | |
73edd18f DV |
966 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
967 | ||
20e4d407 | 968 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 969 | |
7648fa99 | 970 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
971 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
972 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
973 | max_avg = I915_READ(RCBMAXAVG); |
974 | min_avg = I915_READ(RCBMINAVG); | |
975 | ||
976 | /* Handle RCS change request from hw */ | |
b5b72e89 | 977 | if (busy_up > max_avg) { |
20e4d407 DV |
978 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
979 | new_delay = dev_priv->ips.cur_delay - 1; | |
980 | if (new_delay < dev_priv->ips.max_delay) | |
981 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 982 | } else if (busy_down < min_avg) { |
20e4d407 DV |
983 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
984 | new_delay = dev_priv->ips.cur_delay + 1; | |
985 | if (new_delay > dev_priv->ips.min_delay) | |
986 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
987 | } |
988 | ||
7648fa99 | 989 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 990 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 991 | |
d0ecd7e2 | 992 | spin_unlock(&mchdev_lock); |
9270388e | 993 | |
f97108d1 JB |
994 | return; |
995 | } | |
996 | ||
0bc40be8 | 997 | static void notify_ring(struct intel_engine_cs *engine) |
549f7365 | 998 | { |
117897f4 | 999 | if (!intel_engine_initialized(engine)) |
475553de CW |
1000 | return; |
1001 | ||
0bc40be8 | 1002 | trace_i915_gem_request_notify(engine); |
12471ba8 | 1003 | engine->user_interrupts++; |
9862e600 | 1004 | |
0bc40be8 | 1005 | wake_up_all(&engine->irq_queue); |
549f7365 CW |
1006 | } |
1007 | ||
43cf3bf0 CW |
1008 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
1009 | struct intel_rps_ei *ei) | |
31685c25 | 1010 | { |
43cf3bf0 CW |
1011 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
1012 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
1013 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
1014 | } | |
31685c25 | 1015 | |
43cf3bf0 CW |
1016 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
1017 | const struct intel_rps_ei *old, | |
1018 | const struct intel_rps_ei *now, | |
1019 | int threshold) | |
1020 | { | |
1021 | u64 time, c0; | |
7bad74d5 | 1022 | unsigned int mul = 100; |
31685c25 | 1023 | |
43cf3bf0 CW |
1024 | if (old->cz_clock == 0) |
1025 | return false; | |
31685c25 | 1026 | |
7bad74d5 VS |
1027 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) |
1028 | mul <<= 8; | |
1029 | ||
43cf3bf0 | 1030 | time = now->cz_clock - old->cz_clock; |
7bad74d5 | 1031 | time *= threshold * dev_priv->czclk_freq; |
31685c25 | 1032 | |
43cf3bf0 CW |
1033 | /* Workload can be split between render + media, e.g. SwapBuffers |
1034 | * being blitted in X after being rendered in mesa. To account for | |
1035 | * this we need to combine both engines into our activity counter. | |
31685c25 | 1036 | */ |
43cf3bf0 CW |
1037 | c0 = now->render_c0 - old->render_c0; |
1038 | c0 += now->media_c0 - old->media_c0; | |
7bad74d5 | 1039 | c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC; |
31685c25 | 1040 | |
43cf3bf0 | 1041 | return c0 >= time; |
31685c25 D |
1042 | } |
1043 | ||
43cf3bf0 | 1044 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 1045 | { |
43cf3bf0 CW |
1046 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
1047 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 1048 | } |
31685c25 | 1049 | |
43cf3bf0 CW |
1050 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1051 | { | |
1052 | struct intel_rps_ei now; | |
1053 | u32 events = 0; | |
31685c25 | 1054 | |
6f4b12f8 | 1055 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1056 | return 0; |
31685c25 | 1057 | |
43cf3bf0 CW |
1058 | vlv_c0_read(dev_priv, &now); |
1059 | if (now.cz_clock == 0) | |
1060 | return 0; | |
31685c25 | 1061 | |
43cf3bf0 CW |
1062 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1063 | if (!vlv_c0_above(dev_priv, | |
1064 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1065 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1066 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1067 | dev_priv->rps.down_ei = now; | |
1068 | } | |
31685c25 | 1069 | |
43cf3bf0 CW |
1070 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1071 | if (vlv_c0_above(dev_priv, | |
1072 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1073 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1074 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1075 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1076 | } |
1077 | ||
43cf3bf0 | 1078 | return events; |
31685c25 D |
1079 | } |
1080 | ||
f5a4c67d CW |
1081 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1082 | { | |
e2f80391 | 1083 | struct intel_engine_cs *engine; |
f5a4c67d | 1084 | |
b4ac5afc | 1085 | for_each_engine(engine, dev_priv) |
e2f80391 | 1086 | if (engine->irq_refcount) |
f5a4c67d CW |
1087 | return true; |
1088 | ||
1089 | return false; | |
1090 | } | |
1091 | ||
4912d041 | 1092 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1093 | { |
2d1013dd JN |
1094 | struct drm_i915_private *dev_priv = |
1095 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1096 | bool client_boost; |
1097 | int new_delay, adj, min, max; | |
edbfdb45 | 1098 | u32 pm_iir; |
4912d041 | 1099 | |
59cdb63d | 1100 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1101 | /* Speed up work cancelation during disabling rps interrupts. */ |
1102 | if (!dev_priv->rps.interrupts_enabled) { | |
1103 | spin_unlock_irq(&dev_priv->irq_lock); | |
1104 | return; | |
1105 | } | |
1f814dac ID |
1106 | |
1107 | /* | |
1108 | * The RPS work is synced during runtime suspend, we don't require a | |
1109 | * wakeref. TODO: instead of disabling the asserts make sure that we | |
1110 | * always hold an RPM reference while the work is running. | |
1111 | */ | |
1112 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
1113 | ||
c6a828d3 DV |
1114 | pm_iir = dev_priv->rps.pm_iir; |
1115 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1116 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1117 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1118 | client_boost = dev_priv->rps.client_boost; |
1119 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1120 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1121 | |
60611c13 | 1122 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1123 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1124 | |
8d3afd7d | 1125 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
1f814dac | 1126 | goto out; |
3b8d8d91 | 1127 | |
4fc688ce | 1128 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1129 | |
43cf3bf0 CW |
1130 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1131 | ||
dd75fdc8 | 1132 | adj = dev_priv->rps.last_adj; |
edcf284b | 1133 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1134 | min = dev_priv->rps.min_freq_softlimit; |
1135 | max = dev_priv->rps.max_freq_softlimit; | |
1136 | ||
1137 | if (client_boost) { | |
1138 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1139 | adj = 0; | |
1140 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1141 | if (adj > 0) |
1142 | adj *= 2; | |
edcf284b CW |
1143 | else /* CHV needs even encode values */ |
1144 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1145 | /* |
1146 | * For better performance, jump directly | |
1147 | * to RPe if we're below it. | |
1148 | */ | |
edcf284b | 1149 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1150 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1151 | adj = 0; |
1152 | } | |
f5a4c67d CW |
1153 | } else if (any_waiters(dev_priv)) { |
1154 | adj = 0; | |
dd75fdc8 | 1155 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1156 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1157 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1158 | else |
b39fb297 | 1159 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1160 | adj = 0; |
1161 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1162 | if (adj < 0) | |
1163 | adj *= 2; | |
edcf284b CW |
1164 | else /* CHV needs even encode values */ |
1165 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1166 | } else { /* unknown event */ |
edcf284b | 1167 | adj = 0; |
dd75fdc8 | 1168 | } |
3b8d8d91 | 1169 | |
edcf284b CW |
1170 | dev_priv->rps.last_adj = adj; |
1171 | ||
79249636 BW |
1172 | /* sysfs frequency interfaces may have snuck in while servicing the |
1173 | * interrupt | |
1174 | */ | |
edcf284b | 1175 | new_delay += adj; |
8d3afd7d | 1176 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1177 | |
ffe02b40 | 1178 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1179 | |
4fc688ce | 1180 | mutex_unlock(&dev_priv->rps.hw_lock); |
1f814dac ID |
1181 | out: |
1182 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3b8d8d91 JB |
1183 | } |
1184 | ||
e3689190 BW |
1185 | |
1186 | /** | |
1187 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1188 | * occurred. | |
1189 | * @work: workqueue struct | |
1190 | * | |
1191 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1192 | * this event, userspace should try to remap the bad rows since statistically | |
1193 | * it is likely the same row is more likely to go bad again. | |
1194 | */ | |
1195 | static void ivybridge_parity_work(struct work_struct *work) | |
1196 | { | |
2d1013dd JN |
1197 | struct drm_i915_private *dev_priv = |
1198 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1199 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1200 | char *parity_event[6]; |
e3689190 | 1201 | uint32_t misccpctl; |
35a85ac6 | 1202 | uint8_t slice = 0; |
e3689190 BW |
1203 | |
1204 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1205 | * In order to prevent a get/put style interface, acquire struct mutex | |
1206 | * any time we access those registers. | |
1207 | */ | |
1208 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1209 | ||
35a85ac6 BW |
1210 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1211 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1212 | goto out; | |
1213 | ||
e3689190 BW |
1214 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1215 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1216 | POSTING_READ(GEN7_MISCCPCTL); | |
1217 | ||
35a85ac6 | 1218 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
f0f59a00 | 1219 | i915_reg_t reg; |
e3689190 | 1220 | |
35a85ac6 | 1221 | slice--; |
2d1fe073 | 1222 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv))) |
35a85ac6 | 1223 | break; |
e3689190 | 1224 | |
35a85ac6 | 1225 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1226 | |
6fa1c5f1 | 1227 | reg = GEN7_L3CDERRST1(slice); |
e3689190 | 1228 | |
35a85ac6 BW |
1229 | error_status = I915_READ(reg); |
1230 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1231 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1232 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1233 | ||
1234 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1235 | POSTING_READ(reg); | |
1236 | ||
1237 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1238 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1239 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1240 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1241 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1242 | parity_event[5] = NULL; | |
1243 | ||
5bdebb18 | 1244 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1245 | KOBJ_CHANGE, parity_event); |
e3689190 | 1246 | |
35a85ac6 BW |
1247 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1248 | slice, row, bank, subbank); | |
e3689190 | 1249 | |
35a85ac6 BW |
1250 | kfree(parity_event[4]); |
1251 | kfree(parity_event[3]); | |
1252 | kfree(parity_event[2]); | |
1253 | kfree(parity_event[1]); | |
1254 | } | |
e3689190 | 1255 | |
35a85ac6 | 1256 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1257 | |
35a85ac6 BW |
1258 | out: |
1259 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1260 | spin_lock_irq(&dev_priv->irq_lock); |
2d1fe073 | 1261 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
4cb21832 | 1262 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1263 | |
1264 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1265 | } |
1266 | ||
261e40b8 VS |
1267 | static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv, |
1268 | u32 iir) | |
e3689190 | 1269 | { |
261e40b8 | 1270 | if (!HAS_L3_DPF(dev_priv)) |
e3689190 BW |
1271 | return; |
1272 | ||
d0ecd7e2 | 1273 | spin_lock(&dev_priv->irq_lock); |
261e40b8 | 1274 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv)); |
d0ecd7e2 | 1275 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1276 | |
261e40b8 | 1277 | iir &= GT_PARITY_ERROR(dev_priv); |
35a85ac6 BW |
1278 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) |
1279 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1280 | ||
1281 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1282 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1283 | ||
a4da4fa4 | 1284 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1285 | } |
1286 | ||
261e40b8 | 1287 | static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv, |
f1af8fc1 PZ |
1288 | u32 gt_iir) |
1289 | { | |
1290 | if (gt_iir & | |
1291 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1292 | notify_ring(&dev_priv->engine[RCS]); |
f1af8fc1 | 1293 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
4a570db5 | 1294 | notify_ring(&dev_priv->engine[VCS]); |
f1af8fc1 PZ |
1295 | } |
1296 | ||
261e40b8 | 1297 | static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, |
e7b4c6b1 DV |
1298 | u32 gt_iir) |
1299 | { | |
1300 | ||
cc609d5d BW |
1301 | if (gt_iir & |
1302 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
4a570db5 | 1303 | notify_ring(&dev_priv->engine[RCS]); |
cc609d5d | 1304 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
4a570db5 | 1305 | notify_ring(&dev_priv->engine[VCS]); |
cc609d5d | 1306 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
4a570db5 | 1307 | notify_ring(&dev_priv->engine[BCS]); |
e7b4c6b1 | 1308 | |
cc609d5d BW |
1309 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1310 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1311 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1312 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1313 | |
261e40b8 VS |
1314 | if (gt_iir & GT_PARITY_ERROR(dev_priv)) |
1315 | ivybridge_parity_error_irq_handler(dev_priv, gt_iir); | |
e7b4c6b1 DV |
1316 | } |
1317 | ||
fbcc1a0c | 1318 | static __always_inline void |
0bc40be8 | 1319 | gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) |
fbcc1a0c NH |
1320 | { |
1321 | if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) | |
0bc40be8 | 1322 | notify_ring(engine); |
fbcc1a0c | 1323 | if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) |
27af5eea | 1324 | tasklet_schedule(&engine->irq_tasklet); |
fbcc1a0c NH |
1325 | } |
1326 | ||
e30e251a VS |
1327 | static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, |
1328 | u32 master_ctl, | |
1329 | u32 gt_iir[4]) | |
abd58f01 | 1330 | { |
abd58f01 BW |
1331 | irqreturn_t ret = IRQ_NONE; |
1332 | ||
1333 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
e30e251a VS |
1334 | gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); |
1335 | if (gt_iir[0]) { | |
1336 | I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]); | |
abd58f01 | 1337 | ret = IRQ_HANDLED; |
abd58f01 BW |
1338 | } else |
1339 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1340 | } | |
1341 | ||
85f9b5f9 | 1342 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
e30e251a VS |
1343 | gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); |
1344 | if (gt_iir[1]) { | |
1345 | I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]); | |
abd58f01 | 1346 | ret = IRQ_HANDLED; |
0961021a | 1347 | } else |
abd58f01 | 1348 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1349 | } |
1350 | ||
abd58f01 | 1351 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
e30e251a VS |
1352 | gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); |
1353 | if (gt_iir[3]) { | |
1354 | I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]); | |
abd58f01 | 1355 | ret = IRQ_HANDLED; |
abd58f01 BW |
1356 | } else |
1357 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1358 | } | |
1359 | ||
0961021a | 1360 | if (master_ctl & GEN8_GT_PM_IRQ) { |
e30e251a VS |
1361 | gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); |
1362 | if (gt_iir[2] & dev_priv->pm_rps_events) { | |
cb0d205e | 1363 | I915_WRITE_FW(GEN8_GT_IIR(2), |
e30e251a | 1364 | gt_iir[2] & dev_priv->pm_rps_events); |
38cc46d7 | 1365 | ret = IRQ_HANDLED; |
0961021a BW |
1366 | } else |
1367 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1368 | } | |
1369 | ||
abd58f01 BW |
1370 | return ret; |
1371 | } | |
1372 | ||
e30e251a VS |
1373 | static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
1374 | u32 gt_iir[4]) | |
1375 | { | |
1376 | if (gt_iir[0]) { | |
1377 | gen8_cs_irq_handler(&dev_priv->engine[RCS], | |
1378 | gt_iir[0], GEN8_RCS_IRQ_SHIFT); | |
1379 | gen8_cs_irq_handler(&dev_priv->engine[BCS], | |
1380 | gt_iir[0], GEN8_BCS_IRQ_SHIFT); | |
1381 | } | |
1382 | ||
1383 | if (gt_iir[1]) { | |
1384 | gen8_cs_irq_handler(&dev_priv->engine[VCS], | |
1385 | gt_iir[1], GEN8_VCS1_IRQ_SHIFT); | |
1386 | gen8_cs_irq_handler(&dev_priv->engine[VCS2], | |
1387 | gt_iir[1], GEN8_VCS2_IRQ_SHIFT); | |
1388 | } | |
1389 | ||
1390 | if (gt_iir[3]) | |
1391 | gen8_cs_irq_handler(&dev_priv->engine[VECS], | |
1392 | gt_iir[3], GEN8_VECS_IRQ_SHIFT); | |
1393 | ||
1394 | if (gt_iir[2] & dev_priv->pm_rps_events) | |
1395 | gen6_rps_irq_handler(dev_priv, gt_iir[2]); | |
1396 | } | |
1397 | ||
63c88d22 ID |
1398 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1399 | { | |
1400 | switch (port) { | |
1401 | case PORT_A: | |
195baa06 | 1402 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1403 | case PORT_B: |
1404 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1405 | case PORT_C: | |
1406 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1407 | default: |
1408 | return false; | |
1409 | } | |
1410 | } | |
1411 | ||
6dbf30ce VS |
1412 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1413 | { | |
1414 | switch (port) { | |
1415 | case PORT_E: | |
1416 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1417 | default: | |
1418 | return false; | |
1419 | } | |
1420 | } | |
1421 | ||
74c0b395 VS |
1422 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1423 | { | |
1424 | switch (port) { | |
1425 | case PORT_A: | |
1426 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1427 | case PORT_B: | |
1428 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1429 | case PORT_C: | |
1430 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1431 | case PORT_D: | |
1432 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1433 | default: | |
1434 | return false; | |
1435 | } | |
1436 | } | |
1437 | ||
e4ce95aa VS |
1438 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1439 | { | |
1440 | switch (port) { | |
1441 | case PORT_A: | |
1442 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1443 | default: | |
1444 | return false; | |
1445 | } | |
1446 | } | |
1447 | ||
676574df | 1448 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1449 | { |
1450 | switch (port) { | |
13cf5504 | 1451 | case PORT_B: |
676574df | 1452 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1453 | case PORT_C: |
676574df | 1454 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1455 | case PORT_D: |
676574df JN |
1456 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1457 | default: | |
1458 | return false; | |
13cf5504 DA |
1459 | } |
1460 | } | |
1461 | ||
676574df | 1462 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1463 | { |
1464 | switch (port) { | |
13cf5504 | 1465 | case PORT_B: |
676574df | 1466 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1467 | case PORT_C: |
676574df | 1468 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1469 | case PORT_D: |
676574df JN |
1470 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1471 | default: | |
1472 | return false; | |
13cf5504 DA |
1473 | } |
1474 | } | |
1475 | ||
42db67d6 VS |
1476 | /* |
1477 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1478 | * This can be called multiple times with the same masks to accumulate | |
1479 | * hotplug detection results from several registers. | |
1480 | * | |
1481 | * Note that the caller is expected to zero out the masks initially. | |
1482 | */ | |
fd63e2a9 | 1483 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1484 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1485 | const u32 hpd[HPD_NUM_PINS], |
1486 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1487 | { |
8c841e57 | 1488 | enum port port; |
676574df JN |
1489 | int i; |
1490 | ||
676574df | 1491 | for_each_hpd_pin(i) { |
8c841e57 JN |
1492 | if ((hpd[i] & hotplug_trigger) == 0) |
1493 | continue; | |
676574df | 1494 | |
8c841e57 JN |
1495 | *pin_mask |= BIT(i); |
1496 | ||
cc24fcdc ID |
1497 | if (!intel_hpd_pin_to_port(i, &port)) |
1498 | continue; | |
1499 | ||
fd63e2a9 | 1500 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1501 | *long_mask |= BIT(i); |
676574df JN |
1502 | } |
1503 | ||
1504 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1505 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1506 | ||
1507 | } | |
1508 | ||
515ac2bb DV |
1509 | static void gmbus_irq_handler(struct drm_device *dev) |
1510 | { | |
2d1013dd | 1511 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1512 | |
28c70f16 | 1513 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1514 | } |
1515 | ||
ce99c256 DV |
1516 | static void dp_aux_irq_handler(struct drm_device *dev) |
1517 | { | |
2d1013dd | 1518 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1519 | |
9ee32fea | 1520 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1521 | } |
1522 | ||
8bf1e9f1 | 1523 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1524 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1525 | uint32_t crc0, uint32_t crc1, | |
1526 | uint32_t crc2, uint32_t crc3, | |
1527 | uint32_t crc4) | |
8bf1e9f1 SH |
1528 | { |
1529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1530 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1531 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1532 | int head, tail; |
b2c88f5b | 1533 | |
d538bbdf DL |
1534 | spin_lock(&pipe_crc->lock); |
1535 | ||
0c912c79 | 1536 | if (!pipe_crc->entries) { |
d538bbdf | 1537 | spin_unlock(&pipe_crc->lock); |
34273620 | 1538 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1539 | return; |
1540 | } | |
1541 | ||
d538bbdf DL |
1542 | head = pipe_crc->head; |
1543 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1544 | |
1545 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1546 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1547 | DRM_ERROR("CRC buffer overflowing\n"); |
1548 | return; | |
1549 | } | |
1550 | ||
1551 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1552 | |
8bc5e955 | 1553 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1554 | entry->crc[0] = crc0; |
1555 | entry->crc[1] = crc1; | |
1556 | entry->crc[2] = crc2; | |
1557 | entry->crc[3] = crc3; | |
1558 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1559 | |
1560 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1561 | pipe_crc->head = head; |
1562 | ||
1563 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1564 | |
1565 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1566 | } |
277de95e DV |
1567 | #else |
1568 | static inline void | |
1569 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1570 | uint32_t crc0, uint32_t crc1, | |
1571 | uint32_t crc2, uint32_t crc3, | |
1572 | uint32_t crc4) {} | |
1573 | #endif | |
1574 | ||
eba94eb9 | 1575 | |
277de95e | 1576 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1577 | { |
1578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1579 | ||
277de95e DV |
1580 | display_pipe_crc_irq_handler(dev, pipe, |
1581 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1582 | 0, 0, 0, 0); | |
5a69b89f DV |
1583 | } |
1584 | ||
277de95e | 1585 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1586 | { |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | ||
277de95e DV |
1589 | display_pipe_crc_irq_handler(dev, pipe, |
1590 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1591 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1592 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1593 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1594 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1595 | } |
5b3a856b | 1596 | |
277de95e | 1597 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1598 | { |
1599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1600 | uint32_t res1, res2; |
1601 | ||
1602 | if (INTEL_INFO(dev)->gen >= 3) | |
1603 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1604 | else | |
1605 | res1 = 0; | |
1606 | ||
1607 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1608 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1609 | else | |
1610 | res2 = 0; | |
5b3a856b | 1611 | |
277de95e DV |
1612 | display_pipe_crc_irq_handler(dev, pipe, |
1613 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1614 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1615 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1616 | res1, res2); | |
5b3a856b | 1617 | } |
8bf1e9f1 | 1618 | |
1403c0d4 PZ |
1619 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1620 | * IMR bits until the work is done. Other interrupts can be processed without | |
1621 | * the work queue. */ | |
1622 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1623 | { |
a6706b45 | 1624 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1625 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1626 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1627 | if (dev_priv->rps.interrupts_enabled) { |
1628 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1629 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1630 | } | |
59cdb63d | 1631 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1632 | } |
baf02a1f | 1633 | |
c9a9a268 ID |
1634 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1635 | return; | |
1636 | ||
2d1fe073 | 1637 | if (HAS_VEBOX(dev_priv)) { |
1403c0d4 | 1638 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) |
4a570db5 | 1639 | notify_ring(&dev_priv->engine[VECS]); |
12638c57 | 1640 | |
aaecdf61 DV |
1641 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1642 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1643 | } |
baf02a1f BW |
1644 | } |
1645 | ||
8d7849db VS |
1646 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1647 | { | |
8d7849db VS |
1648 | if (!drm_handle_vblank(dev, pipe)) |
1649 | return false; | |
1650 | ||
8d7849db VS |
1651 | return true; |
1652 | } | |
1653 | ||
2ecb8ca4 VS |
1654 | static void valleyview_pipestat_irq_ack(struct drm_device *dev, u32 iir, |
1655 | u32 pipe_stats[I915_MAX_PIPES]) | |
c1874ed7 ID |
1656 | { |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1874ed7 ID |
1658 | int pipe; |
1659 | ||
58ead0d7 | 1660 | spin_lock(&dev_priv->irq_lock); |
1ca993d2 VS |
1661 | |
1662 | if (!dev_priv->display_irqs_enabled) { | |
1663 | spin_unlock(&dev_priv->irq_lock); | |
1664 | return; | |
1665 | } | |
1666 | ||
055e393f | 1667 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 1668 | i915_reg_t reg; |
bbb5eebf | 1669 | u32 mask, iir_bit = 0; |
91d181dd | 1670 | |
bbb5eebf DV |
1671 | /* |
1672 | * PIPESTAT bits get signalled even when the interrupt is | |
1673 | * disabled with the mask bits, and some of the status bits do | |
1674 | * not generate interrupts at all (like the underrun bit). Hence | |
1675 | * we need to be careful that we only handle what we want to | |
1676 | * handle. | |
1677 | */ | |
0f239f4c DV |
1678 | |
1679 | /* fifo underruns are filterered in the underrun handler. */ | |
1680 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1681 | |
1682 | switch (pipe) { | |
1683 | case PIPE_A: | |
1684 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1685 | break; | |
1686 | case PIPE_B: | |
1687 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1688 | break; | |
3278f67f VS |
1689 | case PIPE_C: |
1690 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1691 | break; | |
bbb5eebf DV |
1692 | } |
1693 | if (iir & iir_bit) | |
1694 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1695 | ||
1696 | if (!mask) | |
91d181dd ID |
1697 | continue; |
1698 | ||
1699 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1700 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1701 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1702 | |
1703 | /* | |
1704 | * Clear the PIPE*STAT regs before the IIR | |
1705 | */ | |
91d181dd ID |
1706 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1707 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1708 | I915_WRITE(reg, pipe_stats[pipe]); |
1709 | } | |
58ead0d7 | 1710 | spin_unlock(&dev_priv->irq_lock); |
2ecb8ca4 VS |
1711 | } |
1712 | ||
1713 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, | |
1714 | u32 pipe_stats[I915_MAX_PIPES]) | |
1715 | { | |
1716 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1717 | enum pipe pipe; | |
c1874ed7 | 1718 | |
055e393f | 1719 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1720 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1721 | intel_pipe_handle_vblank(dev, pipe)) | |
1722 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1723 | |
579a9b0e | 1724 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1725 | intel_prepare_page_flip(dev, pipe); |
1726 | intel_finish_page_flip(dev, pipe); | |
1727 | } | |
1728 | ||
1729 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1730 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1731 | ||
1f7247c0 DV |
1732 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1733 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1734 | } |
1735 | ||
1736 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1737 | gmbus_irq_handler(dev); | |
1738 | } | |
1739 | ||
1ae3c34c | 1740 | static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) |
16c6c56b | 1741 | { |
16c6c56b VS |
1742 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
1743 | ||
1ae3c34c VS |
1744 | if (hotplug_status) |
1745 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
16c6c56b | 1746 | |
1ae3c34c VS |
1747 | return hotplug_status; |
1748 | } | |
1749 | ||
1750 | static void i9xx_hpd_irq_handler(struct drm_device *dev, | |
1751 | u32 hotplug_status) | |
1752 | { | |
1753 | u32 pin_mask = 0, long_mask = 0; | |
16c6c56b | 1754 | |
666a4537 | 1755 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
0d2e4297 | 1756 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; |
16c6c56b | 1757 | |
58f2cf24 VS |
1758 | if (hotplug_trigger) { |
1759 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1760 | hotplug_trigger, hpd_status_g4x, | |
1761 | i9xx_port_hotplug_long_detect); | |
1762 | ||
1763 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1764 | } | |
369712e8 JN |
1765 | |
1766 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1767 | dp_aux_irq_handler(dev); | |
0d2e4297 JN |
1768 | } else { |
1769 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1770 | |
58f2cf24 VS |
1771 | if (hotplug_trigger) { |
1772 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
44cc6c08 | 1773 | hotplug_trigger, hpd_status_i915, |
58f2cf24 | 1774 | i9xx_port_hotplug_long_detect); |
58f2cf24 VS |
1775 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
1776 | } | |
3ff60f89 | 1777 | } |
16c6c56b VS |
1778 | } |
1779 | ||
ff1f525e | 1780 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1781 | { |
45a83f84 | 1782 | struct drm_device *dev = arg; |
2d1013dd | 1783 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 1784 | irqreturn_t ret = IRQ_NONE; |
7e231dbe | 1785 | |
2dd2a883 ID |
1786 | if (!intel_irqs_enabled(dev_priv)) |
1787 | return IRQ_NONE; | |
1788 | ||
1f814dac ID |
1789 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1790 | disable_rpm_wakeref_asserts(dev_priv); | |
1791 | ||
1e1cace9 | 1792 | do { |
6e814800 | 1793 | u32 iir, gt_iir, pm_iir; |
2ecb8ca4 | 1794 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1795 | u32 hotplug_status = 0; |
a5e485a9 | 1796 | u32 ier = 0; |
3ff60f89 | 1797 | |
7e231dbe JB |
1798 | gt_iir = I915_READ(GTIIR); |
1799 | pm_iir = I915_READ(GEN6_PMIIR); | |
3ff60f89 | 1800 | iir = I915_READ(VLV_IIR); |
7e231dbe JB |
1801 | |
1802 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1e1cace9 | 1803 | break; |
7e231dbe JB |
1804 | |
1805 | ret = IRQ_HANDLED; | |
1806 | ||
a5e485a9 VS |
1807 | /* |
1808 | * Theory on interrupt generation, based on empirical evidence: | |
1809 | * | |
1810 | * x = ((VLV_IIR & VLV_IER) || | |
1811 | * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) && | |
1812 | * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE))); | |
1813 | * | |
1814 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1815 | * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to | |
1816 | * guarantee the CPU interrupt will be raised again even if we | |
1817 | * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR | |
1818 | * bits this time around. | |
1819 | */ | |
4a0a0202 | 1820 | I915_WRITE(VLV_MASTER_IER, 0); |
a5e485a9 VS |
1821 | ier = I915_READ(VLV_IER); |
1822 | I915_WRITE(VLV_IER, 0); | |
4a0a0202 VS |
1823 | |
1824 | if (gt_iir) | |
1825 | I915_WRITE(GTIIR, gt_iir); | |
1826 | if (pm_iir) | |
1827 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1828 | ||
7ce4d1f2 | 1829 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1830 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1831 | |
3ff60f89 OM |
1832 | /* Call regardless, as some status bits might not be |
1833 | * signalled in iir */ | |
2ecb8ca4 | 1834 | valleyview_pipestat_irq_ack(dev, iir, pipe_stats); |
7ce4d1f2 VS |
1835 | |
1836 | /* | |
1837 | * VLV_IIR is single buffered, and reflects the level | |
1838 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1839 | */ | |
1840 | if (iir) | |
1841 | I915_WRITE(VLV_IIR, iir); | |
4a0a0202 | 1842 | |
a5e485a9 | 1843 | I915_WRITE(VLV_IER, ier); |
4a0a0202 VS |
1844 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
1845 | POSTING_READ(VLV_MASTER_IER); | |
1ae3c34c | 1846 | |
52894874 | 1847 | if (gt_iir) |
261e40b8 | 1848 | snb_gt_irq_handler(dev_priv, gt_iir); |
52894874 VS |
1849 | if (pm_iir) |
1850 | gen6_rps_irq_handler(dev_priv, pm_iir); | |
1851 | ||
1ae3c34c VS |
1852 | if (hotplug_status) |
1853 | i9xx_hpd_irq_handler(dev, hotplug_status); | |
2ecb8ca4 VS |
1854 | |
1855 | valleyview_pipestat_irq_handler(dev, pipe_stats); | |
1e1cace9 | 1856 | } while (0); |
7e231dbe | 1857 | |
1f814dac ID |
1858 | enable_rpm_wakeref_asserts(dev_priv); |
1859 | ||
7e231dbe JB |
1860 | return ret; |
1861 | } | |
1862 | ||
43f328d7 VS |
1863 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1864 | { | |
45a83f84 | 1865 | struct drm_device *dev = arg; |
43f328d7 | 1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
43f328d7 | 1867 | irqreturn_t ret = IRQ_NONE; |
43f328d7 | 1868 | |
2dd2a883 ID |
1869 | if (!intel_irqs_enabled(dev_priv)) |
1870 | return IRQ_NONE; | |
1871 | ||
1f814dac ID |
1872 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
1873 | disable_rpm_wakeref_asserts(dev_priv); | |
1874 | ||
579de73b | 1875 | do { |
6e814800 | 1876 | u32 master_ctl, iir; |
e30e251a | 1877 | u32 gt_iir[4] = {}; |
2ecb8ca4 | 1878 | u32 pipe_stats[I915_MAX_PIPES] = {}; |
1ae3c34c | 1879 | u32 hotplug_status = 0; |
a5e485a9 VS |
1880 | u32 ier = 0; |
1881 | ||
8e5fd599 VS |
1882 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; |
1883 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1884 | |
8e5fd599 VS |
1885 | if (master_ctl == 0 && iir == 0) |
1886 | break; | |
43f328d7 | 1887 | |
27b6c122 OM |
1888 | ret = IRQ_HANDLED; |
1889 | ||
a5e485a9 VS |
1890 | /* |
1891 | * Theory on interrupt generation, based on empirical evidence: | |
1892 | * | |
1893 | * x = ((VLV_IIR & VLV_IER) || | |
1894 | * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && | |
1895 | * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); | |
1896 | * | |
1897 | * A CPU interrupt will only be raised when 'x' has a 0->1 edge. | |
1898 | * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to | |
1899 | * guarantee the CPU interrupt will be raised again even if we | |
1900 | * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL | |
1901 | * bits this time around. | |
1902 | */ | |
8e5fd599 | 1903 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
a5e485a9 VS |
1904 | ier = I915_READ(VLV_IER); |
1905 | I915_WRITE(VLV_IER, 0); | |
43f328d7 | 1906 | |
e30e251a | 1907 | gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
43f328d7 | 1908 | |
7ce4d1f2 | 1909 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
1ae3c34c | 1910 | hotplug_status = i9xx_hpd_irq_ack(dev_priv); |
7ce4d1f2 | 1911 | |
27b6c122 OM |
1912 | /* Call regardless, as some status bits might not be |
1913 | * signalled in iir */ | |
2ecb8ca4 | 1914 | valleyview_pipestat_irq_ack(dev, iir, pipe_stats); |
43f328d7 | 1915 | |
7ce4d1f2 VS |
1916 | /* |
1917 | * VLV_IIR is single buffered, and reflects the level | |
1918 | * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. | |
1919 | */ | |
1920 | if (iir) | |
1921 | I915_WRITE(VLV_IIR, iir); | |
1922 | ||
a5e485a9 | 1923 | I915_WRITE(VLV_IER, ier); |
e5328c43 | 1924 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
8e5fd599 | 1925 | POSTING_READ(GEN8_MASTER_IRQ); |
1ae3c34c | 1926 | |
e30e251a VS |
1927 | gen8_gt_irq_handler(dev_priv, gt_iir); |
1928 | ||
1ae3c34c VS |
1929 | if (hotplug_status) |
1930 | i9xx_hpd_irq_handler(dev, hotplug_status); | |
2ecb8ca4 VS |
1931 | |
1932 | valleyview_pipestat_irq_handler(dev, pipe_stats); | |
579de73b | 1933 | } while (0); |
3278f67f | 1934 | |
1f814dac ID |
1935 | enable_rpm_wakeref_asserts(dev_priv); |
1936 | ||
43f328d7 VS |
1937 | return ret; |
1938 | } | |
1939 | ||
40e56410 VS |
1940 | static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
1941 | const u32 hpd[HPD_NUM_PINS]) | |
1942 | { | |
1943 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1944 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1945 | ||
6a39d7c9 JN |
1946 | /* |
1947 | * Somehow the PCH doesn't seem to really ack the interrupt to the CPU | |
1948 | * unless we touch the hotplug register, even if hotplug_trigger is | |
1949 | * zero. Not acking leads to "The master control interrupt lied (SDE)!" | |
1950 | * errors. | |
1951 | */ | |
40e56410 | 1952 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
6a39d7c9 JN |
1953 | if (!hotplug_trigger) { |
1954 | u32 mask = PORTA_HOTPLUG_STATUS_MASK | | |
1955 | PORTD_HOTPLUG_STATUS_MASK | | |
1956 | PORTC_HOTPLUG_STATUS_MASK | | |
1957 | PORTB_HOTPLUG_STATUS_MASK; | |
1958 | dig_hotplug_reg &= ~mask; | |
1959 | } | |
1960 | ||
40e56410 | 1961 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); |
6a39d7c9 JN |
1962 | if (!hotplug_trigger) |
1963 | return; | |
40e56410 VS |
1964 | |
1965 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1966 | dig_hotplug_reg, hpd, | |
1967 | pch_port_hotplug_long_detect); | |
1968 | ||
1969 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1970 | } | |
1971 | ||
23e81d69 | 1972 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1973 | { |
2d1013dd | 1974 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1975 | int pipe; |
b543fb04 | 1976 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1977 | |
6a39d7c9 | 1978 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
91d131d2 | 1979 | |
cfc33bf7 VS |
1980 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1981 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1982 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1983 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1984 | port_name(port)); |
1985 | } | |
776ad806 | 1986 | |
ce99c256 DV |
1987 | if (pch_iir & SDE_AUX_MASK) |
1988 | dp_aux_irq_handler(dev); | |
1989 | ||
776ad806 | 1990 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1991 | gmbus_irq_handler(dev); |
776ad806 JB |
1992 | |
1993 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1994 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1995 | ||
1996 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1997 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1998 | ||
1999 | if (pch_iir & SDE_POISON) | |
2000 | DRM_ERROR("PCH poison interrupt\n"); | |
2001 | ||
9db4a9c7 | 2002 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 2003 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
2004 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2005 | pipe_name(pipe), | |
2006 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
2007 | |
2008 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
2009 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
2010 | ||
2011 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
2012 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
2013 | ||
776ad806 | 2014 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 2015 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2016 | |
2017 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 2018 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2019 | } |
2020 | ||
2021 | static void ivb_err_int_handler(struct drm_device *dev) | |
2022 | { | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2024 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 2025 | enum pipe pipe; |
8664281b | 2026 | |
de032bf4 PZ |
2027 | if (err_int & ERR_INT_POISON) |
2028 | DRM_ERROR("Poison interrupt\n"); | |
2029 | ||
055e393f | 2030 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
2031 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
2032 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 2033 | |
5a69b89f DV |
2034 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
2035 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 2036 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 2037 | else |
277de95e | 2038 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
2039 | } |
2040 | } | |
8bf1e9f1 | 2041 | |
8664281b PZ |
2042 | I915_WRITE(GEN7_ERR_INT, err_int); |
2043 | } | |
2044 | ||
2045 | static void cpt_serr_int_handler(struct drm_device *dev) | |
2046 | { | |
2047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2048 | u32 serr_int = I915_READ(SERR_INT); | |
2049 | ||
de032bf4 PZ |
2050 | if (serr_int & SERR_INT_POISON) |
2051 | DRM_ERROR("PCH poison interrupt\n"); | |
2052 | ||
8664281b | 2053 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 2054 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
2055 | |
2056 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 2057 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
2058 | |
2059 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 2060 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
2061 | |
2062 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
2063 | } |
2064 | ||
23e81d69 AJ |
2065 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2066 | { | |
2d1013dd | 2067 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 2068 | int pipe; |
6dbf30ce | 2069 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 2070 | |
6a39d7c9 | 2071 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
91d131d2 | 2072 | |
cfc33bf7 VS |
2073 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
2074 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
2075 | SDE_AUDIO_POWER_SHIFT_CPT); | |
2076 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
2077 | port_name(port)); | |
2078 | } | |
23e81d69 AJ |
2079 | |
2080 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 2081 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
2082 | |
2083 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 2084 | gmbus_irq_handler(dev); |
23e81d69 AJ |
2085 | |
2086 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
2087 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
2088 | ||
2089 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
2090 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
2091 | ||
2092 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 2093 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
2094 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
2095 | pipe_name(pipe), | |
2096 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
2097 | |
2098 | if (pch_iir & SDE_ERROR_CPT) | |
2099 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
2100 | } |
2101 | ||
6dbf30ce VS |
2102 | static void spt_irq_handler(struct drm_device *dev, u32 pch_iir) |
2103 | { | |
2104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2105 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & | |
2106 | ~SDE_PORTE_HOTPLUG_SPT; | |
2107 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
2108 | u32 pin_mask = 0, long_mask = 0; | |
2109 | ||
2110 | if (hotplug_trigger) { | |
2111 | u32 dig_hotplug_reg; | |
2112 | ||
2113 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
2114 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
2115 | ||
2116 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2117 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 2118 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
2119 | } |
2120 | ||
2121 | if (hotplug2_trigger) { | |
2122 | u32 dig_hotplug_reg; | |
2123 | ||
2124 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
2125 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
2126 | ||
2127 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
2128 | dig_hotplug_reg, hpd_spt, | |
2129 | spt_port_hotplug2_long_detect); | |
2130 | } | |
2131 | ||
2132 | if (pin_mask) | |
2133 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2134 | ||
2135 | if (pch_iir & SDE_GMBUS_CPT) | |
2136 | gmbus_irq_handler(dev); | |
2137 | } | |
2138 | ||
40e56410 VS |
2139 | static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
2140 | const u32 hpd[HPD_NUM_PINS]) | |
2141 | { | |
2142 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2143 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
2144 | ||
2145 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
2146 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
2147 | ||
2148 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
2149 | dig_hotplug_reg, hpd, | |
2150 | ilk_port_hotplug_long_detect); | |
2151 | ||
2152 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
2153 | } | |
2154 | ||
c008bc6e PZ |
2155 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2156 | { | |
2157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 2158 | enum pipe pipe; |
e4ce95aa VS |
2159 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
2160 | ||
40e56410 VS |
2161 | if (hotplug_trigger) |
2162 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk); | |
c008bc6e PZ |
2163 | |
2164 | if (de_iir & DE_AUX_CHANNEL_A) | |
2165 | dp_aux_irq_handler(dev); | |
2166 | ||
2167 | if (de_iir & DE_GSE) | |
2168 | intel_opregion_asle_intr(dev); | |
2169 | ||
c008bc6e PZ |
2170 | if (de_iir & DE_POISON) |
2171 | DRM_ERROR("Poison interrupt\n"); | |
2172 | ||
055e393f | 2173 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2174 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2175 | intel_pipe_handle_vblank(dev, pipe)) | |
2176 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2177 | |
40da17c2 | 2178 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2179 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2180 | |
40da17c2 DV |
2181 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2182 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2183 | |
40da17c2 DV |
2184 | /* plane/pipes map 1:1 on ilk+ */ |
2185 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2186 | intel_prepare_page_flip(dev, pipe); | |
2187 | intel_finish_page_flip_plane(dev, pipe); | |
2188 | } | |
c008bc6e PZ |
2189 | } |
2190 | ||
2191 | /* check event from PCH */ | |
2192 | if (de_iir & DE_PCH_EVENT) { | |
2193 | u32 pch_iir = I915_READ(SDEIIR); | |
2194 | ||
2195 | if (HAS_PCH_CPT(dev)) | |
2196 | cpt_irq_handler(dev, pch_iir); | |
2197 | else | |
2198 | ibx_irq_handler(dev, pch_iir); | |
2199 | ||
2200 | /* should clear PCH hotplug event before clear CPU irq */ | |
2201 | I915_WRITE(SDEIIR, pch_iir); | |
2202 | } | |
2203 | ||
2204 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2205 | ironlake_rps_change_irq_handler(dev); | |
2206 | } | |
2207 | ||
9719fb98 PZ |
2208 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2209 | { | |
2210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2211 | enum pipe pipe; |
23bb4cb5 VS |
2212 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2213 | ||
40e56410 VS |
2214 | if (hotplug_trigger) |
2215 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb); | |
9719fb98 PZ |
2216 | |
2217 | if (de_iir & DE_ERR_INT_IVB) | |
2218 | ivb_err_int_handler(dev); | |
2219 | ||
2220 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2221 | dp_aux_irq_handler(dev); | |
2222 | ||
2223 | if (de_iir & DE_GSE_IVB) | |
2224 | intel_opregion_asle_intr(dev); | |
2225 | ||
055e393f | 2226 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2227 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2228 | intel_pipe_handle_vblank(dev, pipe)) | |
2229 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2230 | |
2231 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2232 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2233 | intel_prepare_page_flip(dev, pipe); | |
2234 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2235 | } |
2236 | } | |
2237 | ||
2238 | /* check event from PCH */ | |
2239 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2240 | u32 pch_iir = I915_READ(SDEIIR); | |
2241 | ||
2242 | cpt_irq_handler(dev, pch_iir); | |
2243 | ||
2244 | /* clear PCH hotplug event before clear CPU irq */ | |
2245 | I915_WRITE(SDEIIR, pch_iir); | |
2246 | } | |
2247 | } | |
2248 | ||
72c90f62 OM |
2249 | /* |
2250 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2251 | * 1 - Disable Master Interrupt Control. | |
2252 | * 2 - Find the source(s) of the interrupt. | |
2253 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2254 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2255 | * 5 - Re-enable Master Interrupt Control. | |
2256 | */ | |
f1af8fc1 | 2257 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2258 | { |
45a83f84 | 2259 | struct drm_device *dev = arg; |
2d1013dd | 2260 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2261 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2262 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2263 | |
2dd2a883 ID |
2264 | if (!intel_irqs_enabled(dev_priv)) |
2265 | return IRQ_NONE; | |
2266 | ||
1f814dac ID |
2267 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2268 | disable_rpm_wakeref_asserts(dev_priv); | |
2269 | ||
b1f14ad0 JB |
2270 | /* disable master interrupt before clearing iir */ |
2271 | de_ier = I915_READ(DEIER); | |
2272 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2273 | POSTING_READ(DEIER); |
b1f14ad0 | 2274 | |
44498aea PZ |
2275 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2276 | * interrupts will will be stored on its back queue, and then we'll be | |
2277 | * able to process them after we restore SDEIER (as soon as we restore | |
2278 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2279 | * due to its back queue). */ | |
ab5c608b BW |
2280 | if (!HAS_PCH_NOP(dev)) { |
2281 | sde_ier = I915_READ(SDEIER); | |
2282 | I915_WRITE(SDEIER, 0); | |
2283 | POSTING_READ(SDEIER); | |
2284 | } | |
44498aea | 2285 | |
72c90f62 OM |
2286 | /* Find, clear, then process each source of interrupt */ |
2287 | ||
b1f14ad0 | 2288 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2289 | if (gt_iir) { |
72c90f62 OM |
2290 | I915_WRITE(GTIIR, gt_iir); |
2291 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2292 | if (INTEL_INFO(dev)->gen >= 6) |
261e40b8 | 2293 | snb_gt_irq_handler(dev_priv, gt_iir); |
d8fc8a47 | 2294 | else |
261e40b8 | 2295 | ilk_gt_irq_handler(dev_priv, gt_iir); |
b1f14ad0 JB |
2296 | } |
2297 | ||
0e43406b CW |
2298 | de_iir = I915_READ(DEIIR); |
2299 | if (de_iir) { | |
72c90f62 OM |
2300 | I915_WRITE(DEIIR, de_iir); |
2301 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2302 | if (INTEL_INFO(dev)->gen >= 7) |
2303 | ivb_display_irq_handler(dev, de_iir); | |
2304 | else | |
2305 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2306 | } |
2307 | ||
f1af8fc1 PZ |
2308 | if (INTEL_INFO(dev)->gen >= 6) { |
2309 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2310 | if (pm_iir) { | |
f1af8fc1 PZ |
2311 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2312 | ret = IRQ_HANDLED; | |
72c90f62 | 2313 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2314 | } |
0e43406b | 2315 | } |
b1f14ad0 | 2316 | |
b1f14ad0 JB |
2317 | I915_WRITE(DEIER, de_ier); |
2318 | POSTING_READ(DEIER); | |
ab5c608b BW |
2319 | if (!HAS_PCH_NOP(dev)) { |
2320 | I915_WRITE(SDEIER, sde_ier); | |
2321 | POSTING_READ(SDEIER); | |
2322 | } | |
b1f14ad0 | 2323 | |
1f814dac ID |
2324 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
2325 | enable_rpm_wakeref_asserts(dev_priv); | |
2326 | ||
b1f14ad0 JB |
2327 | return ret; |
2328 | } | |
2329 | ||
40e56410 VS |
2330 | static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
2331 | const u32 hpd[HPD_NUM_PINS]) | |
d04a492d | 2332 | { |
cebd87a0 VS |
2333 | struct drm_i915_private *dev_priv = to_i915(dev); |
2334 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
d04a492d | 2335 | |
a52bb15b VS |
2336 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2337 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2338 | |
cebd87a0 | 2339 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2340 | dig_hotplug_reg, hpd, |
cebd87a0 | 2341 | bxt_port_hotplug_long_detect); |
40e56410 | 2342 | |
676574df | 2343 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
d04a492d SS |
2344 | } |
2345 | ||
f11a0f46 TU |
2346 | static irqreturn_t |
2347 | gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) | |
abd58f01 | 2348 | { |
f11a0f46 | 2349 | struct drm_device *dev = dev_priv->dev; |
abd58f01 | 2350 | irqreturn_t ret = IRQ_NONE; |
f11a0f46 | 2351 | u32 iir; |
c42664cc | 2352 | enum pipe pipe; |
88e04703 | 2353 | |
abd58f01 | 2354 | if (master_ctl & GEN8_DE_MISC_IRQ) { |
e32192e1 TU |
2355 | iir = I915_READ(GEN8_DE_MISC_IIR); |
2356 | if (iir) { | |
2357 | I915_WRITE(GEN8_DE_MISC_IIR, iir); | |
abd58f01 | 2358 | ret = IRQ_HANDLED; |
e32192e1 | 2359 | if (iir & GEN8_DE_MISC_GSE) |
38cc46d7 OM |
2360 | intel_opregion_asle_intr(dev); |
2361 | else | |
2362 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2363 | } |
38cc46d7 OM |
2364 | else |
2365 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2366 | } |
2367 | ||
6d766f02 | 2368 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
e32192e1 TU |
2369 | iir = I915_READ(GEN8_DE_PORT_IIR); |
2370 | if (iir) { | |
2371 | u32 tmp_mask; | |
d04a492d | 2372 | bool found = false; |
cebd87a0 | 2373 | |
e32192e1 | 2374 | I915_WRITE(GEN8_DE_PORT_IIR, iir); |
6d766f02 | 2375 | ret = IRQ_HANDLED; |
88e04703 | 2376 | |
e32192e1 TU |
2377 | tmp_mask = GEN8_AUX_CHANNEL_A; |
2378 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2379 | tmp_mask |= GEN9_AUX_CHANNEL_B | | |
2380 | GEN9_AUX_CHANNEL_C | | |
2381 | GEN9_AUX_CHANNEL_D; | |
2382 | ||
2383 | if (iir & tmp_mask) { | |
38cc46d7 | 2384 | dp_aux_irq_handler(dev); |
d04a492d SS |
2385 | found = true; |
2386 | } | |
2387 | ||
e32192e1 TU |
2388 | if (IS_BROXTON(dev_priv)) { |
2389 | tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; | |
2390 | if (tmp_mask) { | |
2391 | bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt); | |
2392 | found = true; | |
2393 | } | |
2394 | } else if (IS_BROADWELL(dev_priv)) { | |
2395 | tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG; | |
2396 | if (tmp_mask) { | |
2397 | ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw); | |
2398 | found = true; | |
2399 | } | |
d04a492d SS |
2400 | } |
2401 | ||
e32192e1 | 2402 | if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) { |
9e63743e SS |
2403 | gmbus_irq_handler(dev); |
2404 | found = true; | |
2405 | } | |
2406 | ||
d04a492d | 2407 | if (!found) |
38cc46d7 | 2408 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2409 | } |
38cc46d7 OM |
2410 | else |
2411 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2412 | } |
2413 | ||
055e393f | 2414 | for_each_pipe(dev_priv, pipe) { |
e32192e1 | 2415 | u32 flip_done, fault_errors; |
abd58f01 | 2416 | |
c42664cc DV |
2417 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2418 | continue; | |
abd58f01 | 2419 | |
e32192e1 TU |
2420 | iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2421 | if (!iir) { | |
2422 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); | |
2423 | continue; | |
2424 | } | |
770de83d | 2425 | |
e32192e1 TU |
2426 | ret = IRQ_HANDLED; |
2427 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir); | |
38cc46d7 | 2428 | |
e32192e1 TU |
2429 | if (iir & GEN8_PIPE_VBLANK && |
2430 | intel_pipe_handle_vblank(dev, pipe)) | |
2431 | intel_check_page_flip(dev, pipe); | |
770de83d | 2432 | |
e32192e1 TU |
2433 | flip_done = iir; |
2434 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2435 | flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE; | |
2436 | else | |
2437 | flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE; | |
38cc46d7 | 2438 | |
e32192e1 TU |
2439 | if (flip_done) { |
2440 | intel_prepare_page_flip(dev, pipe); | |
2441 | intel_finish_page_flip_plane(dev, pipe); | |
2442 | } | |
38cc46d7 | 2443 | |
e32192e1 TU |
2444 | if (iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2445 | hsw_pipe_crc_irq_handler(dev, pipe); | |
38cc46d7 | 2446 | |
e32192e1 TU |
2447 | if (iir & GEN8_PIPE_FIFO_UNDERRUN) |
2448 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
770de83d | 2449 | |
e32192e1 TU |
2450 | fault_errors = iir; |
2451 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2452 | fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
2453 | else | |
2454 | fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
770de83d | 2455 | |
e32192e1 TU |
2456 | if (fault_errors) |
2457 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2458 | pipe_name(pipe), | |
2459 | fault_errors); | |
abd58f01 BW |
2460 | } |
2461 | ||
266ea3d9 SS |
2462 | if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && |
2463 | master_ctl & GEN8_DE_PCH_IRQ) { | |
92d03a80 DV |
2464 | /* |
2465 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2466 | * scheme also closed the SDE interrupt handling race we've seen | |
2467 | * on older pch-split platforms. But this needs testing. | |
2468 | */ | |
e32192e1 TU |
2469 | iir = I915_READ(SDEIIR); |
2470 | if (iir) { | |
2471 | I915_WRITE(SDEIIR, iir); | |
92d03a80 | 2472 | ret = IRQ_HANDLED; |
6dbf30ce | 2473 | |
bc7135b9 | 2474 | if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) |
e32192e1 | 2475 | spt_irq_handler(dev, iir); |
6dbf30ce | 2476 | else |
e32192e1 | 2477 | cpt_irq_handler(dev, iir); |
2dfb0b81 JN |
2478 | } else { |
2479 | /* | |
2480 | * Like on previous PCH there seems to be something | |
2481 | * fishy going on with forwarding PCH interrupts. | |
2482 | */ | |
2483 | DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n"); | |
2484 | } | |
92d03a80 DV |
2485 | } |
2486 | ||
f11a0f46 TU |
2487 | return ret; |
2488 | } | |
2489 | ||
2490 | static irqreturn_t gen8_irq_handler(int irq, void *arg) | |
2491 | { | |
2492 | struct drm_device *dev = arg; | |
2493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2494 | u32 master_ctl; | |
e30e251a | 2495 | u32 gt_iir[4] = {}; |
f11a0f46 TU |
2496 | irqreturn_t ret; |
2497 | ||
2498 | if (!intel_irqs_enabled(dev_priv)) | |
2499 | return IRQ_NONE; | |
2500 | ||
2501 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); | |
2502 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
2503 | if (!master_ctl) | |
2504 | return IRQ_NONE; | |
2505 | ||
2506 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); | |
2507 | ||
2508 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ | |
2509 | disable_rpm_wakeref_asserts(dev_priv); | |
2510 | ||
2511 | /* Find, clear, then process each source of interrupt */ | |
e30e251a VS |
2512 | ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); |
2513 | gen8_gt_irq_handler(dev_priv, gt_iir); | |
f11a0f46 TU |
2514 | ret |= gen8_de_irq_handler(dev_priv, master_ctl); |
2515 | ||
cb0d205e CW |
2516 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2517 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 | 2518 | |
1f814dac ID |
2519 | enable_rpm_wakeref_asserts(dev_priv); |
2520 | ||
abd58f01 BW |
2521 | return ret; |
2522 | } | |
2523 | ||
17e1df07 DV |
2524 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2525 | bool reset_completed) | |
2526 | { | |
e2f80391 | 2527 | struct intel_engine_cs *engine; |
17e1df07 DV |
2528 | |
2529 | /* | |
2530 | * Notify all waiters for GPU completion events that reset state has | |
2531 | * been changed, and that they need to restart their wait after | |
2532 | * checking for potential errors (and bail out to drop locks if there is | |
2533 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2534 | */ | |
2535 | ||
2536 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
b4ac5afc | 2537 | for_each_engine(engine, dev_priv) |
e2f80391 | 2538 | wake_up_all(&engine->irq_queue); |
17e1df07 DV |
2539 | |
2540 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2541 | wake_up_all(&dev_priv->pending_flip_queue); | |
2542 | ||
2543 | /* | |
2544 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2545 | * reset state is cleared. | |
2546 | */ | |
2547 | if (reset_completed) | |
2548 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2549 | } | |
2550 | ||
8a905236 | 2551 | /** |
b8d24a06 | 2552 | * i915_reset_and_wakeup - do process context error handling work |
468f9d29 | 2553 | * @dev: drm device |
8a905236 JB |
2554 | * |
2555 | * Fire an error uevent so userspace can see that a hang or error | |
2556 | * was detected. | |
2557 | */ | |
b8d24a06 | 2558 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2559 | { |
b8d24a06 | 2560 | struct drm_i915_private *dev_priv = to_i915(dev); |
cce723ed BW |
2561 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2562 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2563 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2564 | int ret; |
8a905236 | 2565 | |
5bdebb18 | 2566 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2567 | |
7db0ba24 DV |
2568 | /* |
2569 | * Note that there's only one work item which does gpu resets, so we | |
2570 | * need not worry about concurrent gpu resets potentially incrementing | |
2571 | * error->reset_counter twice. We only need to take care of another | |
2572 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2573 | * quick check for that is good enough: schedule_work ensures the | |
2574 | * correct ordering between hang detection and this work item, and since | |
2575 | * the reset in-progress bit is only ever set by code outside of this | |
2576 | * work we don't need to worry about any other races. | |
2577 | */ | |
d98c52cf | 2578 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
f803aa55 | 2579 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2580 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2581 | reset_event); |
1f83fee0 | 2582 | |
f454c694 ID |
2583 | /* |
2584 | * In most cases it's guaranteed that we get here with an RPM | |
2585 | * reference held, for example because there is a pending GPU | |
2586 | * request that won't finish until the reset is done. This | |
2587 | * isn't the case at least when we get here by doing a | |
2588 | * simulated reset via debugs, so get an RPM reference. | |
2589 | */ | |
2590 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2591 | |
2592 | intel_prepare_reset(dev); | |
2593 | ||
17e1df07 DV |
2594 | /* |
2595 | * All state reset _must_ be completed before we update the | |
2596 | * reset counter, for otherwise waiters might miss the reset | |
2597 | * pending state and not properly drop locks, resulting in | |
2598 | * deadlocks with the reset work. | |
2599 | */ | |
f69061be DV |
2600 | ret = i915_reset(dev); |
2601 | ||
7514747d | 2602 | intel_finish_reset(dev); |
17e1df07 | 2603 | |
f454c694 ID |
2604 | intel_runtime_pm_put(dev_priv); |
2605 | ||
d98c52cf | 2606 | if (ret == 0) |
5bdebb18 | 2607 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2608 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2609 | |
17e1df07 DV |
2610 | /* |
2611 | * Note: The wake_up also serves as a memory barrier so that | |
2612 | * waiters see the update value of the reset counter atomic_t. | |
2613 | */ | |
2614 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2615 | } |
8a905236 JB |
2616 | } |
2617 | ||
35aed2e6 | 2618 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2619 | { |
2620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2621 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2622 | u32 eir = I915_READ(EIR); |
050ee91f | 2623 | int pipe, i; |
8a905236 | 2624 | |
35aed2e6 CW |
2625 | if (!eir) |
2626 | return; | |
8a905236 | 2627 | |
a70491cc | 2628 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2629 | |
bd9854f9 BW |
2630 | i915_get_extra_instdone(dev, instdone); |
2631 | ||
8a905236 JB |
2632 | if (IS_G4X(dev)) { |
2633 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2634 | u32 ipeir = I915_READ(IPEIR_I965); | |
2635 | ||
a70491cc JP |
2636 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2637 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2638 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2639 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2640 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2641 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2642 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2643 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2644 | } |
2645 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2646 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2647 | pr_err("page table error\n"); |
2648 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2649 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2650 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2651 | } |
2652 | } | |
2653 | ||
a6c45cf0 | 2654 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2655 | if (eir & I915_ERROR_PAGE_TABLE) { |
2656 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2657 | pr_err("page table error\n"); |
2658 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2659 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2660 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2661 | } |
2662 | } | |
2663 | ||
2664 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2665 | pr_err("memory refresh error:\n"); |
055e393f | 2666 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2667 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2668 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2669 | /* pipestat has already been acked */ |
2670 | } | |
2671 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2672 | pr_err("instruction error\n"); |
2673 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2674 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2675 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2676 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2677 | u32 ipeir = I915_READ(IPEIR); |
2678 | ||
a70491cc JP |
2679 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2680 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2681 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2682 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2683 | POSTING_READ(IPEIR); |
8a905236 JB |
2684 | } else { |
2685 | u32 ipeir = I915_READ(IPEIR_I965); | |
2686 | ||
a70491cc JP |
2687 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2688 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2689 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2690 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2691 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2692 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2693 | } |
2694 | } | |
2695 | ||
2696 | I915_WRITE(EIR, eir); | |
3143a2bf | 2697 | POSTING_READ(EIR); |
8a905236 JB |
2698 | eir = I915_READ(EIR); |
2699 | if (eir) { | |
2700 | /* | |
2701 | * some errors might have become stuck, | |
2702 | * mask them. | |
2703 | */ | |
2704 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2705 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2706 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2707 | } | |
35aed2e6 CW |
2708 | } |
2709 | ||
2710 | /** | |
b8d24a06 | 2711 | * i915_handle_error - handle a gpu error |
35aed2e6 | 2712 | * @dev: drm device |
14b730fc | 2713 | * @engine_mask: mask representing engines that are hung |
aafd8581 | 2714 | * Do some basic checking of register state at error time and |
35aed2e6 CW |
2715 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2716 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2717 | * so userspace knows something bad happened (should trigger collection | |
2718 | * of a ring dump etc.). | |
2719 | */ | |
14b730fc | 2720 | void i915_handle_error(struct drm_device *dev, u32 engine_mask, |
58174462 | 2721 | const char *fmt, ...) |
35aed2e6 CW |
2722 | { |
2723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2724 | va_list args; |
2725 | char error_msg[80]; | |
35aed2e6 | 2726 | |
58174462 MK |
2727 | va_start(args, fmt); |
2728 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2729 | va_end(args); | |
2730 | ||
14b730fc | 2731 | i915_capture_error_state(dev, engine_mask, error_msg); |
35aed2e6 | 2732 | i915_report_and_clear_eir(dev); |
8a905236 | 2733 | |
14b730fc | 2734 | if (engine_mask) { |
805de8f4 | 2735 | atomic_or(I915_RESET_IN_PROGRESS_FLAG, |
f69061be | 2736 | &dev_priv->gpu_error.reset_counter); |
ba1234d1 | 2737 | |
11ed50ec | 2738 | /* |
b8d24a06 MK |
2739 | * Wakeup waiting processes so that the reset function |
2740 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2741 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2742 | * processes will see a reset in progress and back off, |
2743 | * releasing their locks and then wait for the reset completion. | |
2744 | * We must do this for _all_ gpu waiters that might hold locks | |
2745 | * that the reset work needs to acquire. | |
2746 | * | |
2747 | * Note: The wake_up serves as the required memory barrier to | |
2748 | * ensure that the waiters see the updated value of the reset | |
2749 | * counter atomic_t. | |
11ed50ec | 2750 | */ |
17e1df07 | 2751 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2752 | } |
2753 | ||
b8d24a06 | 2754 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2755 | } |
2756 | ||
42f52ef8 KP |
2757 | /* Called from drm generic code, passed 'crtc' which |
2758 | * we use as a pipe index | |
2759 | */ | |
88e72717 | 2760 | static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2761 | { |
2d1013dd | 2762 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2763 | unsigned long irqflags; |
71e0ffa5 | 2764 | |
1ec14ad3 | 2765 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2766 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2767 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2768 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2769 | else |
7c463586 | 2770 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2771 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2772 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2773 | |
0a3e67a4 JB |
2774 | return 0; |
2775 | } | |
2776 | ||
88e72717 | 2777 | static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2778 | { |
2d1013dd | 2779 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2780 | unsigned long irqflags; |
b518421f | 2781 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2782 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2783 | |
f796cf8f | 2784 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
fbdedaea | 2785 | ilk_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2786 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2787 | ||
2788 | return 0; | |
2789 | } | |
2790 | ||
88e72717 | 2791 | static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2792 | { |
2d1013dd | 2793 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2794 | unsigned long irqflags; |
7e231dbe | 2795 | |
7e231dbe | 2796 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2797 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2798 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2799 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2800 | ||
2801 | return 0; | |
2802 | } | |
2803 | ||
88e72717 | 2804 | static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2805 | { |
2806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2807 | unsigned long irqflags; | |
abd58f01 | 2808 | |
abd58f01 | 2809 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2810 | bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 | 2811 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
013d3752 | 2812 | |
abd58f01 BW |
2813 | return 0; |
2814 | } | |
2815 | ||
42f52ef8 KP |
2816 | /* Called from drm generic code, passed 'crtc' which |
2817 | * we use as a pipe index | |
2818 | */ | |
88e72717 | 2819 | static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) |
0a3e67a4 | 2820 | { |
2d1013dd | 2821 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2822 | unsigned long irqflags; |
0a3e67a4 | 2823 | |
1ec14ad3 | 2824 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2825 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2826 | PIPE_VBLANK_INTERRUPT_STATUS | |
2827 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2828 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2829 | } | |
2830 | ||
88e72717 | 2831 | static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) |
f796cf8f | 2832 | { |
2d1013dd | 2833 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2834 | unsigned long irqflags; |
b518421f | 2835 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2836 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2837 | |
2838 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
fbdedaea | 2839 | ilk_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2840 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2841 | } | |
2842 | ||
88e72717 | 2843 | static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) |
7e231dbe | 2844 | { |
2d1013dd | 2845 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2846 | unsigned long irqflags; |
7e231dbe JB |
2847 | |
2848 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2849 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2850 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2851 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2852 | } | |
2853 | ||
88e72717 | 2854 | static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) |
abd58f01 BW |
2855 | { |
2856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2857 | unsigned long irqflags; | |
abd58f01 | 2858 | |
abd58f01 | 2859 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
013d3752 | 2860 | bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); |
abd58f01 BW |
2861 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2862 | } | |
2863 | ||
9107e9d2 | 2864 | static bool |
0bc40be8 | 2865 | ring_idle(struct intel_engine_cs *engine, u32 seqno) |
9107e9d2 | 2866 | { |
cffa781e CW |
2867 | return i915_seqno_passed(seqno, |
2868 | READ_ONCE(engine->last_submitted_seqno)); | |
f65d9421 BG |
2869 | } |
2870 | ||
a028c4b0 DV |
2871 | static bool |
2872 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2873 | { | |
2874 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2875 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2876 | } else { |
2877 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2878 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2879 | MI_SEMAPHORE_REGISTER); | |
2880 | } | |
2881 | } | |
2882 | ||
a4872ba6 | 2883 | static struct intel_engine_cs * |
0bc40be8 TU |
2884 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, |
2885 | u64 offset) | |
921d42ea | 2886 | { |
0bc40be8 | 2887 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
a4872ba6 | 2888 | struct intel_engine_cs *signaller; |
921d42ea | 2889 | |
2d1fe073 | 2890 | if (INTEL_INFO(dev_priv)->gen >= 8) { |
b4ac5afc | 2891 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2892 | if (engine == signaller) |
a6cdb93a RV |
2893 | continue; |
2894 | ||
0bc40be8 | 2895 | if (offset == signaller->semaphore.signal_ggtt[engine->id]) |
a6cdb93a RV |
2896 | return signaller; |
2897 | } | |
921d42ea DV |
2898 | } else { |
2899 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2900 | ||
b4ac5afc | 2901 | for_each_engine(signaller, dev_priv) { |
0bc40be8 | 2902 | if(engine == signaller) |
921d42ea DV |
2903 | continue; |
2904 | ||
0bc40be8 | 2905 | if (sync_bits == signaller->semaphore.mbox.wait[engine->id]) |
921d42ea DV |
2906 | return signaller; |
2907 | } | |
2908 | } | |
2909 | ||
a6cdb93a | 2910 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
0bc40be8 | 2911 | engine->id, ipehr, offset); |
921d42ea DV |
2912 | |
2913 | return NULL; | |
2914 | } | |
2915 | ||
a4872ba6 | 2916 | static struct intel_engine_cs * |
0bc40be8 | 2917 | semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) |
a24a11e6 | 2918 | { |
0bc40be8 | 2919 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
88fe429d | 2920 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2921 | u64 offset = 0; |
2922 | int i, backwards; | |
a24a11e6 | 2923 | |
381e8ae3 TE |
2924 | /* |
2925 | * This function does not support execlist mode - any attempt to | |
2926 | * proceed further into this function will result in a kernel panic | |
2927 | * when dereferencing ring->buffer, which is not set up in execlist | |
2928 | * mode. | |
2929 | * | |
2930 | * The correct way of doing it would be to derive the currently | |
2931 | * executing ring buffer from the current context, which is derived | |
2932 | * from the currently running request. Unfortunately, to get the | |
2933 | * current request we would have to grab the struct_mutex before doing | |
2934 | * anything else, which would be ill-advised since some other thread | |
2935 | * might have grabbed it already and managed to hang itself, causing | |
2936 | * the hang checker to deadlock. | |
2937 | * | |
2938 | * Therefore, this function does not support execlist mode in its | |
2939 | * current form. Just return NULL and move on. | |
2940 | */ | |
0bc40be8 | 2941 | if (engine->buffer == NULL) |
381e8ae3 TE |
2942 | return NULL; |
2943 | ||
0bc40be8 TU |
2944 | ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); |
2945 | if (!ipehr_is_semaphore_wait(engine->dev, ipehr)) | |
6274f212 | 2946 | return NULL; |
a24a11e6 | 2947 | |
88fe429d DV |
2948 | /* |
2949 | * HEAD is likely pointing to the dword after the actual command, | |
2950 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2951 | * or 4 dwords depending on the semaphore wait command size. |
2952 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2953 | * point at at batch, and semaphores are always emitted into the |
2954 | * ringbuffer itself. | |
a24a11e6 | 2955 | */ |
0bc40be8 TU |
2956 | head = I915_READ_HEAD(engine) & HEAD_ADDR; |
2957 | backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4; | |
88fe429d | 2958 | |
a6cdb93a | 2959 | for (i = backwards; i; --i) { |
88fe429d DV |
2960 | /* |
2961 | * Be paranoid and presume the hw has gone off into the wild - | |
2962 | * our ring is smaller than what the hardware (and hence | |
2963 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2964 | */ | |
0bc40be8 | 2965 | head &= engine->buffer->size - 1; |
88fe429d DV |
2966 | |
2967 | /* This here seems to blow up */ | |
0bc40be8 | 2968 | cmd = ioread32(engine->buffer->virtual_start + head); |
a24a11e6 CW |
2969 | if (cmd == ipehr) |
2970 | break; | |
2971 | ||
88fe429d DV |
2972 | head -= 4; |
2973 | } | |
a24a11e6 | 2974 | |
88fe429d DV |
2975 | if (!i) |
2976 | return NULL; | |
a24a11e6 | 2977 | |
0bc40be8 TU |
2978 | *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1; |
2979 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2980 | offset = ioread32(engine->buffer->virtual_start + head + 12); | |
a6cdb93a | 2981 | offset <<= 32; |
0bc40be8 | 2982 | offset = ioread32(engine->buffer->virtual_start + head + 8); |
a6cdb93a | 2983 | } |
0bc40be8 | 2984 | return semaphore_wait_to_signaller_ring(engine, ipehr, offset); |
a24a11e6 CW |
2985 | } |
2986 | ||
0bc40be8 | 2987 | static int semaphore_passed(struct intel_engine_cs *engine) |
6274f212 | 2988 | { |
0bc40be8 | 2989 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
a4872ba6 | 2990 | struct intel_engine_cs *signaller; |
a0d036b0 | 2991 | u32 seqno; |
6274f212 | 2992 | |
0bc40be8 | 2993 | engine->hangcheck.deadlock++; |
6274f212 | 2994 | |
0bc40be8 | 2995 | signaller = semaphore_waits_for(engine, &seqno); |
4be17381 CW |
2996 | if (signaller == NULL) |
2997 | return -1; | |
2998 | ||
2999 | /* Prevent pathological recursion due to driver bugs */ | |
666796da | 3000 | if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) |
6274f212 CW |
3001 | return -1; |
3002 | ||
c04e0f3b | 3003 | if (i915_seqno_passed(signaller->get_seqno(signaller), seqno)) |
4be17381 CW |
3004 | return 1; |
3005 | ||
a0d036b0 CW |
3006 | /* cursory check for an unkickable deadlock */ |
3007 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
3008 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
3009 | return -1; |
3010 | ||
3011 | return 0; | |
6274f212 CW |
3012 | } |
3013 | ||
3014 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
3015 | { | |
e2f80391 | 3016 | struct intel_engine_cs *engine; |
6274f212 | 3017 | |
b4ac5afc | 3018 | for_each_engine(engine, dev_priv) |
e2f80391 | 3019 | engine->hangcheck.deadlock = 0; |
6274f212 CW |
3020 | } |
3021 | ||
0bc40be8 | 3022 | static bool subunits_stuck(struct intel_engine_cs *engine) |
1ec14ad3 | 3023 | { |
61642ff0 MK |
3024 | u32 instdone[I915_NUM_INSTDONE_REG]; |
3025 | bool stuck; | |
3026 | int i; | |
3027 | ||
0bc40be8 | 3028 | if (engine->id != RCS) |
61642ff0 MK |
3029 | return true; |
3030 | ||
0bc40be8 | 3031 | i915_get_extra_instdone(engine->dev, instdone); |
9107e9d2 | 3032 | |
61642ff0 MK |
3033 | /* There might be unstable subunit states even when |
3034 | * actual head is not moving. Filter out the unstable ones by | |
3035 | * accumulating the undone -> done transitions and only | |
3036 | * consider those as progress. | |
3037 | */ | |
3038 | stuck = true; | |
3039 | for (i = 0; i < I915_NUM_INSTDONE_REG; i++) { | |
0bc40be8 | 3040 | const u32 tmp = instdone[i] | engine->hangcheck.instdone[i]; |
61642ff0 | 3041 | |
0bc40be8 | 3042 | if (tmp != engine->hangcheck.instdone[i]) |
61642ff0 MK |
3043 | stuck = false; |
3044 | ||
0bc40be8 | 3045 | engine->hangcheck.instdone[i] |= tmp; |
61642ff0 MK |
3046 | } |
3047 | ||
3048 | return stuck; | |
3049 | } | |
3050 | ||
3051 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3052 | head_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3053 | { |
0bc40be8 | 3054 | if (acthd != engine->hangcheck.acthd) { |
61642ff0 MK |
3055 | |
3056 | /* Clear subunit states on head movement */ | |
0bc40be8 TU |
3057 | memset(engine->hangcheck.instdone, 0, |
3058 | sizeof(engine->hangcheck.instdone)); | |
61642ff0 | 3059 | |
24a65e62 | 3060 | return HANGCHECK_ACTIVE; |
f260fe7b | 3061 | } |
6274f212 | 3062 | |
0bc40be8 | 3063 | if (!subunits_stuck(engine)) |
61642ff0 MK |
3064 | return HANGCHECK_ACTIVE; |
3065 | ||
3066 | return HANGCHECK_HUNG; | |
3067 | } | |
3068 | ||
3069 | static enum intel_ring_hangcheck_action | |
0bc40be8 | 3070 | ring_stuck(struct intel_engine_cs *engine, u64 acthd) |
61642ff0 | 3071 | { |
0bc40be8 | 3072 | struct drm_device *dev = engine->dev; |
61642ff0 MK |
3073 | struct drm_i915_private *dev_priv = dev->dev_private; |
3074 | enum intel_ring_hangcheck_action ha; | |
3075 | u32 tmp; | |
3076 | ||
0bc40be8 | 3077 | ha = head_stuck(engine, acthd); |
61642ff0 MK |
3078 | if (ha != HANGCHECK_HUNG) |
3079 | return ha; | |
3080 | ||
9107e9d2 | 3081 | if (IS_GEN2(dev)) |
f2f4d82f | 3082 | return HANGCHECK_HUNG; |
9107e9d2 CW |
3083 | |
3084 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
3085 | * If so we can simply poke the RB_WAIT bit | |
3086 | * and break the hang. This should work on | |
3087 | * all but the second generation chipsets. | |
3088 | */ | |
0bc40be8 | 3089 | tmp = I915_READ_CTL(engine); |
1ec14ad3 | 3090 | if (tmp & RING_WAIT) { |
14b730fc | 3091 | i915_handle_error(dev, 0, |
58174462 | 3092 | "Kicking stuck wait on %s", |
0bc40be8 TU |
3093 | engine->name); |
3094 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3095 | return HANGCHECK_KICK; |
6274f212 CW |
3096 | } |
3097 | ||
3098 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
0bc40be8 | 3099 | switch (semaphore_passed(engine)) { |
6274f212 | 3100 | default: |
f2f4d82f | 3101 | return HANGCHECK_HUNG; |
6274f212 | 3102 | case 1: |
14b730fc | 3103 | i915_handle_error(dev, 0, |
58174462 | 3104 | "Kicking stuck semaphore on %s", |
0bc40be8 TU |
3105 | engine->name); |
3106 | I915_WRITE_CTL(engine, tmp); | |
f2f4d82f | 3107 | return HANGCHECK_KICK; |
6274f212 | 3108 | case 0: |
f2f4d82f | 3109 | return HANGCHECK_WAIT; |
6274f212 | 3110 | } |
9107e9d2 | 3111 | } |
ed5cbb03 | 3112 | |
f2f4d82f | 3113 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
3114 | } |
3115 | ||
12471ba8 CW |
3116 | static unsigned kick_waiters(struct intel_engine_cs *engine) |
3117 | { | |
3118 | struct drm_i915_private *i915 = to_i915(engine->dev); | |
3119 | unsigned user_interrupts = READ_ONCE(engine->user_interrupts); | |
3120 | ||
3121 | if (engine->hangcheck.user_interrupts == user_interrupts && | |
3122 | !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) { | |
3123 | if (!(i915->gpu_error.test_irq_rings & intel_engine_flag(engine))) | |
3124 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
3125 | engine->name); | |
3126 | else | |
3127 | DRM_INFO("Fake missed irq on %s\n", | |
3128 | engine->name); | |
3129 | wake_up_all(&engine->irq_queue); | |
3130 | } | |
3131 | ||
3132 | return user_interrupts; | |
3133 | } | |
737b1506 | 3134 | /* |
f65d9421 | 3135 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
3136 | * batchbuffers in a long time. We keep track per ring seqno progress and |
3137 | * if there are no progress, hangcheck score for that ring is increased. | |
3138 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
3139 | * we kick the ring. If we see no progress on three subsequent calls | |
3140 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 3141 | */ |
737b1506 | 3142 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 3143 | { |
737b1506 CW |
3144 | struct drm_i915_private *dev_priv = |
3145 | container_of(work, typeof(*dev_priv), | |
3146 | gpu_error.hangcheck_work.work); | |
3147 | struct drm_device *dev = dev_priv->dev; | |
e2f80391 | 3148 | struct intel_engine_cs *engine; |
c3232b18 | 3149 | enum intel_engine_id id; |
05407ff8 | 3150 | int busy_count = 0, rings_hung = 0; |
666796da | 3151 | bool stuck[I915_NUM_ENGINES] = { 0 }; |
9107e9d2 CW |
3152 | #define BUSY 1 |
3153 | #define KICK 5 | |
3154 | #define HUNG 20 | |
24a65e62 | 3155 | #define ACTIVE_DECAY 15 |
893eead0 | 3156 | |
d330a953 | 3157 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
3158 | return; |
3159 | ||
1f814dac ID |
3160 | /* |
3161 | * The hangcheck work is synced during runtime suspend, we don't | |
3162 | * require a wakeref. TODO: instead of disabling the asserts make | |
3163 | * sure that we hold a reference when this work is running. | |
3164 | */ | |
3165 | DISABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
3166 | ||
75714940 MK |
3167 | /* As enabling the GPU requires fairly extensive mmio access, |
3168 | * periodically arm the mmio checker to see if we are triggering | |
3169 | * any invalid access. | |
3170 | */ | |
3171 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
3172 | ||
c3232b18 | 3173 | for_each_engine_id(engine, dev_priv, id) { |
50877445 CW |
3174 | u64 acthd; |
3175 | u32 seqno; | |
12471ba8 | 3176 | unsigned user_interrupts; |
9107e9d2 | 3177 | bool busy = true; |
05407ff8 | 3178 | |
6274f212 CW |
3179 | semaphore_clear_deadlocks(dev_priv); |
3180 | ||
c04e0f3b CW |
3181 | /* We don't strictly need an irq-barrier here, as we are not |
3182 | * serving an interrupt request, be paranoid in case the | |
3183 | * barrier has side-effects (such as preventing a broken | |
3184 | * cacheline snoop) and so be sure that we can see the seqno | |
3185 | * advance. If the seqno should stick, due to a stale | |
3186 | * cacheline, we would erroneously declare the GPU hung. | |
3187 | */ | |
3188 | if (engine->irq_seqno_barrier) | |
3189 | engine->irq_seqno_barrier(engine); | |
3190 | ||
e2f80391 | 3191 | acthd = intel_ring_get_active_head(engine); |
c04e0f3b | 3192 | seqno = engine->get_seqno(engine); |
b4519513 | 3193 | |
12471ba8 CW |
3194 | /* Reset stuck interrupts between batch advances */ |
3195 | user_interrupts = 0; | |
3196 | ||
e2f80391 TU |
3197 | if (engine->hangcheck.seqno == seqno) { |
3198 | if (ring_idle(engine, seqno)) { | |
3199 | engine->hangcheck.action = HANGCHECK_IDLE; | |
e2f80391 | 3200 | if (waitqueue_active(&engine->irq_queue)) { |
094f9a54 | 3201 | /* Safeguard against driver failure */ |
12471ba8 | 3202 | user_interrupts = kick_waiters(engine); |
e2f80391 | 3203 | engine->hangcheck.score += BUSY; |
9107e9d2 CW |
3204 | } else |
3205 | busy = false; | |
05407ff8 | 3206 | } else { |
6274f212 CW |
3207 | /* We always increment the hangcheck score |
3208 | * if the ring is busy and still processing | |
3209 | * the same request, so that no single request | |
3210 | * can run indefinitely (such as a chain of | |
3211 | * batches). The only time we do not increment | |
3212 | * the hangcheck score on this ring, if this | |
3213 | * ring is in a legitimate wait for another | |
3214 | * ring. In that case the waiting ring is a | |
3215 | * victim and we want to be sure we catch the | |
3216 | * right culprit. Then every time we do kick | |
3217 | * the ring, add a small increment to the | |
3218 | * score so that we can catch a batch that is | |
3219 | * being repeatedly kicked and so responsible | |
3220 | * for stalling the machine. | |
3221 | */ | |
e2f80391 TU |
3222 | engine->hangcheck.action = ring_stuck(engine, |
3223 | acthd); | |
ad8beaea | 3224 | |
e2f80391 | 3225 | switch (engine->hangcheck.action) { |
da661464 | 3226 | case HANGCHECK_IDLE: |
f2f4d82f | 3227 | case HANGCHECK_WAIT: |
f260fe7b | 3228 | break; |
24a65e62 | 3229 | case HANGCHECK_ACTIVE: |
e2f80391 | 3230 | engine->hangcheck.score += BUSY; |
6274f212 | 3231 | break; |
f2f4d82f | 3232 | case HANGCHECK_KICK: |
e2f80391 | 3233 | engine->hangcheck.score += KICK; |
6274f212 | 3234 | break; |
f2f4d82f | 3235 | case HANGCHECK_HUNG: |
e2f80391 | 3236 | engine->hangcheck.score += HUNG; |
c3232b18 | 3237 | stuck[id] = true; |
6274f212 CW |
3238 | break; |
3239 | } | |
05407ff8 | 3240 | } |
9107e9d2 | 3241 | } else { |
e2f80391 | 3242 | engine->hangcheck.action = HANGCHECK_ACTIVE; |
da661464 | 3243 | |
9107e9d2 CW |
3244 | /* Gradually reduce the count so that we catch DoS |
3245 | * attempts across multiple batches. | |
3246 | */ | |
e2f80391 TU |
3247 | if (engine->hangcheck.score > 0) |
3248 | engine->hangcheck.score -= ACTIVE_DECAY; | |
3249 | if (engine->hangcheck.score < 0) | |
3250 | engine->hangcheck.score = 0; | |
f260fe7b | 3251 | |
61642ff0 | 3252 | /* Clear head and subunit states on seqno movement */ |
12471ba8 | 3253 | acthd = 0; |
61642ff0 | 3254 | |
e2f80391 TU |
3255 | memset(engine->hangcheck.instdone, 0, |
3256 | sizeof(engine->hangcheck.instdone)); | |
d1e61e7f CW |
3257 | } |
3258 | ||
e2f80391 TU |
3259 | engine->hangcheck.seqno = seqno; |
3260 | engine->hangcheck.acthd = acthd; | |
12471ba8 | 3261 | engine->hangcheck.user_interrupts = user_interrupts; |
9107e9d2 | 3262 | busy_count += busy; |
893eead0 | 3263 | } |
b9201c14 | 3264 | |
c3232b18 | 3265 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 3266 | if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d | 3267 | DRM_INFO("%s on %s\n", |
c3232b18 | 3268 | stuck[id] ? "stuck" : "no progress", |
e2f80391 | 3269 | engine->name); |
14b730fc | 3270 | rings_hung |= intel_engine_flag(engine); |
92cab734 MK |
3271 | } |
3272 | } | |
3273 | ||
1f814dac | 3274 | if (rings_hung) { |
14b730fc | 3275 | i915_handle_error(dev, rings_hung, "Engine(s) hung"); |
1f814dac ID |
3276 | goto out; |
3277 | } | |
f65d9421 | 3278 | |
05407ff8 MK |
3279 | if (busy_count) |
3280 | /* Reset timer case chip hangs without another request | |
3281 | * being added */ | |
10cd45b6 | 3282 | i915_queue_hangcheck(dev); |
1f814dac ID |
3283 | |
3284 | out: | |
3285 | ENABLE_RPM_WAKEREF_ASSERTS(dev_priv); | |
10cd45b6 MK |
3286 | } |
3287 | ||
3288 | void i915_queue_hangcheck(struct drm_device *dev) | |
3289 | { | |
737b1506 | 3290 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 3291 | |
d330a953 | 3292 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3293 | return; |
3294 | ||
737b1506 CW |
3295 | /* Don't continually defer the hangcheck so that it is always run at |
3296 | * least once after work has been scheduled on any ring. Otherwise, | |
3297 | * we will ignore a hung ring if a second ring is kept busy. | |
3298 | */ | |
3299 | ||
3300 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
3301 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3302 | } |
3303 | ||
1c69eb42 | 3304 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3305 | { |
3306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3307 | ||
3308 | if (HAS_PCH_NOP(dev)) | |
3309 | return; | |
3310 | ||
f86f3fb0 | 3311 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3312 | |
3313 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3314 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3315 | } |
105b122e | 3316 | |
622364b6 PZ |
3317 | /* |
3318 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3319 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3320 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3321 | * only unmask them as needed with SDEIMR. | |
3322 | * | |
3323 | * This function needs to be called before interrupts are enabled. | |
3324 | */ | |
3325 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3326 | { | |
3327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3328 | ||
3329 | if (HAS_PCH_NOP(dev)) | |
3330 | return; | |
3331 | ||
3332 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3333 | I915_WRITE(SDEIER, 0xffffffff); |
3334 | POSTING_READ(SDEIER); | |
3335 | } | |
3336 | ||
7c4d664e | 3337 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3338 | { |
3339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3340 | ||
f86f3fb0 | 3341 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3342 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3343 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3344 | } |
3345 | ||
70591a41 VS |
3346 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3347 | { | |
3348 | enum pipe pipe; | |
3349 | ||
71b8b41d VS |
3350 | if (IS_CHERRYVIEW(dev_priv)) |
3351 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); | |
3352 | else | |
3353 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3354 | ||
ad22d106 | 3355 | i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); |
70591a41 VS |
3356 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3357 | ||
ad22d106 VS |
3358 | for_each_pipe(dev_priv, pipe) { |
3359 | I915_WRITE(PIPESTAT(pipe), | |
3360 | PIPE_FIFO_UNDERRUN_STATUS | | |
3361 | PIPESTAT_INT_STATUS_MASK); | |
3362 | dev_priv->pipestat_irq_mask[pipe] = 0; | |
3363 | } | |
70591a41 VS |
3364 | |
3365 | GEN5_IRQ_RESET(VLV_); | |
ad22d106 | 3366 | dev_priv->irq_mask = ~0; |
70591a41 VS |
3367 | } |
3368 | ||
8bb61306 VS |
3369 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
3370 | { | |
3371 | u32 pipestat_mask; | |
9ab981f2 | 3372 | u32 enable_mask; |
8bb61306 VS |
3373 | enum pipe pipe; |
3374 | ||
8bb61306 VS |
3375 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | |
3376 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3377 | ||
3378 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); | |
3379 | for_each_pipe(dev_priv, pipe) | |
3380 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
3381 | ||
9ab981f2 VS |
3382 | enable_mask = I915_DISPLAY_PORT_INTERRUPT | |
3383 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3384 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
8bb61306 | 3385 | if (IS_CHERRYVIEW(dev_priv)) |
9ab981f2 | 3386 | enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; |
6b7eafc1 VS |
3387 | |
3388 | WARN_ON(dev_priv->irq_mask != ~0); | |
3389 | ||
9ab981f2 VS |
3390 | dev_priv->irq_mask = ~enable_mask; |
3391 | ||
3392 | GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask); | |
8bb61306 VS |
3393 | } |
3394 | ||
3395 | /* drm_dma.h hooks | |
3396 | */ | |
3397 | static void ironlake_irq_reset(struct drm_device *dev) | |
3398 | { | |
3399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3400 | ||
3401 | I915_WRITE(HWSTAM, 0xffffffff); | |
3402 | ||
3403 | GEN5_IRQ_RESET(DE); | |
3404 | if (IS_GEN7(dev)) | |
3405 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
3406 | ||
3407 | gen5_gt_irq_reset(dev); | |
3408 | ||
3409 | ibx_irq_reset(dev); | |
3410 | } | |
3411 | ||
7e231dbe JB |
3412 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3413 | { | |
2d1013dd | 3414 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3415 | |
34c7b8a7 VS |
3416 | I915_WRITE(VLV_MASTER_IER, 0); |
3417 | POSTING_READ(VLV_MASTER_IER); | |
3418 | ||
7c4d664e | 3419 | gen5_gt_irq_reset(dev); |
7e231dbe | 3420 | |
ad22d106 | 3421 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3422 | if (dev_priv->display_irqs_enabled) |
3423 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3424 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3425 | } |
3426 | ||
d6e3cca3 DV |
3427 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3428 | { | |
3429 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3430 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3431 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3432 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3433 | } | |
3434 | ||
823f6b38 | 3435 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3436 | { |
3437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3438 | int pipe; | |
3439 | ||
abd58f01 BW |
3440 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3441 | POSTING_READ(GEN8_MASTER_IRQ); | |
3442 | ||
d6e3cca3 | 3443 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3444 | |
055e393f | 3445 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3446 | if (intel_display_power_is_enabled(dev_priv, |
3447 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3448 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3449 | |
f86f3fb0 PZ |
3450 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3451 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3452 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3453 | |
266ea3d9 SS |
3454 | if (HAS_PCH_SPLIT(dev)) |
3455 | ibx_irq_reset(dev); | |
abd58f01 | 3456 | } |
09f2344d | 3457 | |
4c6c03be DL |
3458 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3459 | unsigned int pipe_mask) | |
d49bdb0e | 3460 | { |
1180e206 | 3461 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
6831f3e3 | 3462 | enum pipe pipe; |
d49bdb0e | 3463 | |
13321786 | 3464 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3465 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3466 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3467 | dev_priv->de_irq_mask[pipe], | |
3468 | ~dev_priv->de_irq_mask[pipe] | extra_ier); | |
13321786 | 3469 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3470 | } |
3471 | ||
aae8ba84 VS |
3472 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
3473 | unsigned int pipe_mask) | |
3474 | { | |
6831f3e3 VS |
3475 | enum pipe pipe; |
3476 | ||
aae8ba84 | 3477 | spin_lock_irq(&dev_priv->irq_lock); |
6831f3e3 VS |
3478 | for_each_pipe_masked(dev_priv, pipe, pipe_mask) |
3479 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); | |
aae8ba84 VS |
3480 | spin_unlock_irq(&dev_priv->irq_lock); |
3481 | ||
3482 | /* make sure we're done processing display irqs */ | |
3483 | synchronize_irq(dev_priv->dev->irq); | |
3484 | } | |
3485 | ||
43f328d7 VS |
3486 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3487 | { | |
3488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3489 | |
3490 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3491 | POSTING_READ(GEN8_MASTER_IRQ); | |
3492 | ||
d6e3cca3 | 3493 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3494 | |
3495 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3496 | ||
ad22d106 | 3497 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3498 | if (dev_priv->display_irqs_enabled) |
3499 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3500 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3501 | } |
3502 | ||
87a02106 VS |
3503 | static u32 intel_hpd_enabled_irqs(struct drm_device *dev, |
3504 | const u32 hpd[HPD_NUM_PINS]) | |
3505 | { | |
3506 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3507 | struct intel_encoder *encoder; | |
3508 | u32 enabled_irqs = 0; | |
3509 | ||
3510 | for_each_intel_encoder(dev, encoder) | |
3511 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) | |
3512 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3513 | ||
3514 | return enabled_irqs; | |
3515 | } | |
3516 | ||
82a28bcf | 3517 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3518 | { |
2d1013dd | 3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
87a02106 | 3520 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf DV |
3521 | |
3522 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3523 | hotplug_irqs = SDE_HOTPLUG_MASK; |
87a02106 | 3524 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx); |
82a28bcf | 3525 | } else { |
fee884ed | 3526 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
87a02106 | 3527 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt); |
82a28bcf | 3528 | } |
7fe0b973 | 3529 | |
fee884ed | 3530 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3531 | |
3532 | /* | |
3533 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3534 | * duration to 2ms (which is the minimum in the Display Port spec). |
3535 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3536 | */ |
7fe0b973 KP |
3537 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3538 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3539 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3540 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3541 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3542 | /* |
3543 | * When CPU and PCH are on the same package, port A | |
3544 | * HPD must be enabled in both north and south. | |
3545 | */ | |
3546 | if (HAS_PCH_LPT_LP(dev)) | |
3547 | hotplug |= PORTA_HOTPLUG_ENABLE; | |
7fe0b973 | 3548 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3549 | } |
26951caf | 3550 | |
6dbf30ce VS |
3551 | static void spt_hpd_irq_setup(struct drm_device *dev) |
3552 | { | |
3553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3554 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3555 | ||
3556 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3557 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt); | |
3558 | ||
3559 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3560 | ||
3561 | /* Enable digital hotplug on the PCH */ | |
3562 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3563 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
74c0b395 | 3564 | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; |
6dbf30ce VS |
3565 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3566 | ||
3567 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3568 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3569 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3570 | } |
3571 | ||
e4ce95aa VS |
3572 | static void ilk_hpd_irq_setup(struct drm_device *dev) |
3573 | { | |
3574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3575 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3576 | ||
3a3b3c7d VS |
3577 | if (INTEL_INFO(dev)->gen >= 8) { |
3578 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; | |
3579 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); | |
3580 | ||
3581 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3582 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
23bb4cb5 VS |
3583 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
3584 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); | |
3a3b3c7d VS |
3585 | |
3586 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3587 | } else { |
3588 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
3589 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk); | |
e4ce95aa | 3590 | |
3a3b3c7d VS |
3591 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3592 | } | |
e4ce95aa VS |
3593 | |
3594 | /* | |
3595 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3596 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3597 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3598 | */ |
3599 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3600 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3601 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3602 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3603 | ||
3604 | ibx_hpd_irq_setup(dev); | |
3605 | } | |
3606 | ||
e0a20ad7 SS |
3607 | static void bxt_hpd_irq_setup(struct drm_device *dev) |
3608 | { | |
3609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a52bb15b | 3610 | u32 hotplug_irqs, hotplug, enabled_irqs; |
e0a20ad7 | 3611 | |
a52bb15b VS |
3612 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt); |
3613 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
e0a20ad7 | 3614 | |
a52bb15b | 3615 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
e0a20ad7 | 3616 | |
a52bb15b VS |
3617 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3618 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | | |
3619 | PORTA_HOTPLUG_ENABLE; | |
d252bf68 SS |
3620 | |
3621 | DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n", | |
3622 | hotplug, enabled_irqs); | |
3623 | hotplug &= ~BXT_DDI_HPD_INVERT_MASK; | |
3624 | ||
3625 | /* | |
3626 | * For BXT invert bit has to be set based on AOB design | |
3627 | * for HPD detection logic, update it based on VBT fields. | |
3628 | */ | |
3629 | ||
3630 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) && | |
3631 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) | |
3632 | hotplug |= BXT_DDIA_HPD_INVERT; | |
3633 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) && | |
3634 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) | |
3635 | hotplug |= BXT_DDIB_HPD_INVERT; | |
3636 | if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) && | |
3637 | intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) | |
3638 | hotplug |= BXT_DDIC_HPD_INVERT; | |
3639 | ||
a52bb15b | 3640 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
e0a20ad7 SS |
3641 | } |
3642 | ||
d46da437 PZ |
3643 | static void ibx_irq_postinstall(struct drm_device *dev) |
3644 | { | |
2d1013dd | 3645 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3646 | u32 mask; |
e5868a31 | 3647 | |
692a04cf DV |
3648 | if (HAS_PCH_NOP(dev)) |
3649 | return; | |
3650 | ||
105b122e | 3651 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3652 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3653 | else |
5c673b60 | 3654 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3655 | |
b51a2842 | 3656 | gen5_assert_iir_is_zero(dev_priv, SDEIIR); |
d46da437 | 3657 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3658 | } |
3659 | ||
0a9a8c91 DV |
3660 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3661 | { | |
3662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3663 | u32 pm_irqs, gt_irqs; | |
3664 | ||
3665 | pm_irqs = gt_irqs = 0; | |
3666 | ||
3667 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3668 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3669 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3670 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3671 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3672 | } |
3673 | ||
3674 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3675 | if (IS_GEN5(dev)) { | |
3676 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3677 | ILK_BSD_USER_INTERRUPT; | |
3678 | } else { | |
3679 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3680 | } | |
3681 | ||
35079899 | 3682 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3683 | |
3684 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3685 | /* |
3686 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3687 | * itself is enabled/disabled. | |
3688 | */ | |
0a9a8c91 DV |
3689 | if (HAS_VEBOX(dev)) |
3690 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3691 | ||
605cd25b | 3692 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3693 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3694 | } |
3695 | } | |
3696 | ||
f71d4af4 | 3697 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3698 | { |
2d1013dd | 3699 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3700 | u32 display_mask, extra_mask; |
3701 | ||
3702 | if (INTEL_INFO(dev)->gen >= 7) { | |
3703 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3704 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3705 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3706 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3707 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3708 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3709 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3710 | } else { |
3711 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3712 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3713 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3714 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3715 | DE_POISON); | |
e4ce95aa VS |
3716 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3717 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3718 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3719 | } |
036a4a7d | 3720 | |
1ec14ad3 | 3721 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3722 | |
0c841212 PZ |
3723 | I915_WRITE(HWSTAM, 0xeffe); |
3724 | ||
622364b6 PZ |
3725 | ibx_irq_pre_postinstall(dev); |
3726 | ||
35079899 | 3727 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3728 | |
0a9a8c91 | 3729 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3730 | |
d46da437 | 3731 | ibx_irq_postinstall(dev); |
7fe0b973 | 3732 | |
f97108d1 | 3733 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3734 | /* Enable PCU event interrupts |
3735 | * | |
3736 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3737 | * setup is guaranteed to run in single-threaded context. But we |
3738 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3739 | spin_lock_irq(&dev_priv->irq_lock); |
fbdedaea | 3740 | ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3741 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3742 | } |
3743 | ||
036a4a7d ZW |
3744 | return 0; |
3745 | } | |
3746 | ||
f8b79e58 ID |
3747 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) |
3748 | { | |
3749 | assert_spin_locked(&dev_priv->irq_lock); | |
3750 | ||
3751 | if (dev_priv->display_irqs_enabled) | |
3752 | return; | |
3753 | ||
3754 | dev_priv->display_irqs_enabled = true; | |
3755 | ||
d6c69803 VS |
3756 | if (intel_irqs_enabled(dev_priv)) { |
3757 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3758 | vlv_display_irq_postinstall(dev_priv); |
d6c69803 | 3759 | } |
f8b79e58 ID |
3760 | } |
3761 | ||
3762 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3763 | { | |
3764 | assert_spin_locked(&dev_priv->irq_lock); | |
3765 | ||
3766 | if (!dev_priv->display_irqs_enabled) | |
3767 | return; | |
3768 | ||
3769 | dev_priv->display_irqs_enabled = false; | |
3770 | ||
950eabaf | 3771 | if (intel_irqs_enabled(dev_priv)) |
ad22d106 | 3772 | vlv_display_irq_reset(dev_priv); |
f8b79e58 ID |
3773 | } |
3774 | ||
0e6c9a9e VS |
3775 | |
3776 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3777 | { | |
3778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3779 | ||
0a9a8c91 | 3780 | gen5_gt_irq_postinstall(dev); |
7e231dbe | 3781 | |
ad22d106 | 3782 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3783 | if (dev_priv->display_irqs_enabled) |
3784 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3785 | spin_unlock_irq(&dev_priv->irq_lock); |
3786 | ||
7e231dbe | 3787 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); |
34c7b8a7 | 3788 | POSTING_READ(VLV_MASTER_IER); |
20afbda2 DV |
3789 | |
3790 | return 0; | |
3791 | } | |
3792 | ||
abd58f01 BW |
3793 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3794 | { | |
abd58f01 BW |
3795 | /* These are interrupts we'll toggle with the ring mask register */ |
3796 | uint32_t gt_interrupts[] = { | |
3797 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3798 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
73d477f6 OM |
3799 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3800 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3801 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3802 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3803 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3804 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3805 | 0, |
73d477f6 OM |
3806 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3807 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3808 | }; |
3809 | ||
98735739 TU |
3810 | if (HAS_L3_DPF(dev_priv)) |
3811 | gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
3812 | ||
0961021a | 3813 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3814 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3815 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3816 | /* |
3817 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3818 | * is enabled/disabled. | |
3819 | */ | |
3820 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3821 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3822 | } |
3823 | ||
3824 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3825 | { | |
770de83d DL |
3826 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3827 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3828 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3829 | u32 de_port_enables; | |
3830 | enum pipe pipe; | |
770de83d | 3831 | |
b4834a50 | 3832 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3833 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3834 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3835 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3836 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3837 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3838 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3839 | } else { | |
770de83d DL |
3840 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3841 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3842 | } |
770de83d DL |
3843 | |
3844 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3845 | GEN8_PIPE_FIFO_UNDERRUN; | |
3846 | ||
3a3b3c7d | 3847 | de_port_enables = de_port_masked; |
a52bb15b VS |
3848 | if (IS_BROXTON(dev_priv)) |
3849 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3850 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3851 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3852 | ||
13b3a0a7 DV |
3853 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3854 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3855 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3856 | |
055e393f | 3857 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3858 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3859 | POWER_DOMAIN_PIPE(pipe))) |
3860 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3861 | dev_priv->de_irq_mask[pipe], | |
3862 | de_pipe_enables); | |
abd58f01 | 3863 | |
3a3b3c7d | 3864 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
abd58f01 BW |
3865 | } |
3866 | ||
3867 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3868 | { | |
3869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3870 | ||
266ea3d9 SS |
3871 | if (HAS_PCH_SPLIT(dev)) |
3872 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3873 | |
abd58f01 BW |
3874 | gen8_gt_irq_postinstall(dev_priv); |
3875 | gen8_de_irq_postinstall(dev_priv); | |
3876 | ||
266ea3d9 SS |
3877 | if (HAS_PCH_SPLIT(dev)) |
3878 | ibx_irq_postinstall(dev); | |
abd58f01 | 3879 | |
e5328c43 | 3880 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
abd58f01 BW |
3881 | POSTING_READ(GEN8_MASTER_IRQ); |
3882 | ||
3883 | return 0; | |
3884 | } | |
3885 | ||
43f328d7 VS |
3886 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3887 | { | |
3888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3889 | |
43f328d7 VS |
3890 | gen8_gt_irq_postinstall(dev_priv); |
3891 | ||
ad22d106 | 3892 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3893 | if (dev_priv->display_irqs_enabled) |
3894 | vlv_display_irq_postinstall(dev_priv); | |
ad22d106 VS |
3895 | spin_unlock_irq(&dev_priv->irq_lock); |
3896 | ||
e5328c43 | 3897 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
43f328d7 VS |
3898 | POSTING_READ(GEN8_MASTER_IRQ); |
3899 | ||
3900 | return 0; | |
3901 | } | |
3902 | ||
abd58f01 BW |
3903 | static void gen8_irq_uninstall(struct drm_device *dev) |
3904 | { | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3906 | |
3907 | if (!dev_priv) | |
3908 | return; | |
3909 | ||
823f6b38 | 3910 | gen8_irq_reset(dev); |
abd58f01 BW |
3911 | } |
3912 | ||
7e231dbe JB |
3913 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3914 | { | |
2d1013dd | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3916 | |
3917 | if (!dev_priv) | |
3918 | return; | |
3919 | ||
843d0e7d | 3920 | I915_WRITE(VLV_MASTER_IER, 0); |
34c7b8a7 | 3921 | POSTING_READ(VLV_MASTER_IER); |
843d0e7d | 3922 | |
893fce8e VS |
3923 | gen5_gt_irq_reset(dev); |
3924 | ||
7e231dbe | 3925 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3926 | |
ad22d106 | 3927 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3928 | if (dev_priv->display_irqs_enabled) |
3929 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3930 | spin_unlock_irq(&dev_priv->irq_lock); |
7e231dbe JB |
3931 | } |
3932 | ||
43f328d7 VS |
3933 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3934 | { | |
3935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3936 | |
3937 | if (!dev_priv) | |
3938 | return; | |
3939 | ||
3940 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3941 | POSTING_READ(GEN8_MASTER_IRQ); | |
3942 | ||
a2c30fba | 3943 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3944 | |
a2c30fba | 3945 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3946 | |
ad22d106 | 3947 | spin_lock_irq(&dev_priv->irq_lock); |
9918271e VS |
3948 | if (dev_priv->display_irqs_enabled) |
3949 | vlv_display_irq_reset(dev_priv); | |
ad22d106 | 3950 | spin_unlock_irq(&dev_priv->irq_lock); |
43f328d7 VS |
3951 | } |
3952 | ||
f71d4af4 | 3953 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3954 | { |
2d1013dd | 3955 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3956 | |
3957 | if (!dev_priv) | |
3958 | return; | |
3959 | ||
be30b29f | 3960 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3961 | } |
3962 | ||
a266c7d5 | 3963 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3964 | { |
2d1013dd | 3965 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3966 | int pipe; |
91e3738e | 3967 | |
055e393f | 3968 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3969 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3970 | I915_WRITE16(IMR, 0xffff); |
3971 | I915_WRITE16(IER, 0x0); | |
3972 | POSTING_READ16(IER); | |
c2798b19 CW |
3973 | } |
3974 | ||
3975 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3976 | { | |
2d1013dd | 3977 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3978 | |
c2798b19 CW |
3979 | I915_WRITE16(EMR, |
3980 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3981 | ||
3982 | /* Unmask the interrupts that we always want on. */ | |
3983 | dev_priv->irq_mask = | |
3984 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3985 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3986 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3987 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3988 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3989 | ||
3990 | I915_WRITE16(IER, | |
3991 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3992 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3993 | I915_USER_INTERRUPT); |
3994 | POSTING_READ16(IER); | |
3995 | ||
379ef82d DV |
3996 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3997 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3998 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3999 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4000 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4001 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4002 | |
c2798b19 CW |
4003 | return 0; |
4004 | } | |
4005 | ||
90a72f87 VS |
4006 | /* |
4007 | * Returns true when a page flip has completed. | |
4008 | */ | |
4009 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 4010 | int plane, int pipe, u32 iir) |
90a72f87 | 4011 | { |
2d1013dd | 4012 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 4013 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 4014 | |
8d7849db | 4015 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
4016 | return false; |
4017 | ||
4018 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4019 | goto check_page_flip; |
90a72f87 | 4020 | |
90a72f87 VS |
4021 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
4022 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4023 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4024 | * the flip is completed (no longer pending). Since this doesn't raise | |
4025 | * an interrupt per se, we watch for the change at vblank. | |
4026 | */ | |
4027 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 4028 | goto check_page_flip; |
90a72f87 | 4029 | |
7d47559e | 4030 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 4031 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 4032 | return true; |
d6bbafa1 CW |
4033 | |
4034 | check_page_flip: | |
4035 | intel_check_page_flip(dev, pipe); | |
4036 | return false; | |
90a72f87 VS |
4037 | } |
4038 | ||
ff1f525e | 4039 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 4040 | { |
45a83f84 | 4041 | struct drm_device *dev = arg; |
2d1013dd | 4042 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4043 | u16 iir, new_iir; |
4044 | u32 pipe_stats[2]; | |
c2798b19 CW |
4045 | int pipe; |
4046 | u16 flip_mask = | |
4047 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4048 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
1f814dac | 4049 | irqreturn_t ret; |
c2798b19 | 4050 | |
2dd2a883 ID |
4051 | if (!intel_irqs_enabled(dev_priv)) |
4052 | return IRQ_NONE; | |
4053 | ||
1f814dac ID |
4054 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4055 | disable_rpm_wakeref_asserts(dev_priv); | |
4056 | ||
4057 | ret = IRQ_NONE; | |
c2798b19 CW |
4058 | iir = I915_READ16(IIR); |
4059 | if (iir == 0) | |
1f814dac | 4060 | goto out; |
c2798b19 CW |
4061 | |
4062 | while (iir & ~flip_mask) { | |
4063 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4064 | * have been cleared after the pipestat interrupt was received. | |
4065 | * It doesn't set the bit in iir again, but it still produces | |
4066 | * interrupts (for non-MSI). | |
4067 | */ | |
222c7f51 | 4068 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 4069 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4070 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 4071 | |
055e393f | 4072 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4073 | i915_reg_t reg = PIPESTAT(pipe); |
c2798b19 CW |
4074 | pipe_stats[pipe] = I915_READ(reg); |
4075 | ||
4076 | /* | |
4077 | * Clear the PIPE*STAT regs before the IIR | |
4078 | */ | |
2d9d2b0b | 4079 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 4080 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 4081 | } |
222c7f51 | 4082 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
4083 | |
4084 | I915_WRITE16(IIR, iir & ~flip_mask); | |
4085 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
4086 | ||
c2798b19 | 4087 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4088 | notify_ring(&dev_priv->engine[RCS]); |
c2798b19 | 4089 | |
055e393f | 4090 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 4091 | int plane = pipe; |
3a77c4c4 | 4092 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
4093 | plane = !plane; |
4094 | ||
4356d586 | 4095 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
4096 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
4097 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 4098 | |
4356d586 | 4099 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 4100 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 4101 | |
1f7247c0 DV |
4102 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4103 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4104 | pipe); | |
4356d586 | 4105 | } |
c2798b19 CW |
4106 | |
4107 | iir = new_iir; | |
4108 | } | |
1f814dac ID |
4109 | ret = IRQ_HANDLED; |
4110 | ||
4111 | out: | |
4112 | enable_rpm_wakeref_asserts(dev_priv); | |
c2798b19 | 4113 | |
1f814dac | 4114 | return ret; |
c2798b19 CW |
4115 | } |
4116 | ||
4117 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
4118 | { | |
2d1013dd | 4119 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
4120 | int pipe; |
4121 | ||
055e393f | 4122 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
4123 | /* Clear enable bits; then clear status bits */ |
4124 | I915_WRITE(PIPESTAT(pipe), 0); | |
4125 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
4126 | } | |
4127 | I915_WRITE16(IMR, 0xffff); | |
4128 | I915_WRITE16(IER, 0x0); | |
4129 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
4130 | } | |
4131 | ||
a266c7d5 CW |
4132 | static void i915_irq_preinstall(struct drm_device * dev) |
4133 | { | |
2d1013dd | 4134 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4135 | int pipe; |
4136 | ||
a266c7d5 | 4137 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4138 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4139 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4140 | } | |
4141 | ||
00d98ebd | 4142 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 4143 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4144 | I915_WRITE(PIPESTAT(pipe), 0); |
4145 | I915_WRITE(IMR, 0xffffffff); | |
4146 | I915_WRITE(IER, 0x0); | |
4147 | POSTING_READ(IER); | |
4148 | } | |
4149 | ||
4150 | static int i915_irq_postinstall(struct drm_device *dev) | |
4151 | { | |
2d1013dd | 4152 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 4153 | u32 enable_mask; |
a266c7d5 | 4154 | |
38bde180 CW |
4155 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
4156 | ||
4157 | /* Unmask the interrupts that we always want on. */ | |
4158 | dev_priv->irq_mask = | |
4159 | ~(I915_ASLE_INTERRUPT | | |
4160 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4161 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4162 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 4163 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
4164 | |
4165 | enable_mask = | |
4166 | I915_ASLE_INTERRUPT | | |
4167 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
4168 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
4169 | I915_USER_INTERRUPT; |
4170 | ||
a266c7d5 | 4171 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4172 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4173 | POSTING_READ(PORT_HOTPLUG_EN); |
4174 | ||
a266c7d5 CW |
4175 | /* Enable in IER... */ |
4176 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
4177 | /* and unmask in IMR */ | |
4178 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
4179 | } | |
4180 | ||
a266c7d5 CW |
4181 | I915_WRITE(IMR, dev_priv->irq_mask); |
4182 | I915_WRITE(IER, enable_mask); | |
4183 | POSTING_READ(IER); | |
4184 | ||
f49e38dd | 4185 | i915_enable_asle_pipestat(dev); |
20afbda2 | 4186 | |
379ef82d DV |
4187 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4188 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4189 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4190 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
4191 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4192 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 4193 | |
20afbda2 DV |
4194 | return 0; |
4195 | } | |
4196 | ||
90a72f87 VS |
4197 | /* |
4198 | * Returns true when a page flip has completed. | |
4199 | */ | |
4200 | static bool i915_handle_vblank(struct drm_device *dev, | |
4201 | int plane, int pipe, u32 iir) | |
4202 | { | |
2d1013dd | 4203 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
4204 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
4205 | ||
8d7849db | 4206 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
4207 | return false; |
4208 | ||
4209 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 4210 | goto check_page_flip; |
90a72f87 | 4211 | |
90a72f87 VS |
4212 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
4213 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
4214 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
4215 | * the flip is completed (no longer pending). Since this doesn't raise | |
4216 | * an interrupt per se, we watch for the change at vblank. | |
4217 | */ | |
4218 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 4219 | goto check_page_flip; |
90a72f87 | 4220 | |
7d47559e | 4221 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 4222 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 4223 | return true; |
d6bbafa1 CW |
4224 | |
4225 | check_page_flip: | |
4226 | intel_check_page_flip(dev, pipe); | |
4227 | return false; | |
90a72f87 VS |
4228 | } |
4229 | ||
ff1f525e | 4230 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 4231 | { |
45a83f84 | 4232 | struct drm_device *dev = arg; |
2d1013dd | 4233 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 4234 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
4235 | u32 flip_mask = |
4236 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4237 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 4238 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 4239 | |
2dd2a883 ID |
4240 | if (!intel_irqs_enabled(dev_priv)) |
4241 | return IRQ_NONE; | |
4242 | ||
1f814dac ID |
4243 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4244 | disable_rpm_wakeref_asserts(dev_priv); | |
4245 | ||
a266c7d5 | 4246 | iir = I915_READ(IIR); |
38bde180 CW |
4247 | do { |
4248 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 4249 | bool blc_event = false; |
a266c7d5 CW |
4250 | |
4251 | /* Can't rely on pipestat interrupt bit in iir as it might | |
4252 | * have been cleared after the pipestat interrupt was received. | |
4253 | * It doesn't set the bit in iir again, but it still produces | |
4254 | * interrupts (for non-MSI). | |
4255 | */ | |
222c7f51 | 4256 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4257 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4258 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4259 | |
055e393f | 4260 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4261 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4262 | pipe_stats[pipe] = I915_READ(reg); |
4263 | ||
38bde180 | 4264 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4265 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4266 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4267 | irq_received = true; |
a266c7d5 CW |
4268 | } |
4269 | } | |
222c7f51 | 4270 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4271 | |
4272 | if (!irq_received) | |
4273 | break; | |
4274 | ||
a266c7d5 | 4275 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b | 4276 | if (I915_HAS_HOTPLUG(dev) && |
1ae3c34c VS |
4277 | iir & I915_DISPLAY_PORT_INTERRUPT) { |
4278 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4279 | if (hotplug_status) | |
4280 | i9xx_hpd_irq_handler(dev, hotplug_status); | |
4281 | } | |
a266c7d5 | 4282 | |
38bde180 | 4283 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4284 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4285 | ||
a266c7d5 | 4286 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4287 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4288 | |
055e393f | 4289 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 4290 | int plane = pipe; |
3a77c4c4 | 4291 | if (HAS_FBC(dev)) |
38bde180 | 4292 | plane = !plane; |
90a72f87 | 4293 | |
8291ee90 | 4294 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4295 | i915_handle_vblank(dev, plane, pipe, iir)) |
4296 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4297 | |
4298 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4299 | blc_event = true; | |
4356d586 DV |
4300 | |
4301 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4302 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 4303 | |
1f7247c0 DV |
4304 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4305 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4306 | pipe); | |
a266c7d5 CW |
4307 | } |
4308 | ||
a266c7d5 CW |
4309 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
4310 | intel_opregion_asle_intr(dev); | |
4311 | ||
4312 | /* With MSI, interrupts are only generated when iir | |
4313 | * transitions from zero to nonzero. If another bit got | |
4314 | * set while we were handling the existing iir bits, then | |
4315 | * we would never get another interrupt. | |
4316 | * | |
4317 | * This is fine on non-MSI as well, as if we hit this path | |
4318 | * we avoid exiting the interrupt handler only to generate | |
4319 | * another one. | |
4320 | * | |
4321 | * Note that for MSI this could cause a stray interrupt report | |
4322 | * if an interrupt landed in the time between writing IIR and | |
4323 | * the posting read. This should be rare enough to never | |
4324 | * trigger the 99% of 100,000 interrupts test for disabling | |
4325 | * stray interrupts. | |
4326 | */ | |
38bde180 | 4327 | ret = IRQ_HANDLED; |
a266c7d5 | 4328 | iir = new_iir; |
38bde180 | 4329 | } while (iir & ~flip_mask); |
a266c7d5 | 4330 | |
1f814dac ID |
4331 | enable_rpm_wakeref_asserts(dev_priv); |
4332 | ||
a266c7d5 CW |
4333 | return ret; |
4334 | } | |
4335 | ||
4336 | static void i915_irq_uninstall(struct drm_device * dev) | |
4337 | { | |
2d1013dd | 4338 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4339 | int pipe; |
4340 | ||
a266c7d5 | 4341 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4342 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4343 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4344 | } | |
4345 | ||
00d98ebd | 4346 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4347 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4348 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4349 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4350 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4351 | } | |
a266c7d5 CW |
4352 | I915_WRITE(IMR, 0xffffffff); |
4353 | I915_WRITE(IER, 0x0); | |
4354 | ||
a266c7d5 CW |
4355 | I915_WRITE(IIR, I915_READ(IIR)); |
4356 | } | |
4357 | ||
4358 | static void i965_irq_preinstall(struct drm_device * dev) | |
4359 | { | |
2d1013dd | 4360 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4361 | int pipe; |
4362 | ||
0706f17c | 4363 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4364 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4365 | |
4366 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4367 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4368 | I915_WRITE(PIPESTAT(pipe), 0); |
4369 | I915_WRITE(IMR, 0xffffffff); | |
4370 | I915_WRITE(IER, 0x0); | |
4371 | POSTING_READ(IER); | |
4372 | } | |
4373 | ||
4374 | static int i965_irq_postinstall(struct drm_device *dev) | |
4375 | { | |
2d1013dd | 4376 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4377 | u32 enable_mask; |
a266c7d5 CW |
4378 | u32 error_mask; |
4379 | ||
a266c7d5 | 4380 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4381 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4382 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4383 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4384 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4385 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4386 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4387 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4388 | ||
4389 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4390 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4391 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4392 | enable_mask |= I915_USER_INTERRUPT; |
4393 | ||
4394 | if (IS_G4X(dev)) | |
4395 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4396 | |
b79480ba DV |
4397 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4398 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4399 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4400 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4401 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4402 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4403 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4404 | |
a266c7d5 CW |
4405 | /* |
4406 | * Enable some error detection, note the instruction error mask | |
4407 | * bit is reserved, so we leave it masked. | |
4408 | */ | |
4409 | if (IS_G4X(dev)) { | |
4410 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4411 | GM45_ERROR_MEM_PRIV | | |
4412 | GM45_ERROR_CP_PRIV | | |
4413 | I915_ERROR_MEMORY_REFRESH); | |
4414 | } else { | |
4415 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4416 | I915_ERROR_MEMORY_REFRESH); | |
4417 | } | |
4418 | I915_WRITE(EMR, error_mask); | |
4419 | ||
4420 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4421 | I915_WRITE(IER, enable_mask); | |
4422 | POSTING_READ(IER); | |
4423 | ||
0706f17c | 4424 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4425 | POSTING_READ(PORT_HOTPLUG_EN); |
4426 | ||
f49e38dd | 4427 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4428 | |
4429 | return 0; | |
4430 | } | |
4431 | ||
bac56d5b | 4432 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4433 | { |
2d1013dd | 4434 | struct drm_i915_private *dev_priv = dev->dev_private; |
20afbda2 DV |
4435 | u32 hotplug_en; |
4436 | ||
b5ea2d56 DV |
4437 | assert_spin_locked(&dev_priv->irq_lock); |
4438 | ||
778eb334 VS |
4439 | /* Note HDMI and DP share hotplug bits */ |
4440 | /* enable bits are the same for all generations */ | |
0706f17c | 4441 | hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915); |
778eb334 VS |
4442 | /* Programming the CRT detection parameters tends |
4443 | to generate a spurious hotplug event about three | |
4444 | seconds later. So just do it once. | |
4445 | */ | |
4446 | if (IS_G4X(dev)) | |
4447 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
778eb334 VS |
4448 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4449 | ||
4450 | /* Ignore TV since it's buggy */ | |
0706f17c | 4451 | i915_hotplug_interrupt_update_locked(dev_priv, |
f9e3dc78 JN |
4452 | HOTPLUG_INT_EN_MASK | |
4453 | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | | |
4454 | CRT_HOTPLUG_ACTIVATION_PERIOD_64, | |
4455 | hotplug_en); | |
a266c7d5 CW |
4456 | } |
4457 | ||
ff1f525e | 4458 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4459 | { |
45a83f84 | 4460 | struct drm_device *dev = arg; |
2d1013dd | 4461 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4462 | u32 iir, new_iir; |
4463 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4464 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4465 | u32 flip_mask = |
4466 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4467 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4468 | |
2dd2a883 ID |
4469 | if (!intel_irqs_enabled(dev_priv)) |
4470 | return IRQ_NONE; | |
4471 | ||
1f814dac ID |
4472 | /* IRQs are synced during runtime_suspend, we don't require a wakeref */ |
4473 | disable_rpm_wakeref_asserts(dev_priv); | |
4474 | ||
a266c7d5 CW |
4475 | iir = I915_READ(IIR); |
4476 | ||
a266c7d5 | 4477 | for (;;) { |
501e01d7 | 4478 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4479 | bool blc_event = false; |
4480 | ||
a266c7d5 CW |
4481 | /* Can't rely on pipestat interrupt bit in iir as it might |
4482 | * have been cleared after the pipestat interrupt was received. | |
4483 | * It doesn't set the bit in iir again, but it still produces | |
4484 | * interrupts (for non-MSI). | |
4485 | */ | |
222c7f51 | 4486 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4487 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4488 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4489 | |
055e393f | 4490 | for_each_pipe(dev_priv, pipe) { |
f0f59a00 | 4491 | i915_reg_t reg = PIPESTAT(pipe); |
a266c7d5 CW |
4492 | pipe_stats[pipe] = I915_READ(reg); |
4493 | ||
4494 | /* | |
4495 | * Clear the PIPE*STAT regs before the IIR | |
4496 | */ | |
4497 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4498 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4499 | irq_received = true; |
a266c7d5 CW |
4500 | } |
4501 | } | |
222c7f51 | 4502 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4503 | |
4504 | if (!irq_received) | |
4505 | break; | |
4506 | ||
4507 | ret = IRQ_HANDLED; | |
4508 | ||
4509 | /* Consume port. Then clear IIR or we'll miss events */ | |
1ae3c34c VS |
4510 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
4511 | u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv); | |
4512 | if (hotplug_status) | |
4513 | i9xx_hpd_irq_handler(dev, hotplug_status); | |
4514 | } | |
a266c7d5 | 4515 | |
21ad8330 | 4516 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4517 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4518 | ||
a266c7d5 | 4519 | if (iir & I915_USER_INTERRUPT) |
4a570db5 | 4520 | notify_ring(&dev_priv->engine[RCS]); |
a266c7d5 | 4521 | if (iir & I915_BSD_USER_INTERRUPT) |
4a570db5 | 4522 | notify_ring(&dev_priv->engine[VCS]); |
a266c7d5 | 4523 | |
055e393f | 4524 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4525 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4526 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4527 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4528 | |
4529 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4530 | blc_event = true; | |
4356d586 DV |
4531 | |
4532 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4533 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4534 | |
1f7247c0 DV |
4535 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4536 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4537 | } |
a266c7d5 CW |
4538 | |
4539 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4540 | intel_opregion_asle_intr(dev); | |
4541 | ||
515ac2bb DV |
4542 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4543 | gmbus_irq_handler(dev); | |
4544 | ||
a266c7d5 CW |
4545 | /* With MSI, interrupts are only generated when iir |
4546 | * transitions from zero to nonzero. If another bit got | |
4547 | * set while we were handling the existing iir bits, then | |
4548 | * we would never get another interrupt. | |
4549 | * | |
4550 | * This is fine on non-MSI as well, as if we hit this path | |
4551 | * we avoid exiting the interrupt handler only to generate | |
4552 | * another one. | |
4553 | * | |
4554 | * Note that for MSI this could cause a stray interrupt report | |
4555 | * if an interrupt landed in the time between writing IIR and | |
4556 | * the posting read. This should be rare enough to never | |
4557 | * trigger the 99% of 100,000 interrupts test for disabling | |
4558 | * stray interrupts. | |
4559 | */ | |
4560 | iir = new_iir; | |
4561 | } | |
4562 | ||
1f814dac ID |
4563 | enable_rpm_wakeref_asserts(dev_priv); |
4564 | ||
a266c7d5 CW |
4565 | return ret; |
4566 | } | |
4567 | ||
4568 | static void i965_irq_uninstall(struct drm_device * dev) | |
4569 | { | |
2d1013dd | 4570 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4571 | int pipe; |
4572 | ||
4573 | if (!dev_priv) | |
4574 | return; | |
4575 | ||
0706f17c | 4576 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4577 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4578 | |
4579 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4580 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4581 | I915_WRITE(PIPESTAT(pipe), 0); |
4582 | I915_WRITE(IMR, 0xffffffff); | |
4583 | I915_WRITE(IER, 0x0); | |
4584 | ||
055e393f | 4585 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4586 | I915_WRITE(PIPESTAT(pipe), |
4587 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4588 | I915_WRITE(IIR, I915_READ(IIR)); | |
4589 | } | |
4590 | ||
fca52a55 DV |
4591 | /** |
4592 | * intel_irq_init - initializes irq support | |
4593 | * @dev_priv: i915 device instance | |
4594 | * | |
4595 | * This function initializes all the irq support including work items, timers | |
4596 | * and all the vtables. It does not setup the interrupt itself though. | |
4597 | */ | |
b963291c | 4598 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4599 | { |
b963291c | 4600 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4601 | |
77913b39 JN |
4602 | intel_hpd_init_work(dev_priv); |
4603 | ||
c6a828d3 | 4604 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4605 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4606 | |
a6706b45 | 4607 | /* Let's track the enabled rps events */ |
666a4537 | 4608 | if (IS_VALLEYVIEW(dev_priv)) |
6c65a587 | 4609 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4610 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4611 | else |
4612 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4613 | |
737b1506 CW |
4614 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4615 | i915_hangcheck_elapsed); | |
61bac78e | 4616 | |
b963291c | 4617 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4618 | dev->max_vblank_count = 0; |
4619 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4620 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 | 4621 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
fd8f507c | 4622 | dev->driver->get_vblank_counter = g4x_get_vblank_counter; |
391f75e2 VS |
4623 | } else { |
4624 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4625 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4626 | } |
4627 | ||
21da2700 VS |
4628 | /* |
4629 | * Opt out of the vblank disable timer on everything except gen2. | |
4630 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4631 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4632 | */ | |
b963291c | 4633 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4634 | dev->vblank_disable_immediate = true; |
4635 | ||
f3a5c3f6 DV |
4636 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4637 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4638 | |
b963291c | 4639 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4640 | dev->driver->irq_handler = cherryview_irq_handler; |
4641 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4642 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4643 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4644 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4645 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4646 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4647 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4648 | dev->driver->irq_handler = valleyview_irq_handler; |
4649 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4650 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4651 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4652 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4653 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4654 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4655 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4656 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4657 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4658 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4659 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4660 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4661 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4662 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4663 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
bc7135b9 | 4664 | else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev)) |
6dbf30ce VS |
4665 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; |
4666 | else | |
3a3b3c7d | 4667 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4668 | } else if (HAS_PCH_SPLIT(dev)) { |
4669 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4670 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4671 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4672 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4673 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4674 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4675 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4676 | } else { |
b963291c | 4677 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4678 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4679 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4680 | dev->driver->irq_handler = i8xx_irq_handler; | |
4681 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4682 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4683 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4684 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4685 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4686 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4687 | } else { |
a266c7d5 CW |
4688 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4689 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4690 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4691 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4692 | } |
778eb334 VS |
4693 | if (I915_HAS_HOTPLUG(dev_priv)) |
4694 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4695 | dev->driver->enable_vblank = i915_enable_vblank; |
4696 | dev->driver->disable_vblank = i915_disable_vblank; | |
4697 | } | |
4698 | } | |
20afbda2 | 4699 | |
fca52a55 DV |
4700 | /** |
4701 | * intel_irq_install - enables the hardware interrupt | |
4702 | * @dev_priv: i915 device instance | |
4703 | * | |
4704 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4705 | * handling still disabled. It is called after intel_irq_init(). | |
4706 | * | |
4707 | * In the driver load and resume code we need working interrupts in a few places | |
4708 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4709 | * workers. Hence the split into this two-stage approach. | |
4710 | */ | |
2aeb7d3a DV |
4711 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4712 | { | |
4713 | /* | |
4714 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4715 | * interrupts as enabled _before_ actually enabling them to avoid | |
4716 | * special cases in our ordering checks. | |
4717 | */ | |
4718 | dev_priv->pm.irqs_enabled = true; | |
4719 | ||
4720 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4721 | } | |
4722 | ||
fca52a55 DV |
4723 | /** |
4724 | * intel_irq_uninstall - finilizes all irq handling | |
4725 | * @dev_priv: i915 device instance | |
4726 | * | |
4727 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4728 | * resources acquired in the init functions. | |
4729 | */ | |
2aeb7d3a DV |
4730 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4731 | { | |
4732 | drm_irq_uninstall(dev_priv->dev); | |
4733 | intel_hpd_cancel_work(dev_priv); | |
4734 | dev_priv->pm.irqs_enabled = false; | |
4735 | } | |
4736 | ||
fca52a55 DV |
4737 | /** |
4738 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4739 | * @dev_priv: i915 device instance | |
4740 | * | |
4741 | * This function is used to disable interrupts at runtime, both in the runtime | |
4742 | * pm and the system suspend/resume code. | |
4743 | */ | |
b963291c | 4744 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4745 | { |
b963291c | 4746 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4747 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4748 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4749 | } |
4750 | ||
fca52a55 DV |
4751 | /** |
4752 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4753 | * @dev_priv: i915 device instance | |
4754 | * | |
4755 | * This function is used to enable interrupts at runtime, both in the runtime | |
4756 | * pm and the system suspend/resume code. | |
4757 | */ | |
b963291c | 4758 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4759 | { |
2aeb7d3a | 4760 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4761 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4762 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4763 | } |