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drm/i915: Fix the confusing comment about the ioctl limits
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
fca52a55
DV		 40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
7c7e10db 48static const u32 hpd_ibx[HPD_NUM_PINS] = {
e5868a31
EE		 49 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
7c7e10db 56static const u32 hpd_cpt[HPD_NUM_PINS] = {
e5868a31 57 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 58 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 59 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
7c7e10db 64static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
e5868a31
EE		 65 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
7c7e10db 73static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
e5868a31
EE		 74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
4bca26d0 82static const u32 hpd_status_i915[HPD_NUM_PINS] = {
e5868a31
EE		 83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
e0a20ad7
SS		 91/* BXT hpd list */
92static const u32 hpd_bxt[HPD_NUM_PINS] = {
93 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
94 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
95};
96
5c502442 97/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 98#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 99 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
100 POSTING_READ(GEN8_##type##_IMR(which)); \
101 I915_WRITE(GEN8_##type##_IER(which), 0); \
102 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 POSTING_READ(GEN8_##type##_IIR(which)); \
104 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
105 POSTING_READ(GEN8_##type##_IIR(which)); \
106} while (0)
107
f86f3fb0 108#define GEN5_IRQ_RESET(type) do { \
a9d356a6 109 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 110 POSTING_READ(type##IMR); \
a9d356a6 111 I915_WRITE(type##IER, 0); \
5c502442
PZ		 112 I915_WRITE(type##IIR, 0xffffffff); \
113 POSTING_READ(type##IIR); \
114 I915_WRITE(type##IIR, 0xffffffff); \
115 POSTING_READ(type##IIR); \
a9d356a6
PZ		 116} while (0)
117
337ba017
PZ		 118/*
119 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
120 */
121#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
122 u32 val = I915_READ(reg); \
123 if (val) { \
124 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
125 (reg), val); \
126 I915_WRITE((reg), 0xffffffff); \
127 POSTING_READ(reg); \
128 I915_WRITE((reg), 0xffffffff); \
129 POSTING_READ(reg); \
130 } \
131} while (0)
132
35079899 133#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 134 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899 135 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
7d1bd539
VS		 136 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
137 POSTING_READ(GEN8_##type##_IMR(which)); \
35079899
PZ		 138} while (0)
139
140#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 141 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899 142 I915_WRITE(type##IER, (ier_val)); \
7d1bd539
VS		 143 I915_WRITE(type##IMR, (imr_val)); \
144 POSTING_READ(type##IMR); \
35079899
PZ		 145} while (0)
146
c9a9a268
ID		 147static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
148
036a4a7d 149/* For display hotplug interrupt */
47339cd9 150void
2d1013dd 151ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 152{
4bc9d430
DV		 153 assert_spin_locked(&dev_priv->irq_lock);
154
9df7575f 155 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 156 return;
c67a470b 157
1ec14ad3
CW		 158 if ((dev_priv->irq_mask & mask) != 0) {
159 dev_priv->irq_mask &= ~mask;
160 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 161 POSTING_READ(DEIMR);
036a4a7d
ZW		 162 }
163}
164
47339cd9 165void
2d1013dd 166ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 167{
4bc9d430
DV		 168 assert_spin_locked(&dev_priv->irq_lock);
169
06ffc778 170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 171 return;
c67a470b 172
1ec14ad3
CW		 173 if ((dev_priv->irq_mask & mask) != mask) {
174 dev_priv->irq_mask |= mask;
175 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 176 POSTING_READ(DEIMR);
036a4a7d
ZW		 177 }
178}
179
43eaea13
PZ		 180/**
181 * ilk_update_gt_irq - update GTIMR
182 * @dev_priv: driver private
183 * @interrupt_mask: mask of interrupt bits to update
184 * @enabled_irq_mask: mask of interrupt bits to enable
185 */
186static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
187 uint32_t interrupt_mask,
188 uint32_t enabled_irq_mask)
189{
190 assert_spin_locked(&dev_priv->irq_lock);
191
15a17aae
DV		 192 WARN_ON(enabled_irq_mask & ~interrupt_mask);
193
9df7575f 194 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 195 return;
c67a470b 196
43eaea13
PZ		 197 dev_priv->gt_irq_mask &= ~interrupt_mask;
198 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
199 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
200 POSTING_READ(GTIMR);
201}
202
480c8033 203void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 204{
205 ilk_update_gt_irq(dev_priv, mask, mask);
206}
207
480c8033 208void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 209{
210 ilk_update_gt_irq(dev_priv, mask, 0);
211}
212
b900b949
ID		 213static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
214{
215 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
216}
217
a72fbc3a
ID		 218static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
219{
220 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
221}
222
b900b949
ID		 223static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
224{
225 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
226}
227
edbfdb45
PZ		 228/**
229 * snb_update_pm_irq - update GEN6_PMIMR
230 * @dev_priv: driver private
231 * @interrupt_mask: mask of interrupt bits to update
232 * @enabled_irq_mask: mask of interrupt bits to enable
233 */
234static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
235 uint32_t interrupt_mask,
236 uint32_t enabled_irq_mask)
237{
605cd25b 238 uint32_t new_val;
edbfdb45 239
15a17aae
DV		 240 WARN_ON(enabled_irq_mask & ~interrupt_mask);
241
edbfdb45
PZ		 242 assert_spin_locked(&dev_priv->irq_lock);
243
605cd25b 244 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 245 new_val &= ~interrupt_mask;
246 new_val |= (~enabled_irq_mask & interrupt_mask);
247
605cd25b
PZ		 248 if (new_val != dev_priv->pm_irq_mask) {
249 dev_priv->pm_irq_mask = new_val;
a72fbc3a
ID		 250 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
251 POSTING_READ(gen6_pm_imr(dev_priv));
f52ecbcf 252 }
edbfdb45
PZ		 253}
254
480c8033 255void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45 256{
9939fba2
ID		 257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
edbfdb45
PZ		 260 snb_update_pm_irq(dev_priv, mask, mask);
261}
262
9939fba2
ID		 263static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
264 uint32_t mask)
edbfdb45
PZ		 265{
266 snb_update_pm_irq(dev_priv, mask, 0);
267}
268
9939fba2
ID		 269void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
270{
271 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
272 return;
273
274 __gen6_disable_pm_irq(dev_priv, mask);
275}
276
3cc134e3
ID		 277void gen6_reset_rps_interrupts(struct drm_device *dev)
278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 uint32_t reg = gen6_pm_iir(dev_priv);
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 I915_WRITE(reg, dev_priv->pm_rps_events);
284 I915_WRITE(reg, dev_priv->pm_rps_events);
285 POSTING_READ(reg);
096fad9e 286 dev_priv->rps.pm_iir = 0;
3cc134e3
ID		 287 spin_unlock_irq(&dev_priv->irq_lock);
288}
289
b900b949
ID		 290void gen6_enable_rps_interrupts(struct drm_device *dev)
291{
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 spin_lock_irq(&dev_priv->irq_lock);
78e68d36 295
b900b949 296 WARN_ON(dev_priv->rps.pm_iir);
3cc134e3 297 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
d4d70aa5 298 dev_priv->rps.interrupts_enabled = true;
78e68d36
ID		 299 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
300 dev_priv->pm_rps_events);
b900b949 301 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
78e68d36 302
b900b949
ID		 303 spin_unlock_irq(&dev_priv->irq_lock);
304}
305
59d02a1f
ID		 306u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
307{
308 /*
f24eeb19 309 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
59d02a1f 310 * if GEN6_PM_UP_EI_EXPIRED is masked.
f24eeb19
ID		 311 *
312 * TODO: verify if this can be reproduced on VLV,CHV.
59d02a1f
ID		 313 */
314 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
315 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
316
317 if (INTEL_INFO(dev_priv)->gen >= 8)
318 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
319
320 return mask;
321}
322
b900b949
ID		 323void gen6_disable_rps_interrupts(struct drm_device *dev)
324{
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
d4d70aa5
ID		 327 spin_lock_irq(&dev_priv->irq_lock);
328 dev_priv->rps.interrupts_enabled = false;
329 spin_unlock_irq(&dev_priv->irq_lock);
330
331 cancel_work_sync(&dev_priv->rps.work);
332
9939fba2
ID		 333 spin_lock_irq(&dev_priv->irq_lock);
334
59d02a1f 335 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
9939fba2
ID		 336
337 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
b900b949
ID		 338 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
339 ~dev_priv->pm_rps_events);
58072ccb
ID		 340
341 spin_unlock_irq(&dev_priv->irq_lock);
342
343 synchronize_irq(dev->irq);
b900b949
ID		 344}
345
fee884ed
DV		 346/**
347 * ibx_display_interrupt_update - update SDEIMR
348 * @dev_priv: driver private
349 * @interrupt_mask: mask of interrupt bits to update
350 * @enabled_irq_mask: mask of interrupt bits to enable
351 */
47339cd9
DV		 352void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
353 uint32_t interrupt_mask,
354 uint32_t enabled_irq_mask)
fee884ed
DV		 355{
356 uint32_t sdeimr = I915_READ(SDEIMR);
357 sdeimr &= ~interrupt_mask;
358 sdeimr |= (~enabled_irq_mask & interrupt_mask);
359
15a17aae
DV		 360 WARN_ON(enabled_irq_mask & ~interrupt_mask);
361
fee884ed
DV		 362 assert_spin_locked(&dev_priv->irq_lock);
363
9df7575f 364 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 365 return;
c67a470b 366
fee884ed
DV		 367 I915_WRITE(SDEIMR, sdeimr);
368 POSTING_READ(SDEIMR);
369}
8664281b 370
b5ea642a 371static void
755e9019
ID		 372__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
373 u32 enable_mask, u32 status_mask)
7c463586 374{
46c06a30 375 u32 reg = PIPESTAT(pipe);
755e9019 376 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 377
b79480ba 378 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 379 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 380
04feced9
VS		 381 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
382 status_mask & ~PIPESTAT_INT_STATUS_MASK,
383 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
384 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 385 return;
386
387 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 388 return;
389
91d181dd
ID		 390 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
391
46c06a30 392 /* Enable the interrupt, clear any pending status */
755e9019 393 pipestat |= enable_mask | status_mask;
46c06a30
VS		 394 I915_WRITE(reg, pipestat);
395 POSTING_READ(reg);
7c463586
KP		 396}
397
b5ea642a 398static void
755e9019
ID		 399__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
400 u32 enable_mask, u32 status_mask)
7c463586 401{
46c06a30 402 u32 reg = PIPESTAT(pipe);
755e9019 403 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 404
b79480ba 405 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 406 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 407
04feced9
VS		 408 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
409 status_mask & ~PIPESTAT_INT_STATUS_MASK,
410 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
411 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 412 return;
413
755e9019
ID		 414 if ((pipestat & enable_mask) == 0)
415 return;
416
91d181dd
ID		 417 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
418
755e9019 419 pipestat &= ~enable_mask;
46c06a30
VS		 420 I915_WRITE(reg, pipestat);
421 POSTING_READ(reg);
7c463586
KP		 422}
423
10c59c51
ID		 424static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
425{
426 u32 enable_mask = status_mask << 16;
427
428 /*
724a6905
VS		 429 * On pipe A we don't support the PSR interrupt yet,
430 * on pipe B and C the same bit MBZ.
10c59c51
ID		 431 */
432 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
433 return 0;
724a6905
VS		 434 /*
435 * On pipe B and C we don't support the PSR interrupt yet, on pipe
436 * A the same bit is for perf counters which we don't use either.
437 */
438 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
439 return 0;
10c59c51
ID		 440
441 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
442 SPRITE0_FLIP_DONE_INT_EN_VLV |
443 SPRITE1_FLIP_DONE_INT_EN_VLV);
444 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
445 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
446 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
447 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
448
449 return enable_mask;
450}
451
755e9019
ID		 452void
453i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
454 u32 status_mask)
455{
456 u32 enable_mask;
457
10c59c51
ID		 458 if (IS_VALLEYVIEW(dev_priv->dev))
459 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
460 status_mask);
461 else
462 enable_mask = status_mask << 16;
755e9019
ID		 463 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
464}
465
466void
467i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
468 u32 status_mask)
469{
470 u32 enable_mask;
471
10c59c51
ID		 472 if (IS_VALLEYVIEW(dev_priv->dev))
473 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
474 status_mask);
475 else
476 enable_mask = status_mask << 16;
755e9019
ID		 477 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
478}
479
01c66889 480/**
f49e38dd 481 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 482 */
f49e38dd 483static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 484{
2d1013dd 485 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3 486
f49e38dd
JN		 487 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
488 return;
489
13321786 490 spin_lock_irq(&dev_priv->irq_lock);
01c66889 491
755e9019 492 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 493 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 494 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 495 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3 496
13321786 497 spin_unlock_irq(&dev_priv->irq_lock);
01c66889
ZY		 498}
499
f75f3746
VS		 500/*
501 * This timing diagram depicts the video signal in and
502 * around the vertical blanking period.
503 *
504 * Assumptions about the fictitious mode used in this example:
505 * vblank_start >= 3
506 * vsync_start = vblank_start + 1
507 * vsync_end = vblank_start + 2
508 * vtotal = vblank_start + 3
509 *
510 * start of vblank:
511 * latch double buffered registers
512 * increment frame counter (ctg+)
513 * generate start of vblank interrupt (gen4+)
514 * |
515 * | frame start:
516 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
517 * | may be shifted forward 1-3 extra lines via PIPECONF
518 * | |
519 * | | start of vsync:
520 * | | generate vsync interrupt
521 * | | |
522 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
523 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
524 * ----va---> <-----------------vb--------------------> <--------va-------------
525 * | | <----vs-----> |
526 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
527 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
528 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
529 * | | |
530 * last visible pixel first visible pixel
531 * | increment frame counter (gen3/4)
532 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
533 *
534 * x = horizontal active
535 * _ = horizontal blanking
536 * hs = horizontal sync
537 * va = vertical active
538 * vb = vertical blanking
539 * vs = vertical sync
540 * vbs = vblank_start (number)
541 *
542 * Summary:
543 * - most events happen at the start of horizontal sync
544 * - frame start happens at the start of horizontal blank, 1-4 lines
545 * (depending on PIPECONF settings) after the start of vblank
546 * - gen3/4 pixel and frame counter are synchronized with the start
547 * of horizontal active on the first line of vertical active
548 */
549
4cdb83ec
VS		 550static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
551{
552 /* Gen2 doesn't have a hardware frame counter */
553 return 0;
554}
555
42f52ef8
KP		 556/* Called from drm generic code, passed a 'crtc', which
557 * we use as a pipe index
558 */
f71d4af4 559static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 560{
2d1013dd 561 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 562 unsigned long high_frame;
563 unsigned long low_frame;
0b2a8e09 564 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
f3a5c3f6
DV		 565 struct intel_crtc *intel_crtc =
566 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
567 const struct drm_display_mode *mode =
568 &intel_crtc->config->base.adjusted_mode;
0a3e67a4 569
f3a5c3f6
DV		 570 htotal = mode->crtc_htotal;
571 hsync_start = mode->crtc_hsync_start;
572 vbl_start = mode->crtc_vblank_start;
573 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
574 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 575
0b2a8e09
VS		 576 /* Convert to pixel count */
577 vbl_start *= htotal;
578
579 /* Start of vblank event occurs at start of hsync */
580 vbl_start -= htotal - hsync_start;
581
9db4a9c7
JB		 582 high_frame = PIPEFRAME(pipe);
583 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 584
0a3e67a4
JB		 585 /*
586 * High & low register fields aren't synchronized, so make sure
587 * we get a low value that's stable across two reads of the high
588 * register.
589 */
590 do {
5eddb70b 591 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 592 low = I915_READ(low_frame);
5eddb70b 593 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 594 } while (high1 != high2);
595
5eddb70b 596 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 597 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 598 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 599
600 /*
601 * The frame counter increments at beginning of active.
602 * Cook up a vblank counter by also checking the pixel
603 * counter against vblank start.
604 */
edc08d0a 605 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 606}
607
f71d4af4 608static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 609{
2d1013dd 610 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 611 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5 612
9880b7a5
JB		 613 return I915_READ(reg);
614}
615
ad3543ed
MK		 616/* raw reads, only for fast reads of display block, no need for forcewake etc. */
617#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 618
a225f079
VS		 619static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
620{
621 struct drm_device *dev = crtc->base.dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 623 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
a225f079 624 enum pipe pipe = crtc->pipe;
80715b2f 625 int position, vtotal;
a225f079 626
80715b2f 627 vtotal = mode->crtc_vtotal;
a225f079
VS		 628 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
629 vtotal /= 2;
630
631 if (IS_GEN2(dev))
632 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
633 else
634 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
635
636 /*
80715b2f
VS		 637 * See update_scanline_offset() for the details on the
638 * scanline_offset adjustment.
a225f079 639 */
80715b2f 640 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 641}
642
f71d4af4 643static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 644 unsigned int flags, int *vpos, int *hpos,
645 ktime_t *stime, ktime_t *etime)
0af7e4df 646{
c2baf4b7
VS		 647 struct drm_i915_private *dev_priv = dev->dev_private;
648 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 650 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
3aa18df8 651 int position;
78e8fc6b 652 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 653 bool in_vbl = true;
654 int ret = 0;
ad3543ed 655 unsigned long irqflags;
0af7e4df 656
c2baf4b7 657 if (!intel_crtc->active) {
0af7e4df 658 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 659 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 660 return 0;
661 }
662
c2baf4b7 663 htotal = mode->crtc_htotal;
78e8fc6b 664 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 665 vtotal = mode->crtc_vtotal;
666 vbl_start = mode->crtc_vblank_start;
667 vbl_end = mode->crtc_vblank_end;
0af7e4df 668
d31faf65
VS		 669 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
670 vbl_start = DIV_ROUND_UP(vbl_start, 2);
671 vbl_end /= 2;
672 vtotal /= 2;
673 }
674
c2baf4b7
VS		 675 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
676
ad3543ed
MK		 677 /*
678 * Lock uncore.lock, as we will do multiple timing critical raw
679 * register reads, potentially with preemption disabled, so the
680 * following code must not block on uncore.lock.
681 */
682 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 683
ad3543ed
MK		 684 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
685
686 /* Get optional system timestamp before query. */
687 if (stime)
688 *stime = ktime_get();
689
7c06b08a 690 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 691 /* No obvious pixelcount register. Only query vertical
692 * scanout position from Display scan line register.
693 */
a225f079 694 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 695 } else {
696 /* Have access to pixelcount since start of frame.
697 * We can split this into vertical and horizontal
698 * scanout position.
699 */
ad3543ed 700 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 701
3aa18df8
VS		 702 /* convert to pixel counts */
703 vbl_start *= htotal;
704 vbl_end *= htotal;
705 vtotal *= htotal;
78e8fc6b 706
7e78f1cb
VS		 707 /*
708 * In interlaced modes, the pixel counter counts all pixels,
709 * so one field will have htotal more pixels. In order to avoid
710 * the reported position from jumping backwards when the pixel
711 * counter is beyond the length of the shorter field, just
712 * clamp the position the length of the shorter field. This
713 * matches how the scanline counter based position works since
714 * the scanline counter doesn't count the two half lines.
715 */
716 if (position >= vtotal)
717 position = vtotal - 1;
718
78e8fc6b
VS		 719 /*
720 * Start of vblank interrupt is triggered at start of hsync,
721 * just prior to the first active line of vblank. However we
722 * consider lines to start at the leading edge of horizontal
723 * active. So, should we get here before we've crossed into
724 * the horizontal active of the first line in vblank, we would
725 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
726 * always add htotal-hsync_start to the current pixel position.
727 */
728 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 729 }
730
ad3543ed
MK		 731 /* Get optional system timestamp after query. */
732 if (etime)
733 *etime = ktime_get();
734
735 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
736
737 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
738
3aa18df8
VS		 739 in_vbl = position >= vbl_start && position < vbl_end;
740
741 /*
742 * While in vblank, position will be negative
743 * counting up towards 0 at vbl_end. And outside
744 * vblank, position will be positive counting
745 * up since vbl_end.
746 */
747 if (position >= vbl_start)
748 position -= vbl_end;
749 else
750 position += vtotal - vbl_end;
0af7e4df 751
7c06b08a 752 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 753 *vpos = position;
754 *hpos = 0;
755 } else {
756 *vpos = position / htotal;
757 *hpos = position - (*vpos * htotal);
758 }
0af7e4df 759
0af7e4df
MK		 760 /* In vblank? */
761 if (in_vbl)
3d3cbd84 762 ret |= DRM_SCANOUTPOS_IN_VBLANK;
0af7e4df
MK		 763
764 return ret;
765}
766
a225f079
VS		 767int intel_get_crtc_scanline(struct intel_crtc *crtc)
768{
769 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
770 unsigned long irqflags;
771 int position;
772
773 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
774 position = __intel_get_crtc_scanline(crtc);
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
777 return position;
778}
779
f71d4af4 780static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 781 int *max_error,
782 struct timeval *vblank_time,
783 unsigned flags)
784{
4041b853 785 struct drm_crtc *crtc;
0af7e4df 786
7eb552ae 787 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 788 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 789 return -EINVAL;
790 }
791
792 /* Get drm_crtc to timestamp: */
4041b853
CW		 793 crtc = intel_get_crtc_for_pipe(dev, pipe);
794 if (crtc == NULL) {
795 DRM_ERROR("Invalid crtc %d\n", pipe);
796 return -EINVAL;
797 }
798
83d65738 799 if (!crtc->state->enable) {
4041b853
CW		 800 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
801 return -EBUSY;
802 }
0af7e4df
MK		 803
804 /* Helper routine in DRM core does all the work: */
4041b853
CW		 805 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
806 vblank_time, flags,
7da903ef 807 crtc,
6e3c9717 808 &to_intel_crtc(crtc)->config->base.adjusted_mode);
0af7e4df
MK		 809}
810
67c347ff
JN		 811static bool intel_hpd_irq_event(struct drm_device *dev,
812 struct drm_connector *connector)
321a1b30
EE		 813{
814 enum drm_connector_status old_status;
815
816 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
817 old_status = connector->status;
818
819 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 820 if (old_status == connector->status)
821 return false;
822
823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30 824 connector->base.id,
c23cc417 825 connector->name,
67c347ff
JN		 826 drm_get_connector_status_name(old_status),
827 drm_get_connector_status_name(connector->status));
828
829 return true;
321a1b30
EE		 830}
831
13cf5504
DA		 832static void i915_digport_work_func(struct work_struct *work)
833{
834 struct drm_i915_private *dev_priv =
835 container_of(work, struct drm_i915_private, dig_port_work);
13cf5504
DA		 836 u32 long_port_mask, short_port_mask;
837 struct intel_digital_port *intel_dig_port;
b2c5c181 838 int i;
13cf5504
DA		 839 u32 old_bits = 0;
840
4cb21832 841 spin_lock_irq(&dev_priv->irq_lock);
13cf5504
DA		 842 long_port_mask = dev_priv->long_hpd_port_mask;
843 dev_priv->long_hpd_port_mask = 0;
844 short_port_mask = dev_priv->short_hpd_port_mask;
845 dev_priv->short_hpd_port_mask = 0;
4cb21832 846 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 847
848 for (i = 0; i < I915_MAX_PORTS; i++) {
849 bool valid = false;
850 bool long_hpd = false;
851 intel_dig_port = dev_priv->hpd_irq_port[i];
852 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
853 continue;
854
855 if (long_port_mask & (1 << i)) {
856 valid = true;
857 long_hpd = true;
858 } else if (short_port_mask & (1 << i))
859 valid = true;
860
861 if (valid) {
b2c5c181
DV		 862 enum irqreturn ret;
863
13cf5504 864 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
b2c5c181
DV		 865 if (ret == IRQ_NONE) {
866 /* fall back to old school hpd */
13cf5504
DA		 867 old_bits |= (1 << intel_dig_port->base.hpd_pin);
868 }
869 }
870 }
871
872 if (old_bits) {
4cb21832 873 spin_lock_irq(&dev_priv->irq_lock);
13cf5504 874 dev_priv->hpd_event_bits |= old_bits;
4cb21832 875 spin_unlock_irq(&dev_priv->irq_lock);
13cf5504
DA		 876 schedule_work(&dev_priv->hotplug_work);
877 }
878}
879
5ca58282
JB		 880/*
881 * Handle hotplug events outside the interrupt handler proper.
882 */
ac4c16c5
EE		 883#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
884
5ca58282
JB		 885static void i915_hotplug_work_func(struct work_struct *work)
886{
2d1013dd
JN		 887 struct drm_i915_private *dev_priv =
888 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 889 struct drm_device *dev = dev_priv->dev;
c31c4ba3 890 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 891 struct intel_connector *intel_connector;
892 struct intel_encoder *intel_encoder;
893 struct drm_connector *connector;
cd569aed 894 bool hpd_disabled = false;
321a1b30 895 bool changed = false;
142e2398 896 u32 hpd_event_bits;
4ef69c7a 897
a65e34c7 898 mutex_lock(&mode_config->mutex);
e67189ab
JB		 899 DRM_DEBUG_KMS("running encoder hotplug functions\n");
900
4cb21832 901 spin_lock_irq(&dev_priv->irq_lock);
142e2398
EE		 902
903 hpd_event_bits = dev_priv->hpd_event_bits;
904 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 905 list_for_each_entry(connector, &mode_config->connector_list, head) {
906 intel_connector = to_intel_connector(connector);
36cd7444
DA		 907 if (!intel_connector->encoder)
908 continue;
cd569aed
EE		 909 intel_encoder = intel_connector->encoder;
910 if (intel_encoder->hpd_pin > HPD_NONE &&
911 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
912 connector->polled == DRM_CONNECTOR_POLL_HPD) {
913 DRM_INFO("HPD interrupt storm detected on connector %s: "
914 "switching from hotplug detection to polling\n",
c23cc417 915 connector->name);
cd569aed
EE		 916 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
917 connector->polled = DRM_CONNECTOR_POLL_CONNECT
918 | DRM_CONNECTOR_POLL_DISCONNECT;
919 hpd_disabled = true;
920 }
142e2398
EE		 921 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
922 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
c23cc417 923 connector->name, intel_encoder->hpd_pin);
142e2398 924 }
cd569aed
EE		 925 }
926 /* if there were no outputs to poll, poll was disabled,
927 * therefore make sure it's enabled when disabling HPD on
928 * some connectors */
ac4c16c5 929 if (hpd_disabled) {
cd569aed 930 drm_kms_helper_poll_enable(dev);
6323751d
ID		 931 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
932 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
ac4c16c5 933 }
cd569aed 934
4cb21832 935 spin_unlock_irq(&dev_priv->irq_lock);
cd569aed 936
321a1b30
EE		 937 list_for_each_entry(connector, &mode_config->connector_list, head) {
938 intel_connector = to_intel_connector(connector);
36cd7444
DA		 939 if (!intel_connector->encoder)
940 continue;
321a1b30
EE		 941 intel_encoder = intel_connector->encoder;
942 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
943 if (intel_encoder->hot_plug)
944 intel_encoder->hot_plug(intel_encoder);
945 if (intel_hpd_irq_event(dev, connector))
946 changed = true;
947 }
948 }
40ee3381
KP		 949 mutex_unlock(&mode_config->mutex);
950
321a1b30
EE		 951 if (changed)
952 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 953}
954
d0ecd7e2 955static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 956{
2d1013dd 957 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 958 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 959 u8 new_delay;
9270388e 960
d0ecd7e2 961 spin_lock(&mchdev_lock);
f97108d1 962
73edd18f
DV		 963 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
964
20e4d407 965 new_delay = dev_priv->ips.cur_delay;
9270388e 966
7648fa99 967 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 968 busy_up = I915_READ(RCPREVBSYTUPAVG);
969 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 970 max_avg = I915_READ(RCBMAXAVG);
971 min_avg = I915_READ(RCBMINAVG);
972
973 /* Handle RCS change request from hw */
b5b72e89 974 if (busy_up > max_avg) {
20e4d407
DV		 975 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
976 new_delay = dev_priv->ips.cur_delay - 1;
977 if (new_delay < dev_priv->ips.max_delay)
978 new_delay = dev_priv->ips.max_delay;
b5b72e89 979 } else if (busy_down < min_avg) {
20e4d407
DV		 980 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
981 new_delay = dev_priv->ips.cur_delay + 1;
982 if (new_delay > dev_priv->ips.min_delay)
983 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 984 }
985
7648fa99 986 if (ironlake_set_drps(dev, new_delay))
20e4d407 987 dev_priv->ips.cur_delay = new_delay;
f97108d1 988
d0ecd7e2 989 spin_unlock(&mchdev_lock);
9270388e 990
f97108d1
JB		 991 return;
992}
993
74cdb337 994static void notify_ring(struct intel_engine_cs *ring)
549f7365 995{
93b0a4e0 996 if (!intel_ring_initialized(ring))
475553de
CW		 997 return;
998
bcfcc8ba 999 trace_i915_gem_request_notify(ring);
9862e600 1000
549f7365 1001 wake_up_all(&ring->irq_queue);
549f7365
CW		 1002}
1003
43cf3bf0
CW		 1004static void vlv_c0_read(struct drm_i915_private *dev_priv,
1005 struct intel_rps_ei *ei)
31685c25 1006{
43cf3bf0
CW		 1007 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1008 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1009 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1010}
31685c25 1011
43cf3bf0
CW		 1012static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1013 const struct intel_rps_ei *old,
1014 const struct intel_rps_ei *now,
1015 int threshold)
1016{
1017 u64 time, c0;
31685c25 1018
43cf3bf0
CW		 1019 if (old->cz_clock == 0)
1020 return false;
31685c25 1021
43cf3bf0
CW		 1022 time = now->cz_clock - old->cz_clock;
1023 time *= threshold * dev_priv->mem_freq;
31685c25 1024
43cf3bf0
CW		 1025 /* Workload can be split between render + media, e.g. SwapBuffers
1026 * being blitted in X after being rendered in mesa. To account for
1027 * this we need to combine both engines into our activity counter.
31685c25 1028 */
43cf3bf0
CW		 1029 c0 = now->render_c0 - old->render_c0;
1030 c0 += now->media_c0 - old->media_c0;
1031 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
31685c25 1032
43cf3bf0 1033 return c0 >= time;
31685c25
D		 1034}
1035
43cf3bf0 1036void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
31685c25 1037{
43cf3bf0
CW		 1038 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1039 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
43cf3bf0 1040}
31685c25 1041
43cf3bf0
CW		 1042static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1043{
1044 struct intel_rps_ei now;
1045 u32 events = 0;
31685c25 1046
6f4b12f8 1047 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
43cf3bf0 1048 return 0;
31685c25 1049
43cf3bf0
CW		 1050 vlv_c0_read(dev_priv, &now);
1051 if (now.cz_clock == 0)
1052 return 0;
31685c25 1053
43cf3bf0
CW		 1054 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1055 if (!vlv_c0_above(dev_priv,
1056 &dev_priv->rps.down_ei, &now,
8fb55197 1057 dev_priv->rps.down_threshold))
43cf3bf0
CW		 1058 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1059 dev_priv->rps.down_ei = now;
1060 }
31685c25 1061
43cf3bf0
CW		 1062 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1063 if (vlv_c0_above(dev_priv,
1064 &dev_priv->rps.up_ei, &now,
8fb55197 1065 dev_priv->rps.up_threshold))
43cf3bf0
CW		 1066 events |= GEN6_PM_RP_UP_THRESHOLD;
1067 dev_priv->rps.up_ei = now;
31685c25
D		 1068 }
1069
43cf3bf0 1070 return events;
31685c25
D		 1071}
1072
f5a4c67d
CW		 1073static bool any_waiters(struct drm_i915_private *dev_priv)
1074{
1075 struct intel_engine_cs *ring;
1076 int i;
1077
1078 for_each_ring(ring, dev_priv, i)
1079 if (ring->irq_refcount)
1080 return true;
1081
1082 return false;
1083}
1084
4912d041 1085static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1086{
2d1013dd
JN		 1087 struct drm_i915_private *dev_priv =
1088 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1089 u32 pm_iir;
dd75fdc8 1090 int new_delay, adj;
4912d041 1091
59cdb63d 1092 spin_lock_irq(&dev_priv->irq_lock);
d4d70aa5
ID		 1093 /* Speed up work cancelation during disabling rps interrupts. */
1094 if (!dev_priv->rps.interrupts_enabled) {
1095 spin_unlock_irq(&dev_priv->irq_lock);
1096 return;
1097 }
c6a828d3
DV		 1098 pm_iir = dev_priv->rps.pm_iir;
1099 dev_priv->rps.pm_iir = 0;
a72fbc3a
ID		 1100 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1101 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
59cdb63d 1102 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1103
60611c13 1104 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1105 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1106
a6706b45 1107 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1108 return;
1109
4fc688ce 1110 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1111
43cf3bf0
CW		 1112 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1113
dd75fdc8 1114 adj = dev_priv->rps.last_adj;
edcf284b 1115 new_delay = dev_priv->rps.cur_freq;
7425034a 1116 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1117 if (adj > 0)
1118 adj *= 2;
edcf284b
CW		 1119 else /* CHV needs even encode values */
1120 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
7425034a
VS		 1121 /*
1122 * For better performance, jump directly
1123 * to RPe if we're below it.
1124 */
edcf284b 1125 if (new_delay < dev_priv->rps.efficient_freq - adj) {
b39fb297 1126 new_delay = dev_priv->rps.efficient_freq;
edcf284b
CW		 1127 adj = 0;
1128 }
f5a4c67d
CW		 1129 } else if (any_waiters(dev_priv)) {
1130 adj = 0;
dd75fdc8 1131 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1132 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1133 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1134 else
b39fb297 1135 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8
CW		 1136 adj = 0;
1137 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1138 if (adj < 0)
1139 adj *= 2;
edcf284b
CW		 1140 else /* CHV needs even encode values */
1141 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
dd75fdc8 1142 } else { /* unknown event */
edcf284b 1143 adj = 0;
dd75fdc8 1144 }
3b8d8d91 1145
edcf284b
CW		 1146 dev_priv->rps.last_adj = adj;
1147
79249636
BW		 1148 /* sysfs frequency interfaces may have snuck in while servicing the
1149 * interrupt
1150 */
edcf284b 1151 new_delay += adj;
1272e7b8 1152 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1153 dev_priv->rps.min_freq_softlimit,
1154 dev_priv->rps.max_freq_softlimit);
27544369 1155
ffe02b40 1156 intel_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1157
4fc688ce 1158 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1159}
1160
e3689190
BW		 1161
1162/**
1163 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1164 * occurred.
1165 * @work: workqueue struct
1166 *
1167 * Doesn't actually do anything except notify userspace. As a consequence of
1168 * this event, userspace should try to remap the bad rows since statistically
1169 * it is likely the same row is more likely to go bad again.
1170 */
1171static void ivybridge_parity_work(struct work_struct *work)
1172{
2d1013dd
JN		 1173 struct drm_i915_private *dev_priv =
1174 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1175 u32 error_status, row, bank, subbank;
35a85ac6 1176 char *parity_event[6];
e3689190 1177 uint32_t misccpctl;
35a85ac6 1178 uint8_t slice = 0;
e3689190
BW		 1179
1180 /* We must turn off DOP level clock gating to access the L3 registers.
1181 * In order to prevent a get/put style interface, acquire struct mutex
1182 * any time we access those registers.
1183 */
1184 mutex_lock(&dev_priv->dev->struct_mutex);
1185
35a85ac6
BW		 1186 /* If we've screwed up tracking, just let the interrupt fire again */
1187 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1188 goto out;
1189
e3689190
BW		 1190 misccpctl = I915_READ(GEN7_MISCCPCTL);
1191 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1192 POSTING_READ(GEN7_MISCCPCTL);
1193
35a85ac6
BW		 1194 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1195 u32 reg;
e3689190 1196
35a85ac6
BW		 1197 slice--;
1198 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1199 break;
e3689190 1200
35a85ac6 1201 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1202
35a85ac6 1203 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1204
35a85ac6
BW		 1205 error_status = I915_READ(reg);
1206 row = GEN7_PARITY_ERROR_ROW(error_status);
1207 bank = GEN7_PARITY_ERROR_BANK(error_status);
1208 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1209
1210 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1211 POSTING_READ(reg);
1212
1213 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1214 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1215 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1216 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1217 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1218 parity_event[5] = NULL;
1219
5bdebb18 1220 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1221 KOBJ_CHANGE, parity_event);
e3689190 1222
35a85ac6
BW		 1223 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1224 slice, row, bank, subbank);
e3689190 1225
35a85ac6
BW		 1226 kfree(parity_event[4]);
1227 kfree(parity_event[3]);
1228 kfree(parity_event[2]);
1229 kfree(parity_event[1]);
1230 }
e3689190 1231
35a85ac6 1232 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1233
35a85ac6
BW		 1234out:
1235 WARN_ON(dev_priv->l3_parity.which_slice);
4cb21832 1236 spin_lock_irq(&dev_priv->irq_lock);
480c8033 1237 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
4cb21832 1238 spin_unlock_irq(&dev_priv->irq_lock);
35a85ac6
BW		 1239
1240 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1241}
1242
35a85ac6 1243static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1244{
2d1013dd 1245 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1246
040d2baa 1247 if (!HAS_L3_DPF(dev))
e3689190
BW		 1248 return;
1249
d0ecd7e2 1250 spin_lock(&dev_priv->irq_lock);
480c8033 1251 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1252 spin_unlock(&dev_priv->irq_lock);
e3689190 1253
35a85ac6
BW		 1254 iir &= GT_PARITY_ERROR(dev);
1255 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1256 dev_priv->l3_parity.which_slice |= 1 << 1;
1257
1258 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1259 dev_priv->l3_parity.which_slice |= 1 << 0;
1260
a4da4fa4 1261 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1262}
1263
f1af8fc1
PZ		 1264static void ilk_gt_irq_handler(struct drm_device *dev,
1265 struct drm_i915_private *dev_priv,
1266 u32 gt_iir)
1267{
1268 if (gt_iir &
1269 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
74cdb337 1270 notify_ring(&dev_priv->ring[RCS]);
f1af8fc1 1271 if (gt_iir & ILK_BSD_USER_INTERRUPT)
74cdb337 1272 notify_ring(&dev_priv->ring[VCS]);
f1af8fc1
PZ		 1273}
1274
e7b4c6b1
DV		 1275static void snb_gt_irq_handler(struct drm_device *dev,
1276 struct drm_i915_private *dev_priv,
1277 u32 gt_iir)
1278{
1279
cc609d5d
BW		 1280 if (gt_iir &
1281 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
74cdb337 1282 notify_ring(&dev_priv->ring[RCS]);
cc609d5d 1283 if (gt_iir & GT_BSD_USER_INTERRUPT)
74cdb337 1284 notify_ring(&dev_priv->ring[VCS]);
cc609d5d 1285 if (gt_iir & GT_BLT_USER_INTERRUPT)
74cdb337 1286 notify_ring(&dev_priv->ring[BCS]);
e7b4c6b1 1287
cc609d5d
BW		 1288 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1289 GT_BSD_CS_ERROR_INTERRUPT |
aaecdf61
DV		 1290 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1291 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
e3689190 1292
35a85ac6
BW		 1293 if (gt_iir & GT_PARITY_ERROR(dev))
1294 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1295}
1296
74cdb337 1297static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
abd58f01
BW		 1298 u32 master_ctl)
1299{
abd58f01
BW		 1300 irqreturn_t ret = IRQ_NONE;
1301
1302 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
74cdb337 1303 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
abd58f01 1304 if (tmp) {
cb0d205e 1305 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
abd58f01 1306 ret = IRQ_HANDLED;
e981e7b1 1307
74cdb337
CW		 1308 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1309 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1310 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1311 notify_ring(&dev_priv->ring[RCS]);
1312
1313 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1314 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1315 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1316 notify_ring(&dev_priv->ring[BCS]);
abd58f01
BW		 1317 } else
1318 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1319 }
1320
85f9b5f9 1321 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
74cdb337 1322 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
abd58f01 1323 if (tmp) {
cb0d205e 1324 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
abd58f01 1325 ret = IRQ_HANDLED;
e981e7b1 1326
74cdb337
CW		 1327 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1328 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1329 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1330 notify_ring(&dev_priv->ring[VCS]);
abd58f01 1331
74cdb337
CW		 1332 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1333 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1334 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1335 notify_ring(&dev_priv->ring[VCS2]);
0961021a 1336 } else
abd58f01 1337 DRM_ERROR("The master control interrupt lied (GT1)!\n");
0961021a
BW		 1338 }
1339
abd58f01 1340 if (master_ctl & GEN8_GT_VECS_IRQ) {
74cdb337 1341 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
abd58f01 1342 if (tmp) {
74cdb337 1343 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
abd58f01 1344 ret = IRQ_HANDLED;
e981e7b1 1345
74cdb337
CW		 1346 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1347 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1348 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1349 notify_ring(&dev_priv->ring[VECS]);
abd58f01
BW		 1350 } else
1351 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1352 }
1353
0961021a 1354 if (master_ctl & GEN8_GT_PM_IRQ) {
74cdb337 1355 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
0961021a 1356 if (tmp & dev_priv->pm_rps_events) {
cb0d205e
CW		 1357 I915_WRITE_FW(GEN8_GT_IIR(2),
1358 tmp & dev_priv->pm_rps_events);
38cc46d7 1359 ret = IRQ_HANDLED;
c9a9a268 1360 gen6_rps_irq_handler(dev_priv, tmp);
0961021a
BW		 1361 } else
1362 DRM_ERROR("The master control interrupt lied (PM)!\n");
1363 }
1364
abd58f01
BW		 1365 return ret;
1366}
1367
b543fb04
EE		 1368#define HPD_STORM_DETECT_PERIOD 1000
1369#define HPD_STORM_THRESHOLD 5
1370
07c338ce 1371static int pch_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1372{
1373 switch (port) {
1374 case PORT_A:
1375 case PORT_E:
1376 default:
1377 return -1;
1378 case PORT_B:
1379 return 0;
1380 case PORT_C:
1381 return 8;
1382 case PORT_D:
1383 return 16;
1384 }
1385}
1386
07c338ce 1387static int i915_port_to_hotplug_shift(enum port port)
13cf5504
DA		 1388{
1389 switch (port) {
1390 case PORT_A:
1391 case PORT_E:
1392 default:
1393 return -1;
1394 case PORT_B:
1395 return 17;
1396 case PORT_C:
1397 return 19;
1398 case PORT_D:
1399 return 21;
1400 }
1401}
1402
8fc3b42e 1403static enum port get_port_from_pin(enum hpd_pin pin)
13cf5504
DA		 1404{
1405 switch (pin) {
1406 case HPD_PORT_B:
1407 return PORT_B;
1408 case HPD_PORT_C:
1409 return PORT_C;
1410 case HPD_PORT_D:
1411 return PORT_D;
1412 default:
1413 return PORT_A; /* no hpd */
1414 }
1415}
1416
8fc3b42e
VS		 1417static void intel_hpd_irq_handler(struct drm_device *dev,
1418 u32 hotplug_trigger,
1419 u32 dig_hotplug_reg,
1420 const u32 hpd[HPD_NUM_PINS])
b543fb04 1421{
2d1013dd 1422 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1423 int i;
13cf5504 1424 enum port port;
10a504de 1425 bool storm_detected = false;
13cf5504
DA		 1426 bool queue_dig = false, queue_hp = false;
1427 u32 dig_shift;
1428 u32 dig_port_mask = 0;
b543fb04 1429
91d131d2
DV		 1430 if (!hotplug_trigger)
1431 return;
1432
13cf5504
DA		 1433 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1434 hotplug_trigger, dig_hotplug_reg);
cc9bd499 1435
b5ea2d56 1436 spin_lock(&dev_priv->irq_lock);
b543fb04 1437 for (i = 1; i < HPD_NUM_PINS; i++) {
13cf5504
DA		 1438 if (!(hpd[i] & hotplug_trigger))
1439 continue;
1440
1441 port = get_port_from_pin(i);
1442 if (port && dev_priv->hpd_irq_port[port]) {
1443 bool long_hpd;
1444
6b5ad42f 1445 if (!HAS_GMCH_DISPLAY(dev_priv)) {
07c338ce 1446 dig_shift = pch_port_to_hotplug_shift(port);
13cf5504 1447 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
07c338ce
JN		 1448 } else {
1449 dig_shift = i915_port_to_hotplug_shift(port);
1450 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
13cf5504
DA		 1451 }
1452
26fbb774
VS		 1453 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1454 port_name(port),
1455 long_hpd ? "long" : "short");
13cf5504
DA		 1456 /* for long HPD pulses we want to have the digital queue happen,
1457 but we still want HPD storm detection to function. */
1458 if (long_hpd) {
1459 dev_priv->long_hpd_port_mask |= (1 << port);
1460 dig_port_mask |= hpd[i];
1461 } else {
1462 /* for short HPD just trigger the digital queue */
1463 dev_priv->short_hpd_port_mask |= (1 << port);
1464 hotplug_trigger &= ~hpd[i];
1465 }
1466 queue_dig = true;
1467 }
1468 }
821450c6 1469
13cf5504 1470 for (i = 1; i < HPD_NUM_PINS; i++) {
3ff04a16
DV		 1471 if (hpd[i] & hotplug_trigger &&
1472 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1473 /*
1474 * On GMCH platforms the interrupt mask bits only
1475 * prevent irq generation, not the setting of the
1476 * hotplug bits itself. So only WARN about unexpected
1477 * interrupts on saner platforms.
1478 */
1479 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1480 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1481 hotplug_trigger, i, hpd[i]);
1482
1483 continue;
1484 }
b8f102e8 1485
b543fb04
EE		 1486 if (!(hpd[i] & hotplug_trigger) ||
1487 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1488 continue;
1489
13cf5504
DA		 1490 if (!(dig_port_mask & hpd[i])) {
1491 dev_priv->hpd_event_bits |= (1 << i);
1492 queue_hp = true;
1493 }
1494
b543fb04
EE		 1495 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1496 dev_priv->hpd_stats[i].hpd_last_jiffies
1497 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1498 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1499 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1500 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1501 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1502 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1503 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1504 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1505 storm_detected = true;
b543fb04
EE		 1506 } else {
1507 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1508 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1509 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1510 }
1511 }
1512
10a504de
DV		 1513 if (storm_detected)
1514 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1515 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1516
645416f5
DV		 1517 /*
1518 * Our hotplug handler can grab modeset locks (by calling down into the
1519 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1520 * queue for otherwise the flush_work in the pageflip code will
1521 * deadlock.
1522 */
13cf5504 1523 if (queue_dig)
0e32b39c 1524 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
13cf5504
DA		 1525 if (queue_hp)
1526 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1527}
1528
515ac2bb
DV		 1529static void gmbus_irq_handler(struct drm_device *dev)
1530{
2d1013dd 1531 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1532
28c70f16 1533 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1534}
1535
ce99c256
DV		 1536static void dp_aux_irq_handler(struct drm_device *dev)
1537{
2d1013dd 1538 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1539
9ee32fea 1540 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1541}
1542
8bf1e9f1 1543#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1544static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1545 uint32_t crc0, uint32_t crc1,
1546 uint32_t crc2, uint32_t crc3,
1547 uint32_t crc4)
8bf1e9f1
SH		 1548{
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1551 struct intel_pipe_crc_entry *entry;
ac2300d4 1552 int head, tail;
b2c88f5b 1553
d538bbdf
DL		 1554 spin_lock(&pipe_crc->lock);
1555
0c912c79 1556 if (!pipe_crc->entries) {
d538bbdf 1557 spin_unlock(&pipe_crc->lock);
34273620 1558 DRM_DEBUG_KMS("spurious interrupt\n");
0c912c79
DL		 1559 return;
1560 }
1561
d538bbdf
DL		 1562 head = pipe_crc->head;
1563 tail = pipe_crc->tail;
b2c88f5b
DL		 1564
1565 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1566 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1567 DRM_ERROR("CRC buffer overflowing\n");
1568 return;
1569 }
1570
1571 entry = &pipe_crc->entries[head];
8bf1e9f1 1572
8bc5e955 1573 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1574 entry->crc[0] = crc0;
1575 entry->crc[1] = crc1;
1576 entry->crc[2] = crc2;
1577 entry->crc[3] = crc3;
1578 entry->crc[4] = crc4;
b2c88f5b
DL		 1579
1580 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1581 pipe_crc->head = head;
1582
1583 spin_unlock(&pipe_crc->lock);
07144428
DL		 1584
1585 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1586}
277de95e
DV		 1587#else
1588static inline void
1589display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1590 uint32_t crc0, uint32_t crc1,
1591 uint32_t crc2, uint32_t crc3,
1592 uint32_t crc4) {}
1593#endif
1594
eba94eb9 1595
277de95e 1596static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1597{
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599
277de95e
DV		 1600 display_pipe_crc_irq_handler(dev, pipe,
1601 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1602 0, 0, 0, 0);
5a69b89f
DV		 1603}
1604
277de95e 1605static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1606{
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608
277de95e
DV		 1609 display_pipe_crc_irq_handler(dev, pipe,
1610 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1611 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1612 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1613 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1614 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1615}
5b3a856b 1616
277de95e 1617static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1618{
1619 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1620 uint32_t res1, res2;
1621
1622 if (INTEL_INFO(dev)->gen >= 3)
1623 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1624 else
1625 res1 = 0;
1626
1627 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1628 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1629 else
1630 res2 = 0;
5b3a856b 1631
277de95e
DV		 1632 display_pipe_crc_irq_handler(dev, pipe,
1633 I915_READ(PIPE_CRC_RES_RED(pipe)),
1634 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1635 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1636 res1, res2);
5b3a856b 1637}
8bf1e9f1 1638
1403c0d4
PZ		 1639/* The RPS events need forcewake, so we add them to a work queue and mask their
1640 * IMR bits until the work is done. Other interrupts can be processed without
1641 * the work queue. */
1642static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1643{
a6706b45 1644 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1645 spin_lock(&dev_priv->irq_lock);
480c8033 1646 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
d4d70aa5
ID		 1647 if (dev_priv->rps.interrupts_enabled) {
1648 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1649 queue_work(dev_priv->wq, &dev_priv->rps.work);
1650 }
59cdb63d 1651 spin_unlock(&dev_priv->irq_lock);
baf02a1f 1652 }
baf02a1f 1653
c9a9a268
ID		 1654 if (INTEL_INFO(dev_priv)->gen >= 8)
1655 return;
1656
1403c0d4
PZ		 1657 if (HAS_VEBOX(dev_priv->dev)) {
1658 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
74cdb337 1659 notify_ring(&dev_priv->ring[VECS]);
12638c57 1660
aaecdf61
DV		 1661 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1662 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
12638c57 1663 }
baf02a1f
BW		 1664}
1665
8d7849db
VS		 1666static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1667{
8d7849db
VS		 1668 if (!drm_handle_vblank(dev, pipe))
1669 return false;
1670
8d7849db
VS		 1671 return true;
1672}
1673
c1874ed7
ID		 1674static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1675{
1676 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1677 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1678 int pipe;
1679
58ead0d7 1680 spin_lock(&dev_priv->irq_lock);
055e393f 1681 for_each_pipe(dev_priv, pipe) {
91d181dd 1682 int reg;
bbb5eebf 1683 u32 mask, iir_bit = 0;
91d181dd 1684
bbb5eebf
DV		 1685 /*
1686 * PIPESTAT bits get signalled even when the interrupt is
1687 * disabled with the mask bits, and some of the status bits do
1688 * not generate interrupts at all (like the underrun bit). Hence
1689 * we need to be careful that we only handle what we want to
1690 * handle.
1691 */
0f239f4c
DV		 1692
1693 /* fifo underruns are filterered in the underrun handler. */
1694 mask = PIPE_FIFO_UNDERRUN_STATUS;
bbb5eebf
DV		 1695
1696 switch (pipe) {
1697 case PIPE_A:
1698 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1699 break;
1700 case PIPE_B:
1701 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1702 break;
3278f67f
VS		 1703 case PIPE_C:
1704 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1705 break;
bbb5eebf
DV		 1706 }
1707 if (iir & iir_bit)
1708 mask |= dev_priv->pipestat_irq_mask[pipe];
1709
1710 if (!mask)
91d181dd
ID		 1711 continue;
1712
1713 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1714 mask |= PIPESTAT_INT_ENABLE_MASK;
1715 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1716
1717 /*
1718 * Clear the PIPE*STAT regs before the IIR
1719 */
91d181dd
ID		 1720 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1721 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1722 I915_WRITE(reg, pipe_stats[pipe]);
1723 }
58ead0d7 1724 spin_unlock(&dev_priv->irq_lock);
c1874ed7 1725
055e393f 1726 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1727 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1728 intel_pipe_handle_vblank(dev, pipe))
1729 intel_check_page_flip(dev, pipe);
c1874ed7 1730
579a9b0e 1731 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1732 intel_prepare_page_flip(dev, pipe);
1733 intel_finish_page_flip(dev, pipe);
1734 }
1735
1736 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1737 i9xx_pipe_crc_irq_handler(dev, pipe);
1738
1f7247c0
DV		 1739 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1740 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
c1874ed7
ID		 1741 }
1742
1743 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1744 gmbus_irq_handler(dev);
1745}
1746
16c6c56b
VS		 1747static void i9xx_hpd_irq_handler(struct drm_device *dev)
1748{
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1751
3ff60f89
OM		 1752 if (hotplug_status) {
1753 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1754 /*
1755 * Make sure hotplug status is cleared before we clear IIR, or else we
1756 * may miss hotplug events.
1757 */
1758 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 1759
4bca26d0 1760 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
3ff60f89 1761 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 1762
13cf5504 1763 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
3ff60f89
OM		 1764 } else {
1765 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 1766
13cf5504 1767 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
3ff60f89 1768 }
16c6c56b 1769
3ff60f89
OM		 1770 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1771 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1772 dp_aux_irq_handler(dev);
1773 }
16c6c56b
VS		 1774}
1775
ff1f525e 1776static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 1777{
45a83f84 1778 struct drm_device *dev = arg;
2d1013dd 1779 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1780 u32 iir, gt_iir, pm_iir;
1781 irqreturn_t ret = IRQ_NONE;
7e231dbe 1782
2dd2a883
ID		 1783 if (!intel_irqs_enabled(dev_priv))
1784 return IRQ_NONE;
1785
7e231dbe 1786 while (true) {
3ff60f89
OM		 1787 /* Find, clear, then process each source of interrupt */
1788
7e231dbe 1789 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 1790 if (gt_iir)
1791 I915_WRITE(GTIIR, gt_iir);
1792
7e231dbe 1793 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 1794 if (pm_iir)
1795 I915_WRITE(GEN6_PMIIR, pm_iir);
1796
1797 iir = I915_READ(VLV_IIR);
1798 if (iir) {
1799 /* Consume port before clearing IIR or we'll miss events */
1800 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1801 i9xx_hpd_irq_handler(dev);
1802 I915_WRITE(VLV_IIR, iir);
1803 }
7e231dbe
JB		 1804
1805 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1806 goto out;
1807
1808 ret = IRQ_HANDLED;
1809
3ff60f89
OM		 1810 if (gt_iir)
1811 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 1812 if (pm_iir)
d0ecd7e2 1813 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 1814 /* Call regardless, as some status bits might not be
1815 * signalled in iir */
1816 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 1817 }
1818
1819out:
1820 return ret;
1821}
1822
43f328d7
VS		 1823static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1824{
45a83f84 1825 struct drm_device *dev = arg;
43f328d7
VS		 1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 u32 master_ctl, iir;
1828 irqreturn_t ret = IRQ_NONE;
43f328d7 1829
2dd2a883
ID		 1830 if (!intel_irqs_enabled(dev_priv))
1831 return IRQ_NONE;
1832
8e5fd599
VS		 1833 for (;;) {
1834 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1835 iir = I915_READ(VLV_IIR);
43f328d7 1836
8e5fd599
VS		 1837 if (master_ctl == 0 && iir == 0)
1838 break;
43f328d7 1839
27b6c122
OM		 1840 ret = IRQ_HANDLED;
1841
8e5fd599 1842 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 1843
27b6c122 1844 /* Find, clear, then process each source of interrupt */
43f328d7 1845
27b6c122
OM		 1846 if (iir) {
1847 /* Consume port before clearing IIR or we'll miss events */
1848 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1849 i9xx_hpd_irq_handler(dev);
1850 I915_WRITE(VLV_IIR, iir);
1851 }
43f328d7 1852
74cdb337 1853 gen8_gt_irq_handler(dev_priv, master_ctl);
43f328d7 1854
27b6c122
OM		 1855 /* Call regardless, as some status bits might not be
1856 * signalled in iir */
1857 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 1858
8e5fd599
VS		 1859 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1860 POSTING_READ(GEN8_MASTER_IRQ);
8e5fd599 1861 }
3278f67f 1862
43f328d7
VS		 1863 return ret;
1864}
1865
23e81d69 1866static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1867{
2d1013dd 1868 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1869 int pipe;
b543fb04 1870 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504
DA		 1871 u32 dig_hotplug_reg;
1872
1873 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1874 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
776ad806 1875
13cf5504 1876 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
91d131d2 1877
cfc33bf7
VS		 1878 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1879 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1880 SDE_AUDIO_POWER_SHIFT);
776ad806 1881 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1882 port_name(port));
1883 }
776ad806 1884
ce99c256
DV		 1885 if (pch_iir & SDE_AUX_MASK)
1886 dp_aux_irq_handler(dev);
1887
776ad806 1888 if (pch_iir & SDE_GMBUS)
515ac2bb 1889 gmbus_irq_handler(dev);
776ad806
JB		 1890
1891 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1892 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1893
1894 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1895 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1896
1897 if (pch_iir & SDE_POISON)
1898 DRM_ERROR("PCH poison interrupt\n");
1899
9db4a9c7 1900 if (pch_iir & SDE_FDI_MASK)
055e393f 1901 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 1902 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1903 pipe_name(pipe),
1904 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1905
1906 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1907 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1908
1909 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1910 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1911
776ad806 1912 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1f7247c0 1913 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1914
1915 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1f7247c0 1916 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1917}
1918
1919static void ivb_err_int_handler(struct drm_device *dev)
1920{
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1923 enum pipe pipe;
8664281b 1924
de032bf4
PZ		 1925 if (err_int & ERR_INT_POISON)
1926 DRM_ERROR("Poison interrupt\n");
1927
055e393f 1928 for_each_pipe(dev_priv, pipe) {
1f7247c0
DV		 1929 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1930 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
8bf1e9f1 1931
5a69b89f
DV		 1932 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1933 if (IS_IVYBRIDGE(dev))
277de95e 1934 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1935 else
277de95e 1936 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1937 }
1938 }
8bf1e9f1 1939
8664281b
PZ		 1940 I915_WRITE(GEN7_ERR_INT, err_int);
1941}
1942
1943static void cpt_serr_int_handler(struct drm_device *dev)
1944{
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 u32 serr_int = I915_READ(SERR_INT);
1947
de032bf4
PZ		 1948 if (serr_int & SERR_INT_POISON)
1949 DRM_ERROR("PCH poison interrupt\n");
1950
8664281b 1951 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1f7247c0 1952 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1953
1954 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1f7247c0 1955 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1956
1957 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1f7247c0 1958 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
8664281b
PZ		 1959
1960 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1961}
1962
23e81d69
AJ		 1963static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1964{
2d1013dd 1965 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 1966 int pipe;
b543fb04 1967 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504
DA		 1968 u32 dig_hotplug_reg;
1969
1970 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1971 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
23e81d69 1972
13cf5504 1973 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
91d131d2 1974
cfc33bf7
VS		 1975 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1976 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1977 SDE_AUDIO_POWER_SHIFT_CPT);
1978 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1979 port_name(port));
1980 }
23e81d69
AJ		 1981
1982 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1983 dp_aux_irq_handler(dev);
23e81d69
AJ		 1984
1985 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1986 gmbus_irq_handler(dev);
23e81d69
AJ		 1987
1988 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1989 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1990
1991 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1992 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1993
1994 if (pch_iir & SDE_FDI_MASK_CPT)
055e393f 1995 for_each_pipe(dev_priv, pipe)
23e81d69
AJ		 1996 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1997 pipe_name(pipe),
1998 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1999
2000 if (pch_iir & SDE_ERROR_CPT)
2001 cpt_serr_int_handler(dev);
23e81d69
AJ		 2002}
2003
c008bc6e
PZ		 2004static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2005{
2006 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 2007 enum pipe pipe;
c008bc6e
PZ		 2008
2009 if (de_iir & DE_AUX_CHANNEL_A)
2010 dp_aux_irq_handler(dev);
2011
2012 if (de_iir & DE_GSE)
2013 intel_opregion_asle_intr(dev);
2014
c008bc6e
PZ		 2015 if (de_iir & DE_POISON)
2016 DRM_ERROR("Poison interrupt\n");
2017
055e393f 2018 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2019 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2020 intel_pipe_handle_vblank(dev, pipe))
2021 intel_check_page_flip(dev, pipe);
5b3a856b 2022
40da17c2 2023 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1f7247c0 2024 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
5b3a856b 2025
40da17c2
DV		 2026 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2027 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 2028
40da17c2
DV		 2029 /* plane/pipes map 1:1 on ilk+ */
2030 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2031 intel_prepare_page_flip(dev, pipe);
2032 intel_finish_page_flip_plane(dev, pipe);
2033 }
c008bc6e
PZ		 2034 }
2035
2036 /* check event from PCH */
2037 if (de_iir & DE_PCH_EVENT) {
2038 u32 pch_iir = I915_READ(SDEIIR);
2039
2040 if (HAS_PCH_CPT(dev))
2041 cpt_irq_handler(dev, pch_iir);
2042 else
2043 ibx_irq_handler(dev, pch_iir);
2044
2045 /* should clear PCH hotplug event before clear CPU irq */
2046 I915_WRITE(SDEIIR, pch_iir);
2047 }
2048
2049 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2050 ironlake_rps_change_irq_handler(dev);
2051}
2052
9719fb98
PZ		 2053static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2054{
2055 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 2056 enum pipe pipe;
9719fb98
PZ		 2057
2058 if (de_iir & DE_ERR_INT_IVB)
2059 ivb_err_int_handler(dev);
2060
2061 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2062 dp_aux_irq_handler(dev);
2063
2064 if (de_iir & DE_GSE_IVB)
2065 intel_opregion_asle_intr(dev);
2066
055e393f 2067 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2068 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2069 intel_pipe_handle_vblank(dev, pipe))
2070 intel_check_page_flip(dev, pipe);
40da17c2
DV		 2071
2072 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 2073 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2074 intel_prepare_page_flip(dev, pipe);
2075 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 2076 }
2077 }
2078
2079 /* check event from PCH */
2080 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2081 u32 pch_iir = I915_READ(SDEIIR);
2082
2083 cpt_irq_handler(dev, pch_iir);
2084
2085 /* clear PCH hotplug event before clear CPU irq */
2086 I915_WRITE(SDEIIR, pch_iir);
2087 }
2088}
2089
72c90f62
OM		 2090/*
2091 * To handle irqs with the minimum potential races with fresh interrupts, we:
2092 * 1 - Disable Master Interrupt Control.
2093 * 2 - Find the source(s) of the interrupt.
2094 * 3 - Clear the Interrupt Identity bits (IIR).
2095 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2096 * 5 - Re-enable Master Interrupt Control.
2097 */
f1af8fc1 2098static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 2099{
45a83f84 2100 struct drm_device *dev = arg;
2d1013dd 2101 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 2102 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 2103 irqreturn_t ret = IRQ_NONE;
b1f14ad0 2104
2dd2a883
ID		 2105 if (!intel_irqs_enabled(dev_priv))
2106 return IRQ_NONE;
2107
8664281b
PZ		 2108 /* We get interrupts on unclaimed registers, so check for this before we
2109 * do any I915_{READ,WRITE}. */
907b28c5 2110 intel_uncore_check_errors(dev);
8664281b 2111
b1f14ad0
JB		 2112 /* disable master interrupt before clearing iir */
2113 de_ier = I915_READ(DEIER);
2114 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 2115 POSTING_READ(DEIER);
b1f14ad0 2116
44498aea
PZ		 2117 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2118 * interrupts will will be stored on its back queue, and then we'll be
2119 * able to process them after we restore SDEIER (as soon as we restore
2120 * it, we'll get an interrupt if SDEIIR still has something to process
2121 * due to its back queue). */
ab5c608b
BW		 2122 if (!HAS_PCH_NOP(dev)) {
2123 sde_ier = I915_READ(SDEIER);
2124 I915_WRITE(SDEIER, 0);
2125 POSTING_READ(SDEIER);
2126 }
44498aea 2127
72c90f62
OM		 2128 /* Find, clear, then process each source of interrupt */
2129
b1f14ad0 2130 gt_iir = I915_READ(GTIIR);
0e43406b 2131 if (gt_iir) {
72c90f62
OM		 2132 I915_WRITE(GTIIR, gt_iir);
2133 ret = IRQ_HANDLED;
d8fc8a47 2134 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 2135 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 2136 else
2137 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 2138 }
2139
0e43406b
CW		 2140 de_iir = I915_READ(DEIIR);
2141 if (de_iir) {
72c90f62
OM		 2142 I915_WRITE(DEIIR, de_iir);
2143 ret = IRQ_HANDLED;
f1af8fc1
PZ		 2144 if (INTEL_INFO(dev)->gen >= 7)
2145 ivb_display_irq_handler(dev, de_iir);
2146 else
2147 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 2148 }
2149
f1af8fc1
PZ		 2150 if (INTEL_INFO(dev)->gen >= 6) {
2151 u32 pm_iir = I915_READ(GEN6_PMIIR);
2152 if (pm_iir) {
f1af8fc1
PZ		 2153 I915_WRITE(GEN6_PMIIR, pm_iir);
2154 ret = IRQ_HANDLED;
72c90f62 2155 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 2156 }
0e43406b 2157 }
b1f14ad0 2158
b1f14ad0
JB		 2159 I915_WRITE(DEIER, de_ier);
2160 POSTING_READ(DEIER);
ab5c608b
BW		 2161 if (!HAS_PCH_NOP(dev)) {
2162 I915_WRITE(SDEIER, sde_ier);
2163 POSTING_READ(SDEIER);
2164 }
b1f14ad0
JB		 2165
2166 return ret;
2167}
2168
d04a492d
SS		 2169static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
2170{
2171 struct drm_i915_private *dev_priv = dev->dev_private;
2172 uint32_t hp_control;
2173 uint32_t hp_trigger;
2174
2175 /* Get the status */
2176 hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
2177 hp_control = I915_READ(BXT_HOTPLUG_CTL);
2178
2179 /* Hotplug not enabled ? */
2180 if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
2181 DRM_ERROR("Interrupt when HPD disabled\n");
2182 return;
2183 }
2184
2185 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2186 hp_control & BXT_HOTPLUG_CTL_MASK);
2187
2188 /* Check for HPD storm and schedule bottom half */
2189 intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
2190
2191 /*
2192 * FIXME: Save the hot plug status for bottom half before
2193 * clearing the sticky status bits, else the status will be
2194 * lost.
2195 */
2196
2197 /* Clear sticky bits in hpd status */
2198 I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
2199}
2200
abd58f01
BW		 2201static irqreturn_t gen8_irq_handler(int irq, void *arg)
2202{
2203 struct drm_device *dev = arg;
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205 u32 master_ctl;
2206 irqreturn_t ret = IRQ_NONE;
2207 uint32_t tmp = 0;
c42664cc 2208 enum pipe pipe;
88e04703
JB		 2209 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2210
2dd2a883
ID		 2211 if (!intel_irqs_enabled(dev_priv))
2212 return IRQ_NONE;
2213
88e04703
JB		 2214 if (IS_GEN9(dev))
2215 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2216 GEN9_AUX_CHANNEL_D;
abd58f01 2217
cb0d205e 2218 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
abd58f01
BW		 2219 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2220 if (!master_ctl)
2221 return IRQ_NONE;
2222
cb0d205e 2223 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
abd58f01 2224
38cc46d7
OM		 2225 /* Find, clear, then process each source of interrupt */
2226
74cdb337 2227 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
abd58f01
BW		 2228
2229 if (master_ctl & GEN8_DE_MISC_IRQ) {
2230 tmp = I915_READ(GEN8_DE_MISC_IIR);
abd58f01
BW		 2231 if (tmp) {
2232 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2233 ret = IRQ_HANDLED;
38cc46d7
OM		 2234 if (tmp & GEN8_DE_MISC_GSE)
2235 intel_opregion_asle_intr(dev);
2236 else
2237 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2238 }
38cc46d7
OM		 2239 else
2240 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2241 }
2242
6d766f02
DV		 2243 if (master_ctl & GEN8_DE_PORT_IRQ) {
2244 tmp = I915_READ(GEN8_DE_PORT_IIR);
6d766f02 2245 if (tmp) {
d04a492d
SS		 2246 bool found = false;
2247
6d766f02
DV		 2248 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2249 ret = IRQ_HANDLED;
88e04703 2250
d04a492d 2251 if (tmp & aux_mask) {
38cc46d7 2252 dp_aux_irq_handler(dev);
d04a492d
SS		 2253 found = true;
2254 }
2255
2256 if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
2257 bxt_hpd_handler(dev, tmp);
2258 found = true;
2259 }
2260
9e63743e
SS		 2261 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2262 gmbus_irq_handler(dev);
2263 found = true;
2264 }
2265
d04a492d 2266 if (!found)
38cc46d7 2267 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2268 }
38cc46d7
OM		 2269 else
2270 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2271 }
2272
055e393f 2273 for_each_pipe(dev_priv, pipe) {
770de83d 2274 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
abd58f01 2275
c42664cc
DV		 2276 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2277 continue;
abd58f01 2278
c42664cc 2279 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
c42664cc
DV		 2280 if (pipe_iir) {
2281 ret = IRQ_HANDLED;
2282 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
770de83d 2283
d6bbafa1
CW		 2284 if (pipe_iir & GEN8_PIPE_VBLANK &&
2285 intel_pipe_handle_vblank(dev, pipe))
2286 intel_check_page_flip(dev, pipe);
38cc46d7 2287
770de83d
DL		 2288 if (IS_GEN9(dev))
2289 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2290 else
2291 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2292
2293 if (flip_done) {
38cc46d7
OM		 2294 intel_prepare_page_flip(dev, pipe);
2295 intel_finish_page_flip_plane(dev, pipe);
2296 }
2297
2298 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2299 hsw_pipe_crc_irq_handler(dev, pipe);
2300
1f7247c0
DV		 2301 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2302 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2303 pipe);
38cc46d7 2304
770de83d
DL		 2305
2306 if (IS_GEN9(dev))
2307 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2308 else
2309 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2310
2311 if (fault_errors)
38cc46d7
OM		 2312 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2313 pipe_name(pipe),
2314 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
c42664cc 2315 } else
abd58f01
BW		 2316 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2317 }
2318
266ea3d9
SS		 2319 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2320 master_ctl & GEN8_DE_PCH_IRQ) {
92d03a80
DV		 2321 /*
2322 * FIXME(BDW): Assume for now that the new interrupt handling
2323 * scheme also closed the SDE interrupt handling race we've seen
2324 * on older pch-split platforms. But this needs testing.
2325 */
2326 u32 pch_iir = I915_READ(SDEIIR);
92d03a80
DV		 2327 if (pch_iir) {
2328 I915_WRITE(SDEIIR, pch_iir);
2329 ret = IRQ_HANDLED;
38cc46d7
OM		 2330 cpt_irq_handler(dev, pch_iir);
2331 } else
2332 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2333
92d03a80
DV		 2334 }
2335
cb0d205e
CW		 2336 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2337 POSTING_READ_FW(GEN8_MASTER_IRQ);
abd58f01
BW		 2338
2339 return ret;
2340}
2341
17e1df07
DV		 2342static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2343 bool reset_completed)
2344{
a4872ba6 2345 struct intel_engine_cs *ring;
17e1df07
DV		 2346 int i;
2347
2348 /*
2349 * Notify all waiters for GPU completion events that reset state has
2350 * been changed, and that they need to restart their wait after
2351 * checking for potential errors (and bail out to drop locks if there is
2352 * a gpu reset pending so that i915_error_work_func can acquire them).
2353 */
2354
2355 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2356 for_each_ring(ring, dev_priv, i)
2357 wake_up_all(&ring->irq_queue);
2358
2359 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2360 wake_up_all(&dev_priv->pending_flip_queue);
2361
2362 /*
2363 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2364 * reset state is cleared.
2365 */
2366 if (reset_completed)
2367 wake_up_all(&dev_priv->gpu_error.reset_queue);
2368}
2369
8a905236 2370/**
b8d24a06 2371 * i915_reset_and_wakeup - do process context error handling work
8a905236
JB		 2372 *
2373 * Fire an error uevent so userspace can see that a hang or error
2374 * was detected.
2375 */
b8d24a06 2376static void i915_reset_and_wakeup(struct drm_device *dev)
8a905236 2377{
b8d24a06
MK		 2378 struct drm_i915_private *dev_priv = to_i915(dev);
2379 struct i915_gpu_error *error = &dev_priv->gpu_error;
cce723ed
BW		 2380 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2381 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2382 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2383 int ret;
8a905236 2384
5bdebb18 2385 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2386
7db0ba24
DV		 2387 /*
2388 * Note that there's only one work item which does gpu resets, so we
2389 * need not worry about concurrent gpu resets potentially incrementing
2390 * error->reset_counter twice. We only need to take care of another
2391 * racing irq/hangcheck declaring the gpu dead for a second time. A
2392 * quick check for that is good enough: schedule_work ensures the
2393 * correct ordering between hang detection and this work item, and since
2394 * the reset in-progress bit is only ever set by code outside of this
2395 * work we don't need to worry about any other races.
2396 */
2397 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2398 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2399 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2400 reset_event);
1f83fee0 2401
f454c694
ID		 2402 /*
2403 * In most cases it's guaranteed that we get here with an RPM
2404 * reference held, for example because there is a pending GPU
2405 * request that won't finish until the reset is done. This
2406 * isn't the case at least when we get here by doing a
2407 * simulated reset via debugs, so get an RPM reference.
2408 */
2409 intel_runtime_pm_get(dev_priv);
7514747d
VS		 2410
2411 intel_prepare_reset(dev);
2412
17e1df07
DV		 2413 /*
2414 * All state reset _must_ be completed before we update the
2415 * reset counter, for otherwise waiters might miss the reset
2416 * pending state and not properly drop locks, resulting in
2417 * deadlocks with the reset work.
2418 */
f69061be
DV		 2419 ret = i915_reset(dev);
2420
7514747d 2421 intel_finish_reset(dev);
17e1df07 2422
f454c694
ID		 2423 intel_runtime_pm_put(dev_priv);
2424
f69061be
DV		 2425 if (ret == 0) {
2426 /*
2427 * After all the gem state is reset, increment the reset
2428 * counter and wake up everyone waiting for the reset to
2429 * complete.
2430 *
2431 * Since unlock operations are a one-sided barrier only,
2432 * we need to insert a barrier here to order any seqno
2433 * updates before
2434 * the counter increment.
2435 */
4e857c58 2436 smp_mb__before_atomic();
f69061be
DV		 2437 atomic_inc(&dev_priv->gpu_error.reset_counter);
2438
5bdebb18 2439 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2440 KOBJ_CHANGE, reset_done_event);
1f83fee0 2441 } else {
2ac0f450 2442 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2443 }
1f83fee0 2444
17e1df07
DV		 2445 /*
2446 * Note: The wake_up also serves as a memory barrier so that
2447 * waiters see the update value of the reset counter atomic_t.
2448 */
2449 i915_error_wake_up(dev_priv, true);
f316a42c 2450 }
8a905236
JB		 2451}
2452
35aed2e6 2453static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2454{
2455 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2456 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2457 u32 eir = I915_READ(EIR);
050ee91f 2458 int pipe, i;
8a905236 2459
35aed2e6
CW		 2460 if (!eir)
2461 return;
8a905236 2462
a70491cc 2463 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2464
bd9854f9
BW		 2465 i915_get_extra_instdone(dev, instdone);
2466
8a905236
JB		 2467 if (IS_G4X(dev)) {
2468 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2469 u32 ipeir = I915_READ(IPEIR_I965);
2470
a70491cc
JP		 2471 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2472 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2473 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2474 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2475 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2476 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2477 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2478 POSTING_READ(IPEIR_I965);
8a905236
JB		 2479 }
2480 if (eir & GM45_ERROR_PAGE_TABLE) {
2481 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2482 pr_err("page table error\n");
2483 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2484 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2485 POSTING_READ(PGTBL_ER);
8a905236
JB		 2486 }
2487 }
2488
a6c45cf0 2489 if (!IS_GEN2(dev)) {
8a905236
JB		 2490 if (eir & I915_ERROR_PAGE_TABLE) {
2491 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2492 pr_err("page table error\n");
2493 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2494 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2495 POSTING_READ(PGTBL_ER);
8a905236
JB		 2496 }
2497 }
2498
2499 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2500 pr_err("memory refresh error:\n");
055e393f 2501 for_each_pipe(dev_priv, pipe)
a70491cc 2502 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2503 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2504 /* pipestat has already been acked */
2505 }
2506 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2507 pr_err("instruction error\n");
2508 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2509 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2510 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2511 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2512 u32 ipeir = I915_READ(IPEIR);
2513
a70491cc
JP		 2514 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2515 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2516 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2517 I915_WRITE(IPEIR, ipeir);
3143a2bf 2518 POSTING_READ(IPEIR);
8a905236
JB		 2519 } else {
2520 u32 ipeir = I915_READ(IPEIR_I965);
2521
a70491cc
JP		 2522 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2523 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2524 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2525 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2526 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2527 POSTING_READ(IPEIR_I965);
8a905236
JB		 2528 }
2529 }
2530
2531 I915_WRITE(EIR, eir);
3143a2bf 2532 POSTING_READ(EIR);
8a905236
JB		 2533 eir = I915_READ(EIR);
2534 if (eir) {
2535 /*
2536 * some errors might have become stuck,
2537 * mask them.
2538 */
2539 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2540 I915_WRITE(EMR, I915_READ(EMR) | eir);
2541 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2542 }
35aed2e6
CW		 2543}
2544
2545/**
b8d24a06 2546 * i915_handle_error - handle a gpu error
35aed2e6
CW		 2547 * @dev: drm device
2548 *
b8d24a06 2549 * Do some basic checking of regsiter state at error time and
35aed2e6
CW		 2550 * dump it to the syslog. Also call i915_capture_error_state() to make
2551 * sure we get a record and make it available in debugfs. Fire a uevent
2552 * so userspace knows something bad happened (should trigger collection
2553 * of a ring dump etc.).
2554 */
58174462
MK		 2555void i915_handle_error(struct drm_device *dev, bool wedged,
2556 const char *fmt, ...)
35aed2e6
CW		 2557{
2558 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2559 va_list args;
2560 char error_msg[80];
35aed2e6 2561
58174462
MK		 2562 va_start(args, fmt);
2563 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2564 va_end(args);
2565
2566 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2567 i915_report_and_clear_eir(dev);
8a905236 2568
ba1234d1 2569 if (wedged) {
f69061be
DV		 2570 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2571 &dev_priv->gpu_error.reset_counter);
ba1234d1 2572
11ed50ec 2573 /*
b8d24a06
MK		 2574 * Wakeup waiting processes so that the reset function
2575 * i915_reset_and_wakeup doesn't deadlock trying to grab
2576 * various locks. By bumping the reset counter first, the woken
17e1df07
DV		 2577 * processes will see a reset in progress and back off,
2578 * releasing their locks and then wait for the reset completion.
2579 * We must do this for _all_ gpu waiters that might hold locks
2580 * that the reset work needs to acquire.
2581 *
2582 * Note: The wake_up serves as the required memory barrier to
2583 * ensure that the waiters see the updated value of the reset
2584 * counter atomic_t.
11ed50ec 2585 */
17e1df07 2586 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2587 }
2588
b8d24a06 2589 i915_reset_and_wakeup(dev);
8a905236
JB		 2590}
2591
42f52ef8
KP		 2592/* Called from drm generic code, passed 'crtc' which
2593 * we use as a pipe index
2594 */
f71d4af4 2595static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2596{
2d1013dd 2597 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2598 unsigned long irqflags;
71e0ffa5 2599
1ec14ad3 2600 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2601 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2602 i915_enable_pipestat(dev_priv, pipe,
755e9019 2603 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2604 else
7c463586 2605 i915_enable_pipestat(dev_priv, pipe,
755e9019 2606 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2607 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2608
0a3e67a4
JB		 2609 return 0;
2610}
2611
f71d4af4 2612static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2613{
2d1013dd 2614 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2615 unsigned long irqflags;
b518421f 2616 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2617 DE_PIPE_VBLANK(pipe);
f796cf8f 2618
f796cf8f 2619 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2620 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2621 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2622
2623 return 0;
2624}
2625
7e231dbe
JB		 2626static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2627{
2d1013dd 2628 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2629 unsigned long irqflags;
7e231dbe 2630
7e231dbe 2631 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2632 i915_enable_pipestat(dev_priv, pipe,
755e9019 2633 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2634 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2635
2636 return 0;
2637}
2638
abd58f01
BW		 2639static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2640{
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 unsigned long irqflags;
abd58f01 2643
abd58f01 2644 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2645 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2646 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2647 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2648 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2649 return 0;
2650}
2651
42f52ef8
KP		 2652/* Called from drm generic code, passed 'crtc' which
2653 * we use as a pipe index
2654 */
f71d4af4 2655static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2656{
2d1013dd 2657 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2658 unsigned long irqflags;
0a3e67a4 2659
1ec14ad3 2660 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2661 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2662 PIPE_VBLANK_INTERRUPT_STATUS |
2663 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2664 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2665}
2666
f71d4af4 2667static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2668{
2d1013dd 2669 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2670 unsigned long irqflags;
b518421f 2671 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2672 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2673
2674 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2675 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2676 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2677}
2678
7e231dbe
JB		 2679static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2680{
2d1013dd 2681 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2682 unsigned long irqflags;
7e231dbe
JB		 2683
2684 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2685 i915_disable_pipestat(dev_priv, pipe,
755e9019 2686 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2687 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2688}
2689
abd58f01
BW		 2690static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2691{
2692 struct drm_i915_private *dev_priv = dev->dev_private;
2693 unsigned long irqflags;
abd58f01 2694
abd58f01 2695 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2696 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2697 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2698 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2699 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2700}
2701
44cdd6d2
JH		 2702static struct drm_i915_gem_request *
2703ring_last_request(struct intel_engine_cs *ring)
852835f3 2704{
893eead0 2705 return list_entry(ring->request_list.prev,
44cdd6d2 2706 struct drm_i915_gem_request, list);
893eead0
CW		 2707}
2708
9107e9d2 2709static bool
44cdd6d2 2710ring_idle(struct intel_engine_cs *ring)
9107e9d2
CW		 2711{
2712 return (list_empty(&ring->request_list) ||
1b5a433a 2713 i915_gem_request_completed(ring_last_request(ring), false));
f65d9421
BG		 2714}
2715
a028c4b0
DV		 2716static bool
2717ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2718{
2719 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 2720 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 2721 } else {
2722 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2723 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2724 MI_SEMAPHORE_REGISTER);
2725 }
2726}
2727
a4872ba6 2728static struct intel_engine_cs *
a6cdb93a 2729semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
921d42ea
DV		 2730{
2731 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2732 struct intel_engine_cs *signaller;
921d42ea
DV		 2733 int i;
2734
2735 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
a6cdb93a
RV		 2736 for_each_ring(signaller, dev_priv, i) {
2737 if (ring == signaller)
2738 continue;
2739
2740 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2741 return signaller;
2742 }
921d42ea
DV		 2743 } else {
2744 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2745
2746 for_each_ring(signaller, dev_priv, i) {
2747 if(ring == signaller)
2748 continue;
2749
ebc348b2 2750 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
921d42ea
DV		 2751 return signaller;
2752 }
2753 }
2754
a6cdb93a
RV		 2755 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2756 ring->id, ipehr, offset);
921d42ea
DV		 2757
2758 return NULL;
2759}
2760
a4872ba6
OM		 2761static struct intel_engine_cs *
2762semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
a24a11e6
CW		 2763{
2764 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d 2765 u32 cmd, ipehr, head;
a6cdb93a
RV		 2766 u64 offset = 0;
2767 int i, backwards;
a24a11e6
CW		 2768
2769 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2770 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2771 return NULL;
a24a11e6 2772
88fe429d
DV		 2773 /*
2774 * HEAD is likely pointing to the dword after the actual command,
2775 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 2776 * or 4 dwords depending on the semaphore wait command size.
2777 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 2778 * point at at batch, and semaphores are always emitted into the
2779 * ringbuffer itself.
a24a11e6 2780 */
88fe429d 2781 head = I915_READ_HEAD(ring) & HEAD_ADDR;
a6cdb93a 2782 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
88fe429d 2783
a6cdb93a 2784 for (i = backwards; i; --i) {
88fe429d
DV		 2785 /*
2786 * Be paranoid and presume the hw has gone off into the wild -
2787 * our ring is smaller than what the hardware (and hence
2788 * HEAD_ADDR) allows. Also handles wrap-around.
2789 */
ee1b1e5e 2790 head &= ring->buffer->size - 1;
88fe429d
DV		 2791
2792 /* This here seems to blow up */
ee1b1e5e 2793 cmd = ioread32(ring->buffer->virtual_start + head);
a24a11e6
CW		 2794 if (cmd == ipehr)
2795 break;
2796
88fe429d
DV		 2797 head -= 4;
2798 }
a24a11e6 2799
88fe429d
DV		 2800 if (!i)
2801 return NULL;
a24a11e6 2802
ee1b1e5e 2803 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
a6cdb93a
RV		 2804 if (INTEL_INFO(ring->dev)->gen >= 8) {
2805 offset = ioread32(ring->buffer->virtual_start + head + 12);
2806 offset <<= 32;
2807 offset = ioread32(ring->buffer->virtual_start + head + 8);
2808 }
2809 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
a24a11e6
CW		 2810}
2811
a4872ba6 2812static int semaphore_passed(struct intel_engine_cs *ring)
6274f212
CW		 2813{
2814 struct drm_i915_private *dev_priv = ring->dev->dev_private;
a4872ba6 2815 struct intel_engine_cs *signaller;
a0d036b0 2816 u32 seqno;
6274f212 2817
4be17381 2818 ring->hangcheck.deadlock++;
6274f212
CW		 2819
2820 signaller = semaphore_waits_for(ring, &seqno);
4be17381
CW		 2821 if (signaller == NULL)
2822 return -1;
2823
2824 /* Prevent pathological recursion due to driver bugs */
2825 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
6274f212
CW		 2826 return -1;
2827
4be17381
CW		 2828 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2829 return 1;
2830
a0d036b0
CW		 2831 /* cursory check for an unkickable deadlock */
2832 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2833 semaphore_passed(signaller) < 0)
4be17381
CW		 2834 return -1;
2835
2836 return 0;
6274f212
CW		 2837}
2838
2839static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2840{
a4872ba6 2841 struct intel_engine_cs *ring;
6274f212
CW		 2842 int i;
2843
2844 for_each_ring(ring, dev_priv, i)
4be17381 2845 ring->hangcheck.deadlock = 0;
6274f212
CW		 2846}
2847
ad8beaea 2848static enum intel_ring_hangcheck_action
a4872ba6 2849ring_stuck(struct intel_engine_cs *ring, u64 acthd)
1ec14ad3
CW		 2850{
2851 struct drm_device *dev = ring->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2853 u32 tmp;
2854
f260fe7b
MK		 2855 if (acthd != ring->hangcheck.acthd) {
2856 if (acthd > ring->hangcheck.max_acthd) {
2857 ring->hangcheck.max_acthd = acthd;
2858 return HANGCHECK_ACTIVE;
2859 }
2860
2861 return HANGCHECK_ACTIVE_LOOP;
2862 }
6274f212 2863
9107e9d2 2864 if (IS_GEN2(dev))
f2f4d82f 2865 return HANGCHECK_HUNG;
9107e9d2
CW		 2866
2867 /* Is the chip hanging on a WAIT_FOR_EVENT?
2868 * If so we can simply poke the RB_WAIT bit
2869 * and break the hang. This should work on
2870 * all but the second generation chipsets.
2871 */
2872 tmp = I915_READ_CTL(ring);
1ec14ad3 2873 if (tmp & RING_WAIT) {
58174462
MK		 2874 i915_handle_error(dev, false,
2875 "Kicking stuck wait on %s",
2876 ring->name);
1ec14ad3 2877 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2878 return HANGCHECK_KICK;
6274f212
CW		 2879 }
2880
2881 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2882 switch (semaphore_passed(ring)) {
2883 default:
f2f4d82f 2884 return HANGCHECK_HUNG;
6274f212 2885 case 1:
58174462
MK		 2886 i915_handle_error(dev, false,
2887 "Kicking stuck semaphore on %s",
2888 ring->name);
6274f212 2889 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2890 return HANGCHECK_KICK;
6274f212 2891 case 0:
f2f4d82f 2892 return HANGCHECK_WAIT;
6274f212 2893 }
9107e9d2 2894 }
ed5cbb03 2895
f2f4d82f 2896 return HANGCHECK_HUNG;
ed5cbb03
MK		 2897}
2898
737b1506 2899/*
f65d9421 2900 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2901 * batchbuffers in a long time. We keep track per ring seqno progress and
2902 * if there are no progress, hangcheck score for that ring is increased.
2903 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2904 * we kick the ring. If we see no progress on three subsequent calls
2905 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2906 */
737b1506 2907static void i915_hangcheck_elapsed(struct work_struct *work)
f65d9421 2908{
737b1506
CW		 2909 struct drm_i915_private *dev_priv =
2910 container_of(work, typeof(*dev_priv),
2911 gpu_error.hangcheck_work.work);
2912 struct drm_device *dev = dev_priv->dev;
a4872ba6 2913 struct intel_engine_cs *ring;
b4519513 2914 int i;
05407ff8 2915 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2916 bool stuck[I915_NUM_RINGS] = { 0 };
2917#define BUSY 1
2918#define KICK 5
2919#define HUNG 20
893eead0 2920
d330a953 2921 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2922 return;
2923
b4519513 2924 for_each_ring(ring, dev_priv, i) {
50877445
CW		 2925 u64 acthd;
2926 u32 seqno;
9107e9d2 2927 bool busy = true;
05407ff8 2928
6274f212
CW		 2929 semaphore_clear_deadlocks(dev_priv);
2930
05407ff8
MK		 2931 seqno = ring->get_seqno(ring, false);
2932 acthd = intel_ring_get_active_head(ring);
b4519513 2933
9107e9d2 2934 if (ring->hangcheck.seqno == seqno) {
44cdd6d2 2935 if (ring_idle(ring)) {
da661464
MK		 2936 ring->hangcheck.action = HANGCHECK_IDLE;
2937
9107e9d2
CW		 2938 if (waitqueue_active(&ring->irq_queue)) {
2939 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2940 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2941 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2942 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2943 ring->name);
2944 else
2945 DRM_INFO("Fake missed irq on %s\n",
2946 ring->name);
094f9a54
CW		 2947 wake_up_all(&ring->irq_queue);
2948 }
2949 /* Safeguard against driver failure */
2950 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2951 } else
2952 busy = false;
05407ff8 2953 } else {
6274f212
CW		 2954 /* We always increment the hangcheck score
2955 * if the ring is busy and still processing
2956 * the same request, so that no single request
2957 * can run indefinitely (such as a chain of
2958 * batches). The only time we do not increment
2959 * the hangcheck score on this ring, if this
2960 * ring is in a legitimate wait for another
2961 * ring. In that case the waiting ring is a
2962 * victim and we want to be sure we catch the
2963 * right culprit. Then every time we do kick
2964 * the ring, add a small increment to the
2965 * score so that we can catch a batch that is
2966 * being repeatedly kicked and so responsible
2967 * for stalling the machine.
2968 */
ad8beaea
MK		 2969 ring->hangcheck.action = ring_stuck(ring,
2970 acthd);
2971
2972 switch (ring->hangcheck.action) {
da661464 2973 case HANGCHECK_IDLE:
f2f4d82f 2974 case HANGCHECK_WAIT:
f2f4d82f 2975 case HANGCHECK_ACTIVE:
f260fe7b
MK		 2976 break;
2977 case HANGCHECK_ACTIVE_LOOP:
ea04cb31 2978 ring->hangcheck.score += BUSY;
6274f212 2979 break;
f2f4d82f 2980 case HANGCHECK_KICK:
ea04cb31 2981 ring->hangcheck.score += KICK;
6274f212 2982 break;
f2f4d82f 2983 case HANGCHECK_HUNG:
ea04cb31 2984 ring->hangcheck.score += HUNG;
6274f212
CW		 2985 stuck[i] = true;
2986 break;
2987 }
05407ff8 2988 }
9107e9d2 2989 } else {
da661464
MK		 2990 ring->hangcheck.action = HANGCHECK_ACTIVE;
2991
9107e9d2
CW		 2992 /* Gradually reduce the count so that we catch DoS
2993 * attempts across multiple batches.
2994 */
2995 if (ring->hangcheck.score > 0)
2996 ring->hangcheck.score--;
f260fe7b
MK		 2997
2998 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
d1e61e7f
CW		 2999 }
3000
05407ff8
MK		 3001 ring->hangcheck.seqno = seqno;
3002 ring->hangcheck.acthd = acthd;
9107e9d2 3003 busy_count += busy;
893eead0 3004 }
b9201c14 3005
92cab734 3006 for_each_ring(ring, dev_priv, i) {
b6b0fac0 3007 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 3008 DRM_INFO("%s on %s\n",
3009 stuck[i] ? "stuck" : "no progress",
3010 ring->name);
a43adf07 3011 rings_hung++;
92cab734
MK		 3012 }
3013 }
3014
05407ff8 3015 if (rings_hung)
58174462 3016 return i915_handle_error(dev, true, "Ring hung");
f65d9421 3017
05407ff8
MK		 3018 if (busy_count)
3019 /* Reset timer case chip hangs without another request
3020 * being added */
10cd45b6
MK		 3021 i915_queue_hangcheck(dev);
3022}
3023
3024void i915_queue_hangcheck(struct drm_device *dev)
3025{
737b1506 3026 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
672e7b7c 3027
d330a953 3028 if (!i915.enable_hangcheck)
10cd45b6
MK		 3029 return;
3030
737b1506
CW		 3031 /* Don't continually defer the hangcheck so that it is always run at
3032 * least once after work has been scheduled on any ring. Otherwise,
3033 * we will ignore a hung ring if a second ring is kept busy.
3034 */
3035
3036 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3037 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 3038}
3039
1c69eb42 3040static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 3041{
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043
3044 if (HAS_PCH_NOP(dev))
3045 return;
3046
f86f3fb0 3047 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 3048
3049 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3050 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 3051}
105b122e 3052
622364b6
PZ		 3053/*
3054 * SDEIER is also touched by the interrupt handler to work around missed PCH
3055 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3056 * instead we unconditionally enable all PCH interrupt sources here, but then
3057 * only unmask them as needed with SDEIMR.
3058 *
3059 * This function needs to be called before interrupts are enabled.
3060 */
3061static void ibx_irq_pre_postinstall(struct drm_device *dev)
3062{
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064
3065 if (HAS_PCH_NOP(dev))
3066 return;
3067
3068 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 3069 I915_WRITE(SDEIER, 0xffffffff);
3070 POSTING_READ(SDEIER);
3071}
3072
7c4d664e 3073static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 3074{
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076
f86f3fb0 3077 GEN5_IRQ_RESET(GT);
a9d356a6 3078 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 3079 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 3080}
3081
1da177e4
LT		 3082/* drm_dma.h hooks
3083*/
be30b29f 3084static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 3085{
2d1013dd 3086 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 3087
0c841212 3088 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 3089
f86f3fb0 3090 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 3091 if (IS_GEN7(dev))
3092 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3093
7c4d664e 3094 gen5_gt_irq_reset(dev);
c650156a 3095
1c69eb42 3096 ibx_irq_reset(dev);
7d99163d 3097}
c650156a 3098
70591a41
VS		 3099static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3100{
3101 enum pipe pipe;
3102
3103 I915_WRITE(PORT_HOTPLUG_EN, 0);
3104 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3105
3106 for_each_pipe(dev_priv, pipe)
3107 I915_WRITE(PIPESTAT(pipe), 0xffff);
3108
3109 GEN5_IRQ_RESET(VLV_);
3110}
3111
7e231dbe
JB		 3112static void valleyview_irq_preinstall(struct drm_device *dev)
3113{
2d1013dd 3114 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 3115
7e231dbe
JB		 3116 /* VLV magic */
3117 I915_WRITE(VLV_IMR, 0);
3118 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3119 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3120 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3121
7c4d664e 3122 gen5_gt_irq_reset(dev);
7e231dbe 3123
7c4cde39 3124 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
7e231dbe 3125
70591a41 3126 vlv_display_irq_reset(dev_priv);
7e231dbe
JB		 3127}
3128
d6e3cca3
DV		 3129static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3130{
3131 GEN8_IRQ_RESET_NDX(GT, 0);
3132 GEN8_IRQ_RESET_NDX(GT, 1);
3133 GEN8_IRQ_RESET_NDX(GT, 2);
3134 GEN8_IRQ_RESET_NDX(GT, 3);
3135}
3136
823f6b38 3137static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 3138{
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 int pipe;
3141
abd58f01
BW		 3142 I915_WRITE(GEN8_MASTER_IRQ, 0);
3143 POSTING_READ(GEN8_MASTER_IRQ);
3144
d6e3cca3 3145 gen8_gt_irq_reset(dev_priv);
abd58f01 3146
055e393f 3147 for_each_pipe(dev_priv, pipe)
f458ebbc
DV		 3148 if (intel_display_power_is_enabled(dev_priv,
3149 POWER_DOMAIN_PIPE(pipe)))
813bde43 3150 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3151
f86f3fb0
PZ		 3152 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3153 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3154 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 3155
266ea3d9
SS		 3156 if (HAS_PCH_SPLIT(dev))
3157 ibx_irq_reset(dev);
abd58f01 3158}
09f2344d 3159
4c6c03be
DL		 3160void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3161 unsigned int pipe_mask)
d49bdb0e 3162{
1180e206 3163 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
d49bdb0e 3164
13321786 3165 spin_lock_irq(&dev_priv->irq_lock);
d14c0343
DL		 3166 if (pipe_mask & 1 << PIPE_A)
3167 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3168 dev_priv->de_irq_mask[PIPE_A],
3169 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
4c6c03be
DL		 3170 if (pipe_mask & 1 << PIPE_B)
3171 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3172 dev_priv->de_irq_mask[PIPE_B],
3173 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3174 if (pipe_mask & 1 << PIPE_C)
3175 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3176 dev_priv->de_irq_mask[PIPE_C],
3177 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
13321786 3178 spin_unlock_irq(&dev_priv->irq_lock);
d49bdb0e
PZ		 3179}
3180
43f328d7
VS		 3181static void cherryview_irq_preinstall(struct drm_device *dev)
3182{
3183 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3184
3185 I915_WRITE(GEN8_MASTER_IRQ, 0);
3186 POSTING_READ(GEN8_MASTER_IRQ);
3187
d6e3cca3 3188 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 3189
3190 GEN5_IRQ_RESET(GEN8_PCU_);
3191
43f328d7
VS		 3192 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3193
70591a41 3194 vlv_display_irq_reset(dev_priv);
43f328d7
VS		 3195}
3196
82a28bcf 3197static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 3198{
2d1013dd 3199 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3200 struct intel_encoder *intel_encoder;
fee884ed 3201 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 3202
3203 if (HAS_PCH_IBX(dev)) {
fee884ed 3204 hotplug_irqs = SDE_HOTPLUG_MASK;
b2784e15 3205 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3206 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3207 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 3208 } else {
fee884ed 3209 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
b2784e15 3210 for_each_intel_encoder(dev, intel_encoder)
cd569aed 3211 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 3212 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 3213 }
7fe0b973 3214
fee884ed 3215 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3216
3217 /*
3218 * Enable digital hotplug on the PCH, and configure the DP short pulse
3219 * duration to 2ms (which is the minimum in the Display Port spec)
3220 *
3221 * This register is the same on all known PCH chips.
3222 */
7fe0b973
KP		 3223 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3224 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3225 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3226 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3227 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3228 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3229}
3230
e0a20ad7
SS		 3231static void bxt_hpd_irq_setup(struct drm_device *dev)
3232{
3233 struct drm_i915_private *dev_priv = dev->dev_private;
3234 struct intel_encoder *intel_encoder;
3235 u32 hotplug_port = 0;
3236 u32 hotplug_ctrl;
3237
3238 /* Now, enable HPD */
3239 for_each_intel_encoder(dev, intel_encoder) {
3240 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
3241 == HPD_ENABLED)
3242 hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
3243 }
3244
3245 /* Mask all HPD control bits */
3246 hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
3247
3248 /* Enable requested port in hotplug control */
3249 /* TODO: implement (short) HPD support on port A */
3250 WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
3251 if (hotplug_port & BXT_DE_PORT_HP_DDIB)
3252 hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
3253 if (hotplug_port & BXT_DE_PORT_HP_DDIC)
3254 hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
3255 I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
3256
3257 /* Unmask DDI hotplug in IMR */
3258 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
3259 I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
3260
3261 /* Enable DDI hotplug in IER */
3262 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
3263 I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
3264 POSTING_READ(GEN8_DE_PORT_IER);
3265}
3266
d46da437
PZ		 3267static void ibx_irq_postinstall(struct drm_device *dev)
3268{
2d1013dd 3269 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3270 u32 mask;
e5868a31 3271
692a04cf
DV		 3272 if (HAS_PCH_NOP(dev))
3273 return;
3274
105b122e 3275 if (HAS_PCH_IBX(dev))
5c673b60 3276 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3277 else
5c673b60 3278 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3279
337ba017 3280 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3281 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3282}
3283
0a9a8c91
DV		 3284static void gen5_gt_irq_postinstall(struct drm_device *dev)
3285{
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 u32 pm_irqs, gt_irqs;
3288
3289 pm_irqs = gt_irqs = 0;
3290
3291 dev_priv->gt_irq_mask = ~0;
040d2baa 3292 if (HAS_L3_DPF(dev)) {
0a9a8c91 3293 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3294 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3295 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3296 }
3297
3298 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3299 if (IS_GEN5(dev)) {
3300 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3301 ILK_BSD_USER_INTERRUPT;
3302 } else {
3303 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3304 }
3305
35079899 3306 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3307
3308 if (INTEL_INFO(dev)->gen >= 6) {
78e68d36
ID		 3309 /*
3310 * RPS interrupts will get enabled/disabled on demand when RPS
3311 * itself is enabled/disabled.
3312 */
0a9a8c91
DV		 3313 if (HAS_VEBOX(dev))
3314 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3315
605cd25b 3316 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3317 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3318 }
3319}
3320
f71d4af4 3321static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3322{
2d1013dd 3323 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3324 u32 display_mask, extra_mask;
3325
3326 if (INTEL_INFO(dev)->gen >= 7) {
3327 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3328 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3329 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3330 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3331 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3332 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3333 } else {
3334 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3335 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3336 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3337 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3338 DE_POISON);
5c673b60
DV		 3339 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3340 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3341 }
036a4a7d 3342
1ec14ad3 3343 dev_priv->irq_mask = ~display_mask;
036a4a7d 3344
0c841212
PZ		 3345 I915_WRITE(HWSTAM, 0xeffe);
3346
622364b6
PZ		 3347 ibx_irq_pre_postinstall(dev);
3348
35079899 3349 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3350
0a9a8c91 3351 gen5_gt_irq_postinstall(dev);
036a4a7d 3352
d46da437 3353 ibx_irq_postinstall(dev);
7fe0b973 3354
f97108d1 3355 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3356 /* Enable PCU event interrupts
3357 *
3358 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3359 * setup is guaranteed to run in single-threaded context. But we
3360 * need it to make the assert_spin_locked happy. */
d6207435 3361 spin_lock_irq(&dev_priv->irq_lock);
f97108d1 3362 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
d6207435 3363 spin_unlock_irq(&dev_priv->irq_lock);
f97108d1
JB		 3364 }
3365
036a4a7d
ZW		 3366 return 0;
3367}
3368
f8b79e58
ID		 3369static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3370{
3371 u32 pipestat_mask;
3372 u32 iir_mask;
120dda4f 3373 enum pipe pipe;
f8b79e58
ID		 3374
3375 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3376 PIPE_FIFO_UNDERRUN_STATUS;
3377
120dda4f
VS		 3378 for_each_pipe(dev_priv, pipe)
3379 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3380 POSTING_READ(PIPESTAT(PIPE_A));
3381
3382 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3383 PIPE_CRC_DONE_INTERRUPT_STATUS;
3384
120dda4f
VS		 3385 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3386 for_each_pipe(dev_priv, pipe)
3387 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3388
3389 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3390 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3391 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3392 if (IS_CHERRYVIEW(dev_priv))
3393 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3394 dev_priv->irq_mask &= ~iir_mask;
3395
3396 I915_WRITE(VLV_IIR, iir_mask);
3397 I915_WRITE(VLV_IIR, iir_mask);
f8b79e58 3398 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
76e41860
VS		 3399 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3400 POSTING_READ(VLV_IMR);
f8b79e58
ID		 3401}
3402
3403static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3404{
3405 u32 pipestat_mask;
3406 u32 iir_mask;
120dda4f 3407 enum pipe pipe;
f8b79e58
ID		 3408
3409 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3410 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3411 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3412 if (IS_CHERRYVIEW(dev_priv))
3413 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3414
3415 dev_priv->irq_mask |= iir_mask;
f8b79e58 3416 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
76e41860 3417 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
f8b79e58
ID		 3418 I915_WRITE(VLV_IIR, iir_mask);
3419 I915_WRITE(VLV_IIR, iir_mask);
3420 POSTING_READ(VLV_IIR);
3421
3422 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3423 PIPE_CRC_DONE_INTERRUPT_STATUS;
3424
120dda4f
VS		 3425 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3426 for_each_pipe(dev_priv, pipe)
3427 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3428
3429 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3430 PIPE_FIFO_UNDERRUN_STATUS;
120dda4f
VS		 3431
3432 for_each_pipe(dev_priv, pipe)
3433 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3434 POSTING_READ(PIPESTAT(PIPE_A));
3435}
3436
3437void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3438{
3439 assert_spin_locked(&dev_priv->irq_lock);
3440
3441 if (dev_priv->display_irqs_enabled)
3442 return;
3443
3444 dev_priv->display_irqs_enabled = true;
3445
950eabaf 3446 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3447 valleyview_display_irqs_install(dev_priv);
3448}
3449
3450void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3451{
3452 assert_spin_locked(&dev_priv->irq_lock);
3453
3454 if (!dev_priv->display_irqs_enabled)
3455 return;
3456
3457 dev_priv->display_irqs_enabled = false;
3458
950eabaf 3459 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3460 valleyview_display_irqs_uninstall(dev_priv);
3461}
3462
0e6c9a9e 3463static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
7e231dbe 3464{
f8b79e58 3465 dev_priv->irq_mask = ~0;
7e231dbe 3466
20afbda2
DV		 3467 I915_WRITE(PORT_HOTPLUG_EN, 0);
3468 POSTING_READ(PORT_HOTPLUG_EN);
3469
7e231dbe 3470 I915_WRITE(VLV_IIR, 0xffffffff);
76e41860
VS		 3471 I915_WRITE(VLV_IIR, 0xffffffff);
3472 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3473 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3474 POSTING_READ(VLV_IMR);
7e231dbe 3475
b79480ba
DV		 3476 /* Interrupt setup is already guaranteed to be single-threaded, this is
3477 * just to make the assert_spin_locked check happy. */
d6207435 3478 spin_lock_irq(&dev_priv->irq_lock);
f8b79e58
ID		 3479 if (dev_priv->display_irqs_enabled)
3480 valleyview_display_irqs_install(dev_priv);
d6207435 3481 spin_unlock_irq(&dev_priv->irq_lock);
0e6c9a9e
VS		 3482}
3483
3484static int valleyview_irq_postinstall(struct drm_device *dev)
3485{
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487
3488 vlv_display_irq_postinstall(dev_priv);
7e231dbe 3489
0a9a8c91 3490 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3491
3492 /* ack & enable invalid PTE error interrupts */
3493#if 0 /* FIXME: add support to irq handler for checking these bits */
3494 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3495 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3496#endif
3497
3498 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3499
3500 return 0;
3501}
3502
abd58f01
BW		 3503static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3504{
abd58f01
BW		 3505 /* These are interrupts we'll toggle with the ring mask register */
3506 uint32_t gt_interrupts[] = {
3507 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3508 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3509 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3510 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3511 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3512 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3513 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3514 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3515 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3516 0,
73d477f6
OM		 3517 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3518 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3519 };
3520
0961021a 3521 dev_priv->pm_irq_mask = 0xffffffff;
9a2d2d87
D		 3522 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3523 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
78e68d36
ID		 3524 /*
3525 * RPS interrupts will get enabled/disabled on demand when RPS itself
3526 * is enabled/disabled.
3527 */
3528 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
9a2d2d87 3529 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
abd58f01
BW		 3530}
3531
3532static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3533{
770de83d
DL		 3534 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3535 uint32_t de_pipe_enables;
abd58f01 3536 int pipe;
9e63743e 3537 u32 de_port_en = GEN8_AUX_CHANNEL_A;
770de83d 3538
88e04703 3539 if (IS_GEN9(dev_priv)) {
770de83d
DL		 3540 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3541 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
9e63743e 3542 de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
88e04703 3543 GEN9_AUX_CHANNEL_D;
9e63743e
SS		 3544
3545 if (IS_BROXTON(dev_priv))
3546 de_port_en |= BXT_DE_PORT_GMBUS;
88e04703 3547 } else
770de83d
DL		 3548 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3549 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3550
3551 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3552 GEN8_PIPE_FIFO_UNDERRUN;
3553
13b3a0a7
DV		 3554 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3555 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3556 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3557
055e393f 3558 for_each_pipe(dev_priv, pipe)
f458ebbc 3559 if (intel_display_power_is_enabled(dev_priv,
813bde43
PZ		 3560 POWER_DOMAIN_PIPE(pipe)))
3561 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3562 dev_priv->de_irq_mask[pipe],
3563 de_pipe_enables);
abd58f01 3564
9e63743e 3565 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
abd58f01
BW		 3566}
3567
3568static int gen8_irq_postinstall(struct drm_device *dev)
3569{
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571
266ea3d9
SS		 3572 if (HAS_PCH_SPLIT(dev))
3573 ibx_irq_pre_postinstall(dev);
622364b6 3574
abd58f01
BW		 3575 gen8_gt_irq_postinstall(dev_priv);
3576 gen8_de_irq_postinstall(dev_priv);
3577
266ea3d9
SS		 3578 if (HAS_PCH_SPLIT(dev))
3579 ibx_irq_postinstall(dev);
abd58f01
BW		 3580
3581 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3582 POSTING_READ(GEN8_MASTER_IRQ);
3583
3584 return 0;
3585}
3586
43f328d7
VS		 3587static int cherryview_irq_postinstall(struct drm_device *dev)
3588{
3589 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7 3590
c2b66797 3591 vlv_display_irq_postinstall(dev_priv);
43f328d7
VS		 3592
3593 gen8_gt_irq_postinstall(dev_priv);
3594
3595 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3596 POSTING_READ(GEN8_MASTER_IRQ);
3597
3598 return 0;
3599}
3600
abd58f01
BW		 3601static void gen8_irq_uninstall(struct drm_device *dev)
3602{
3603 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3604
3605 if (!dev_priv)
3606 return;
3607
823f6b38 3608 gen8_irq_reset(dev);
abd58f01
BW		 3609}
3610
8ea0be4f
VS		 3611static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3612{
3613 /* Interrupt setup is already guaranteed to be single-threaded, this is
3614 * just to make the assert_spin_locked check happy. */
3615 spin_lock_irq(&dev_priv->irq_lock);
3616 if (dev_priv->display_irqs_enabled)
3617 valleyview_display_irqs_uninstall(dev_priv);
3618 spin_unlock_irq(&dev_priv->irq_lock);
3619
3620 vlv_display_irq_reset(dev_priv);
3621
c352d1ba 3622 dev_priv->irq_mask = ~0;
8ea0be4f
VS		 3623}
3624
7e231dbe
JB		 3625static void valleyview_irq_uninstall(struct drm_device *dev)
3626{
2d1013dd 3627 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3628
3629 if (!dev_priv)
3630 return;
3631
843d0e7d
ID		 3632 I915_WRITE(VLV_MASTER_IER, 0);
3633
893fce8e
VS		 3634 gen5_gt_irq_reset(dev);
3635
7e231dbe 3636 I915_WRITE(HWSTAM, 0xffffffff);
f8b79e58 3637
8ea0be4f 3638 vlv_display_irq_uninstall(dev_priv);
7e231dbe
JB		 3639}
3640
43f328d7
VS		 3641static void cherryview_irq_uninstall(struct drm_device *dev)
3642{
3643 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3644
3645 if (!dev_priv)
3646 return;
3647
3648 I915_WRITE(GEN8_MASTER_IRQ, 0);
3649 POSTING_READ(GEN8_MASTER_IRQ);
3650
a2c30fba 3651 gen8_gt_irq_reset(dev_priv);
43f328d7 3652
a2c30fba 3653 GEN5_IRQ_RESET(GEN8_PCU_);
43f328d7 3654
c2b66797 3655 vlv_display_irq_uninstall(dev_priv);
43f328d7
VS		 3656}
3657
f71d4af4 3658static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3659{
2d1013dd 3660 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3661
3662 if (!dev_priv)
3663 return;
3664
be30b29f 3665 ironlake_irq_reset(dev);
036a4a7d
ZW		 3666}
3667
a266c7d5 3668static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3669{
2d1013dd 3670 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3671 int pipe;
91e3738e 3672
055e393f 3673 for_each_pipe(dev_priv, pipe)
9db4a9c7 3674 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3675 I915_WRITE16(IMR, 0xffff);
3676 I915_WRITE16(IER, 0x0);
3677 POSTING_READ16(IER);
c2798b19
CW		 3678}
3679
3680static int i8xx_irq_postinstall(struct drm_device *dev)
3681{
2d1013dd 3682 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19 3683
c2798b19
CW		 3684 I915_WRITE16(EMR,
3685 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3686
3687 /* Unmask the interrupts that we always want on. */
3688 dev_priv->irq_mask =
3689 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3690 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3691 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 3692 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
c2798b19
CW		 3693 I915_WRITE16(IMR, dev_priv->irq_mask);
3694
3695 I915_WRITE16(IER,
3696 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3697 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
c2798b19
CW		 3698 I915_USER_INTERRUPT);
3699 POSTING_READ16(IER);
3700
379ef82d
DV		 3701 /* Interrupt setup is already guaranteed to be single-threaded, this is
3702 * just to make the assert_spin_locked check happy. */
d6207435 3703 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3704 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3705 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3706 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3707
c2798b19
CW		 3708 return 0;
3709}
3710
90a72f87
VS		 3711/*
3712 * Returns true when a page flip has completed.
3713 */
3714static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3715 int plane, int pipe, u32 iir)
90a72f87 3716{
2d1013dd 3717 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3718 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 3719
8d7849db 3720 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3721 return false;
3722
3723 if ((iir & flip_pending) == 0)
d6bbafa1 3724 goto check_page_flip;
90a72f87 3725
90a72f87
VS		 3726 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3727 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3728 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3729 * the flip is completed (no longer pending). Since this doesn't raise
3730 * an interrupt per se, we watch for the change at vblank.
3731 */
3732 if (I915_READ16(ISR) & flip_pending)
d6bbafa1 3733 goto check_page_flip;
90a72f87 3734
7d47559e 3735 intel_prepare_page_flip(dev, plane);
90a72f87 3736 intel_finish_page_flip(dev, pipe);
90a72f87 3737 return true;
d6bbafa1
CW		 3738
3739check_page_flip:
3740 intel_check_page_flip(dev, pipe);
3741 return false;
90a72f87
VS		 3742}
3743
ff1f525e 3744static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 3745{
45a83f84 3746 struct drm_device *dev = arg;
2d1013dd 3747 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3748 u16 iir, new_iir;
3749 u32 pipe_stats[2];
c2798b19
CW		 3750 int pipe;
3751 u16 flip_mask =
3752 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3753 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3754
2dd2a883
ID		 3755 if (!intel_irqs_enabled(dev_priv))
3756 return IRQ_NONE;
3757
c2798b19
CW		 3758 iir = I915_READ16(IIR);
3759 if (iir == 0)
3760 return IRQ_NONE;
3761
3762 while (iir & ~flip_mask) {
3763 /* Can't rely on pipestat interrupt bit in iir as it might
3764 * have been cleared after the pipestat interrupt was received.
3765 * It doesn't set the bit in iir again, but it still produces
3766 * interrupts (for non-MSI).
3767 */
222c7f51 3768 spin_lock(&dev_priv->irq_lock);
c2798b19 3769 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3770 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
c2798b19 3771
055e393f 3772 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3773 int reg = PIPESTAT(pipe);
3774 pipe_stats[pipe] = I915_READ(reg);
3775
3776 /*
3777 * Clear the PIPE*STAT regs before the IIR
3778 */
2d9d2b0b 3779 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3780 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19 3781 }
222c7f51 3782 spin_unlock(&dev_priv->irq_lock);
c2798b19
CW		 3783
3784 I915_WRITE16(IIR, iir & ~flip_mask);
3785 new_iir = I915_READ16(IIR); /* Flush posted writes */
3786
c2798b19 3787 if (iir & I915_USER_INTERRUPT)
74cdb337 3788 notify_ring(&dev_priv->ring[RCS]);
c2798b19 3789
055e393f 3790 for_each_pipe(dev_priv, pipe) {
1f1c2e24 3791 int plane = pipe;
3a77c4c4 3792 if (HAS_FBC(dev))
1f1c2e24
VS		 3793 plane = !plane;
3794
4356d586 3795 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3796 i8xx_handle_vblank(dev, plane, pipe, iir))
3797 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3798
4356d586 3799 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3800 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3801
1f7247c0
DV		 3802 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3803 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3804 pipe);
4356d586 3805 }
c2798b19
CW		 3806
3807 iir = new_iir;
3808 }
3809
3810 return IRQ_HANDLED;
3811}
3812
3813static void i8xx_irq_uninstall(struct drm_device * dev)
3814{
2d1013dd 3815 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3816 int pipe;
3817
055e393f 3818 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 3819 /* Clear enable bits; then clear status bits */
3820 I915_WRITE(PIPESTAT(pipe), 0);
3821 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3822 }
3823 I915_WRITE16(IMR, 0xffff);
3824 I915_WRITE16(IER, 0x0);
3825 I915_WRITE16(IIR, I915_READ16(IIR));
3826}
3827
a266c7d5
CW		 3828static void i915_irq_preinstall(struct drm_device * dev)
3829{
2d1013dd 3830 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3831 int pipe;
3832
a266c7d5
CW		 3833 if (I915_HAS_HOTPLUG(dev)) {
3834 I915_WRITE(PORT_HOTPLUG_EN, 0);
3835 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3836 }
3837
00d98ebd 3838 I915_WRITE16(HWSTAM, 0xeffe);
055e393f 3839 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 3840 I915_WRITE(PIPESTAT(pipe), 0);
3841 I915_WRITE(IMR, 0xffffffff);
3842 I915_WRITE(IER, 0x0);
3843 POSTING_READ(IER);
3844}
3845
3846static int i915_irq_postinstall(struct drm_device *dev)
3847{
2d1013dd 3848 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3849 u32 enable_mask;
a266c7d5 3850
38bde180
CW		 3851 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3852
3853 /* Unmask the interrupts that we always want on. */
3854 dev_priv->irq_mask =
3855 ~(I915_ASLE_INTERRUPT |
3856 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3857 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3858 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 3859 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
38bde180
CW		 3860
3861 enable_mask =
3862 I915_ASLE_INTERRUPT |
3863 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3864 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
38bde180
CW		 3865 I915_USER_INTERRUPT;
3866
a266c7d5 3867 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3868 I915_WRITE(PORT_HOTPLUG_EN, 0);
3869 POSTING_READ(PORT_HOTPLUG_EN);
3870
a266c7d5
CW		 3871 /* Enable in IER... */
3872 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3873 /* and unmask in IMR */
3874 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3875 }
3876
a266c7d5
CW		 3877 I915_WRITE(IMR, dev_priv->irq_mask);
3878 I915_WRITE(IER, enable_mask);
3879 POSTING_READ(IER);
3880
f49e38dd 3881 i915_enable_asle_pipestat(dev);
20afbda2 3882
379ef82d
DV		 3883 /* Interrupt setup is already guaranteed to be single-threaded, this is
3884 * just to make the assert_spin_locked check happy. */
d6207435 3885 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3886 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3887 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3888 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3889
20afbda2
DV		 3890 return 0;
3891}
3892
90a72f87
VS		 3893/*
3894 * Returns true when a page flip has completed.
3895 */
3896static bool i915_handle_vblank(struct drm_device *dev,
3897 int plane, int pipe, u32 iir)
3898{
2d1013dd 3899 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3900 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3901
8d7849db 3902 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3903 return false;
3904
3905 if ((iir & flip_pending) == 0)
d6bbafa1 3906 goto check_page_flip;
90a72f87 3907
90a72f87
VS		 3908 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3909 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3910 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3911 * the flip is completed (no longer pending). Since this doesn't raise
3912 * an interrupt per se, we watch for the change at vblank.
3913 */
3914 if (I915_READ(ISR) & flip_pending)
d6bbafa1 3915 goto check_page_flip;
90a72f87 3916
7d47559e 3917 intel_prepare_page_flip(dev, plane);
90a72f87 3918 intel_finish_page_flip(dev, pipe);
90a72f87 3919 return true;
d6bbafa1
CW		 3920
3921check_page_flip:
3922 intel_check_page_flip(dev, pipe);
3923 return false;
90a72f87
VS		 3924}
3925
ff1f525e 3926static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 3927{
45a83f84 3928 struct drm_device *dev = arg;
2d1013dd 3929 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3930 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
38bde180
CW		 3931 u32 flip_mask =
3932 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3933 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3934 int pipe, ret = IRQ_NONE;
a266c7d5 3935
2dd2a883
ID		 3936 if (!intel_irqs_enabled(dev_priv))
3937 return IRQ_NONE;
3938
a266c7d5 3939 iir = I915_READ(IIR);
38bde180
CW		 3940 do {
3941 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3942 bool blc_event = false;
a266c7d5
CW		 3943
3944 /* Can't rely on pipestat interrupt bit in iir as it might
3945 * have been cleared after the pipestat interrupt was received.
3946 * It doesn't set the bit in iir again, but it still produces
3947 * interrupts (for non-MSI).
3948 */
222c7f51 3949 spin_lock(&dev_priv->irq_lock);
a266c7d5 3950 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 3951 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 3952
055e393f 3953 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 3954 int reg = PIPESTAT(pipe);
3955 pipe_stats[pipe] = I915_READ(reg);
3956
38bde180 3957 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3958 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3959 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3960 irq_received = true;
a266c7d5
CW		 3961 }
3962 }
222c7f51 3963 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 3964
3965 if (!irq_received)
3966 break;
3967
a266c7d5 3968 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3969 if (I915_HAS_HOTPLUG(dev) &&
3970 iir & I915_DISPLAY_PORT_INTERRUPT)
3971 i9xx_hpd_irq_handler(dev);
a266c7d5 3972
38bde180 3973 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3974 new_iir = I915_READ(IIR); /* Flush posted writes */
3975
a266c7d5 3976 if (iir & I915_USER_INTERRUPT)
74cdb337 3977 notify_ring(&dev_priv->ring[RCS]);
a266c7d5 3978
055e393f 3979 for_each_pipe(dev_priv, pipe) {
38bde180 3980 int plane = pipe;
3a77c4c4 3981 if (HAS_FBC(dev))
38bde180 3982 plane = !plane;
90a72f87 3983
8291ee90 3984 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3985 i915_handle_vblank(dev, plane, pipe, iir))
3986 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3987
3988 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3989 blc_event = true;
4356d586
DV		 3990
3991 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3992 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 3993
1f7247c0
DV		 3994 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3995 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3996 pipe);
a266c7d5
CW		 3997 }
3998
a266c7d5
CW		 3999 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4000 intel_opregion_asle_intr(dev);
4001
4002 /* With MSI, interrupts are only generated when iir
4003 * transitions from zero to nonzero. If another bit got
4004 * set while we were handling the existing iir bits, then
4005 * we would never get another interrupt.
4006 *
4007 * This is fine on non-MSI as well, as if we hit this path
4008 * we avoid exiting the interrupt handler only to generate
4009 * another one.
4010 *
4011 * Note that for MSI this could cause a stray interrupt report
4012 * if an interrupt landed in the time between writing IIR and
4013 * the posting read. This should be rare enough to never
4014 * trigger the 99% of 100,000 interrupts test for disabling
4015 * stray interrupts.
4016 */
38bde180 4017 ret = IRQ_HANDLED;
a266c7d5 4018 iir = new_iir;
38bde180 4019 } while (iir & ~flip_mask);
a266c7d5
CW		 4020
4021 return ret;
4022}
4023
4024static void i915_irq_uninstall(struct drm_device * dev)
4025{
2d1013dd 4026 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4027 int pipe;
4028
a266c7d5
CW		 4029 if (I915_HAS_HOTPLUG(dev)) {
4030 I915_WRITE(PORT_HOTPLUG_EN, 0);
4031 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4032 }
4033
00d98ebd 4034 I915_WRITE16(HWSTAM, 0xffff);
055e393f 4035 for_each_pipe(dev_priv, pipe) {
55b39755 4036 /* Clear enable bits; then clear status bits */
a266c7d5 4037 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 4038 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4039 }
a266c7d5
CW		 4040 I915_WRITE(IMR, 0xffffffff);
4041 I915_WRITE(IER, 0x0);
4042
a266c7d5
CW		 4043 I915_WRITE(IIR, I915_READ(IIR));
4044}
4045
4046static void i965_irq_preinstall(struct drm_device * dev)
4047{
2d1013dd 4048 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4049 int pipe;
4050
adca4730
CW		 4051 I915_WRITE(PORT_HOTPLUG_EN, 0);
4052 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4053
4054 I915_WRITE(HWSTAM, 0xeffe);
055e393f 4055 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4056 I915_WRITE(PIPESTAT(pipe), 0);
4057 I915_WRITE(IMR, 0xffffffff);
4058 I915_WRITE(IER, 0x0);
4059 POSTING_READ(IER);
4060}
4061
4062static int i965_irq_postinstall(struct drm_device *dev)
4063{
2d1013dd 4064 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 4065 u32 enable_mask;
a266c7d5
CW		 4066 u32 error_mask;
4067
a266c7d5 4068 /* Unmask the interrupts that we always want on. */
bbba0a97 4069 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 4070 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 4071 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4072 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4073 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4074 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4075 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4076
4077 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 4078 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4079 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 4080 enable_mask |= I915_USER_INTERRUPT;
4081
4082 if (IS_G4X(dev))
4083 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 4084
b79480ba
DV		 4085 /* Interrupt setup is already guaranteed to be single-threaded, this is
4086 * just to make the assert_spin_locked check happy. */
d6207435 4087 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 4088 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4089 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4090 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 4091 spin_unlock_irq(&dev_priv->irq_lock);
a266c7d5 4092
a266c7d5
CW		 4093 /*
4094 * Enable some error detection, note the instruction error mask
4095 * bit is reserved, so we leave it masked.
4096 */
4097 if (IS_G4X(dev)) {
4098 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4099 GM45_ERROR_MEM_PRIV |
4100 GM45_ERROR_CP_PRIV |
4101 I915_ERROR_MEMORY_REFRESH);
4102 } else {
4103 error_mask = ~(I915_ERROR_PAGE_TABLE |
4104 I915_ERROR_MEMORY_REFRESH);
4105 }
4106 I915_WRITE(EMR, error_mask);
4107
4108 I915_WRITE(IMR, dev_priv->irq_mask);
4109 I915_WRITE(IER, enable_mask);
4110 POSTING_READ(IER);
4111
20afbda2
DV		 4112 I915_WRITE(PORT_HOTPLUG_EN, 0);
4113 POSTING_READ(PORT_HOTPLUG_EN);
4114
f49e38dd 4115 i915_enable_asle_pipestat(dev);
20afbda2
DV		 4116
4117 return 0;
4118}
4119
bac56d5b 4120static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 4121{
2d1013dd 4122 struct drm_i915_private *dev_priv = dev->dev_private;
cd569aed 4123 struct intel_encoder *intel_encoder;
20afbda2
DV		 4124 u32 hotplug_en;
4125
b5ea2d56
DV		 4126 assert_spin_locked(&dev_priv->irq_lock);
4127
778eb334
VS		 4128 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4129 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4130 /* Note HDMI and DP share hotplug bits */
4131 /* enable bits are the same for all generations */
4132 for_each_intel_encoder(dev, intel_encoder)
4133 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4134 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4135 /* Programming the CRT detection parameters tends
4136 to generate a spurious hotplug event about three
4137 seconds later. So just do it once.
4138 */
4139 if (IS_G4X(dev))
4140 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4141 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4142 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4143
4144 /* Ignore TV since it's buggy */
4145 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 4146}
4147
ff1f525e 4148static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 4149{
45a83f84 4150 struct drm_device *dev = arg;
2d1013dd 4151 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4152 u32 iir, new_iir;
4153 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 4154 int ret = IRQ_NONE, pipe;
21ad8330
VS		 4155 u32 flip_mask =
4156 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4157 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 4158
2dd2a883
ID		 4159 if (!intel_irqs_enabled(dev_priv))
4160 return IRQ_NONE;
4161
a266c7d5
CW		 4162 iir = I915_READ(IIR);
4163
a266c7d5 4164 for (;;) {
501e01d7 4165 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 4166 bool blc_event = false;
4167
a266c7d5
CW		 4168 /* Can't rely on pipestat interrupt bit in iir as it might
4169 * have been cleared after the pipestat interrupt was received.
4170 * It doesn't set the bit in iir again, but it still produces
4171 * interrupts (for non-MSI).
4172 */
222c7f51 4173 spin_lock(&dev_priv->irq_lock);
a266c7d5 4174 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4175 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 4176
055e393f 4177 for_each_pipe(dev_priv, pipe) {
a266c7d5
CW		 4178 int reg = PIPESTAT(pipe);
4179 pipe_stats[pipe] = I915_READ(reg);
4180
4181 /*
4182 * Clear the PIPE*STAT regs before the IIR
4183 */
4184 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4185 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 4186 irq_received = true;
a266c7d5
CW		 4187 }
4188 }
222c7f51 4189 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 4190
4191 if (!irq_received)
4192 break;
4193
4194 ret = IRQ_HANDLED;
4195
4196 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4197 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4198 i9xx_hpd_irq_handler(dev);
a266c7d5 4199
21ad8330 4200 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4201 new_iir = I915_READ(IIR); /* Flush posted writes */
4202
a266c7d5 4203 if (iir & I915_USER_INTERRUPT)
74cdb337 4204 notify_ring(&dev_priv->ring[RCS]);
a266c7d5 4205 if (iir & I915_BSD_USER_INTERRUPT)
74cdb337 4206 notify_ring(&dev_priv->ring[VCS]);
a266c7d5 4207
055e393f 4208 for_each_pipe(dev_priv, pipe) {
2c8ba29f 4209 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4210 i915_handle_vblank(dev, pipe, pipe, iir))
4211 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 4212
4213 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4214 blc_event = true;
4356d586
DV		 4215
4216 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4217 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 4218
1f7247c0
DV		 4219 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4220 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2d9d2b0b 4221 }
a266c7d5
CW		 4222
4223 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4224 intel_opregion_asle_intr(dev);
4225
515ac2bb
DV		 4226 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4227 gmbus_irq_handler(dev);
4228
a266c7d5
CW		 4229 /* With MSI, interrupts are only generated when iir
4230 * transitions from zero to nonzero. If another bit got
4231 * set while we were handling the existing iir bits, then
4232 * we would never get another interrupt.
4233 *
4234 * This is fine on non-MSI as well, as if we hit this path
4235 * we avoid exiting the interrupt handler only to generate
4236 * another one.
4237 *
4238 * Note that for MSI this could cause a stray interrupt report
4239 * if an interrupt landed in the time between writing IIR and
4240 * the posting read. This should be rare enough to never
4241 * trigger the 99% of 100,000 interrupts test for disabling
4242 * stray interrupts.
4243 */
4244 iir = new_iir;
4245 }
4246
4247 return ret;
4248}
4249
4250static void i965_irq_uninstall(struct drm_device * dev)
4251{
2d1013dd 4252 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4253 int pipe;
4254
4255 if (!dev_priv)
4256 return;
4257
adca4730
CW		 4258 I915_WRITE(PORT_HOTPLUG_EN, 0);
4259 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4260
4261 I915_WRITE(HWSTAM, 0xffffffff);
055e393f 4262 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4263 I915_WRITE(PIPESTAT(pipe), 0);
4264 I915_WRITE(IMR, 0xffffffff);
4265 I915_WRITE(IER, 0x0);
4266
055e393f 4267 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4268 I915_WRITE(PIPESTAT(pipe),
4269 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4270 I915_WRITE(IIR, I915_READ(IIR));
4271}
4272
4cb21832 4273static void intel_hpd_irq_reenable_work(struct work_struct *work)
ac4c16c5 4274{
6323751d
ID		 4275 struct drm_i915_private *dev_priv =
4276 container_of(work, typeof(*dev_priv),
4277 hotplug_reenable_work.work);
ac4c16c5
EE		 4278 struct drm_device *dev = dev_priv->dev;
4279 struct drm_mode_config *mode_config = &dev->mode_config;
ac4c16c5
EE		 4280 int i;
4281
6323751d
ID		 4282 intel_runtime_pm_get(dev_priv);
4283
4cb21832 4284 spin_lock_irq(&dev_priv->irq_lock);
ac4c16c5
EE		 4285 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4286 struct drm_connector *connector;
4287
4288 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4289 continue;
4290
4291 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4292
4293 list_for_each_entry(connector, &mode_config->connector_list, head) {
4294 struct intel_connector *intel_connector = to_intel_connector(connector);
4295
4296 if (intel_connector->encoder->hpd_pin == i) {
4297 if (connector->polled != intel_connector->polled)
4298 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
c23cc417 4299 connector->name);
ac4c16c5
EE		 4300 connector->polled = intel_connector->polled;
4301 if (!connector->polled)
4302 connector->polled = DRM_CONNECTOR_POLL_HPD;
4303 }
4304 }
4305 }
4306 if (dev_priv->display.hpd_irq_setup)
4307 dev_priv->display.hpd_irq_setup(dev);
4cb21832 4308 spin_unlock_irq(&dev_priv->irq_lock);
6323751d
ID		 4309
4310 intel_runtime_pm_put(dev_priv);
ac4c16c5
EE		 4311}
4312
fca52a55
DV		 4313/**
4314 * intel_irq_init - initializes irq support
4315 * @dev_priv: i915 device instance
4316 *
4317 * This function initializes all the irq support including work items, timers
4318 * and all the vtables. It does not setup the interrupt itself though.
4319 */
b963291c 4320void intel_irq_init(struct drm_i915_private *dev_priv)
f71d4af4 4321{
b963291c 4322 struct drm_device *dev = dev_priv->dev;
8b2e326d
CW		 4323
4324 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
13cf5504 4325 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
c6a828d3 4326 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4327 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4328
a6706b45 4329 /* Let's track the enabled rps events */
b963291c 4330 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6c65a587 4331 /* WaGsvRC0ResidencyMethod:vlv */
6f4b12f8 4332 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
31685c25
D		 4333 else
4334 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4335
737b1506
CW		 4336 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4337 i915_hangcheck_elapsed);
6323751d 4338 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4cb21832 4339 intel_hpd_irq_reenable_work);
61bac78e 4340
97a19a24 4341 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4342
b963291c 4343 if (IS_GEN2(dev_priv)) {
4cdb83ec
VS		 4344 dev->max_vblank_count = 0;
4345 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
b963291c 4346 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
f71d4af4
JB		 4347 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4348 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4349 } else {
4350 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4351 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4352 }
4353
21da2700
VS		 4354 /*
4355 * Opt out of the vblank disable timer on everything except gen2.
4356 * Gen2 doesn't have a hardware frame counter and so depends on
4357 * vblank interrupts to produce sane vblank seuquence numbers.
4358 */
b963291c 4359 if (!IS_GEN2(dev_priv))
21da2700
VS		 4360 dev->vblank_disable_immediate = true;
4361
f3a5c3f6
DV		 4362 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4363 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
f71d4af4 4364
b963291c 4365 if (IS_CHERRYVIEW(dev_priv)) {
43f328d7
VS		 4366 dev->driver->irq_handler = cherryview_irq_handler;
4367 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4368 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4369 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4370 dev->driver->enable_vblank = valleyview_enable_vblank;
4371 dev->driver->disable_vblank = valleyview_disable_vblank;
4372 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4373 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 4374 dev->driver->irq_handler = valleyview_irq_handler;
4375 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4376 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4377 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4378 dev->driver->enable_vblank = valleyview_enable_vblank;
4379 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4380 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4381 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
abd58f01 4382 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4383 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4384 dev->driver->irq_postinstall = gen8_irq_postinstall;
4385 dev->driver->irq_uninstall = gen8_irq_uninstall;
4386 dev->driver->enable_vblank = gen8_enable_vblank;
4387 dev->driver->disable_vblank = gen8_disable_vblank;
e0a20ad7
SS		 4388 if (HAS_PCH_SPLIT(dev))
4389 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4390 else
4391 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
f71d4af4
JB		 4392 } else if (HAS_PCH_SPLIT(dev)) {
4393 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4394 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4395 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4396 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4397 dev->driver->enable_vblank = ironlake_enable_vblank;
4398 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4399 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4400 } else {
b963291c 4401 if (INTEL_INFO(dev_priv)->gen == 2) {
c2798b19
CW		 4402 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4403 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4404 dev->driver->irq_handler = i8xx_irq_handler;
4405 dev->driver->irq_uninstall = i8xx_irq_uninstall;
b963291c 4406 } else if (INTEL_INFO(dev_priv)->gen == 3) {
a266c7d5
CW		 4407 dev->driver->irq_preinstall = i915_irq_preinstall;
4408 dev->driver->irq_postinstall = i915_irq_postinstall;
4409 dev->driver->irq_uninstall = i915_irq_uninstall;
4410 dev->driver->irq_handler = i915_irq_handler;
c2798b19 4411 } else {
a266c7d5
CW		 4412 dev->driver->irq_preinstall = i965_irq_preinstall;
4413 dev->driver->irq_postinstall = i965_irq_postinstall;
4414 dev->driver->irq_uninstall = i965_irq_uninstall;
4415 dev->driver->irq_handler = i965_irq_handler;
c2798b19 4416 }
778eb334
VS		 4417 if (I915_HAS_HOTPLUG(dev_priv))
4418 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 4419 dev->driver->enable_vblank = i915_enable_vblank;
4420 dev->driver->disable_vblank = i915_disable_vblank;
4421 }
4422}
20afbda2 4423
fca52a55
DV		 4424/**
4425 * intel_hpd_init - initializes and enables hpd support
4426 * @dev_priv: i915 device instance
4427 *
4428 * This function enables the hotplug support. It requires that interrupts have
4429 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4430 * poll request can run concurrently to other code, so locking rules must be
4431 * obeyed.
4432 *
4433 * This is a separate step from interrupt enabling to simplify the locking rules
4434 * in the driver load and resume code.
4435 */
b963291c 4436void intel_hpd_init(struct drm_i915_private *dev_priv)
20afbda2 4437{
b963291c 4438 struct drm_device *dev = dev_priv->dev;
821450c6
EE		 4439 struct drm_mode_config *mode_config = &dev->mode_config;
4440 struct drm_connector *connector;
4441 int i;
20afbda2 4442
821450c6
EE		 4443 for (i = 1; i < HPD_NUM_PINS; i++) {
4444 dev_priv->hpd_stats[i].hpd_cnt = 0;
4445 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4446 }
4447 list_for_each_entry(connector, &mode_config->connector_list, head) {
4448 struct intel_connector *intel_connector = to_intel_connector(connector);
4449 connector->polled = intel_connector->polled;
0e32b39c
DA		 4450 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4451 connector->polled = DRM_CONNECTOR_POLL_HPD;
4452 if (intel_connector->mst_port)
821450c6
EE		 4453 connector->polled = DRM_CONNECTOR_POLL_HPD;
4454 }
b5ea2d56
DV		 4455
4456 /* Interrupt setup is already guaranteed to be single-threaded, this is
4457 * just to make the assert_spin_locked checks happy. */
d6207435 4458 spin_lock_irq(&dev_priv->irq_lock);
20afbda2
DV		 4459 if (dev_priv->display.hpd_irq_setup)
4460 dev_priv->display.hpd_irq_setup(dev);
d6207435 4461 spin_unlock_irq(&dev_priv->irq_lock);
20afbda2 4462}
c67a470b 4463
fca52a55
DV		 4464/**
4465 * intel_irq_install - enables the hardware interrupt
4466 * @dev_priv: i915 device instance
4467 *
4468 * This function enables the hardware interrupt handling, but leaves the hotplug
4469 * handling still disabled. It is called after intel_irq_init().
4470 *
4471 * In the driver load and resume code we need working interrupts in a few places
4472 * but don't want to deal with the hassle of concurrent probe and hotplug
4473 * workers. Hence the split into this two-stage approach.
4474 */
2aeb7d3a
DV		 4475int intel_irq_install(struct drm_i915_private *dev_priv)
4476{
4477 /*
4478 * We enable some interrupt sources in our postinstall hooks, so mark
4479 * interrupts as enabled _before_ actually enabling them to avoid
4480 * special cases in our ordering checks.
4481 */
4482 dev_priv->pm.irqs_enabled = true;
4483
4484 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4485}
4486
fca52a55
DV		 4487/**
4488 * intel_irq_uninstall - finilizes all irq handling
4489 * @dev_priv: i915 device instance
4490 *
4491 * This stops interrupt and hotplug handling and unregisters and frees all
4492 * resources acquired in the init functions.
4493 */
2aeb7d3a
DV		 4494void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4495{
4496 drm_irq_uninstall(dev_priv->dev);
4497 intel_hpd_cancel_work(dev_priv);
4498 dev_priv->pm.irqs_enabled = false;
4499}
4500
fca52a55
DV		 4501/**
4502 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4503 * @dev_priv: i915 device instance
4504 *
4505 * This function is used to disable interrupts at runtime, both in the runtime
4506 * pm and the system suspend/resume code.
4507 */
b963291c 4508void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4509{
b963291c 4510 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
2aeb7d3a 4511 dev_priv->pm.irqs_enabled = false;
2dd2a883 4512 synchronize_irq(dev_priv->dev->irq);
c67a470b
PZ		 4513}
4514
fca52a55
DV		 4515/**
4516 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4517 * @dev_priv: i915 device instance
4518 *
4519 * This function is used to enable interrupts at runtime, both in the runtime
4520 * pm and the system suspend/resume code.
4521 */
b963291c 4522void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4523{
2aeb7d3a 4524 dev_priv->pm.irqs_enabled = true;
b963291c
DV		 4525 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4526 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
c67a470b 4527}
Linux kernel - Deliverables
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