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drm/i915: move functions around
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
9270388e
DV		 299/* defined intel_pm.c */
300extern spinlock_t mchdev_lock;
301
73edd18f 302static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 303{
304 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 305 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 306 u8 new_delay;
307 unsigned long flags;
308
309 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 310
73edd18f
DV		 311 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
312
9270388e
DV		 313 new_delay = dev_priv->cur_delay;
314
7648fa99 315 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 316 busy_up = I915_READ(RCPREVBSYTUPAVG);
317 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 318 max_avg = I915_READ(RCBMAXAVG);
319 min_avg = I915_READ(RCBMINAVG);
320
321 /* Handle RCS change request from hw */
b5b72e89 322 if (busy_up > max_avg) {
f97108d1
JB		 323 if (dev_priv->cur_delay != dev_priv->max_delay)
324 new_delay = dev_priv->cur_delay - 1;
325 if (new_delay < dev_priv->max_delay)
326 new_delay = dev_priv->max_delay;
b5b72e89 327 } else if (busy_down < min_avg) {
f97108d1
JB		 328 if (dev_priv->cur_delay != dev_priv->min_delay)
329 new_delay = dev_priv->cur_delay + 1;
330 if (new_delay > dev_priv->min_delay)
331 new_delay = dev_priv->min_delay;
332 }
333
7648fa99
JB		 334 if (ironlake_set_drps(dev, new_delay))
335 dev_priv->cur_delay = new_delay;
f97108d1 336
9270388e
DV		 337 spin_unlock_irqrestore(&mchdev_lock, flags);
338
f97108d1
JB		 339 return;
340}
341
549f7365
CW		 342static void notify_ring(struct drm_device *dev,
343 struct intel_ring_buffer *ring)
344{
345 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 346
475553de
CW		 347 if (ring->obj == NULL)
348 return;
349
b2eadbc8 350 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 351
549f7365 352 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 353 if (i915_enable_hangcheck) {
354 dev_priv->hangcheck_count = 0;
355 mod_timer(&dev_priv->hangcheck_timer,
356 jiffies +
357 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
358 }
549f7365
CW		 359}
360
4912d041 361static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 362{
4912d041 363 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 364 rps.work);
4912d041 365 u32 pm_iir, pm_imr;
7b9e0ae6 366 u8 new_delay;
4912d041 367
c6a828d3
DV		 368 spin_lock_irq(&dev_priv->rps.lock);
369 pm_iir = dev_priv->rps.pm_iir;
370 dev_priv->rps.pm_iir = 0;
4912d041 371 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 372 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 373 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 374
7b9e0ae6 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 376 return;
377
4912d041 378 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 379
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 381 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 382 else
c6a828d3 383 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 384
4912d041 385 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 386
4912d041 387 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 388}
389
e3689190
BW		 390
391/**
392 * ivybridge_parity_work - Workqueue called when a parity error interrupt
393 * occurred.
394 * @work: workqueue struct
395 *
396 * Doesn't actually do anything except notify userspace. As a consequence of
397 * this event, userspace should try to remap the bad rows since statistically
398 * it is likely the same row is more likely to go bad again.
399 */
400static void ivybridge_parity_work(struct work_struct *work)
401{
402 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
403 parity_error_work);
404 u32 error_status, row, bank, subbank;
405 char *parity_event[5];
406 uint32_t misccpctl;
407 unsigned long flags;
408
409 /* We must turn off DOP level clock gating to access the L3 registers.
410 * In order to prevent a get/put style interface, acquire struct mutex
411 * any time we access those registers.
412 */
413 mutex_lock(&dev_priv->dev->struct_mutex);
414
415 misccpctl = I915_READ(GEN7_MISCCPCTL);
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
417 POSTING_READ(GEN7_MISCCPCTL);
418
419 error_status = I915_READ(GEN7_L3CDERRST1);
420 row = GEN7_PARITY_ERROR_ROW(error_status);
421 bank = GEN7_PARITY_ERROR_BANK(error_status);
422 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
423
424 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
425 GEN7_L3CDERRST1_ENABLE);
426 POSTING_READ(GEN7_L3CDERRST1);
427
428 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
429
430 spin_lock_irqsave(&dev_priv->irq_lock, flags);
431 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
432 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
433 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
434
435 mutex_unlock(&dev_priv->dev->struct_mutex);
436
437 parity_event[0] = "L3_PARITY_ERROR=1";
438 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
439 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
440 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
441 parity_event[4] = NULL;
442
443 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
444 KOBJ_CHANGE, parity_event);
445
446 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
447 row, bank, subbank);
448
449 kfree(parity_event[3]);
450 kfree(parity_event[2]);
451 kfree(parity_event[1]);
452}
453
d2ba8470 454static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 455{
456 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
457 unsigned long flags;
458
e1ef7cc2 459 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 460 return;
461
462 spin_lock_irqsave(&dev_priv->irq_lock, flags);
463 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
464 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
465 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
466
467 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
468}
469
e7b4c6b1
DV		 470static void snb_gt_irq_handler(struct drm_device *dev,
471 struct drm_i915_private *dev_priv,
472 u32 gt_iir)
473{
474
475 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
476 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
477 notify_ring(dev, &dev_priv->ring[RCS]);
478 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
479 notify_ring(dev, &dev_priv->ring[VCS]);
480 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
481 notify_ring(dev, &dev_priv->ring[BCS]);
482
483 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
484 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
485 GT_RENDER_CS_ERROR_INTERRUPT)) {
486 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
487 i915_handle_error(dev, false);
488 }
e3689190
BW		 489
490 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
491 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 492}
493
fc6826d1
CW		 494static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
495 u32 pm_iir)
496{
497 unsigned long flags;
498
499 /*
500 * IIR bits should never already be set because IMR should
501 * prevent an interrupt from being shown in IIR. The warning
502 * displays a case where we've unsafely cleared
c6a828d3 503 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 504 * type is not a problem, it displays a problem in the logic.
505 *
c6a828d3 506 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 507 */
508
c6a828d3 509 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 510 dev_priv->rps.pm_iir |= pm_iir;
511 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 512 POSTING_READ(GEN6_PMIMR);
c6a828d3 513 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 514
c6a828d3 515 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 516}
517
7e231dbe
JB		 518static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
519{
520 struct drm_device *dev = (struct drm_device *) arg;
521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
522 u32 iir, gt_iir, pm_iir;
523 irqreturn_t ret = IRQ_NONE;
524 unsigned long irqflags;
525 int pipe;
526 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 527 bool blc_event;
528
529 atomic_inc(&dev_priv->irq_received);
530
7e231dbe
JB		 531 while (true) {
532 iir = I915_READ(VLV_IIR);
533 gt_iir = I915_READ(GTIIR);
534 pm_iir = I915_READ(GEN6_PMIIR);
535
536 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
537 goto out;
538
539 ret = IRQ_HANDLED;
540
e7b4c6b1 541 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 542
543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
544 for_each_pipe(pipe) {
545 int reg = PIPESTAT(pipe);
546 pipe_stats[pipe] = I915_READ(reg);
547
548 /*
549 * Clear the PIPE*STAT regs before the IIR
550 */
551 if (pipe_stats[pipe] & 0x8000ffff) {
552 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
553 DRM_DEBUG_DRIVER("pipe %c underrun\n",
554 pipe_name(pipe));
555 I915_WRITE(reg, pipe_stats[pipe]);
556 }
557 }
558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
559
31acc7f5
JB		 560 for_each_pipe(pipe) {
561 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
562 drm_handle_vblank(dev, pipe);
563
564 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
565 intel_prepare_page_flip(dev, pipe);
566 intel_finish_page_flip(dev, pipe);
567 }
568 }
569
7e231dbe
JB		 570 /* Consume port. Then clear IIR or we'll miss events */
571 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
572 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
573
574 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
575 hotplug_status);
576 if (hotplug_status & dev_priv->hotplug_supported_mask)
577 queue_work(dev_priv->wq,
578 &dev_priv->hotplug_work);
579
580 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
581 I915_READ(PORT_HOTPLUG_STAT);
582 }
583
7e231dbe
JB		 584 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
585 blc_event = true;
586
fc6826d1
CW		 587 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
588 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 589
590 I915_WRITE(GTIIR, gt_iir);
591 I915_WRITE(GEN6_PMIIR, pm_iir);
592 I915_WRITE(VLV_IIR, iir);
593 }
594
595out:
596 return ret;
597}
598
23e81d69 599static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 600{
601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 602 int pipe;
776ad806 603
776ad806
JB		 604 if (pch_iir & SDE_AUDIO_POWER_MASK)
605 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
606 (pch_iir & SDE_AUDIO_POWER_MASK) >>
607 SDE_AUDIO_POWER_SHIFT);
608
609 if (pch_iir & SDE_GMBUS)
610 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
611
612 if (pch_iir & SDE_AUDIO_HDCP_MASK)
613 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
614
615 if (pch_iir & SDE_AUDIO_TRANS_MASK)
616 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
617
618 if (pch_iir & SDE_POISON)
619 DRM_ERROR("PCH poison interrupt\n");
620
9db4a9c7
JB		 621 if (pch_iir & SDE_FDI_MASK)
622 for_each_pipe(pipe)
623 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
624 pipe_name(pipe),
625 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 626
627 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
629
630 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
631 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
632
633 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
634 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
635 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
636 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
637}
638
23e81d69
AJ		 639static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
640{
641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
642 int pipe;
643
644 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
645 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
646 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
647 SDE_AUDIO_POWER_SHIFT_CPT);
648
649 if (pch_iir & SDE_AUX_MASK_CPT)
650 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
651
652 if (pch_iir & SDE_GMBUS_CPT)
653 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
654
655 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
656 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
657
658 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
659 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
660
661 if (pch_iir & SDE_FDI_MASK_CPT)
662 for_each_pipe(pipe)
663 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
664 pipe_name(pipe),
665 I915_READ(FDI_RX_IIR(pipe)));
666}
667
f71d4af4 668static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 669{
670 struct drm_device *dev = (struct drm_device *) arg;
671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 672 u32 de_iir, gt_iir, de_ier, pm_iir;
673 irqreturn_t ret = IRQ_NONE;
674 int i;
b1f14ad0
JB		 675
676 atomic_inc(&dev_priv->irq_received);
677
678 /* disable master interrupt before clearing iir */
679 de_ier = I915_READ(DEIER);
680 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 681
b1f14ad0 682 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 683 if (gt_iir) {
684 snb_gt_irq_handler(dev, dev_priv, gt_iir);
685 I915_WRITE(GTIIR, gt_iir);
686 ret = IRQ_HANDLED;
b1f14ad0
JB		 687 }
688
0e43406b
CW		 689 de_iir = I915_READ(DEIIR);
690 if (de_iir) {
691 if (de_iir & DE_GSE_IVB)
692 intel_opregion_gse_intr(dev);
693
694 for (i = 0; i < 3; i++) {
695 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
696 intel_prepare_page_flip(dev, i);
697 intel_finish_page_flip_plane(dev, i);
698 }
699 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
700 drm_handle_vblank(dev, i);
701 }
b615b57a 702
0e43406b
CW		 703 /* check event from PCH */
704 if (de_iir & DE_PCH_EVENT_IVB) {
705 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 706
0e43406b
CW		 707 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
708 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69 709 cpt_irq_handler(dev, pch_iir);
b1f14ad0 710
0e43406b
CW		 711 /* clear PCH hotplug event before clear CPU irq */
712 I915_WRITE(SDEIIR, pch_iir);
713 }
b615b57a 714
0e43406b
CW		 715 I915_WRITE(DEIIR, de_iir);
716 ret = IRQ_HANDLED;
b1f14ad0
JB		 717 }
718
0e43406b
CW		 719 pm_iir = I915_READ(GEN6_PMIIR);
720 if (pm_iir) {
721 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
722 gen6_queue_rps_work(dev_priv, pm_iir);
723 I915_WRITE(GEN6_PMIIR, pm_iir);
724 ret = IRQ_HANDLED;
725 }
b1f14ad0 726
b1f14ad0
JB		 727 I915_WRITE(DEIER, de_ier);
728 POSTING_READ(DEIER);
729
730 return ret;
731}
732
e7b4c6b1
DV		 733static void ilk_gt_irq_handler(struct drm_device *dev,
734 struct drm_i915_private *dev_priv,
735 u32 gt_iir)
736{
737 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
738 notify_ring(dev, &dev_priv->ring[RCS]);
739 if (gt_iir & GT_BSD_USER_INTERRUPT)
740 notify_ring(dev, &dev_priv->ring[VCS]);
741}
742
f71d4af4 743static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 744{
4697995b 745 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
747 int ret = IRQ_NONE;
3b8d8d91 748 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 749 u32 hotplug_mask;
881f47b6 750
4697995b
JB		 751 atomic_inc(&dev_priv->irq_received);
752
2d109a84
ZN		 753 /* disable master interrupt before clearing iir */
754 de_ier = I915_READ(DEIER);
755 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 756 POSTING_READ(DEIER);
2d109a84 757
036a4a7d
ZW		 758 de_iir = I915_READ(DEIIR);
759 gt_iir = I915_READ(GTIIR);
c650156a 760 pch_iir = I915_READ(SDEIIR);
3b8d8d91 761 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 762
3b8d8d91
JB		 763 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
764 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 765 goto done;
036a4a7d 766
2d7b8366
YL		 767 if (HAS_PCH_CPT(dev))
768 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
769 else
770 hotplug_mask = SDE_HOTPLUG_MASK;
771
c7c85101 772 ret = IRQ_HANDLED;
036a4a7d 773
e7b4c6b1
DV		 774 if (IS_GEN5(dev))
775 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
776 else
777 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 778
c7c85101 779 if (de_iir & DE_GSE)
3b617967 780 intel_opregion_gse_intr(dev);
c650156a 781
f072d2e7 782 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 783 intel_prepare_page_flip(dev, 0);
2bbda389 784 intel_finish_page_flip_plane(dev, 0);
f072d2e7 785 }
013d5aa2 786
f072d2e7 787 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 788 intel_prepare_page_flip(dev, 1);
2bbda389 789 intel_finish_page_flip_plane(dev, 1);
f072d2e7 790 }
013d5aa2 791
f072d2e7 792 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 793 drm_handle_vblank(dev, 0);
794
f072d2e7 795 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 796 drm_handle_vblank(dev, 1);
797
c7c85101 798 /* check event from PCH */
776ad806
JB		 799 if (de_iir & DE_PCH_EVENT) {
800 if (pch_iir & hotplug_mask)
801 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69
AJ		 802 if (HAS_PCH_CPT(dev))
803 cpt_irq_handler(dev, pch_iir);
804 else
805 ibx_irq_handler(dev, pch_iir);
776ad806 806 }
036a4a7d 807
73edd18f
DV		 808 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
809 ironlake_handle_rps_change(dev);
f97108d1 810
fc6826d1
CW		 811 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
812 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 813
c7c85101
ZN		 814 /* should clear PCH hotplug event before clear CPU irq */
815 I915_WRITE(SDEIIR, pch_iir);
816 I915_WRITE(GTIIR, gt_iir);
817 I915_WRITE(DEIIR, de_iir);
4912d041 818 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 819
820done:
2d109a84 821 I915_WRITE(DEIER, de_ier);
3143a2bf 822 POSTING_READ(DEIER);
2d109a84 823
036a4a7d
ZW		 824 return ret;
825}
826
8a905236
JB		 827/**
828 * i915_error_work_func - do process context error handling work
829 * @work: work struct
830 *
831 * Fire an error uevent so userspace can see that a hang or error
832 * was detected.
833 */
834static void i915_error_work_func(struct work_struct *work)
835{
836 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
837 error_work);
838 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 839 char *error_event[] = { "ERROR=1", NULL };
840 char *reset_event[] = { "RESET=1", NULL };
841 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 842
f316a42c
BG		 843 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
844
ba1234d1 845 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 846 DRM_DEBUG_DRIVER("resetting chip\n");
847 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 848 if (!i915_reset(dev)) {
f803aa55
CW		 849 atomic_set(&dev_priv->mm.wedged, 0);
850 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 851 }
30dbf0c0 852 complete_all(&dev_priv->error_completion);
f316a42c 853 }
8a905236
JB		 854}
855
3bd3c932 856#ifdef CONFIG_DEBUG_FS
9df30794 857static struct drm_i915_error_object *
bcfb2e28 858i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 859 struct drm_i915_gem_object *src)
9df30794
CW		 860{
861 struct drm_i915_error_object *dst;
9df30794 862 int page, page_count;
e56660dd 863 u32 reloc_offset;
9df30794 864
05394f39 865 if (src == NULL || src->pages == NULL)
9df30794
CW		 866 return NULL;
867
05394f39 868 page_count = src->base.size / PAGE_SIZE;
9df30794 869
0206e353 870 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 871 if (dst == NULL)
872 return NULL;
873
05394f39 874 reloc_offset = src->gtt_offset;
9df30794 875 for (page = 0; page < page_count; page++) {
788885ae 876 unsigned long flags;
e56660dd 877 void *d;
788885ae 878
e56660dd 879 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 880 if (d == NULL)
881 goto unwind;
e56660dd 882
788885ae 883 local_irq_save(flags);
74898d7e
DV		 884 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
885 src->has_global_gtt_mapping) {
172975aa
CW		 886 void __iomem *s;
887
888 /* Simply ignore tiling or any overlapping fence.
889 * It's part of the error state, and this hopefully
890 * captures what the GPU read.
891 */
892
893 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
894 reloc_offset);
895 memcpy_fromio(d, s, PAGE_SIZE);
896 io_mapping_unmap_atomic(s);
897 } else {
898 void *s;
899
900 drm_clflush_pages(&src->pages[page], 1);
901
902 s = kmap_atomic(src->pages[page]);
903 memcpy(d, s, PAGE_SIZE);
904 kunmap_atomic(s);
905
906 drm_clflush_pages(&src->pages[page], 1);
907 }
788885ae 908 local_irq_restore(flags);
e56660dd 909
9df30794 910 dst->pages[page] = d;
e56660dd
CW		 911
912 reloc_offset += PAGE_SIZE;
9df30794
CW		 913 }
914 dst->page_count = page_count;
05394f39 915 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 916
917 return dst;
918
919unwind:
920 while (page--)
921 kfree(dst->pages[page]);
922 kfree(dst);
923 return NULL;
924}
925
926static void
927i915_error_object_free(struct drm_i915_error_object *obj)
928{
929 int page;
930
931 if (obj == NULL)
932 return;
933
934 for (page = 0; page < obj->page_count; page++)
935 kfree(obj->pages[page]);
936
937 kfree(obj);
938}
939
742cbee8
DV		 940void
941i915_error_state_free(struct kref *error_ref)
9df30794 942{
742cbee8
DV		 943 struct drm_i915_error_state *error = container_of(error_ref,
944 typeof(*error), ref);
e2f973d5
CW		 945 int i;
946
52d39a21
CW		 947 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
948 i915_error_object_free(error->ring[i].batchbuffer);
949 i915_error_object_free(error->ring[i].ringbuffer);
950 kfree(error->ring[i].requests);
951 }
e2f973d5 952
9df30794 953 kfree(error->active_bo);
6ef3d427 954 kfree(error->overlay);
9df30794
CW		 955 kfree(error);
956}
1b50247a
CW		 957static void capture_bo(struct drm_i915_error_buffer *err,
958 struct drm_i915_gem_object *obj)
959{
960 err->size = obj->base.size;
961 err->name = obj->base.name;
0201f1ec
CW		 962 err->rseqno = obj->last_read_seqno;
963 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 964 err->gtt_offset = obj->gtt_offset;
965 err->read_domains = obj->base.read_domains;
966 err->write_domain = obj->base.write_domain;
967 err->fence_reg = obj->fence_reg;
968 err->pinned = 0;
969 if (obj->pin_count > 0)
970 err->pinned = 1;
971 if (obj->user_pin_count > 0)
972 err->pinned = -1;
973 err->tiling = obj->tiling_mode;
974 err->dirty = obj->dirty;
975 err->purgeable = obj->madv != I915_MADV_WILLNEED;
976 err->ring = obj->ring ? obj->ring->id : -1;
977 err->cache_level = obj->cache_level;
978}
9df30794 979
1b50247a
CW		 980static u32 capture_active_bo(struct drm_i915_error_buffer *err,
981 int count, struct list_head *head)
c724e8a9
CW		 982{
983 struct drm_i915_gem_object *obj;
984 int i = 0;
985
986 list_for_each_entry(obj, head, mm_list) {
1b50247a 987 capture_bo(err++, obj);
c724e8a9
CW		 988 if (++i == count)
989 break;
1b50247a
CW		 990 }
991
992 return i;
993}
994
995static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
996 int count, struct list_head *head)
997{
998 struct drm_i915_gem_object *obj;
999 int i = 0;
1000
1001 list_for_each_entry(obj, head, gtt_list) {
1002 if (obj->pin_count == 0)
1003 continue;
c724e8a9 1004
1b50247a
CW		 1005 capture_bo(err++, obj);
1006 if (++i == count)
1007 break;
c724e8a9
CW		 1008 }
1009
1010 return i;
1011}
1012
748ebc60
CW		 1013static void i915_gem_record_fences(struct drm_device *dev,
1014 struct drm_i915_error_state *error)
1015{
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017 int i;
1018
1019 /* Fences */
1020 switch (INTEL_INFO(dev)->gen) {
775d17b6 1021 case 7:
748ebc60
CW		 1022 case 6:
1023 for (i = 0; i < 16; i++)
1024 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1025 break;
1026 case 5:
1027 case 4:
1028 for (i = 0; i < 16; i++)
1029 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1030 break;
1031 case 3:
1032 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1033 for (i = 0; i < 8; i++)
1034 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1035 case 2:
1036 for (i = 0; i < 8; i++)
1037 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1038 break;
1039
1040 }
1041}
1042
bcfb2e28
CW		 1043static struct drm_i915_error_object *
1044i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1045 struct intel_ring_buffer *ring)
1046{
1047 struct drm_i915_gem_object *obj;
1048 u32 seqno;
1049
1050 if (!ring->get_seqno)
1051 return NULL;
1052
b2eadbc8 1053 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1054 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1055 if (obj->ring != ring)
1056 continue;
1057
0201f1ec 1058 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1059 continue;
1060
1061 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1062 continue;
1063
1064 /* We need to copy these to an anonymous buffer as the simplest
1065 * method to avoid being overwritten by userspace.
1066 */
1067 return i915_error_object_create(dev_priv, obj);
1068 }
1069
1070 return NULL;
1071}
1072
d27b1e0e
DV		 1073static void i915_record_ring_state(struct drm_device *dev,
1074 struct drm_i915_error_state *error,
1075 struct intel_ring_buffer *ring)
1076{
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078
33f3f518 1079 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1080 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1081 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1082 error->semaphore_mboxes[ring->id][0]
1083 = I915_READ(RING_SYNC_0(ring->mmio_base));
1084 error->semaphore_mboxes[ring->id][1]
1085 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1086 }
c1cd90ed 1087
d27b1e0e 1088 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1089 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1090 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1091 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1092 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1093 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1094 if (ring->id == RCS) {
d27b1e0e
DV		 1095 error->instdone1 = I915_READ(INSTDONE1);
1096 error->bbaddr = I915_READ64(BB_ADDR);
1097 }
1098 } else {
9d2f41fa 1099 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1100 error->ipeir[ring->id] = I915_READ(IPEIR);
1101 error->ipehr[ring->id] = I915_READ(IPEHR);
1102 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1103 }
1104
9574b3fe 1105 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1106 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1107 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1108 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1109 error->head[ring->id] = I915_READ_HEAD(ring);
1110 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1111
1112 error->cpu_ring_head[ring->id] = ring->head;
1113 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1114}
1115
52d39a21
CW		 1116static void i915_gem_record_rings(struct drm_device *dev,
1117 struct drm_i915_error_state *error)
1118{
1119 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1120 struct intel_ring_buffer *ring;
52d39a21
CW		 1121 struct drm_i915_gem_request *request;
1122 int i, count;
1123
b4519513 1124 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1125 i915_record_ring_state(dev, error, ring);
1126
1127 error->ring[i].batchbuffer =
1128 i915_error_first_batchbuffer(dev_priv, ring);
1129
1130 error->ring[i].ringbuffer =
1131 i915_error_object_create(dev_priv, ring->obj);
1132
1133 count = 0;
1134 list_for_each_entry(request, &ring->request_list, list)
1135 count++;
1136
1137 error->ring[i].num_requests = count;
1138 error->ring[i].requests =
1139 kmalloc(count*sizeof(struct drm_i915_error_request),
1140 GFP_ATOMIC);
1141 if (error->ring[i].requests == NULL) {
1142 error->ring[i].num_requests = 0;
1143 continue;
1144 }
1145
1146 count = 0;
1147 list_for_each_entry(request, &ring->request_list, list) {
1148 struct drm_i915_error_request *erq;
1149
1150 erq = &error->ring[i].requests[count++];
1151 erq->seqno = request->seqno;
1152 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1153 erq->tail = request->tail;
52d39a21
CW		 1154 }
1155 }
1156}
1157
8a905236
JB		 1158/**
1159 * i915_capture_error_state - capture an error record for later analysis
1160 * @dev: drm device
1161 *
1162 * Should be called when an error is detected (either a hang or an error
1163 * interrupt) to capture error state from the time of the error. Fills
1164 * out a structure which becomes available in debugfs for user level tools
1165 * to pick up.
1166 */
63eeaf38
JB		 1167static void i915_capture_error_state(struct drm_device *dev)
1168{
1169 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1170 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1171 struct drm_i915_error_state *error;
1172 unsigned long flags;
9db4a9c7 1173 int i, pipe;
63eeaf38
JB		 1174
1175 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1176 error = dev_priv->first_error;
1177 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1178 if (error)
1179 return;
63eeaf38 1180
9db4a9c7 1181 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1182 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1183 if (!error) {
9df30794
CW		 1184 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1185 return;
63eeaf38
JB		 1186 }
1187
b6f7833b
CW		 1188 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1189 dev->primary->index);
2fa772f3 1190
742cbee8 1191 kref_init(&error->ref);
63eeaf38
JB		 1192 error->eir = I915_READ(EIR);
1193 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1194 error->ccid = I915_READ(CCID);
be998e2e
BW		 1195
1196 if (HAS_PCH_SPLIT(dev))
1197 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1198 else if (IS_VALLEYVIEW(dev))
1199 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1200 else if (IS_GEN2(dev))
1201 error->ier = I915_READ16(IER);
1202 else
1203 error->ier = I915_READ(IER);
1204
9db4a9c7
JB		 1205 for_each_pipe(pipe)
1206 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1207
33f3f518 1208 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1209 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1210 error->done_reg = I915_READ(DONE_REG);
1211 }
d27b1e0e 1212
748ebc60 1213 i915_gem_record_fences(dev, error);
52d39a21 1214 i915_gem_record_rings(dev, error);
9df30794 1215
c724e8a9 1216 /* Record buffers on the active and pinned lists. */
9df30794 1217 error->active_bo = NULL;
c724e8a9 1218 error->pinned_bo = NULL;
9df30794 1219
bcfb2e28
CW		 1220 i = 0;
1221 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1222 i++;
1223 error->active_bo_count = i;
1b50247a
CW		 1224 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1225 if (obj->pin_count)
1226 i++;
bcfb2e28 1227 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1228
8e934dbf
CW		 1229 error->active_bo = NULL;
1230 error->pinned_bo = NULL;
bcfb2e28
CW		 1231 if (i) {
1232 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1233 GFP_ATOMIC);
c724e8a9
CW		 1234 if (error->active_bo)
1235 error->pinned_bo =
1236 error->active_bo + error->active_bo_count;
9df30794
CW		 1237 }
1238
c724e8a9
CW		 1239 if (error->active_bo)
1240 error->active_bo_count =
1b50247a
CW		 1241 capture_active_bo(error->active_bo,
1242 error->active_bo_count,
1243 &dev_priv->mm.active_list);
c724e8a9
CW		 1244
1245 if (error->pinned_bo)
1246 error->pinned_bo_count =
1b50247a
CW		 1247 capture_pinned_bo(error->pinned_bo,
1248 error->pinned_bo_count,
1249 &dev_priv->mm.gtt_list);
c724e8a9 1250
9df30794
CW		 1251 do_gettimeofday(&error->time);
1252
6ef3d427 1253 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1254 error->display = intel_display_capture_error_state(dev);
6ef3d427 1255
9df30794
CW		 1256 spin_lock_irqsave(&dev_priv->error_lock, flags);
1257 if (dev_priv->first_error == NULL) {
1258 dev_priv->first_error = error;
1259 error = NULL;
1260 }
63eeaf38 1261 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1262
1263 if (error)
742cbee8 1264 i915_error_state_free(&error->ref);
9df30794
CW		 1265}
1266
1267void i915_destroy_error_state(struct drm_device *dev)
1268{
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 struct drm_i915_error_state *error;
6dc0e816 1271 unsigned long flags;
9df30794 1272
6dc0e816 1273 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1274 error = dev_priv->first_error;
1275 dev_priv->first_error = NULL;
6dc0e816 1276 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1277
1278 if (error)
742cbee8 1279 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1280}
3bd3c932
CW		 1281#else
1282#define i915_capture_error_state(x)
1283#endif
63eeaf38 1284
35aed2e6 1285static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1286{
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 u32 eir = I915_READ(EIR);
9db4a9c7 1289 int pipe;
8a905236 1290
35aed2e6
CW		 1291 if (!eir)
1292 return;
8a905236 1293
a70491cc 1294 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1295
1296 if (IS_G4X(dev)) {
1297 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1298 u32 ipeir = I915_READ(IPEIR_I965);
1299
a70491cc
JP		 1300 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1301 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1302 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1303 I915_READ(INSTDONE_I965));
a70491cc
JP		 1304 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1305 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1306 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1307 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1308 POSTING_READ(IPEIR_I965);
8a905236
JB		 1309 }
1310 if (eir & GM45_ERROR_PAGE_TABLE) {
1311 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1312 pr_err("page table error\n");
1313 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1314 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1315 POSTING_READ(PGTBL_ER);
8a905236
JB		 1316 }
1317 }
1318
a6c45cf0 1319 if (!IS_GEN2(dev)) {
8a905236
JB		 1320 if (eir & I915_ERROR_PAGE_TABLE) {
1321 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1322 pr_err("page table error\n");
1323 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1324 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1325 POSTING_READ(PGTBL_ER);
8a905236
JB		 1326 }
1327 }
1328
1329 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1330 pr_err("memory refresh error:\n");
9db4a9c7 1331 for_each_pipe(pipe)
a70491cc 1332 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1333 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1334 /* pipestat has already been acked */
1335 }
1336 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1337 pr_err("instruction error\n");
1338 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1339 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1340 u32 ipeir = I915_READ(IPEIR);
1341
a70491cc
JP		 1342 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1343 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1344 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1345 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1346 I915_WRITE(IPEIR, ipeir);
3143a2bf 1347 POSTING_READ(IPEIR);
8a905236
JB		 1348 } else {
1349 u32 ipeir = I915_READ(IPEIR_I965);
1350
a70491cc
JP		 1351 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1352 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1353 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1354 I915_READ(INSTDONE_I965));
a70491cc
JP		 1355 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1356 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1357 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1358 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1359 POSTING_READ(IPEIR_I965);
8a905236
JB		 1360 }
1361 }
1362
1363 I915_WRITE(EIR, eir);
3143a2bf 1364 POSTING_READ(EIR);
8a905236
JB		 1365 eir = I915_READ(EIR);
1366 if (eir) {
1367 /*
1368 * some errors might have become stuck,
1369 * mask them.
1370 */
1371 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1372 I915_WRITE(EMR, I915_READ(EMR) | eir);
1373 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1374 }
35aed2e6
CW		 1375}
1376
1377/**
1378 * i915_handle_error - handle an error interrupt
1379 * @dev: drm device
1380 *
1381 * Do some basic checking of regsiter state at error interrupt time and
1382 * dump it to the syslog. Also call i915_capture_error_state() to make
1383 * sure we get a record and make it available in debugfs. Fire a uevent
1384 * so userspace knows something bad happened (should trigger collection
1385 * of a ring dump etc.).
1386 */
527f9e90 1387void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1388{
1389 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1390 struct intel_ring_buffer *ring;
1391 int i;
35aed2e6
CW		 1392
1393 i915_capture_error_state(dev);
1394 i915_report_and_clear_eir(dev);
8a905236 1395
ba1234d1 1396 if (wedged) {
30dbf0c0 1397 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1398 atomic_set(&dev_priv->mm.wedged, 1);
1399
11ed50ec
BG		 1400 /*
1401 * Wakeup waiting processes so they don't hang
1402 */
b4519513
CW		 1403 for_each_ring(ring, dev_priv, i)
1404 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1405 }
1406
9c9fe1f8 1407 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1408}
1409
4e5359cd
SF		 1410static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1411{
1412 drm_i915_private_t *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1415 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1416 struct intel_unpin_work *work;
1417 unsigned long flags;
1418 bool stall_detected;
1419
1420 /* Ignore early vblank irqs */
1421 if (intel_crtc == NULL)
1422 return;
1423
1424 spin_lock_irqsave(&dev->event_lock, flags);
1425 work = intel_crtc->unpin_work;
1426
1427 if (work == NULL || work->pending || !work->enable_stall_check) {
1428 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1429 spin_unlock_irqrestore(&dev->event_lock, flags);
1430 return;
1431 }
1432
1433 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1434 obj = work->pending_flip_obj;
a6c45cf0 1435 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1436 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1437 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1438 obj->gtt_offset;
4e5359cd 1439 } else {
9db4a9c7 1440 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1441 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1442 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1443 crtc->x * crtc->fb->bits_per_pixel/8);
1444 }
1445
1446 spin_unlock_irqrestore(&dev->event_lock, flags);
1447
1448 if (stall_detected) {
1449 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1450 intel_prepare_page_flip(dev, intel_crtc->plane);
1451 }
1452}
1453
42f52ef8
KP		 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index
1456 */
f71d4af4 1457static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1460 unsigned long irqflags;
71e0ffa5 1461
5eddb70b 1462 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1463 return -EINVAL;
0a3e67a4 1464
1ec14ad3 1465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1466 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1467 i915_enable_pipestat(dev_priv, pipe,
1468 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1469 else
7c463586
KP		 1470 i915_enable_pipestat(dev_priv, pipe,
1471 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1472
1473 /* maintain vblank delivery even in deep C-states */
1474 if (dev_priv->info->gen == 3)
6b26c86d 1475 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1477
0a3e67a4
JB		 1478 return 0;
1479}
1480
f71d4af4 1481static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags;
1485
1486 if (!i915_pipe_enabled(dev, pipe))
1487 return -EINVAL;
1488
1489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1490 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1491 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1493
1494 return 0;
1495}
1496
f71d4af4 1497static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags;
1501
1502 if (!i915_pipe_enabled(dev, pipe))
1503 return -EINVAL;
1504
1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1506 ironlake_enable_display_irq(dev_priv,
1507 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1509
1510 return 0;
1511}
1512
7e231dbe
JB		 1513static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1514{
1515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1516 unsigned long irqflags;
31acc7f5 1517 u32 imr;
7e231dbe
JB		 1518
1519 if (!i915_pipe_enabled(dev, pipe))
1520 return -EINVAL;
1521
1522 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1523 imr = I915_READ(VLV_IMR);
31acc7f5 1524 if (pipe == 0)
7e231dbe 1525 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1526 else
7e231dbe 1527 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1528 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1529 i915_enable_pipestat(dev_priv, pipe,
1530 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1531 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1532
1533 return 0;
1534}
1535
42f52ef8
KP		 1536/* Called from drm generic code, passed 'crtc' which
1537 * we use as a pipe index
1538 */
f71d4af4 1539static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1540{
1541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1542 unsigned long irqflags;
0a3e67a4 1543
1ec14ad3 1544 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1545 if (dev_priv->info->gen == 3)
6b26c86d 1546 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1547
f796cf8f
JB		 1548 i915_disable_pipestat(dev_priv, pipe,
1549 PIPE_VBLANK_INTERRUPT_ENABLE |
1550 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1551 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1552}
1553
f71d4af4 1554static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1555{
1556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1557 unsigned long irqflags;
1558
1559 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1560 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1561 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1562 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1563}
1564
f71d4af4 1565static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1566{
1567 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1568 unsigned long irqflags;
1569
1570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1571 ironlake_disable_display_irq(dev_priv,
1572 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1573 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1574}
1575
7e231dbe
JB		 1576static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1577{
1578 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1579 unsigned long irqflags;
31acc7f5 1580 u32 imr;
7e231dbe
JB		 1581
1582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1583 i915_disable_pipestat(dev_priv, pipe,
1584 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1585 imr = I915_READ(VLV_IMR);
31acc7f5 1586 if (pipe == 0)
7e231dbe 1587 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1588 else
7e231dbe 1589 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1590 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1591 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1592}
1593
893eead0
CW		 1594static u32
1595ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1596{
893eead0
CW		 1597 return list_entry(ring->request_list.prev,
1598 struct drm_i915_gem_request, list)->seqno;
1599}
1600
1601static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1602{
1603 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1604 i915_seqno_passed(ring->get_seqno(ring, false),
1605 ring_last_seqno(ring))) {
893eead0 1606 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1607 if (waitqueue_active(&ring->irq_queue)) {
1608 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1609 ring->name);
893eead0
CW		 1610 wake_up_all(&ring->irq_queue);
1611 *err = true;
1612 }
1613 return true;
1614 }
1615 return false;
f65d9421
BG		 1616}
1617
1ec14ad3
CW		 1618static bool kick_ring(struct intel_ring_buffer *ring)
1619{
1620 struct drm_device *dev = ring->dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 tmp = I915_READ_CTL(ring);
1623 if (tmp & RING_WAIT) {
1624 DRM_ERROR("Kicking stuck wait on %s\n",
1625 ring->name);
1626 I915_WRITE_CTL(ring, tmp);
1627 return true;
1628 }
1ec14ad3
CW		 1629 return false;
1630}
1631
d1e61e7f
CW		 1632static bool i915_hangcheck_hung(struct drm_device *dev)
1633{
1634 drm_i915_private_t *dev_priv = dev->dev_private;
1635
1636 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1637 bool hung = true;
1638
d1e61e7f
CW		 1639 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1640 i915_handle_error(dev, true);
1641
1642 if (!IS_GEN2(dev)) {
b4519513
CW		 1643 struct intel_ring_buffer *ring;
1644 int i;
1645
d1e61e7f
CW		 1646 /* Is the chip hanging on a WAIT_FOR_EVENT?
1647 * If so we can simply poke the RB_WAIT bit
1648 * and break the hang. This should work on
1649 * all but the second generation chipsets.
1650 */
b4519513
CW		 1651 for_each_ring(ring, dev_priv, i)
1652 hung &= !kick_ring(ring);
d1e61e7f
CW		 1653 }
1654
b4519513 1655 return hung;
d1e61e7f
CW		 1656 }
1657
1658 return false;
1659}
1660
f65d9421
BG		 1661/**
1662 * This is called when the chip hasn't reported back with completed
1663 * batchbuffers in a long time. The first time this is called we simply record
1664 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1665 * again, we assume the chip is wedged and try to fix it.
1666 */
1667void i915_hangcheck_elapsed(unsigned long data)
1668{
1669 struct drm_device *dev = (struct drm_device *)data;
1670 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1671 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1672 struct intel_ring_buffer *ring;
1673 bool err = false, idle;
1674 int i;
893eead0 1675
3e0dc6b0
BW		 1676 if (!i915_enable_hangcheck)
1677 return;
1678
b4519513
CW		 1679 memset(acthd, 0, sizeof(acthd));
1680 idle = true;
1681 for_each_ring(ring, dev_priv, i) {
1682 idle &= i915_hangcheck_ring_idle(ring, &err);
1683 acthd[i] = intel_ring_get_active_head(ring);
1684 }
1685
893eead0 1686 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1687 if (idle) {
d1e61e7f
CW		 1688 if (err) {
1689 if (i915_hangcheck_hung(dev))
1690 return;
1691
893eead0 1692 goto repeat;
d1e61e7f
CW		 1693 }
1694
1695 dev_priv->hangcheck_count = 0;
893eead0
CW		 1696 return;
1697 }
b9201c14 1698
a6c45cf0 1699 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1700 instdone = I915_READ(INSTDONE);
1701 instdone1 = 0;
1702 } else {
cbb465e7
CW		 1703 instdone = I915_READ(INSTDONE_I965);
1704 instdone1 = I915_READ(INSTDONE1);
1705 }
b4519513
CW		 1706
1707 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1708 dev_priv->last_instdone == instdone &&
1709 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1710 if (i915_hangcheck_hung(dev))
cbb465e7 1711 return;
cbb465e7
CW		 1712 } else {
1713 dev_priv->hangcheck_count = 0;
1714
b4519513 1715 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1716 dev_priv->last_instdone = instdone;
1717 dev_priv->last_instdone1 = instdone1;
1718 }
f65d9421 1719
893eead0 1720repeat:
f65d9421 1721 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1722 mod_timer(&dev_priv->hangcheck_timer,
1723 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1724}
1725
1da177e4
LT		 1726/* drm_dma.h hooks
1727*/
f71d4af4 1728static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1729{
1730 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1731
4697995b
JB		 1732 atomic_set(&dev_priv->irq_received, 0);
1733
036a4a7d 1734 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1735
036a4a7d
ZW		 1736 /* XXX hotplug from PCH */
1737
1738 I915_WRITE(DEIMR, 0xffffffff);
1739 I915_WRITE(DEIER, 0x0);
3143a2bf 1740 POSTING_READ(DEIER);
036a4a7d
ZW		 1741
1742 /* and GT */
1743 I915_WRITE(GTIMR, 0xffffffff);
1744 I915_WRITE(GTIER, 0x0);
3143a2bf 1745 POSTING_READ(GTIER);
c650156a
ZW		 1746
1747 /* south display irq */
1748 I915_WRITE(SDEIMR, 0xffffffff);
1749 I915_WRITE(SDEIER, 0x0);
3143a2bf 1750 POSTING_READ(SDEIER);
036a4a7d
ZW		 1751}
1752
7e231dbe
JB		 1753static void valleyview_irq_preinstall(struct drm_device *dev)
1754{
1755 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1756 int pipe;
1757
1758 atomic_set(&dev_priv->irq_received, 0);
1759
7e231dbe
JB		 1760 /* VLV magic */
1761 I915_WRITE(VLV_IMR, 0);
1762 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1763 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1764 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1765
7e231dbe
JB		 1766 /* and GT */
1767 I915_WRITE(GTIIR, I915_READ(GTIIR));
1768 I915_WRITE(GTIIR, I915_READ(GTIIR));
1769 I915_WRITE(GTIMR, 0xffffffff);
1770 I915_WRITE(GTIER, 0x0);
1771 POSTING_READ(GTIER);
1772
1773 I915_WRITE(DPINVGTT, 0xff);
1774
1775 I915_WRITE(PORT_HOTPLUG_EN, 0);
1776 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1777 for_each_pipe(pipe)
1778 I915_WRITE(PIPESTAT(pipe), 0xffff);
1779 I915_WRITE(VLV_IIR, 0xffffffff);
1780 I915_WRITE(VLV_IMR, 0xffffffff);
1781 I915_WRITE(VLV_IER, 0x0);
1782 POSTING_READ(VLV_IER);
1783}
1784
7fe0b973
KP		 1785/*
1786 * Enable digital hotplug on the PCH, and configure the DP short pulse
1787 * duration to 2ms (which is the minimum in the Display Port spec)
1788 *
1789 * This register is the same on all known PCH chips.
1790 */
1791
1792static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1793{
1794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1795 u32 hotplug;
1796
1797 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1798 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1799 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1800 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1801 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1802 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1803}
1804
f71d4af4 1805static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1806{
1807 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1808 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1809 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1810 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1811 u32 render_irqs;
2d7b8366 1812 u32 hotplug_mask;
036a4a7d 1813
1ec14ad3 1814 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1815
1816 /* should always can generate irq */
1817 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1818 I915_WRITE(DEIMR, dev_priv->irq_mask);
1819 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1820 POSTING_READ(DEIER);
036a4a7d 1821
1ec14ad3 1822 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1823
1824 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1825 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1826
1ec14ad3
CW		 1827 if (IS_GEN6(dev))
1828 render_irqs =
1829 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1830 GEN6_BSD_USER_INTERRUPT |
1831 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1832 else
1833 render_irqs =
88f23b8f 1834 GT_USER_INTERRUPT |
c6df541c 1835 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1836 GT_BSD_USER_INTERRUPT;
1837 I915_WRITE(GTIER, render_irqs);
3143a2bf 1838 POSTING_READ(GTIER);
036a4a7d 1839
2d7b8366 1840 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1841 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1842 SDE_PORTB_HOTPLUG_CPT |
1843 SDE_PORTC_HOTPLUG_CPT |
1844 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1845 } else {
9035a97a
CW		 1846 hotplug_mask = (SDE_CRT_HOTPLUG |
1847 SDE_PORTB_HOTPLUG |
1848 SDE_PORTC_HOTPLUG |
1849 SDE_PORTD_HOTPLUG |
1850 SDE_AUX_MASK);
2d7b8366
YL		 1851 }
1852
1ec14ad3 1853 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1854
1855 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1856 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1857 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1858 POSTING_READ(SDEIER);
c650156a 1859
7fe0b973
KP		 1860 ironlake_enable_pch_hotplug(dev);
1861
f97108d1
JB		 1862 if (IS_IRONLAKE_M(dev)) {
1863 /* Clear & enable PCU event interrupts */
1864 I915_WRITE(DEIIR, DE_PCU_EVENT);
1865 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1866 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1867 }
1868
036a4a7d
ZW		 1869 return 0;
1870}
1871
f71d4af4 1872static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1873{
1874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1875 /* enable kind of interrupts always enabled */
b615b57a
CW		 1876 u32 display_mask =
1877 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1878 DE_PLANEC_FLIP_DONE_IVB |
1879 DE_PLANEB_FLIP_DONE_IVB |
1880 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1881 u32 render_irqs;
1882 u32 hotplug_mask;
1883
b1f14ad0
JB		 1884 dev_priv->irq_mask = ~display_mask;
1885
1886 /* should always can generate irq */
1887 I915_WRITE(DEIIR, I915_READ(DEIIR));
1888 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1889 I915_WRITE(DEIER,
1890 display_mask |
1891 DE_PIPEC_VBLANK_IVB |
1892 DE_PIPEB_VBLANK_IVB |
1893 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1894 POSTING_READ(DEIER);
1895
15b9f80e 1896 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1897
1898 I915_WRITE(GTIIR, I915_READ(GTIIR));
1899 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1900
e2a1e2f0 1901 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1902 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1903 I915_WRITE(GTIER, render_irqs);
1904 POSTING_READ(GTIER);
1905
1906 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1907 SDE_PORTB_HOTPLUG_CPT |
1908 SDE_PORTC_HOTPLUG_CPT |
1909 SDE_PORTD_HOTPLUG_CPT);
1910 dev_priv->pch_irq_mask = ~hotplug_mask;
1911
1912 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1913 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1914 I915_WRITE(SDEIER, hotplug_mask);
1915 POSTING_READ(SDEIER);
1916
7fe0b973
KP		 1917 ironlake_enable_pch_hotplug(dev);
1918
b1f14ad0
JB		 1919 return 0;
1920}
1921
7e231dbe
JB		 1922static int valleyview_irq_postinstall(struct drm_device *dev)
1923{
1924 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1925 u32 enable_mask;
1926 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1927 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 1928 u16 msid;
1929
1930 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1931 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1932 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1933 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1934 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1935
31acc7f5
JB		 1936 /*
1937 *Leave vblank interrupts masked initially. enable/disable will
1938 * toggle them based on usage.
1939 */
1940 dev_priv->irq_mask = (~enable_mask) |
1941 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1942 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1943
7e231dbe
JB		 1944 dev_priv->pipestat[0] = 0;
1945 dev_priv->pipestat[1] = 0;
1946
7e231dbe
JB		 1947 /* Hack for broken MSIs on VLV */
1948 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1949 pci_read_config_word(dev->pdev, 0x98, &msid);
1950 msid &= 0xff; /* mask out delivery bits */
1951 msid |= (1<<14);
1952 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1953
1954 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1955 I915_WRITE(VLV_IER, enable_mask);
1956 I915_WRITE(VLV_IIR, 0xffffffff);
1957 I915_WRITE(PIPESTAT(0), 0xffff);
1958 I915_WRITE(PIPESTAT(1), 0xffff);
1959 POSTING_READ(VLV_IER);
1960
31acc7f5
JB		 1961 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1962 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1963
7e231dbe
JB		 1964 I915_WRITE(VLV_IIR, 0xffffffff);
1965 I915_WRITE(VLV_IIR, 0xffffffff);
1966
31acc7f5 1967 dev_priv->gt_irq_mask = ~0;
7e231dbe
JB		 1968
1969 I915_WRITE(GTIIR, I915_READ(GTIIR));
1970 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5
JB		 1971 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1972 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1973 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1974 GT_GEN6_BLT_USER_INTERRUPT |
1975 GT_GEN6_BSD_USER_INTERRUPT |
1976 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1977 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1978 GT_PIPE_NOTIFY |
1979 GT_RENDER_CS_ERROR_INTERRUPT |
1980 GT_SYNC_STATUS |
1981 GT_USER_INTERRUPT);
7e231dbe
JB		 1982 POSTING_READ(GTIER);
1983
1984 /* ack & enable invalid PTE error interrupts */
1985#if 0 /* FIXME: add support to irq handler for checking these bits */
1986 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1987 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1988#endif
1989
1990 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1991#if 0 /* FIXME: check register definitions; some have moved */
1992 /* Note HDMI and DP share bits */
1993 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1994 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1995 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1996 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1997 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1998 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1999 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2000 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2001 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2002 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2003 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2004 hotplug_en |= CRT_HOTPLUG_INT_EN;
2005 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2006 }
2007#endif
2008
2009 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2010
2011 return 0;
2012}
2013
7e231dbe
JB		 2014static void valleyview_irq_uninstall(struct drm_device *dev)
2015{
2016 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2017 int pipe;
2018
2019 if (!dev_priv)
2020 return;
2021
7e231dbe
JB		 2022 for_each_pipe(pipe)
2023 I915_WRITE(PIPESTAT(pipe), 0xffff);
2024
2025 I915_WRITE(HWSTAM, 0xffffffff);
2026 I915_WRITE(PORT_HOTPLUG_EN, 0);
2027 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2028 for_each_pipe(pipe)
2029 I915_WRITE(PIPESTAT(pipe), 0xffff);
2030 I915_WRITE(VLV_IIR, 0xffffffff);
2031 I915_WRITE(VLV_IMR, 0xffffffff);
2032 I915_WRITE(VLV_IER, 0x0);
2033 POSTING_READ(VLV_IER);
2034}
2035
f71d4af4 2036static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2037{
2038 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2039
2040 if (!dev_priv)
2041 return;
2042
036a4a7d
ZW		 2043 I915_WRITE(HWSTAM, 0xffffffff);
2044
2045 I915_WRITE(DEIMR, 0xffffffff);
2046 I915_WRITE(DEIER, 0x0);
2047 I915_WRITE(DEIIR, I915_READ(DEIIR));
2048
2049 I915_WRITE(GTIMR, 0xffffffff);
2050 I915_WRITE(GTIER, 0x0);
2051 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2052
2053 I915_WRITE(SDEIMR, 0xffffffff);
2054 I915_WRITE(SDEIER, 0x0);
2055 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2056}
2057
a266c7d5 2058static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2059{
2060 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2061 int pipe;
91e3738e 2062
a266c7d5 2063 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2064
9db4a9c7
JB		 2065 for_each_pipe(pipe)
2066 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2067 I915_WRITE16(IMR, 0xffff);
2068 I915_WRITE16(IER, 0x0);
2069 POSTING_READ16(IER);
c2798b19
CW		 2070}
2071
2072static int i8xx_irq_postinstall(struct drm_device *dev)
2073{
2074 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2075
c2798b19
CW		 2076 dev_priv->pipestat[0] = 0;
2077 dev_priv->pipestat[1] = 0;
2078
2079 I915_WRITE16(EMR,
2080 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2081
2082 /* Unmask the interrupts that we always want on. */
2083 dev_priv->irq_mask =
2084 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2085 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2086 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2087 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2088 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2089 I915_WRITE16(IMR, dev_priv->irq_mask);
2090
2091 I915_WRITE16(IER,
2092 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2093 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2094 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2095 I915_USER_INTERRUPT);
2096 POSTING_READ16(IER);
2097
2098 return 0;
2099}
2100
2101static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2102{
2103 struct drm_device *dev = (struct drm_device *) arg;
2104 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2105 u16 iir, new_iir;
2106 u32 pipe_stats[2];
2107 unsigned long irqflags;
2108 int irq_received;
2109 int pipe;
2110 u16 flip_mask =
2111 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2112 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2113
2114 atomic_inc(&dev_priv->irq_received);
2115
2116 iir = I915_READ16(IIR);
2117 if (iir == 0)
2118 return IRQ_NONE;
2119
2120 while (iir & ~flip_mask) {
2121 /* Can't rely on pipestat interrupt bit in iir as it might
2122 * have been cleared after the pipestat interrupt was received.
2123 * It doesn't set the bit in iir again, but it still produces
2124 * interrupts (for non-MSI).
2125 */
2126 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2127 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2128 i915_handle_error(dev, false);
2129
2130 for_each_pipe(pipe) {
2131 int reg = PIPESTAT(pipe);
2132 pipe_stats[pipe] = I915_READ(reg);
2133
2134 /*
2135 * Clear the PIPE*STAT regs before the IIR
2136 */
2137 if (pipe_stats[pipe] & 0x8000ffff) {
2138 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2139 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2140 pipe_name(pipe));
2141 I915_WRITE(reg, pipe_stats[pipe]);
2142 irq_received = 1;
2143 }
2144 }
2145 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2146
2147 I915_WRITE16(IIR, iir & ~flip_mask);
2148 new_iir = I915_READ16(IIR); /* Flush posted writes */
2149
d05c617e 2150 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2151
2152 if (iir & I915_USER_INTERRUPT)
2153 notify_ring(dev, &dev_priv->ring[RCS]);
2154
2155 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2156 drm_handle_vblank(dev, 0)) {
2157 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2158 intel_prepare_page_flip(dev, 0);
2159 intel_finish_page_flip(dev, 0);
2160 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2161 }
2162 }
2163
2164 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2165 drm_handle_vblank(dev, 1)) {
2166 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2167 intel_prepare_page_flip(dev, 1);
2168 intel_finish_page_flip(dev, 1);
2169 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2170 }
2171 }
2172
2173 iir = new_iir;
2174 }
2175
2176 return IRQ_HANDLED;
2177}
2178
2179static void i8xx_irq_uninstall(struct drm_device * dev)
2180{
2181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2182 int pipe;
2183
c2798b19
CW		 2184 for_each_pipe(pipe) {
2185 /* Clear enable bits; then clear status bits */
2186 I915_WRITE(PIPESTAT(pipe), 0);
2187 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2188 }
2189 I915_WRITE16(IMR, 0xffff);
2190 I915_WRITE16(IER, 0x0);
2191 I915_WRITE16(IIR, I915_READ16(IIR));
2192}
2193
a266c7d5
CW		 2194static void i915_irq_preinstall(struct drm_device * dev)
2195{
2196 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2197 int pipe;
2198
2199 atomic_set(&dev_priv->irq_received, 0);
2200
2201 if (I915_HAS_HOTPLUG(dev)) {
2202 I915_WRITE(PORT_HOTPLUG_EN, 0);
2203 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2204 }
2205
00d98ebd 2206 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2207 for_each_pipe(pipe)
2208 I915_WRITE(PIPESTAT(pipe), 0);
2209 I915_WRITE(IMR, 0xffffffff);
2210 I915_WRITE(IER, 0x0);
2211 POSTING_READ(IER);
2212}
2213
2214static int i915_irq_postinstall(struct drm_device *dev)
2215{
2216 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2217 u32 enable_mask;
a266c7d5 2218
a266c7d5
CW		 2219 dev_priv->pipestat[0] = 0;
2220 dev_priv->pipestat[1] = 0;
2221
38bde180
CW		 2222 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2223
2224 /* Unmask the interrupts that we always want on. */
2225 dev_priv->irq_mask =
2226 ~(I915_ASLE_INTERRUPT |
2227 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2228 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2229 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2230 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2231 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2232
2233 enable_mask =
2234 I915_ASLE_INTERRUPT |
2235 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2236 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2237 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2238 I915_USER_INTERRUPT;
2239
a266c7d5
CW		 2240 if (I915_HAS_HOTPLUG(dev)) {
2241 /* Enable in IER... */
2242 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2243 /* and unmask in IMR */
2244 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2245 }
2246
a266c7d5
CW		 2247 I915_WRITE(IMR, dev_priv->irq_mask);
2248 I915_WRITE(IER, enable_mask);
2249 POSTING_READ(IER);
2250
2251 if (I915_HAS_HOTPLUG(dev)) {
2252 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2253
a266c7d5
CW		 2254 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2255 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2256 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2257 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2258 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2259 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2260 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2261 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2262 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2263 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2264 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2265 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2266 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2267 }
2268
2269 /* Ignore TV since it's buggy */
2270
2271 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2272 }
2273
2274 intel_opregion_enable_asle(dev);
2275
2276 return 0;
2277}
2278
2279static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2280{
2281 struct drm_device *dev = (struct drm_device *) arg;
2282 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2283 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2284 unsigned long irqflags;
38bde180
CW		 2285 u32 flip_mask =
2286 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2287 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2288 u32 flip[2] = {
2289 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2290 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2291 };
2292 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2293
2294 atomic_inc(&dev_priv->irq_received);
2295
2296 iir = I915_READ(IIR);
38bde180
CW		 2297 do {
2298 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2299 bool blc_event = false;
a266c7d5
CW		 2300
2301 /* Can't rely on pipestat interrupt bit in iir as it might
2302 * have been cleared after the pipestat interrupt was received.
2303 * It doesn't set the bit in iir again, but it still produces
2304 * interrupts (for non-MSI).
2305 */
2306 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2307 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2308 i915_handle_error(dev, false);
2309
2310 for_each_pipe(pipe) {
2311 int reg = PIPESTAT(pipe);
2312 pipe_stats[pipe] = I915_READ(reg);
2313
38bde180 2314 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2315 if (pipe_stats[pipe] & 0x8000ffff) {
2316 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2317 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2318 pipe_name(pipe));
2319 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2320 irq_received = true;
a266c7d5
CW		 2321 }
2322 }
2323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2324
2325 if (!irq_received)
2326 break;
2327
a266c7d5
CW		 2328 /* Consume port. Then clear IIR or we'll miss events */
2329 if ((I915_HAS_HOTPLUG(dev)) &&
2330 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2331 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2332
2333 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2334 hotplug_status);
2335 if (hotplug_status & dev_priv->hotplug_supported_mask)
2336 queue_work(dev_priv->wq,
2337 &dev_priv->hotplug_work);
2338
2339 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2340 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2341 }
2342
38bde180 2343 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2344 new_iir = I915_READ(IIR); /* Flush posted writes */
2345
a266c7d5
CW		 2346 if (iir & I915_USER_INTERRUPT)
2347 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2348
a266c7d5 2349 for_each_pipe(pipe) {
38bde180
CW		 2350 int plane = pipe;
2351 if (IS_MOBILE(dev))
2352 plane = !plane;
8291ee90 2353 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2354 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2355 if (iir & flip[plane]) {
2356 intel_prepare_page_flip(dev, plane);
2357 intel_finish_page_flip(dev, pipe);
2358 flip_mask &= ~flip[plane];
2359 }
a266c7d5
CW		 2360 }
2361
2362 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2363 blc_event = true;
2364 }
2365
a266c7d5
CW		 2366 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2367 intel_opregion_asle_intr(dev);
2368
2369 /* With MSI, interrupts are only generated when iir
2370 * transitions from zero to nonzero. If another bit got
2371 * set while we were handling the existing iir bits, then
2372 * we would never get another interrupt.
2373 *
2374 * This is fine on non-MSI as well, as if we hit this path
2375 * we avoid exiting the interrupt handler only to generate
2376 * another one.
2377 *
2378 * Note that for MSI this could cause a stray interrupt report
2379 * if an interrupt landed in the time between writing IIR and
2380 * the posting read. This should be rare enough to never
2381 * trigger the 99% of 100,000 interrupts test for disabling
2382 * stray interrupts.
2383 */
38bde180 2384 ret = IRQ_HANDLED;
a266c7d5 2385 iir = new_iir;
38bde180 2386 } while (iir & ~flip_mask);
a266c7d5 2387
d05c617e 2388 i915_update_dri1_breadcrumb(dev);
8291ee90 2389
a266c7d5
CW		 2390 return ret;
2391}
2392
2393static void i915_irq_uninstall(struct drm_device * dev)
2394{
2395 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2396 int pipe;
2397
a266c7d5
CW		 2398 if (I915_HAS_HOTPLUG(dev)) {
2399 I915_WRITE(PORT_HOTPLUG_EN, 0);
2400 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2401 }
2402
00d98ebd 2403 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2404 for_each_pipe(pipe) {
2405 /* Clear enable bits; then clear status bits */
a266c7d5 2406 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2407 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2408 }
a266c7d5
CW		 2409 I915_WRITE(IMR, 0xffffffff);
2410 I915_WRITE(IER, 0x0);
2411
a266c7d5
CW		 2412 I915_WRITE(IIR, I915_READ(IIR));
2413}
2414
2415static void i965_irq_preinstall(struct drm_device * dev)
2416{
2417 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2418 int pipe;
2419
2420 atomic_set(&dev_priv->irq_received, 0);
2421
adca4730
CW		 2422 I915_WRITE(PORT_HOTPLUG_EN, 0);
2423 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2424
2425 I915_WRITE(HWSTAM, 0xeffe);
2426 for_each_pipe(pipe)
2427 I915_WRITE(PIPESTAT(pipe), 0);
2428 I915_WRITE(IMR, 0xffffffff);
2429 I915_WRITE(IER, 0x0);
2430 POSTING_READ(IER);
2431}
2432
2433static int i965_irq_postinstall(struct drm_device *dev)
2434{
2435 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2436 u32 hotplug_en;
bbba0a97 2437 u32 enable_mask;
a266c7d5
CW		 2438 u32 error_mask;
2439
a266c7d5 2440 /* Unmask the interrupts that we always want on. */
bbba0a97 2441 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2442 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2443 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2444 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2445 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2446 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2447 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2448
2449 enable_mask = ~dev_priv->irq_mask;
2450 enable_mask |= I915_USER_INTERRUPT;
2451
2452 if (IS_G4X(dev))
2453 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2454
2455 dev_priv->pipestat[0] = 0;
2456 dev_priv->pipestat[1] = 0;
2457
a266c7d5
CW		 2458 /*
2459 * Enable some error detection, note the instruction error mask
2460 * bit is reserved, so we leave it masked.
2461 */
2462 if (IS_G4X(dev)) {
2463 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2464 GM45_ERROR_MEM_PRIV |
2465 GM45_ERROR_CP_PRIV |
2466 I915_ERROR_MEMORY_REFRESH);
2467 } else {
2468 error_mask = ~(I915_ERROR_PAGE_TABLE |
2469 I915_ERROR_MEMORY_REFRESH);
2470 }
2471 I915_WRITE(EMR, error_mask);
2472
2473 I915_WRITE(IMR, dev_priv->irq_mask);
2474 I915_WRITE(IER, enable_mask);
2475 POSTING_READ(IER);
2476
adca4730
CW		 2477 /* Note HDMI and DP share hotplug bits */
2478 hotplug_en = 0;
2479 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2480 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2481 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2482 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2483 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2484 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2485 if (IS_G4X(dev)) {
2486 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2487 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2488 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2489 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2490 } else {
2491 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2492 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2493 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2494 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2495 }
adca4730
CW		 2496 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2497 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2498
adca4730
CW		 2499 /* Programming the CRT detection parameters tends
2500 to generate a spurious hotplug event about three
2501 seconds later. So just do it once.
2502 */
2503 if (IS_G4X(dev))
2504 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2505 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2506 }
a266c7d5 2507
adca4730 2508 /* Ignore TV since it's buggy */
a266c7d5 2509
adca4730 2510 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2511
2512 intel_opregion_enable_asle(dev);
2513
2514 return 0;
2515}
2516
2517static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2518{
2519 struct drm_device *dev = (struct drm_device *) arg;
2520 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2521 u32 iir, new_iir;
2522 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2523 unsigned long irqflags;
2524 int irq_received;
2525 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2526
2527 atomic_inc(&dev_priv->irq_received);
2528
2529 iir = I915_READ(IIR);
2530
a266c7d5 2531 for (;;) {
2c8ba29f
CW		 2532 bool blc_event = false;
2533
a266c7d5
CW		 2534 irq_received = iir != 0;
2535
2536 /* Can't rely on pipestat interrupt bit in iir as it might
2537 * have been cleared after the pipestat interrupt was received.
2538 * It doesn't set the bit in iir again, but it still produces
2539 * interrupts (for non-MSI).
2540 */
2541 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2542 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2543 i915_handle_error(dev, false);
2544
2545 for_each_pipe(pipe) {
2546 int reg = PIPESTAT(pipe);
2547 pipe_stats[pipe] = I915_READ(reg);
2548
2549 /*
2550 * Clear the PIPE*STAT regs before the IIR
2551 */
2552 if (pipe_stats[pipe] & 0x8000ffff) {
2553 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2554 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2555 pipe_name(pipe));
2556 I915_WRITE(reg, pipe_stats[pipe]);
2557 irq_received = 1;
2558 }
2559 }
2560 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2561
2562 if (!irq_received)
2563 break;
2564
2565 ret = IRQ_HANDLED;
2566
2567 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2568 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2569 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2570
2571 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2572 hotplug_status);
2573 if (hotplug_status & dev_priv->hotplug_supported_mask)
2574 queue_work(dev_priv->wq,
2575 &dev_priv->hotplug_work);
2576
2577 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2578 I915_READ(PORT_HOTPLUG_STAT);
2579 }
2580
2581 I915_WRITE(IIR, iir);
2582 new_iir = I915_READ(IIR); /* Flush posted writes */
2583
a266c7d5
CW		 2584 if (iir & I915_USER_INTERRUPT)
2585 notify_ring(dev, &dev_priv->ring[RCS]);
2586 if (iir & I915_BSD_USER_INTERRUPT)
2587 notify_ring(dev, &dev_priv->ring[VCS]);
2588
4f7d1e79 2589 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2590 intel_prepare_page_flip(dev, 0);
a266c7d5 2591
4f7d1e79 2592 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2593 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2594
2595 for_each_pipe(pipe) {
2c8ba29f 2596 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2597 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2598 i915_pageflip_stall_check(dev, pipe);
2599 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2600 }
2601
2602 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2603 blc_event = true;
2604 }
2605
2606
2607 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2608 intel_opregion_asle_intr(dev);
2609
2610 /* With MSI, interrupts are only generated when iir
2611 * transitions from zero to nonzero. If another bit got
2612 * set while we were handling the existing iir bits, then
2613 * we would never get another interrupt.
2614 *
2615 * This is fine on non-MSI as well, as if we hit this path
2616 * we avoid exiting the interrupt handler only to generate
2617 * another one.
2618 *
2619 * Note that for MSI this could cause a stray interrupt report
2620 * if an interrupt landed in the time between writing IIR and
2621 * the posting read. This should be rare enough to never
2622 * trigger the 99% of 100,000 interrupts test for disabling
2623 * stray interrupts.
2624 */
2625 iir = new_iir;
2626 }
2627
d05c617e 2628 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2629
a266c7d5
CW		 2630 return ret;
2631}
2632
2633static void i965_irq_uninstall(struct drm_device * dev)
2634{
2635 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2636 int pipe;
2637
2638 if (!dev_priv)
2639 return;
2640
adca4730
CW		 2641 I915_WRITE(PORT_HOTPLUG_EN, 0);
2642 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2643
2644 I915_WRITE(HWSTAM, 0xffffffff);
2645 for_each_pipe(pipe)
2646 I915_WRITE(PIPESTAT(pipe), 0);
2647 I915_WRITE(IMR, 0xffffffff);
2648 I915_WRITE(IER, 0x0);
2649
2650 for_each_pipe(pipe)
2651 I915_WRITE(PIPESTAT(pipe),
2652 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2653 I915_WRITE(IIR, I915_READ(IIR));
2654}
2655
f71d4af4
JB		 2656void intel_irq_init(struct drm_device *dev)
2657{
8b2e326d
CW		 2658 struct drm_i915_private *dev_priv = dev->dev_private;
2659
2660 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2661 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2662 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2663 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2664
f71d4af4
JB		 2665 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2666 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2667 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2668 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2669 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2670 }
2671
c3613de9
KP		 2672 if (drm_core_check_feature(dev, DRIVER_MODESET))
2673 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2674 else
2675 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2676 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2677
7e231dbe
JB		 2678 if (IS_VALLEYVIEW(dev)) {
2679 dev->driver->irq_handler = valleyview_irq_handler;
2680 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2681 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2682 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2683 dev->driver->enable_vblank = valleyview_enable_vblank;
2684 dev->driver->disable_vblank = valleyview_disable_vblank;
2685 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2686 /* Share pre & uninstall handlers with ILK/SNB */
2687 dev->driver->irq_handler = ivybridge_irq_handler;
2688 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2689 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2690 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2691 dev->driver->enable_vblank = ivybridge_enable_vblank;
2692 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2693 } else if (IS_HASWELL(dev)) {
2694 /* Share interrupts handling with IVB */
2695 dev->driver->irq_handler = ivybridge_irq_handler;
2696 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2697 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2698 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2699 dev->driver->enable_vblank = ivybridge_enable_vblank;
2700 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2701 } else if (HAS_PCH_SPLIT(dev)) {
2702 dev->driver->irq_handler = ironlake_irq_handler;
2703 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2704 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2705 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2706 dev->driver->enable_vblank = ironlake_enable_vblank;
2707 dev->driver->disable_vblank = ironlake_disable_vblank;
2708 } else {
c2798b19
CW		 2709 if (INTEL_INFO(dev)->gen == 2) {
2710 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2711 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2712 dev->driver->irq_handler = i8xx_irq_handler;
2713 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2714 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2715 /* IIR "flip pending" means done if this bit is set */
2716 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2717
a266c7d5
CW		 2718 dev->driver->irq_preinstall = i915_irq_preinstall;
2719 dev->driver->irq_postinstall = i915_irq_postinstall;
2720 dev->driver->irq_uninstall = i915_irq_uninstall;
2721 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2722 } else {
a266c7d5
CW		 2723 dev->driver->irq_preinstall = i965_irq_preinstall;
2724 dev->driver->irq_postinstall = i965_irq_postinstall;
2725 dev->driver->irq_uninstall = i965_irq_uninstall;
2726 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2727 }
f71d4af4
JB		 2728 dev->driver->enable_vblank = i915_enable_vblank;
2729 dev->driver->disable_vblank = i915_disable_vblank;
2730 }
2731}
Linux kernel - Deliverables
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