projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Limit FIFO underrun reports on GMCH platforms
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
704cfb87 65static const u32 hpd_status_g4x[] = {
e5868a31
EE		 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
036a4a7d 83/* For display hotplug interrupt */
995b6762 84static void
f2b115e6 85ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 86{
4bc9d430
DV		 87 assert_spin_locked(&dev_priv->irq_lock);
88
c67a470b
PZ		 89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
92 return;
93 }
94
1ec14ad3
CW		 95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 98 POSTING_READ(DEIMR);
036a4a7d
ZW		 99 }
100}
101
0ff9800a 102static void
f2b115e6 103ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 104{
4bc9d430
DV		 105 assert_spin_locked(&dev_priv->irq_lock);
106
c67a470b
PZ		 107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
110 return;
111 }
112
1ec14ad3
CW		 113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 116 POSTING_READ(DEIMR);
036a4a7d
ZW		 117 }
118}
119
43eaea13
PZ		 120/**
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
125 */
126static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
129{
130 assert_spin_locked(&dev_priv->irq_lock);
131
c67a470b
PZ		 132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask);
137 return;
138 }
139
43eaea13
PZ		 140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
143 POSTING_READ(GTIMR);
144}
145
146void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
147{
148 ilk_update_gt_irq(dev_priv, mask, mask);
149}
150
151void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
152{
153 ilk_update_gt_irq(dev_priv, mask, 0);
154}
155
edbfdb45
PZ		 156/**
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
161 */
162static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
165{
605cd25b 166 uint32_t new_val;
edbfdb45
PZ		 167
168 assert_spin_locked(&dev_priv->irq_lock);
169
c67a470b
PZ		 170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask);
175 return;
176 }
177
605cd25b 178 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
181
605cd25b
PZ		 182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 185 POSTING_READ(GEN6_PMIMR);
186 }
edbfdb45
PZ		 187}
188
189void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
190{
191 snb_update_pm_irq(dev_priv, mask, mask);
192}
193
194void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
195{
196 snb_update_pm_irq(dev_priv, mask, 0);
197}
198
8664281b
PZ		 199static bool ivb_can_enable_err_int(struct drm_device *dev)
200{
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
203 enum pipe pipe;
204
4bc9d430
DV		 205 assert_spin_locked(&dev_priv->irq_lock);
206
8664281b
PZ		 207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
209
210 if (crtc->cpu_fifo_underrun_disabled)
211 return false;
212 }
213
214 return true;
215}
216
217static bool cpt_can_enable_serr_int(struct drm_device *dev)
218{
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 enum pipe pipe;
221 struct intel_crtc *crtc;
222
fee884ed
DV		 223 assert_spin_locked(&dev_priv->irq_lock);
224
8664281b
PZ		 225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
227
228 if (crtc->pch_fifo_underrun_disabled)
229 return false;
230 }
231
232 return true;
233}
234
2d9d2b0b
VS		 235static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 reg = PIPESTAT(pipe);
239 u32 pipestat = I915_READ(reg) & 0x7fff0000;
240
241 assert_spin_locked(&dev_priv->irq_lock);
242
243 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
244 POSTING_READ(reg);
245}
246
8664281b
PZ		 247static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum pipe pipe, bool enable)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
252 DE_PIPEB_FIFO_UNDERRUN;
253
254 if (enable)
255 ironlake_enable_display_irq(dev_priv, bit);
256 else
257 ironlake_disable_display_irq(dev_priv, bit);
258}
259
260static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 261 enum pipe pipe, bool enable)
8664281b
PZ		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 264 if (enable) {
7336df65
DV		 265 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
266
8664281b
PZ		 267 if (!ivb_can_enable_err_int(dev))
268 return;
269
8664281b
PZ		 270 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
271 } else {
7336df65
DV		 272 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
273
274 /* Change the state _after_ we've read out the current one. */
8664281b 275 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 276
277 if (!was_enabled &&
278 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
279 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
280 pipe_name(pipe));
281 }
8664281b
PZ		 282 }
283}
284
38d83c96
DV		 285static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
286 enum pipe pipe, bool enable)
287{
288 struct drm_i915_private *dev_priv = dev->dev_private;
289
290 assert_spin_locked(&dev_priv->irq_lock);
291
292 if (enable)
293 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
294 else
295 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
296 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
297 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
298}
299
fee884ed
DV		 300/**
301 * ibx_display_interrupt_update - update SDEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
307 uint32_t interrupt_mask,
308 uint32_t enabled_irq_mask)
309{
310 uint32_t sdeimr = I915_READ(SDEIMR);
311 sdeimr &= ~interrupt_mask;
312 sdeimr |= (~enabled_irq_mask & interrupt_mask);
313
314 assert_spin_locked(&dev_priv->irq_lock);
315
c67a470b
PZ		 316 if (dev_priv->pc8.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n");
319 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask);
322 return;
323 }
324
fee884ed
DV		 325 I915_WRITE(SDEIMR, sdeimr);
326 POSTING_READ(SDEIMR);
327}
328#define ibx_enable_display_interrupt(dev_priv, bits) \
329 ibx_display_interrupt_update((dev_priv), (bits), (bits))
330#define ibx_disable_display_interrupt(dev_priv, bits) \
331 ibx_display_interrupt_update((dev_priv), (bits), 0)
332
de28075d
DV		 333static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
334 enum transcoder pch_transcoder,
8664281b
PZ		 335 bool enable)
336{
8664281b 337 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 338 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
339 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 340
341 if (enable)
fee884ed 342 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 343 else
fee884ed 344 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 345}
346
347static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
348 enum transcoder pch_transcoder,
349 bool enable)
350{
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 if (enable) {
1dd246fb
DV		 354 I915_WRITE(SERR_INT,
355 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
356
8664281b
PZ		 357 if (!cpt_can_enable_serr_int(dev))
358 return;
359
fee884ed 360 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 361 } else {
1dd246fb
DV		 362 uint32_t tmp = I915_READ(SERR_INT);
363 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
364
365 /* Change the state _after_ we've read out the current one. */
fee884ed 366 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 367
368 if (!was_enabled &&
369 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
370 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
371 transcoder_name(pch_transcoder));
372 }
8664281b 373 }
8664281b
PZ		 374}
375
376/**
377 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
378 * @dev: drm device
379 * @pipe: pipe
380 * @enable: true if we want to report FIFO underrun errors, false otherwise
381 *
382 * This function makes us disable or enable CPU fifo underruns for a specific
383 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
384 * reporting for one pipe may also disable all the other CPU error interruts for
385 * the other pipes, due to the fact that there's just one interrupt mask/enable
386 * bit for all the pipes.
387 *
388 * Returns the previous state of underrun reporting.
389 */
390bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
391 enum pipe pipe, bool enable)
392{
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
396 unsigned long flags;
397 bool ret;
398
399 spin_lock_irqsave(&dev_priv->irq_lock, flags);
400
401 ret = !intel_crtc->cpu_fifo_underrun_disabled;
402
403 if (enable == ret)
404 goto done;
405
406 intel_crtc->cpu_fifo_underrun_disabled = !enable;
407
2d9d2b0b
VS		 408 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
409 i9xx_clear_fifo_underrun(dev, pipe);
410 else if (IS_GEN5(dev) || IS_GEN6(dev))
8664281b
PZ		 411 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
412 else if (IS_GEN7(dev))
7336df65 413 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
38d83c96
DV		 414 else if (IS_GEN8(dev))
415 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 416
417done:
418 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
419 return ret;
420}
421
422/**
423 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
424 * @dev: drm device
425 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
426 * @enable: true if we want to report FIFO underrun errors, false otherwise
427 *
428 * This function makes us disable or enable PCH fifo underruns for a specific
429 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
430 * underrun reporting for one transcoder may also disable all the other PCH
431 * error interruts for the other transcoders, due to the fact that there's just
432 * one interrupt mask/enable bit for all the transcoders.
433 *
434 * Returns the previous state of underrun reporting.
435 */
436bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
437 enum transcoder pch_transcoder,
438 bool enable)
439{
440 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 441 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 443 unsigned long flags;
444 bool ret;
445
de28075d
DV		 446 /*
447 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
448 * has only one pch transcoder A that all pipes can use. To avoid racy
449 * pch transcoder -> pipe lookups from interrupt code simply store the
450 * underrun statistics in crtc A. Since we never expose this anywhere
451 * nor use it outside of the fifo underrun code here using the "wrong"
452 * crtc on LPT won't cause issues.
453 */
8664281b
PZ		 454
455 spin_lock_irqsave(&dev_priv->irq_lock, flags);
456
457 ret = !intel_crtc->pch_fifo_underrun_disabled;
458
459 if (enable == ret)
460 goto done;
461
462 intel_crtc->pch_fifo_underrun_disabled = !enable;
463
464 if (HAS_PCH_IBX(dev))
de28075d 465 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 466 else
467 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
468
469done:
470 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
471 return ret;
472}
473
474
7c463586 475void
3b6c42e8 476i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
7c463586 477{
46c06a30
VS		 478 u32 reg = PIPESTAT(pipe);
479 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 480
b79480ba
DV		 481 assert_spin_locked(&dev_priv->irq_lock);
482
46c06a30
VS		 483 if ((pipestat & mask) == mask)
484 return;
485
486 /* Enable the interrupt, clear any pending status */
487 pipestat |= mask | (mask >> 16);
488 I915_WRITE(reg, pipestat);
489 POSTING_READ(reg);
7c463586
KP		 490}
491
492void
3b6c42e8 493i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
7c463586 494{
46c06a30
VS		 495 u32 reg = PIPESTAT(pipe);
496 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 497
b79480ba
DV		 498 assert_spin_locked(&dev_priv->irq_lock);
499
46c06a30
VS		 500 if ((pipestat & mask) == 0)
501 return;
502
503 pipestat &= ~mask;
504 I915_WRITE(reg, pipestat);
505 POSTING_READ(reg);
7c463586
KP		 506}
507
01c66889 508/**
f49e38dd 509 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 510 */
f49e38dd 511static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 512{
1ec14ad3
CW		 513 drm_i915_private_t *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515
f49e38dd
JN		 516 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
517 return;
518
1ec14ad3 519 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 520
3b6c42e8 521 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
f898780b 522 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8
DV		 523 i915_enable_pipestat(dev_priv, PIPE_A,
524 PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 525
526 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 527}
528
0a3e67a4
JB		 529/**
530 * i915_pipe_enabled - check if a pipe is enabled
531 * @dev: DRM device
532 * @pipe: pipe to check
533 *
534 * Reading certain registers when the pipe is disabled can hang the chip.
535 * Use this routine to make sure the PLL is running and the pipe is active
536 * before reading such registers if unsure.
537 */
538static int
539i915_pipe_enabled(struct drm_device *dev, int pipe)
540{
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 542
a01025af
DV		 543 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
544 /* Locking is horribly broken here, but whatever. */
545 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 547
a01025af
DV		 548 return intel_crtc->active;
549 } else {
550 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
551 }
0a3e67a4
JB		 552}
553
4cdb83ec
VS		 554static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
555{
556 /* Gen2 doesn't have a hardware frame counter */
557 return 0;
558}
559
42f52ef8
KP		 560/* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
f71d4af4 563static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 564{
565 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
566 unsigned long high_frame;
567 unsigned long low_frame;
391f75e2 568 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 569
570 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 571 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 572 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 573 return 0;
574 }
575
391f75e2
VS		 576 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
577 struct intel_crtc *intel_crtc =
578 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
579 const struct drm_display_mode *mode =
580 &intel_crtc->config.adjusted_mode;
581
582 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
583 } else {
584 enum transcoder cpu_transcoder =
585 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
586 u32 htotal;
587
588 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
589 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
590
591 vbl_start *= htotal;
592 }
593
9db4a9c7
JB		 594 high_frame = PIPEFRAME(pipe);
595 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 596
0a3e67a4
JB		 597 /*
598 * High & low register fields aren't synchronized, so make sure
599 * we get a low value that's stable across two reads of the high
600 * register.
601 */
602 do {
5eddb70b 603 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 604 low = I915_READ(low_frame);
5eddb70b 605 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 606 } while (high1 != high2);
607
5eddb70b 608 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 609 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 610 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 611
612 /*
613 * The frame counter increments at beginning of active.
614 * Cook up a vblank counter by also checking the pixel
615 * counter against vblank start.
616 */
edc08d0a 617 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 618}
619
f71d4af4 620static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 621{
622 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 623 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 624
625 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 626 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 627 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 628 return 0;
629 }
630
631 return I915_READ(reg);
632}
633
ad3543ed
MK		 634/* raw reads, only for fast reads of display block, no need for forcewake etc. */
635#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
636#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
637
095163ba 638static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 639{
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 uint32_t status;
642
095163ba 643 if (INTEL_INFO(dev)->gen < 7) {
54ddcbd2
VS		 644 status = pipe == PIPE_A ?
645 DE_PIPEA_VBLANK :
646 DE_PIPEB_VBLANK;
54ddcbd2
VS		 647 } else {
648 switch (pipe) {
649 default:
650 case PIPE_A:
651 status = DE_PIPEA_VBLANK_IVB;
652 break;
653 case PIPE_B:
654 status = DE_PIPEB_VBLANK_IVB;
655 break;
656 case PIPE_C:
657 status = DE_PIPEC_VBLANK_IVB;
658 break;
659 }
54ddcbd2 660 }
ad3543ed 661
095163ba 662 return __raw_i915_read32(dev_priv, DEISR) & status;
54ddcbd2
VS		 663}
664
f71d4af4 665static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 666 unsigned int flags, int *vpos, int *hpos,
667 ktime_t *stime, ktime_t *etime)
0af7e4df 668{
c2baf4b7
VS		 669 struct drm_i915_private *dev_priv = dev->dev_private;
670 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
672 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 673 int position;
0af7e4df
MK		 674 int vbl_start, vbl_end, htotal, vtotal;
675 bool in_vbl = true;
676 int ret = 0;
ad3543ed 677 unsigned long irqflags;
0af7e4df 678
c2baf4b7 679 if (!intel_crtc->active) {
0af7e4df 680 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 681 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 682 return 0;
683 }
684
c2baf4b7
VS		 685 htotal = mode->crtc_htotal;
686 vtotal = mode->crtc_vtotal;
687 vbl_start = mode->crtc_vblank_start;
688 vbl_end = mode->crtc_vblank_end;
0af7e4df 689
d31faf65
VS		 690 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
691 vbl_start = DIV_ROUND_UP(vbl_start, 2);
692 vbl_end /= 2;
693 vtotal /= 2;
694 }
695
c2baf4b7
VS		 696 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
697
ad3543ed
MK		 698 /*
699 * Lock uncore.lock, as we will do multiple timing critical raw
700 * register reads, potentially with preemption disabled, so the
701 * following code must not block on uncore.lock.
702 */
703 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
704
705 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
706
707 /* Get optional system timestamp before query. */
708 if (stime)
709 *stime = ktime_get();
710
7c06b08a 711 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 712 /* No obvious pixelcount register. Only query vertical
713 * scanout position from Display scan line register.
714 */
7c06b08a 715 if (IS_GEN2(dev))
ad3543ed 716 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
7c06b08a 717 else
ad3543ed 718 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2 719
095163ba
VS		 720 if (HAS_PCH_SPLIT(dev)) {
721 /*
722 * The scanline counter increments at the leading edge
723 * of hsync, ie. it completely misses the active portion
724 * of the line. Fix up the counter at both edges of vblank
725 * to get a more accurate picture whether we're in vblank
726 * or not.
727 */
728 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
729 if ((in_vbl && position == vbl_start - 1) ||
730 (!in_vbl && position == vbl_end - 1))
731 position = (position + 1) % vtotal;
732 } else {
733 /*
734 * ISR vblank status bits don't work the way we'd want
735 * them to work on non-PCH platforms (for
736 * ilk_pipe_in_vblank_locked()), and there doesn't
737 * appear any other way to determine if we're currently
738 * in vblank.
739 *
740 * Instead let's assume that we're already in vblank if
741 * we got called from the vblank interrupt and the
742 * scanline counter value indicates that we're on the
743 * line just prior to vblank start. This should result
744 * in the correct answer, unless the vblank interrupt
745 * delivery really got delayed for almost exactly one
746 * full frame/field.
747 */
748 if (flags & DRM_CALLED_FROM_VBLIRQ &&
749 position == vbl_start - 1) {
750 position = (position + 1) % vtotal;
751
752 /* Signal this correction as "applied". */
753 ret |= 0x8;
754 }
755 }
0af7e4df
MK		 756 } else {
757 /* Have access to pixelcount since start of frame.
758 * We can split this into vertical and horizontal
759 * scanout position.
760 */
ad3543ed 761 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 762
3aa18df8
VS		 763 /* convert to pixel counts */
764 vbl_start *= htotal;
765 vbl_end *= htotal;
766 vtotal *= htotal;
0af7e4df
MK		 767 }
768
ad3543ed
MK		 769 /* Get optional system timestamp after query. */
770 if (etime)
771 *etime = ktime_get();
772
773 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
774
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
3aa18df8
VS		 777 in_vbl = position >= vbl_start && position < vbl_end;
778
779 /*
780 * While in vblank, position will be negative
781 * counting up towards 0 at vbl_end. And outside
782 * vblank, position will be positive counting
783 * up since vbl_end.
784 */
785 if (position >= vbl_start)
786 position -= vbl_end;
787 else
788 position += vtotal - vbl_end;
0af7e4df 789
7c06b08a 790 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 791 *vpos = position;
792 *hpos = 0;
793 } else {
794 *vpos = position / htotal;
795 *hpos = position - (*vpos * htotal);
796 }
0af7e4df 797
0af7e4df
MK		 798 /* In vblank? */
799 if (in_vbl)
800 ret |= DRM_SCANOUTPOS_INVBL;
801
802 return ret;
803}
804
f71d4af4 805static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 806 int *max_error,
807 struct timeval *vblank_time,
808 unsigned flags)
809{
4041b853 810 struct drm_crtc *crtc;
0af7e4df 811
7eb552ae 812 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 813 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 814 return -EINVAL;
815 }
816
817 /* Get drm_crtc to timestamp: */
4041b853
CW		 818 crtc = intel_get_crtc_for_pipe(dev, pipe);
819 if (crtc == NULL) {
820 DRM_ERROR("Invalid crtc %d\n", pipe);
821 return -EINVAL;
822 }
823
824 if (!crtc->enabled) {
825 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
826 return -EBUSY;
827 }
0af7e4df
MK		 828
829 /* Helper routine in DRM core does all the work: */
4041b853
CW		 830 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
831 vblank_time, flags,
7da903ef
VS		 832 crtc,
833 &to_intel_crtc(crtc)->config.adjusted_mode);
0af7e4df
MK		 834}
835
67c347ff
JN		 836static bool intel_hpd_irq_event(struct drm_device *dev,
837 struct drm_connector *connector)
321a1b30
EE		 838{
839 enum drm_connector_status old_status;
840
841 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
842 old_status = connector->status;
843
844 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 845 if (old_status == connector->status)
846 return false;
847
848 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 849 connector->base.id,
850 drm_get_connector_name(connector),
67c347ff
JN		 851 drm_get_connector_status_name(old_status),
852 drm_get_connector_status_name(connector->status));
853
854 return true;
321a1b30
EE		 855}
856
5ca58282
JB		 857/*
858 * Handle hotplug events outside the interrupt handler proper.
859 */
ac4c16c5
EE		 860#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
861
5ca58282
JB		 862static void i915_hotplug_work_func(struct work_struct *work)
863{
864 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
865 hotplug_work);
866 struct drm_device *dev = dev_priv->dev;
c31c4ba3 867 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 868 struct intel_connector *intel_connector;
869 struct intel_encoder *intel_encoder;
870 struct drm_connector *connector;
871 unsigned long irqflags;
872 bool hpd_disabled = false;
321a1b30 873 bool changed = false;
142e2398 874 u32 hpd_event_bits;
4ef69c7a 875
52d7eced
DV		 876 /* HPD irq before everything is fully set up. */
877 if (!dev_priv->enable_hotplug_processing)
878 return;
879
a65e34c7 880 mutex_lock(&mode_config->mutex);
e67189ab
JB		 881 DRM_DEBUG_KMS("running encoder hotplug functions\n");
882
cd569aed 883 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 884
885 hpd_event_bits = dev_priv->hpd_event_bits;
886 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 887 list_for_each_entry(connector, &mode_config->connector_list, head) {
888 intel_connector = to_intel_connector(connector);
889 intel_encoder = intel_connector->encoder;
890 if (intel_encoder->hpd_pin > HPD_NONE &&
891 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
892 connector->polled == DRM_CONNECTOR_POLL_HPD) {
893 DRM_INFO("HPD interrupt storm detected on connector %s: "
894 "switching from hotplug detection to polling\n",
895 drm_get_connector_name(connector));
896 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
897 connector->polled = DRM_CONNECTOR_POLL_CONNECT
898 | DRM_CONNECTOR_POLL_DISCONNECT;
899 hpd_disabled = true;
900 }
142e2398
EE		 901 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
902 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
903 drm_get_connector_name(connector), intel_encoder->hpd_pin);
904 }
cd569aed
EE		 905 }
906 /* if there were no outputs to poll, poll was disabled,
907 * therefore make sure it's enabled when disabling HPD on
908 * some connectors */
ac4c16c5 909 if (hpd_disabled) {
cd569aed 910 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 911 mod_timer(&dev_priv->hotplug_reenable_timer,
912 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
913 }
cd569aed
EE		 914
915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
916
321a1b30
EE		 917 list_for_each_entry(connector, &mode_config->connector_list, head) {
918 intel_connector = to_intel_connector(connector);
919 intel_encoder = intel_connector->encoder;
920 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
921 if (intel_encoder->hot_plug)
922 intel_encoder->hot_plug(intel_encoder);
923 if (intel_hpd_irq_event(dev, connector))
924 changed = true;
925 }
926 }
40ee3381
KP		 927 mutex_unlock(&mode_config->mutex);
928
321a1b30
EE		 929 if (changed)
930 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 931}
932
3ca1cced
VS		 933static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
934{
935 del_timer_sync(&dev_priv->hotplug_reenable_timer);
936}
937
d0ecd7e2 938static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 939{
940 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 941 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 942 u8 new_delay;
9270388e 943
d0ecd7e2 944 spin_lock(&mchdev_lock);
f97108d1 945
73edd18f
DV		 946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
947
20e4d407 948 new_delay = dev_priv->ips.cur_delay;
9270388e 949
7648fa99 950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
955
956 /* Handle RCS change request from hw */
b5b72e89 957 if (busy_up > max_avg) {
20e4d407
DV		 958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
b5b72e89 962 } else if (busy_down < min_avg) {
20e4d407
DV		 963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 967 }
968
7648fa99 969 if (ironlake_set_drps(dev, new_delay))
20e4d407 970 dev_priv->ips.cur_delay = new_delay;
f97108d1 971
d0ecd7e2 972 spin_unlock(&mchdev_lock);
9270388e 973
f97108d1
JB		 974 return;
975}
976
549f7365
CW		 977static void notify_ring(struct drm_device *dev,
978 struct intel_ring_buffer *ring)
979{
475553de
CW		 980 if (ring->obj == NULL)
981 return;
982
814e9b57 983 trace_i915_gem_request_complete(ring);
9862e600 984
549f7365 985 wake_up_all(&ring->irq_queue);
10cd45b6 986 i915_queue_hangcheck(dev);
549f7365
CW		 987}
988
4912d041 989static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 990{
4912d041 991 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 992 rps.work);
edbfdb45 993 u32 pm_iir;
dd75fdc8 994 int new_delay, adj;
4912d041 995
59cdb63d 996 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 997 pm_iir = dev_priv->rps.pm_iir;
998 dev_priv->rps.pm_iir = 0;
4848405c 999 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 1000 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 1001 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1002
60611c13
PZ		 1003 /* Make sure we didn't queue anything we're not going to process. */
1004 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1005
4848405c 1006 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 1007 return;
1008
4fc688ce 1009 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1010
dd75fdc8 1011 adj = dev_priv->rps.last_adj;
7425034a 1012 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1013 if (adj > 0)
1014 adj *= 2;
1015 else
1016 adj = 1;
1017 new_delay = dev_priv->rps.cur_delay + adj;
7425034a
VS		 1018
1019 /*
1020 * For better performance, jump directly
1021 * to RPe if we're below it.
1022 */
dd75fdc8
CW		 1023 if (new_delay < dev_priv->rps.rpe_delay)
1024 new_delay = dev_priv->rps.rpe_delay;
1025 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1026 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
7425034a 1027 new_delay = dev_priv->rps.rpe_delay;
dd75fdc8
CW		 1028 else
1029 new_delay = dev_priv->rps.min_delay;
1030 adj = 0;
1031 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1032 if (adj < 0)
1033 adj *= 2;
1034 else
1035 adj = -1;
1036 new_delay = dev_priv->rps.cur_delay + adj;
1037 } else { /* unknown event */
1038 new_delay = dev_priv->rps.cur_delay;
1039 }
3b8d8d91 1040
79249636
BW		 1041 /* sysfs frequency interfaces may have snuck in while servicing the
1042 * interrupt
1043 */
1272e7b8
VS		 1044 new_delay = clamp_t(int, new_delay,
1045 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
dd75fdc8
CW		 1046 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1047
1048 if (IS_VALLEYVIEW(dev_priv->dev))
1049 valleyview_set_rps(dev_priv->dev, new_delay);
1050 else
1051 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1052
4fc688ce 1053 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1054}
1055
e3689190
BW		 1056
1057/**
1058 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1059 * occurred.
1060 * @work: workqueue struct
1061 *
1062 * Doesn't actually do anything except notify userspace. As a consequence of
1063 * this event, userspace should try to remap the bad rows since statistically
1064 * it is likely the same row is more likely to go bad again.
1065 */
1066static void ivybridge_parity_work(struct work_struct *work)
1067{
1068 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 1069 l3_parity.error_work);
e3689190 1070 u32 error_status, row, bank, subbank;
35a85ac6 1071 char *parity_event[6];
e3689190
BW		 1072 uint32_t misccpctl;
1073 unsigned long flags;
35a85ac6 1074 uint8_t slice = 0;
e3689190
BW		 1075
1076 /* We must turn off DOP level clock gating to access the L3 registers.
1077 * In order to prevent a get/put style interface, acquire struct mutex
1078 * any time we access those registers.
1079 */
1080 mutex_lock(&dev_priv->dev->struct_mutex);
1081
35a85ac6
BW		 1082 /* If we've screwed up tracking, just let the interrupt fire again */
1083 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1084 goto out;
1085
e3689190
BW		 1086 misccpctl = I915_READ(GEN7_MISCCPCTL);
1087 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1088 POSTING_READ(GEN7_MISCCPCTL);
1089
35a85ac6
BW		 1090 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1091 u32 reg;
e3689190 1092
35a85ac6
BW		 1093 slice--;
1094 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1095 break;
e3689190 1096
35a85ac6 1097 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1098
35a85ac6 1099 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1100
35a85ac6
BW		 1101 error_status = I915_READ(reg);
1102 row = GEN7_PARITY_ERROR_ROW(error_status);
1103 bank = GEN7_PARITY_ERROR_BANK(error_status);
1104 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1105
1106 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1107 POSTING_READ(reg);
1108
1109 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1110 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1111 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1112 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1113 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1114 parity_event[5] = NULL;
1115
5bdebb18 1116 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1117 KOBJ_CHANGE, parity_event);
e3689190 1118
35a85ac6
BW		 1119 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1120 slice, row, bank, subbank);
e3689190 1121
35a85ac6
BW		 1122 kfree(parity_event[4]);
1123 kfree(parity_event[3]);
1124 kfree(parity_event[2]);
1125 kfree(parity_event[1]);
1126 }
e3689190 1127
35a85ac6 1128 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1129
35a85ac6
BW		 1130out:
1131 WARN_ON(dev_priv->l3_parity.which_slice);
1132 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1133 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1134 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1135
1136 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1137}
1138
35a85ac6 1139static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190
BW		 1140{
1141 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 1142
040d2baa 1143 if (!HAS_L3_DPF(dev))
e3689190
BW		 1144 return;
1145
d0ecd7e2 1146 spin_lock(&dev_priv->irq_lock);
35a85ac6 1147 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1148 spin_unlock(&dev_priv->irq_lock);
e3689190 1149
35a85ac6
BW		 1150 iir &= GT_PARITY_ERROR(dev);
1151 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1152 dev_priv->l3_parity.which_slice |= 1 << 1;
1153
1154 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1155 dev_priv->l3_parity.which_slice |= 1 << 0;
1156
a4da4fa4 1157 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1158}
1159
f1af8fc1
PZ		 1160static void ilk_gt_irq_handler(struct drm_device *dev,
1161 struct drm_i915_private *dev_priv,
1162 u32 gt_iir)
1163{
1164 if (gt_iir &
1165 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1166 notify_ring(dev, &dev_priv->ring[RCS]);
1167 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1168 notify_ring(dev, &dev_priv->ring[VCS]);
1169}
1170
e7b4c6b1
DV		 1171static void snb_gt_irq_handler(struct drm_device *dev,
1172 struct drm_i915_private *dev_priv,
1173 u32 gt_iir)
1174{
1175
cc609d5d
BW		 1176 if (gt_iir &
1177 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1178 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1179 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1180 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1181 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1182 notify_ring(dev, &dev_priv->ring[BCS]);
1183
cc609d5d
BW		 1184 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1185 GT_BSD_CS_ERROR_INTERRUPT |
1186 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 1187 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1188 i915_handle_error(dev, false);
1189 }
e3689190 1190
35a85ac6
BW		 1191 if (gt_iir & GT_PARITY_ERROR(dev))
1192 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1193}
1194
abd58f01
BW		 1195static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1196 struct drm_i915_private *dev_priv,
1197 u32 master_ctl)
1198{
1199 u32 rcs, bcs, vcs;
1200 uint32_t tmp = 0;
1201 irqreturn_t ret = IRQ_NONE;
1202
1203 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1204 tmp = I915_READ(GEN8_GT_IIR(0));
1205 if (tmp) {
1206 ret = IRQ_HANDLED;
1207 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1208 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1209 if (rcs & GT_RENDER_USER_INTERRUPT)
1210 notify_ring(dev, &dev_priv->ring[RCS]);
1211 if (bcs & GT_RENDER_USER_INTERRUPT)
1212 notify_ring(dev, &dev_priv->ring[BCS]);
1213 I915_WRITE(GEN8_GT_IIR(0), tmp);
1214 } else
1215 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1216 }
1217
1218 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1219 tmp = I915_READ(GEN8_GT_IIR(1));
1220 if (tmp) {
1221 ret = IRQ_HANDLED;
1222 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1223 if (vcs & GT_RENDER_USER_INTERRUPT)
1224 notify_ring(dev, &dev_priv->ring[VCS]);
1225 I915_WRITE(GEN8_GT_IIR(1), tmp);
1226 } else
1227 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1228 }
1229
1230 if (master_ctl & GEN8_GT_VECS_IRQ) {
1231 tmp = I915_READ(GEN8_GT_IIR(3));
1232 if (tmp) {
1233 ret = IRQ_HANDLED;
1234 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1235 if (vcs & GT_RENDER_USER_INTERRUPT)
1236 notify_ring(dev, &dev_priv->ring[VECS]);
1237 I915_WRITE(GEN8_GT_IIR(3), tmp);
1238 } else
1239 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1240 }
1241
1242 return ret;
1243}
1244
b543fb04
EE		 1245#define HPD_STORM_DETECT_PERIOD 1000
1246#define HPD_STORM_THRESHOLD 5
1247
10a504de 1248static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1249 u32 hotplug_trigger,
1250 const u32 *hpd)
b543fb04
EE		 1251{
1252 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 1253 int i;
10a504de 1254 bool storm_detected = false;
b543fb04 1255
91d131d2
DV		 1256 if (!hotplug_trigger)
1257 return;
1258
cc9bd499
ID		 1259 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1260 hotplug_trigger);
1261
b5ea2d56 1262 spin_lock(&dev_priv->irq_lock);
b543fb04 1263 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1264
3432087e 1265 WARN_ONCE(hpd[i] & hotplug_trigger &&
8b5565b8 1266 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
cba1c073
CW		 1267 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1268 hotplug_trigger, i, hpd[i]);
b8f102e8 1269
b543fb04
EE		 1270 if (!(hpd[i] & hotplug_trigger) ||
1271 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1272 continue;
1273
bc5ead8c 1274 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1275 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1276 dev_priv->hpd_stats[i].hpd_last_jiffies
1277 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1278 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1279 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1280 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1281 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1282 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1283 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1284 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1285 storm_detected = true;
b543fb04
EE		 1286 } else {
1287 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1288 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1289 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1290 }
1291 }
1292
10a504de
DV		 1293 if (storm_detected)
1294 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1295 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1296
645416f5
DV		 1297 /*
1298 * Our hotplug handler can grab modeset locks (by calling down into the
1299 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1300 * queue for otherwise the flush_work in the pageflip code will
1301 * deadlock.
1302 */
1303 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1304}
1305
515ac2bb
DV		 1306static void gmbus_irq_handler(struct drm_device *dev)
1307{
28c70f16
DV		 1308 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1309
28c70f16 1310 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1311}
1312
ce99c256
DV		 1313static void dp_aux_irq_handler(struct drm_device *dev)
1314{
9ee32fea
DV		 1315 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1316
9ee32fea 1317 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1318}
1319
8bf1e9f1 1320#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1321static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1322 uint32_t crc0, uint32_t crc1,
1323 uint32_t crc2, uint32_t crc3,
1324 uint32_t crc4)
8bf1e9f1
SH		 1325{
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1328 struct intel_pipe_crc_entry *entry;
ac2300d4 1329 int head, tail;
b2c88f5b 1330
d538bbdf
DL		 1331 spin_lock(&pipe_crc->lock);
1332
0c912c79 1333 if (!pipe_crc->entries) {
d538bbdf 1334 spin_unlock(&pipe_crc->lock);
0c912c79
DL		 1335 DRM_ERROR("spurious interrupt\n");
1336 return;
1337 }
1338
d538bbdf
DL		 1339 head = pipe_crc->head;
1340 tail = pipe_crc->tail;
b2c88f5b
DL		 1341
1342 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1343 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1344 DRM_ERROR("CRC buffer overflowing\n");
1345 return;
1346 }
1347
1348 entry = &pipe_crc->entries[head];
8bf1e9f1 1349
8bc5e955 1350 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1351 entry->crc[0] = crc0;
1352 entry->crc[1] = crc1;
1353 entry->crc[2] = crc2;
1354 entry->crc[3] = crc3;
1355 entry->crc[4] = crc4;
b2c88f5b
DL		 1356
1357 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1358 pipe_crc->head = head;
1359
1360 spin_unlock(&pipe_crc->lock);
07144428
DL		 1361
1362 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1363}
277de95e
DV		 1364#else
1365static inline void
1366display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1367 uint32_t crc0, uint32_t crc1,
1368 uint32_t crc2, uint32_t crc3,
1369 uint32_t crc4) {}
1370#endif
1371
eba94eb9 1372
277de95e 1373static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1374{
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376
277de95e
DV		 1377 display_pipe_crc_irq_handler(dev, pipe,
1378 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1379 0, 0, 0, 0);
5a69b89f
DV		 1380}
1381
277de95e 1382static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1383{
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385
277de95e
DV		 1386 display_pipe_crc_irq_handler(dev, pipe,
1387 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1388 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1389 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1390 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1391 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1392}
5b3a856b 1393
277de95e 1394static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1395{
1396 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1397 uint32_t res1, res2;
1398
1399 if (INTEL_INFO(dev)->gen >= 3)
1400 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1401 else
1402 res1 = 0;
1403
1404 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1405 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1406 else
1407 res2 = 0;
5b3a856b 1408
277de95e
DV		 1409 display_pipe_crc_irq_handler(dev, pipe,
1410 I915_READ(PIPE_CRC_RES_RED(pipe)),
1411 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1412 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1413 res1, res2);
5b3a856b 1414}
8bf1e9f1 1415
1403c0d4
PZ		 1416/* The RPS events need forcewake, so we add them to a work queue and mask their
1417 * IMR bits until the work is done. Other interrupts can be processed without
1418 * the work queue. */
1419static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1420{
41a05a3a 1421 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1422 spin_lock(&dev_priv->irq_lock);
41a05a3a 1423 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
4d3b3d5f 1424 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
59cdb63d 1425 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1426
1427 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1428 }
baf02a1f 1429
1403c0d4
PZ		 1430 if (HAS_VEBOX(dev_priv->dev)) {
1431 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1432 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1433
1403c0d4
PZ		 1434 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1435 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1436 i915_handle_error(dev_priv->dev, false);
1437 }
12638c57 1438 }
baf02a1f
BW		 1439}
1440
ff1f525e 1441static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1442{
1443 struct drm_device *dev = (struct drm_device *) arg;
1444 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1445 u32 iir, gt_iir, pm_iir;
1446 irqreturn_t ret = IRQ_NONE;
1447 unsigned long irqflags;
1448 int pipe;
1449 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe 1450
7e231dbe
JB		 1451 while (true) {
1452 iir = I915_READ(VLV_IIR);
1453 gt_iir = I915_READ(GTIIR);
1454 pm_iir = I915_READ(GEN6_PMIIR);
1455
1456 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1457 goto out;
1458
1459 ret = IRQ_HANDLED;
1460
e7b4c6b1 1461 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1462
1463 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1464 for_each_pipe(pipe) {
1465 int reg = PIPESTAT(pipe);
1466 pipe_stats[pipe] = I915_READ(reg);
1467
1468 /*
1469 * Clear the PIPE*STAT regs before the IIR
1470 */
2d9d2b0b 1471 if (pipe_stats[pipe] & 0x8000ffff)
7e231dbe 1472 I915_WRITE(reg, pipe_stats[pipe]);
7e231dbe
JB		 1473 }
1474 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1475
31acc7f5 1476 for_each_pipe(pipe) {
7b5562d4 1477 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
31acc7f5
JB		 1478 drm_handle_vblank(dev, pipe);
1479
1480 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1481 intel_prepare_page_flip(dev, pipe);
1482 intel_finish_page_flip(dev, pipe);
1483 }
4356d586
DV		 1484
1485 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 1486 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 1487
1488 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1489 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1490 DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
31acc7f5
JB		 1491 }
1492
7e231dbe
JB		 1493 /* Consume port. Then clear IIR or we'll miss events */
1494 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1495 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1496 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe 1497
91d131d2
DV		 1498 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1499
4aeebd74
DV		 1500 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1501 dp_aux_irq_handler(dev);
1502
7e231dbe
JB		 1503 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1504 I915_READ(PORT_HOTPLUG_STAT);
1505 }
1506
515ac2bb
DV		 1507 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1508 gmbus_irq_handler(dev);
7e231dbe 1509
60611c13 1510 if (pm_iir)
d0ecd7e2 1511 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1512
1513 I915_WRITE(GTIIR, gt_iir);
1514 I915_WRITE(GEN6_PMIIR, pm_iir);
1515 I915_WRITE(VLV_IIR, iir);
1516 }
1517
1518out:
1519 return ret;
1520}
1521
23e81d69 1522static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1523{
1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1525 int pipe;
b543fb04 1526 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1527
91d131d2
DV		 1528 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1529
cfc33bf7
VS		 1530 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1531 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1532 SDE_AUDIO_POWER_SHIFT);
776ad806 1533 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1534 port_name(port));
1535 }
776ad806 1536
ce99c256
DV		 1537 if (pch_iir & SDE_AUX_MASK)
1538 dp_aux_irq_handler(dev);
1539
776ad806 1540 if (pch_iir & SDE_GMBUS)
515ac2bb 1541 gmbus_irq_handler(dev);
776ad806
JB		 1542
1543 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1544 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1545
1546 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1547 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1548
1549 if (pch_iir & SDE_POISON)
1550 DRM_ERROR("PCH poison interrupt\n");
1551
9db4a9c7
JB		 1552 if (pch_iir & SDE_FDI_MASK)
1553 for_each_pipe(pipe)
1554 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1555 pipe_name(pipe),
1556 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1557
1558 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1559 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1560
1561 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1562 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1563
776ad806 1564 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1565 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1566 false))
1567 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1568
1569 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1570 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1571 false))
1572 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1573}
1574
1575static void ivb_err_int_handler(struct drm_device *dev)
1576{
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1579 enum pipe pipe;
8664281b 1580
de032bf4
PZ		 1581 if (err_int & ERR_INT_POISON)
1582 DRM_ERROR("Poison interrupt\n");
1583
5a69b89f
DV		 1584 for_each_pipe(pipe) {
1585 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1586 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1587 false))
1588 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1589 pipe_name(pipe));
1590 }
8bf1e9f1 1591
5a69b89f
DV		 1592 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1593 if (IS_IVYBRIDGE(dev))
277de95e 1594 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1595 else
277de95e 1596 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1597 }
1598 }
8bf1e9f1 1599
8664281b
PZ		 1600 I915_WRITE(GEN7_ERR_INT, err_int);
1601}
1602
1603static void cpt_serr_int_handler(struct drm_device *dev)
1604{
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606 u32 serr_int = I915_READ(SERR_INT);
1607
de032bf4
PZ		 1608 if (serr_int & SERR_INT_POISON)
1609 DRM_ERROR("PCH poison interrupt\n");
1610
8664281b
PZ		 1611 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1612 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1613 false))
1614 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1615
1616 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1617 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1618 false))
1619 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1620
1621 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1622 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1623 false))
1624 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1625
1626 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1627}
1628
23e81d69
AJ		 1629static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1630{
1631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1632 int pipe;
b543fb04 1633 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1634
91d131d2
DV		 1635 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1636
cfc33bf7
VS		 1637 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1638 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1639 SDE_AUDIO_POWER_SHIFT_CPT);
1640 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1641 port_name(port));
1642 }
23e81d69
AJ		 1643
1644 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1645 dp_aux_irq_handler(dev);
23e81d69
AJ		 1646
1647 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1648 gmbus_irq_handler(dev);
23e81d69
AJ		 1649
1650 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1651 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1652
1653 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1654 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1655
1656 if (pch_iir & SDE_FDI_MASK_CPT)
1657 for_each_pipe(pipe)
1658 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1659 pipe_name(pipe),
1660 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1661
1662 if (pch_iir & SDE_ERROR_CPT)
1663 cpt_serr_int_handler(dev);
23e81d69
AJ		 1664}
1665
c008bc6e
PZ		 1666static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1667{
1668 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 1669 enum pipe pipe;
c008bc6e
PZ		 1670
1671 if (de_iir & DE_AUX_CHANNEL_A)
1672 dp_aux_irq_handler(dev);
1673
1674 if (de_iir & DE_GSE)
1675 intel_opregion_asle_intr(dev);
1676
c008bc6e
PZ		 1677 if (de_iir & DE_POISON)
1678 DRM_ERROR("Poison interrupt\n");
1679
40da17c2
DV		 1680 for_each_pipe(pipe) {
1681 if (de_iir & DE_PIPE_VBLANK(pipe))
1682 drm_handle_vblank(dev, pipe);
5b3a856b 1683
40da17c2
DV		 1684 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1685 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1686 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1687 pipe_name(pipe));
5b3a856b 1688
40da17c2
DV		 1689 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1690 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 1691
40da17c2
DV		 1692 /* plane/pipes map 1:1 on ilk+ */
1693 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1694 intel_prepare_page_flip(dev, pipe);
1695 intel_finish_page_flip_plane(dev, pipe);
1696 }
c008bc6e
PZ		 1697 }
1698
1699 /* check event from PCH */
1700 if (de_iir & DE_PCH_EVENT) {
1701 u32 pch_iir = I915_READ(SDEIIR);
1702
1703 if (HAS_PCH_CPT(dev))
1704 cpt_irq_handler(dev, pch_iir);
1705 else
1706 ibx_irq_handler(dev, pch_iir);
1707
1708 /* should clear PCH hotplug event before clear CPU irq */
1709 I915_WRITE(SDEIIR, pch_iir);
1710 }
1711
1712 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1713 ironlake_rps_change_irq_handler(dev);
1714}
1715
9719fb98
PZ		 1716static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1717{
1718 struct drm_i915_private *dev_priv = dev->dev_private;
3b6c42e8 1719 enum pipe i;
9719fb98
PZ		 1720
1721 if (de_iir & DE_ERR_INT_IVB)
1722 ivb_err_int_handler(dev);
1723
1724 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1725 dp_aux_irq_handler(dev);
1726
1727 if (de_iir & DE_GSE_IVB)
1728 intel_opregion_asle_intr(dev);
1729
3b6c42e8 1730 for_each_pipe(i) {
40da17c2 1731 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
9719fb98 1732 drm_handle_vblank(dev, i);
40da17c2
DV		 1733
1734 /* plane/pipes map 1:1 on ilk+ */
1735 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
9719fb98
PZ		 1736 intel_prepare_page_flip(dev, i);
1737 intel_finish_page_flip_plane(dev, i);
1738 }
1739 }
1740
1741 /* check event from PCH */
1742 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1743 u32 pch_iir = I915_READ(SDEIIR);
1744
1745 cpt_irq_handler(dev, pch_iir);
1746
1747 /* clear PCH hotplug event before clear CPU irq */
1748 I915_WRITE(SDEIIR, pch_iir);
1749 }
1750}
1751
f1af8fc1 1752static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1753{
1754 struct drm_device *dev = (struct drm_device *) arg;
1755 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1756 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1757 irqreturn_t ret = IRQ_NONE;
b1f14ad0 1758
8664281b
PZ		 1759 /* We get interrupts on unclaimed registers, so check for this before we
1760 * do any I915_{READ,WRITE}. */
907b28c5 1761 intel_uncore_check_errors(dev);
8664281b 1762
b1f14ad0
JB		 1763 /* disable master interrupt before clearing iir */
1764 de_ier = I915_READ(DEIER);
1765 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1766 POSTING_READ(DEIER);
b1f14ad0 1767
44498aea
PZ		 1768 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1769 * interrupts will will be stored on its back queue, and then we'll be
1770 * able to process them after we restore SDEIER (as soon as we restore
1771 * it, we'll get an interrupt if SDEIIR still has something to process
1772 * due to its back queue). */
ab5c608b
BW		 1773 if (!HAS_PCH_NOP(dev)) {
1774 sde_ier = I915_READ(SDEIER);
1775 I915_WRITE(SDEIER, 0);
1776 POSTING_READ(SDEIER);
1777 }
44498aea 1778
b1f14ad0 1779 gt_iir = I915_READ(GTIIR);
0e43406b 1780 if (gt_iir) {
d8fc8a47 1781 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1782 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1783 else
1784 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1785 I915_WRITE(GTIIR, gt_iir);
1786 ret = IRQ_HANDLED;
b1f14ad0
JB		 1787 }
1788
0e43406b
CW		 1789 de_iir = I915_READ(DEIIR);
1790 if (de_iir) {
f1af8fc1
PZ		 1791 if (INTEL_INFO(dev)->gen >= 7)
1792 ivb_display_irq_handler(dev, de_iir);
1793 else
1794 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1795 I915_WRITE(DEIIR, de_iir);
1796 ret = IRQ_HANDLED;
b1f14ad0
JB		 1797 }
1798
f1af8fc1
PZ		 1799 if (INTEL_INFO(dev)->gen >= 6) {
1800 u32 pm_iir = I915_READ(GEN6_PMIIR);
1801 if (pm_iir) {
1403c0d4 1802 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 1803 I915_WRITE(GEN6_PMIIR, pm_iir);
1804 ret = IRQ_HANDLED;
1805 }
0e43406b 1806 }
b1f14ad0 1807
b1f14ad0
JB		 1808 I915_WRITE(DEIER, de_ier);
1809 POSTING_READ(DEIER);
ab5c608b
BW		 1810 if (!HAS_PCH_NOP(dev)) {
1811 I915_WRITE(SDEIER, sde_ier);
1812 POSTING_READ(SDEIER);
1813 }
b1f14ad0
JB		 1814
1815 return ret;
1816}
1817
abd58f01
BW		 1818static irqreturn_t gen8_irq_handler(int irq, void *arg)
1819{
1820 struct drm_device *dev = arg;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 u32 master_ctl;
1823 irqreturn_t ret = IRQ_NONE;
1824 uint32_t tmp = 0;
c42664cc 1825 enum pipe pipe;
abd58f01 1826
abd58f01
BW		 1827 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1828 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1829 if (!master_ctl)
1830 return IRQ_NONE;
1831
1832 I915_WRITE(GEN8_MASTER_IRQ, 0);
1833 POSTING_READ(GEN8_MASTER_IRQ);
1834
1835 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1836
1837 if (master_ctl & GEN8_DE_MISC_IRQ) {
1838 tmp = I915_READ(GEN8_DE_MISC_IIR);
1839 if (tmp & GEN8_DE_MISC_GSE)
1840 intel_opregion_asle_intr(dev);
1841 else if (tmp)
1842 DRM_ERROR("Unexpected DE Misc interrupt\n");
1843 else
1844 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1845
1846 if (tmp) {
1847 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1848 ret = IRQ_HANDLED;
1849 }
1850 }
1851
6d766f02
DV		 1852 if (master_ctl & GEN8_DE_PORT_IRQ) {
1853 tmp = I915_READ(GEN8_DE_PORT_IIR);
1854 if (tmp & GEN8_AUX_CHANNEL_A)
1855 dp_aux_irq_handler(dev);
1856 else if (tmp)
1857 DRM_ERROR("Unexpected DE Port interrupt\n");
1858 else
1859 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1860
1861 if (tmp) {
1862 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1863 ret = IRQ_HANDLED;
1864 }
1865 }
1866
c42664cc
DV		 1867 for_each_pipe(pipe) {
1868 uint32_t pipe_iir;
abd58f01 1869
c42664cc
DV		 1870 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1871 continue;
abd58f01 1872
c42664cc
DV		 1873 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1874 if (pipe_iir & GEN8_PIPE_VBLANK)
1875 drm_handle_vblank(dev, pipe);
abd58f01 1876
c42664cc
DV		 1877 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1878 intel_prepare_page_flip(dev, pipe);
1879 intel_finish_page_flip_plane(dev, pipe);
abd58f01 1880 }
c42664cc 1881
0fbe7870
DV		 1882 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1883 hsw_pipe_crc_irq_handler(dev, pipe);
1884
38d83c96
DV		 1885 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1886 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1887 false))
1888 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1889 pipe_name(pipe));
1890 }
1891
30100f2b
DV		 1892 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1893 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1894 pipe_name(pipe),
1895 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1896 }
c42664cc
DV		 1897
1898 if (pipe_iir) {
1899 ret = IRQ_HANDLED;
1900 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1901 } else
abd58f01
BW		 1902 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1903 }
1904
92d03a80
DV		 1905 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1906 /*
1907 * FIXME(BDW): Assume for now that the new interrupt handling
1908 * scheme also closed the SDE interrupt handling race we've seen
1909 * on older pch-split platforms. But this needs testing.
1910 */
1911 u32 pch_iir = I915_READ(SDEIIR);
1912
1913 cpt_irq_handler(dev, pch_iir);
1914
1915 if (pch_iir) {
1916 I915_WRITE(SDEIIR, pch_iir);
1917 ret = IRQ_HANDLED;
1918 }
1919 }
1920
abd58f01
BW		 1921 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1922 POSTING_READ(GEN8_MASTER_IRQ);
1923
1924 return ret;
1925}
1926
17e1df07
DV		 1927static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1928 bool reset_completed)
1929{
1930 struct intel_ring_buffer *ring;
1931 int i;
1932
1933 /*
1934 * Notify all waiters for GPU completion events that reset state has
1935 * been changed, and that they need to restart their wait after
1936 * checking for potential errors (and bail out to drop locks if there is
1937 * a gpu reset pending so that i915_error_work_func can acquire them).
1938 */
1939
1940 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1941 for_each_ring(ring, dev_priv, i)
1942 wake_up_all(&ring->irq_queue);
1943
1944 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1945 wake_up_all(&dev_priv->pending_flip_queue);
1946
1947 /*
1948 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1949 * reset state is cleared.
1950 */
1951 if (reset_completed)
1952 wake_up_all(&dev_priv->gpu_error.reset_queue);
1953}
1954
8a905236
JB		 1955/**
1956 * i915_error_work_func - do process context error handling work
1957 * @work: work struct
1958 *
1959 * Fire an error uevent so userspace can see that a hang or error
1960 * was detected.
1961 */
1962static void i915_error_work_func(struct work_struct *work)
1963{
1f83fee0
DV		 1964 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1965 work);
1966 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1967 gpu_error);
8a905236 1968 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 1969 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1970 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1971 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 1972 int ret;
8a905236 1973
5bdebb18 1974 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 1975
7db0ba24
DV		 1976 /*
1977 * Note that there's only one work item which does gpu resets, so we
1978 * need not worry about concurrent gpu resets potentially incrementing
1979 * error->reset_counter twice. We only need to take care of another
1980 * racing irq/hangcheck declaring the gpu dead for a second time. A
1981 * quick check for that is good enough: schedule_work ensures the
1982 * correct ordering between hang detection and this work item, and since
1983 * the reset in-progress bit is only ever set by code outside of this
1984 * work we don't need to worry about any other races.
1985 */
1986 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1987 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 1988 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 1989 reset_event);
1f83fee0 1990
17e1df07
DV		 1991 /*
1992 * All state reset _must_ be completed before we update the
1993 * reset counter, for otherwise waiters might miss the reset
1994 * pending state and not properly drop locks, resulting in
1995 * deadlocks with the reset work.
1996 */
f69061be
DV		 1997 ret = i915_reset(dev);
1998
17e1df07
DV		 1999 intel_display_handle_reset(dev);
2000
f69061be
DV		 2001 if (ret == 0) {
2002 /*
2003 * After all the gem state is reset, increment the reset
2004 * counter and wake up everyone waiting for the reset to
2005 * complete.
2006 *
2007 * Since unlock operations are a one-sided barrier only,
2008 * we need to insert a barrier here to order any seqno
2009 * updates before
2010 * the counter increment.
2011 */
2012 smp_mb__before_atomic_inc();
2013 atomic_inc(&dev_priv->gpu_error.reset_counter);
2014
5bdebb18 2015 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2016 KOBJ_CHANGE, reset_done_event);
1f83fee0 2017 } else {
2ac0f450 2018 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2019 }
1f83fee0 2020
17e1df07
DV		 2021 /*
2022 * Note: The wake_up also serves as a memory barrier so that
2023 * waiters see the update value of the reset counter atomic_t.
2024 */
2025 i915_error_wake_up(dev_priv, true);
f316a42c 2026 }
8a905236
JB		 2027}
2028
35aed2e6 2029static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2030{
2031 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2032 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2033 u32 eir = I915_READ(EIR);
050ee91f 2034 int pipe, i;
8a905236 2035
35aed2e6
CW		 2036 if (!eir)
2037 return;
8a905236 2038
a70491cc 2039 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2040
bd9854f9
BW		 2041 i915_get_extra_instdone(dev, instdone);
2042
8a905236
JB		 2043 if (IS_G4X(dev)) {
2044 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2045 u32 ipeir = I915_READ(IPEIR_I965);
2046
a70491cc
JP		 2047 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2048 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2049 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2050 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2051 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2052 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2053 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2054 POSTING_READ(IPEIR_I965);
8a905236
JB		 2055 }
2056 if (eir & GM45_ERROR_PAGE_TABLE) {
2057 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2058 pr_err("page table error\n");
2059 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2060 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2061 POSTING_READ(PGTBL_ER);
8a905236
JB		 2062 }
2063 }
2064
a6c45cf0 2065 if (!IS_GEN2(dev)) {
8a905236
JB		 2066 if (eir & I915_ERROR_PAGE_TABLE) {
2067 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2068 pr_err("page table error\n");
2069 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2070 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2071 POSTING_READ(PGTBL_ER);
8a905236
JB		 2072 }
2073 }
2074
2075 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2076 pr_err("memory refresh error:\n");
9db4a9c7 2077 for_each_pipe(pipe)
a70491cc 2078 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2079 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2080 /* pipestat has already been acked */
2081 }
2082 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2083 pr_err("instruction error\n");
2084 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2085 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2086 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2087 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2088 u32 ipeir = I915_READ(IPEIR);
2089
a70491cc
JP		 2090 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2091 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2092 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2093 I915_WRITE(IPEIR, ipeir);
3143a2bf 2094 POSTING_READ(IPEIR);
8a905236
JB		 2095 } else {
2096 u32 ipeir = I915_READ(IPEIR_I965);
2097
a70491cc
JP		 2098 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2099 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2100 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2101 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2102 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2103 POSTING_READ(IPEIR_I965);
8a905236
JB		 2104 }
2105 }
2106
2107 I915_WRITE(EIR, eir);
3143a2bf 2108 POSTING_READ(EIR);
8a905236
JB		 2109 eir = I915_READ(EIR);
2110 if (eir) {
2111 /*
2112 * some errors might have become stuck,
2113 * mask them.
2114 */
2115 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2116 I915_WRITE(EMR, I915_READ(EMR) | eir);
2117 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2118 }
35aed2e6
CW		 2119}
2120
2121/**
2122 * i915_handle_error - handle an error interrupt
2123 * @dev: drm device
2124 *
2125 * Do some basic checking of regsiter state at error interrupt time and
2126 * dump it to the syslog. Also call i915_capture_error_state() to make
2127 * sure we get a record and make it available in debugfs. Fire a uevent
2128 * so userspace knows something bad happened (should trigger collection
2129 * of a ring dump etc.).
2130 */
527f9e90 2131void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2132{
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134
2135 i915_capture_error_state(dev);
2136 i915_report_and_clear_eir(dev);
8a905236 2137
ba1234d1 2138 if (wedged) {
f69061be
DV		 2139 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2140 &dev_priv->gpu_error.reset_counter);
ba1234d1 2141
11ed50ec 2142 /*
17e1df07
DV		 2143 * Wakeup waiting processes so that the reset work function
2144 * i915_error_work_func doesn't deadlock trying to grab various
2145 * locks. By bumping the reset counter first, the woken
2146 * processes will see a reset in progress and back off,
2147 * releasing their locks and then wait for the reset completion.
2148 * We must do this for _all_ gpu waiters that might hold locks
2149 * that the reset work needs to acquire.
2150 *
2151 * Note: The wake_up serves as the required memory barrier to
2152 * ensure that the waiters see the updated value of the reset
2153 * counter atomic_t.
11ed50ec 2154 */
17e1df07 2155 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2156 }
2157
122f46ba
DV		 2158 /*
2159 * Our reset work can grab modeset locks (since it needs to reset the
2160 * state of outstanding pagelips). Hence it must not be run on our own
2161 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2162 * code will deadlock.
2163 */
2164 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2165}
2166
21ad8330 2167static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2168{
2169 drm_i915_private_t *dev_priv = dev->dev_private;
2170 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2172 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2173 struct intel_unpin_work *work;
2174 unsigned long flags;
2175 bool stall_detected;
2176
2177 /* Ignore early vblank irqs */
2178 if (intel_crtc == NULL)
2179 return;
2180
2181 spin_lock_irqsave(&dev->event_lock, flags);
2182 work = intel_crtc->unpin_work;
2183
e7d841ca
CW		 2184 if (work == NULL ||
2185 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2186 !work->enable_stall_check) {
4e5359cd
SF		 2187 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2188 spin_unlock_irqrestore(&dev->event_lock, flags);
2189 return;
2190 }
2191
2192 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2193 obj = work->pending_flip_obj;
a6c45cf0 2194 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2195 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2196 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2197 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2198 } else {
9db4a9c7 2199 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2200 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2201 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2202 crtc->x * crtc->fb->bits_per_pixel/8);
2203 }
2204
2205 spin_unlock_irqrestore(&dev->event_lock, flags);
2206
2207 if (stall_detected) {
2208 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2209 intel_prepare_page_flip(dev, intel_crtc->plane);
2210 }
2211}
2212
42f52ef8
KP		 2213/* Called from drm generic code, passed 'crtc' which
2214 * we use as a pipe index
2215 */
f71d4af4 2216static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2217{
2218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2219 unsigned long irqflags;
71e0ffa5 2220
5eddb70b 2221 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2222 return -EINVAL;
0a3e67a4 2223
1ec14ad3 2224 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2225 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2226 i915_enable_pipestat(dev_priv, pipe,
2227 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2228 else
7c463586
KP		 2229 i915_enable_pipestat(dev_priv, pipe,
2230 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2231
2232 /* maintain vblank delivery even in deep C-states */
2233 if (dev_priv->info->gen == 3)
6b26c86d 2234 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2235 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2236
0a3e67a4
JB		 2237 return 0;
2238}
2239
f71d4af4 2240static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2241{
2242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2243 unsigned long irqflags;
b518421f 2244 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2245 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2246
2247 if (!i915_pipe_enabled(dev, pipe))
2248 return -EINVAL;
2249
2250 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2251 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2252 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2253
2254 return 0;
2255}
2256
7e231dbe
JB		 2257static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2258{
2259 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2260 unsigned long irqflags;
31acc7f5 2261 u32 imr;
7e231dbe
JB		 2262
2263 if (!i915_pipe_enabled(dev, pipe))
2264 return -EINVAL;
2265
2266 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2267 imr = I915_READ(VLV_IMR);
3b6c42e8 2268 if (pipe == PIPE_A)
7e231dbe 2269 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2270 else
7e231dbe 2271 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2272 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2273 i915_enable_pipestat(dev_priv, pipe,
2274 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2275 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2276
2277 return 0;
2278}
2279
abd58f01
BW		 2280static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 unsigned long irqflags;
abd58f01
BW		 2284
2285 if (!i915_pipe_enabled(dev, pipe))
2286 return -EINVAL;
2287
2288 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2289 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2290 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2291 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2292 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2293 return 0;
2294}
2295
42f52ef8
KP		 2296/* Called from drm generic code, passed 'crtc' which
2297 * we use as a pipe index
2298 */
f71d4af4 2299static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2300{
2301 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2302 unsigned long irqflags;
0a3e67a4 2303
1ec14ad3 2304 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2305 if (dev_priv->info->gen == 3)
6b26c86d 2306 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2307
f796cf8f
JB		 2308 i915_disable_pipestat(dev_priv, pipe,
2309 PIPE_VBLANK_INTERRUPT_ENABLE |
2310 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2311 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2312}
2313
f71d4af4 2314static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2315{
2316 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2317 unsigned long irqflags;
b518421f 2318 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2319 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2320
2321 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2322 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2323 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2324}
2325
7e231dbe
JB		 2326static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2327{
2328 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2329 unsigned long irqflags;
31acc7f5 2330 u32 imr;
7e231dbe
JB		 2331
2332 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2333 i915_disable_pipestat(dev_priv, pipe,
2334 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2335 imr = I915_READ(VLV_IMR);
3b6c42e8 2336 if (pipe == PIPE_A)
7e231dbe 2337 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2338 else
7e231dbe 2339 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2340 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2341 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2342}
2343
abd58f01
BW		 2344static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2345{
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 unsigned long irqflags;
abd58f01
BW		 2348
2349 if (!i915_pipe_enabled(dev, pipe))
2350 return;
2351
2352 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2353 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2354 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2355 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2356 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2357}
2358
893eead0
CW		 2359static u32
2360ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2361{
893eead0
CW		 2362 return list_entry(ring->request_list.prev,
2363 struct drm_i915_gem_request, list)->seqno;
2364}
2365
9107e9d2
CW		 2366static bool
2367ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2368{
2369 return (list_empty(&ring->request_list) ||
2370 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2371}
2372
6274f212
CW		 2373static struct intel_ring_buffer *
2374semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2375{
2376 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2377 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2378
2379 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2380 if ((ipehr & ~(0x3 << 16)) !=
2381 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2382 return NULL;
a24a11e6
CW		 2383
2384 /* ACTHD is likely pointing to the dword after the actual command,
2385 * so scan backwards until we find the MBOX.
2386 */
6274f212 2387 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2388 acthd_min = max((int)acthd - 3 * 4, 0);
2389 do {
2390 cmd = ioread32(ring->virtual_start + acthd);
2391 if (cmd == ipehr)
2392 break;
2393
2394 acthd -= 4;
2395 if (acthd < acthd_min)
6274f212 2396 return NULL;
a24a11e6
CW		 2397 } while (1);
2398
6274f212
CW		 2399 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2400 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2401}
2402
6274f212
CW		 2403static int semaphore_passed(struct intel_ring_buffer *ring)
2404{
2405 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2406 struct intel_ring_buffer *signaller;
2407 u32 seqno, ctl;
2408
2409 ring->hangcheck.deadlock = true;
2410
2411 signaller = semaphore_waits_for(ring, &seqno);
2412 if (signaller == NULL || signaller->hangcheck.deadlock)
2413 return -1;
2414
2415 /* cursory check for an unkickable deadlock */
2416 ctl = I915_READ_CTL(signaller);
2417 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2418 return -1;
2419
2420 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2421}
2422
2423static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2424{
2425 struct intel_ring_buffer *ring;
2426 int i;
2427
2428 for_each_ring(ring, dev_priv, i)
2429 ring->hangcheck.deadlock = false;
2430}
2431
ad8beaea
MK		 2432static enum intel_ring_hangcheck_action
2433ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2434{
2435 struct drm_device *dev = ring->dev;
2436 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2437 u32 tmp;
2438
6274f212 2439 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2440 return HANGCHECK_ACTIVE;
6274f212 2441
9107e9d2 2442 if (IS_GEN2(dev))
f2f4d82f 2443 return HANGCHECK_HUNG;
9107e9d2
CW		 2444
2445 /* Is the chip hanging on a WAIT_FOR_EVENT?
2446 * If so we can simply poke the RB_WAIT bit
2447 * and break the hang. This should work on
2448 * all but the second generation chipsets.
2449 */
2450 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2451 if (tmp & RING_WAIT) {
2452 DRM_ERROR("Kicking stuck wait on %s\n",
2453 ring->name);
09e14bf3 2454 i915_handle_error(dev, false);
1ec14ad3 2455 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2456 return HANGCHECK_KICK;
6274f212
CW		 2457 }
2458
2459 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2460 switch (semaphore_passed(ring)) {
2461 default:
f2f4d82f 2462 return HANGCHECK_HUNG;
6274f212
CW		 2463 case 1:
2464 DRM_ERROR("Kicking stuck semaphore on %s\n",
2465 ring->name);
09e14bf3 2466 i915_handle_error(dev, false);
6274f212 2467 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2468 return HANGCHECK_KICK;
6274f212 2469 case 0:
f2f4d82f 2470 return HANGCHECK_WAIT;
6274f212 2471 }
9107e9d2 2472 }
ed5cbb03 2473
f2f4d82f 2474 return HANGCHECK_HUNG;
ed5cbb03
MK		 2475}
2476
f65d9421
BG		 2477/**
2478 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2479 * batchbuffers in a long time. We keep track per ring seqno progress and
2480 * if there are no progress, hangcheck score for that ring is increased.
2481 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2482 * we kick the ring. If we see no progress on three subsequent calls
2483 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2484 */
a658b5d2 2485static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2486{
2487 struct drm_device *dev = (struct drm_device *)data;
2488 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2489 struct intel_ring_buffer *ring;
b4519513 2490 int i;
05407ff8 2491 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2492 bool stuck[I915_NUM_RINGS] = { 0 };
2493#define BUSY 1
2494#define KICK 5
2495#define HUNG 20
2496#define FIRE 30
893eead0 2497
3e0dc6b0
BW		 2498 if (!i915_enable_hangcheck)
2499 return;
2500
b4519513 2501 for_each_ring(ring, dev_priv, i) {
05407ff8 2502 u32 seqno, acthd;
9107e9d2 2503 bool busy = true;
05407ff8 2504
6274f212
CW		 2505 semaphore_clear_deadlocks(dev_priv);
2506
05407ff8
MK		 2507 seqno = ring->get_seqno(ring, false);
2508 acthd = intel_ring_get_active_head(ring);
b4519513 2509
9107e9d2
CW		 2510 if (ring->hangcheck.seqno == seqno) {
2511 if (ring_idle(ring, seqno)) {
da661464
MK		 2512 ring->hangcheck.action = HANGCHECK_IDLE;
2513
9107e9d2
CW		 2514 if (waitqueue_active(&ring->irq_queue)) {
2515 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2516 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2517 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2518 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2519 ring->name);
2520 else
2521 DRM_INFO("Fake missed irq on %s\n",
2522 ring->name);
094f9a54
CW		 2523 wake_up_all(&ring->irq_queue);
2524 }
2525 /* Safeguard against driver failure */
2526 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2527 } else
2528 busy = false;
05407ff8 2529 } else {
6274f212
CW		 2530 /* We always increment the hangcheck score
2531 * if the ring is busy and still processing
2532 * the same request, so that no single request
2533 * can run indefinitely (such as a chain of
2534 * batches). The only time we do not increment
2535 * the hangcheck score on this ring, if this
2536 * ring is in a legitimate wait for another
2537 * ring. In that case the waiting ring is a
2538 * victim and we want to be sure we catch the
2539 * right culprit. Then every time we do kick
2540 * the ring, add a small increment to the
2541 * score so that we can catch a batch that is
2542 * being repeatedly kicked and so responsible
2543 * for stalling the machine.
2544 */
ad8beaea
MK		 2545 ring->hangcheck.action = ring_stuck(ring,
2546 acthd);
2547
2548 switch (ring->hangcheck.action) {
da661464 2549 case HANGCHECK_IDLE:
f2f4d82f 2550 case HANGCHECK_WAIT:
6274f212 2551 break;
f2f4d82f 2552 case HANGCHECK_ACTIVE:
ea04cb31 2553 ring->hangcheck.score += BUSY;
6274f212 2554 break;
f2f4d82f 2555 case HANGCHECK_KICK:
ea04cb31 2556 ring->hangcheck.score += KICK;
6274f212 2557 break;
f2f4d82f 2558 case HANGCHECK_HUNG:
ea04cb31 2559 ring->hangcheck.score += HUNG;
6274f212
CW		 2560 stuck[i] = true;
2561 break;
2562 }
05407ff8 2563 }
9107e9d2 2564 } else {
da661464
MK		 2565 ring->hangcheck.action = HANGCHECK_ACTIVE;
2566
9107e9d2
CW		 2567 /* Gradually reduce the count so that we catch DoS
2568 * attempts across multiple batches.
2569 */
2570 if (ring->hangcheck.score > 0)
2571 ring->hangcheck.score--;
d1e61e7f
CW		 2572 }
2573
05407ff8
MK		 2574 ring->hangcheck.seqno = seqno;
2575 ring->hangcheck.acthd = acthd;
9107e9d2 2576 busy_count += busy;
893eead0 2577 }
b9201c14 2578
92cab734 2579 for_each_ring(ring, dev_priv, i) {
9107e9d2 2580 if (ring->hangcheck.score > FIRE) {
b8d88d1d
DV		 2581 DRM_INFO("%s on %s\n",
2582 stuck[i] ? "stuck" : "no progress",
2583 ring->name);
a43adf07 2584 rings_hung++;
92cab734
MK		 2585 }
2586 }
2587
05407ff8
MK		 2588 if (rings_hung)
2589 return i915_handle_error(dev, true);
f65d9421 2590
05407ff8
MK		 2591 if (busy_count)
2592 /* Reset timer case chip hangs without another request
2593 * being added */
10cd45b6
MK		 2594 i915_queue_hangcheck(dev);
2595}
2596
2597void i915_queue_hangcheck(struct drm_device *dev)
2598{
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 if (!i915_enable_hangcheck)
2601 return;
2602
2603 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2604 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2605}
2606
91738a95
PZ		 2607static void ibx_irq_preinstall(struct drm_device *dev)
2608{
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610
2611 if (HAS_PCH_NOP(dev))
2612 return;
2613
2614 /* south display irq */
2615 I915_WRITE(SDEIMR, 0xffffffff);
2616 /*
2617 * SDEIER is also touched by the interrupt handler to work around missed
2618 * PCH interrupts. Hence we can't update it after the interrupt handler
2619 * is enabled - instead we unconditionally enable all PCH interrupt
2620 * sources here, but then only unmask them as needed with SDEIMR.
2621 */
2622 I915_WRITE(SDEIER, 0xffffffff);
2623 POSTING_READ(SDEIER);
2624}
2625
d18ea1b5
DV		 2626static void gen5_gt_irq_preinstall(struct drm_device *dev)
2627{
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629
2630 /* and GT */
2631 I915_WRITE(GTIMR, 0xffffffff);
2632 I915_WRITE(GTIER, 0x0);
2633 POSTING_READ(GTIER);
2634
2635 if (INTEL_INFO(dev)->gen >= 6) {
2636 /* and PM */
2637 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2638 I915_WRITE(GEN6_PMIER, 0x0);
2639 POSTING_READ(GEN6_PMIER);
2640 }
2641}
2642
1da177e4
LT		 2643/* drm_dma.h hooks
2644*/
f71d4af4 2645static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2646{
2647 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2648
2649 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2650
036a4a7d
ZW		 2651 I915_WRITE(DEIMR, 0xffffffff);
2652 I915_WRITE(DEIER, 0x0);
3143a2bf 2653 POSTING_READ(DEIER);
036a4a7d 2654
d18ea1b5 2655 gen5_gt_irq_preinstall(dev);
c650156a 2656
91738a95 2657 ibx_irq_preinstall(dev);
7d99163d
BW		 2658}
2659
7e231dbe
JB		 2660static void valleyview_irq_preinstall(struct drm_device *dev)
2661{
2662 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2663 int pipe;
2664
7e231dbe
JB		 2665 /* VLV magic */
2666 I915_WRITE(VLV_IMR, 0);
2667 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2668 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2669 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2670
7e231dbe
JB		 2671 /* and GT */
2672 I915_WRITE(GTIIR, I915_READ(GTIIR));
2673 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2674
2675 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2676
2677 I915_WRITE(DPINVGTT, 0xff);
2678
2679 I915_WRITE(PORT_HOTPLUG_EN, 0);
2680 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2681 for_each_pipe(pipe)
2682 I915_WRITE(PIPESTAT(pipe), 0xffff);
2683 I915_WRITE(VLV_IIR, 0xffffffff);
2684 I915_WRITE(VLV_IMR, 0xffffffff);
2685 I915_WRITE(VLV_IER, 0x0);
2686 POSTING_READ(VLV_IER);
2687}
2688
abd58f01
BW		 2689static void gen8_irq_preinstall(struct drm_device *dev)
2690{
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 int pipe;
2693
abd58f01
BW		 2694 I915_WRITE(GEN8_MASTER_IRQ, 0);
2695 POSTING_READ(GEN8_MASTER_IRQ);
2696
2697 /* IIR can theoretically queue up two events. Be paranoid */
2698#define GEN8_IRQ_INIT_NDX(type, which) do { \
2699 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2700 POSTING_READ(GEN8_##type##_IMR(which)); \
2701 I915_WRITE(GEN8_##type##_IER(which), 0); \
2702 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2703 POSTING_READ(GEN8_##type##_IIR(which)); \
2704 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2705 } while (0)
2706
2707#define GEN8_IRQ_INIT(type) do { \
2708 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2709 POSTING_READ(GEN8_##type##_IMR); \
2710 I915_WRITE(GEN8_##type##_IER, 0); \
2711 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2712 POSTING_READ(GEN8_##type##_IIR); \
2713 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2714 } while (0)
2715
2716 GEN8_IRQ_INIT_NDX(GT, 0);
2717 GEN8_IRQ_INIT_NDX(GT, 1);
2718 GEN8_IRQ_INIT_NDX(GT, 2);
2719 GEN8_IRQ_INIT_NDX(GT, 3);
2720
2721 for_each_pipe(pipe) {
2722 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2723 }
2724
2725 GEN8_IRQ_INIT(DE_PORT);
2726 GEN8_IRQ_INIT(DE_MISC);
2727 GEN8_IRQ_INIT(PCU);
2728#undef GEN8_IRQ_INIT
2729#undef GEN8_IRQ_INIT_NDX
2730
2731 POSTING_READ(GEN8_PCU_IIR);
09f2344d
JB		 2732
2733 ibx_irq_preinstall(dev);
abd58f01
BW		 2734}
2735
82a28bcf 2736static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2737{
2738 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2739 struct drm_mode_config *mode_config = &dev->mode_config;
2740 struct intel_encoder *intel_encoder;
fee884ed 2741 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2742
2743 if (HAS_PCH_IBX(dev)) {
fee884ed 2744 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2745 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2746 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2747 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2748 } else {
fee884ed 2749 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2750 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2751 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2752 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2753 }
7fe0b973 2754
fee884ed 2755 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2756
2757 /*
2758 * Enable digital hotplug on the PCH, and configure the DP short pulse
2759 * duration to 2ms (which is the minimum in the Display Port spec)
2760 *
2761 * This register is the same on all known PCH chips.
2762 */
7fe0b973
KP		 2763 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2764 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2765 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2766 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2767 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2768 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2769}
2770
d46da437
PZ		 2771static void ibx_irq_postinstall(struct drm_device *dev)
2772{
2773 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2774 u32 mask;
e5868a31 2775
692a04cf
DV		 2776 if (HAS_PCH_NOP(dev))
2777 return;
2778
8664281b
PZ		 2779 if (HAS_PCH_IBX(dev)) {
2780 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2781 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2782 } else {
2783 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2784
2785 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2786 }
ab5c608b 2787
d46da437
PZ		 2788 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2789 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2790}
2791
0a9a8c91
DV		 2792static void gen5_gt_irq_postinstall(struct drm_device *dev)
2793{
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 u32 pm_irqs, gt_irqs;
2796
2797 pm_irqs = gt_irqs = 0;
2798
2799 dev_priv->gt_irq_mask = ~0;
040d2baa 2800 if (HAS_L3_DPF(dev)) {
0a9a8c91 2801 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 2802 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2803 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 2804 }
2805
2806 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2807 if (IS_GEN5(dev)) {
2808 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2809 ILK_BSD_USER_INTERRUPT;
2810 } else {
2811 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2812 }
2813
2814 I915_WRITE(GTIIR, I915_READ(GTIIR));
2815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2816 I915_WRITE(GTIER, gt_irqs);
2817 POSTING_READ(GTIER);
2818
2819 if (INTEL_INFO(dev)->gen >= 6) {
2820 pm_irqs |= GEN6_PM_RPS_EVENTS;
2821
2822 if (HAS_VEBOX(dev))
2823 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2824
605cd25b 2825 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2826 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2827 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2828 I915_WRITE(GEN6_PMIER, pm_irqs);
2829 POSTING_READ(GEN6_PMIER);
2830 }
2831}
2832
f71d4af4 2833static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2834{
4bc9d430 2835 unsigned long irqflags;
036a4a7d 2836 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2837 u32 display_mask, extra_mask;
2838
2839 if (INTEL_INFO(dev)->gen >= 7) {
2840 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2841 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2842 DE_PLANEB_FLIP_DONE_IVB |
2843 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2844 DE_ERR_INT_IVB);
2845 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2846 DE_PIPEA_VBLANK_IVB);
2847
2848 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2849 } else {
2850 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2851 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b
DV		 2852 DE_AUX_CHANNEL_A |
2853 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2854 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2855 DE_POISON);
8e76f8dc
PZ		 2856 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2857 }
036a4a7d 2858
1ec14ad3 2859 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2860
2861 /* should always can generate irq */
2862 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2863 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2864 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2865 POSTING_READ(DEIER);
036a4a7d 2866
0a9a8c91 2867 gen5_gt_irq_postinstall(dev);
036a4a7d 2868
d46da437 2869 ibx_irq_postinstall(dev);
7fe0b973 2870
f97108d1 2871 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2872 /* Enable PCU event interrupts
2873 *
2874 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2875 * setup is guaranteed to run in single-threaded context. But we
2876 * need it to make the assert_spin_locked happy. */
2877 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2878 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2879 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2880 }
2881
036a4a7d
ZW		 2882 return 0;
2883}
2884
7e231dbe
JB		 2885static int valleyview_irq_postinstall(struct drm_device *dev)
2886{
2887 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2888 u32 enable_mask;
379ef82d
DV		 2889 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2890 PIPE_CRC_DONE_ENABLE;
b79480ba 2891 unsigned long irqflags;
7e231dbe
JB		 2892
2893 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2894 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2895 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2896 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2897 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2898
31acc7f5
JB		 2899 /*
2900 *Leave vblank interrupts masked initially. enable/disable will
2901 * toggle them based on usage.
2902 */
2903 dev_priv->irq_mask = (~enable_mask) |
2904 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2905 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2906
20afbda2
DV		 2907 I915_WRITE(PORT_HOTPLUG_EN, 0);
2908 POSTING_READ(PORT_HOTPLUG_EN);
2909
7e231dbe
JB		 2910 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2911 I915_WRITE(VLV_IER, enable_mask);
2912 I915_WRITE(VLV_IIR, 0xffffffff);
2913 I915_WRITE(PIPESTAT(0), 0xffff);
2914 I915_WRITE(PIPESTAT(1), 0xffff);
2915 POSTING_READ(VLV_IER);
2916
b79480ba
DV		 2917 /* Interrupt setup is already guaranteed to be single-threaded, this is
2918 * just to make the assert_spin_locked check happy. */
2919 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 2920 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2921 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2922 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
b79480ba 2923 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2924
7e231dbe
JB		 2925 I915_WRITE(VLV_IIR, 0xffffffff);
2926 I915_WRITE(VLV_IIR, 0xffffffff);
2927
0a9a8c91 2928 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2929
2930 /* ack & enable invalid PTE error interrupts */
2931#if 0 /* FIXME: add support to irq handler for checking these bits */
2932 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2933 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2934#endif
2935
2936 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2937
2938 return 0;
2939}
2940
abd58f01
BW		 2941static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2942{
2943 int i;
2944
2945 /* These are interrupts we'll toggle with the ring mask register */
2946 uint32_t gt_interrupts[] = {
2947 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2948 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2949 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2950 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2951 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2952 0,
2953 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2954 };
2955
2956 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2957 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2958 if (tmp)
2959 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2960 i, tmp);
2961 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2962 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2963 }
2964 POSTING_READ(GEN8_GT_IER(0));
2965}
2966
2967static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2968{
2969 struct drm_device *dev = dev_priv->dev;
13b3a0a7
DV		 2970 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2971 GEN8_PIPE_CDCLK_CRC_DONE |
2972 GEN8_PIPE_FIFO_UNDERRUN |
2973 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2974 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
abd58f01 2975 int pipe;
13b3a0a7
DV		 2976 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2977 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2978 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01
BW		 2979
2980 for_each_pipe(pipe) {
2981 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2982 if (tmp)
2983 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2984 pipe, tmp);
2985 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2986 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2987 }
2988 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2989
6d766f02
DV		 2990 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2991 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
abd58f01
BW		 2992 POSTING_READ(GEN8_DE_PORT_IER);
2993}
2994
2995static int gen8_irq_postinstall(struct drm_device *dev)
2996{
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998
2999 gen8_gt_irq_postinstall(dev_priv);
3000 gen8_de_irq_postinstall(dev_priv);
3001
3002 ibx_irq_postinstall(dev);
3003
3004 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3005 POSTING_READ(GEN8_MASTER_IRQ);
3006
3007 return 0;
3008}
3009
3010static void gen8_irq_uninstall(struct drm_device *dev)
3011{
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 int pipe;
3014
3015 if (!dev_priv)
3016 return;
3017
abd58f01
BW		 3018 I915_WRITE(GEN8_MASTER_IRQ, 0);
3019
3020#define GEN8_IRQ_FINI_NDX(type, which) do { \
3021 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3022 I915_WRITE(GEN8_##type##_IER(which), 0); \
3023 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3024 } while (0)
3025
3026#define GEN8_IRQ_FINI(type) do { \
3027 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3028 I915_WRITE(GEN8_##type##_IER, 0); \
3029 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3030 } while (0)
3031
3032 GEN8_IRQ_FINI_NDX(GT, 0);
3033 GEN8_IRQ_FINI_NDX(GT, 1);
3034 GEN8_IRQ_FINI_NDX(GT, 2);
3035 GEN8_IRQ_FINI_NDX(GT, 3);
3036
3037 for_each_pipe(pipe) {
3038 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3039 }
3040
3041 GEN8_IRQ_FINI(DE_PORT);
3042 GEN8_IRQ_FINI(DE_MISC);
3043 GEN8_IRQ_FINI(PCU);
3044#undef GEN8_IRQ_FINI
3045#undef GEN8_IRQ_FINI_NDX
3046
3047 POSTING_READ(GEN8_PCU_IIR);
3048}
3049
7e231dbe
JB		 3050static void valleyview_irq_uninstall(struct drm_device *dev)
3051{
3052 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3053 int pipe;
3054
3055 if (!dev_priv)
3056 return;
3057
3ca1cced 3058 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3059
7e231dbe
JB		 3060 for_each_pipe(pipe)
3061 I915_WRITE(PIPESTAT(pipe), 0xffff);
3062
3063 I915_WRITE(HWSTAM, 0xffffffff);
3064 I915_WRITE(PORT_HOTPLUG_EN, 0);
3065 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3066 for_each_pipe(pipe)
3067 I915_WRITE(PIPESTAT(pipe), 0xffff);
3068 I915_WRITE(VLV_IIR, 0xffffffff);
3069 I915_WRITE(VLV_IMR, 0xffffffff);
3070 I915_WRITE(VLV_IER, 0x0);
3071 POSTING_READ(VLV_IER);
3072}
3073
f71d4af4 3074static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 3075{
3076 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 3077
3078 if (!dev_priv)
3079 return;
3080
3ca1cced 3081 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3082
036a4a7d
ZW		 3083 I915_WRITE(HWSTAM, 0xffffffff);
3084
3085 I915_WRITE(DEIMR, 0xffffffff);
3086 I915_WRITE(DEIER, 0x0);
3087 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 3088 if (IS_GEN7(dev))
3089 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 3090
3091 I915_WRITE(GTIMR, 0xffffffff);
3092 I915_WRITE(GTIER, 0x0);
3093 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 3094
ab5c608b
BW		 3095 if (HAS_PCH_NOP(dev))
3096 return;
3097
192aac1f
KP		 3098 I915_WRITE(SDEIMR, 0xffffffff);
3099 I915_WRITE(SDEIER, 0x0);
3100 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 3101 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3102 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 3103}
3104
a266c7d5 3105static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 3106{
3107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 3108 int pipe;
91e3738e 3109
9db4a9c7
JB		 3110 for_each_pipe(pipe)
3111 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3112 I915_WRITE16(IMR, 0xffff);
3113 I915_WRITE16(IER, 0x0);
3114 POSTING_READ16(IER);
c2798b19
CW		 3115}
3116
3117static int i8xx_irq_postinstall(struct drm_device *dev)
3118{
3119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
379ef82d 3120 unsigned long irqflags;
c2798b19 3121
c2798b19
CW		 3122 I915_WRITE16(EMR,
3123 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3124
3125 /* Unmask the interrupts that we always want on. */
3126 dev_priv->irq_mask =
3127 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3128 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3129 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3130 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3131 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3132 I915_WRITE16(IMR, dev_priv->irq_mask);
3133
3134 I915_WRITE16(IER,
3135 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3136 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3137 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3138 I915_USER_INTERRUPT);
3139 POSTING_READ16(IER);
3140
379ef82d
DV		 3141 /* Interrupt setup is already guaranteed to be single-threaded, this is
3142 * just to make the assert_spin_locked check happy. */
3143 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3144 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3145 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
379ef82d
DV		 3146 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3147
c2798b19
CW		 3148 return 0;
3149}
3150
90a72f87
VS		 3151/*
3152 * Returns true when a page flip has completed.
3153 */
3154static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3155 int plane, int pipe, u32 iir)
90a72f87
VS		 3156{
3157 drm_i915_private_t *dev_priv = dev->dev_private;
1f1c2e24 3158 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87
VS		 3159
3160 if (!drm_handle_vblank(dev, pipe))
3161 return false;
3162
3163 if ((iir & flip_pending) == 0)
3164 return false;
3165
1f1c2e24 3166 intel_prepare_page_flip(dev, plane);
90a72f87
VS		 3167
3168 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3169 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3170 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3171 * the flip is completed (no longer pending). Since this doesn't raise
3172 * an interrupt per se, we watch for the change at vblank.
3173 */
3174 if (I915_READ16(ISR) & flip_pending)
3175 return false;
3176
3177 intel_finish_page_flip(dev, pipe);
3178
3179 return true;
3180}
3181
ff1f525e 3182static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3183{
3184 struct drm_device *dev = (struct drm_device *) arg;
3185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3186 u16 iir, new_iir;
3187 u32 pipe_stats[2];
3188 unsigned long irqflags;
c2798b19
CW		 3189 int pipe;
3190 u16 flip_mask =
3191 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3192 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3193
c2798b19
CW		 3194 iir = I915_READ16(IIR);
3195 if (iir == 0)
3196 return IRQ_NONE;
3197
3198 while (iir & ~flip_mask) {
3199 /* Can't rely on pipestat interrupt bit in iir as it might
3200 * have been cleared after the pipestat interrupt was received.
3201 * It doesn't set the bit in iir again, but it still produces
3202 * interrupts (for non-MSI).
3203 */
3204 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3205 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3206 i915_handle_error(dev, false);
3207
3208 for_each_pipe(pipe) {
3209 int reg = PIPESTAT(pipe);
3210 pipe_stats[pipe] = I915_READ(reg);
3211
3212 /*
3213 * Clear the PIPE*STAT regs before the IIR
3214 */
2d9d2b0b 3215 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3216 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 3217 }
3218 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3219
3220 I915_WRITE16(IIR, iir & ~flip_mask);
3221 new_iir = I915_READ16(IIR); /* Flush posted writes */
3222
d05c617e 3223 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3224
3225 if (iir & I915_USER_INTERRUPT)
3226 notify_ring(dev, &dev_priv->ring[RCS]);
3227
4356d586 3228 for_each_pipe(pipe) {
1f1c2e24 3229 int plane = pipe;
3a77c4c4 3230 if (HAS_FBC(dev))
1f1c2e24
VS		 3231 plane = !plane;
3232
4356d586 3233 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3234 i8xx_handle_vblank(dev, plane, pipe, iir))
3235 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3236
4356d586 3237 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3238 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3239
3240 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3241 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3242 DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
4356d586 3243 }
c2798b19
CW		 3244
3245 iir = new_iir;
3246 }
3247
3248 return IRQ_HANDLED;
3249}
3250
3251static void i8xx_irq_uninstall(struct drm_device * dev)
3252{
3253 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3254 int pipe;
3255
c2798b19
CW		 3256 for_each_pipe(pipe) {
3257 /* Clear enable bits; then clear status bits */
3258 I915_WRITE(PIPESTAT(pipe), 0);
3259 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3260 }
3261 I915_WRITE16(IMR, 0xffff);
3262 I915_WRITE16(IER, 0x0);
3263 I915_WRITE16(IIR, I915_READ16(IIR));
3264}
3265
a266c7d5
CW		 3266static void i915_irq_preinstall(struct drm_device * dev)
3267{
3268 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3269 int pipe;
3270
a266c7d5
CW		 3271 if (I915_HAS_HOTPLUG(dev)) {
3272 I915_WRITE(PORT_HOTPLUG_EN, 0);
3273 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3274 }
3275
00d98ebd 3276 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3277 for_each_pipe(pipe)
3278 I915_WRITE(PIPESTAT(pipe), 0);
3279 I915_WRITE(IMR, 0xffffffff);
3280 I915_WRITE(IER, 0x0);
3281 POSTING_READ(IER);
3282}
3283
3284static int i915_irq_postinstall(struct drm_device *dev)
3285{
3286 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3287 u32 enable_mask;
379ef82d 3288 unsigned long irqflags;
a266c7d5 3289
38bde180
CW		 3290 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3291
3292 /* Unmask the interrupts that we always want on. */
3293 dev_priv->irq_mask =
3294 ~(I915_ASLE_INTERRUPT |
3295 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3296 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3297 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3298 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3299 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3300
3301 enable_mask =
3302 I915_ASLE_INTERRUPT |
3303 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3304 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3305 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3306 I915_USER_INTERRUPT;
3307
a266c7d5 3308 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3309 I915_WRITE(PORT_HOTPLUG_EN, 0);
3310 POSTING_READ(PORT_HOTPLUG_EN);
3311
a266c7d5
CW		 3312 /* Enable in IER... */
3313 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3314 /* and unmask in IMR */
3315 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3316 }
3317
a266c7d5
CW		 3318 I915_WRITE(IMR, dev_priv->irq_mask);
3319 I915_WRITE(IER, enable_mask);
3320 POSTING_READ(IER);
3321
f49e38dd 3322 i915_enable_asle_pipestat(dev);
20afbda2 3323
379ef82d
DV		 3324 /* Interrupt setup is already guaranteed to be single-threaded, this is
3325 * just to make the assert_spin_locked check happy. */
3326 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3327 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3328 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
379ef82d
DV		 3329 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3330
20afbda2
DV		 3331 return 0;
3332}
3333
90a72f87
VS		 3334/*
3335 * Returns true when a page flip has completed.
3336 */
3337static bool i915_handle_vblank(struct drm_device *dev,
3338 int plane, int pipe, u32 iir)
3339{
3340 drm_i915_private_t *dev_priv = dev->dev_private;
3341 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3342
3343 if (!drm_handle_vblank(dev, pipe))
3344 return false;
3345
3346 if ((iir & flip_pending) == 0)
3347 return false;
3348
3349 intel_prepare_page_flip(dev, plane);
3350
3351 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3352 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3353 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3354 * the flip is completed (no longer pending). Since this doesn't raise
3355 * an interrupt per se, we watch for the change at vblank.
3356 */
3357 if (I915_READ(ISR) & flip_pending)
3358 return false;
3359
3360 intel_finish_page_flip(dev, pipe);
3361
3362 return true;
3363}
3364
ff1f525e 3365static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3366{
3367 struct drm_device *dev = (struct drm_device *) arg;
3368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3369 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3370 unsigned long irqflags;
38bde180
CW		 3371 u32 flip_mask =
3372 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3373 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3374 int pipe, ret = IRQ_NONE;
a266c7d5 3375
a266c7d5 3376 iir = I915_READ(IIR);
38bde180
CW		 3377 do {
3378 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3379 bool blc_event = false;
a266c7d5
CW		 3380
3381 /* Can't rely on pipestat interrupt bit in iir as it might
3382 * have been cleared after the pipestat interrupt was received.
3383 * It doesn't set the bit in iir again, but it still produces
3384 * interrupts (for non-MSI).
3385 */
3386 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3387 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3388 i915_handle_error(dev, false);
3389
3390 for_each_pipe(pipe) {
3391 int reg = PIPESTAT(pipe);
3392 pipe_stats[pipe] = I915_READ(reg);
3393
38bde180 3394 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3395 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3396 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3397 irq_received = true;
a266c7d5
CW		 3398 }
3399 }
3400 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3401
3402 if (!irq_received)
3403 break;
3404
a266c7d5
CW		 3405 /* Consume port. Then clear IIR or we'll miss events */
3406 if ((I915_HAS_HOTPLUG(dev)) &&
3407 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3408 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3409 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5 3410
91d131d2
DV		 3411 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3412
a266c7d5 3413 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3414 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3415 }
3416
38bde180 3417 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3418 new_iir = I915_READ(IIR); /* Flush posted writes */
3419
a266c7d5
CW		 3420 if (iir & I915_USER_INTERRUPT)
3421 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3422
a266c7d5 3423 for_each_pipe(pipe) {
38bde180 3424 int plane = pipe;
3a77c4c4 3425 if (HAS_FBC(dev))
38bde180 3426 plane = !plane;
90a72f87 3427
8291ee90 3428 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3429 i915_handle_vblank(dev, plane, pipe, iir))
3430 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3431
3432 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3433 blc_event = true;
4356d586
DV		 3434
3435 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3436 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3437
3438 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3439 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3440 DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
a266c7d5
CW		 3441 }
3442
a266c7d5
CW		 3443 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3444 intel_opregion_asle_intr(dev);
3445
3446 /* With MSI, interrupts are only generated when iir
3447 * transitions from zero to nonzero. If another bit got
3448 * set while we were handling the existing iir bits, then
3449 * we would never get another interrupt.
3450 *
3451 * This is fine on non-MSI as well, as if we hit this path
3452 * we avoid exiting the interrupt handler only to generate
3453 * another one.
3454 *
3455 * Note that for MSI this could cause a stray interrupt report
3456 * if an interrupt landed in the time between writing IIR and
3457 * the posting read. This should be rare enough to never
3458 * trigger the 99% of 100,000 interrupts test for disabling
3459 * stray interrupts.
3460 */
38bde180 3461 ret = IRQ_HANDLED;
a266c7d5 3462 iir = new_iir;
38bde180 3463 } while (iir & ~flip_mask);
a266c7d5 3464
d05c617e 3465 i915_update_dri1_breadcrumb(dev);
8291ee90 3466
a266c7d5
CW		 3467 return ret;
3468}
3469
3470static void i915_irq_uninstall(struct drm_device * dev)
3471{
3472 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3473 int pipe;
3474
3ca1cced 3475 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3476
a266c7d5
CW		 3477 if (I915_HAS_HOTPLUG(dev)) {
3478 I915_WRITE(PORT_HOTPLUG_EN, 0);
3479 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3480 }
3481
00d98ebd 3482 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3483 for_each_pipe(pipe) {
3484 /* Clear enable bits; then clear status bits */
a266c7d5 3485 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3486 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3487 }
a266c7d5
CW		 3488 I915_WRITE(IMR, 0xffffffff);
3489 I915_WRITE(IER, 0x0);
3490
a266c7d5
CW		 3491 I915_WRITE(IIR, I915_READ(IIR));
3492}
3493
3494static void i965_irq_preinstall(struct drm_device * dev)
3495{
3496 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3497 int pipe;
3498
adca4730
CW		 3499 I915_WRITE(PORT_HOTPLUG_EN, 0);
3500 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3501
3502 I915_WRITE(HWSTAM, 0xeffe);
3503 for_each_pipe(pipe)
3504 I915_WRITE(PIPESTAT(pipe), 0);
3505 I915_WRITE(IMR, 0xffffffff);
3506 I915_WRITE(IER, 0x0);
3507 POSTING_READ(IER);
3508}
3509
3510static int i965_irq_postinstall(struct drm_device *dev)
3511{
3512 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3513 u32 enable_mask;
a266c7d5 3514 u32 error_mask;
b79480ba 3515 unsigned long irqflags;
a266c7d5 3516
a266c7d5 3517 /* Unmask the interrupts that we always want on. */
bbba0a97 3518 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3519 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3520 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3521 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3522 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3523 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3524 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3525
3526 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3527 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3528 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3529 enable_mask |= I915_USER_INTERRUPT;
3530
3531 if (IS_G4X(dev))
3532 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3533
b79480ba
DV		 3534 /* Interrupt setup is already guaranteed to be single-threaded, this is
3535 * just to make the assert_spin_locked check happy. */
3536 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3b6c42e8
DV		 3537 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3538 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3539 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
b79480ba 3540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3541
a266c7d5
CW		 3542 /*
3543 * Enable some error detection, note the instruction error mask
3544 * bit is reserved, so we leave it masked.
3545 */
3546 if (IS_G4X(dev)) {
3547 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3548 GM45_ERROR_MEM_PRIV |
3549 GM45_ERROR_CP_PRIV |
3550 I915_ERROR_MEMORY_REFRESH);
3551 } else {
3552 error_mask = ~(I915_ERROR_PAGE_TABLE |
3553 I915_ERROR_MEMORY_REFRESH);
3554 }
3555 I915_WRITE(EMR, error_mask);
3556
3557 I915_WRITE(IMR, dev_priv->irq_mask);
3558 I915_WRITE(IER, enable_mask);
3559 POSTING_READ(IER);
3560
20afbda2
DV		 3561 I915_WRITE(PORT_HOTPLUG_EN, 0);
3562 POSTING_READ(PORT_HOTPLUG_EN);
3563
f49e38dd 3564 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3565
3566 return 0;
3567}
3568
bac56d5b 3569static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3570{
3571 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3572 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3573 struct intel_encoder *intel_encoder;
20afbda2
DV		 3574 u32 hotplug_en;
3575
b5ea2d56
DV		 3576 assert_spin_locked(&dev_priv->irq_lock);
3577
bac56d5b
EE		 3578 if (I915_HAS_HOTPLUG(dev)) {
3579 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3580 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3581 /* Note HDMI and DP share hotplug bits */
e5868a31 3582 /* enable bits are the same for all generations */
cd569aed
EE		 3583 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3584 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3585 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3586 /* Programming the CRT detection parameters tends
3587 to generate a spurious hotplug event about three
3588 seconds later. So just do it once.
3589 */
3590 if (IS_G4X(dev))
3591 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3592 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3593 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3594
bac56d5b
EE		 3595 /* Ignore TV since it's buggy */
3596 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3597 }
a266c7d5
CW		 3598}
3599
ff1f525e 3600static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3601{
3602 struct drm_device *dev = (struct drm_device *) arg;
3603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3604 u32 iir, new_iir;
3605 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 3606 unsigned long irqflags;
a266c7d5 3607 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3608 u32 flip_mask =
3609 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3610 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 3611
a266c7d5
CW		 3612 iir = I915_READ(IIR);
3613
a266c7d5 3614 for (;;) {
501e01d7 3615 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 3616 bool blc_event = false;
3617
a266c7d5
CW		 3618 /* Can't rely on pipestat interrupt bit in iir as it might
3619 * have been cleared after the pipestat interrupt was received.
3620 * It doesn't set the bit in iir again, but it still produces
3621 * interrupts (for non-MSI).
3622 */
3623 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3624 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3625 i915_handle_error(dev, false);
3626
3627 for_each_pipe(pipe) {
3628 int reg = PIPESTAT(pipe);
3629 pipe_stats[pipe] = I915_READ(reg);
3630
3631 /*
3632 * Clear the PIPE*STAT regs before the IIR
3633 */
3634 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3635 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 3636 irq_received = true;
a266c7d5
CW		 3637 }
3638 }
3639 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3640
3641 if (!irq_received)
3642 break;
3643
3644 ret = IRQ_HANDLED;
3645
3646 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3647 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3648 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3649 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3650 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3651 HOTPLUG_INT_STATUS_I915);
a266c7d5 3652
91d131d2 3653 intel_hpd_irq_handler(dev, hotplug_trigger,
704cfb87 3654 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
91d131d2 3655
4aeebd74
DV		 3656 if (IS_G4X(dev) &&
3657 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3658 dp_aux_irq_handler(dev);
3659
a266c7d5
CW		 3660 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3661 I915_READ(PORT_HOTPLUG_STAT);
3662 }
3663
21ad8330 3664 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3665 new_iir = I915_READ(IIR); /* Flush posted writes */
3666
a266c7d5
CW		 3667 if (iir & I915_USER_INTERRUPT)
3668 notify_ring(dev, &dev_priv->ring[RCS]);
3669 if (iir & I915_BSD_USER_INTERRUPT)
3670 notify_ring(dev, &dev_priv->ring[VCS]);
3671
a266c7d5 3672 for_each_pipe(pipe) {
2c8ba29f 3673 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3674 i915_handle_vblank(dev, pipe, pipe, iir))
3675 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3676
3677 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3678 blc_event = true;
4356d586
DV		 3679
3680 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3681 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 3682
2d9d2b0b
VS		 3683 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3684 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3685 DRM_DEBUG_DRIVER("pipe %c underrun\n", pipe_name(pipe));
3686 }
a266c7d5
CW		 3687
3688 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3689 intel_opregion_asle_intr(dev);
3690
515ac2bb
DV		 3691 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3692 gmbus_irq_handler(dev);
3693
a266c7d5
CW		 3694 /* With MSI, interrupts are only generated when iir
3695 * transitions from zero to nonzero. If another bit got
3696 * set while we were handling the existing iir bits, then
3697 * we would never get another interrupt.
3698 *
3699 * This is fine on non-MSI as well, as if we hit this path
3700 * we avoid exiting the interrupt handler only to generate
3701 * another one.
3702 *
3703 * Note that for MSI this could cause a stray interrupt report
3704 * if an interrupt landed in the time between writing IIR and
3705 * the posting read. This should be rare enough to never
3706 * trigger the 99% of 100,000 interrupts test for disabling
3707 * stray interrupts.
3708 */
3709 iir = new_iir;
3710 }
3711
d05c617e 3712 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3713
a266c7d5
CW		 3714 return ret;
3715}
3716
3717static void i965_irq_uninstall(struct drm_device * dev)
3718{
3719 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3720 int pipe;
3721
3722 if (!dev_priv)
3723 return;
3724
3ca1cced 3725 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3726
adca4730
CW		 3727 I915_WRITE(PORT_HOTPLUG_EN, 0);
3728 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3729
3730 I915_WRITE(HWSTAM, 0xffffffff);
3731 for_each_pipe(pipe)
3732 I915_WRITE(PIPESTAT(pipe), 0);
3733 I915_WRITE(IMR, 0xffffffff);
3734 I915_WRITE(IER, 0x0);
3735
3736 for_each_pipe(pipe)
3737 I915_WRITE(PIPESTAT(pipe),
3738 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3739 I915_WRITE(IIR, I915_READ(IIR));
3740}
3741
3ca1cced 3742static void intel_hpd_irq_reenable(unsigned long data)
ac4c16c5
EE		 3743{
3744 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3745 struct drm_device *dev = dev_priv->dev;
3746 struct drm_mode_config *mode_config = &dev->mode_config;
3747 unsigned long irqflags;
3748 int i;
3749
3750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3751 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3752 struct drm_connector *connector;
3753
3754 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3755 continue;
3756
3757 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3758
3759 list_for_each_entry(connector, &mode_config->connector_list, head) {
3760 struct intel_connector *intel_connector = to_intel_connector(connector);
3761
3762 if (intel_connector->encoder->hpd_pin == i) {
3763 if (connector->polled != intel_connector->polled)
3764 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3765 drm_get_connector_name(connector));
3766 connector->polled = intel_connector->polled;
3767 if (!connector->polled)
3768 connector->polled = DRM_CONNECTOR_POLL_HPD;
3769 }
3770 }
3771 }
3772 if (dev_priv->display.hpd_irq_setup)
3773 dev_priv->display.hpd_irq_setup(dev);
3774 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775}
3776
f71d4af4
JB		 3777void intel_irq_init(struct drm_device *dev)
3778{
8b2e326d
CW		 3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3782 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3783 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3784 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3785
99584db3
DV		 3786 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3787 i915_hangcheck_elapsed,
61bac78e 3788 (unsigned long) dev);
3ca1cced 3789 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
ac4c16c5 3790 (unsigned long) dev_priv);
61bac78e 3791
97a19a24 3792 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3793
4cdb83ec
VS		 3794 if (IS_GEN2(dev)) {
3795 dev->max_vblank_count = 0;
3796 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3797 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3798 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3799 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 3800 } else {
3801 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3802 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 3803 }
3804
c2baf4b7 3805 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 3806 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 3807 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3808 }
f71d4af4 3809
7e231dbe
JB		 3810 if (IS_VALLEYVIEW(dev)) {
3811 dev->driver->irq_handler = valleyview_irq_handler;
3812 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3813 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3814 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3815 dev->driver->enable_vblank = valleyview_enable_vblank;
3816 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3817 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
abd58f01
BW		 3818 } else if (IS_GEN8(dev)) {
3819 dev->driver->irq_handler = gen8_irq_handler;
3820 dev->driver->irq_preinstall = gen8_irq_preinstall;
3821 dev->driver->irq_postinstall = gen8_irq_postinstall;
3822 dev->driver->irq_uninstall = gen8_irq_uninstall;
3823 dev->driver->enable_vblank = gen8_enable_vblank;
3824 dev->driver->disable_vblank = gen8_disable_vblank;
3825 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3826 } else if (HAS_PCH_SPLIT(dev)) {
3827 dev->driver->irq_handler = ironlake_irq_handler;
3828 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3829 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3830 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3831 dev->driver->enable_vblank = ironlake_enable_vblank;
3832 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3833 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3834 } else {
c2798b19
CW		 3835 if (INTEL_INFO(dev)->gen == 2) {
3836 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3837 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3838 dev->driver->irq_handler = i8xx_irq_handler;
3839 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3840 } else if (INTEL_INFO(dev)->gen == 3) {
3841 dev->driver->irq_preinstall = i915_irq_preinstall;
3842 dev->driver->irq_postinstall = i915_irq_postinstall;
3843 dev->driver->irq_uninstall = i915_irq_uninstall;
3844 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3845 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3846 } else {
a266c7d5
CW		 3847 dev->driver->irq_preinstall = i965_irq_preinstall;
3848 dev->driver->irq_postinstall = i965_irq_postinstall;
3849 dev->driver->irq_uninstall = i965_irq_uninstall;
3850 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3851 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3852 }
f71d4af4
JB		 3853 dev->driver->enable_vblank = i915_enable_vblank;
3854 dev->driver->disable_vblank = i915_disable_vblank;
3855 }
3856}
20afbda2
DV		 3857
3858void intel_hpd_init(struct drm_device *dev)
3859{
3860 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3861 struct drm_mode_config *mode_config = &dev->mode_config;
3862 struct drm_connector *connector;
b5ea2d56 3863 unsigned long irqflags;
821450c6 3864 int i;
20afbda2 3865
821450c6
EE		 3866 for (i = 1; i < HPD_NUM_PINS; i++) {
3867 dev_priv->hpd_stats[i].hpd_cnt = 0;
3868 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3869 }
3870 list_for_each_entry(connector, &mode_config->connector_list, head) {
3871 struct intel_connector *intel_connector = to_intel_connector(connector);
3872 connector->polled = intel_connector->polled;
3873 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3874 connector->polled = DRM_CONNECTOR_POLL_HPD;
3875 }
b5ea2d56
DV		 3876
3877 /* Interrupt setup is already guaranteed to be single-threaded, this is
3878 * just to make the assert_spin_locked checks happy. */
3879 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3880 if (dev_priv->display.hpd_irq_setup)
3881 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3882 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3883}
c67a470b
PZ		 3884
3885/* Disable interrupts so we can allow Package C8+. */
3886void hsw_pc8_disable_interrupts(struct drm_device *dev)
3887{
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 unsigned long irqflags;
3890
3891 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3892
3893 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3894 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3895 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3896 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3897 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3898
1f2d4531
PZ		 3899 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3900 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
c67a470b
PZ		 3901 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3902 snb_disable_pm_irq(dev_priv, 0xffffffff);
3903
3904 dev_priv->pc8.irqs_disabled = true;
3905
3906 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3907}
3908
3909/* Restore interrupts so we can recover from Package C8+. */
3910void hsw_pc8_restore_interrupts(struct drm_device *dev)
3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 unsigned long irqflags;
1f2d4531 3914 uint32_t val;
c67a470b
PZ		 3915
3916 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3917
3918 val = I915_READ(DEIMR);
1f2d4531 3919 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
c67a470b 3920
1f2d4531
PZ		 3921 val = I915_READ(SDEIMR);
3922 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
c67a470b
PZ		 3923
3924 val = I915_READ(GTIMR);
1f2d4531 3925 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
c67a470b
PZ		 3926
3927 val = I915_READ(GEN6_PMIMR);
1f2d4531 3928 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
c67a470b
PZ		 3929
3930 dev_priv->pc8.irqs_disabled = false;
3931
3932 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
1f2d4531 3933 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
c67a470b
PZ		 3934 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3935 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3936 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3937
3938 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3939}
Linux kernel - Deliverables
This page took 1.024366 seconds and 5 git commands to generate.