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drm: Change create block to reserve node
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
8664281b
PZ		 107static bool ivb_can_enable_err_int(struct drm_device *dev)
108{
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
4bc9d430
DV		 113 assert_spin_locked(&dev_priv->irq_lock);
114
8664281b
PZ		 115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123}
124
125static bool cpt_can_enable_serr_int(struct drm_device *dev)
126{
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
131 for_each_pipe(pipe) {
132 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
133
134 if (crtc->pch_fifo_underrun_disabled)
135 return false;
136 }
137
138 return true;
139}
140
141static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
142 enum pipe pipe, bool enable)
143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
146 DE_PIPEB_FIFO_UNDERRUN;
147
148 if (enable)
149 ironlake_enable_display_irq(dev_priv, bit);
150 else
151 ironlake_disable_display_irq(dev_priv, bit);
152}
153
154static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
155 bool enable)
156{
157 struct drm_i915_private *dev_priv = dev->dev_private;
158
159 if (enable) {
160 if (!ivb_can_enable_err_int(dev))
161 return;
162
163 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
164 ERR_INT_FIFO_UNDERRUN_B |
165 ERR_INT_FIFO_UNDERRUN_C);
166
167 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
168 } else {
169 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
170 }
171}
172
173static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
174 bool enable)
175{
176 struct drm_device *dev = crtc->base.dev;
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
179 SDE_TRANSB_FIFO_UNDER;
180
181 if (enable)
182 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
183 else
184 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
185
186 POSTING_READ(SDEIMR);
187}
188
189static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
190 enum transcoder pch_transcoder,
191 bool enable)
192{
193 struct drm_i915_private *dev_priv = dev->dev_private;
194
195 if (enable) {
196 if (!cpt_can_enable_serr_int(dev))
197 return;
198
199 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
200 SERR_INT_TRANS_B_FIFO_UNDERRUN |
201 SERR_INT_TRANS_C_FIFO_UNDERRUN);
202
203 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
204 } else {
205 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
206 }
207
208 POSTING_READ(SDEIMR);
209}
210
211/**
212 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
213 * @dev: drm device
214 * @pipe: pipe
215 * @enable: true if we want to report FIFO underrun errors, false otherwise
216 *
217 * This function makes us disable or enable CPU fifo underruns for a specific
218 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
219 * reporting for one pipe may also disable all the other CPU error interruts for
220 * the other pipes, due to the fact that there's just one interrupt mask/enable
221 * bit for all the pipes.
222 *
223 * Returns the previous state of underrun reporting.
224 */
225bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
226 enum pipe pipe, bool enable)
227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
231 unsigned long flags;
232 bool ret;
233
234 spin_lock_irqsave(&dev_priv->irq_lock, flags);
235
236 ret = !intel_crtc->cpu_fifo_underrun_disabled;
237
238 if (enable == ret)
239 goto done;
240
241 intel_crtc->cpu_fifo_underrun_disabled = !enable;
242
243 if (IS_GEN5(dev) || IS_GEN6(dev))
244 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
245 else if (IS_GEN7(dev))
246 ivybridge_set_fifo_underrun_reporting(dev, enable);
247
248done:
249 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
250 return ret;
251}
252
253/**
254 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
255 * @dev: drm device
256 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
257 * @enable: true if we want to report FIFO underrun errors, false otherwise
258 *
259 * This function makes us disable or enable PCH fifo underruns for a specific
260 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
261 * underrun reporting for one transcoder may also disable all the other PCH
262 * error interruts for the other transcoders, due to the fact that there's just
263 * one interrupt mask/enable bit for all the transcoders.
264 *
265 * Returns the previous state of underrun reporting.
266 */
267bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
268 enum transcoder pch_transcoder,
269 bool enable)
270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 enum pipe p;
273 struct drm_crtc *crtc;
274 struct intel_crtc *intel_crtc;
275 unsigned long flags;
276 bool ret;
277
278 if (HAS_PCH_LPT(dev)) {
279 crtc = NULL;
280 for_each_pipe(p) {
281 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
282 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
283 crtc = c;
284 break;
285 }
286 }
287 if (!crtc) {
288 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
289 return false;
290 }
291 } else {
292 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
293 }
294 intel_crtc = to_intel_crtc(crtc);
295
296 spin_lock_irqsave(&dev_priv->irq_lock, flags);
297
298 ret = !intel_crtc->pch_fifo_underrun_disabled;
299
300 if (enable == ret)
301 goto done;
302
303 intel_crtc->pch_fifo_underrun_disabled = !enable;
304
305 if (HAS_PCH_IBX(dev))
306 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
307 else
308 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
309
310done:
311 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
312 return ret;
313}
314
315
7c463586
KP		 316void
317i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
318{
46c06a30
VS		 319 u32 reg = PIPESTAT(pipe);
320 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 321
b79480ba
DV		 322 assert_spin_locked(&dev_priv->irq_lock);
323
46c06a30
VS		 324 if ((pipestat & mask) == mask)
325 return;
326
327 /* Enable the interrupt, clear any pending status */
328 pipestat |= mask | (mask >> 16);
329 I915_WRITE(reg, pipestat);
330 POSTING_READ(reg);
7c463586
KP		 331}
332
333void
334i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
335{
46c06a30
VS		 336 u32 reg = PIPESTAT(pipe);
337 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 338
b79480ba
DV		 339 assert_spin_locked(&dev_priv->irq_lock);
340
46c06a30
VS		 341 if ((pipestat & mask) == 0)
342 return;
343
344 pipestat &= ~mask;
345 I915_WRITE(reg, pipestat);
346 POSTING_READ(reg);
7c463586
KP		 347}
348
01c66889 349/**
f49e38dd 350 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 351 */
f49e38dd 352static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 353{
1ec14ad3
CW		 354 drm_i915_private_t *dev_priv = dev->dev_private;
355 unsigned long irqflags;
356
f49e38dd
JN		 357 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
358 return;
359
1ec14ad3 360 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 361
f898780b
JN		 362 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
363 if (INTEL_INFO(dev)->gen >= 4)
364 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 365
366 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 367}
368
0a3e67a4
JB		 369/**
370 * i915_pipe_enabled - check if a pipe is enabled
371 * @dev: DRM device
372 * @pipe: pipe to check
373 *
374 * Reading certain registers when the pipe is disabled can hang the chip.
375 * Use this routine to make sure the PLL is running and the pipe is active
376 * before reading such registers if unsure.
377 */
378static int
379i915_pipe_enabled(struct drm_device *dev, int pipe)
380{
381 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 382
a01025af
DV		 383 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
384 /* Locking is horribly broken here, but whatever. */
385 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 387
a01025af
DV		 388 return intel_crtc->active;
389 } else {
390 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
391 }
0a3e67a4
JB		 392}
393
42f52ef8
KP		 394/* Called from drm generic code, passed a 'crtc', which
395 * we use as a pipe index
396 */
f71d4af4 397static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 398{
399 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
400 unsigned long high_frame;
401 unsigned long low_frame;
5eddb70b 402 u32 high1, high2, low;
0a3e67a4
JB		 403
404 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 405 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 406 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 407 return 0;
408 }
409
9db4a9c7
JB		 410 high_frame = PIPEFRAME(pipe);
411 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 412
0a3e67a4
JB		 413 /*
414 * High & low register fields aren't synchronized, so make sure
415 * we get a low value that's stable across two reads of the high
416 * register.
417 */
418 do {
5eddb70b
CW		 419 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
420 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
421 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 422 } while (high1 != high2);
423
5eddb70b
CW		 424 high1 >>= PIPE_FRAME_HIGH_SHIFT;
425 low >>= PIPE_FRAME_LOW_SHIFT;
426 return (high1 << 8) | low;
0a3e67a4
JB		 427}
428
f71d4af4 429static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 430{
431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 432 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 433
434 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 435 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 436 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 437 return 0;
438 }
439
440 return I915_READ(reg);
441}
442
f71d4af4 443static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 444 int *vpos, int *hpos)
445{
446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
447 u32 vbl = 0, position = 0;
448 int vbl_start, vbl_end, htotal, vtotal;
449 bool in_vbl = true;
450 int ret = 0;
fe2b8f9d
PZ		 451 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
452 pipe);
0af7e4df
MK		 453
454 if (!i915_pipe_enabled(dev, pipe)) {
455 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 456 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 457 return 0;
458 }
459
460 /* Get vtotal. */
fe2b8f9d 461 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 462
463 if (INTEL_INFO(dev)->gen >= 4) {
464 /* No obvious pixelcount register. Only query vertical
465 * scanout position from Display scan line register.
466 */
467 position = I915_READ(PIPEDSL(pipe));
468
469 /* Decode into vertical scanout position. Don't have
470 * horizontal scanout position.
471 */
472 *vpos = position & 0x1fff;
473 *hpos = 0;
474 } else {
475 /* Have access to pixelcount since start of frame.
476 * We can split this into vertical and horizontal
477 * scanout position.
478 */
479 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
480
fe2b8f9d 481 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 482 *vpos = position / htotal;
483 *hpos = position - (*vpos * htotal);
484 }
485
486 /* Query vblank area. */
fe2b8f9d 487 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 488
489 /* Test position against vblank region. */
490 vbl_start = vbl & 0x1fff;
491 vbl_end = (vbl >> 16) & 0x1fff;
492
493 if ((*vpos < vbl_start) || (*vpos > vbl_end))
494 in_vbl = false;
495
496 /* Inside "upper part" of vblank area? Apply corrective offset: */
497 if (in_vbl && (*vpos >= vbl_start))
498 *vpos = *vpos - vtotal;
499
500 /* Readouts valid? */
501 if (vbl > 0)
502 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
503
504 /* In vblank? */
505 if (in_vbl)
506 ret |= DRM_SCANOUTPOS_INVBL;
507
508 return ret;
509}
510
f71d4af4 511static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 512 int *max_error,
513 struct timeval *vblank_time,
514 unsigned flags)
515{
4041b853 516 struct drm_crtc *crtc;
0af7e4df 517
7eb552ae 518 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 519 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 520 return -EINVAL;
521 }
522
523 /* Get drm_crtc to timestamp: */
4041b853
CW		 524 crtc = intel_get_crtc_for_pipe(dev, pipe);
525 if (crtc == NULL) {
526 DRM_ERROR("Invalid crtc %d\n", pipe);
527 return -EINVAL;
528 }
529
530 if (!crtc->enabled) {
531 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
532 return -EBUSY;
533 }
0af7e4df
MK		 534
535 /* Helper routine in DRM core does all the work: */
4041b853
CW		 536 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
537 vblank_time, flags,
538 crtc);
0af7e4df
MK		 539}
540
321a1b30
EE		 541static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
542{
543 enum drm_connector_status old_status;
544
545 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
546 old_status = connector->status;
547
548 connector->status = connector->funcs->detect(connector, false);
549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
550 connector->base.id,
551 drm_get_connector_name(connector),
552 old_status, connector->status);
553 return (old_status != connector->status);
554}
555
5ca58282
JB		 556/*
557 * Handle hotplug events outside the interrupt handler proper.
558 */
ac4c16c5
EE		 559#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
560
5ca58282
JB		 561static void i915_hotplug_work_func(struct work_struct *work)
562{
563 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
564 hotplug_work);
565 struct drm_device *dev = dev_priv->dev;
c31c4ba3 566 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 567 struct intel_connector *intel_connector;
568 struct intel_encoder *intel_encoder;
569 struct drm_connector *connector;
570 unsigned long irqflags;
571 bool hpd_disabled = false;
321a1b30 572 bool changed = false;
142e2398 573 u32 hpd_event_bits;
4ef69c7a 574
52d7eced
DV		 575 /* HPD irq before everything is fully set up. */
576 if (!dev_priv->enable_hotplug_processing)
577 return;
578
a65e34c7 579 mutex_lock(&mode_config->mutex);
e67189ab
JB		 580 DRM_DEBUG_KMS("running encoder hotplug functions\n");
581
cd569aed 582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 583
584 hpd_event_bits = dev_priv->hpd_event_bits;
585 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 586 list_for_each_entry(connector, &mode_config->connector_list, head) {
587 intel_connector = to_intel_connector(connector);
588 intel_encoder = intel_connector->encoder;
589 if (intel_encoder->hpd_pin > HPD_NONE &&
590 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
591 connector->polled == DRM_CONNECTOR_POLL_HPD) {
592 DRM_INFO("HPD interrupt storm detected on connector %s: "
593 "switching from hotplug detection to polling\n",
594 drm_get_connector_name(connector));
595 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
596 connector->polled = DRM_CONNECTOR_POLL_CONNECT
597 | DRM_CONNECTOR_POLL_DISCONNECT;
598 hpd_disabled = true;
599 }
142e2398
EE		 600 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
601 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
602 drm_get_connector_name(connector), intel_encoder->hpd_pin);
603 }
cd569aed
EE		 604 }
605 /* if there were no outputs to poll, poll was disabled,
606 * therefore make sure it's enabled when disabling HPD on
607 * some connectors */
ac4c16c5 608 if (hpd_disabled) {
cd569aed 609 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 610 mod_timer(&dev_priv->hotplug_reenable_timer,
611 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
612 }
cd569aed
EE		 613
614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
615
321a1b30
EE		 616 list_for_each_entry(connector, &mode_config->connector_list, head) {
617 intel_connector = to_intel_connector(connector);
618 intel_encoder = intel_connector->encoder;
619 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
620 if (intel_encoder->hot_plug)
621 intel_encoder->hot_plug(intel_encoder);
622 if (intel_hpd_irq_event(dev, connector))
623 changed = true;
624 }
625 }
40ee3381
KP		 626 mutex_unlock(&mode_config->mutex);
627
321a1b30
EE		 628 if (changed)
629 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 630}
631
73edd18f 632static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 633{
634 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 635 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 636 u8 new_delay;
637 unsigned long flags;
638
639 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 640
73edd18f
DV		 641 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
642
20e4d407 643 new_delay = dev_priv->ips.cur_delay;
9270388e 644
7648fa99 645 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 646 busy_up = I915_READ(RCPREVBSYTUPAVG);
647 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 648 max_avg = I915_READ(RCBMAXAVG);
649 min_avg = I915_READ(RCBMINAVG);
650
651 /* Handle RCS change request from hw */
b5b72e89 652 if (busy_up > max_avg) {
20e4d407
DV		 653 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
654 new_delay = dev_priv->ips.cur_delay - 1;
655 if (new_delay < dev_priv->ips.max_delay)
656 new_delay = dev_priv->ips.max_delay;
b5b72e89 657 } else if (busy_down < min_avg) {
20e4d407
DV		 658 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
659 new_delay = dev_priv->ips.cur_delay + 1;
660 if (new_delay > dev_priv->ips.min_delay)
661 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 662 }
663
7648fa99 664 if (ironlake_set_drps(dev, new_delay))
20e4d407 665 dev_priv->ips.cur_delay = new_delay;
f97108d1 666
9270388e
DV		 667 spin_unlock_irqrestore(&mchdev_lock, flags);
668
f97108d1
JB		 669 return;
670}
671
549f7365
CW		 672static void notify_ring(struct drm_device *dev,
673 struct intel_ring_buffer *ring)
674{
675 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 676
475553de
CW		 677 if (ring->obj == NULL)
678 return;
679
b2eadbc8 680 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 681
549f7365 682 wake_up_all(&ring->irq_queue);
3e0dc6b0 683 if (i915_enable_hangcheck) {
99584db3 684 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 685 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 686 }
549f7365
CW		 687}
688
4912d041 689static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 690{
4912d041 691 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 692 rps.work);
4912d041 693 u32 pm_iir, pm_imr;
7b9e0ae6 694 u8 new_delay;
4912d041 695
c6a828d3
DV		 696 spin_lock_irq(&dev_priv->rps.lock);
697 pm_iir = dev_priv->rps.pm_iir;
698 dev_priv->rps.pm_iir = 0;
4912d041 699 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 700 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
701 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 702 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 703
4848405c 704 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 705 return;
706
4fc688ce 707 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 708
7425034a 709 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 710 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 711
712 /*
713 * For better performance, jump directly
714 * to RPe if we're below it.
715 */
716 if (IS_VALLEYVIEW(dev_priv->dev) &&
717 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
718 new_delay = dev_priv->rps.rpe_delay;
719 } else
c6a828d3 720 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 721
79249636
BW		 722 /* sysfs frequency interfaces may have snuck in while servicing the
723 * interrupt
724 */
d8289c9e
VS		 725 if (new_delay >= dev_priv->rps.min_delay &&
726 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 727 if (IS_VALLEYVIEW(dev_priv->dev))
728 valleyview_set_rps(dev_priv->dev, new_delay);
729 else
730 gen6_set_rps(dev_priv->dev, new_delay);
79249636 731 }
3b8d8d91 732
52ceb908
JB		 733 if (IS_VALLEYVIEW(dev_priv->dev)) {
734 /*
735 * On VLV, when we enter RC6 we may not be at the minimum
736 * voltage level, so arm a timer to check. It should only
737 * fire when there's activity or once after we've entered
738 * RC6, and then won't be re-armed until the next RPS interrupt.
739 */
740 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
741 msecs_to_jiffies(100));
742 }
743
4fc688ce 744 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 745}
746
e3689190
BW		 747
748/**
749 * ivybridge_parity_work - Workqueue called when a parity error interrupt
750 * occurred.
751 * @work: workqueue struct
752 *
753 * Doesn't actually do anything except notify userspace. As a consequence of
754 * this event, userspace should try to remap the bad rows since statistically
755 * it is likely the same row is more likely to go bad again.
756 */
757static void ivybridge_parity_work(struct work_struct *work)
758{
759 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 760 l3_parity.error_work);
e3689190
BW		 761 u32 error_status, row, bank, subbank;
762 char *parity_event[5];
763 uint32_t misccpctl;
764 unsigned long flags;
765
766 /* We must turn off DOP level clock gating to access the L3 registers.
767 * In order to prevent a get/put style interface, acquire struct mutex
768 * any time we access those registers.
769 */
770 mutex_lock(&dev_priv->dev->struct_mutex);
771
772 misccpctl = I915_READ(GEN7_MISCCPCTL);
773 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
774 POSTING_READ(GEN7_MISCCPCTL);
775
776 error_status = I915_READ(GEN7_L3CDERRST1);
777 row = GEN7_PARITY_ERROR_ROW(error_status);
778 bank = GEN7_PARITY_ERROR_BANK(error_status);
779 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
780
781 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
782 GEN7_L3CDERRST1_ENABLE);
783 POSTING_READ(GEN7_L3CDERRST1);
784
785 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
786
787 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 788 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 789 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
790 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
791
792 mutex_unlock(&dev_priv->dev->struct_mutex);
793
794 parity_event[0] = "L3_PARITY_ERROR=1";
795 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
796 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
797 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
798 parity_event[4] = NULL;
799
800 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
801 KOBJ_CHANGE, parity_event);
802
803 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
804 row, bank, subbank);
805
806 kfree(parity_event[3]);
807 kfree(parity_event[2]);
808 kfree(parity_event[1]);
809}
810
d2ba8470 811static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 812{
813 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
814 unsigned long flags;
815
e1ef7cc2 816 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 817 return;
818
819 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 820 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 821 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
822 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
823
a4da4fa4 824 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 825}
826
e7b4c6b1
DV		 827static void snb_gt_irq_handler(struct drm_device *dev,
828 struct drm_i915_private *dev_priv,
829 u32 gt_iir)
830{
831
cc609d5d
BW		 832 if (gt_iir &
833 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 834 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 835 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 836 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 837 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 838 notify_ring(dev, &dev_priv->ring[BCS]);
839
cc609d5d
BW		 840 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
841 GT_BSD_CS_ERROR_INTERRUPT |
842 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 843 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
844 i915_handle_error(dev, false);
845 }
e3689190 846
cc609d5d 847 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
e3689190 848 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 849}
850
baf02a1f 851/* Legacy way of handling PM interrupts */
fc6826d1
CW		 852static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
853 u32 pm_iir)
854{
855 unsigned long flags;
856
857 /*
858 * IIR bits should never already be set because IMR should
859 * prevent an interrupt from being shown in IIR. The warning
860 * displays a case where we've unsafely cleared
c6a828d3 861 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 862 * type is not a problem, it displays a problem in the logic.
863 *
c6a828d3 864 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 865 */
866
c6a828d3 867 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 868 dev_priv->rps.pm_iir |= pm_iir;
869 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 870 POSTING_READ(GEN6_PMIMR);
c6a828d3 871 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 872
c6a828d3 873 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 874}
875
b543fb04
EE		 876#define HPD_STORM_DETECT_PERIOD 1000
877#define HPD_STORM_THRESHOLD 5
878
10a504de 879static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 880 u32 hotplug_trigger,
881 const u32 *hpd)
b543fb04
EE		 882{
883 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 884 int i;
10a504de 885 bool storm_detected = false;
b543fb04 886
91d131d2
DV		 887 if (!hotplug_trigger)
888 return;
889
b5ea2d56 890 spin_lock(&dev_priv->irq_lock);
b543fb04 891 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 892
b543fb04
EE		 893 if (!(hpd[i] & hotplug_trigger) ||
894 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
895 continue;
896
bc5ead8c 897 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 898 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
899 dev_priv->hpd_stats[i].hpd_last_jiffies
900 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
901 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
902 dev_priv->hpd_stats[i].hpd_cnt = 0;
903 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
904 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 905 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 906 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 907 storm_detected = true;
b543fb04
EE		 908 } else {
909 dev_priv->hpd_stats[i].hpd_cnt++;
910 }
911 }
912
10a504de
DV		 913 if (storm_detected)
914 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 915 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 916
917 queue_work(dev_priv->wq,
918 &dev_priv->hotplug_work);
b543fb04
EE		 919}
920
515ac2bb
DV		 921static void gmbus_irq_handler(struct drm_device *dev)
922{
28c70f16
DV		 923 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
924
28c70f16 925 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 926}
927
ce99c256
DV		 928static void dp_aux_irq_handler(struct drm_device *dev)
929{
9ee32fea
DV		 930 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
931
9ee32fea 932 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 933}
934
baf02a1f
BW		 935/* Unlike gen6_queue_rps_work() from which this function is originally derived,
936 * we must be able to deal with other PM interrupts. This is complicated because
937 * of the way in which we use the masks to defer the RPS work (which for
938 * posterity is necessary because of forcewake).
939 */
940static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
941 u32 pm_iir)
942{
943 unsigned long flags;
944
945 spin_lock_irqsave(&dev_priv->rps.lock, flags);
4848405c 946 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 947 if (dev_priv->rps.pm_iir) {
948 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
949 /* never want to mask useful interrupts. (also posting read) */
4848405c 950 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 951 /* TODO: if queue_work is slow, move it out of the spinlock */
952 queue_work(dev_priv->wq, &dev_priv->rps.work);
953 }
954 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
955
12638c57
BW		 956 if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
957 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
958 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
959
960 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
961 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
962 i915_handle_error(dev_priv->dev, false);
963 }
964 }
baf02a1f
BW		 965}
966
ff1f525e 967static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 968{
969 struct drm_device *dev = (struct drm_device *) arg;
970 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
971 u32 iir, gt_iir, pm_iir;
972 irqreturn_t ret = IRQ_NONE;
973 unsigned long irqflags;
974 int pipe;
975 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 976
977 atomic_inc(&dev_priv->irq_received);
978
7e231dbe
JB		 979 while (true) {
980 iir = I915_READ(VLV_IIR);
981 gt_iir = I915_READ(GTIIR);
982 pm_iir = I915_READ(GEN6_PMIIR);
983
984 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
985 goto out;
986
987 ret = IRQ_HANDLED;
988
e7b4c6b1 989 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 990
991 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
992 for_each_pipe(pipe) {
993 int reg = PIPESTAT(pipe);
994 pipe_stats[pipe] = I915_READ(reg);
995
996 /*
997 * Clear the PIPE*STAT regs before the IIR
998 */
999 if (pipe_stats[pipe] & 0x8000ffff) {
1000 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1001 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1002 pipe_name(pipe));
1003 I915_WRITE(reg, pipe_stats[pipe]);
1004 }
1005 }
1006 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1007
31acc7f5
JB		 1008 for_each_pipe(pipe) {
1009 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1010 drm_handle_vblank(dev, pipe);
1011
1012 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1013 intel_prepare_page_flip(dev, pipe);
1014 intel_finish_page_flip(dev, pipe);
1015 }
1016 }
1017
7e231dbe
JB		 1018 /* Consume port. Then clear IIR or we'll miss events */
1019 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1020 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1021 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1022
1023 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1024 hotplug_status);
91d131d2
DV		 1025
1026 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1027
7e231dbe
JB		 1028 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1029 I915_READ(PORT_HOTPLUG_STAT);
1030 }
1031
515ac2bb
DV		 1032 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1033 gmbus_irq_handler(dev);
7e231dbe 1034
4848405c 1035 if (pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1036 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 1037
1038 I915_WRITE(GTIIR, gt_iir);
1039 I915_WRITE(GEN6_PMIIR, pm_iir);
1040 I915_WRITE(VLV_IIR, iir);
1041 }
1042
1043out:
1044 return ret;
1045}
1046
23e81d69 1047static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1048{
1049 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1050 int pipe;
b543fb04 1051 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1052
91d131d2
DV		 1053 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1054
cfc33bf7
VS		 1055 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1056 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1057 SDE_AUDIO_POWER_SHIFT);
776ad806 1058 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1059 port_name(port));
1060 }
776ad806 1061
ce99c256
DV		 1062 if (pch_iir & SDE_AUX_MASK)
1063 dp_aux_irq_handler(dev);
1064
776ad806 1065 if (pch_iir & SDE_GMBUS)
515ac2bb 1066 gmbus_irq_handler(dev);
776ad806
JB		 1067
1068 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1069 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1070
1071 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1072 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1073
1074 if (pch_iir & SDE_POISON)
1075 DRM_ERROR("PCH poison interrupt\n");
1076
9db4a9c7
JB		 1077 if (pch_iir & SDE_FDI_MASK)
1078 for_each_pipe(pipe)
1079 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1080 pipe_name(pipe),
1081 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1082
1083 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1084 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1085
1086 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1087 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1088
776ad806 1089 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1090 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1091 false))
1092 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1093
1094 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1095 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1096 false))
1097 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1098}
1099
1100static void ivb_err_int_handler(struct drm_device *dev)
1101{
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 u32 err_int = I915_READ(GEN7_ERR_INT);
1104
de032bf4
PZ		 1105 if (err_int & ERR_INT_POISON)
1106 DRM_ERROR("Poison interrupt\n");
1107
8664281b
PZ		 1108 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1109 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1110 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1111
1112 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1113 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1114 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1115
1116 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1117 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1118 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1119
1120 I915_WRITE(GEN7_ERR_INT, err_int);
1121}
1122
1123static void cpt_serr_int_handler(struct drm_device *dev)
1124{
1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 u32 serr_int = I915_READ(SERR_INT);
1127
de032bf4
PZ		 1128 if (serr_int & SERR_INT_POISON)
1129 DRM_ERROR("PCH poison interrupt\n");
1130
8664281b
PZ		 1131 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1132 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1133 false))
1134 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1135
1136 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1137 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1138 false))
1139 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1140
1141 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1142 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1143 false))
1144 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1145
1146 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1147}
1148
23e81d69
AJ		 1149static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1150{
1151 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1152 int pipe;
b543fb04 1153 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1154
91d131d2
DV		 1155 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1156
cfc33bf7
VS		 1157 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1158 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1159 SDE_AUDIO_POWER_SHIFT_CPT);
1160 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1161 port_name(port));
1162 }
23e81d69
AJ		 1163
1164 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1165 dp_aux_irq_handler(dev);
23e81d69
AJ		 1166
1167 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1168 gmbus_irq_handler(dev);
23e81d69
AJ		 1169
1170 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1171 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1172
1173 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1174 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1175
1176 if (pch_iir & SDE_FDI_MASK_CPT)
1177 for_each_pipe(pipe)
1178 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1179 pipe_name(pipe),
1180 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1181
1182 if (pch_iir & SDE_ERROR_CPT)
1183 cpt_serr_int_handler(dev);
23e81d69
AJ		 1184}
1185
ff1f525e 1186static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1187{
1188 struct drm_device *dev = (struct drm_device *) arg;
1189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1190 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1191 irqreturn_t ret = IRQ_NONE;
1192 int i;
b1f14ad0
JB		 1193
1194 atomic_inc(&dev_priv->irq_received);
1195
8664281b
PZ		 1196 /* We get interrupts on unclaimed registers, so check for this before we
1197 * do any I915_{READ,WRITE}. */
1198 if (IS_HASWELL(dev) &&
1199 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1200 DRM_ERROR("Unclaimed register before interrupt\n");
1201 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1202 }
1203
b1f14ad0
JB		 1204 /* disable master interrupt before clearing iir */
1205 de_ier = I915_READ(DEIER);
1206 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1207
44498aea
PZ		 1208 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1209 * interrupts will will be stored on its back queue, and then we'll be
1210 * able to process them after we restore SDEIER (as soon as we restore
1211 * it, we'll get an interrupt if SDEIIR still has something to process
1212 * due to its back queue). */
ab5c608b
BW		 1213 if (!HAS_PCH_NOP(dev)) {
1214 sde_ier = I915_READ(SDEIER);
1215 I915_WRITE(SDEIER, 0);
1216 POSTING_READ(SDEIER);
1217 }
44498aea 1218
8664281b
PZ		 1219 /* On Haswell, also mask ERR_INT because we don't want to risk
1220 * generating "unclaimed register" interrupts from inside the interrupt
1221 * handler. */
4bc9d430
DV		 1222 if (IS_HASWELL(dev)) {
1223 spin_lock(&dev_priv->irq_lock);
8664281b 1224 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1225 spin_unlock(&dev_priv->irq_lock);
1226 }
8664281b 1227
b1f14ad0 1228 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1229 if (gt_iir) {
1230 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1231 I915_WRITE(GTIIR, gt_iir);
1232 ret = IRQ_HANDLED;
b1f14ad0
JB		 1233 }
1234
0e43406b
CW		 1235 de_iir = I915_READ(DEIIR);
1236 if (de_iir) {
8664281b
PZ		 1237 if (de_iir & DE_ERR_INT_IVB)
1238 ivb_err_int_handler(dev);
1239
ce99c256
DV		 1240 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1241 dp_aux_irq_handler(dev);
1242
0e43406b 1243 if (de_iir & DE_GSE_IVB)
81a07809 1244 intel_opregion_asle_intr(dev);
0e43406b
CW		 1245
1246 for (i = 0; i < 3; i++) {
74d44445
DV		 1247 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1248 drm_handle_vblank(dev, i);
0e43406b
CW		 1249 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1250 intel_prepare_page_flip(dev, i);
1251 intel_finish_page_flip_plane(dev, i);
1252 }
0e43406b 1253 }
b615b57a 1254
0e43406b 1255 /* check event from PCH */
ab5c608b 1256 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1257 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1258
23e81d69 1259 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1260
0e43406b
CW		 1261 /* clear PCH hotplug event before clear CPU irq */
1262 I915_WRITE(SDEIIR, pch_iir);
1263 }
b615b57a 1264
0e43406b
CW		 1265 I915_WRITE(DEIIR, de_iir);
1266 ret = IRQ_HANDLED;
b1f14ad0
JB		 1267 }
1268
0e43406b
CW		 1269 pm_iir = I915_READ(GEN6_PMIIR);
1270 if (pm_iir) {
baf02a1f
BW		 1271 if (IS_HASWELL(dev))
1272 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1273 else if (pm_iir & GEN6_PM_RPS_EVENTS)
0e43406b
CW		 1274 gen6_queue_rps_work(dev_priv, pm_iir);
1275 I915_WRITE(GEN6_PMIIR, pm_iir);
1276 ret = IRQ_HANDLED;
1277 }
b1f14ad0 1278
4bc9d430
DV		 1279 if (IS_HASWELL(dev)) {
1280 spin_lock(&dev_priv->irq_lock);
1281 if (ivb_can_enable_err_int(dev))
1282 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1283 spin_unlock(&dev_priv->irq_lock);
1284 }
8664281b 1285
b1f14ad0
JB		 1286 I915_WRITE(DEIER, de_ier);
1287 POSTING_READ(DEIER);
ab5c608b
BW		 1288 if (!HAS_PCH_NOP(dev)) {
1289 I915_WRITE(SDEIER, sde_ier);
1290 POSTING_READ(SDEIER);
1291 }
b1f14ad0
JB		 1292
1293 return ret;
1294}
1295
e7b4c6b1
DV		 1296static void ilk_gt_irq_handler(struct drm_device *dev,
1297 struct drm_i915_private *dev_priv,
1298 u32 gt_iir)
1299{
cc609d5d
BW		 1300 if (gt_iir &
1301 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1302 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1303 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1304 notify_ring(dev, &dev_priv->ring[VCS]);
1305}
1306
ff1f525e 1307static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1308{
4697995b 1309 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1311 int ret = IRQ_NONE;
44498aea 1312 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1313
4697995b
JB		 1314 atomic_inc(&dev_priv->irq_received);
1315
2d109a84
ZN		 1316 /* disable master interrupt before clearing iir */
1317 de_ier = I915_READ(DEIER);
1318 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1319 POSTING_READ(DEIER);
2d109a84 1320
44498aea
PZ		 1321 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1322 * interrupts will will be stored on its back queue, and then we'll be
1323 * able to process them after we restore SDEIER (as soon as we restore
1324 * it, we'll get an interrupt if SDEIIR still has something to process
1325 * due to its back queue). */
1326 sde_ier = I915_READ(SDEIER);
1327 I915_WRITE(SDEIER, 0);
1328 POSTING_READ(SDEIER);
1329
036a4a7d
ZW		 1330 de_iir = I915_READ(DEIIR);
1331 gt_iir = I915_READ(GTIIR);
3b8d8d91 1332 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1333
acd15b6c 1334 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1335 goto done;
036a4a7d 1336
c7c85101 1337 ret = IRQ_HANDLED;
036a4a7d 1338
e7b4c6b1
DV		 1339 if (IS_GEN5(dev))
1340 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1341 else
1342 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1343
ce99c256
DV		 1344 if (de_iir & DE_AUX_CHANNEL_A)
1345 dp_aux_irq_handler(dev);
1346
c7c85101 1347 if (de_iir & DE_GSE)
81a07809 1348 intel_opregion_asle_intr(dev);
c650156a 1349
74d44445
DV		 1350 if (de_iir & DE_PIPEA_VBLANK)
1351 drm_handle_vblank(dev, 0);
1352
1353 if (de_iir & DE_PIPEB_VBLANK)
1354 drm_handle_vblank(dev, 1);
1355
de032bf4
PZ		 1356 if (de_iir & DE_POISON)
1357 DRM_ERROR("Poison interrupt\n");
1358
8664281b
PZ		 1359 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1360 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1361 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1362
1363 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1364 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1365 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1366
f072d2e7 1367 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1368 intel_prepare_page_flip(dev, 0);
2bbda389 1369 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1370 }
013d5aa2 1371
f072d2e7 1372 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1373 intel_prepare_page_flip(dev, 1);
2bbda389 1374 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1375 }
013d5aa2 1376
c7c85101 1377 /* check event from PCH */
776ad806 1378 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1379 u32 pch_iir = I915_READ(SDEIIR);
1380
23e81d69
AJ		 1381 if (HAS_PCH_CPT(dev))
1382 cpt_irq_handler(dev, pch_iir);
1383 else
1384 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1385
1386 /* should clear PCH hotplug event before clear CPU irq */
1387 I915_WRITE(SDEIIR, pch_iir);
776ad806 1388 }
036a4a7d 1389
73edd18f
DV		 1390 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1391 ironlake_handle_rps_change(dev);
f97108d1 1392
4848405c 1393 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
fc6826d1 1394 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1395
c7c85101
ZN		 1396 I915_WRITE(GTIIR, gt_iir);
1397 I915_WRITE(DEIIR, de_iir);
4912d041 1398 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1399
1400done:
2d109a84 1401 I915_WRITE(DEIER, de_ier);
3143a2bf 1402 POSTING_READ(DEIER);
44498aea
PZ		 1403 I915_WRITE(SDEIER, sde_ier);
1404 POSTING_READ(SDEIER);
2d109a84 1405
036a4a7d
ZW		 1406 return ret;
1407}
1408
8a905236
JB		 1409/**
1410 * i915_error_work_func - do process context error handling work
1411 * @work: work struct
1412 *
1413 * Fire an error uevent so userspace can see that a hang or error
1414 * was detected.
1415 */
1416static void i915_error_work_func(struct work_struct *work)
1417{
1f83fee0
DV		 1418 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1419 work);
1420 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1421 gpu_error);
8a905236 1422 struct drm_device *dev = dev_priv->dev;
f69061be 1423 struct intel_ring_buffer *ring;
f316a42c
BG		 1424 char *error_event[] = { "ERROR=1", NULL };
1425 char *reset_event[] = { "RESET=1", NULL };
1426 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1427 int i, ret;
8a905236 1428
f316a42c
BG		 1429 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1430
7db0ba24
DV		 1431 /*
1432 * Note that there's only one work item which does gpu resets, so we
1433 * need not worry about concurrent gpu resets potentially incrementing
1434 * error->reset_counter twice. We only need to take care of another
1435 * racing irq/hangcheck declaring the gpu dead for a second time. A
1436 * quick check for that is good enough: schedule_work ensures the
1437 * correct ordering between hang detection and this work item, and since
1438 * the reset in-progress bit is only ever set by code outside of this
1439 * work we don't need to worry about any other races.
1440 */
1441 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1442 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1443 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1444 reset_event);
1f83fee0 1445
f69061be
DV		 1446 ret = i915_reset(dev);
1447
1448 if (ret == 0) {
1449 /*
1450 * After all the gem state is reset, increment the reset
1451 * counter and wake up everyone waiting for the reset to
1452 * complete.
1453 *
1454 * Since unlock operations are a one-sided barrier only,
1455 * we need to insert a barrier here to order any seqno
1456 * updates before
1457 * the counter increment.
1458 */
1459 smp_mb__before_atomic_inc();
1460 atomic_inc(&dev_priv->gpu_error.reset_counter);
1461
1462 kobject_uevent_env(&dev->primary->kdev.kobj,
1463 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1464 } else {
1465 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1466 }
1f83fee0 1467
f69061be
DV		 1468 for_each_ring(ring, dev_priv, i)
1469 wake_up_all(&ring->irq_queue);
1470
96a02917
VS		 1471 intel_display_handle_reset(dev);
1472
1f83fee0 1473 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1474 }
8a905236
JB		 1475}
1476
85f9e50d
DV		 1477/* NB: please notice the memset */
1478static void i915_get_extra_instdone(struct drm_device *dev,
1479 uint32_t *instdone)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1483
1484 switch(INTEL_INFO(dev)->gen) {
1485 case 2:
1486 case 3:
1487 instdone[0] = I915_READ(INSTDONE);
1488 break;
1489 case 4:
1490 case 5:
1491 case 6:
1492 instdone[0] = I915_READ(INSTDONE_I965);
1493 instdone[1] = I915_READ(INSTDONE1);
1494 break;
1495 default:
1496 WARN_ONCE(1, "Unsupported platform\n");
1497 case 7:
1498 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1499 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1500 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1501 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1502 break;
1503 }
1504}
1505
3bd3c932 1506#ifdef CONFIG_DEBUG_FS
9df30794 1507static struct drm_i915_error_object *
d0d045e8
BW		 1508i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1509 struct drm_i915_gem_object *src,
1510 const int num_pages)
9df30794
CW		 1511{
1512 struct drm_i915_error_object *dst;
d0d045e8 1513 int i;
e56660dd 1514 u32 reloc_offset;
9df30794 1515
05394f39 1516 if (src == NULL || src->pages == NULL)
9df30794
CW		 1517 return NULL;
1518
d0d045e8 1519 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1520 if (dst == NULL)
1521 return NULL;
1522
05394f39 1523 reloc_offset = src->gtt_offset;
d0d045e8 1524 for (i = 0; i < num_pages; i++) {
788885ae 1525 unsigned long flags;
e56660dd 1526 void *d;
788885ae 1527
e56660dd 1528 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1529 if (d == NULL)
1530 goto unwind;
e56660dd 1531
788885ae 1532 local_irq_save(flags);
5d4545ae 1533 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1534 src->has_global_gtt_mapping) {
172975aa
CW		 1535 void __iomem *s;
1536
1537 /* Simply ignore tiling or any overlapping fence.
1538 * It's part of the error state, and this hopefully
1539 * captures what the GPU read.
1540 */
1541
5d4545ae 1542 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1543 reloc_offset);
1544 memcpy_fromio(d, s, PAGE_SIZE);
1545 io_mapping_unmap_atomic(s);
960e3564
CW		 1546 } else if (src->stolen) {
1547 unsigned long offset;
1548
1549 offset = dev_priv->mm.stolen_base;
1550 offset += src->stolen->start;
1551 offset += i << PAGE_SHIFT;
1552
1a240d4d 1553 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1554 } else {
9da3da66 1555 struct page *page;
172975aa
CW		 1556 void *s;
1557
9da3da66 1558 page = i915_gem_object_get_page(src, i);
172975aa 1559
9da3da66
CW		 1560 drm_clflush_pages(&page, 1);
1561
1562 s = kmap_atomic(page);
172975aa
CW		 1563 memcpy(d, s, PAGE_SIZE);
1564 kunmap_atomic(s);
1565
9da3da66 1566 drm_clflush_pages(&page, 1);
172975aa 1567 }
788885ae 1568 local_irq_restore(flags);
e56660dd 1569
9da3da66 1570 dst->pages[i] = d;
e56660dd
CW		 1571
1572 reloc_offset += PAGE_SIZE;
9df30794 1573 }
d0d045e8 1574 dst->page_count = num_pages;
05394f39 1575 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1576
1577 return dst;
1578
1579unwind:
9da3da66
CW		 1580 while (i--)
1581 kfree(dst->pages[i]);
9df30794
CW		 1582 kfree(dst);
1583 return NULL;
1584}
d0d045e8
BW		 1585#define i915_error_object_create(dev_priv, src) \
1586 i915_error_object_create_sized((dev_priv), (src), \
1587 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1588
1589static void
1590i915_error_object_free(struct drm_i915_error_object *obj)
1591{
1592 int page;
1593
1594 if (obj == NULL)
1595 return;
1596
1597 for (page = 0; page < obj->page_count; page++)
1598 kfree(obj->pages[page]);
1599
1600 kfree(obj);
1601}
1602
742cbee8
DV		 1603void
1604i915_error_state_free(struct kref *error_ref)
9df30794 1605{
742cbee8
DV		 1606 struct drm_i915_error_state *error = container_of(error_ref,
1607 typeof(*error), ref);
e2f973d5
CW		 1608 int i;
1609
52d39a21
CW		 1610 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1611 i915_error_object_free(error->ring[i].batchbuffer);
1612 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1613 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1614 kfree(error->ring[i].requests);
1615 }
e2f973d5 1616
9df30794 1617 kfree(error->active_bo);
6ef3d427 1618 kfree(error->overlay);
7ed73da0 1619 kfree(error->display);
9df30794
CW		 1620 kfree(error);
1621}
1b50247a
CW		 1622static void capture_bo(struct drm_i915_error_buffer *err,
1623 struct drm_i915_gem_object *obj)
1624{
1625 err->size = obj->base.size;
1626 err->name = obj->base.name;
0201f1ec
CW		 1627 err->rseqno = obj->last_read_seqno;
1628 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1629 err->gtt_offset = obj->gtt_offset;
1630 err->read_domains = obj->base.read_domains;
1631 err->write_domain = obj->base.write_domain;
1632 err->fence_reg = obj->fence_reg;
1633 err->pinned = 0;
1634 if (obj->pin_count > 0)
1635 err->pinned = 1;
1636 if (obj->user_pin_count > 0)
1637 err->pinned = -1;
1638 err->tiling = obj->tiling_mode;
1639 err->dirty = obj->dirty;
1640 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1641 err->ring = obj->ring ? obj->ring->id : -1;
1642 err->cache_level = obj->cache_level;
1643}
9df30794 1644
1b50247a
CW		 1645static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1646 int count, struct list_head *head)
c724e8a9
CW		 1647{
1648 struct drm_i915_gem_object *obj;
1649 int i = 0;
1650
1651 list_for_each_entry(obj, head, mm_list) {
1b50247a 1652 capture_bo(err++, obj);
c724e8a9
CW		 1653 if (++i == count)
1654 break;
1b50247a
CW		 1655 }
1656
1657 return i;
1658}
1659
1660static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1661 int count, struct list_head *head)
1662{
1663 struct drm_i915_gem_object *obj;
1664 int i = 0;
1665
35c20a60 1666 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1667 if (obj->pin_count == 0)
1668 continue;
c724e8a9 1669
1b50247a
CW		 1670 capture_bo(err++, obj);
1671 if (++i == count)
1672 break;
c724e8a9
CW		 1673 }
1674
1675 return i;
1676}
1677
748ebc60
CW		 1678static void i915_gem_record_fences(struct drm_device *dev,
1679 struct drm_i915_error_state *error)
1680{
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 int i;
1683
1684 /* Fences */
1685 switch (INTEL_INFO(dev)->gen) {
775d17b6 1686 case 7:
748ebc60 1687 case 6:
42b5aeab 1688 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1689 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1690 break;
1691 case 5:
1692 case 4:
1693 for (i = 0; i < 16; i++)
1694 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1695 break;
1696 case 3:
1697 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1698 for (i = 0; i < 8; i++)
1699 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1700 case 2:
1701 for (i = 0; i < 8; i++)
1702 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1703 break;
1704
7dbf9d6e
BW		 1705 default:
1706 BUG();
748ebc60
CW		 1707 }
1708}
1709
bcfb2e28
CW		 1710static struct drm_i915_error_object *
1711i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1712 struct intel_ring_buffer *ring)
1713{
1714 struct drm_i915_gem_object *obj;
1715 u32 seqno;
1716
1717 if (!ring->get_seqno)
1718 return NULL;
1719
b45305fc
DV		 1720 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1721 u32 acthd = I915_READ(ACTHD);
1722
1723 if (WARN_ON(ring->id != RCS))
1724 return NULL;
1725
1726 obj = ring->private;
1727 if (acthd >= obj->gtt_offset &&
1728 acthd < obj->gtt_offset + obj->base.size)
1729 return i915_error_object_create(dev_priv, obj);
1730 }
1731
b2eadbc8 1732 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1733 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1734 if (obj->ring != ring)
1735 continue;
1736
0201f1ec 1737 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1738 continue;
1739
1740 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1741 continue;
1742
1743 /* We need to copy these to an anonymous buffer as the simplest
1744 * method to avoid being overwritten by userspace.
1745 */
1746 return i915_error_object_create(dev_priv, obj);
1747 }
1748
1749 return NULL;
1750}
1751
d27b1e0e
DV		 1752static void i915_record_ring_state(struct drm_device *dev,
1753 struct drm_i915_error_state *error,
1754 struct intel_ring_buffer *ring)
1755{
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757
33f3f518 1758 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1759 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1760 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1761 error->semaphore_mboxes[ring->id][0]
1762 = I915_READ(RING_SYNC_0(ring->mmio_base));
1763 error->semaphore_mboxes[ring->id][1]
1764 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1765 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1766 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1767 }
c1cd90ed 1768
d27b1e0e 1769 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1770 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1771 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1772 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1773 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1774 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1775 if (ring->id == RCS)
d27b1e0e 1776 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1777 } else {
9d2f41fa 1778 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1779 error->ipeir[ring->id] = I915_READ(IPEIR);
1780 error->ipehr[ring->id] = I915_READ(IPEHR);
1781 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1782 }
1783
9574b3fe 1784 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1785 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1786 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1787 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1788 error->head[ring->id] = I915_READ_HEAD(ring);
1789 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1790 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1791
1792 error->cpu_ring_head[ring->id] = ring->head;
1793 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1794}
1795
8c123e54
BW		 1796
1797static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1798 struct drm_i915_error_state *error,
1799 struct drm_i915_error_ring *ering)
1800{
1801 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1802 struct drm_i915_gem_object *obj;
1803
1804 /* Currently render ring is the only HW context user */
1805 if (ring->id != RCS || !error->ccid)
1806 return;
1807
35c20a60 1808 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
8c123e54
BW		 1809 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1810 ering->ctx = i915_error_object_create_sized(dev_priv,
1811 obj, 1);
3ef8fb5a 1812 break;
8c123e54
BW		 1813 }
1814 }
1815}
1816
52d39a21
CW		 1817static void i915_gem_record_rings(struct drm_device *dev,
1818 struct drm_i915_error_state *error)
1819{
1820 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1821 struct intel_ring_buffer *ring;
52d39a21
CW		 1822 struct drm_i915_gem_request *request;
1823 int i, count;
1824
b4519513 1825 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1826 i915_record_ring_state(dev, error, ring);
1827
1828 error->ring[i].batchbuffer =
1829 i915_error_first_batchbuffer(dev_priv, ring);
1830
1831 error->ring[i].ringbuffer =
1832 i915_error_object_create(dev_priv, ring->obj);
1833
8c123e54
BW		 1834
1835 i915_gem_record_active_context(ring, error, &error->ring[i]);
1836
52d39a21
CW		 1837 count = 0;
1838 list_for_each_entry(request, &ring->request_list, list)
1839 count++;
1840
1841 error->ring[i].num_requests = count;
1842 error->ring[i].requests =
1843 kmalloc(count*sizeof(struct drm_i915_error_request),
1844 GFP_ATOMIC);
1845 if (error->ring[i].requests == NULL) {
1846 error->ring[i].num_requests = 0;
1847 continue;
1848 }
1849
1850 count = 0;
1851 list_for_each_entry(request, &ring->request_list, list) {
1852 struct drm_i915_error_request *erq;
1853
1854 erq = &error->ring[i].requests[count++];
1855 erq->seqno = request->seqno;
1856 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1857 erq->tail = request->tail;
52d39a21
CW		 1858 }
1859 }
1860}
1861
26b7c224
BW		 1862static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1863 struct drm_i915_error_state *error)
1864{
1865 struct drm_i915_gem_object *obj;
1866 int i;
1867
1868 i = 0;
1869 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1870 i++;
1871 error->active_bo_count = i;
1872 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1873 if (obj->pin_count)
1874 i++;
1875 error->pinned_bo_count = i - error->active_bo_count;
1876
1877 if (i) {
1878 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1879 GFP_ATOMIC);
1880 if (error->active_bo)
1881 error->pinned_bo =
1882 error->active_bo + error->active_bo_count;
1883 }
1884
1885 if (error->active_bo)
1886 error->active_bo_count =
1887 capture_active_bo(error->active_bo,
1888 error->active_bo_count,
1889 &dev_priv->mm.active_list);
1890
1891 if (error->pinned_bo)
1892 error->pinned_bo_count =
1893 capture_pinned_bo(error->pinned_bo,
1894 error->pinned_bo_count,
1895 &dev_priv->mm.bound_list);
1896}
1897
8a905236
JB		 1898/**
1899 * i915_capture_error_state - capture an error record for later analysis
1900 * @dev: drm device
1901 *
1902 * Should be called when an error is detected (either a hang or an error
1903 * interrupt) to capture error state from the time of the error. Fills
1904 * out a structure which becomes available in debugfs for user level tools
1905 * to pick up.
1906 */
63eeaf38
JB		 1907static void i915_capture_error_state(struct drm_device *dev)
1908{
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct drm_i915_error_state *error;
1911 unsigned long flags;
26b7c224 1912 int pipe;
63eeaf38 1913
99584db3
DV		 1914 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1915 error = dev_priv->gpu_error.first_error;
1916 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1917 if (error)
1918 return;
63eeaf38 1919
9db4a9c7 1920 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1921 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1922 if (!error) {
9df30794
CW		 1923 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1924 return;
63eeaf38
JB		 1925 }
1926
5d83d294 1927 DRM_INFO("capturing error event; look for more information in "
ef86ddce 1928 "/sys/class/drm/card%d/error\n", dev->primary->index);
2fa772f3 1929
742cbee8 1930 kref_init(&error->ref);
63eeaf38
JB		 1931 error->eir = I915_READ(EIR);
1932 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1933 if (HAS_HW_CONTEXTS(dev))
1934 error->ccid = I915_READ(CCID);
be998e2e
BW		 1935
1936 if (HAS_PCH_SPLIT(dev))
1937 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1938 else if (IS_VALLEYVIEW(dev))
1939 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1940 else if (IS_GEN2(dev))
1941 error->ier = I915_READ16(IER);
1942 else
1943 error->ier = I915_READ(IER);
1944
0f3b6849
CW		 1945 if (INTEL_INFO(dev)->gen >= 6)
1946 error->derrmr = I915_READ(DERRMR);
1947
1948 if (IS_VALLEYVIEW(dev))
1949 error->forcewake = I915_READ(FORCEWAKE_VLV);
1950 else if (INTEL_INFO(dev)->gen >= 7)
1951 error->forcewake = I915_READ(FORCEWAKE_MT);
1952 else if (INTEL_INFO(dev)->gen == 6)
1953 error->forcewake = I915_READ(FORCEWAKE);
1954
4f3308b9
PZ		 1955 if (!HAS_PCH_SPLIT(dev))
1956 for_each_pipe(pipe)
1957 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1958
33f3f518 1959 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1960 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1961 error->done_reg = I915_READ(DONE_REG);
1962 }
d27b1e0e 1963
71e172e8
BW		 1964 if (INTEL_INFO(dev)->gen == 7)
1965 error->err_int = I915_READ(GEN7_ERR_INT);
1966
050ee91f
BW		 1967 i915_get_extra_instdone(dev, error->extra_instdone);
1968
26b7c224 1969 i915_gem_capture_buffers(dev_priv, error);
748ebc60 1970 i915_gem_record_fences(dev, error);
52d39a21 1971 i915_gem_record_rings(dev, error);
9df30794 1972
9df30794
CW		 1973 do_gettimeofday(&error->time);
1974
6ef3d427 1975 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1976 error->display = intel_display_capture_error_state(dev);
6ef3d427 1977
99584db3
DV		 1978 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1979 if (dev_priv->gpu_error.first_error == NULL) {
1980 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1981 error = NULL;
1982 }
99584db3 1983 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1984
1985 if (error)
742cbee8 1986 i915_error_state_free(&error->ref);
9df30794
CW		 1987}
1988
1989void i915_destroy_error_state(struct drm_device *dev)
1990{
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 struct drm_i915_error_state *error;
6dc0e816 1993 unsigned long flags;
9df30794 1994
99584db3
DV		 1995 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1996 error = dev_priv->gpu_error.first_error;
1997 dev_priv->gpu_error.first_error = NULL;
1998 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1999
2000 if (error)
742cbee8 2001 kref_put(&error->ref, i915_error_state_free);
63eeaf38 2002}
3bd3c932
CW		 2003#else
2004#define i915_capture_error_state(x)
2005#endif
63eeaf38 2006
35aed2e6 2007static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2008{
2009 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2010 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2011 u32 eir = I915_READ(EIR);
050ee91f 2012 int pipe, i;
8a905236 2013
35aed2e6
CW		 2014 if (!eir)
2015 return;
8a905236 2016
a70491cc 2017 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2018
bd9854f9
BW		 2019 i915_get_extra_instdone(dev, instdone);
2020
8a905236
JB		 2021 if (IS_G4X(dev)) {
2022 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2023 u32 ipeir = I915_READ(IPEIR_I965);
2024
a70491cc
JP		 2025 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2026 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2027 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2028 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2029 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2030 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2031 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2032 POSTING_READ(IPEIR_I965);
8a905236
JB		 2033 }
2034 if (eir & GM45_ERROR_PAGE_TABLE) {
2035 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2036 pr_err("page table error\n");
2037 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2038 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2039 POSTING_READ(PGTBL_ER);
8a905236
JB		 2040 }
2041 }
2042
a6c45cf0 2043 if (!IS_GEN2(dev)) {
8a905236
JB		 2044 if (eir & I915_ERROR_PAGE_TABLE) {
2045 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2046 pr_err("page table error\n");
2047 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2048 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2049 POSTING_READ(PGTBL_ER);
8a905236
JB		 2050 }
2051 }
2052
2053 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2054 pr_err("memory refresh error:\n");
9db4a9c7 2055 for_each_pipe(pipe)
a70491cc 2056 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2057 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2058 /* pipestat has already been acked */
2059 }
2060 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2061 pr_err("instruction error\n");
2062 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2063 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2064 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2066 u32 ipeir = I915_READ(IPEIR);
2067
a70491cc
JP		 2068 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2069 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2070 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2071 I915_WRITE(IPEIR, ipeir);
3143a2bf 2072 POSTING_READ(IPEIR);
8a905236
JB		 2073 } else {
2074 u32 ipeir = I915_READ(IPEIR_I965);
2075
a70491cc
JP		 2076 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2077 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2078 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2079 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2080 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2081 POSTING_READ(IPEIR_I965);
8a905236
JB		 2082 }
2083 }
2084
2085 I915_WRITE(EIR, eir);
3143a2bf 2086 POSTING_READ(EIR);
8a905236
JB		 2087 eir = I915_READ(EIR);
2088 if (eir) {
2089 /*
2090 * some errors might have become stuck,
2091 * mask them.
2092 */
2093 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2094 I915_WRITE(EMR, I915_READ(EMR) | eir);
2095 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2096 }
35aed2e6
CW		 2097}
2098
2099/**
2100 * i915_handle_error - handle an error interrupt
2101 * @dev: drm device
2102 *
2103 * Do some basic checking of regsiter state at error interrupt time and
2104 * dump it to the syslog. Also call i915_capture_error_state() to make
2105 * sure we get a record and make it available in debugfs. Fire a uevent
2106 * so userspace knows something bad happened (should trigger collection
2107 * of a ring dump etc.).
2108 */
527f9e90 2109void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2110{
2111 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2112 struct intel_ring_buffer *ring;
2113 int i;
35aed2e6
CW		 2114
2115 i915_capture_error_state(dev);
2116 i915_report_and_clear_eir(dev);
8a905236 2117
ba1234d1 2118 if (wedged) {
f69061be
DV		 2119 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2120 &dev_priv->gpu_error.reset_counter);
ba1234d1 2121
11ed50ec 2122 /*
1f83fee0
DV		 2123 * Wakeup waiting processes so that the reset work item
2124 * doesn't deadlock trying to grab various locks.
11ed50ec 2125 */
b4519513
CW		 2126 for_each_ring(ring, dev_priv, i)
2127 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2128 }
2129
99584db3 2130 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2131}
2132
21ad8330 2133static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2134{
2135 drm_i915_private_t *dev_priv = dev->dev_private;
2136 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2138 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2139 struct intel_unpin_work *work;
2140 unsigned long flags;
2141 bool stall_detected;
2142
2143 /* Ignore early vblank irqs */
2144 if (intel_crtc == NULL)
2145 return;
2146
2147 spin_lock_irqsave(&dev->event_lock, flags);
2148 work = intel_crtc->unpin_work;
2149
e7d841ca
CW		 2150 if (work == NULL ||
2151 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2152 !work->enable_stall_check) {
4e5359cd
SF		 2153 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2154 spin_unlock_irqrestore(&dev->event_lock, flags);
2155 return;
2156 }
2157
2158 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2159 obj = work->pending_flip_obj;
a6c45cf0 2160 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2161 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 2162 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2163 obj->gtt_offset;
4e5359cd 2164 } else {
9db4a9c7 2165 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 2166 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 2167 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2168 crtc->x * crtc->fb->bits_per_pixel/8);
2169 }
2170
2171 spin_unlock_irqrestore(&dev->event_lock, flags);
2172
2173 if (stall_detected) {
2174 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2175 intel_prepare_page_flip(dev, intel_crtc->plane);
2176 }
2177}
2178
42f52ef8
KP		 2179/* Called from drm generic code, passed 'crtc' which
2180 * we use as a pipe index
2181 */
f71d4af4 2182static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2183{
2184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2185 unsigned long irqflags;
71e0ffa5 2186
5eddb70b 2187 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2188 return -EINVAL;
0a3e67a4 2189
1ec14ad3 2190 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2191 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2192 i915_enable_pipestat(dev_priv, pipe,
2193 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2194 else
7c463586
KP		 2195 i915_enable_pipestat(dev_priv, pipe,
2196 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2197
2198 /* maintain vblank delivery even in deep C-states */
2199 if (dev_priv->info->gen == 3)
6b26c86d 2200 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2201 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2202
0a3e67a4
JB		 2203 return 0;
2204}
2205
f71d4af4 2206static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2207{
2208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2209 unsigned long irqflags;
2210
2211 if (!i915_pipe_enabled(dev, pipe))
2212 return -EINVAL;
2213
2214 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2215 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2216 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2217 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2218
2219 return 0;
2220}
2221
f71d4af4 2222static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2223{
2224 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2225 unsigned long irqflags;
2226
2227 if (!i915_pipe_enabled(dev, pipe))
2228 return -EINVAL;
2229
2230 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2231 ironlake_enable_display_irq(dev_priv,
2232 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2233 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2234
2235 return 0;
2236}
2237
7e231dbe
JB		 2238static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2239{
2240 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2241 unsigned long irqflags;
31acc7f5 2242 u32 imr;
7e231dbe
JB		 2243
2244 if (!i915_pipe_enabled(dev, pipe))
2245 return -EINVAL;
2246
2247 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2248 imr = I915_READ(VLV_IMR);
31acc7f5 2249 if (pipe == 0)
7e231dbe 2250 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2251 else
7e231dbe 2252 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2253 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2254 i915_enable_pipestat(dev_priv, pipe,
2255 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2256 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2257
2258 return 0;
2259}
2260
42f52ef8
KP		 2261/* Called from drm generic code, passed 'crtc' which
2262 * we use as a pipe index
2263 */
f71d4af4 2264static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2265{
2266 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2267 unsigned long irqflags;
0a3e67a4 2268
1ec14ad3 2269 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2270 if (dev_priv->info->gen == 3)
6b26c86d 2271 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2272
f796cf8f
JB		 2273 i915_disable_pipestat(dev_priv, pipe,
2274 PIPE_VBLANK_INTERRUPT_ENABLE |
2275 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2276 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2277}
2278
f71d4af4 2279static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2280{
2281 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2282 unsigned long irqflags;
2283
2284 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2285 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2286 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2287 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2288}
2289
f71d4af4 2290static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2291{
2292 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2293 unsigned long irqflags;
2294
2295 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2296 ironlake_disable_display_irq(dev_priv,
2297 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2298 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2299}
2300
7e231dbe
JB		 2301static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2302{
2303 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2304 unsigned long irqflags;
31acc7f5 2305 u32 imr;
7e231dbe
JB		 2306
2307 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2308 i915_disable_pipestat(dev_priv, pipe,
2309 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2310 imr = I915_READ(VLV_IMR);
31acc7f5 2311 if (pipe == 0)
7e231dbe 2312 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2313 else
7e231dbe 2314 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2315 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2316 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2317}
2318
893eead0
CW		 2319static u32
2320ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2321{
893eead0
CW		 2322 return list_entry(ring->request_list.prev,
2323 struct drm_i915_gem_request, list)->seqno;
2324}
2325
9107e9d2
CW		 2326static bool
2327ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2328{
2329 return (list_empty(&ring->request_list) ||
2330 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2331}
2332
6274f212
CW		 2333static struct intel_ring_buffer *
2334semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2335{
2336 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2337 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2338
2339 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2340 if ((ipehr & ~(0x3 << 16)) !=
2341 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2342 return NULL;
a24a11e6
CW		 2343
2344 /* ACTHD is likely pointing to the dword after the actual command,
2345 * so scan backwards until we find the MBOX.
2346 */
6274f212 2347 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2348 acthd_min = max((int)acthd - 3 * 4, 0);
2349 do {
2350 cmd = ioread32(ring->virtual_start + acthd);
2351 if (cmd == ipehr)
2352 break;
2353
2354 acthd -= 4;
2355 if (acthd < acthd_min)
6274f212 2356 return NULL;
a24a11e6
CW		 2357 } while (1);
2358
6274f212
CW		 2359 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2360 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2361}
2362
6274f212
CW		 2363static int semaphore_passed(struct intel_ring_buffer *ring)
2364{
2365 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2366 struct intel_ring_buffer *signaller;
2367 u32 seqno, ctl;
2368
2369 ring->hangcheck.deadlock = true;
2370
2371 signaller = semaphore_waits_for(ring, &seqno);
2372 if (signaller == NULL || signaller->hangcheck.deadlock)
2373 return -1;
2374
2375 /* cursory check for an unkickable deadlock */
2376 ctl = I915_READ_CTL(signaller);
2377 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2378 return -1;
2379
2380 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2381}
2382
2383static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2384{
2385 struct intel_ring_buffer *ring;
2386 int i;
2387
2388 for_each_ring(ring, dev_priv, i)
2389 ring->hangcheck.deadlock = false;
2390}
2391
ad8beaea
MK		 2392static enum intel_ring_hangcheck_action
2393ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2394{
2395 struct drm_device *dev = ring->dev;
2396 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2397 u32 tmp;
2398
6274f212
CW		 2399 if (ring->hangcheck.acthd != acthd)
2400 return active;
2401
9107e9d2 2402 if (IS_GEN2(dev))
6274f212 2403 return hung;
9107e9d2
CW		 2404
2405 /* Is the chip hanging on a WAIT_FOR_EVENT?
2406 * If so we can simply poke the RB_WAIT bit
2407 * and break the hang. This should work on
2408 * all but the second generation chipsets.
2409 */
2410 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2411 if (tmp & RING_WAIT) {
2412 DRM_ERROR("Kicking stuck wait on %s\n",
2413 ring->name);
2414 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2415 return kick;
2416 }
2417
2418 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2419 switch (semaphore_passed(ring)) {
2420 default:
2421 return hung;
2422 case 1:
2423 DRM_ERROR("Kicking stuck semaphore on %s\n",
2424 ring->name);
2425 I915_WRITE_CTL(ring, tmp);
2426 return kick;
2427 case 0:
2428 return wait;
2429 }
9107e9d2 2430 }
ed5cbb03 2431
6274f212 2432 return hung;
ed5cbb03
MK		 2433}
2434
f65d9421
BG		 2435/**
2436 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2437 * batchbuffers in a long time. We keep track per ring seqno progress and
2438 * if there are no progress, hangcheck score for that ring is increased.
2439 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2440 * we kick the ring. If we see no progress on three subsequent calls
2441 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2442 */
2443void i915_hangcheck_elapsed(unsigned long data)
2444{
2445 struct drm_device *dev = (struct drm_device *)data;
2446 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2447 struct intel_ring_buffer *ring;
b4519513 2448 int i;
05407ff8 2449 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2450 bool stuck[I915_NUM_RINGS] = { 0 };
2451#define BUSY 1
2452#define KICK 5
2453#define HUNG 20
2454#define FIRE 30
893eead0 2455
3e0dc6b0
BW		 2456 if (!i915_enable_hangcheck)
2457 return;
2458
b4519513 2459 for_each_ring(ring, dev_priv, i) {
05407ff8 2460 u32 seqno, acthd;
9107e9d2 2461 bool busy = true;
05407ff8 2462
6274f212
CW		 2463 semaphore_clear_deadlocks(dev_priv);
2464
05407ff8
MK		 2465 seqno = ring->get_seqno(ring, false);
2466 acthd = intel_ring_get_active_head(ring);
b4519513 2467
9107e9d2
CW		 2468 if (ring->hangcheck.seqno == seqno) {
2469 if (ring_idle(ring, seqno)) {
2470 if (waitqueue_active(&ring->irq_queue)) {
2471 /* Issue a wake-up to catch stuck h/w. */
2472 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2473 ring->name);
2474 wake_up_all(&ring->irq_queue);
2475 ring->hangcheck.score += HUNG;
2476 } else
2477 busy = false;
05407ff8 2478 } else {
9107e9d2
CW		 2479 int score;
2480
6274f212
CW		 2481 /* We always increment the hangcheck score
2482 * if the ring is busy and still processing
2483 * the same request, so that no single request
2484 * can run indefinitely (such as a chain of
2485 * batches). The only time we do not increment
2486 * the hangcheck score on this ring, if this
2487 * ring is in a legitimate wait for another
2488 * ring. In that case the waiting ring is a
2489 * victim and we want to be sure we catch the
2490 * right culprit. Then every time we do kick
2491 * the ring, add a small increment to the
2492 * score so that we can catch a batch that is
2493 * being repeatedly kicked and so responsible
2494 * for stalling the machine.
2495 */
ad8beaea
MK		 2496 ring->hangcheck.action = ring_stuck(ring,
2497 acthd);
2498
2499 switch (ring->hangcheck.action) {
6274f212
CW		 2500 case wait:
2501 score = 0;
2502 break;
2503 case active:
9107e9d2 2504 score = BUSY;
6274f212
CW		 2505 break;
2506 case kick:
2507 score = KICK;
2508 break;
2509 case hung:
2510 score = HUNG;
2511 stuck[i] = true;
2512 break;
2513 }
9107e9d2 2514 ring->hangcheck.score += score;
05407ff8 2515 }
9107e9d2
CW		 2516 } else {
2517 /* Gradually reduce the count so that we catch DoS
2518 * attempts across multiple batches.
2519 */
2520 if (ring->hangcheck.score > 0)
2521 ring->hangcheck.score--;
d1e61e7f
CW		 2522 }
2523
05407ff8
MK		 2524 ring->hangcheck.seqno = seqno;
2525 ring->hangcheck.acthd = acthd;
9107e9d2 2526 busy_count += busy;
893eead0 2527 }
b9201c14 2528
92cab734 2529 for_each_ring(ring, dev_priv, i) {
9107e9d2 2530 if (ring->hangcheck.score > FIRE) {
acd78c11 2531 DRM_ERROR("%s on %s\n",
05407ff8 2532 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2533 ring->name);
2534 rings_hung++;
92cab734
MK		 2535 }
2536 }
2537
05407ff8
MK		 2538 if (rings_hung)
2539 return i915_handle_error(dev, true);
f65d9421 2540
05407ff8
MK		 2541 if (busy_count)
2542 /* Reset timer case chip hangs without another request
2543 * being added */
2544 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2545 round_jiffies_up(jiffies +
2546 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2547}
2548
91738a95
PZ		 2549static void ibx_irq_preinstall(struct drm_device *dev)
2550{
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552
2553 if (HAS_PCH_NOP(dev))
2554 return;
2555
2556 /* south display irq */
2557 I915_WRITE(SDEIMR, 0xffffffff);
2558 /*
2559 * SDEIER is also touched by the interrupt handler to work around missed
2560 * PCH interrupts. Hence we can't update it after the interrupt handler
2561 * is enabled - instead we unconditionally enable all PCH interrupt
2562 * sources here, but then only unmask them as needed with SDEIMR.
2563 */
2564 I915_WRITE(SDEIER, 0xffffffff);
2565 POSTING_READ(SDEIER);
2566}
2567
1da177e4
LT		 2568/* drm_dma.h hooks
2569*/
f71d4af4 2570static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2571{
2572 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2573
4697995b
JB		 2574 atomic_set(&dev_priv->irq_received, 0);
2575
036a4a7d 2576 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2577
036a4a7d
ZW		 2578 /* XXX hotplug from PCH */
2579
2580 I915_WRITE(DEIMR, 0xffffffff);
2581 I915_WRITE(DEIER, 0x0);
3143a2bf 2582 POSTING_READ(DEIER);
036a4a7d
ZW		 2583
2584 /* and GT */
2585 I915_WRITE(GTIMR, 0xffffffff);
2586 I915_WRITE(GTIER, 0x0);
3143a2bf 2587 POSTING_READ(GTIER);
c650156a 2588
91738a95 2589 ibx_irq_preinstall(dev);
7d99163d
BW		 2590}
2591
2592static void ivybridge_irq_preinstall(struct drm_device *dev)
2593{
2594 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2595
2596 atomic_set(&dev_priv->irq_received, 0);
2597
2598 I915_WRITE(HWSTAM, 0xeffe);
2599
2600 /* XXX hotplug from PCH */
2601
2602 I915_WRITE(DEIMR, 0xffffffff);
2603 I915_WRITE(DEIER, 0x0);
2604 POSTING_READ(DEIER);
2605
2606 /* and GT */
2607 I915_WRITE(GTIMR, 0xffffffff);
2608 I915_WRITE(GTIER, 0x0);
2609 POSTING_READ(GTIER);
2610
eda63ffb
BW		 2611 /* Power management */
2612 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2613 I915_WRITE(GEN6_PMIER, 0x0);
2614 POSTING_READ(GEN6_PMIER);
2615
91738a95 2616 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2617}
2618
7e231dbe
JB		 2619static void valleyview_irq_preinstall(struct drm_device *dev)
2620{
2621 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2622 int pipe;
2623
2624 atomic_set(&dev_priv->irq_received, 0);
2625
7e231dbe
JB		 2626 /* VLV magic */
2627 I915_WRITE(VLV_IMR, 0);
2628 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2629 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2630 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2631
7e231dbe
JB		 2632 /* and GT */
2633 I915_WRITE(GTIIR, I915_READ(GTIIR));
2634 I915_WRITE(GTIIR, I915_READ(GTIIR));
2635 I915_WRITE(GTIMR, 0xffffffff);
2636 I915_WRITE(GTIER, 0x0);
2637 POSTING_READ(GTIER);
2638
2639 I915_WRITE(DPINVGTT, 0xff);
2640
2641 I915_WRITE(PORT_HOTPLUG_EN, 0);
2642 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2643 for_each_pipe(pipe)
2644 I915_WRITE(PIPESTAT(pipe), 0xffff);
2645 I915_WRITE(VLV_IIR, 0xffffffff);
2646 I915_WRITE(VLV_IMR, 0xffffffff);
2647 I915_WRITE(VLV_IER, 0x0);
2648 POSTING_READ(VLV_IER);
2649}
2650
82a28bcf 2651static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2652{
2653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2654 struct drm_mode_config *mode_config = &dev->mode_config;
2655 struct intel_encoder *intel_encoder;
2656 u32 mask = ~I915_READ(SDEIMR);
2657 u32 hotplug;
2658
2659 if (HAS_PCH_IBX(dev)) {
995e6b3d 2660 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2661 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2662 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2663 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2664 } else {
995e6b3d 2665 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2666 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2667 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2668 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2669 }
7fe0b973 2670
82a28bcf
DV		 2671 I915_WRITE(SDEIMR, ~mask);
2672
2673 /*
2674 * Enable digital hotplug on the PCH, and configure the DP short pulse
2675 * duration to 2ms (which is the minimum in the Display Port spec)
2676 *
2677 * This register is the same on all known PCH chips.
2678 */
7fe0b973
KP		 2679 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2680 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2681 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2682 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2683 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2684 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2685}
2686
d46da437
PZ		 2687static void ibx_irq_postinstall(struct drm_device *dev)
2688{
2689 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2690 u32 mask;
e5868a31 2691
692a04cf
DV		 2692 if (HAS_PCH_NOP(dev))
2693 return;
2694
8664281b
PZ		 2695 if (HAS_PCH_IBX(dev)) {
2696 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2697 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2698 } else {
2699 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2700
2701 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2702 }
ab5c608b 2703
d46da437
PZ		 2704 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2705 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2706}
2707
f71d4af4 2708static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2709{
4bc9d430
DV		 2710 unsigned long irqflags;
2711
036a4a7d
ZW		 2712 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2713 /* enable kind of interrupts always enabled */
013d5aa2 2714 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2715 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2716 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2717 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2718 u32 gt_irqs;
036a4a7d 2719
1ec14ad3 2720 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2721
2722 /* should always can generate irq */
2723 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2724 I915_WRITE(DEIMR, dev_priv->irq_mask);
6005ce42
DV		 2725 I915_WRITE(DEIER, display_mask |
2726 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
3143a2bf 2727 POSTING_READ(DEIER);
036a4a7d 2728
1ec14ad3 2729 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2730
2731 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2732 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2733
cc609d5d
BW		 2734 gt_irqs = GT_RENDER_USER_INTERRUPT;
2735
1ec14ad3 2736 if (IS_GEN6(dev))
cc609d5d 2737 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2738 else
cc609d5d
BW		 2739 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2740 ILK_BSD_USER_INTERRUPT;
2741
2742 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2743 POSTING_READ(GTIER);
036a4a7d 2744
d46da437 2745 ibx_irq_postinstall(dev);
7fe0b973 2746
f97108d1 2747 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2748 /* Enable PCU event interrupts
2749 *
2750 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2751 * setup is guaranteed to run in single-threaded context. But we
2752 * need it to make the assert_spin_locked happy. */
2753 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2754 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2755 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2756 }
2757
036a4a7d
ZW		 2758 return 0;
2759}
2760
f71d4af4 2761static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2762{
2763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2764 /* enable kind of interrupts always enabled */
b615b57a
CW		 2765 u32 display_mask =
2766 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2767 DE_PLANEC_FLIP_DONE_IVB |
2768 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2769 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2770 DE_AUX_CHANNEL_A_IVB |
2771 DE_ERR_INT_IVB;
12638c57 2772 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2773 u32 gt_irqs;
b1f14ad0 2774
b1f14ad0
JB		 2775 dev_priv->irq_mask = ~display_mask;
2776
2777 /* should always can generate irq */
8664281b 2778 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2779 I915_WRITE(DEIIR, I915_READ(DEIIR));
2780 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2781 I915_WRITE(DEIER,
2782 display_mask |
2783 DE_PIPEC_VBLANK_IVB |
2784 DE_PIPEB_VBLANK_IVB |
2785 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2786 POSTING_READ(DEIER);
2787
cc609d5d 2788 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2789
2790 I915_WRITE(GTIIR, I915_READ(GTIIR));
2791 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2792
cc609d5d
BW		 2793 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2794 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2795 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2796 POSTING_READ(GTIER);
2797
12638c57
BW		 2798 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2799 if (HAS_VEBOX(dev))
2800 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2801 PM_VEBOX_CS_ERROR_INTERRUPT;
2802
2803 /* Our enable/disable rps functions may touch these registers so
2804 * make sure to set a known state for only the non-RPS bits.
2805 * The RMW is extra paranoia since this should be called after being set
2806 * to a known state in preinstall.
2807 * */
2808 I915_WRITE(GEN6_PMIMR,
2809 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2810 I915_WRITE(GEN6_PMIER,
2811 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2812 POSTING_READ(GEN6_PMIER);
eda63ffb 2813
d46da437 2814 ibx_irq_postinstall(dev);
7fe0b973 2815
b1f14ad0
JB		 2816 return 0;
2817}
2818
7e231dbe
JB		 2819static int valleyview_irq_postinstall(struct drm_device *dev)
2820{
2821 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2822 u32 gt_irqs;
7e231dbe 2823 u32 enable_mask;
31acc7f5 2824 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2825 unsigned long irqflags;
7e231dbe
JB		 2826
2827 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2828 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2829 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2830 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2831 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2832
31acc7f5
JB		 2833 /*
2834 *Leave vblank interrupts masked initially. enable/disable will
2835 * toggle them based on usage.
2836 */
2837 dev_priv->irq_mask = (~enable_mask) |
2838 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2839 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2840
20afbda2
DV		 2841 I915_WRITE(PORT_HOTPLUG_EN, 0);
2842 POSTING_READ(PORT_HOTPLUG_EN);
2843
7e231dbe
JB		 2844 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2845 I915_WRITE(VLV_IER, enable_mask);
2846 I915_WRITE(VLV_IIR, 0xffffffff);
2847 I915_WRITE(PIPESTAT(0), 0xffff);
2848 I915_WRITE(PIPESTAT(1), 0xffff);
2849 POSTING_READ(VLV_IER);
2850
b79480ba
DV		 2851 /* Interrupt setup is already guaranteed to be single-threaded, this is
2852 * just to make the assert_spin_locked check happy. */
2853 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2854 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2855 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2856 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2857 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2858
7e231dbe
JB		 2859 I915_WRITE(VLV_IIR, 0xffffffff);
2860 I915_WRITE(VLV_IIR, 0xffffffff);
2861
7e231dbe 2862 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2863 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2864
cc609d5d
BW		 2865 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2866 GT_BLT_USER_INTERRUPT;
2867 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2868 POSTING_READ(GTIER);
2869
2870 /* ack & enable invalid PTE error interrupts */
2871#if 0 /* FIXME: add support to irq handler for checking these bits */
2872 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2873 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2874#endif
2875
2876 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2877
2878 return 0;
2879}
2880
7e231dbe
JB		 2881static void valleyview_irq_uninstall(struct drm_device *dev)
2882{
2883 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2884 int pipe;
2885
2886 if (!dev_priv)
2887 return;
2888
ac4c16c5
EE		 2889 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2890
7e231dbe
JB		 2891 for_each_pipe(pipe)
2892 I915_WRITE(PIPESTAT(pipe), 0xffff);
2893
2894 I915_WRITE(HWSTAM, 0xffffffff);
2895 I915_WRITE(PORT_HOTPLUG_EN, 0);
2896 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2897 for_each_pipe(pipe)
2898 I915_WRITE(PIPESTAT(pipe), 0xffff);
2899 I915_WRITE(VLV_IIR, 0xffffffff);
2900 I915_WRITE(VLV_IMR, 0xffffffff);
2901 I915_WRITE(VLV_IER, 0x0);
2902 POSTING_READ(VLV_IER);
2903}
2904
f71d4af4 2905static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2906{
2907 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2908
2909 if (!dev_priv)
2910 return;
2911
ac4c16c5
EE		 2912 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2913
036a4a7d
ZW		 2914 I915_WRITE(HWSTAM, 0xffffffff);
2915
2916 I915_WRITE(DEIMR, 0xffffffff);
2917 I915_WRITE(DEIER, 0x0);
2918 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2919 if (IS_GEN7(dev))
2920 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2921
2922 I915_WRITE(GTIMR, 0xffffffff);
2923 I915_WRITE(GTIER, 0x0);
2924 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2925
ab5c608b
BW		 2926 if (HAS_PCH_NOP(dev))
2927 return;
2928
192aac1f
KP		 2929 I915_WRITE(SDEIMR, 0xffffffff);
2930 I915_WRITE(SDEIER, 0x0);
2931 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2932 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2933 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2934}
2935
a266c7d5 2936static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2937{
2938 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2939 int pipe;
91e3738e 2940
a266c7d5 2941 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2942
9db4a9c7
JB		 2943 for_each_pipe(pipe)
2944 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2945 I915_WRITE16(IMR, 0xffff);
2946 I915_WRITE16(IER, 0x0);
2947 POSTING_READ16(IER);
c2798b19
CW		 2948}
2949
2950static int i8xx_irq_postinstall(struct drm_device *dev)
2951{
2952 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2953
c2798b19
CW		 2954 I915_WRITE16(EMR,
2955 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2956
2957 /* Unmask the interrupts that we always want on. */
2958 dev_priv->irq_mask =
2959 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2960 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2961 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2962 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2963 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2964 I915_WRITE16(IMR, dev_priv->irq_mask);
2965
2966 I915_WRITE16(IER,
2967 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2968 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2969 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2970 I915_USER_INTERRUPT);
2971 POSTING_READ16(IER);
2972
2973 return 0;
2974}
2975
90a72f87
VS		 2976/*
2977 * Returns true when a page flip has completed.
2978 */
2979static bool i8xx_handle_vblank(struct drm_device *dev,
2980 int pipe, u16 iir)
2981{
2982 drm_i915_private_t *dev_priv = dev->dev_private;
2983 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2984
2985 if (!drm_handle_vblank(dev, pipe))
2986 return false;
2987
2988 if ((iir & flip_pending) == 0)
2989 return false;
2990
2991 intel_prepare_page_flip(dev, pipe);
2992
2993 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2994 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2995 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2996 * the flip is completed (no longer pending). Since this doesn't raise
2997 * an interrupt per se, we watch for the change at vblank.
2998 */
2999 if (I915_READ16(ISR) & flip_pending)
3000 return false;
3001
3002 intel_finish_page_flip(dev, pipe);
3003
3004 return true;
3005}
3006
ff1f525e 3007static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3008{
3009 struct drm_device *dev = (struct drm_device *) arg;
3010 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3011 u16 iir, new_iir;
3012 u32 pipe_stats[2];
3013 unsigned long irqflags;
3014 int irq_received;
3015 int pipe;
3016 u16 flip_mask =
3017 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3018 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3019
3020 atomic_inc(&dev_priv->irq_received);
3021
3022 iir = I915_READ16(IIR);
3023 if (iir == 0)
3024 return IRQ_NONE;
3025
3026 while (iir & ~flip_mask) {
3027 /* Can't rely on pipestat interrupt bit in iir as it might
3028 * have been cleared after the pipestat interrupt was received.
3029 * It doesn't set the bit in iir again, but it still produces
3030 * interrupts (for non-MSI).
3031 */
3032 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3033 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3034 i915_handle_error(dev, false);
3035
3036 for_each_pipe(pipe) {
3037 int reg = PIPESTAT(pipe);
3038 pipe_stats[pipe] = I915_READ(reg);
3039
3040 /*
3041 * Clear the PIPE*STAT regs before the IIR
3042 */
3043 if (pipe_stats[pipe] & 0x8000ffff) {
3044 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3045 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3046 pipe_name(pipe));
3047 I915_WRITE(reg, pipe_stats[pipe]);
3048 irq_received = 1;
3049 }
3050 }
3051 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3052
3053 I915_WRITE16(IIR, iir & ~flip_mask);
3054 new_iir = I915_READ16(IIR); /* Flush posted writes */
3055
d05c617e 3056 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3057
3058 if (iir & I915_USER_INTERRUPT)
3059 notify_ring(dev, &dev_priv->ring[RCS]);
3060
3061 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3062 i8xx_handle_vblank(dev, 0, iir))
3063 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3064
3065 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3066 i8xx_handle_vblank(dev, 1, iir))
3067 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3068
3069 iir = new_iir;
3070 }
3071
3072 return IRQ_HANDLED;
3073}
3074
3075static void i8xx_irq_uninstall(struct drm_device * dev)
3076{
3077 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3078 int pipe;
3079
c2798b19
CW		 3080 for_each_pipe(pipe) {
3081 /* Clear enable bits; then clear status bits */
3082 I915_WRITE(PIPESTAT(pipe), 0);
3083 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3084 }
3085 I915_WRITE16(IMR, 0xffff);
3086 I915_WRITE16(IER, 0x0);
3087 I915_WRITE16(IIR, I915_READ16(IIR));
3088}
3089
a266c7d5
CW		 3090static void i915_irq_preinstall(struct drm_device * dev)
3091{
3092 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3093 int pipe;
3094
3095 atomic_set(&dev_priv->irq_received, 0);
3096
3097 if (I915_HAS_HOTPLUG(dev)) {
3098 I915_WRITE(PORT_HOTPLUG_EN, 0);
3099 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3100 }
3101
00d98ebd 3102 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3103 for_each_pipe(pipe)
3104 I915_WRITE(PIPESTAT(pipe), 0);
3105 I915_WRITE(IMR, 0xffffffff);
3106 I915_WRITE(IER, 0x0);
3107 POSTING_READ(IER);
3108}
3109
3110static int i915_irq_postinstall(struct drm_device *dev)
3111{
3112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3113 u32 enable_mask;
a266c7d5 3114
38bde180
CW		 3115 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3116
3117 /* Unmask the interrupts that we always want on. */
3118 dev_priv->irq_mask =
3119 ~(I915_ASLE_INTERRUPT |
3120 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3121 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3122 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3123 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3124 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3125
3126 enable_mask =
3127 I915_ASLE_INTERRUPT |
3128 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3129 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3130 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3131 I915_USER_INTERRUPT;
3132
a266c7d5 3133 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3134 I915_WRITE(PORT_HOTPLUG_EN, 0);
3135 POSTING_READ(PORT_HOTPLUG_EN);
3136
a266c7d5
CW		 3137 /* Enable in IER... */
3138 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3139 /* and unmask in IMR */
3140 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3141 }
3142
a266c7d5
CW		 3143 I915_WRITE(IMR, dev_priv->irq_mask);
3144 I915_WRITE(IER, enable_mask);
3145 POSTING_READ(IER);
3146
f49e38dd 3147 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3148
3149 return 0;
3150}
3151
90a72f87
VS		 3152/*
3153 * Returns true when a page flip has completed.
3154 */
3155static bool i915_handle_vblank(struct drm_device *dev,
3156 int plane, int pipe, u32 iir)
3157{
3158 drm_i915_private_t *dev_priv = dev->dev_private;
3159 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3160
3161 if (!drm_handle_vblank(dev, pipe))
3162 return false;
3163
3164 if ((iir & flip_pending) == 0)
3165 return false;
3166
3167 intel_prepare_page_flip(dev, plane);
3168
3169 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3170 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3171 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3172 * the flip is completed (no longer pending). Since this doesn't raise
3173 * an interrupt per se, we watch for the change at vblank.
3174 */
3175 if (I915_READ(ISR) & flip_pending)
3176 return false;
3177
3178 intel_finish_page_flip(dev, pipe);
3179
3180 return true;
3181}
3182
ff1f525e 3183static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3184{
3185 struct drm_device *dev = (struct drm_device *) arg;
3186 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3187 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3188 unsigned long irqflags;
38bde180
CW		 3189 u32 flip_mask =
3190 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3191 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3192 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3193
3194 atomic_inc(&dev_priv->irq_received);
3195
3196 iir = I915_READ(IIR);
38bde180
CW		 3197 do {
3198 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3199 bool blc_event = false;
a266c7d5
CW		 3200
3201 /* Can't rely on pipestat interrupt bit in iir as it might
3202 * have been cleared after the pipestat interrupt was received.
3203 * It doesn't set the bit in iir again, but it still produces
3204 * interrupts (for non-MSI).
3205 */
3206 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3207 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3208 i915_handle_error(dev, false);
3209
3210 for_each_pipe(pipe) {
3211 int reg = PIPESTAT(pipe);
3212 pipe_stats[pipe] = I915_READ(reg);
3213
38bde180 3214 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3215 if (pipe_stats[pipe] & 0x8000ffff) {
3216 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3217 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3218 pipe_name(pipe));
3219 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3220 irq_received = true;
a266c7d5
CW		 3221 }
3222 }
3223 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3224
3225 if (!irq_received)
3226 break;
3227
a266c7d5
CW		 3228 /* Consume port. Then clear IIR or we'll miss events */
3229 if ((I915_HAS_HOTPLUG(dev)) &&
3230 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3231 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3232 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3233
3234 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3235 hotplug_status);
91d131d2
DV		 3236
3237 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3238
a266c7d5 3239 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3240 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3241 }
3242
38bde180 3243 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3244 new_iir = I915_READ(IIR); /* Flush posted writes */
3245
a266c7d5
CW		 3246 if (iir & I915_USER_INTERRUPT)
3247 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3248
a266c7d5 3249 for_each_pipe(pipe) {
38bde180
CW		 3250 int plane = pipe;
3251 if (IS_MOBILE(dev))
3252 plane = !plane;
90a72f87 3253
8291ee90 3254 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3255 i915_handle_vblank(dev, plane, pipe, iir))
3256 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3257
3258 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3259 blc_event = true;
3260 }
3261
a266c7d5
CW		 3262 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3263 intel_opregion_asle_intr(dev);
3264
3265 /* With MSI, interrupts are only generated when iir
3266 * transitions from zero to nonzero. If another bit got
3267 * set while we were handling the existing iir bits, then
3268 * we would never get another interrupt.
3269 *
3270 * This is fine on non-MSI as well, as if we hit this path
3271 * we avoid exiting the interrupt handler only to generate
3272 * another one.
3273 *
3274 * Note that for MSI this could cause a stray interrupt report
3275 * if an interrupt landed in the time between writing IIR and
3276 * the posting read. This should be rare enough to never
3277 * trigger the 99% of 100,000 interrupts test for disabling
3278 * stray interrupts.
3279 */
38bde180 3280 ret = IRQ_HANDLED;
a266c7d5 3281 iir = new_iir;
38bde180 3282 } while (iir & ~flip_mask);
a266c7d5 3283
d05c617e 3284 i915_update_dri1_breadcrumb(dev);
8291ee90 3285
a266c7d5
CW		 3286 return ret;
3287}
3288
3289static void i915_irq_uninstall(struct drm_device * dev)
3290{
3291 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3292 int pipe;
3293
ac4c16c5
EE		 3294 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3295
a266c7d5
CW		 3296 if (I915_HAS_HOTPLUG(dev)) {
3297 I915_WRITE(PORT_HOTPLUG_EN, 0);
3298 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3299 }
3300
00d98ebd 3301 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3302 for_each_pipe(pipe) {
3303 /* Clear enable bits; then clear status bits */
a266c7d5 3304 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3305 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3306 }
a266c7d5
CW		 3307 I915_WRITE(IMR, 0xffffffff);
3308 I915_WRITE(IER, 0x0);
3309
a266c7d5
CW		 3310 I915_WRITE(IIR, I915_READ(IIR));
3311}
3312
3313static void i965_irq_preinstall(struct drm_device * dev)
3314{
3315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3316 int pipe;
3317
3318 atomic_set(&dev_priv->irq_received, 0);
3319
adca4730
CW		 3320 I915_WRITE(PORT_HOTPLUG_EN, 0);
3321 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3322
3323 I915_WRITE(HWSTAM, 0xeffe);
3324 for_each_pipe(pipe)
3325 I915_WRITE(PIPESTAT(pipe), 0);
3326 I915_WRITE(IMR, 0xffffffff);
3327 I915_WRITE(IER, 0x0);
3328 POSTING_READ(IER);
3329}
3330
3331static int i965_irq_postinstall(struct drm_device *dev)
3332{
3333 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3334 u32 enable_mask;
a266c7d5 3335 u32 error_mask;
b79480ba 3336 unsigned long irqflags;
a266c7d5 3337
a266c7d5 3338 /* Unmask the interrupts that we always want on. */
bbba0a97 3339 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3340 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3341 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3342 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3343 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3344 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3345 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3346
3347 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3348 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3349 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3350 enable_mask |= I915_USER_INTERRUPT;
3351
3352 if (IS_G4X(dev))
3353 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3354
b79480ba
DV		 3355 /* Interrupt setup is already guaranteed to be single-threaded, this is
3356 * just to make the assert_spin_locked check happy. */
3357 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3358 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3359 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3360
a266c7d5
CW		 3361 /*
3362 * Enable some error detection, note the instruction error mask
3363 * bit is reserved, so we leave it masked.
3364 */
3365 if (IS_G4X(dev)) {
3366 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3367 GM45_ERROR_MEM_PRIV |
3368 GM45_ERROR_CP_PRIV |
3369 I915_ERROR_MEMORY_REFRESH);
3370 } else {
3371 error_mask = ~(I915_ERROR_PAGE_TABLE |
3372 I915_ERROR_MEMORY_REFRESH);
3373 }
3374 I915_WRITE(EMR, error_mask);
3375
3376 I915_WRITE(IMR, dev_priv->irq_mask);
3377 I915_WRITE(IER, enable_mask);
3378 POSTING_READ(IER);
3379
20afbda2
DV		 3380 I915_WRITE(PORT_HOTPLUG_EN, 0);
3381 POSTING_READ(PORT_HOTPLUG_EN);
3382
f49e38dd 3383 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3384
3385 return 0;
3386}
3387
bac56d5b 3388static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3389{
3390 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3391 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3392 struct intel_encoder *intel_encoder;
20afbda2
DV		 3393 u32 hotplug_en;
3394
b5ea2d56
DV		 3395 assert_spin_locked(&dev_priv->irq_lock);
3396
bac56d5b
EE		 3397 if (I915_HAS_HOTPLUG(dev)) {
3398 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3399 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3400 /* Note HDMI and DP share hotplug bits */
e5868a31 3401 /* enable bits are the same for all generations */
cd569aed
EE		 3402 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3403 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3404 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3405 /* Programming the CRT detection parameters tends
3406 to generate a spurious hotplug event about three
3407 seconds later. So just do it once.
3408 */
3409 if (IS_G4X(dev))
3410 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3411 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3412 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3413
bac56d5b
EE		 3414 /* Ignore TV since it's buggy */
3415 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3416 }
a266c7d5
CW		 3417}
3418
ff1f525e 3419static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3420{
3421 struct drm_device *dev = (struct drm_device *) arg;
3422 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3423 u32 iir, new_iir;
3424 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3425 unsigned long irqflags;
3426 int irq_received;
3427 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3428 u32 flip_mask =
3429 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3430 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3431
3432 atomic_inc(&dev_priv->irq_received);
3433
3434 iir = I915_READ(IIR);
3435
a266c7d5 3436 for (;;) {
2c8ba29f
CW		 3437 bool blc_event = false;
3438
21ad8330 3439 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3440
3441 /* Can't rely on pipestat interrupt bit in iir as it might
3442 * have been cleared after the pipestat interrupt was received.
3443 * It doesn't set the bit in iir again, but it still produces
3444 * interrupts (for non-MSI).
3445 */
3446 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3447 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3448 i915_handle_error(dev, false);
3449
3450 for_each_pipe(pipe) {
3451 int reg = PIPESTAT(pipe);
3452 pipe_stats[pipe] = I915_READ(reg);
3453
3454 /*
3455 * Clear the PIPE*STAT regs before the IIR
3456 */
3457 if (pipe_stats[pipe] & 0x8000ffff) {
3458 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3459 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3460 pipe_name(pipe));
3461 I915_WRITE(reg, pipe_stats[pipe]);
3462 irq_received = 1;
3463 }
3464 }
3465 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3466
3467 if (!irq_received)
3468 break;
3469
3470 ret = IRQ_HANDLED;
3471
3472 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3473 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3474 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3475 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3476 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3477 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3478
3479 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3480 hotplug_status);
91d131d2
DV		 3481
3482 intel_hpd_irq_handler(dev, hotplug_trigger,
3483 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3484
a266c7d5
CW		 3485 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3486 I915_READ(PORT_HOTPLUG_STAT);
3487 }
3488
21ad8330 3489 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3490 new_iir = I915_READ(IIR); /* Flush posted writes */
3491
a266c7d5
CW		 3492 if (iir & I915_USER_INTERRUPT)
3493 notify_ring(dev, &dev_priv->ring[RCS]);
3494 if (iir & I915_BSD_USER_INTERRUPT)
3495 notify_ring(dev, &dev_priv->ring[VCS]);
3496
a266c7d5 3497 for_each_pipe(pipe) {
2c8ba29f 3498 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3499 i915_handle_vblank(dev, pipe, pipe, iir))
3500 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3501
3502 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3503 blc_event = true;
3504 }
3505
3506
3507 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3508 intel_opregion_asle_intr(dev);
3509
515ac2bb
DV		 3510 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3511 gmbus_irq_handler(dev);
3512
a266c7d5
CW		 3513 /* With MSI, interrupts are only generated when iir
3514 * transitions from zero to nonzero. If another bit got
3515 * set while we were handling the existing iir bits, then
3516 * we would never get another interrupt.
3517 *
3518 * This is fine on non-MSI as well, as if we hit this path
3519 * we avoid exiting the interrupt handler only to generate
3520 * another one.
3521 *
3522 * Note that for MSI this could cause a stray interrupt report
3523 * if an interrupt landed in the time between writing IIR and
3524 * the posting read. This should be rare enough to never
3525 * trigger the 99% of 100,000 interrupts test for disabling
3526 * stray interrupts.
3527 */
3528 iir = new_iir;
3529 }
3530
d05c617e 3531 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3532
a266c7d5
CW		 3533 return ret;
3534}
3535
3536static void i965_irq_uninstall(struct drm_device * dev)
3537{
3538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3539 int pipe;
3540
3541 if (!dev_priv)
3542 return;
3543
ac4c16c5
EE		 3544 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3545
adca4730
CW		 3546 I915_WRITE(PORT_HOTPLUG_EN, 0);
3547 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3548
3549 I915_WRITE(HWSTAM, 0xffffffff);
3550 for_each_pipe(pipe)
3551 I915_WRITE(PIPESTAT(pipe), 0);
3552 I915_WRITE(IMR, 0xffffffff);
3553 I915_WRITE(IER, 0x0);
3554
3555 for_each_pipe(pipe)
3556 I915_WRITE(PIPESTAT(pipe),
3557 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3558 I915_WRITE(IIR, I915_READ(IIR));
3559}
3560
ac4c16c5
EE		 3561static void i915_reenable_hotplug_timer_func(unsigned long data)
3562{
3563 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3564 struct drm_device *dev = dev_priv->dev;
3565 struct drm_mode_config *mode_config = &dev->mode_config;
3566 unsigned long irqflags;
3567 int i;
3568
3569 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3570 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3571 struct drm_connector *connector;
3572
3573 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3574 continue;
3575
3576 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3577
3578 list_for_each_entry(connector, &mode_config->connector_list, head) {
3579 struct intel_connector *intel_connector = to_intel_connector(connector);
3580
3581 if (intel_connector->encoder->hpd_pin == i) {
3582 if (connector->polled != intel_connector->polled)
3583 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3584 drm_get_connector_name(connector));
3585 connector->polled = intel_connector->polled;
3586 if (!connector->polled)
3587 connector->polled = DRM_CONNECTOR_POLL_HPD;
3588 }
3589 }
3590 }
3591 if (dev_priv->display.hpd_irq_setup)
3592 dev_priv->display.hpd_irq_setup(dev);
3593 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3594}
3595
f71d4af4
JB		 3596void intel_irq_init(struct drm_device *dev)
3597{
8b2e326d
CW		 3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599
3600 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3601 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3602 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3603 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3604
99584db3
DV		 3605 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3606 i915_hangcheck_elapsed,
61bac78e 3607 (unsigned long) dev);
ac4c16c5
EE		 3608 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3609 (unsigned long) dev_priv);
61bac78e 3610
97a19a24 3611 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3612
f71d4af4
JB		 3613 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3614 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3615 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3616 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3617 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3618 }
3619
c3613de9
KP		 3620 if (drm_core_check_feature(dev, DRIVER_MODESET))
3621 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3622 else
3623 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3624 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3625
7e231dbe
JB		 3626 if (IS_VALLEYVIEW(dev)) {
3627 dev->driver->irq_handler = valleyview_irq_handler;
3628 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3629 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3630 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3631 dev->driver->enable_vblank = valleyview_enable_vblank;
3632 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3633 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3634 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3635 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3636 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3637 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3638 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3639 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3640 dev->driver->enable_vblank = ivybridge_enable_vblank;
3641 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3642 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3643 } else if (HAS_PCH_SPLIT(dev)) {
3644 dev->driver->irq_handler = ironlake_irq_handler;
3645 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3646 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3647 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3648 dev->driver->enable_vblank = ironlake_enable_vblank;
3649 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3650 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3651 } else {
c2798b19
CW		 3652 if (INTEL_INFO(dev)->gen == 2) {
3653 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3654 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3655 dev->driver->irq_handler = i8xx_irq_handler;
3656 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3657 } else if (INTEL_INFO(dev)->gen == 3) {
3658 dev->driver->irq_preinstall = i915_irq_preinstall;
3659 dev->driver->irq_postinstall = i915_irq_postinstall;
3660 dev->driver->irq_uninstall = i915_irq_uninstall;
3661 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3662 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3663 } else {
a266c7d5
CW		 3664 dev->driver->irq_preinstall = i965_irq_preinstall;
3665 dev->driver->irq_postinstall = i965_irq_postinstall;
3666 dev->driver->irq_uninstall = i965_irq_uninstall;
3667 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3668 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3669 }
f71d4af4
JB		 3670 dev->driver->enable_vblank = i915_enable_vblank;
3671 dev->driver->disable_vblank = i915_disable_vblank;
3672 }
3673}
20afbda2
DV		 3674
3675void intel_hpd_init(struct drm_device *dev)
3676{
3677 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3678 struct drm_mode_config *mode_config = &dev->mode_config;
3679 struct drm_connector *connector;
b5ea2d56 3680 unsigned long irqflags;
821450c6 3681 int i;
20afbda2 3682
821450c6
EE		 3683 for (i = 1; i < HPD_NUM_PINS; i++) {
3684 dev_priv->hpd_stats[i].hpd_cnt = 0;
3685 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3686 }
3687 list_for_each_entry(connector, &mode_config->connector_list, head) {
3688 struct intel_connector *intel_connector = to_intel_connector(connector);
3689 connector->polled = intel_connector->polled;
3690 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3691 connector->polled = DRM_CONNECTOR_POLL_HPD;
3692 }
b5ea2d56
DV		 3693
3694 /* Interrupt setup is already guaranteed to be single-threaded, this is
3695 * just to make the assert_spin_locked checks happy. */
3696 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3697 if (dev_priv->display.hpd_irq_setup)
3698 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3699 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3700}
Linux kernel - Deliverables
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