Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3143a2bf | 73 | POSTING_READ(GTIMR); |
036a4a7d ZW |
74 | } |
75 | } | |
76 | ||
62fdfeaf | 77 | void |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3143a2bf | 83 | POSTING_READ(GTIMR); |
036a4a7d ZW |
84 | } |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
995b6762 | 88 | static void |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
3143a2bf | 94 | POSTING_READ(DEIMR); |
036a4a7d ZW |
95 | } |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
3143a2bf | 104 | POSTING_READ(DEIMR); |
036a4a7d ZW |
105 | } |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
3143a2bf | 114 | POSTING_READ(IMR); |
ed4cb414 EA |
115 | } |
116 | } | |
117 | ||
62fdfeaf | 118 | void |
ed4cb414 EA |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
3143a2bf | 124 | POSTING_READ(IMR); |
ed4cb414 EA |
125 | } |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 147 | POSTING_READ(reg); |
7c463586 KP |
148 | } |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 159 | POSTING_READ(reg); |
7c463586 KP |
160 | } |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 | 173 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 175 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 176 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 178 | } |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 194 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
195 | } |
196 | ||
42f52ef8 KP |
197 | /* Called from drm generic code, passed a 'crtc', which |
198 | * we use as a pipe index | |
199 | */ | |
200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
201 | { |
202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
203 | unsigned long high_frame; | |
204 | unsigned long low_frame; | |
5eddb70b | 205 | u32 high1, high2, low; |
0a3e67a4 JB |
206 | |
207 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
209 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
210 | return 0; |
211 | } | |
212 | ||
5eddb70b CW |
213 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
214 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
215 | ||
0a3e67a4 JB |
216 | /* |
217 | * High & low register fields aren't synchronized, so make sure | |
218 | * we get a low value that's stable across two reads of the high | |
219 | * register. | |
220 | */ | |
221 | do { | |
5eddb70b CW |
222 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
223 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
224 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
225 | } while (high1 != high2); |
226 | ||
5eddb70b CW |
227 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
228 | low >>= PIPE_FRAME_LOW_SHIFT; | |
229 | return (high1 << 8) | low; | |
0a3e67a4 JB |
230 | } |
231 | ||
9880b7a5 JB |
232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
233 | { | |
234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
236 | ||
237 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
239 | "pipe %d\n", pipe); | |
9880b7a5 JB |
240 | return 0; |
241 | } | |
242 | ||
243 | return I915_READ(reg); | |
244 | } | |
245 | ||
5ca58282 JB |
246 | /* |
247 | * Handle hotplug events outside the interrupt handler proper. | |
248 | */ | |
249 | static void i915_hotplug_work_func(struct work_struct *work) | |
250 | { | |
251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
252 | hotplug_work); | |
253 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 254 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
255 | struct intel_encoder *encoder; |
256 | ||
257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
258 | if (encoder->hot_plug) | |
259 | encoder->hot_plug(encoder); | |
260 | ||
5ca58282 | 261 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 262 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
263 | } |
264 | ||
f97108d1 JB |
265 | static void i915_handle_rps_change(struct drm_device *dev) |
266 | { | |
267 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 268 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
269 | u8 new_delay = dev_priv->cur_delay; |
270 | ||
7648fa99 | 271 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
272 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
273 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
274 | max_avg = I915_READ(RCBMAXAVG); |
275 | min_avg = I915_READ(RCBMINAVG); | |
276 | ||
277 | /* Handle RCS change request from hw */ | |
b5b72e89 | 278 | if (busy_up > max_avg) { |
f97108d1 JB |
279 | if (dev_priv->cur_delay != dev_priv->max_delay) |
280 | new_delay = dev_priv->cur_delay - 1; | |
281 | if (new_delay < dev_priv->max_delay) | |
282 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 283 | } else if (busy_down < min_avg) { |
f97108d1 JB |
284 | if (dev_priv->cur_delay != dev_priv->min_delay) |
285 | new_delay = dev_priv->cur_delay + 1; | |
286 | if (new_delay > dev_priv->min_delay) | |
287 | new_delay = dev_priv->min_delay; | |
288 | } | |
289 | ||
7648fa99 JB |
290 | if (ironlake_set_drps(dev, new_delay)) |
291 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
292 | |
293 | return; | |
294 | } | |
295 | ||
549f7365 CW |
296 | static void notify_ring(struct drm_device *dev, |
297 | struct intel_ring_buffer *ring) | |
298 | { | |
299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
78501eac | 300 | u32 seqno = ring->get_seqno(ring); |
b2223497 | 301 | ring->irq_seqno = seqno; |
549f7365 CW |
302 | trace_i915_gem_request_complete(dev, seqno); |
303 | wake_up_all(&ring->irq_queue); | |
304 | dev_priv->hangcheck_count = 0; | |
305 | mod_timer(&dev_priv->hangcheck_timer, | |
306 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
307 | } | |
308 | ||
995b6762 | 309 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
310 | { |
311 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
312 | int ret = IRQ_NONE; | |
3ff99164 | 313 | u32 de_iir, gt_iir, de_ier, pch_iir; |
2d7b8366 | 314 | u32 hotplug_mask; |
036a4a7d | 315 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
316 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
317 | ||
318 | if (IS_GEN6(dev)) | |
319 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 320 | |
2d109a84 ZN |
321 | /* disable master interrupt before clearing iir */ |
322 | de_ier = I915_READ(DEIER); | |
323 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 324 | POSTING_READ(DEIER); |
2d109a84 | 325 | |
036a4a7d ZW |
326 | de_iir = I915_READ(DEIIR); |
327 | gt_iir = I915_READ(GTIIR); | |
c650156a | 328 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 329 | |
c7c85101 ZN |
330 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
331 | goto done; | |
036a4a7d | 332 | |
2d7b8366 YL |
333 | if (HAS_PCH_CPT(dev)) |
334 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
335 | else | |
336 | hotplug_mask = SDE_HOTPLUG_MASK; | |
337 | ||
c7c85101 | 338 | ret = IRQ_HANDLED; |
036a4a7d | 339 | |
c7c85101 ZN |
340 | if (dev->primary->master) { |
341 | master_priv = dev->primary->master->driver_priv; | |
342 | if (master_priv->sarea_priv) | |
343 | master_priv->sarea_priv->last_dispatch = | |
344 | READ_BREADCRUMB(dev_priv); | |
345 | } | |
036a4a7d | 346 | |
549f7365 CW |
347 | if (gt_iir & GT_PIPE_NOTIFY) |
348 | notify_ring(dev, &dev_priv->render_ring); | |
881f47b6 | 349 | if (gt_iir & bsd_usr_interrupt) |
549f7365 CW |
350 | notify_ring(dev, &dev_priv->bsd_ring); |
351 | if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT) | |
352 | notify_ring(dev, &dev_priv->blt_ring); | |
01c66889 | 353 | |
c7c85101 | 354 | if (de_iir & DE_GSE) |
3b617967 | 355 | intel_opregion_gse_intr(dev); |
c650156a | 356 | |
f072d2e7 | 357 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 358 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 359 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 360 | } |
013d5aa2 | 361 | |
f072d2e7 | 362 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 363 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 364 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 365 | } |
013d5aa2 | 366 | |
f072d2e7 | 367 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
368 | drm_handle_vblank(dev, 0); |
369 | ||
f072d2e7 | 370 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
371 | drm_handle_vblank(dev, 1); |
372 | ||
c7c85101 | 373 | /* check event from PCH */ |
2d7b8366 | 374 | if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask)) |
c7c85101 | 375 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
036a4a7d | 376 | |
f97108d1 | 377 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 378 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
379 | i915_handle_rps_change(dev); |
380 | } | |
381 | ||
c7c85101 ZN |
382 | /* should clear PCH hotplug event before clear CPU irq */ |
383 | I915_WRITE(SDEIIR, pch_iir); | |
384 | I915_WRITE(GTIIR, gt_iir); | |
385 | I915_WRITE(DEIIR, de_iir); | |
386 | ||
387 | done: | |
2d109a84 | 388 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 389 | POSTING_READ(DEIER); |
2d109a84 | 390 | |
036a4a7d ZW |
391 | return ret; |
392 | } | |
393 | ||
8a905236 JB |
394 | /** |
395 | * i915_error_work_func - do process context error handling work | |
396 | * @work: work struct | |
397 | * | |
398 | * Fire an error uevent so userspace can see that a hang or error | |
399 | * was detected. | |
400 | */ | |
401 | static void i915_error_work_func(struct work_struct *work) | |
402 | { | |
403 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
404 | error_work); | |
405 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
406 | char *error_event[] = { "ERROR=1", NULL }; |
407 | char *reset_event[] = { "RESET=1", NULL }; | |
408 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 409 | |
f316a42c BG |
410 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
411 | ||
ba1234d1 | 412 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
413 | DRM_DEBUG_DRIVER("resetting chip\n"); |
414 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
415 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
416 | atomic_set(&dev_priv->mm.wedged, 0); | |
417 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 418 | } |
30dbf0c0 | 419 | complete_all(&dev_priv->error_completion); |
f316a42c | 420 | } |
8a905236 JB |
421 | } |
422 | ||
3bd3c932 | 423 | #ifdef CONFIG_DEBUG_FS |
9df30794 CW |
424 | static struct drm_i915_error_object * |
425 | i915_error_object_create(struct drm_device *dev, | |
05394f39 | 426 | struct drm_i915_gem_object *src) |
9df30794 | 427 | { |
e56660dd | 428 | drm_i915_private_t *dev_priv = dev->dev_private; |
9df30794 | 429 | struct drm_i915_error_object *dst; |
9df30794 | 430 | int page, page_count; |
e56660dd | 431 | u32 reloc_offset; |
9df30794 | 432 | |
05394f39 | 433 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
434 | return NULL; |
435 | ||
05394f39 | 436 | page_count = src->base.size / PAGE_SIZE; |
9df30794 CW |
437 | |
438 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
439 | if (dst == NULL) | |
440 | return NULL; | |
441 | ||
05394f39 | 442 | reloc_offset = src->gtt_offset; |
9df30794 | 443 | for (page = 0; page < page_count; page++) { |
788885ae | 444 | unsigned long flags; |
e56660dd CW |
445 | void __iomem *s; |
446 | void *d; | |
788885ae | 447 | |
e56660dd | 448 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
449 | if (d == NULL) |
450 | goto unwind; | |
e56660dd | 451 | |
788885ae | 452 | local_irq_save(flags); |
e56660dd | 453 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3e4d3af5 | 454 | reloc_offset); |
e56660dd | 455 | memcpy_fromio(d, s, PAGE_SIZE); |
3e4d3af5 | 456 | io_mapping_unmap_atomic(s); |
788885ae | 457 | local_irq_restore(flags); |
e56660dd | 458 | |
9df30794 | 459 | dst->pages[page] = d; |
e56660dd CW |
460 | |
461 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
462 | } |
463 | dst->page_count = page_count; | |
05394f39 | 464 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
465 | |
466 | return dst; | |
467 | ||
468 | unwind: | |
469 | while (page--) | |
470 | kfree(dst->pages[page]); | |
471 | kfree(dst); | |
472 | return NULL; | |
473 | } | |
474 | ||
475 | static void | |
476 | i915_error_object_free(struct drm_i915_error_object *obj) | |
477 | { | |
478 | int page; | |
479 | ||
480 | if (obj == NULL) | |
481 | return; | |
482 | ||
483 | for (page = 0; page < obj->page_count; page++) | |
484 | kfree(obj->pages[page]); | |
485 | ||
486 | kfree(obj); | |
487 | } | |
488 | ||
489 | static void | |
490 | i915_error_state_free(struct drm_device *dev, | |
491 | struct drm_i915_error_state *error) | |
492 | { | |
493 | i915_error_object_free(error->batchbuffer[0]); | |
494 | i915_error_object_free(error->batchbuffer[1]); | |
495 | i915_error_object_free(error->ringbuffer); | |
496 | kfree(error->active_bo); | |
6ef3d427 | 497 | kfree(error->overlay); |
9df30794 CW |
498 | kfree(error); |
499 | } | |
500 | ||
501 | static u32 | |
502 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
503 | { | |
504 | u32 cmd; | |
505 | ||
506 | if (IS_I830(dev) || IS_845G(dev)) | |
507 | cmd = MI_BATCH_BUFFER; | |
a6c45cf0 | 508 | else if (INTEL_INFO(dev)->gen >= 4) |
9df30794 CW |
509 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
510 | MI_BATCH_NON_SECURE_I965); | |
511 | else | |
512 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
513 | ||
514 | return ring[0] == cmd ? ring[1] : 0; | |
515 | } | |
516 | ||
517 | static u32 | |
8168bd48 CW |
518 | i915_ringbuffer_last_batch(struct drm_device *dev, |
519 | struct intel_ring_buffer *ring) | |
9df30794 CW |
520 | { |
521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
522 | u32 head, bbaddr; | |
8168bd48 | 523 | u32 *val; |
9df30794 CW |
524 | |
525 | /* Locate the current position in the ringbuffer and walk back | |
526 | * to find the most recently dispatched batch buffer. | |
527 | */ | |
8168bd48 | 528 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
9df30794 | 529 | |
ab5793ad | 530 | val = (u32 *)(ring->virtual_start + head); |
8168bd48 CW |
531 | while (--val >= (u32 *)ring->virtual_start) { |
532 | bbaddr = i915_get_bbaddr(dev, val); | |
9df30794 | 533 | if (bbaddr) |
ab5793ad | 534 | return bbaddr; |
9df30794 CW |
535 | } |
536 | ||
ab5793ad CW |
537 | val = (u32 *)(ring->virtual_start + ring->size); |
538 | while (--val >= (u32 *)ring->virtual_start) { | |
539 | bbaddr = i915_get_bbaddr(dev, val); | |
540 | if (bbaddr) | |
541 | return bbaddr; | |
9df30794 CW |
542 | } |
543 | ||
ab5793ad | 544 | return 0; |
9df30794 CW |
545 | } |
546 | ||
c724e8a9 CW |
547 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
548 | int count, | |
549 | struct list_head *head) | |
550 | { | |
551 | struct drm_i915_gem_object *obj; | |
552 | int i = 0; | |
553 | ||
554 | list_for_each_entry(obj, head, mm_list) { | |
555 | err->size = obj->base.size; | |
556 | err->name = obj->base.name; | |
557 | err->seqno = obj->last_rendering_seqno; | |
558 | err->gtt_offset = obj->gtt_offset; | |
559 | err->read_domains = obj->base.read_domains; | |
560 | err->write_domain = obj->base.write_domain; | |
561 | err->fence_reg = obj->fence_reg; | |
562 | err->pinned = 0; | |
563 | if (obj->pin_count > 0) | |
564 | err->pinned = 1; | |
565 | if (obj->user_pin_count > 0) | |
566 | err->pinned = -1; | |
567 | err->tiling = obj->tiling_mode; | |
568 | err->dirty = obj->dirty; | |
569 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
3685092b | 570 | err->ring = obj->ring ? obj->ring->id : 0; |
c724e8a9 CW |
571 | |
572 | if (++i == count) | |
573 | break; | |
574 | ||
575 | err++; | |
576 | } | |
577 | ||
578 | return i; | |
579 | } | |
580 | ||
748ebc60 CW |
581 | static void i915_gem_record_fences(struct drm_device *dev, |
582 | struct drm_i915_error_state *error) | |
583 | { | |
584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
585 | int i; | |
586 | ||
587 | /* Fences */ | |
588 | switch (INTEL_INFO(dev)->gen) { | |
589 | case 6: | |
590 | for (i = 0; i < 16; i++) | |
591 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
592 | break; | |
593 | case 5: | |
594 | case 4: | |
595 | for (i = 0; i < 16; i++) | |
596 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
597 | break; | |
598 | case 3: | |
599 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
600 | for (i = 0; i < 8; i++) | |
601 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
602 | case 2: | |
603 | for (i = 0; i < 8; i++) | |
604 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
605 | break; | |
606 | ||
607 | } | |
608 | } | |
609 | ||
8a905236 JB |
610 | /** |
611 | * i915_capture_error_state - capture an error record for later analysis | |
612 | * @dev: drm device | |
613 | * | |
614 | * Should be called when an error is detected (either a hang or an error | |
615 | * interrupt) to capture error state from the time of the error. Fills | |
616 | * out a structure which becomes available in debugfs for user level tools | |
617 | * to pick up. | |
618 | */ | |
63eeaf38 JB |
619 | static void i915_capture_error_state(struct drm_device *dev) |
620 | { | |
621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 622 | struct drm_i915_gem_object *obj; |
63eeaf38 | 623 | struct drm_i915_error_state *error; |
05394f39 | 624 | struct drm_i915_gem_object *batchbuffer[2]; |
63eeaf38 | 625 | unsigned long flags; |
9df30794 CW |
626 | u32 bbaddr; |
627 | int count; | |
63eeaf38 JB |
628 | |
629 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
630 | error = dev_priv->first_error; |
631 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
632 | if (error) | |
633 | return; | |
63eeaf38 JB |
634 | |
635 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
636 | if (!error) { | |
9df30794 CW |
637 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
638 | return; | |
63eeaf38 JB |
639 | } |
640 | ||
2fa772f3 CW |
641 | DRM_DEBUG_DRIVER("generating error event\n"); |
642 | ||
f787a5f5 | 643 | error->seqno = |
78501eac | 644 | dev_priv->render_ring.get_seqno(&dev_priv->render_ring); |
63eeaf38 JB |
645 | error->eir = I915_READ(EIR); |
646 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
647 | error->pipeastat = I915_READ(PIPEASTAT); | |
648 | error->pipebstat = I915_READ(PIPEBSTAT); | |
649 | error->instpm = I915_READ(INSTPM); | |
f406839f CW |
650 | error->error = 0; |
651 | if (INTEL_INFO(dev)->gen >= 6) { | |
652 | error->error = I915_READ(ERROR_GEN6); | |
add354dd | 653 | |
1d8f38f4 CW |
654 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
655 | error->bcs_ipehr = I915_READ(BCS_IPEHR); | |
656 | error->bcs_ipeir = I915_READ(BCS_IPEIR); | |
657 | error->bcs_instdone = I915_READ(BCS_INSTDONE); | |
658 | error->bcs_seqno = 0; | |
659 | if (dev_priv->blt_ring.get_seqno) | |
660 | error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring); | |
add354dd CW |
661 | |
662 | error->vcs_acthd = I915_READ(VCS_ACTHD); | |
663 | error->vcs_ipehr = I915_READ(VCS_IPEHR); | |
664 | error->vcs_ipeir = I915_READ(VCS_IPEIR); | |
665 | error->vcs_instdone = I915_READ(VCS_INSTDONE); | |
666 | error->vcs_seqno = 0; | |
667 | if (dev_priv->bsd_ring.get_seqno) | |
668 | error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring); | |
f406839f CW |
669 | } |
670 | if (INTEL_INFO(dev)->gen >= 4) { | |
63eeaf38 JB |
671 | error->ipeir = I915_READ(IPEIR_I965); |
672 | error->ipehr = I915_READ(IPEHR_I965); | |
673 | error->instdone = I915_READ(INSTDONE_I965); | |
674 | error->instps = I915_READ(INSTPS); | |
675 | error->instdone1 = I915_READ(INSTDONE1); | |
676 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 677 | error->bbaddr = I915_READ64(BB_ADDR); |
f406839f CW |
678 | } else { |
679 | error->ipeir = I915_READ(IPEIR); | |
680 | error->ipehr = I915_READ(IPEHR); | |
681 | error->instdone = I915_READ(INSTDONE); | |
682 | error->acthd = I915_READ(ACTHD); | |
683 | error->bbaddr = 0; | |
63eeaf38 | 684 | } |
748ebc60 | 685 | i915_gem_record_fences(dev, error); |
63eeaf38 | 686 | |
8168bd48 | 687 | bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring); |
8a905236 | 688 | |
9df30794 CW |
689 | /* Grab the current batchbuffer, most likely to have crashed. */ |
690 | batchbuffer[0] = NULL; | |
691 | batchbuffer[1] = NULL; | |
692 | count = 0; | |
05394f39 | 693 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { |
9df30794 | 694 | if (batchbuffer[0] == NULL && |
05394f39 CW |
695 | bbaddr >= obj->gtt_offset && |
696 | bbaddr < obj->gtt_offset + obj->base.size) | |
9df30794 CW |
697 | batchbuffer[0] = obj; |
698 | ||
699 | if (batchbuffer[1] == NULL && | |
05394f39 CW |
700 | error->acthd >= obj->gtt_offset && |
701 | error->acthd < obj->gtt_offset + obj->base.size) | |
9df30794 CW |
702 | batchbuffer[1] = obj; |
703 | ||
704 | count++; | |
705 | } | |
e56660dd CW |
706 | /* Scan the other lists for completeness for those bizarre errors. */ |
707 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
05394f39 | 708 | list_for_each_entry(obj, &dev_priv->mm.flushing_list, mm_list) { |
e56660dd | 709 | if (batchbuffer[0] == NULL && |
05394f39 CW |
710 | bbaddr >= obj->gtt_offset && |
711 | bbaddr < obj->gtt_offset + obj->base.size) | |
e56660dd CW |
712 | batchbuffer[0] = obj; |
713 | ||
714 | if (batchbuffer[1] == NULL && | |
05394f39 CW |
715 | error->acthd >= obj->gtt_offset && |
716 | error->acthd < obj->gtt_offset + obj->base.size) | |
e56660dd CW |
717 | batchbuffer[1] = obj; |
718 | ||
719 | if (batchbuffer[0] && batchbuffer[1]) | |
720 | break; | |
721 | } | |
722 | } | |
723 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
05394f39 | 724 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) { |
e56660dd | 725 | if (batchbuffer[0] == NULL && |
05394f39 CW |
726 | bbaddr >= obj->gtt_offset && |
727 | bbaddr < obj->gtt_offset + obj->base.size) | |
e56660dd CW |
728 | batchbuffer[0] = obj; |
729 | ||
730 | if (batchbuffer[1] == NULL && | |
05394f39 CW |
731 | error->acthd >= obj->gtt_offset && |
732 | error->acthd < obj->gtt_offset + obj->base.size) | |
e56660dd CW |
733 | batchbuffer[1] = obj; |
734 | ||
735 | if (batchbuffer[0] && batchbuffer[1]) | |
736 | break; | |
737 | } | |
738 | } | |
9df30794 CW |
739 | |
740 | /* We need to copy these to an anonymous buffer as the simplest | |
139d363b | 741 | * method to avoid being overwritten by userspace. |
9df30794 CW |
742 | */ |
743 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
e56660dd CW |
744 | if (batchbuffer[1] != batchbuffer[0]) |
745 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
746 | else | |
747 | error->batchbuffer[1] = NULL; | |
9df30794 CW |
748 | |
749 | /* Record the ringbuffer */ | |
8187a2b7 | 750 | error->ringbuffer = i915_error_object_create(dev, |
05394f39 | 751 | dev_priv->render_ring.obj); |
9df30794 | 752 | |
c724e8a9 | 753 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 754 | error->active_bo = NULL; |
c724e8a9 | 755 | error->pinned_bo = NULL; |
9df30794 | 756 | |
c724e8a9 | 757 | error->active_bo_count = count; |
05394f39 | 758 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
c724e8a9 CW |
759 | count++; |
760 | error->pinned_bo_count = count - error->active_bo_count; | |
761 | ||
762 | if (count) { | |
9df30794 CW |
763 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, |
764 | GFP_ATOMIC); | |
c724e8a9 CW |
765 | if (error->active_bo) |
766 | error->pinned_bo = | |
767 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
768 | } |
769 | ||
c724e8a9 CW |
770 | if (error->active_bo) |
771 | error->active_bo_count = | |
772 | capture_bo_list(error->active_bo, | |
773 | error->active_bo_count, | |
774 | &dev_priv->mm.active_list); | |
775 | ||
776 | if (error->pinned_bo) | |
777 | error->pinned_bo_count = | |
778 | capture_bo_list(error->pinned_bo, | |
779 | error->pinned_bo_count, | |
780 | &dev_priv->mm.pinned_list); | |
781 | ||
9df30794 CW |
782 | do_gettimeofday(&error->time); |
783 | ||
6ef3d427 | 784 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 785 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 786 | |
9df30794 CW |
787 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
788 | if (dev_priv->first_error == NULL) { | |
789 | dev_priv->first_error = error; | |
790 | error = NULL; | |
791 | } | |
63eeaf38 | 792 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
793 | |
794 | if (error) | |
795 | i915_error_state_free(dev, error); | |
796 | } | |
797 | ||
798 | void i915_destroy_error_state(struct drm_device *dev) | |
799 | { | |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | struct drm_i915_error_state *error; | |
802 | ||
803 | spin_lock(&dev_priv->error_lock); | |
804 | error = dev_priv->first_error; | |
805 | dev_priv->first_error = NULL; | |
806 | spin_unlock(&dev_priv->error_lock); | |
807 | ||
808 | if (error) | |
809 | i915_error_state_free(dev, error); | |
63eeaf38 | 810 | } |
3bd3c932 CW |
811 | #else |
812 | #define i915_capture_error_state(x) | |
813 | #endif | |
63eeaf38 | 814 | |
35aed2e6 | 815 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
816 | { |
817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
818 | u32 eir = I915_READ(EIR); | |
8a905236 | 819 | |
35aed2e6 CW |
820 | if (!eir) |
821 | return; | |
8a905236 JB |
822 | |
823 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
824 | eir); | |
825 | ||
826 | if (IS_G4X(dev)) { | |
827 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
828 | u32 ipeir = I915_READ(IPEIR_I965); | |
829 | ||
830 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
831 | I915_READ(IPEIR_I965)); | |
832 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
833 | I915_READ(IPEHR_I965)); | |
834 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
835 | I915_READ(INSTDONE_I965)); | |
836 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
837 | I915_READ(INSTPS)); | |
838 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
839 | I915_READ(INSTDONE1)); | |
840 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
841 | I915_READ(ACTHD_I965)); | |
842 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 843 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
844 | } |
845 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
846 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
847 | printk(KERN_ERR "page table error\n"); | |
848 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
849 | pgtbl_err); | |
850 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 851 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
852 | } |
853 | } | |
854 | ||
a6c45cf0 | 855 | if (!IS_GEN2(dev)) { |
8a905236 JB |
856 | if (eir & I915_ERROR_PAGE_TABLE) { |
857 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
858 | printk(KERN_ERR "page table error\n"); | |
859 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
860 | pgtbl_err); | |
861 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 862 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
863 | } |
864 | } | |
865 | ||
866 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
867 | u32 pipea_stats = I915_READ(PIPEASTAT); |
868 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
869 | ||
8a905236 JB |
870 | printk(KERN_ERR "memory refresh error\n"); |
871 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
872 | pipea_stats); | |
873 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
874 | pipeb_stats); | |
875 | /* pipestat has already been acked */ | |
876 | } | |
877 | if (eir & I915_ERROR_INSTRUCTION) { | |
878 | printk(KERN_ERR "instruction error\n"); | |
879 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
880 | I915_READ(INSTPM)); | |
a6c45cf0 | 881 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
882 | u32 ipeir = I915_READ(IPEIR); |
883 | ||
884 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
885 | I915_READ(IPEIR)); | |
886 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
887 | I915_READ(IPEHR)); | |
888 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
889 | I915_READ(INSTDONE)); | |
890 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
891 | I915_READ(ACTHD)); | |
892 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 893 | POSTING_READ(IPEIR); |
8a905236 JB |
894 | } else { |
895 | u32 ipeir = I915_READ(IPEIR_I965); | |
896 | ||
897 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
898 | I915_READ(IPEIR_I965)); | |
899 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
900 | I915_READ(IPEHR_I965)); | |
901 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
902 | I915_READ(INSTDONE_I965)); | |
903 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
904 | I915_READ(INSTPS)); | |
905 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
906 | I915_READ(INSTDONE1)); | |
907 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
908 | I915_READ(ACTHD_I965)); | |
909 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 910 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
911 | } |
912 | } | |
913 | ||
914 | I915_WRITE(EIR, eir); | |
3143a2bf | 915 | POSTING_READ(EIR); |
8a905236 JB |
916 | eir = I915_READ(EIR); |
917 | if (eir) { | |
918 | /* | |
919 | * some errors might have become stuck, | |
920 | * mask them. | |
921 | */ | |
922 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
923 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
924 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
925 | } | |
35aed2e6 CW |
926 | } |
927 | ||
928 | /** | |
929 | * i915_handle_error - handle an error interrupt | |
930 | * @dev: drm device | |
931 | * | |
932 | * Do some basic checking of regsiter state at error interrupt time and | |
933 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
934 | * sure we get a record and make it available in debugfs. Fire a uevent | |
935 | * so userspace knows something bad happened (should trigger collection | |
936 | * of a ring dump etc.). | |
937 | */ | |
527f9e90 | 938 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
939 | { |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
941 | ||
942 | i915_capture_error_state(dev); | |
943 | i915_report_and_clear_eir(dev); | |
8a905236 | 944 | |
ba1234d1 | 945 | if (wedged) { |
30dbf0c0 | 946 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
947 | atomic_set(&dev_priv->mm.wedged, 1); |
948 | ||
11ed50ec BG |
949 | /* |
950 | * Wakeup waiting processes so they don't hang | |
951 | */ | |
f787a5f5 CW |
952 | wake_up_all(&dev_priv->render_ring.irq_queue); |
953 | if (HAS_BSD(dev)) | |
954 | wake_up_all(&dev_priv->bsd_ring.irq_queue); | |
549f7365 CW |
955 | if (HAS_BLT(dev)) |
956 | wake_up_all(&dev_priv->blt_ring.irq_queue); | |
11ed50ec BG |
957 | } |
958 | ||
9c9fe1f8 | 959 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
960 | } |
961 | ||
4e5359cd SF |
962 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
963 | { | |
964 | drm_i915_private_t *dev_priv = dev->dev_private; | |
965 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 967 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
968 | struct intel_unpin_work *work; |
969 | unsigned long flags; | |
970 | bool stall_detected; | |
971 | ||
972 | /* Ignore early vblank irqs */ | |
973 | if (intel_crtc == NULL) | |
974 | return; | |
975 | ||
976 | spin_lock_irqsave(&dev->event_lock, flags); | |
977 | work = intel_crtc->unpin_work; | |
978 | ||
979 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
980 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
981 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
982 | return; | |
983 | } | |
984 | ||
985 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 986 | obj = work->pending_flip_obj; |
a6c45cf0 | 987 | if (INTEL_INFO(dev)->gen >= 4) { |
4e5359cd | 988 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
05394f39 | 989 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd SF |
990 | } else { |
991 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
05394f39 | 992 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
4e5359cd SF |
993 | crtc->y * crtc->fb->pitch + |
994 | crtc->x * crtc->fb->bits_per_pixel/8); | |
995 | } | |
996 | ||
997 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
998 | ||
999 | if (stall_detected) { | |
1000 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1001 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1002 | } | |
1003 | } | |
1004 | ||
1da177e4 LT |
1005 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1006 | { | |
84b1fd10 | 1007 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1008 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1009 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
1010 | u32 iir, new_iir; |
1011 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 1012 | u32 vblank_status; |
0a3e67a4 | 1013 | int vblank = 0; |
7c463586 | 1014 | unsigned long irqflags; |
05eff845 KP |
1015 | int irq_received; |
1016 | int ret = IRQ_NONE; | |
6e5fca53 | 1017 | |
630681d9 EA |
1018 | atomic_inc(&dev_priv->irq_received); |
1019 | ||
bad720ff | 1020 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1021 | return ironlake_irq_handler(dev); |
036a4a7d | 1022 | |
ed4cb414 | 1023 | iir = I915_READ(IIR); |
a6b54f3f | 1024 | |
a6c45cf0 | 1025 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1026 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1027 | else |
d874bcff | 1028 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1029 | |
05eff845 KP |
1030 | for (;;) { |
1031 | irq_received = iir != 0; | |
1032 | ||
1033 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1034 | * have been cleared after the pipestat interrupt was received. | |
1035 | * It doesn't set the bit in iir again, but it still produces | |
1036 | * interrupts (for non-MSI). | |
1037 | */ | |
1038 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
1039 | pipea_stats = I915_READ(PIPEASTAT); | |
1040 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 1041 | |
8a905236 | 1042 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1043 | i915_handle_error(dev, false); |
8a905236 | 1044 | |
cdfbc41f EA |
1045 | /* |
1046 | * Clear the PIPE(A|B)STAT regs before the IIR | |
1047 | */ | |
05eff845 | 1048 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 1049 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1050 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 1051 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 1052 | irq_received = 1; |
cdfbc41f | 1053 | } |
1da177e4 | 1054 | |
05eff845 | 1055 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 1056 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1057 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 1058 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 1059 | irq_received = 1; |
cdfbc41f | 1060 | } |
05eff845 KP |
1061 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
1062 | ||
1063 | if (!irq_received) | |
1064 | break; | |
1065 | ||
1066 | ret = IRQ_HANDLED; | |
8ee1c3db | 1067 | |
5ca58282 JB |
1068 | /* Consume port. Then clear IIR or we'll miss events */ |
1069 | if ((I915_HAS_HOTPLUG(dev)) && | |
1070 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1071 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1072 | ||
44d98a61 | 1073 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1074 | hotplug_status); |
1075 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1076 | queue_work(dev_priv->wq, |
1077 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1078 | |
1079 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1080 | I915_READ(PORT_HOTPLUG_STAT); | |
1081 | } | |
1082 | ||
cdfbc41f EA |
1083 | I915_WRITE(IIR, iir); |
1084 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1085 | |
7c1c2871 DA |
1086 | if (dev->primary->master) { |
1087 | master_priv = dev->primary->master->driver_priv; | |
1088 | if (master_priv->sarea_priv) | |
1089 | master_priv->sarea_priv->last_dispatch = | |
1090 | READ_BREADCRUMB(dev_priv); | |
1091 | } | |
0a3e67a4 | 1092 | |
549f7365 CW |
1093 | if (iir & I915_USER_INTERRUPT) |
1094 | notify_ring(dev, &dev_priv->render_ring); | |
d1b851fc | 1095 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
549f7365 | 1096 | notify_ring(dev, &dev_priv->bsd_ring); |
d1b851fc | 1097 | |
1afe3e9d | 1098 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1099 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1100 | if (dev_priv->flip_pending_is_done) |
1101 | intel_finish_page_flip_plane(dev, 0); | |
1102 | } | |
6b95a207 | 1103 | |
1afe3e9d | 1104 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1105 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1106 | if (dev_priv->flip_pending_is_done) |
1107 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1108 | } |
6b95a207 | 1109 | |
05eff845 | 1110 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
1111 | vblank++; |
1112 | drm_handle_vblank(dev, 0); | |
4e5359cd SF |
1113 | if (!dev_priv->flip_pending_is_done) { |
1114 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1115 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1116 | } |
cdfbc41f | 1117 | } |
7c463586 | 1118 | |
05eff845 | 1119 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
1120 | vblank++; |
1121 | drm_handle_vblank(dev, 1); | |
4e5359cd SF |
1122 | if (!dev_priv->flip_pending_is_done) { |
1123 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1124 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1125 | } |
cdfbc41f | 1126 | } |
7c463586 | 1127 | |
d874bcff JB |
1128 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1129 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1130 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1131 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1132 | |
1133 | /* With MSI, interrupts are only generated when iir | |
1134 | * transitions from zero to nonzero. If another bit got | |
1135 | * set while we were handling the existing iir bits, then | |
1136 | * we would never get another interrupt. | |
1137 | * | |
1138 | * This is fine on non-MSI as well, as if we hit this path | |
1139 | * we avoid exiting the interrupt handler only to generate | |
1140 | * another one. | |
1141 | * | |
1142 | * Note that for MSI this could cause a stray interrupt report | |
1143 | * if an interrupt landed in the time between writing IIR and | |
1144 | * the posting read. This should be rare enough to never | |
1145 | * trigger the 99% of 100,000 interrupts test for disabling | |
1146 | * stray interrupts. | |
1147 | */ | |
1148 | iir = new_iir; | |
05eff845 | 1149 | } |
0a3e67a4 | 1150 | |
05eff845 | 1151 | return ret; |
1da177e4 LT |
1152 | } |
1153 | ||
af6061af | 1154 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1155 | { |
1156 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1157 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1158 | |
1159 | i915_kernel_lost_context(dev); | |
1160 | ||
44d98a61 | 1161 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1162 | |
c99b058f | 1163 | dev_priv->counter++; |
c29b669c | 1164 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1165 | dev_priv->counter = 1; |
7c1c2871 DA |
1166 | if (master_priv->sarea_priv) |
1167 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1168 | |
e1f99ce6 CW |
1169 | if (BEGIN_LP_RING(4) == 0) { |
1170 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1171 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1172 | OUT_RING(dev_priv->counter); | |
1173 | OUT_RING(MI_USER_INTERRUPT); | |
1174 | ADVANCE_LP_RING(); | |
1175 | } | |
bc5f4523 | 1176 | |
c29b669c | 1177 | return dev_priv->counter; |
1da177e4 LT |
1178 | } |
1179 | ||
9d34e5db CW |
1180 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1181 | { | |
1182 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8187a2b7 | 1183 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
9d34e5db CW |
1184 | |
1185 | if (dev_priv->trace_irq_seqno == 0) | |
78501eac | 1186 | render_ring->user_irq_get(render_ring); |
9d34e5db CW |
1187 | |
1188 | dev_priv->trace_irq_seqno = seqno; | |
1189 | } | |
1190 | ||
84b1fd10 | 1191 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1192 | { |
1193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1194 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1195 | int ret = 0; |
8187a2b7 | 1196 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
1da177e4 | 1197 | |
44d98a61 | 1198 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1199 | READ_BREADCRUMB(dev_priv)); |
1200 | ||
ed4cb414 | 1201 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1202 | if (master_priv->sarea_priv) |
1203 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1204 | return 0; |
ed4cb414 | 1205 | } |
1da177e4 | 1206 | |
7c1c2871 DA |
1207 | if (master_priv->sarea_priv) |
1208 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1209 | |
78501eac | 1210 | render_ring->user_irq_get(render_ring); |
852835f3 | 1211 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
1da177e4 | 1212 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
78501eac | 1213 | render_ring->user_irq_put(render_ring); |
1da177e4 | 1214 | |
20caafa6 | 1215 | if (ret == -EBUSY) { |
3e684eae | 1216 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1217 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1218 | } | |
1219 | ||
af6061af DA |
1220 | return ret; |
1221 | } | |
1222 | ||
1da177e4 LT |
1223 | /* Needs the lock as it touches the ring. |
1224 | */ | |
c153f45f EA |
1225 | int i915_irq_emit(struct drm_device *dev, void *data, |
1226 | struct drm_file *file_priv) | |
1da177e4 | 1227 | { |
1da177e4 | 1228 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1229 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1230 | int result; |
1231 | ||
d3301d86 | 1232 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
3e684eae | 1233 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1234 | return -EINVAL; |
1da177e4 | 1235 | } |
299eb93c EA |
1236 | |
1237 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1238 | ||
546b0974 | 1239 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1240 | result = i915_emit_irq(dev); |
546b0974 | 1241 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1242 | |
c153f45f | 1243 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1244 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1245 | return -EFAULT; |
1da177e4 LT |
1246 | } |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | /* Doesn't need the hardware lock. | |
1252 | */ | |
c153f45f EA |
1253 | int i915_irq_wait(struct drm_device *dev, void *data, |
1254 | struct drm_file *file_priv) | |
1da177e4 | 1255 | { |
1da177e4 | 1256 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1257 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1258 | |
1259 | if (!dev_priv) { | |
3e684eae | 1260 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1261 | return -EINVAL; |
1da177e4 LT |
1262 | } |
1263 | ||
c153f45f | 1264 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1265 | } |
1266 | ||
42f52ef8 KP |
1267 | /* Called from drm generic code, passed 'crtc' which |
1268 | * we use as a pipe index | |
1269 | */ | |
1270 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1271 | { |
1272 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1273 | unsigned long irqflags; |
71e0ffa5 | 1274 | |
5eddb70b | 1275 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1276 | return -EINVAL; |
0a3e67a4 | 1277 | |
e9d21d7f | 1278 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1279 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1280 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1281 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
a6c45cf0 | 1282 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1283 | i915_enable_pipestat(dev_priv, pipe, |
1284 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1285 | else |
7c463586 KP |
1286 | i915_enable_pipestat(dev_priv, pipe, |
1287 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1288 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1289 | return 0; |
1290 | } | |
1291 | ||
42f52ef8 KP |
1292 | /* Called from drm generic code, passed 'crtc' which |
1293 | * we use as a pipe index | |
1294 | */ | |
1295 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1296 | { |
1297 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1298 | unsigned long irqflags; |
0a3e67a4 | 1299 | |
e9d21d7f | 1300 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1301 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1302 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1303 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1304 | else | |
1305 | i915_disable_pipestat(dev_priv, pipe, | |
1306 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1307 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1308 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1309 | } |
1310 | ||
79e53945 JB |
1311 | void i915_enable_interrupt (struct drm_device *dev) |
1312 | { | |
1313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1314 | |
bad720ff | 1315 | if (!HAS_PCH_SPLIT(dev)) |
3b617967 | 1316 | intel_opregion_enable_asle(dev); |
79e53945 JB |
1317 | dev_priv->irq_enabled = 1; |
1318 | } | |
1319 | ||
1320 | ||
702880f2 DA |
1321 | /* Set the vblank monitor pipe |
1322 | */ | |
c153f45f EA |
1323 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1324 | struct drm_file *file_priv) | |
702880f2 | 1325 | { |
702880f2 | 1326 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1327 | |
1328 | if (!dev_priv) { | |
3e684eae | 1329 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1330 | return -EINVAL; |
702880f2 DA |
1331 | } |
1332 | ||
5b51694a | 1333 | return 0; |
702880f2 DA |
1334 | } |
1335 | ||
c153f45f EA |
1336 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1337 | struct drm_file *file_priv) | |
702880f2 | 1338 | { |
702880f2 | 1339 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1340 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1341 | |
1342 | if (!dev_priv) { | |
3e684eae | 1343 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1344 | return -EINVAL; |
702880f2 DA |
1345 | } |
1346 | ||
0a3e67a4 | 1347 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1348 | |
702880f2 DA |
1349 | return 0; |
1350 | } | |
1351 | ||
a6b54f3f MCA |
1352 | /** |
1353 | * Schedule buffer swap at given vertical blank. | |
1354 | */ | |
c153f45f EA |
1355 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1356 | struct drm_file *file_priv) | |
a6b54f3f | 1357 | { |
bd95e0a4 EA |
1358 | /* The delayed swap mechanism was fundamentally racy, and has been |
1359 | * removed. The model was that the client requested a delayed flip/swap | |
1360 | * from the kernel, then waited for vblank before continuing to perform | |
1361 | * rendering. The problem was that the kernel might wake the client | |
1362 | * up before it dispatched the vblank swap (since the lock has to be | |
1363 | * held while touching the ringbuffer), in which case the client would | |
1364 | * clear and start the next frame before the swap occurred, and | |
1365 | * flicker would occur in addition to likely missing the vblank. | |
1366 | * | |
1367 | * In the absence of this ioctl, userland falls back to a correct path | |
1368 | * of waiting for a vblank, then dispatching the swap on its own. | |
1369 | * Context switching to userland and back is plenty fast enough for | |
1370 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1371 | */ |
bd95e0a4 | 1372 | return -EINVAL; |
a6b54f3f MCA |
1373 | } |
1374 | ||
893eead0 CW |
1375 | static u32 |
1376 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1377 | { |
893eead0 CW |
1378 | return list_entry(ring->request_list.prev, |
1379 | struct drm_i915_gem_request, list)->seqno; | |
1380 | } | |
1381 | ||
1382 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1383 | { | |
1384 | if (list_empty(&ring->request_list) || | |
1385 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1386 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1387 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1388 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1389 | ring->name, | |
b2223497 | 1390 | ring->waiting_seqno, |
893eead0 CW |
1391 | ring->get_seqno(ring)); |
1392 | wake_up_all(&ring->irq_queue); | |
1393 | *err = true; | |
1394 | } | |
1395 | return true; | |
1396 | } | |
1397 | return false; | |
f65d9421 BG |
1398 | } |
1399 | ||
1400 | /** | |
1401 | * This is called when the chip hasn't reported back with completed | |
1402 | * batchbuffers in a long time. The first time this is called we simply record | |
1403 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1404 | * again, we assume the chip is wedged and try to fix it. | |
1405 | */ | |
1406 | void i915_hangcheck_elapsed(unsigned long data) | |
1407 | { | |
1408 | struct drm_device *dev = (struct drm_device *)data; | |
1409 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1410 | uint32_t acthd, instdone, instdone1; |
893eead0 CW |
1411 | bool err = false; |
1412 | ||
1413 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
1414 | if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) && | |
1415 | i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) && | |
1416 | i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) { | |
1417 | dev_priv->hangcheck_count = 0; | |
1418 | if (err) | |
1419 | goto repeat; | |
1420 | return; | |
1421 | } | |
b9201c14 | 1422 | |
a6c45cf0 | 1423 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1424 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1425 | instdone = I915_READ(INSTDONE); |
1426 | instdone1 = 0; | |
1427 | } else { | |
f65d9421 | 1428 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1429 | instdone = I915_READ(INSTDONE_I965); |
1430 | instdone1 = I915_READ(INSTDONE1); | |
1431 | } | |
f65d9421 | 1432 | |
cbb465e7 CW |
1433 | if (dev_priv->last_acthd == acthd && |
1434 | dev_priv->last_instdone == instdone && | |
1435 | dev_priv->last_instdone1 == instdone1) { | |
1436 | if (dev_priv->hangcheck_count++ > 1) { | |
1437 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1438 | |
1439 | if (!IS_GEN2(dev)) { | |
1440 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1441 | * If so we can simply poke the RB_WAIT bit | |
1442 | * and break the hang. This should work on | |
1443 | * all but the second generation chipsets. | |
1444 | */ | |
8168bd48 CW |
1445 | struct intel_ring_buffer *ring = &dev_priv->render_ring; |
1446 | u32 tmp = I915_READ_CTL(ring); | |
8c80b59b | 1447 | if (tmp & RING_WAIT) { |
8168bd48 | 1448 | I915_WRITE_CTL(ring, tmp); |
893eead0 | 1449 | goto repeat; |
8c80b59b CW |
1450 | } |
1451 | } | |
1452 | ||
cbb465e7 CW |
1453 | i915_handle_error(dev, true); |
1454 | return; | |
1455 | } | |
1456 | } else { | |
1457 | dev_priv->hangcheck_count = 0; | |
1458 | ||
1459 | dev_priv->last_acthd = acthd; | |
1460 | dev_priv->last_instdone = instdone; | |
1461 | dev_priv->last_instdone1 = instdone1; | |
1462 | } | |
f65d9421 | 1463 | |
893eead0 | 1464 | repeat: |
f65d9421 | 1465 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1466 | mod_timer(&dev_priv->hangcheck_timer, |
1467 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1468 | } |
1469 | ||
1da177e4 LT |
1470 | /* drm_dma.h hooks |
1471 | */ | |
f2b115e6 | 1472 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1473 | { |
1474 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1475 | ||
1476 | I915_WRITE(HWSTAM, 0xeffe); | |
1477 | ||
1478 | /* XXX hotplug from PCH */ | |
1479 | ||
1480 | I915_WRITE(DEIMR, 0xffffffff); | |
1481 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1482 | POSTING_READ(DEIER); |
036a4a7d ZW |
1483 | |
1484 | /* and GT */ | |
1485 | I915_WRITE(GTIMR, 0xffffffff); | |
1486 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1487 | POSTING_READ(GTIER); |
c650156a ZW |
1488 | |
1489 | /* south display irq */ | |
1490 | I915_WRITE(SDEIMR, 0xffffffff); | |
1491 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1492 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1493 | } |
1494 | ||
f2b115e6 | 1495 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1496 | { |
1497 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1498 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1499 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1500 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
d1b851fc | 1501 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
2d7b8366 | 1502 | u32 hotplug_mask; |
036a4a7d ZW |
1503 | |
1504 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1505 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1506 | |
1507 | /* should always can generate irq */ | |
1508 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1509 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1510 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
3143a2bf | 1511 | POSTING_READ(DEIER); |
036a4a7d | 1512 | |
549f7365 CW |
1513 | if (IS_GEN6(dev)) { |
1514 | render_mask = | |
1515 | GT_PIPE_NOTIFY | | |
1516 | GT_GEN6_BSD_USER_INTERRUPT | | |
1517 | GT_BLT_USER_INTERRUPT; | |
1518 | } | |
3fdef020 | 1519 | |
852835f3 | 1520 | dev_priv->gt_irq_mask_reg = ~render_mask; |
036a4a7d ZW |
1521 | dev_priv->gt_irq_enable_reg = render_mask; |
1522 | ||
1523 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1524 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
881f47b6 | 1525 | if (IS_GEN6(dev)) { |
3fdef020 | 1526 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); |
881f47b6 | 1527 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT); |
549f7365 | 1528 | I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT); |
881f47b6 XH |
1529 | } |
1530 | ||
036a4a7d | 1531 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
3143a2bf | 1532 | POSTING_READ(GTIER); |
036a4a7d | 1533 | |
2d7b8366 YL |
1534 | if (HAS_PCH_CPT(dev)) { |
1535 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | | |
1536 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; | |
1537 | } else { | |
1538 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | |
1539 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
1540 | } | |
1541 | ||
c650156a ZW |
1542 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1543 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1544 | ||
1545 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1546 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1547 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
3143a2bf | 1548 | POSTING_READ(SDEIER); |
c650156a | 1549 | |
f97108d1 JB |
1550 | if (IS_IRONLAKE_M(dev)) { |
1551 | /* Clear & enable PCU event interrupts */ | |
1552 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1553 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1554 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1555 | } | |
1556 | ||
036a4a7d ZW |
1557 | return 0; |
1558 | } | |
1559 | ||
84b1fd10 | 1560 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1561 | { |
1562 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1563 | ||
79e53945 JB |
1564 | atomic_set(&dev_priv->irq_received, 0); |
1565 | ||
036a4a7d | 1566 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1567 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1568 | |
bad720ff | 1569 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1570 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1571 | return; |
1572 | } | |
1573 | ||
5ca58282 JB |
1574 | if (I915_HAS_HOTPLUG(dev)) { |
1575 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1576 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1577 | } | |
1578 | ||
0a3e67a4 | 1579 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1580 | I915_WRITE(PIPEASTAT, 0); |
1581 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1582 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1583 | I915_WRITE(IER, 0x0); |
3143a2bf | 1584 | POSTING_READ(IER); |
1da177e4 LT |
1585 | } |
1586 | ||
b01f2c3a JB |
1587 | /* |
1588 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1589 | * enabled correctly. | |
1590 | */ | |
0a3e67a4 | 1591 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1592 | { |
1593 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1594 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1595 | u32 error_mask; |
0a3e67a4 | 1596 | |
852835f3 | 1597 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
d1b851fc ZN |
1598 | if (HAS_BSD(dev)) |
1599 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); | |
549f7365 CW |
1600 | if (HAS_BLT(dev)) |
1601 | DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue); | |
d1b851fc | 1602 | |
0a3e67a4 | 1603 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1604 | |
bad720ff | 1605 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1606 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1607 | |
7c463586 KP |
1608 | /* Unmask the interrupts that we always want on. */ |
1609 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1610 | ||
1611 | dev_priv->pipestat[0] = 0; | |
1612 | dev_priv->pipestat[1] = 0; | |
1613 | ||
5ca58282 | 1614 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1615 | /* Enable in IER... */ |
1616 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1617 | /* and unmask in IMR */ | |
c496fa1f | 1618 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1619 | } |
1620 | ||
63eeaf38 JB |
1621 | /* |
1622 | * Enable some error detection, note the instruction error mask | |
1623 | * bit is reserved, so we leave it masked. | |
1624 | */ | |
1625 | if (IS_G4X(dev)) { | |
1626 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1627 | GM45_ERROR_MEM_PRIV | | |
1628 | GM45_ERROR_CP_PRIV | | |
1629 | I915_ERROR_MEMORY_REFRESH); | |
1630 | } else { | |
1631 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1632 | I915_ERROR_MEMORY_REFRESH); | |
1633 | } | |
1634 | I915_WRITE(EMR, error_mask); | |
1635 | ||
7c463586 | 1636 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
c496fa1f | 1637 | I915_WRITE(IER, enable_mask); |
3143a2bf | 1638 | POSTING_READ(IER); |
ed4cb414 | 1639 | |
c496fa1f AJ |
1640 | if (I915_HAS_HOTPLUG(dev)) { |
1641 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1642 | ||
1643 | /* Note HDMI and DP share bits */ | |
1644 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1645 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1646 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1647 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1648 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1649 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1650 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1651 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1652 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1653 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1654 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1655 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1656 | |
1657 | /* Programming the CRT detection parameters tends | |
1658 | to generate a spurious hotplug event about three | |
1659 | seconds later. So just do it once. | |
1660 | */ | |
1661 | if (IS_G4X(dev)) | |
1662 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1663 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1664 | } | |
1665 | ||
c496fa1f AJ |
1666 | /* Ignore TV since it's buggy */ |
1667 | ||
1668 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1669 | } | |
1670 | ||
3b617967 | 1671 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1672 | |
1673 | return 0; | |
1da177e4 LT |
1674 | } |
1675 | ||
f2b115e6 | 1676 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1677 | { |
1678 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1679 | I915_WRITE(HWSTAM, 0xffffffff); | |
1680 | ||
1681 | I915_WRITE(DEIMR, 0xffffffff); | |
1682 | I915_WRITE(DEIER, 0x0); | |
1683 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1684 | ||
1685 | I915_WRITE(GTIMR, 0xffffffff); | |
1686 | I915_WRITE(GTIER, 0x0); | |
1687 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1688 | } | |
1689 | ||
84b1fd10 | 1690 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1691 | { |
1692 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1693 | |
1da177e4 LT |
1694 | if (!dev_priv) |
1695 | return; | |
1696 | ||
0a3e67a4 JB |
1697 | dev_priv->vblank_pipe = 0; |
1698 | ||
bad720ff | 1699 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1700 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1701 | return; |
1702 | } | |
1703 | ||
5ca58282 JB |
1704 | if (I915_HAS_HOTPLUG(dev)) { |
1705 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1706 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1707 | } | |
1708 | ||
0a3e67a4 | 1709 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1710 | I915_WRITE(PIPEASTAT, 0); |
1711 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1712 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1713 | I915_WRITE(IER, 0x0); |
af6061af | 1714 | |
7c463586 KP |
1715 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1716 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1717 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1718 | } |