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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/i915_drm.h> | |
1da177e4 | 35 | #include "i915_drv.h" |
1c5d22f7 | 36 | #include "i915_trace.h" |
79e53945 | 37 | #include "intel_drv.h" |
1da177e4 | 38 | |
e5868a31 EE |
39 | static const u32 hpd_ibx[] = { |
40 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
41 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
42 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
43 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
44 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
45 | }; | |
46 | ||
47 | static const u32 hpd_cpt[] = { | |
48 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 49 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
50 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
51 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
52 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
53 | }; | |
54 | ||
55 | static const u32 hpd_mask_i915[] = { | |
56 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
57 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
59 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
62 | }; | |
63 | ||
64 | static const u32 hpd_status_gen4[] = { | |
65 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
66 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
67 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
69 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
71 | }; | |
72 | ||
e5868a31 EE |
73 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
74 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
75 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
76 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
78 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
80 | }; | |
81 | ||
036a4a7d | 82 | /* For display hotplug interrupt */ |
995b6762 | 83 | static void |
f2b115e6 | 84 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 85 | { |
4bc9d430 DV |
86 | assert_spin_locked(&dev_priv->irq_lock); |
87 | ||
c67a470b PZ |
88 | if (dev_priv->pc8.irqs_disabled) { |
89 | WARN(1, "IRQs disabled\n"); | |
90 | dev_priv->pc8.regsave.deimr &= ~mask; | |
91 | return; | |
92 | } | |
93 | ||
1ec14ad3 CW |
94 | if ((dev_priv->irq_mask & mask) != 0) { |
95 | dev_priv->irq_mask &= ~mask; | |
96 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 97 | POSTING_READ(DEIMR); |
036a4a7d ZW |
98 | } |
99 | } | |
100 | ||
0ff9800a | 101 | static void |
f2b115e6 | 102 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 103 | { |
4bc9d430 DV |
104 | assert_spin_locked(&dev_priv->irq_lock); |
105 | ||
c67a470b PZ |
106 | if (dev_priv->pc8.irqs_disabled) { |
107 | WARN(1, "IRQs disabled\n"); | |
108 | dev_priv->pc8.regsave.deimr |= mask; | |
109 | return; | |
110 | } | |
111 | ||
1ec14ad3 CW |
112 | if ((dev_priv->irq_mask & mask) != mask) { |
113 | dev_priv->irq_mask |= mask; | |
114 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 115 | POSTING_READ(DEIMR); |
036a4a7d ZW |
116 | } |
117 | } | |
118 | ||
43eaea13 PZ |
119 | /** |
120 | * ilk_update_gt_irq - update GTIMR | |
121 | * @dev_priv: driver private | |
122 | * @interrupt_mask: mask of interrupt bits to update | |
123 | * @enabled_irq_mask: mask of interrupt bits to enable | |
124 | */ | |
125 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
126 | uint32_t interrupt_mask, | |
127 | uint32_t enabled_irq_mask) | |
128 | { | |
129 | assert_spin_locked(&dev_priv->irq_lock); | |
130 | ||
c67a470b PZ |
131 | if (dev_priv->pc8.irqs_disabled) { |
132 | WARN(1, "IRQs disabled\n"); | |
133 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; | |
134 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & | |
135 | interrupt_mask); | |
136 | return; | |
137 | } | |
138 | ||
43eaea13 PZ |
139 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
140 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
141 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
142 | POSTING_READ(GTIMR); | |
143 | } | |
144 | ||
145 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
146 | { | |
147 | ilk_update_gt_irq(dev_priv, mask, mask); | |
148 | } | |
149 | ||
150 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
151 | { | |
152 | ilk_update_gt_irq(dev_priv, mask, 0); | |
153 | } | |
154 | ||
edbfdb45 PZ |
155 | /** |
156 | * snb_update_pm_irq - update GEN6_PMIMR | |
157 | * @dev_priv: driver private | |
158 | * @interrupt_mask: mask of interrupt bits to update | |
159 | * @enabled_irq_mask: mask of interrupt bits to enable | |
160 | */ | |
161 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
162 | uint32_t interrupt_mask, | |
163 | uint32_t enabled_irq_mask) | |
164 | { | |
605cd25b | 165 | uint32_t new_val; |
edbfdb45 PZ |
166 | |
167 | assert_spin_locked(&dev_priv->irq_lock); | |
168 | ||
c67a470b PZ |
169 | if (dev_priv->pc8.irqs_disabled) { |
170 | WARN(1, "IRQs disabled\n"); | |
171 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; | |
172 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
173 | interrupt_mask); | |
174 | return; | |
175 | } | |
176 | ||
605cd25b | 177 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
178 | new_val &= ~interrupt_mask; |
179 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
180 | ||
605cd25b PZ |
181 | if (new_val != dev_priv->pm_irq_mask) { |
182 | dev_priv->pm_irq_mask = new_val; | |
183 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
184 | POSTING_READ(GEN6_PMIMR); |
185 | } | |
edbfdb45 PZ |
186 | } |
187 | ||
188 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
189 | { | |
190 | snb_update_pm_irq(dev_priv, mask, mask); | |
191 | } | |
192 | ||
193 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
194 | { | |
195 | snb_update_pm_irq(dev_priv, mask, 0); | |
196 | } | |
197 | ||
8664281b PZ |
198 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
199 | { | |
200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
201 | struct intel_crtc *crtc; | |
202 | enum pipe pipe; | |
203 | ||
4bc9d430 DV |
204 | assert_spin_locked(&dev_priv->irq_lock); |
205 | ||
8664281b PZ |
206 | for_each_pipe(pipe) { |
207 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
208 | ||
209 | if (crtc->cpu_fifo_underrun_disabled) | |
210 | return false; | |
211 | } | |
212 | ||
213 | return true; | |
214 | } | |
215 | ||
216 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
217 | { | |
218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
219 | enum pipe pipe; | |
220 | struct intel_crtc *crtc; | |
221 | ||
fee884ed DV |
222 | assert_spin_locked(&dev_priv->irq_lock); |
223 | ||
8664281b PZ |
224 | for_each_pipe(pipe) { |
225 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
226 | ||
227 | if (crtc->pch_fifo_underrun_disabled) | |
228 | return false; | |
229 | } | |
230 | ||
231 | return true; | |
232 | } | |
233 | ||
234 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
235 | enum pipe pipe, bool enable) | |
236 | { | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
239 | DE_PIPEB_FIFO_UNDERRUN; | |
240 | ||
241 | if (enable) | |
242 | ironlake_enable_display_irq(dev_priv, bit); | |
243 | else | |
244 | ironlake_disable_display_irq(dev_priv, bit); | |
245 | } | |
246 | ||
247 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 248 | enum pipe pipe, bool enable) |
8664281b PZ |
249 | { |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 251 | if (enable) { |
7336df65 DV |
252 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
253 | ||
8664281b PZ |
254 | if (!ivb_can_enable_err_int(dev)) |
255 | return; | |
256 | ||
8664281b PZ |
257 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
258 | } else { | |
7336df65 DV |
259 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
260 | ||
261 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 262 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
263 | |
264 | if (!was_enabled && | |
265 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
266 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
267 | pipe_name(pipe)); | |
268 | } | |
8664281b PZ |
269 | } |
270 | } | |
271 | ||
fee884ed DV |
272 | /** |
273 | * ibx_display_interrupt_update - update SDEIMR | |
274 | * @dev_priv: driver private | |
275 | * @interrupt_mask: mask of interrupt bits to update | |
276 | * @enabled_irq_mask: mask of interrupt bits to enable | |
277 | */ | |
278 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
279 | uint32_t interrupt_mask, | |
280 | uint32_t enabled_irq_mask) | |
281 | { | |
282 | uint32_t sdeimr = I915_READ(SDEIMR); | |
283 | sdeimr &= ~interrupt_mask; | |
284 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
285 | ||
286 | assert_spin_locked(&dev_priv->irq_lock); | |
287 | ||
c67a470b PZ |
288 | if (dev_priv->pc8.irqs_disabled && |
289 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { | |
290 | WARN(1, "IRQs disabled\n"); | |
291 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; | |
292 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & | |
293 | interrupt_mask); | |
294 | return; | |
295 | } | |
296 | ||
fee884ed DV |
297 | I915_WRITE(SDEIMR, sdeimr); |
298 | POSTING_READ(SDEIMR); | |
299 | } | |
300 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
301 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
302 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
303 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
304 | ||
de28075d DV |
305 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
306 | enum transcoder pch_transcoder, | |
8664281b PZ |
307 | bool enable) |
308 | { | |
8664281b | 309 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
310 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
311 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
312 | |
313 | if (enable) | |
fee884ed | 314 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 315 | else |
fee884ed | 316 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
317 | } |
318 | ||
319 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
320 | enum transcoder pch_transcoder, | |
321 | bool enable) | |
322 | { | |
323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
324 | ||
325 | if (enable) { | |
1dd246fb DV |
326 | I915_WRITE(SERR_INT, |
327 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
328 | ||
8664281b PZ |
329 | if (!cpt_can_enable_serr_int(dev)) |
330 | return; | |
331 | ||
fee884ed | 332 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 333 | } else { |
1dd246fb DV |
334 | uint32_t tmp = I915_READ(SERR_INT); |
335 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
336 | ||
337 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 338 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
339 | |
340 | if (!was_enabled && | |
341 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
342 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
343 | transcoder_name(pch_transcoder)); | |
344 | } | |
8664281b | 345 | } |
8664281b PZ |
346 | } |
347 | ||
348 | /** | |
349 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
350 | * @dev: drm device | |
351 | * @pipe: pipe | |
352 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
353 | * | |
354 | * This function makes us disable or enable CPU fifo underruns for a specific | |
355 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
356 | * reporting for one pipe may also disable all the other CPU error interruts for | |
357 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
358 | * bit for all the pipes. | |
359 | * | |
360 | * Returns the previous state of underrun reporting. | |
361 | */ | |
362 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
363 | enum pipe pipe, bool enable) | |
364 | { | |
365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
366 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
368 | unsigned long flags; | |
369 | bool ret; | |
370 | ||
371 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
372 | ||
373 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
374 | ||
375 | if (enable == ret) | |
376 | goto done; | |
377 | ||
378 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
379 | ||
380 | if (IS_GEN5(dev) || IS_GEN6(dev)) | |
381 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); | |
382 | else if (IS_GEN7(dev)) | |
7336df65 | 383 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
8664281b PZ |
384 | |
385 | done: | |
386 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
387 | return ret; | |
388 | } | |
389 | ||
390 | /** | |
391 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
392 | * @dev: drm device | |
393 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
394 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
395 | * | |
396 | * This function makes us disable or enable PCH fifo underruns for a specific | |
397 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
398 | * underrun reporting for one transcoder may also disable all the other PCH | |
399 | * error interruts for the other transcoders, due to the fact that there's just | |
400 | * one interrupt mask/enable bit for all the transcoders. | |
401 | * | |
402 | * Returns the previous state of underrun reporting. | |
403 | */ | |
404 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
405 | enum transcoder pch_transcoder, | |
406 | bool enable) | |
407 | { | |
408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
409 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
411 | unsigned long flags; |
412 | bool ret; | |
413 | ||
de28075d DV |
414 | /* |
415 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
416 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
417 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
418 | * underrun statistics in crtc A. Since we never expose this anywhere | |
419 | * nor use it outside of the fifo underrun code here using the "wrong" | |
420 | * crtc on LPT won't cause issues. | |
421 | */ | |
8664281b PZ |
422 | |
423 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
424 | ||
425 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
426 | ||
427 | if (enable == ret) | |
428 | goto done; | |
429 | ||
430 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
431 | ||
432 | if (HAS_PCH_IBX(dev)) | |
de28075d | 433 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
434 | else |
435 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
436 | ||
437 | done: | |
438 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
439 | return ret; | |
440 | } | |
441 | ||
442 | ||
7c463586 KP |
443 | void |
444 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
445 | { | |
46c06a30 VS |
446 | u32 reg = PIPESTAT(pipe); |
447 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 448 | |
b79480ba DV |
449 | assert_spin_locked(&dev_priv->irq_lock); |
450 | ||
46c06a30 VS |
451 | if ((pipestat & mask) == mask) |
452 | return; | |
453 | ||
454 | /* Enable the interrupt, clear any pending status */ | |
455 | pipestat |= mask | (mask >> 16); | |
456 | I915_WRITE(reg, pipestat); | |
457 | POSTING_READ(reg); | |
7c463586 KP |
458 | } |
459 | ||
460 | void | |
461 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
462 | { | |
46c06a30 VS |
463 | u32 reg = PIPESTAT(pipe); |
464 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 465 | |
b79480ba DV |
466 | assert_spin_locked(&dev_priv->irq_lock); |
467 | ||
46c06a30 VS |
468 | if ((pipestat & mask) == 0) |
469 | return; | |
470 | ||
471 | pipestat &= ~mask; | |
472 | I915_WRITE(reg, pipestat); | |
473 | POSTING_READ(reg); | |
7c463586 KP |
474 | } |
475 | ||
01c66889 | 476 | /** |
f49e38dd | 477 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 478 | */ |
f49e38dd | 479 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 480 | { |
1ec14ad3 CW |
481 | drm_i915_private_t *dev_priv = dev->dev_private; |
482 | unsigned long irqflags; | |
483 | ||
f49e38dd JN |
484 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
485 | return; | |
486 | ||
1ec14ad3 | 487 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 488 | |
f898780b JN |
489 | i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); |
490 | if (INTEL_INFO(dev)->gen >= 4) | |
491 | i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); | |
1ec14ad3 CW |
492 | |
493 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
494 | } |
495 | ||
0a3e67a4 JB |
496 | /** |
497 | * i915_pipe_enabled - check if a pipe is enabled | |
498 | * @dev: DRM device | |
499 | * @pipe: pipe to check | |
500 | * | |
501 | * Reading certain registers when the pipe is disabled can hang the chip. | |
502 | * Use this routine to make sure the PLL is running and the pipe is active | |
503 | * before reading such registers if unsure. | |
504 | */ | |
505 | static int | |
506 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
507 | { | |
508 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 509 | |
a01025af DV |
510 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
511 | /* Locking is horribly broken here, but whatever. */ | |
512 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 514 | |
a01025af DV |
515 | return intel_crtc->active; |
516 | } else { | |
517 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
518 | } | |
0a3e67a4 JB |
519 | } |
520 | ||
42f52ef8 KP |
521 | /* Called from drm generic code, passed a 'crtc', which |
522 | * we use as a pipe index | |
523 | */ | |
f71d4af4 | 524 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
525 | { |
526 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
527 | unsigned long high_frame; | |
528 | unsigned long low_frame; | |
391f75e2 | 529 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
530 | |
531 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 532 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 533 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
534 | return 0; |
535 | } | |
536 | ||
391f75e2 VS |
537 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
538 | struct intel_crtc *intel_crtc = | |
539 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
540 | const struct drm_display_mode *mode = | |
541 | &intel_crtc->config.adjusted_mode; | |
542 | ||
543 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
544 | } else { | |
545 | enum transcoder cpu_transcoder = | |
546 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
547 | u32 htotal; | |
548 | ||
549 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
550 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
551 | ||
552 | vbl_start *= htotal; | |
553 | } | |
554 | ||
9db4a9c7 JB |
555 | high_frame = PIPEFRAME(pipe); |
556 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 557 | |
0a3e67a4 JB |
558 | /* |
559 | * High & low register fields aren't synchronized, so make sure | |
560 | * we get a low value that's stable across two reads of the high | |
561 | * register. | |
562 | */ | |
563 | do { | |
5eddb70b | 564 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 565 | low = I915_READ(low_frame); |
5eddb70b | 566 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
567 | } while (high1 != high2); |
568 | ||
5eddb70b | 569 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 570 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 571 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
572 | |
573 | /* | |
574 | * The frame counter increments at beginning of active. | |
575 | * Cook up a vblank counter by also checking the pixel | |
576 | * counter against vblank start. | |
577 | */ | |
578 | return ((high1 << 8) | low) + (pixel >= vbl_start); | |
0a3e67a4 JB |
579 | } |
580 | ||
f71d4af4 | 581 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
582 | { |
583 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 584 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
585 | |
586 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 587 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 588 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
589 | return 0; |
590 | } | |
591 | ||
592 | return I915_READ(reg); | |
593 | } | |
594 | ||
f71d4af4 | 595 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
596 | int *vpos, int *hpos) |
597 | { | |
c2baf4b7 VS |
598 | struct drm_i915_private *dev_priv = dev->dev_private; |
599 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
601 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 602 | int position; |
0af7e4df MK |
603 | int vbl_start, vbl_end, htotal, vtotal; |
604 | bool in_vbl = true; | |
605 | int ret = 0; | |
606 | ||
c2baf4b7 | 607 | if (!intel_crtc->active) { |
0af7e4df | 608 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 609 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
610 | return 0; |
611 | } | |
612 | ||
c2baf4b7 VS |
613 | htotal = mode->crtc_htotal; |
614 | vtotal = mode->crtc_vtotal; | |
615 | vbl_start = mode->crtc_vblank_start; | |
616 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 617 | |
c2baf4b7 VS |
618 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
619 | ||
620 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
0af7e4df MK |
621 | /* No obvious pixelcount register. Only query vertical |
622 | * scanout position from Display scan line register. | |
623 | */ | |
3aa18df8 | 624 | position = I915_READ(PIPEDSL(pipe)) & 0x1fff; |
0af7e4df MK |
625 | } else { |
626 | /* Have access to pixelcount since start of frame. | |
627 | * We can split this into vertical and horizontal | |
628 | * scanout position. | |
629 | */ | |
630 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
631 | ||
3aa18df8 VS |
632 | /* convert to pixel counts */ |
633 | vbl_start *= htotal; | |
634 | vbl_end *= htotal; | |
635 | vtotal *= htotal; | |
0af7e4df MK |
636 | } |
637 | ||
3aa18df8 VS |
638 | in_vbl = position >= vbl_start && position < vbl_end; |
639 | ||
640 | /* | |
641 | * While in vblank, position will be negative | |
642 | * counting up towards 0 at vbl_end. And outside | |
643 | * vblank, position will be positive counting | |
644 | * up since vbl_end. | |
645 | */ | |
646 | if (position >= vbl_start) | |
647 | position -= vbl_end; | |
648 | else | |
649 | position += vtotal - vbl_end; | |
0af7e4df | 650 | |
3aa18df8 VS |
651 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
652 | *vpos = position; | |
653 | *hpos = 0; | |
654 | } else { | |
655 | *vpos = position / htotal; | |
656 | *hpos = position - (*vpos * htotal); | |
657 | } | |
0af7e4df | 658 | |
0af7e4df MK |
659 | /* In vblank? */ |
660 | if (in_vbl) | |
661 | ret |= DRM_SCANOUTPOS_INVBL; | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
f71d4af4 | 666 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
667 | int *max_error, |
668 | struct timeval *vblank_time, | |
669 | unsigned flags) | |
670 | { | |
4041b853 | 671 | struct drm_crtc *crtc; |
0af7e4df | 672 | |
7eb552ae | 673 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 674 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
675 | return -EINVAL; |
676 | } | |
677 | ||
678 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
679 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
680 | if (crtc == NULL) { | |
681 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
682 | return -EINVAL; | |
683 | } | |
684 | ||
685 | if (!crtc->enabled) { | |
686 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
687 | return -EBUSY; | |
688 | } | |
0af7e4df MK |
689 | |
690 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
691 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
692 | vblank_time, flags, | |
693 | crtc); | |
0af7e4df MK |
694 | } |
695 | ||
67c347ff JN |
696 | static bool intel_hpd_irq_event(struct drm_device *dev, |
697 | struct drm_connector *connector) | |
321a1b30 EE |
698 | { |
699 | enum drm_connector_status old_status; | |
700 | ||
701 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
702 | old_status = connector->status; | |
703 | ||
704 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
705 | if (old_status == connector->status) |
706 | return false; | |
707 | ||
708 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
709 | connector->base.id, |
710 | drm_get_connector_name(connector), | |
67c347ff JN |
711 | drm_get_connector_status_name(old_status), |
712 | drm_get_connector_status_name(connector->status)); | |
713 | ||
714 | return true; | |
321a1b30 EE |
715 | } |
716 | ||
5ca58282 JB |
717 | /* |
718 | * Handle hotplug events outside the interrupt handler proper. | |
719 | */ | |
ac4c16c5 EE |
720 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
721 | ||
5ca58282 JB |
722 | static void i915_hotplug_work_func(struct work_struct *work) |
723 | { | |
724 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
725 | hotplug_work); | |
726 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 727 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
728 | struct intel_connector *intel_connector; |
729 | struct intel_encoder *intel_encoder; | |
730 | struct drm_connector *connector; | |
731 | unsigned long irqflags; | |
732 | bool hpd_disabled = false; | |
321a1b30 | 733 | bool changed = false; |
142e2398 | 734 | u32 hpd_event_bits; |
4ef69c7a | 735 | |
52d7eced DV |
736 | /* HPD irq before everything is fully set up. */ |
737 | if (!dev_priv->enable_hotplug_processing) | |
738 | return; | |
739 | ||
a65e34c7 | 740 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
741 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
742 | ||
cd569aed | 743 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
744 | |
745 | hpd_event_bits = dev_priv->hpd_event_bits; | |
746 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
747 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
748 | intel_connector = to_intel_connector(connector); | |
749 | intel_encoder = intel_connector->encoder; | |
750 | if (intel_encoder->hpd_pin > HPD_NONE && | |
751 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
752 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
753 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
754 | "switching from hotplug detection to polling\n", | |
755 | drm_get_connector_name(connector)); | |
756 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
757 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
758 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
759 | hpd_disabled = true; | |
760 | } | |
142e2398 EE |
761 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
762 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
763 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
764 | } | |
cd569aed EE |
765 | } |
766 | /* if there were no outputs to poll, poll was disabled, | |
767 | * therefore make sure it's enabled when disabling HPD on | |
768 | * some connectors */ | |
ac4c16c5 | 769 | if (hpd_disabled) { |
cd569aed | 770 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
771 | mod_timer(&dev_priv->hotplug_reenable_timer, |
772 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
773 | } | |
cd569aed EE |
774 | |
775 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
776 | ||
321a1b30 EE |
777 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
778 | intel_connector = to_intel_connector(connector); | |
779 | intel_encoder = intel_connector->encoder; | |
780 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
781 | if (intel_encoder->hot_plug) | |
782 | intel_encoder->hot_plug(intel_encoder); | |
783 | if (intel_hpd_irq_event(dev, connector)) | |
784 | changed = true; | |
785 | } | |
786 | } | |
40ee3381 KP |
787 | mutex_unlock(&mode_config->mutex); |
788 | ||
321a1b30 EE |
789 | if (changed) |
790 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
791 | } |
792 | ||
d0ecd7e2 | 793 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 JB |
794 | { |
795 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 796 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 797 | u8 new_delay; |
9270388e | 798 | |
d0ecd7e2 | 799 | spin_lock(&mchdev_lock); |
f97108d1 | 800 | |
73edd18f DV |
801 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
802 | ||
20e4d407 | 803 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 804 | |
7648fa99 | 805 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
806 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
807 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
808 | max_avg = I915_READ(RCBMAXAVG); |
809 | min_avg = I915_READ(RCBMINAVG); | |
810 | ||
811 | /* Handle RCS change request from hw */ | |
b5b72e89 | 812 | if (busy_up > max_avg) { |
20e4d407 DV |
813 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
814 | new_delay = dev_priv->ips.cur_delay - 1; | |
815 | if (new_delay < dev_priv->ips.max_delay) | |
816 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 817 | } else if (busy_down < min_avg) { |
20e4d407 DV |
818 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
819 | new_delay = dev_priv->ips.cur_delay + 1; | |
820 | if (new_delay > dev_priv->ips.min_delay) | |
821 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
822 | } |
823 | ||
7648fa99 | 824 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 825 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 826 | |
d0ecd7e2 | 827 | spin_unlock(&mchdev_lock); |
9270388e | 828 | |
f97108d1 JB |
829 | return; |
830 | } | |
831 | ||
549f7365 CW |
832 | static void notify_ring(struct drm_device *dev, |
833 | struct intel_ring_buffer *ring) | |
834 | { | |
475553de CW |
835 | if (ring->obj == NULL) |
836 | return; | |
837 | ||
814e9b57 | 838 | trace_i915_gem_request_complete(ring); |
9862e600 | 839 | |
549f7365 | 840 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 841 | i915_queue_hangcheck(dev); |
549f7365 CW |
842 | } |
843 | ||
4912d041 | 844 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 845 | { |
4912d041 | 846 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 847 | rps.work); |
edbfdb45 | 848 | u32 pm_iir; |
dd75fdc8 | 849 | int new_delay, adj; |
4912d041 | 850 | |
59cdb63d | 851 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
852 | pm_iir = dev_priv->rps.pm_iir; |
853 | dev_priv->rps.pm_iir = 0; | |
4848405c | 854 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
edbfdb45 | 855 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
59cdb63d | 856 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 857 | |
60611c13 PZ |
858 | /* Make sure we didn't queue anything we're not going to process. */ |
859 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); | |
860 | ||
4848405c | 861 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
862 | return; |
863 | ||
4fc688ce | 864 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 865 | |
dd75fdc8 | 866 | adj = dev_priv->rps.last_adj; |
7425034a | 867 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
868 | if (adj > 0) |
869 | adj *= 2; | |
870 | else | |
871 | adj = 1; | |
872 | new_delay = dev_priv->rps.cur_delay + adj; | |
7425034a VS |
873 | |
874 | /* | |
875 | * For better performance, jump directly | |
876 | * to RPe if we're below it. | |
877 | */ | |
dd75fdc8 CW |
878 | if (new_delay < dev_priv->rps.rpe_delay) |
879 | new_delay = dev_priv->rps.rpe_delay; | |
880 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { | |
881 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) | |
7425034a | 882 | new_delay = dev_priv->rps.rpe_delay; |
dd75fdc8 CW |
883 | else |
884 | new_delay = dev_priv->rps.min_delay; | |
885 | adj = 0; | |
886 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
887 | if (adj < 0) | |
888 | adj *= 2; | |
889 | else | |
890 | adj = -1; | |
891 | new_delay = dev_priv->rps.cur_delay + adj; | |
892 | } else { /* unknown event */ | |
893 | new_delay = dev_priv->rps.cur_delay; | |
894 | } | |
3b8d8d91 | 895 | |
79249636 BW |
896 | /* sysfs frequency interfaces may have snuck in while servicing the |
897 | * interrupt | |
898 | */ | |
dd75fdc8 CW |
899 | if (new_delay < (int)dev_priv->rps.min_delay) |
900 | new_delay = dev_priv->rps.min_delay; | |
901 | if (new_delay > (int)dev_priv->rps.max_delay) | |
902 | new_delay = dev_priv->rps.max_delay; | |
903 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; | |
904 | ||
905 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
906 | valleyview_set_rps(dev_priv->dev, new_delay); | |
907 | else | |
908 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 909 | |
4fc688ce | 910 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
911 | } |
912 | ||
e3689190 BW |
913 | |
914 | /** | |
915 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
916 | * occurred. | |
917 | * @work: workqueue struct | |
918 | * | |
919 | * Doesn't actually do anything except notify userspace. As a consequence of | |
920 | * this event, userspace should try to remap the bad rows since statistically | |
921 | * it is likely the same row is more likely to go bad again. | |
922 | */ | |
923 | static void ivybridge_parity_work(struct work_struct *work) | |
924 | { | |
925 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 926 | l3_parity.error_work); |
e3689190 | 927 | u32 error_status, row, bank, subbank; |
35a85ac6 | 928 | char *parity_event[6]; |
e3689190 BW |
929 | uint32_t misccpctl; |
930 | unsigned long flags; | |
35a85ac6 | 931 | uint8_t slice = 0; |
e3689190 BW |
932 | |
933 | /* We must turn off DOP level clock gating to access the L3 registers. | |
934 | * In order to prevent a get/put style interface, acquire struct mutex | |
935 | * any time we access those registers. | |
936 | */ | |
937 | mutex_lock(&dev_priv->dev->struct_mutex); | |
938 | ||
35a85ac6 BW |
939 | /* If we've screwed up tracking, just let the interrupt fire again */ |
940 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
941 | goto out; | |
942 | ||
e3689190 BW |
943 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
944 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
945 | POSTING_READ(GEN7_MISCCPCTL); | |
946 | ||
35a85ac6 BW |
947 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
948 | u32 reg; | |
e3689190 | 949 | |
35a85ac6 BW |
950 | slice--; |
951 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
952 | break; | |
e3689190 | 953 | |
35a85ac6 | 954 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 955 | |
35a85ac6 | 956 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 957 | |
35a85ac6 BW |
958 | error_status = I915_READ(reg); |
959 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
960 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
961 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
962 | ||
963 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
964 | POSTING_READ(reg); | |
965 | ||
966 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
967 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
968 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
969 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
970 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
971 | parity_event[5] = NULL; | |
972 | ||
973 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, | |
974 | KOBJ_CHANGE, parity_event); | |
e3689190 | 975 | |
35a85ac6 BW |
976 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
977 | slice, row, bank, subbank); | |
e3689190 | 978 | |
35a85ac6 BW |
979 | kfree(parity_event[4]); |
980 | kfree(parity_event[3]); | |
981 | kfree(parity_event[2]); | |
982 | kfree(parity_event[1]); | |
983 | } | |
e3689190 | 984 | |
35a85ac6 | 985 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 986 | |
35a85ac6 BW |
987 | out: |
988 | WARN_ON(dev_priv->l3_parity.which_slice); | |
989 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
990 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
991 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
992 | ||
993 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
994 | } |
995 | ||
35a85ac6 | 996 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 BW |
997 | { |
998 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e3689190 | 999 | |
040d2baa | 1000 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1001 | return; |
1002 | ||
d0ecd7e2 | 1003 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1004 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1005 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1006 | |
35a85ac6 BW |
1007 | iir &= GT_PARITY_ERROR(dev); |
1008 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1009 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1010 | ||
1011 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1012 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1013 | ||
a4da4fa4 | 1014 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1015 | } |
1016 | ||
f1af8fc1 PZ |
1017 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1018 | struct drm_i915_private *dev_priv, | |
1019 | u32 gt_iir) | |
1020 | { | |
1021 | if (gt_iir & | |
1022 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1023 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1024 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1025 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1026 | } | |
1027 | ||
e7b4c6b1 DV |
1028 | static void snb_gt_irq_handler(struct drm_device *dev, |
1029 | struct drm_i915_private *dev_priv, | |
1030 | u32 gt_iir) | |
1031 | { | |
1032 | ||
cc609d5d BW |
1033 | if (gt_iir & |
1034 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1035 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1036 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1037 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1038 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1039 | notify_ring(dev, &dev_priv->ring[BCS]); |
1040 | ||
cc609d5d BW |
1041 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1042 | GT_BSD_CS_ERROR_INTERRUPT | | |
1043 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
1044 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
1045 | i915_handle_error(dev, false); | |
1046 | } | |
e3689190 | 1047 | |
35a85ac6 BW |
1048 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1049 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1050 | } |
1051 | ||
b543fb04 EE |
1052 | #define HPD_STORM_DETECT_PERIOD 1000 |
1053 | #define HPD_STORM_THRESHOLD 5 | |
1054 | ||
10a504de | 1055 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1056 | u32 hotplug_trigger, |
1057 | const u32 *hpd) | |
b543fb04 EE |
1058 | { |
1059 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b543fb04 | 1060 | int i; |
10a504de | 1061 | bool storm_detected = false; |
b543fb04 | 1062 | |
91d131d2 DV |
1063 | if (!hotplug_trigger) |
1064 | return; | |
1065 | ||
b5ea2d56 | 1066 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1067 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1068 | |
b8f102e8 EE |
1069 | WARN(((hpd[i] & hotplug_trigger) && |
1070 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), | |
1071 | "Received HPD interrupt although disabled\n"); | |
1072 | ||
b543fb04 EE |
1073 | if (!(hpd[i] & hotplug_trigger) || |
1074 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1075 | continue; | |
1076 | ||
bc5ead8c | 1077 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1078 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1079 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1080 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1081 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1082 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1083 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1084 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1085 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1086 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1087 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1088 | storm_detected = true; |
b543fb04 EE |
1089 | } else { |
1090 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1091 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1092 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1093 | } |
1094 | } | |
1095 | ||
10a504de DV |
1096 | if (storm_detected) |
1097 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1098 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1099 | |
645416f5 DV |
1100 | /* |
1101 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1102 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1103 | * queue for otherwise the flush_work in the pageflip code will | |
1104 | * deadlock. | |
1105 | */ | |
1106 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1107 | } |
1108 | ||
515ac2bb DV |
1109 | static void gmbus_irq_handler(struct drm_device *dev) |
1110 | { | |
28c70f16 DV |
1111 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1112 | ||
28c70f16 | 1113 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1114 | } |
1115 | ||
ce99c256 DV |
1116 | static void dp_aux_irq_handler(struct drm_device *dev) |
1117 | { | |
9ee32fea DV |
1118 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1119 | ||
9ee32fea | 1120 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1121 | } |
1122 | ||
1403c0d4 PZ |
1123 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1124 | * IMR bits until the work is done. Other interrupts can be processed without | |
1125 | * the work queue. */ | |
1126 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1127 | { |
41a05a3a | 1128 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
59cdb63d | 1129 | spin_lock(&dev_priv->irq_lock); |
41a05a3a | 1130 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
4d3b3d5f | 1131 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
59cdb63d | 1132 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1133 | |
1134 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1135 | } |
baf02a1f | 1136 | |
1403c0d4 PZ |
1137 | if (HAS_VEBOX(dev_priv->dev)) { |
1138 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1139 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1140 | |
1403c0d4 PZ |
1141 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
1142 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
1143 | i915_handle_error(dev_priv->dev, false); | |
1144 | } | |
12638c57 | 1145 | } |
baf02a1f BW |
1146 | } |
1147 | ||
ff1f525e | 1148 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1149 | { |
1150 | struct drm_device *dev = (struct drm_device *) arg; | |
1151 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1152 | u32 iir, gt_iir, pm_iir; | |
1153 | irqreturn_t ret = IRQ_NONE; | |
1154 | unsigned long irqflags; | |
1155 | int pipe; | |
1156 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
1157 | |
1158 | atomic_inc(&dev_priv->irq_received); | |
1159 | ||
7e231dbe JB |
1160 | while (true) { |
1161 | iir = I915_READ(VLV_IIR); | |
1162 | gt_iir = I915_READ(GTIIR); | |
1163 | pm_iir = I915_READ(GEN6_PMIIR); | |
1164 | ||
1165 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1166 | goto out; | |
1167 | ||
1168 | ret = IRQ_HANDLED; | |
1169 | ||
e7b4c6b1 | 1170 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
1171 | |
1172 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1173 | for_each_pipe(pipe) { | |
1174 | int reg = PIPESTAT(pipe); | |
1175 | pipe_stats[pipe] = I915_READ(reg); | |
1176 | ||
1177 | /* | |
1178 | * Clear the PIPE*STAT regs before the IIR | |
1179 | */ | |
1180 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1181 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1182 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1183 | pipe_name(pipe)); | |
1184 | I915_WRITE(reg, pipe_stats[pipe]); | |
1185 | } | |
1186 | } | |
1187 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1188 | ||
31acc7f5 JB |
1189 | for_each_pipe(pipe) { |
1190 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
1191 | drm_handle_vblank(dev, pipe); | |
1192 | ||
1193 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
1194 | intel_prepare_page_flip(dev, pipe); | |
1195 | intel_finish_page_flip(dev, pipe); | |
1196 | } | |
1197 | } | |
1198 | ||
7e231dbe JB |
1199 | /* Consume port. Then clear IIR or we'll miss events */ |
1200 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1201 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1202 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe JB |
1203 | |
1204 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1205 | hotplug_status); | |
91d131d2 DV |
1206 | |
1207 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1208 | ||
7e231dbe JB |
1209 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1210 | I915_READ(PORT_HOTPLUG_STAT); | |
1211 | } | |
1212 | ||
515ac2bb DV |
1213 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
1214 | gmbus_irq_handler(dev); | |
7e231dbe | 1215 | |
60611c13 | 1216 | if (pm_iir) |
d0ecd7e2 | 1217 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1218 | |
1219 | I915_WRITE(GTIIR, gt_iir); | |
1220 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1221 | I915_WRITE(VLV_IIR, iir); | |
1222 | } | |
1223 | ||
1224 | out: | |
1225 | return ret; | |
1226 | } | |
1227 | ||
23e81d69 | 1228 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1229 | { |
1230 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1231 | int pipe; |
b543fb04 | 1232 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1233 | |
91d131d2 DV |
1234 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1235 | ||
cfc33bf7 VS |
1236 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1237 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1238 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1239 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1240 | port_name(port)); |
1241 | } | |
776ad806 | 1242 | |
ce99c256 DV |
1243 | if (pch_iir & SDE_AUX_MASK) |
1244 | dp_aux_irq_handler(dev); | |
1245 | ||
776ad806 | 1246 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1247 | gmbus_irq_handler(dev); |
776ad806 JB |
1248 | |
1249 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1250 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1251 | ||
1252 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1253 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1254 | ||
1255 | if (pch_iir & SDE_POISON) | |
1256 | DRM_ERROR("PCH poison interrupt\n"); | |
1257 | ||
9db4a9c7 JB |
1258 | if (pch_iir & SDE_FDI_MASK) |
1259 | for_each_pipe(pipe) | |
1260 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1261 | pipe_name(pipe), | |
1262 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1263 | |
1264 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1265 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1266 | ||
1267 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1268 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1269 | ||
776ad806 | 1270 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1271 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1272 | false)) | |
1273 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1274 | ||
1275 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1276 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1277 | false)) | |
1278 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1279 | } | |
1280 | ||
1281 | static void ivb_err_int_handler(struct drm_device *dev) | |
1282 | { | |
1283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1284 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
1285 | ||
de032bf4 PZ |
1286 | if (err_int & ERR_INT_POISON) |
1287 | DRM_ERROR("Poison interrupt\n"); | |
1288 | ||
8664281b PZ |
1289 | if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
1290 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1291 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1292 | ||
1293 | if (err_int & ERR_INT_FIFO_UNDERRUN_B) | |
1294 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1295 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1296 | ||
1297 | if (err_int & ERR_INT_FIFO_UNDERRUN_C) | |
1298 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) | |
1299 | DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); | |
1300 | ||
1301 | I915_WRITE(GEN7_ERR_INT, err_int); | |
1302 | } | |
1303 | ||
1304 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1305 | { | |
1306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1307 | u32 serr_int = I915_READ(SERR_INT); | |
1308 | ||
de032bf4 PZ |
1309 | if (serr_int & SERR_INT_POISON) |
1310 | DRM_ERROR("PCH poison interrupt\n"); | |
1311 | ||
8664281b PZ |
1312 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1313 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1314 | false)) | |
1315 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1316 | ||
1317 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1318 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1319 | false)) | |
1320 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1321 | ||
1322 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1323 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1324 | false)) | |
1325 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); | |
1326 | ||
1327 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1328 | } |
1329 | ||
23e81d69 AJ |
1330 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1331 | { | |
1332 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1333 | int pipe; | |
b543fb04 | 1334 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1335 | |
91d131d2 DV |
1336 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1337 | ||
cfc33bf7 VS |
1338 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1339 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1340 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1341 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1342 | port_name(port)); | |
1343 | } | |
23e81d69 AJ |
1344 | |
1345 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1346 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1347 | |
1348 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1349 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1350 | |
1351 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1352 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1353 | ||
1354 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1355 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1356 | ||
1357 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1358 | for_each_pipe(pipe) | |
1359 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1360 | pipe_name(pipe), | |
1361 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1362 | |
1363 | if (pch_iir & SDE_ERROR_CPT) | |
1364 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1365 | } |
1366 | ||
c008bc6e PZ |
1367 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1368 | { | |
1369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1370 | ||
1371 | if (de_iir & DE_AUX_CHANNEL_A) | |
1372 | dp_aux_irq_handler(dev); | |
1373 | ||
1374 | if (de_iir & DE_GSE) | |
1375 | intel_opregion_asle_intr(dev); | |
1376 | ||
1377 | if (de_iir & DE_PIPEA_VBLANK) | |
1378 | drm_handle_vblank(dev, 0); | |
1379 | ||
1380 | if (de_iir & DE_PIPEB_VBLANK) | |
1381 | drm_handle_vblank(dev, 1); | |
1382 | ||
1383 | if (de_iir & DE_POISON) | |
1384 | DRM_ERROR("Poison interrupt\n"); | |
1385 | ||
1386 | if (de_iir & DE_PIPEA_FIFO_UNDERRUN) | |
1387 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1388 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1389 | ||
1390 | if (de_iir & DE_PIPEB_FIFO_UNDERRUN) | |
1391 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1392 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1393 | ||
1394 | if (de_iir & DE_PLANEA_FLIP_DONE) { | |
1395 | intel_prepare_page_flip(dev, 0); | |
1396 | intel_finish_page_flip_plane(dev, 0); | |
1397 | } | |
1398 | ||
1399 | if (de_iir & DE_PLANEB_FLIP_DONE) { | |
1400 | intel_prepare_page_flip(dev, 1); | |
1401 | intel_finish_page_flip_plane(dev, 1); | |
1402 | } | |
1403 | ||
1404 | /* check event from PCH */ | |
1405 | if (de_iir & DE_PCH_EVENT) { | |
1406 | u32 pch_iir = I915_READ(SDEIIR); | |
1407 | ||
1408 | if (HAS_PCH_CPT(dev)) | |
1409 | cpt_irq_handler(dev, pch_iir); | |
1410 | else | |
1411 | ibx_irq_handler(dev, pch_iir); | |
1412 | ||
1413 | /* should clear PCH hotplug event before clear CPU irq */ | |
1414 | I915_WRITE(SDEIIR, pch_iir); | |
1415 | } | |
1416 | ||
1417 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1418 | ironlake_rps_change_irq_handler(dev); | |
1419 | } | |
1420 | ||
9719fb98 PZ |
1421 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1422 | { | |
1423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1424 | int i; | |
1425 | ||
1426 | if (de_iir & DE_ERR_INT_IVB) | |
1427 | ivb_err_int_handler(dev); | |
1428 | ||
1429 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1430 | dp_aux_irq_handler(dev); | |
1431 | ||
1432 | if (de_iir & DE_GSE_IVB) | |
1433 | intel_opregion_asle_intr(dev); | |
1434 | ||
1435 | for (i = 0; i < 3; i++) { | |
1436 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) | |
1437 | drm_handle_vblank(dev, i); | |
1438 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { | |
1439 | intel_prepare_page_flip(dev, i); | |
1440 | intel_finish_page_flip_plane(dev, i); | |
1441 | } | |
1442 | } | |
1443 | ||
1444 | /* check event from PCH */ | |
1445 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1446 | u32 pch_iir = I915_READ(SDEIIR); | |
1447 | ||
1448 | cpt_irq_handler(dev, pch_iir); | |
1449 | ||
1450 | /* clear PCH hotplug event before clear CPU irq */ | |
1451 | I915_WRITE(SDEIIR, pch_iir); | |
1452 | } | |
1453 | } | |
1454 | ||
f1af8fc1 | 1455 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1456 | { |
1457 | struct drm_device *dev = (struct drm_device *) arg; | |
1458 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
f1af8fc1 | 1459 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1460 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 JB |
1461 | |
1462 | atomic_inc(&dev_priv->irq_received); | |
1463 | ||
8664281b PZ |
1464 | /* We get interrupts on unclaimed registers, so check for this before we |
1465 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1466 | intel_uncore_check_errors(dev); |
8664281b | 1467 | |
b1f14ad0 JB |
1468 | /* disable master interrupt before clearing iir */ |
1469 | de_ier = I915_READ(DEIER); | |
1470 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1471 | POSTING_READ(DEIER); |
b1f14ad0 | 1472 | |
44498aea PZ |
1473 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1474 | * interrupts will will be stored on its back queue, and then we'll be | |
1475 | * able to process them after we restore SDEIER (as soon as we restore | |
1476 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1477 | * due to its back queue). */ | |
ab5c608b BW |
1478 | if (!HAS_PCH_NOP(dev)) { |
1479 | sde_ier = I915_READ(SDEIER); | |
1480 | I915_WRITE(SDEIER, 0); | |
1481 | POSTING_READ(SDEIER); | |
1482 | } | |
44498aea | 1483 | |
b1f14ad0 | 1484 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1485 | if (gt_iir) { |
d8fc8a47 | 1486 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1487 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1488 | else |
1489 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1490 | I915_WRITE(GTIIR, gt_iir); |
1491 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1492 | } |
1493 | ||
0e43406b CW |
1494 | de_iir = I915_READ(DEIIR); |
1495 | if (de_iir) { | |
f1af8fc1 PZ |
1496 | if (INTEL_INFO(dev)->gen >= 7) |
1497 | ivb_display_irq_handler(dev, de_iir); | |
1498 | else | |
1499 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1500 | I915_WRITE(DEIIR, de_iir); |
1501 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1502 | } |
1503 | ||
f1af8fc1 PZ |
1504 | if (INTEL_INFO(dev)->gen >= 6) { |
1505 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1506 | if (pm_iir) { | |
1403c0d4 | 1507 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1508 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1509 | ret = IRQ_HANDLED; | |
1510 | } | |
0e43406b | 1511 | } |
b1f14ad0 | 1512 | |
b1f14ad0 JB |
1513 | I915_WRITE(DEIER, de_ier); |
1514 | POSTING_READ(DEIER); | |
ab5c608b BW |
1515 | if (!HAS_PCH_NOP(dev)) { |
1516 | I915_WRITE(SDEIER, sde_ier); | |
1517 | POSTING_READ(SDEIER); | |
1518 | } | |
b1f14ad0 JB |
1519 | |
1520 | return ret; | |
1521 | } | |
1522 | ||
17e1df07 DV |
1523 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
1524 | bool reset_completed) | |
1525 | { | |
1526 | struct intel_ring_buffer *ring; | |
1527 | int i; | |
1528 | ||
1529 | /* | |
1530 | * Notify all waiters for GPU completion events that reset state has | |
1531 | * been changed, and that they need to restart their wait after | |
1532 | * checking for potential errors (and bail out to drop locks if there is | |
1533 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
1534 | */ | |
1535 | ||
1536 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
1537 | for_each_ring(ring, dev_priv, i) | |
1538 | wake_up_all(&ring->irq_queue); | |
1539 | ||
1540 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
1541 | wake_up_all(&dev_priv->pending_flip_queue); | |
1542 | ||
1543 | /* | |
1544 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
1545 | * reset state is cleared. | |
1546 | */ | |
1547 | if (reset_completed) | |
1548 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
1549 | } | |
1550 | ||
8a905236 JB |
1551 | /** |
1552 | * i915_error_work_func - do process context error handling work | |
1553 | * @work: work struct | |
1554 | * | |
1555 | * Fire an error uevent so userspace can see that a hang or error | |
1556 | * was detected. | |
1557 | */ | |
1558 | static void i915_error_work_func(struct work_struct *work) | |
1559 | { | |
1f83fee0 DV |
1560 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
1561 | work); | |
1562 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
1563 | gpu_error); | |
8a905236 | 1564 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
1565 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
1566 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
1567 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 1568 | int ret; |
8a905236 | 1569 | |
f316a42c BG |
1570 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
1571 | ||
7db0ba24 DV |
1572 | /* |
1573 | * Note that there's only one work item which does gpu resets, so we | |
1574 | * need not worry about concurrent gpu resets potentially incrementing | |
1575 | * error->reset_counter twice. We only need to take care of another | |
1576 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
1577 | * quick check for that is good enough: schedule_work ensures the | |
1578 | * correct ordering between hang detection and this work item, and since | |
1579 | * the reset in-progress bit is only ever set by code outside of this | |
1580 | * work we don't need to worry about any other races. | |
1581 | */ | |
1582 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 1583 | DRM_DEBUG_DRIVER("resetting chip\n"); |
7db0ba24 DV |
1584 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
1585 | reset_event); | |
1f83fee0 | 1586 | |
17e1df07 DV |
1587 | /* |
1588 | * All state reset _must_ be completed before we update the | |
1589 | * reset counter, for otherwise waiters might miss the reset | |
1590 | * pending state and not properly drop locks, resulting in | |
1591 | * deadlocks with the reset work. | |
1592 | */ | |
f69061be DV |
1593 | ret = i915_reset(dev); |
1594 | ||
17e1df07 DV |
1595 | intel_display_handle_reset(dev); |
1596 | ||
f69061be DV |
1597 | if (ret == 0) { |
1598 | /* | |
1599 | * After all the gem state is reset, increment the reset | |
1600 | * counter and wake up everyone waiting for the reset to | |
1601 | * complete. | |
1602 | * | |
1603 | * Since unlock operations are a one-sided barrier only, | |
1604 | * we need to insert a barrier here to order any seqno | |
1605 | * updates before | |
1606 | * the counter increment. | |
1607 | */ | |
1608 | smp_mb__before_atomic_inc(); | |
1609 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
1610 | ||
1611 | kobject_uevent_env(&dev->primary->kdev.kobj, | |
1612 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 DV |
1613 | } else { |
1614 | atomic_set(&error->reset_counter, I915_WEDGED); | |
f316a42c | 1615 | } |
1f83fee0 | 1616 | |
17e1df07 DV |
1617 | /* |
1618 | * Note: The wake_up also serves as a memory barrier so that | |
1619 | * waiters see the update value of the reset counter atomic_t. | |
1620 | */ | |
1621 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 1622 | } |
8a905236 JB |
1623 | } |
1624 | ||
35aed2e6 | 1625 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1626 | { |
1627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 1628 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 1629 | u32 eir = I915_READ(EIR); |
050ee91f | 1630 | int pipe, i; |
8a905236 | 1631 | |
35aed2e6 CW |
1632 | if (!eir) |
1633 | return; | |
8a905236 | 1634 | |
a70491cc | 1635 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 1636 | |
bd9854f9 BW |
1637 | i915_get_extra_instdone(dev, instdone); |
1638 | ||
8a905236 JB |
1639 | if (IS_G4X(dev)) { |
1640 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1641 | u32 ipeir = I915_READ(IPEIR_I965); | |
1642 | ||
a70491cc JP |
1643 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1644 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
1645 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1646 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 1647 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1648 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1649 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1650 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1651 | } |
1652 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1653 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1654 | pr_err("page table error\n"); |
1655 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1656 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1657 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1658 | } |
1659 | } | |
1660 | ||
a6c45cf0 | 1661 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1662 | if (eir & I915_ERROR_PAGE_TABLE) { |
1663 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1664 | pr_err("page table error\n"); |
1665 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1666 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1667 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1668 | } |
1669 | } | |
1670 | ||
1671 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 1672 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 1673 | for_each_pipe(pipe) |
a70491cc | 1674 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 1675 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
1676 | /* pipestat has already been acked */ |
1677 | } | |
1678 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
1679 | pr_err("instruction error\n"); |
1680 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
1681 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1682 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 1683 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1684 | u32 ipeir = I915_READ(IPEIR); |
1685 | ||
a70491cc JP |
1686 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
1687 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 1688 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 1689 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 1690 | POSTING_READ(IPEIR); |
8a905236 JB |
1691 | } else { |
1692 | u32 ipeir = I915_READ(IPEIR_I965); | |
1693 | ||
a70491cc JP |
1694 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1695 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 1696 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1697 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1698 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1699 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1700 | } |
1701 | } | |
1702 | ||
1703 | I915_WRITE(EIR, eir); | |
3143a2bf | 1704 | POSTING_READ(EIR); |
8a905236 JB |
1705 | eir = I915_READ(EIR); |
1706 | if (eir) { | |
1707 | /* | |
1708 | * some errors might have become stuck, | |
1709 | * mask them. | |
1710 | */ | |
1711 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1712 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1713 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1714 | } | |
35aed2e6 CW |
1715 | } |
1716 | ||
1717 | /** | |
1718 | * i915_handle_error - handle an error interrupt | |
1719 | * @dev: drm device | |
1720 | * | |
1721 | * Do some basic checking of regsiter state at error interrupt time and | |
1722 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1723 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1724 | * so userspace knows something bad happened (should trigger collection | |
1725 | * of a ring dump etc.). | |
1726 | */ | |
527f9e90 | 1727 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1728 | { |
1729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1730 | ||
1731 | i915_capture_error_state(dev); | |
1732 | i915_report_and_clear_eir(dev); | |
8a905236 | 1733 | |
ba1234d1 | 1734 | if (wedged) { |
f69061be DV |
1735 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
1736 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 1737 | |
11ed50ec | 1738 | /* |
17e1df07 DV |
1739 | * Wakeup waiting processes so that the reset work function |
1740 | * i915_error_work_func doesn't deadlock trying to grab various | |
1741 | * locks. By bumping the reset counter first, the woken | |
1742 | * processes will see a reset in progress and back off, | |
1743 | * releasing their locks and then wait for the reset completion. | |
1744 | * We must do this for _all_ gpu waiters that might hold locks | |
1745 | * that the reset work needs to acquire. | |
1746 | * | |
1747 | * Note: The wake_up serves as the required memory barrier to | |
1748 | * ensure that the waiters see the updated value of the reset | |
1749 | * counter atomic_t. | |
11ed50ec | 1750 | */ |
17e1df07 | 1751 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
1752 | } |
1753 | ||
122f46ba DV |
1754 | /* |
1755 | * Our reset work can grab modeset locks (since it needs to reset the | |
1756 | * state of outstanding pagelips). Hence it must not be run on our own | |
1757 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
1758 | * code will deadlock. | |
1759 | */ | |
1760 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
1761 | } |
1762 | ||
21ad8330 | 1763 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
1764 | { |
1765 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1766 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1768 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1769 | struct intel_unpin_work *work; |
1770 | unsigned long flags; | |
1771 | bool stall_detected; | |
1772 | ||
1773 | /* Ignore early vblank irqs */ | |
1774 | if (intel_crtc == NULL) | |
1775 | return; | |
1776 | ||
1777 | spin_lock_irqsave(&dev->event_lock, flags); | |
1778 | work = intel_crtc->unpin_work; | |
1779 | ||
e7d841ca CW |
1780 | if (work == NULL || |
1781 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
1782 | !work->enable_stall_check) { | |
4e5359cd SF |
1783 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
1784 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1785 | return; | |
1786 | } | |
1787 | ||
1788 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1789 | obj = work->pending_flip_obj; |
a6c45cf0 | 1790 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1791 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 1792 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 1793 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 1794 | } else { |
9db4a9c7 | 1795 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 1796 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
01f2c773 | 1797 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1798 | crtc->x * crtc->fb->bits_per_pixel/8); |
1799 | } | |
1800 | ||
1801 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1802 | ||
1803 | if (stall_detected) { | |
1804 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1805 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1806 | } | |
1807 | } | |
1808 | ||
42f52ef8 KP |
1809 | /* Called from drm generic code, passed 'crtc' which |
1810 | * we use as a pipe index | |
1811 | */ | |
f71d4af4 | 1812 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1813 | { |
1814 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1815 | unsigned long irqflags; |
71e0ffa5 | 1816 | |
5eddb70b | 1817 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1818 | return -EINVAL; |
0a3e67a4 | 1819 | |
1ec14ad3 | 1820 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1821 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1822 | i915_enable_pipestat(dev_priv, pipe, |
1823 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1824 | else |
7c463586 KP |
1825 | i915_enable_pipestat(dev_priv, pipe, |
1826 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1827 | |
1828 | /* maintain vblank delivery even in deep C-states */ | |
1829 | if (dev_priv->info->gen == 3) | |
6b26c86d | 1830 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 1831 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1832 | |
0a3e67a4 JB |
1833 | return 0; |
1834 | } | |
1835 | ||
f71d4af4 | 1836 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1837 | { |
1838 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1839 | unsigned long irqflags; | |
b518421f PZ |
1840 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
1841 | DE_PIPE_VBLANK_ILK(pipe); | |
f796cf8f JB |
1842 | |
1843 | if (!i915_pipe_enabled(dev, pipe)) | |
1844 | return -EINVAL; | |
1845 | ||
1846 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 1847 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
1848 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1849 | ||
1850 | return 0; | |
1851 | } | |
1852 | ||
7e231dbe JB |
1853 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
1854 | { | |
1855 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1856 | unsigned long irqflags; | |
31acc7f5 | 1857 | u32 imr; |
7e231dbe JB |
1858 | |
1859 | if (!i915_pipe_enabled(dev, pipe)) | |
1860 | return -EINVAL; | |
1861 | ||
1862 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 1863 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1864 | if (pipe == 0) |
7e231dbe | 1865 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1866 | else |
7e231dbe | 1867 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1868 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
1869 | i915_enable_pipestat(dev_priv, pipe, |
1870 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
1871 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1872 | ||
1873 | return 0; | |
1874 | } | |
1875 | ||
42f52ef8 KP |
1876 | /* Called from drm generic code, passed 'crtc' which |
1877 | * we use as a pipe index | |
1878 | */ | |
f71d4af4 | 1879 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1880 | { |
1881 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1882 | unsigned long irqflags; |
0a3e67a4 | 1883 | |
1ec14ad3 | 1884 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 1885 | if (dev_priv->info->gen == 3) |
6b26c86d | 1886 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 1887 | |
f796cf8f JB |
1888 | i915_disable_pipestat(dev_priv, pipe, |
1889 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1890 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1891 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1892 | } | |
1893 | ||
f71d4af4 | 1894 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1895 | { |
1896 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1897 | unsigned long irqflags; | |
b518421f PZ |
1898 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
1899 | DE_PIPE_VBLANK_ILK(pipe); | |
f796cf8f JB |
1900 | |
1901 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 1902 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
1903 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1904 | } | |
1905 | ||
7e231dbe JB |
1906 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
1907 | { | |
1908 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1909 | unsigned long irqflags; | |
31acc7f5 | 1910 | u32 imr; |
7e231dbe JB |
1911 | |
1912 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
1913 | i915_disable_pipestat(dev_priv, pipe, |
1914 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 1915 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1916 | if (pipe == 0) |
7e231dbe | 1917 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1918 | else |
7e231dbe | 1919 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 1920 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
1921 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1922 | } | |
1923 | ||
893eead0 CW |
1924 | static u32 |
1925 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1926 | { |
893eead0 CW |
1927 | return list_entry(ring->request_list.prev, |
1928 | struct drm_i915_gem_request, list)->seqno; | |
1929 | } | |
1930 | ||
9107e9d2 CW |
1931 | static bool |
1932 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
1933 | { | |
1934 | return (list_empty(&ring->request_list) || | |
1935 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
1936 | } |
1937 | ||
6274f212 CW |
1938 | static struct intel_ring_buffer * |
1939 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
1940 | { |
1941 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 1942 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
1943 | |
1944 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
1945 | if ((ipehr & ~(0x3 << 16)) != | |
1946 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 1947 | return NULL; |
a24a11e6 CW |
1948 | |
1949 | /* ACTHD is likely pointing to the dword after the actual command, | |
1950 | * so scan backwards until we find the MBOX. | |
1951 | */ | |
6274f212 | 1952 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
1953 | acthd_min = max((int)acthd - 3 * 4, 0); |
1954 | do { | |
1955 | cmd = ioread32(ring->virtual_start + acthd); | |
1956 | if (cmd == ipehr) | |
1957 | break; | |
1958 | ||
1959 | acthd -= 4; | |
1960 | if (acthd < acthd_min) | |
6274f212 | 1961 | return NULL; |
a24a11e6 CW |
1962 | } while (1); |
1963 | ||
6274f212 CW |
1964 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
1965 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
1966 | } |
1967 | ||
6274f212 CW |
1968 | static int semaphore_passed(struct intel_ring_buffer *ring) |
1969 | { | |
1970 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1971 | struct intel_ring_buffer *signaller; | |
1972 | u32 seqno, ctl; | |
1973 | ||
1974 | ring->hangcheck.deadlock = true; | |
1975 | ||
1976 | signaller = semaphore_waits_for(ring, &seqno); | |
1977 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
1978 | return -1; | |
1979 | ||
1980 | /* cursory check for an unkickable deadlock */ | |
1981 | ctl = I915_READ_CTL(signaller); | |
1982 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
1983 | return -1; | |
1984 | ||
1985 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
1986 | } | |
1987 | ||
1988 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
1989 | { | |
1990 | struct intel_ring_buffer *ring; | |
1991 | int i; | |
1992 | ||
1993 | for_each_ring(ring, dev_priv, i) | |
1994 | ring->hangcheck.deadlock = false; | |
1995 | } | |
1996 | ||
ad8beaea MK |
1997 | static enum intel_ring_hangcheck_action |
1998 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
1999 | { |
2000 | struct drm_device *dev = ring->dev; | |
2001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2002 | u32 tmp; |
2003 | ||
6274f212 | 2004 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2005 | return HANGCHECK_ACTIVE; |
6274f212 | 2006 | |
9107e9d2 | 2007 | if (IS_GEN2(dev)) |
f2f4d82f | 2008 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2009 | |
2010 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2011 | * If so we can simply poke the RB_WAIT bit | |
2012 | * and break the hang. This should work on | |
2013 | * all but the second generation chipsets. | |
2014 | */ | |
2015 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2016 | if (tmp & RING_WAIT) { |
2017 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2018 | ring->name); | |
09e14bf3 | 2019 | i915_handle_error(dev, false); |
1ec14ad3 | 2020 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2021 | return HANGCHECK_KICK; |
6274f212 CW |
2022 | } |
2023 | ||
2024 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2025 | switch (semaphore_passed(ring)) { | |
2026 | default: | |
f2f4d82f | 2027 | return HANGCHECK_HUNG; |
6274f212 CW |
2028 | case 1: |
2029 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2030 | ring->name); | |
09e14bf3 | 2031 | i915_handle_error(dev, false); |
6274f212 | 2032 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2033 | return HANGCHECK_KICK; |
6274f212 | 2034 | case 0: |
f2f4d82f | 2035 | return HANGCHECK_WAIT; |
6274f212 | 2036 | } |
9107e9d2 | 2037 | } |
ed5cbb03 | 2038 | |
f2f4d82f | 2039 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2040 | } |
2041 | ||
f65d9421 BG |
2042 | /** |
2043 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2044 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2045 | * if there are no progress, hangcheck score for that ring is increased. | |
2046 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2047 | * we kick the ring. If we see no progress on three subsequent calls | |
2048 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2049 | */ |
a658b5d2 | 2050 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2051 | { |
2052 | struct drm_device *dev = (struct drm_device *)data; | |
2053 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2054 | struct intel_ring_buffer *ring; |
b4519513 | 2055 | int i; |
05407ff8 | 2056 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2057 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2058 | #define BUSY 1 | |
2059 | #define KICK 5 | |
2060 | #define HUNG 20 | |
2061 | #define FIRE 30 | |
893eead0 | 2062 | |
3e0dc6b0 BW |
2063 | if (!i915_enable_hangcheck) |
2064 | return; | |
2065 | ||
b4519513 | 2066 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2067 | u32 seqno, acthd; |
9107e9d2 | 2068 | bool busy = true; |
05407ff8 | 2069 | |
6274f212 CW |
2070 | semaphore_clear_deadlocks(dev_priv); |
2071 | ||
05407ff8 MK |
2072 | seqno = ring->get_seqno(ring, false); |
2073 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2074 | |
9107e9d2 CW |
2075 | if (ring->hangcheck.seqno == seqno) { |
2076 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2077 | ring->hangcheck.action = HANGCHECK_IDLE; |
2078 | ||
9107e9d2 CW |
2079 | if (waitqueue_active(&ring->irq_queue)) { |
2080 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 CW |
2081 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
2082 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2083 | ring->name); | |
2084 | wake_up_all(&ring->irq_queue); | |
2085 | } | |
2086 | /* Safeguard against driver failure */ | |
2087 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2088 | } else |
2089 | busy = false; | |
05407ff8 | 2090 | } else { |
6274f212 CW |
2091 | /* We always increment the hangcheck score |
2092 | * if the ring is busy and still processing | |
2093 | * the same request, so that no single request | |
2094 | * can run indefinitely (such as a chain of | |
2095 | * batches). The only time we do not increment | |
2096 | * the hangcheck score on this ring, if this | |
2097 | * ring is in a legitimate wait for another | |
2098 | * ring. In that case the waiting ring is a | |
2099 | * victim and we want to be sure we catch the | |
2100 | * right culprit. Then every time we do kick | |
2101 | * the ring, add a small increment to the | |
2102 | * score so that we can catch a batch that is | |
2103 | * being repeatedly kicked and so responsible | |
2104 | * for stalling the machine. | |
2105 | */ | |
ad8beaea MK |
2106 | ring->hangcheck.action = ring_stuck(ring, |
2107 | acthd); | |
2108 | ||
2109 | switch (ring->hangcheck.action) { | |
da661464 | 2110 | case HANGCHECK_IDLE: |
f2f4d82f | 2111 | case HANGCHECK_WAIT: |
6274f212 | 2112 | break; |
f2f4d82f | 2113 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2114 | ring->hangcheck.score += BUSY; |
6274f212 | 2115 | break; |
f2f4d82f | 2116 | case HANGCHECK_KICK: |
ea04cb31 | 2117 | ring->hangcheck.score += KICK; |
6274f212 | 2118 | break; |
f2f4d82f | 2119 | case HANGCHECK_HUNG: |
ea04cb31 | 2120 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2121 | stuck[i] = true; |
2122 | break; | |
2123 | } | |
05407ff8 | 2124 | } |
9107e9d2 | 2125 | } else { |
da661464 MK |
2126 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2127 | ||
9107e9d2 CW |
2128 | /* Gradually reduce the count so that we catch DoS |
2129 | * attempts across multiple batches. | |
2130 | */ | |
2131 | if (ring->hangcheck.score > 0) | |
2132 | ring->hangcheck.score--; | |
d1e61e7f CW |
2133 | } |
2134 | ||
05407ff8 MK |
2135 | ring->hangcheck.seqno = seqno; |
2136 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2137 | busy_count += busy; |
893eead0 | 2138 | } |
b9201c14 | 2139 | |
92cab734 | 2140 | for_each_ring(ring, dev_priv, i) { |
9107e9d2 | 2141 | if (ring->hangcheck.score > FIRE) { |
b8d88d1d DV |
2142 | DRM_INFO("%s on %s\n", |
2143 | stuck[i] ? "stuck" : "no progress", | |
2144 | ring->name); | |
a43adf07 | 2145 | rings_hung++; |
92cab734 MK |
2146 | } |
2147 | } | |
2148 | ||
05407ff8 MK |
2149 | if (rings_hung) |
2150 | return i915_handle_error(dev, true); | |
f65d9421 | 2151 | |
05407ff8 MK |
2152 | if (busy_count) |
2153 | /* Reset timer case chip hangs without another request | |
2154 | * being added */ | |
10cd45b6 MK |
2155 | i915_queue_hangcheck(dev); |
2156 | } | |
2157 | ||
2158 | void i915_queue_hangcheck(struct drm_device *dev) | |
2159 | { | |
2160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2161 | if (!i915_enable_hangcheck) | |
2162 | return; | |
2163 | ||
2164 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2165 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2166 | } |
2167 | ||
91738a95 PZ |
2168 | static void ibx_irq_preinstall(struct drm_device *dev) |
2169 | { | |
2170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2171 | ||
2172 | if (HAS_PCH_NOP(dev)) | |
2173 | return; | |
2174 | ||
2175 | /* south display irq */ | |
2176 | I915_WRITE(SDEIMR, 0xffffffff); | |
2177 | /* | |
2178 | * SDEIER is also touched by the interrupt handler to work around missed | |
2179 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2180 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2181 | * sources here, but then only unmask them as needed with SDEIMR. | |
2182 | */ | |
2183 | I915_WRITE(SDEIER, 0xffffffff); | |
2184 | POSTING_READ(SDEIER); | |
2185 | } | |
2186 | ||
d18ea1b5 DV |
2187 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2188 | { | |
2189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2190 | ||
2191 | /* and GT */ | |
2192 | I915_WRITE(GTIMR, 0xffffffff); | |
2193 | I915_WRITE(GTIER, 0x0); | |
2194 | POSTING_READ(GTIER); | |
2195 | ||
2196 | if (INTEL_INFO(dev)->gen >= 6) { | |
2197 | /* and PM */ | |
2198 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2199 | I915_WRITE(GEN6_PMIER, 0x0); | |
2200 | POSTING_READ(GEN6_PMIER); | |
2201 | } | |
2202 | } | |
2203 | ||
1da177e4 LT |
2204 | /* drm_dma.h hooks |
2205 | */ | |
f71d4af4 | 2206 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2207 | { |
2208 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2209 | ||
4697995b JB |
2210 | atomic_set(&dev_priv->irq_received, 0); |
2211 | ||
036a4a7d | 2212 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 2213 | |
036a4a7d ZW |
2214 | I915_WRITE(DEIMR, 0xffffffff); |
2215 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2216 | POSTING_READ(DEIER); |
036a4a7d | 2217 | |
d18ea1b5 | 2218 | gen5_gt_irq_preinstall(dev); |
c650156a | 2219 | |
91738a95 | 2220 | ibx_irq_preinstall(dev); |
7d99163d BW |
2221 | } |
2222 | ||
7e231dbe JB |
2223 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2224 | { | |
2225 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2226 | int pipe; | |
2227 | ||
2228 | atomic_set(&dev_priv->irq_received, 0); | |
2229 | ||
7e231dbe JB |
2230 | /* VLV magic */ |
2231 | I915_WRITE(VLV_IMR, 0); | |
2232 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2233 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2234 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2235 | ||
7e231dbe JB |
2236 | /* and GT */ |
2237 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2238 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2239 | |
2240 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2241 | |
2242 | I915_WRITE(DPINVGTT, 0xff); | |
2243 | ||
2244 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2245 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2246 | for_each_pipe(pipe) | |
2247 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2248 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2249 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2250 | I915_WRITE(VLV_IER, 0x0); | |
2251 | POSTING_READ(VLV_IER); | |
2252 | } | |
2253 | ||
82a28bcf | 2254 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2255 | { |
2256 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2257 | struct drm_mode_config *mode_config = &dev->mode_config; |
2258 | struct intel_encoder *intel_encoder; | |
fee884ed | 2259 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2260 | |
2261 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2262 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2263 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2264 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2265 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2266 | } else { |
fee884ed | 2267 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2268 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2269 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2270 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2271 | } |
7fe0b973 | 2272 | |
fee884ed | 2273 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2274 | |
2275 | /* | |
2276 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2277 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2278 | * | |
2279 | * This register is the same on all known PCH chips. | |
2280 | */ | |
7fe0b973 KP |
2281 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2282 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2283 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2284 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2285 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2286 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2287 | } | |
2288 | ||
d46da437 PZ |
2289 | static void ibx_irq_postinstall(struct drm_device *dev) |
2290 | { | |
2291 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2292 | u32 mask; |
e5868a31 | 2293 | |
692a04cf DV |
2294 | if (HAS_PCH_NOP(dev)) |
2295 | return; | |
2296 | ||
8664281b PZ |
2297 | if (HAS_PCH_IBX(dev)) { |
2298 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2299 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2300 | } else { |
2301 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2302 | ||
2303 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2304 | } | |
ab5c608b | 2305 | |
d46da437 PZ |
2306 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2307 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2308 | } |
2309 | ||
0a9a8c91 DV |
2310 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2311 | { | |
2312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2313 | u32 pm_irqs, gt_irqs; | |
2314 | ||
2315 | pm_irqs = gt_irqs = 0; | |
2316 | ||
2317 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2318 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2319 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2320 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2321 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2322 | } |
2323 | ||
2324 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2325 | if (IS_GEN5(dev)) { | |
2326 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2327 | ILK_BSD_USER_INTERRUPT; | |
2328 | } else { | |
2329 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2330 | } | |
2331 | ||
2332 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2333 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2334 | I915_WRITE(GTIER, gt_irqs); | |
2335 | POSTING_READ(GTIER); | |
2336 | ||
2337 | if (INTEL_INFO(dev)->gen >= 6) { | |
2338 | pm_irqs |= GEN6_PM_RPS_EVENTS; | |
2339 | ||
2340 | if (HAS_VEBOX(dev)) | |
2341 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2342 | ||
605cd25b | 2343 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2344 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2345 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2346 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2347 | POSTING_READ(GEN6_PMIER); | |
2348 | } | |
2349 | } | |
2350 | ||
f71d4af4 | 2351 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2352 | { |
4bc9d430 | 2353 | unsigned long irqflags; |
036a4a7d | 2354 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
8e76f8dc PZ |
2355 | u32 display_mask, extra_mask; |
2356 | ||
2357 | if (INTEL_INFO(dev)->gen >= 7) { | |
2358 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2359 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2360 | DE_PLANEB_FLIP_DONE_IVB | | |
2361 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | | |
2362 | DE_ERR_INT_IVB); | |
2363 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | | |
2364 | DE_PIPEA_VBLANK_IVB); | |
2365 | ||
2366 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2367 | } else { | |
2368 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2369 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
2370 | DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | | |
2371 | DE_PIPEA_FIFO_UNDERRUN | DE_POISON); | |
2372 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; | |
2373 | } | |
036a4a7d | 2374 | |
1ec14ad3 | 2375 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2376 | |
2377 | /* should always can generate irq */ | |
2378 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 2379 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 2380 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 2381 | POSTING_READ(DEIER); |
036a4a7d | 2382 | |
0a9a8c91 | 2383 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 2384 | |
d46da437 | 2385 | ibx_irq_postinstall(dev); |
7fe0b973 | 2386 | |
f97108d1 | 2387 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
2388 | /* Enable PCU event interrupts |
2389 | * | |
2390 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
2391 | * setup is guaranteed to run in single-threaded context. But we |
2392 | * need it to make the assert_spin_locked happy. */ | |
2393 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 2394 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 2395 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
2396 | } |
2397 | ||
036a4a7d ZW |
2398 | return 0; |
2399 | } | |
2400 | ||
7e231dbe JB |
2401 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2402 | { | |
2403 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2404 | u32 enable_mask; |
31acc7f5 | 2405 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
b79480ba | 2406 | unsigned long irqflags; |
7e231dbe JB |
2407 | |
2408 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2409 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2410 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2411 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2412 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2413 | ||
31acc7f5 JB |
2414 | /* |
2415 | *Leave vblank interrupts masked initially. enable/disable will | |
2416 | * toggle them based on usage. | |
2417 | */ | |
2418 | dev_priv->irq_mask = (~enable_mask) | | |
2419 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2420 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2421 | |
20afbda2 DV |
2422 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2423 | POSTING_READ(PORT_HOTPLUG_EN); | |
2424 | ||
7e231dbe JB |
2425 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2426 | I915_WRITE(VLV_IER, enable_mask); | |
2427 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2428 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2429 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2430 | POSTING_READ(VLV_IER); | |
2431 | ||
b79480ba DV |
2432 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
2433 | * just to make the assert_spin_locked check happy. */ | |
2434 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2435 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
515ac2bb | 2436 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
31acc7f5 | 2437 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
b79480ba | 2438 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2439 | |
7e231dbe JB |
2440 | I915_WRITE(VLV_IIR, 0xffffffff); |
2441 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2442 | ||
0a9a8c91 | 2443 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
2444 | |
2445 | /* ack & enable invalid PTE error interrupts */ | |
2446 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2447 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2448 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2449 | #endif | |
2450 | ||
2451 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2452 | |
2453 | return 0; | |
2454 | } | |
2455 | ||
7e231dbe JB |
2456 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2457 | { | |
2458 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2459 | int pipe; | |
2460 | ||
2461 | if (!dev_priv) | |
2462 | return; | |
2463 | ||
ac4c16c5 EE |
2464 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2465 | ||
7e231dbe JB |
2466 | for_each_pipe(pipe) |
2467 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2468 | ||
2469 | I915_WRITE(HWSTAM, 0xffffffff); | |
2470 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2471 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2472 | for_each_pipe(pipe) | |
2473 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2474 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2475 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2476 | I915_WRITE(VLV_IER, 0x0); | |
2477 | POSTING_READ(VLV_IER); | |
2478 | } | |
2479 | ||
f71d4af4 | 2480 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2481 | { |
2482 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2483 | |
2484 | if (!dev_priv) | |
2485 | return; | |
2486 | ||
ac4c16c5 EE |
2487 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2488 | ||
036a4a7d ZW |
2489 | I915_WRITE(HWSTAM, 0xffffffff); |
2490 | ||
2491 | I915_WRITE(DEIMR, 0xffffffff); | |
2492 | I915_WRITE(DEIER, 0x0); | |
2493 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
2494 | if (IS_GEN7(dev)) |
2495 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
2496 | |
2497 | I915_WRITE(GTIMR, 0xffffffff); | |
2498 | I915_WRITE(GTIER, 0x0); | |
2499 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 2500 | |
ab5c608b BW |
2501 | if (HAS_PCH_NOP(dev)) |
2502 | return; | |
2503 | ||
192aac1f KP |
2504 | I915_WRITE(SDEIMR, 0xffffffff); |
2505 | I915_WRITE(SDEIER, 0x0); | |
2506 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
2507 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
2508 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
2509 | } |
2510 | ||
a266c7d5 | 2511 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2512 | { |
2513 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2514 | int pipe; |
91e3738e | 2515 | |
a266c7d5 | 2516 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 2517 | |
9db4a9c7 JB |
2518 | for_each_pipe(pipe) |
2519 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
2520 | I915_WRITE16(IMR, 0xffff); |
2521 | I915_WRITE16(IER, 0x0); | |
2522 | POSTING_READ16(IER); | |
c2798b19 CW |
2523 | } |
2524 | ||
2525 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
2526 | { | |
2527 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2528 | ||
c2798b19 CW |
2529 | I915_WRITE16(EMR, |
2530 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
2531 | ||
2532 | /* Unmask the interrupts that we always want on. */ | |
2533 | dev_priv->irq_mask = | |
2534 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2535 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2536 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2537 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2538 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2539 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
2540 | ||
2541 | I915_WRITE16(IER, | |
2542 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2543 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2544 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2545 | I915_USER_INTERRUPT); | |
2546 | POSTING_READ16(IER); | |
2547 | ||
2548 | return 0; | |
2549 | } | |
2550 | ||
90a72f87 VS |
2551 | /* |
2552 | * Returns true when a page flip has completed. | |
2553 | */ | |
2554 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
2555 | int pipe, u16 iir) | |
2556 | { | |
2557 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2558 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); | |
2559 | ||
2560 | if (!drm_handle_vblank(dev, pipe)) | |
2561 | return false; | |
2562 | ||
2563 | if ((iir & flip_pending) == 0) | |
2564 | return false; | |
2565 | ||
2566 | intel_prepare_page_flip(dev, pipe); | |
2567 | ||
2568 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2569 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2570 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2571 | * the flip is completed (no longer pending). Since this doesn't raise | |
2572 | * an interrupt per se, we watch for the change at vblank. | |
2573 | */ | |
2574 | if (I915_READ16(ISR) & flip_pending) | |
2575 | return false; | |
2576 | ||
2577 | intel_finish_page_flip(dev, pipe); | |
2578 | ||
2579 | return true; | |
2580 | } | |
2581 | ||
ff1f525e | 2582 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
2583 | { |
2584 | struct drm_device *dev = (struct drm_device *) arg; | |
2585 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
2586 | u16 iir, new_iir; |
2587 | u32 pipe_stats[2]; | |
2588 | unsigned long irqflags; | |
c2798b19 CW |
2589 | int pipe; |
2590 | u16 flip_mask = | |
2591 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2592 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2593 | ||
2594 | atomic_inc(&dev_priv->irq_received); | |
2595 | ||
2596 | iir = I915_READ16(IIR); | |
2597 | if (iir == 0) | |
2598 | return IRQ_NONE; | |
2599 | ||
2600 | while (iir & ~flip_mask) { | |
2601 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2602 | * have been cleared after the pipestat interrupt was received. | |
2603 | * It doesn't set the bit in iir again, but it still produces | |
2604 | * interrupts (for non-MSI). | |
2605 | */ | |
2606 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2607 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2608 | i915_handle_error(dev, false); | |
2609 | ||
2610 | for_each_pipe(pipe) { | |
2611 | int reg = PIPESTAT(pipe); | |
2612 | pipe_stats[pipe] = I915_READ(reg); | |
2613 | ||
2614 | /* | |
2615 | * Clear the PIPE*STAT regs before the IIR | |
2616 | */ | |
2617 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2618 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2619 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2620 | pipe_name(pipe)); | |
2621 | I915_WRITE(reg, pipe_stats[pipe]); | |
c2798b19 CW |
2622 | } |
2623 | } | |
2624 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2625 | ||
2626 | I915_WRITE16(IIR, iir & ~flip_mask); | |
2627 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
2628 | ||
d05c617e | 2629 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
2630 | |
2631 | if (iir & I915_USER_INTERRUPT) | |
2632 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2633 | ||
2634 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2635 | i8xx_handle_vblank(dev, 0, iir)) |
2636 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); | |
c2798b19 CW |
2637 | |
2638 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2639 | i8xx_handle_vblank(dev, 1, iir)) |
2640 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); | |
c2798b19 CW |
2641 | |
2642 | iir = new_iir; | |
2643 | } | |
2644 | ||
2645 | return IRQ_HANDLED; | |
2646 | } | |
2647 | ||
2648 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
2649 | { | |
2650 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2651 | int pipe; | |
2652 | ||
c2798b19 CW |
2653 | for_each_pipe(pipe) { |
2654 | /* Clear enable bits; then clear status bits */ | |
2655 | I915_WRITE(PIPESTAT(pipe), 0); | |
2656 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
2657 | } | |
2658 | I915_WRITE16(IMR, 0xffff); | |
2659 | I915_WRITE16(IER, 0x0); | |
2660 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
2661 | } | |
2662 | ||
a266c7d5 CW |
2663 | static void i915_irq_preinstall(struct drm_device * dev) |
2664 | { | |
2665 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2666 | int pipe; | |
2667 | ||
2668 | atomic_set(&dev_priv->irq_received, 0); | |
2669 | ||
2670 | if (I915_HAS_HOTPLUG(dev)) { | |
2671 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2672 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2673 | } | |
2674 | ||
00d98ebd | 2675 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
2676 | for_each_pipe(pipe) |
2677 | I915_WRITE(PIPESTAT(pipe), 0); | |
2678 | I915_WRITE(IMR, 0xffffffff); | |
2679 | I915_WRITE(IER, 0x0); | |
2680 | POSTING_READ(IER); | |
2681 | } | |
2682 | ||
2683 | static int i915_irq_postinstall(struct drm_device *dev) | |
2684 | { | |
2685 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 2686 | u32 enable_mask; |
a266c7d5 | 2687 | |
38bde180 CW |
2688 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
2689 | ||
2690 | /* Unmask the interrupts that we always want on. */ | |
2691 | dev_priv->irq_mask = | |
2692 | ~(I915_ASLE_INTERRUPT | | |
2693 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2694 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2695 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2696 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2697 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2698 | ||
2699 | enable_mask = | |
2700 | I915_ASLE_INTERRUPT | | |
2701 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2702 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2703 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2704 | I915_USER_INTERRUPT; | |
2705 | ||
a266c7d5 | 2706 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
2707 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2708 | POSTING_READ(PORT_HOTPLUG_EN); | |
2709 | ||
a266c7d5 CW |
2710 | /* Enable in IER... */ |
2711 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2712 | /* and unmask in IMR */ | |
2713 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
2714 | } | |
2715 | ||
a266c7d5 CW |
2716 | I915_WRITE(IMR, dev_priv->irq_mask); |
2717 | I915_WRITE(IER, enable_mask); | |
2718 | POSTING_READ(IER); | |
2719 | ||
f49e38dd | 2720 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
2721 | |
2722 | return 0; | |
2723 | } | |
2724 | ||
90a72f87 VS |
2725 | /* |
2726 | * Returns true when a page flip has completed. | |
2727 | */ | |
2728 | static bool i915_handle_vblank(struct drm_device *dev, | |
2729 | int plane, int pipe, u32 iir) | |
2730 | { | |
2731 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2732 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
2733 | ||
2734 | if (!drm_handle_vblank(dev, pipe)) | |
2735 | return false; | |
2736 | ||
2737 | if ((iir & flip_pending) == 0) | |
2738 | return false; | |
2739 | ||
2740 | intel_prepare_page_flip(dev, plane); | |
2741 | ||
2742 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2743 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2744 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2745 | * the flip is completed (no longer pending). Since this doesn't raise | |
2746 | * an interrupt per se, we watch for the change at vblank. | |
2747 | */ | |
2748 | if (I915_READ(ISR) & flip_pending) | |
2749 | return false; | |
2750 | ||
2751 | intel_finish_page_flip(dev, pipe); | |
2752 | ||
2753 | return true; | |
2754 | } | |
2755 | ||
ff1f525e | 2756 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
2757 | { |
2758 | struct drm_device *dev = (struct drm_device *) arg; | |
2759 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 2760 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 2761 | unsigned long irqflags; |
38bde180 CW |
2762 | u32 flip_mask = |
2763 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2764 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 2765 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
2766 | |
2767 | atomic_inc(&dev_priv->irq_received); | |
2768 | ||
2769 | iir = I915_READ(IIR); | |
38bde180 CW |
2770 | do { |
2771 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 2772 | bool blc_event = false; |
a266c7d5 CW |
2773 | |
2774 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2775 | * have been cleared after the pipestat interrupt was received. | |
2776 | * It doesn't set the bit in iir again, but it still produces | |
2777 | * interrupts (for non-MSI). | |
2778 | */ | |
2779 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2780 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2781 | i915_handle_error(dev, false); | |
2782 | ||
2783 | for_each_pipe(pipe) { | |
2784 | int reg = PIPESTAT(pipe); | |
2785 | pipe_stats[pipe] = I915_READ(reg); | |
2786 | ||
38bde180 | 2787 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
2788 | if (pipe_stats[pipe] & 0x8000ffff) { |
2789 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2790 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2791 | pipe_name(pipe)); | |
2792 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 2793 | irq_received = true; |
a266c7d5 CW |
2794 | } |
2795 | } | |
2796 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2797 | ||
2798 | if (!irq_received) | |
2799 | break; | |
2800 | ||
a266c7d5 CW |
2801 | /* Consume port. Then clear IIR or we'll miss events */ |
2802 | if ((I915_HAS_HOTPLUG(dev)) && | |
2803 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
2804 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 2805 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 CW |
2806 | |
2807 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2808 | hotplug_status); | |
91d131d2 DV |
2809 | |
2810 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
2811 | ||
a266c7d5 | 2812 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 2813 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
2814 | } |
2815 | ||
38bde180 | 2816 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
2817 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
2818 | ||
a266c7d5 CW |
2819 | if (iir & I915_USER_INTERRUPT) |
2820 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 2821 | |
a266c7d5 | 2822 | for_each_pipe(pipe) { |
38bde180 CW |
2823 | int plane = pipe; |
2824 | if (IS_MOBILE(dev)) | |
2825 | plane = !plane; | |
90a72f87 | 2826 | |
8291ee90 | 2827 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
2828 | i915_handle_vblank(dev, plane, pipe, iir)) |
2829 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
2830 | |
2831 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2832 | blc_event = true; | |
2833 | } | |
2834 | ||
a266c7d5 CW |
2835 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
2836 | intel_opregion_asle_intr(dev); | |
2837 | ||
2838 | /* With MSI, interrupts are only generated when iir | |
2839 | * transitions from zero to nonzero. If another bit got | |
2840 | * set while we were handling the existing iir bits, then | |
2841 | * we would never get another interrupt. | |
2842 | * | |
2843 | * This is fine on non-MSI as well, as if we hit this path | |
2844 | * we avoid exiting the interrupt handler only to generate | |
2845 | * another one. | |
2846 | * | |
2847 | * Note that for MSI this could cause a stray interrupt report | |
2848 | * if an interrupt landed in the time between writing IIR and | |
2849 | * the posting read. This should be rare enough to never | |
2850 | * trigger the 99% of 100,000 interrupts test for disabling | |
2851 | * stray interrupts. | |
2852 | */ | |
38bde180 | 2853 | ret = IRQ_HANDLED; |
a266c7d5 | 2854 | iir = new_iir; |
38bde180 | 2855 | } while (iir & ~flip_mask); |
a266c7d5 | 2856 | |
d05c617e | 2857 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 2858 | |
a266c7d5 CW |
2859 | return ret; |
2860 | } | |
2861 | ||
2862 | static void i915_irq_uninstall(struct drm_device * dev) | |
2863 | { | |
2864 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2865 | int pipe; | |
2866 | ||
ac4c16c5 EE |
2867 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2868 | ||
a266c7d5 CW |
2869 | if (I915_HAS_HOTPLUG(dev)) { |
2870 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2871 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2872 | } | |
2873 | ||
00d98ebd | 2874 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
2875 | for_each_pipe(pipe) { |
2876 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 2877 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
2878 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
2879 | } | |
a266c7d5 CW |
2880 | I915_WRITE(IMR, 0xffffffff); |
2881 | I915_WRITE(IER, 0x0); | |
2882 | ||
a266c7d5 CW |
2883 | I915_WRITE(IIR, I915_READ(IIR)); |
2884 | } | |
2885 | ||
2886 | static void i965_irq_preinstall(struct drm_device * dev) | |
2887 | { | |
2888 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2889 | int pipe; | |
2890 | ||
2891 | atomic_set(&dev_priv->irq_received, 0); | |
2892 | ||
adca4730 CW |
2893 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2894 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
2895 | |
2896 | I915_WRITE(HWSTAM, 0xeffe); | |
2897 | for_each_pipe(pipe) | |
2898 | I915_WRITE(PIPESTAT(pipe), 0); | |
2899 | I915_WRITE(IMR, 0xffffffff); | |
2900 | I915_WRITE(IER, 0x0); | |
2901 | POSTING_READ(IER); | |
2902 | } | |
2903 | ||
2904 | static int i965_irq_postinstall(struct drm_device *dev) | |
2905 | { | |
2906 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 2907 | u32 enable_mask; |
a266c7d5 | 2908 | u32 error_mask; |
b79480ba | 2909 | unsigned long irqflags; |
a266c7d5 | 2910 | |
a266c7d5 | 2911 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 2912 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 2913 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
2914 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2915 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2916 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2917 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2918 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2919 | ||
2920 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
2921 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
2922 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
2923 | enable_mask |= I915_USER_INTERRUPT; |
2924 | ||
2925 | if (IS_G4X(dev)) | |
2926 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 2927 | |
b79480ba DV |
2928 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
2929 | * just to make the assert_spin_locked check happy. */ | |
2930 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
515ac2bb | 2931 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
b79480ba | 2932 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 2933 | |
a266c7d5 CW |
2934 | /* |
2935 | * Enable some error detection, note the instruction error mask | |
2936 | * bit is reserved, so we leave it masked. | |
2937 | */ | |
2938 | if (IS_G4X(dev)) { | |
2939 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
2940 | GM45_ERROR_MEM_PRIV | | |
2941 | GM45_ERROR_CP_PRIV | | |
2942 | I915_ERROR_MEMORY_REFRESH); | |
2943 | } else { | |
2944 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
2945 | I915_ERROR_MEMORY_REFRESH); | |
2946 | } | |
2947 | I915_WRITE(EMR, error_mask); | |
2948 | ||
2949 | I915_WRITE(IMR, dev_priv->irq_mask); | |
2950 | I915_WRITE(IER, enable_mask); | |
2951 | POSTING_READ(IER); | |
2952 | ||
20afbda2 DV |
2953 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2954 | POSTING_READ(PORT_HOTPLUG_EN); | |
2955 | ||
f49e38dd | 2956 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
2957 | |
2958 | return 0; | |
2959 | } | |
2960 | ||
bac56d5b | 2961 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
2962 | { |
2963 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 2964 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 2965 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
2966 | u32 hotplug_en; |
2967 | ||
b5ea2d56 DV |
2968 | assert_spin_locked(&dev_priv->irq_lock); |
2969 | ||
bac56d5b EE |
2970 | if (I915_HAS_HOTPLUG(dev)) { |
2971 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
2972 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
2973 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 2974 | /* enable bits are the same for all generations */ |
cd569aed EE |
2975 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
2976 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
2977 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
2978 | /* Programming the CRT detection parameters tends |
2979 | to generate a spurious hotplug event about three | |
2980 | seconds later. So just do it once. | |
2981 | */ | |
2982 | if (IS_G4X(dev)) | |
2983 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 2984 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 2985 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 2986 | |
bac56d5b EE |
2987 | /* Ignore TV since it's buggy */ |
2988 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
2989 | } | |
a266c7d5 CW |
2990 | } |
2991 | ||
ff1f525e | 2992 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
2993 | { |
2994 | struct drm_device *dev = (struct drm_device *) arg; | |
2995 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
2996 | u32 iir, new_iir; |
2997 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
2998 | unsigned long irqflags; |
2999 | int irq_received; | |
3000 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
3001 | u32 flip_mask = |
3002 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3003 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
3004 | |
3005 | atomic_inc(&dev_priv->irq_received); | |
3006 | ||
3007 | iir = I915_READ(IIR); | |
3008 | ||
a266c7d5 | 3009 | for (;;) { |
2c8ba29f CW |
3010 | bool blc_event = false; |
3011 | ||
21ad8330 | 3012 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
3013 | |
3014 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3015 | * have been cleared after the pipestat interrupt was received. | |
3016 | * It doesn't set the bit in iir again, but it still produces | |
3017 | * interrupts (for non-MSI). | |
3018 | */ | |
3019 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3020 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3021 | i915_handle_error(dev, false); | |
3022 | ||
3023 | for_each_pipe(pipe) { | |
3024 | int reg = PIPESTAT(pipe); | |
3025 | pipe_stats[pipe] = I915_READ(reg); | |
3026 | ||
3027 | /* | |
3028 | * Clear the PIPE*STAT regs before the IIR | |
3029 | */ | |
3030 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3031 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3032 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3033 | pipe_name(pipe)); | |
3034 | I915_WRITE(reg, pipe_stats[pipe]); | |
3035 | irq_received = 1; | |
3036 | } | |
3037 | } | |
3038 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3039 | ||
3040 | if (!irq_received) | |
3041 | break; | |
3042 | ||
3043 | ret = IRQ_HANDLED; | |
3044 | ||
3045 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3046 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3047 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3048 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3049 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3050 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 CW |
3051 | |
3052 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3053 | hotplug_status); | |
91d131d2 DV |
3054 | |
3055 | intel_hpd_irq_handler(dev, hotplug_trigger, | |
3056 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); | |
3057 | ||
a266c7d5 CW |
3058 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3059 | I915_READ(PORT_HOTPLUG_STAT); | |
3060 | } | |
3061 | ||
21ad8330 | 3062 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3063 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3064 | ||
a266c7d5 CW |
3065 | if (iir & I915_USER_INTERRUPT) |
3066 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3067 | if (iir & I915_BSD_USER_INTERRUPT) | |
3068 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3069 | ||
a266c7d5 | 3070 | for_each_pipe(pipe) { |
2c8ba29f | 3071 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3072 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3073 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3074 | |
3075 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3076 | blc_event = true; | |
3077 | } | |
3078 | ||
3079 | ||
3080 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3081 | intel_opregion_asle_intr(dev); | |
3082 | ||
515ac2bb DV |
3083 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3084 | gmbus_irq_handler(dev); | |
3085 | ||
a266c7d5 CW |
3086 | /* With MSI, interrupts are only generated when iir |
3087 | * transitions from zero to nonzero. If another bit got | |
3088 | * set while we were handling the existing iir bits, then | |
3089 | * we would never get another interrupt. | |
3090 | * | |
3091 | * This is fine on non-MSI as well, as if we hit this path | |
3092 | * we avoid exiting the interrupt handler only to generate | |
3093 | * another one. | |
3094 | * | |
3095 | * Note that for MSI this could cause a stray interrupt report | |
3096 | * if an interrupt landed in the time between writing IIR and | |
3097 | * the posting read. This should be rare enough to never | |
3098 | * trigger the 99% of 100,000 interrupts test for disabling | |
3099 | * stray interrupts. | |
3100 | */ | |
3101 | iir = new_iir; | |
3102 | } | |
3103 | ||
d05c617e | 3104 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3105 | |
a266c7d5 CW |
3106 | return ret; |
3107 | } | |
3108 | ||
3109 | static void i965_irq_uninstall(struct drm_device * dev) | |
3110 | { | |
3111 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3112 | int pipe; | |
3113 | ||
3114 | if (!dev_priv) | |
3115 | return; | |
3116 | ||
ac4c16c5 EE |
3117 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3118 | ||
adca4730 CW |
3119 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3120 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3121 | |
3122 | I915_WRITE(HWSTAM, 0xffffffff); | |
3123 | for_each_pipe(pipe) | |
3124 | I915_WRITE(PIPESTAT(pipe), 0); | |
3125 | I915_WRITE(IMR, 0xffffffff); | |
3126 | I915_WRITE(IER, 0x0); | |
3127 | ||
3128 | for_each_pipe(pipe) | |
3129 | I915_WRITE(PIPESTAT(pipe), | |
3130 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3131 | I915_WRITE(IIR, I915_READ(IIR)); | |
3132 | } | |
3133 | ||
ac4c16c5 EE |
3134 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
3135 | { | |
3136 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3137 | struct drm_device *dev = dev_priv->dev; | |
3138 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3139 | unsigned long irqflags; | |
3140 | int i; | |
3141 | ||
3142 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3143 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3144 | struct drm_connector *connector; | |
3145 | ||
3146 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3147 | continue; | |
3148 | ||
3149 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3150 | ||
3151 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3152 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3153 | ||
3154 | if (intel_connector->encoder->hpd_pin == i) { | |
3155 | if (connector->polled != intel_connector->polled) | |
3156 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3157 | drm_get_connector_name(connector)); | |
3158 | connector->polled = intel_connector->polled; | |
3159 | if (!connector->polled) | |
3160 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3161 | } | |
3162 | } | |
3163 | } | |
3164 | if (dev_priv->display.hpd_irq_setup) | |
3165 | dev_priv->display.hpd_irq_setup(dev); | |
3166 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3167 | } | |
3168 | ||
f71d4af4 JB |
3169 | void intel_irq_init(struct drm_device *dev) |
3170 | { | |
8b2e326d CW |
3171 | struct drm_i915_private *dev_priv = dev->dev_private; |
3172 | ||
3173 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3174 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3175 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3176 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3177 | |
99584db3 DV |
3178 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3179 | i915_hangcheck_elapsed, | |
61bac78e | 3180 | (unsigned long) dev); |
ac4c16c5 EE |
3181 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
3182 | (unsigned long) dev_priv); | |
61bac78e | 3183 | |
97a19a24 | 3184 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3185 | |
7d4e146f | 3186 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
f71d4af4 JB |
3187 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3188 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3189 | } else { |
3190 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3191 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3192 | } |
3193 | ||
c2baf4b7 | 3194 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 3195 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
3196 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3197 | } | |
f71d4af4 | 3198 | |
7e231dbe JB |
3199 | if (IS_VALLEYVIEW(dev)) { |
3200 | dev->driver->irq_handler = valleyview_irq_handler; | |
3201 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3202 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3203 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3204 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3205 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3206 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
f71d4af4 JB |
3207 | } else if (HAS_PCH_SPLIT(dev)) { |
3208 | dev->driver->irq_handler = ironlake_irq_handler; | |
3209 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3210 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3211 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3212 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3213 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3214 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3215 | } else { |
c2798b19 CW |
3216 | if (INTEL_INFO(dev)->gen == 2) { |
3217 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3218 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3219 | dev->driver->irq_handler = i8xx_irq_handler; | |
3220 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3221 | } else if (INTEL_INFO(dev)->gen == 3) { |
3222 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3223 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3224 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3225 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3226 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3227 | } else { |
a266c7d5 CW |
3228 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3229 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3230 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3231 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3232 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3233 | } |
f71d4af4 JB |
3234 | dev->driver->enable_vblank = i915_enable_vblank; |
3235 | dev->driver->disable_vblank = i915_disable_vblank; | |
3236 | } | |
3237 | } | |
20afbda2 DV |
3238 | |
3239 | void intel_hpd_init(struct drm_device *dev) | |
3240 | { | |
3241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3242 | struct drm_mode_config *mode_config = &dev->mode_config; |
3243 | struct drm_connector *connector; | |
b5ea2d56 | 3244 | unsigned long irqflags; |
821450c6 | 3245 | int i; |
20afbda2 | 3246 | |
821450c6 EE |
3247 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3248 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3249 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3250 | } | |
3251 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3252 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3253 | connector->polled = intel_connector->polled; | |
3254 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3255 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3256 | } | |
b5ea2d56 DV |
3257 | |
3258 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3259 | * just to make the assert_spin_locked checks happy. */ | |
3260 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
3261 | if (dev_priv->display.hpd_irq_setup) |
3262 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 3263 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 3264 | } |
c67a470b PZ |
3265 | |
3266 | /* Disable interrupts so we can allow Package C8+. */ | |
3267 | void hsw_pc8_disable_interrupts(struct drm_device *dev) | |
3268 | { | |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3270 | unsigned long irqflags; | |
3271 | ||
3272 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3273 | ||
3274 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); | |
3275 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); | |
3276 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); | |
3277 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); | |
3278 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
3279 | ||
3280 | ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB); | |
3281 | ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT); | |
3282 | ilk_disable_gt_irq(dev_priv, 0xffffffff); | |
3283 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
3284 | ||
3285 | dev_priv->pc8.irqs_disabled = true; | |
3286 | ||
3287 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3288 | } | |
3289 | ||
3290 | /* Restore interrupts so we can recover from Package C8+. */ | |
3291 | void hsw_pc8_restore_interrupts(struct drm_device *dev) | |
3292 | { | |
3293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3294 | unsigned long irqflags; | |
3295 | uint32_t val, expected; | |
3296 | ||
3297 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3298 | ||
3299 | val = I915_READ(DEIMR); | |
3300 | expected = ~DE_PCH_EVENT_IVB; | |
3301 | WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected); | |
3302 | ||
3303 | val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT; | |
3304 | expected = ~SDE_HOTPLUG_MASK_CPT; | |
3305 | WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n", | |
3306 | val, expected); | |
3307 | ||
3308 | val = I915_READ(GTIMR); | |
3309 | expected = 0xffffffff; | |
3310 | WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected); | |
3311 | ||
3312 | val = I915_READ(GEN6_PMIMR); | |
3313 | expected = 0xffffffff; | |
3314 | WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val, | |
3315 | expected); | |
3316 | ||
3317 | dev_priv->pc8.irqs_disabled = false; | |
3318 | ||
3319 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); | |
3320 | ibx_enable_display_interrupt(dev_priv, | |
3321 | ~dev_priv->pc8.regsave.sdeimr & | |
3322 | ~SDE_HOTPLUG_MASK_CPT); | |
3323 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); | |
3324 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); | |
3325 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); | |
3326 | ||
3327 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3328 | } |