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drm/i915: wrap GTIMR changes
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
43eaea13
PZ		 107/**
108 * ilk_update_gt_irq - update GTIMR
109 * @dev_priv: driver private
110 * @interrupt_mask: mask of interrupt bits to update
111 * @enabled_irq_mask: mask of interrupt bits to enable
112 */
113static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
114 uint32_t interrupt_mask,
115 uint32_t enabled_irq_mask)
116{
117 assert_spin_locked(&dev_priv->irq_lock);
118
119 dev_priv->gt_irq_mask &= ~interrupt_mask;
120 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
121 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
122 POSTING_READ(GTIMR);
123}
124
125void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
126{
127 ilk_update_gt_irq(dev_priv, mask, mask);
128}
129
130void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
131{
132 ilk_update_gt_irq(dev_priv, mask, 0);
133}
134
8664281b
PZ		 135static bool ivb_can_enable_err_int(struct drm_device *dev)
136{
137 struct drm_i915_private *dev_priv = dev->dev_private;
138 struct intel_crtc *crtc;
139 enum pipe pipe;
140
4bc9d430
DV		 141 assert_spin_locked(&dev_priv->irq_lock);
142
8664281b
PZ		 143 for_each_pipe(pipe) {
144 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
145
146 if (crtc->cpu_fifo_underrun_disabled)
147 return false;
148 }
149
150 return true;
151}
152
153static bool cpt_can_enable_serr_int(struct drm_device *dev)
154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 enum pipe pipe;
157 struct intel_crtc *crtc;
158
fee884ed
DV		 159 assert_spin_locked(&dev_priv->irq_lock);
160
8664281b
PZ		 161 for_each_pipe(pipe) {
162 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
163
164 if (crtc->pch_fifo_underrun_disabled)
165 return false;
166 }
167
168 return true;
169}
170
171static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
172 enum pipe pipe, bool enable)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
176 DE_PIPEB_FIFO_UNDERRUN;
177
178 if (enable)
179 ironlake_enable_display_irq(dev_priv, bit);
180 else
181 ironlake_disable_display_irq(dev_priv, bit);
182}
183
184static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 185 enum pipe pipe, bool enable)
8664281b
PZ		 186{
187 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 188 if (enable) {
7336df65
DV		 189 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
190
8664281b
PZ		 191 if (!ivb_can_enable_err_int(dev))
192 return;
193
8664281b
PZ		 194 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
195 } else {
7336df65
DV		 196 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
197
198 /* Change the state _after_ we've read out the current one. */
8664281b 199 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 200
201 if (!was_enabled &&
202 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
203 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
204 pipe_name(pipe));
205 }
8664281b
PZ		 206 }
207}
208
fee884ed
DV		 209/**
210 * ibx_display_interrupt_update - update SDEIMR
211 * @dev_priv: driver private
212 * @interrupt_mask: mask of interrupt bits to update
213 * @enabled_irq_mask: mask of interrupt bits to enable
214 */
215static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
216 uint32_t interrupt_mask,
217 uint32_t enabled_irq_mask)
218{
219 uint32_t sdeimr = I915_READ(SDEIMR);
220 sdeimr &= ~interrupt_mask;
221 sdeimr |= (~enabled_irq_mask & interrupt_mask);
222
223 assert_spin_locked(&dev_priv->irq_lock);
224
225 I915_WRITE(SDEIMR, sdeimr);
226 POSTING_READ(SDEIMR);
227}
228#define ibx_enable_display_interrupt(dev_priv, bits) \
229 ibx_display_interrupt_update((dev_priv), (bits), (bits))
230#define ibx_disable_display_interrupt(dev_priv, bits) \
231 ibx_display_interrupt_update((dev_priv), (bits), 0)
232
de28075d
DV		 233static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
234 enum transcoder pch_transcoder,
8664281b
PZ		 235 bool enable)
236{
8664281b 237 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 238 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
239 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 240
241 if (enable)
fee884ed 242 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 243 else
fee884ed 244 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 245}
246
247static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
248 enum transcoder pch_transcoder,
249 bool enable)
250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
252
253 if (enable) {
1dd246fb
DV		 254 I915_WRITE(SERR_INT,
255 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
256
8664281b
PZ		 257 if (!cpt_can_enable_serr_int(dev))
258 return;
259
fee884ed 260 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 261 } else {
1dd246fb
DV		 262 uint32_t tmp = I915_READ(SERR_INT);
263 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
264
265 /* Change the state _after_ we've read out the current one. */
fee884ed 266 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 267
268 if (!was_enabled &&
269 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
270 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
271 transcoder_name(pch_transcoder));
272 }
8664281b 273 }
8664281b
PZ		 274}
275
276/**
277 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
278 * @dev: drm device
279 * @pipe: pipe
280 * @enable: true if we want to report FIFO underrun errors, false otherwise
281 *
282 * This function makes us disable or enable CPU fifo underruns for a specific
283 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
284 * reporting for one pipe may also disable all the other CPU error interruts for
285 * the other pipes, due to the fact that there's just one interrupt mask/enable
286 * bit for all the pipes.
287 *
288 * Returns the previous state of underrun reporting.
289 */
290bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
291 enum pipe pipe, bool enable)
292{
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
296 unsigned long flags;
297 bool ret;
298
299 spin_lock_irqsave(&dev_priv->irq_lock, flags);
300
301 ret = !intel_crtc->cpu_fifo_underrun_disabled;
302
303 if (enable == ret)
304 goto done;
305
306 intel_crtc->cpu_fifo_underrun_disabled = !enable;
307
308 if (IS_GEN5(dev) || IS_GEN6(dev))
309 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
310 else if (IS_GEN7(dev))
7336df65 311 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 312
313done:
314 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
315 return ret;
316}
317
318/**
319 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
320 * @dev: drm device
321 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
322 * @enable: true if we want to report FIFO underrun errors, false otherwise
323 *
324 * This function makes us disable or enable PCH fifo underruns for a specific
325 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
326 * underrun reporting for one transcoder may also disable all the other PCH
327 * error interruts for the other transcoders, due to the fact that there's just
328 * one interrupt mask/enable bit for all the transcoders.
329 *
330 * Returns the previous state of underrun reporting.
331 */
332bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
333 enum transcoder pch_transcoder,
334 bool enable)
335{
336 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 337 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 339 unsigned long flags;
340 bool ret;
341
de28075d
DV		 342 /*
343 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
344 * has only one pch transcoder A that all pipes can use. To avoid racy
345 * pch transcoder -> pipe lookups from interrupt code simply store the
346 * underrun statistics in crtc A. Since we never expose this anywhere
347 * nor use it outside of the fifo underrun code here using the "wrong"
348 * crtc on LPT won't cause issues.
349 */
8664281b
PZ		 350
351 spin_lock_irqsave(&dev_priv->irq_lock, flags);
352
353 ret = !intel_crtc->pch_fifo_underrun_disabled;
354
355 if (enable == ret)
356 goto done;
357
358 intel_crtc->pch_fifo_underrun_disabled = !enable;
359
360 if (HAS_PCH_IBX(dev))
de28075d 361 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 362 else
363 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
364
365done:
366 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
367 return ret;
368}
369
370
7c463586
KP		 371void
372i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
373{
46c06a30
VS		 374 u32 reg = PIPESTAT(pipe);
375 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 376
b79480ba
DV		 377 assert_spin_locked(&dev_priv->irq_lock);
378
46c06a30
VS		 379 if ((pipestat & mask) == mask)
380 return;
381
382 /* Enable the interrupt, clear any pending status */
383 pipestat |= mask | (mask >> 16);
384 I915_WRITE(reg, pipestat);
385 POSTING_READ(reg);
7c463586
KP		 386}
387
388void
389i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
390{
46c06a30
VS		 391 u32 reg = PIPESTAT(pipe);
392 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 393
b79480ba
DV		 394 assert_spin_locked(&dev_priv->irq_lock);
395
46c06a30
VS		 396 if ((pipestat & mask) == 0)
397 return;
398
399 pipestat &= ~mask;
400 I915_WRITE(reg, pipestat);
401 POSTING_READ(reg);
7c463586
KP		 402}
403
01c66889 404/**
f49e38dd 405 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 406 */
f49e38dd 407static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 408{
1ec14ad3
CW		 409 drm_i915_private_t *dev_priv = dev->dev_private;
410 unsigned long irqflags;
411
f49e38dd
JN		 412 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
413 return;
414
1ec14ad3 415 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 416
f898780b
JN		 417 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
418 if (INTEL_INFO(dev)->gen >= 4)
419 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 420
421 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 422}
423
0a3e67a4
JB		 424/**
425 * i915_pipe_enabled - check if a pipe is enabled
426 * @dev: DRM device
427 * @pipe: pipe to check
428 *
429 * Reading certain registers when the pipe is disabled can hang the chip.
430 * Use this routine to make sure the PLL is running and the pipe is active
431 * before reading such registers if unsure.
432 */
433static int
434i915_pipe_enabled(struct drm_device *dev, int pipe)
435{
436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 437
a01025af
DV		 438 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
439 /* Locking is horribly broken here, but whatever. */
440 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 442
a01025af
DV		 443 return intel_crtc->active;
444 } else {
445 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
446 }
0a3e67a4
JB		 447}
448
42f52ef8
KP		 449/* Called from drm generic code, passed a 'crtc', which
450 * we use as a pipe index
451 */
f71d4af4 452static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 453{
454 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
455 unsigned long high_frame;
456 unsigned long low_frame;
5eddb70b 457 u32 high1, high2, low;
0a3e67a4
JB		 458
459 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 460 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 461 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 462 return 0;
463 }
464
9db4a9c7
JB		 465 high_frame = PIPEFRAME(pipe);
466 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 467
0a3e67a4
JB		 468 /*
469 * High & low register fields aren't synchronized, so make sure
470 * we get a low value that's stable across two reads of the high
471 * register.
472 */
473 do {
5eddb70b
CW		 474 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
475 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
476 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 477 } while (high1 != high2);
478
5eddb70b
CW		 479 high1 >>= PIPE_FRAME_HIGH_SHIFT;
480 low >>= PIPE_FRAME_LOW_SHIFT;
481 return (high1 << 8) | low;
0a3e67a4
JB		 482}
483
f71d4af4 484static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 485{
486 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 487 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 488
489 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 490 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 491 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 492 return 0;
493 }
494
495 return I915_READ(reg);
496}
497
f71d4af4 498static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 499 int *vpos, int *hpos)
500{
501 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
502 u32 vbl = 0, position = 0;
503 int vbl_start, vbl_end, htotal, vtotal;
504 bool in_vbl = true;
505 int ret = 0;
fe2b8f9d
PZ		 506 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
507 pipe);
0af7e4df
MK		 508
509 if (!i915_pipe_enabled(dev, pipe)) {
510 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 511 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 512 return 0;
513 }
514
515 /* Get vtotal. */
fe2b8f9d 516 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 517
518 if (INTEL_INFO(dev)->gen >= 4) {
519 /* No obvious pixelcount register. Only query vertical
520 * scanout position from Display scan line register.
521 */
522 position = I915_READ(PIPEDSL(pipe));
523
524 /* Decode into vertical scanout position. Don't have
525 * horizontal scanout position.
526 */
527 *vpos = position & 0x1fff;
528 *hpos = 0;
529 } else {
530 /* Have access to pixelcount since start of frame.
531 * We can split this into vertical and horizontal
532 * scanout position.
533 */
534 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
535
fe2b8f9d 536 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 537 *vpos = position / htotal;
538 *hpos = position - (*vpos * htotal);
539 }
540
541 /* Query vblank area. */
fe2b8f9d 542 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 543
544 /* Test position against vblank region. */
545 vbl_start = vbl & 0x1fff;
546 vbl_end = (vbl >> 16) & 0x1fff;
547
548 if ((*vpos < vbl_start) || (*vpos > vbl_end))
549 in_vbl = false;
550
551 /* Inside "upper part" of vblank area? Apply corrective offset: */
552 if (in_vbl && (*vpos >= vbl_start))
553 *vpos = *vpos - vtotal;
554
555 /* Readouts valid? */
556 if (vbl > 0)
557 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
558
559 /* In vblank? */
560 if (in_vbl)
561 ret |= DRM_SCANOUTPOS_INVBL;
562
563 return ret;
564}
565
f71d4af4 566static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 567 int *max_error,
568 struct timeval *vblank_time,
569 unsigned flags)
570{
4041b853 571 struct drm_crtc *crtc;
0af7e4df 572
7eb552ae 573 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 574 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 575 return -EINVAL;
576 }
577
578 /* Get drm_crtc to timestamp: */
4041b853
CW		 579 crtc = intel_get_crtc_for_pipe(dev, pipe);
580 if (crtc == NULL) {
581 DRM_ERROR("Invalid crtc %d\n", pipe);
582 return -EINVAL;
583 }
584
585 if (!crtc->enabled) {
586 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
587 return -EBUSY;
588 }
0af7e4df
MK		 589
590 /* Helper routine in DRM core does all the work: */
4041b853
CW		 591 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
592 vblank_time, flags,
593 crtc);
0af7e4df
MK		 594}
595
321a1b30
EE		 596static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
597{
598 enum drm_connector_status old_status;
599
600 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
601 old_status = connector->status;
602
603 connector->status = connector->funcs->detect(connector, false);
604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
605 connector->base.id,
606 drm_get_connector_name(connector),
607 old_status, connector->status);
608 return (old_status != connector->status);
609}
610
5ca58282
JB		 611/*
612 * Handle hotplug events outside the interrupt handler proper.
613 */
ac4c16c5
EE		 614#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
615
5ca58282
JB		 616static void i915_hotplug_work_func(struct work_struct *work)
617{
618 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
619 hotplug_work);
620 struct drm_device *dev = dev_priv->dev;
c31c4ba3 621 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 622 struct intel_connector *intel_connector;
623 struct intel_encoder *intel_encoder;
624 struct drm_connector *connector;
625 unsigned long irqflags;
626 bool hpd_disabled = false;
321a1b30 627 bool changed = false;
142e2398 628 u32 hpd_event_bits;
4ef69c7a 629
52d7eced
DV		 630 /* HPD irq before everything is fully set up. */
631 if (!dev_priv->enable_hotplug_processing)
632 return;
633
a65e34c7 634 mutex_lock(&mode_config->mutex);
e67189ab
JB		 635 DRM_DEBUG_KMS("running encoder hotplug functions\n");
636
cd569aed 637 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 638
639 hpd_event_bits = dev_priv->hpd_event_bits;
640 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 641 list_for_each_entry(connector, &mode_config->connector_list, head) {
642 intel_connector = to_intel_connector(connector);
643 intel_encoder = intel_connector->encoder;
644 if (intel_encoder->hpd_pin > HPD_NONE &&
645 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
646 connector->polled == DRM_CONNECTOR_POLL_HPD) {
647 DRM_INFO("HPD interrupt storm detected on connector %s: "
648 "switching from hotplug detection to polling\n",
649 drm_get_connector_name(connector));
650 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
651 connector->polled = DRM_CONNECTOR_POLL_CONNECT
652 | DRM_CONNECTOR_POLL_DISCONNECT;
653 hpd_disabled = true;
654 }
142e2398
EE		 655 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
656 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
657 drm_get_connector_name(connector), intel_encoder->hpd_pin);
658 }
cd569aed
EE		 659 }
660 /* if there were no outputs to poll, poll was disabled,
661 * therefore make sure it's enabled when disabling HPD on
662 * some connectors */
ac4c16c5 663 if (hpd_disabled) {
cd569aed 664 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 665 mod_timer(&dev_priv->hotplug_reenable_timer,
666 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
667 }
cd569aed
EE		 668
669 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
670
321a1b30
EE		 671 list_for_each_entry(connector, &mode_config->connector_list, head) {
672 intel_connector = to_intel_connector(connector);
673 intel_encoder = intel_connector->encoder;
674 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
675 if (intel_encoder->hot_plug)
676 intel_encoder->hot_plug(intel_encoder);
677 if (intel_hpd_irq_event(dev, connector))
678 changed = true;
679 }
680 }
40ee3381
KP		 681 mutex_unlock(&mode_config->mutex);
682
321a1b30
EE		 683 if (changed)
684 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 685}
686
d0ecd7e2 687static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 688{
689 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 690 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 691 u8 new_delay;
9270388e 692
d0ecd7e2 693 spin_lock(&mchdev_lock);
f97108d1 694
73edd18f
DV		 695 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
696
20e4d407 697 new_delay = dev_priv->ips.cur_delay;
9270388e 698
7648fa99 699 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 700 busy_up = I915_READ(RCPREVBSYTUPAVG);
701 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 702 max_avg = I915_READ(RCBMAXAVG);
703 min_avg = I915_READ(RCBMINAVG);
704
705 /* Handle RCS change request from hw */
b5b72e89 706 if (busy_up > max_avg) {
20e4d407
DV		 707 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
708 new_delay = dev_priv->ips.cur_delay - 1;
709 if (new_delay < dev_priv->ips.max_delay)
710 new_delay = dev_priv->ips.max_delay;
b5b72e89 711 } else if (busy_down < min_avg) {
20e4d407
DV		 712 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
713 new_delay = dev_priv->ips.cur_delay + 1;
714 if (new_delay > dev_priv->ips.min_delay)
715 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 716 }
717
7648fa99 718 if (ironlake_set_drps(dev, new_delay))
20e4d407 719 dev_priv->ips.cur_delay = new_delay;
f97108d1 720
d0ecd7e2 721 spin_unlock(&mchdev_lock);
9270388e 722
f97108d1
JB		 723 return;
724}
725
549f7365
CW		 726static void notify_ring(struct drm_device *dev,
727 struct intel_ring_buffer *ring)
728{
475553de
CW		 729 if (ring->obj == NULL)
730 return;
731
b2eadbc8 732 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 733
549f7365 734 wake_up_all(&ring->irq_queue);
10cd45b6 735 i915_queue_hangcheck(dev);
549f7365
CW		 736}
737
4912d041 738static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 739{
4912d041 740 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 741 rps.work);
4912d041 742 u32 pm_iir, pm_imr;
7b9e0ae6 743 u8 new_delay;
4912d041 744
59cdb63d 745 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 746 pm_iir = dev_priv->rps.pm_iir;
747 dev_priv->rps.pm_iir = 0;
4912d041 748 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 749 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
750 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
59cdb63d 751 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 752
4848405c 753 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 754 return;
755
4fc688ce 756 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 757
7425034a 758 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 759 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 760
761 /*
762 * For better performance, jump directly
763 * to RPe if we're below it.
764 */
765 if (IS_VALLEYVIEW(dev_priv->dev) &&
766 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
767 new_delay = dev_priv->rps.rpe_delay;
768 } else
c6a828d3 769 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 770
79249636
BW		 771 /* sysfs frequency interfaces may have snuck in while servicing the
772 * interrupt
773 */
d8289c9e
VS		 774 if (new_delay >= dev_priv->rps.min_delay &&
775 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 776 if (IS_VALLEYVIEW(dev_priv->dev))
777 valleyview_set_rps(dev_priv->dev, new_delay);
778 else
779 gen6_set_rps(dev_priv->dev, new_delay);
79249636 780 }
3b8d8d91 781
52ceb908
JB		 782 if (IS_VALLEYVIEW(dev_priv->dev)) {
783 /*
784 * On VLV, when we enter RC6 we may not be at the minimum
785 * voltage level, so arm a timer to check. It should only
786 * fire when there's activity or once after we've entered
787 * RC6, and then won't be re-armed until the next RPS interrupt.
788 */
789 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
790 msecs_to_jiffies(100));
791 }
792
4fc688ce 793 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 794}
795
e3689190
BW		 796
797/**
798 * ivybridge_parity_work - Workqueue called when a parity error interrupt
799 * occurred.
800 * @work: workqueue struct
801 *
802 * Doesn't actually do anything except notify userspace. As a consequence of
803 * this event, userspace should try to remap the bad rows since statistically
804 * it is likely the same row is more likely to go bad again.
805 */
806static void ivybridge_parity_work(struct work_struct *work)
807{
808 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 809 l3_parity.error_work);
e3689190
BW		 810 u32 error_status, row, bank, subbank;
811 char *parity_event[5];
812 uint32_t misccpctl;
813 unsigned long flags;
814
815 /* We must turn off DOP level clock gating to access the L3 registers.
816 * In order to prevent a get/put style interface, acquire struct mutex
817 * any time we access those registers.
818 */
819 mutex_lock(&dev_priv->dev->struct_mutex);
820
821 misccpctl = I915_READ(GEN7_MISCCPCTL);
822 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
823 POSTING_READ(GEN7_MISCCPCTL);
824
825 error_status = I915_READ(GEN7_L3CDERRST1);
826 row = GEN7_PARITY_ERROR_ROW(error_status);
827 bank = GEN7_PARITY_ERROR_BANK(error_status);
828 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
829
830 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
831 GEN7_L3CDERRST1_ENABLE);
832 POSTING_READ(GEN7_L3CDERRST1);
833
834 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
835
836 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 837 ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
e3689190
BW		 838 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
839
840 mutex_unlock(&dev_priv->dev->struct_mutex);
841
cce723ed 842 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
e3689190
BW		 843 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
844 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
845 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
846 parity_event[4] = NULL;
847
848 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
849 KOBJ_CHANGE, parity_event);
850
851 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
852 row, bank, subbank);
853
854 kfree(parity_event[3]);
855 kfree(parity_event[2]);
856 kfree(parity_event[1]);
857}
858
d0ecd7e2 859static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
e3689190
BW		 860{
861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 862
e1ef7cc2 863 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 864 return;
865
d0ecd7e2 866 spin_lock(&dev_priv->irq_lock);
43eaea13 867 ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
d0ecd7e2 868 spin_unlock(&dev_priv->irq_lock);
e3689190 869
a4da4fa4 870 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 871}
872
f1af8fc1
PZ		 873static void ilk_gt_irq_handler(struct drm_device *dev,
874 struct drm_i915_private *dev_priv,
875 u32 gt_iir)
876{
877 if (gt_iir &
878 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
879 notify_ring(dev, &dev_priv->ring[RCS]);
880 if (gt_iir & ILK_BSD_USER_INTERRUPT)
881 notify_ring(dev, &dev_priv->ring[VCS]);
882}
883
e7b4c6b1
DV		 884static void snb_gt_irq_handler(struct drm_device *dev,
885 struct drm_i915_private *dev_priv,
886 u32 gt_iir)
887{
888
cc609d5d
BW		 889 if (gt_iir &
890 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 891 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 892 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 893 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 894 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 895 notify_ring(dev, &dev_priv->ring[BCS]);
896
cc609d5d
BW		 897 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
898 GT_BSD_CS_ERROR_INTERRUPT |
899 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 900 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
901 i915_handle_error(dev, false);
902 }
e3689190 903
cc609d5d 904 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
d0ecd7e2 905 ivybridge_parity_error_irq_handler(dev);
e7b4c6b1
DV		 906}
907
baf02a1f 908/* Legacy way of handling PM interrupts */
d0ecd7e2
DV		 909static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
910 u32 pm_iir)
fc6826d1 911{
fc6826d1
CW		 912 /*
913 * IIR bits should never already be set because IMR should
914 * prevent an interrupt from being shown in IIR. The warning
915 * displays a case where we've unsafely cleared
c6a828d3 916 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 917 * type is not a problem, it displays a problem in the logic.
918 *
c6a828d3 919 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 920 */
921
59cdb63d 922 spin_lock(&dev_priv->irq_lock);
c6a828d3
DV		 923 dev_priv->rps.pm_iir |= pm_iir;
924 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 925 POSTING_READ(GEN6_PMIMR);
59cdb63d 926 spin_unlock(&dev_priv->irq_lock);
fc6826d1 927
c6a828d3 928 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 929}
930
b543fb04
EE		 931#define HPD_STORM_DETECT_PERIOD 1000
932#define HPD_STORM_THRESHOLD 5
933
10a504de 934static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 935 u32 hotplug_trigger,
936 const u32 *hpd)
b543fb04
EE		 937{
938 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 939 int i;
10a504de 940 bool storm_detected = false;
b543fb04 941
91d131d2
DV		 942 if (!hotplug_trigger)
943 return;
944
b5ea2d56 945 spin_lock(&dev_priv->irq_lock);
b543fb04 946 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 947
b8f102e8
EE		 948 WARN(((hpd[i] & hotplug_trigger) &&
949 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
950 "Received HPD interrupt although disabled\n");
951
b543fb04
EE		 952 if (!(hpd[i] & hotplug_trigger) ||
953 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
954 continue;
955
bc5ead8c 956 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 957 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
958 dev_priv->hpd_stats[i].hpd_last_jiffies
959 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
960 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
961 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 962 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 963 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
964 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 965 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 966 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 967 storm_detected = true;
b543fb04
EE		 968 } else {
969 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 970 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
971 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 972 }
973 }
974
10a504de
DV		 975 if (storm_detected)
976 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 977 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 978
979 queue_work(dev_priv->wq,
980 &dev_priv->hotplug_work);
b543fb04
EE		 981}
982
515ac2bb
DV		 983static void gmbus_irq_handler(struct drm_device *dev)
984{
28c70f16
DV		 985 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
986
28c70f16 987 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 988}
989
ce99c256
DV		 990static void dp_aux_irq_handler(struct drm_device *dev)
991{
9ee32fea
DV		 992 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
993
9ee32fea 994 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 995}
996
d0ecd7e2 997/* Unlike gen6_rps_irq_handler() from which this function is originally derived,
baf02a1f
BW		 998 * we must be able to deal with other PM interrupts. This is complicated because
999 * of the way in which we use the masks to defer the RPS work (which for
1000 * posterity is necessary because of forcewake).
1001 */
1002static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
1003 u32 pm_iir)
1004{
41a05a3a 1005 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1006 spin_lock(&dev_priv->irq_lock);
41a05a3a 1007 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 1008 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
1009 /* never want to mask useful interrupts. (also posting read) */
4848405c 1010 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
59cdb63d 1011 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1012
1013 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1014 }
baf02a1f 1015
41a05a3a
DV		 1016 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1017 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1018
41a05a3a
DV		 1019 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1020 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1021 i915_handle_error(dev_priv->dev, false);
12638c57 1022 }
baf02a1f
BW		 1023}
1024
ff1f525e 1025static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1026{
1027 struct drm_device *dev = (struct drm_device *) arg;
1028 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1029 u32 iir, gt_iir, pm_iir;
1030 irqreturn_t ret = IRQ_NONE;
1031 unsigned long irqflags;
1032 int pipe;
1033 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1034
1035 atomic_inc(&dev_priv->irq_received);
1036
7e231dbe
JB		 1037 while (true) {
1038 iir = I915_READ(VLV_IIR);
1039 gt_iir = I915_READ(GTIIR);
1040 pm_iir = I915_READ(GEN6_PMIIR);
1041
1042 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1043 goto out;
1044
1045 ret = IRQ_HANDLED;
1046
e7b4c6b1 1047 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1048
1049 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1050 for_each_pipe(pipe) {
1051 int reg = PIPESTAT(pipe);
1052 pipe_stats[pipe] = I915_READ(reg);
1053
1054 /*
1055 * Clear the PIPE*STAT regs before the IIR
1056 */
1057 if (pipe_stats[pipe] & 0x8000ffff) {
1058 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1059 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1060 pipe_name(pipe));
1061 I915_WRITE(reg, pipe_stats[pipe]);
1062 }
1063 }
1064 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1065
31acc7f5
JB		 1066 for_each_pipe(pipe) {
1067 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1068 drm_handle_vblank(dev, pipe);
1069
1070 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1071 intel_prepare_page_flip(dev, pipe);
1072 intel_finish_page_flip(dev, pipe);
1073 }
1074 }
1075
7e231dbe
JB		 1076 /* Consume port. Then clear IIR or we'll miss events */
1077 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1078 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1079 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1080
1081 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1082 hotplug_status);
91d131d2
DV		 1083
1084 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1085
7e231dbe
JB		 1086 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1087 I915_READ(PORT_HOTPLUG_STAT);
1088 }
1089
515ac2bb
DV		 1090 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1091 gmbus_irq_handler(dev);
7e231dbe 1092
4848405c 1093 if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1094 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1095
1096 I915_WRITE(GTIIR, gt_iir);
1097 I915_WRITE(GEN6_PMIIR, pm_iir);
1098 I915_WRITE(VLV_IIR, iir);
1099 }
1100
1101out:
1102 return ret;
1103}
1104
23e81d69 1105static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1106{
1107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1108 int pipe;
b543fb04 1109 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1110
91d131d2
DV		 1111 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1112
cfc33bf7
VS		 1113 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1114 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1115 SDE_AUDIO_POWER_SHIFT);
776ad806 1116 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1117 port_name(port));
1118 }
776ad806 1119
ce99c256
DV		 1120 if (pch_iir & SDE_AUX_MASK)
1121 dp_aux_irq_handler(dev);
1122
776ad806 1123 if (pch_iir & SDE_GMBUS)
515ac2bb 1124 gmbus_irq_handler(dev);
776ad806
JB		 1125
1126 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1127 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1128
1129 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1130 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1131
1132 if (pch_iir & SDE_POISON)
1133 DRM_ERROR("PCH poison interrupt\n");
1134
9db4a9c7
JB		 1135 if (pch_iir & SDE_FDI_MASK)
1136 for_each_pipe(pipe)
1137 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1138 pipe_name(pipe),
1139 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1140
1141 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1142 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1143
1144 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1145 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1146
776ad806 1147 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1148 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1149 false))
1150 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1151
1152 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1153 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1154 false))
1155 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1156}
1157
1158static void ivb_err_int_handler(struct drm_device *dev)
1159{
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1161 u32 err_int = I915_READ(GEN7_ERR_INT);
1162
de032bf4
PZ		 1163 if (err_int & ERR_INT_POISON)
1164 DRM_ERROR("Poison interrupt\n");
1165
8664281b
PZ		 1166 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1167 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1168 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1169
1170 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1171 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1172 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1173
1174 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1175 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1176 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1177
1178 I915_WRITE(GEN7_ERR_INT, err_int);
1179}
1180
1181static void cpt_serr_int_handler(struct drm_device *dev)
1182{
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 serr_int = I915_READ(SERR_INT);
1185
de032bf4
PZ		 1186 if (serr_int & SERR_INT_POISON)
1187 DRM_ERROR("PCH poison interrupt\n");
1188
8664281b
PZ		 1189 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1190 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1191 false))
1192 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1193
1194 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1195 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1196 false))
1197 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1198
1199 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1200 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1201 false))
1202 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1203
1204 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1205}
1206
23e81d69
AJ		 1207static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1208{
1209 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1210 int pipe;
b543fb04 1211 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1212
91d131d2
DV		 1213 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1214
cfc33bf7
VS		 1215 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1216 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1217 SDE_AUDIO_POWER_SHIFT_CPT);
1218 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1219 port_name(port));
1220 }
23e81d69
AJ		 1221
1222 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1223 dp_aux_irq_handler(dev);
23e81d69
AJ		 1224
1225 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1226 gmbus_irq_handler(dev);
23e81d69
AJ		 1227
1228 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1229 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1230
1231 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1232 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1233
1234 if (pch_iir & SDE_FDI_MASK_CPT)
1235 for_each_pipe(pipe)
1236 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1237 pipe_name(pipe),
1238 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1239
1240 if (pch_iir & SDE_ERROR_CPT)
1241 cpt_serr_int_handler(dev);
23e81d69
AJ		 1242}
1243
c008bc6e
PZ		 1244static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1245{
1246 struct drm_i915_private *dev_priv = dev->dev_private;
1247
1248 if (de_iir & DE_AUX_CHANNEL_A)
1249 dp_aux_irq_handler(dev);
1250
1251 if (de_iir & DE_GSE)
1252 intel_opregion_asle_intr(dev);
1253
1254 if (de_iir & DE_PIPEA_VBLANK)
1255 drm_handle_vblank(dev, 0);
1256
1257 if (de_iir & DE_PIPEB_VBLANK)
1258 drm_handle_vblank(dev, 1);
1259
1260 if (de_iir & DE_POISON)
1261 DRM_ERROR("Poison interrupt\n");
1262
1263 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1264 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1265 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1266
1267 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1268 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1269 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1270
1271 if (de_iir & DE_PLANEA_FLIP_DONE) {
1272 intel_prepare_page_flip(dev, 0);
1273 intel_finish_page_flip_plane(dev, 0);
1274 }
1275
1276 if (de_iir & DE_PLANEB_FLIP_DONE) {
1277 intel_prepare_page_flip(dev, 1);
1278 intel_finish_page_flip_plane(dev, 1);
1279 }
1280
1281 /* check event from PCH */
1282 if (de_iir & DE_PCH_EVENT) {
1283 u32 pch_iir = I915_READ(SDEIIR);
1284
1285 if (HAS_PCH_CPT(dev))
1286 cpt_irq_handler(dev, pch_iir);
1287 else
1288 ibx_irq_handler(dev, pch_iir);
1289
1290 /* should clear PCH hotplug event before clear CPU irq */
1291 I915_WRITE(SDEIIR, pch_iir);
1292 }
1293
1294 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1295 ironlake_rps_change_irq_handler(dev);
1296}
1297
9719fb98
PZ		 1298static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1299{
1300 struct drm_i915_private *dev_priv = dev->dev_private;
1301 int i;
1302
1303 if (de_iir & DE_ERR_INT_IVB)
1304 ivb_err_int_handler(dev);
1305
1306 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1307 dp_aux_irq_handler(dev);
1308
1309 if (de_iir & DE_GSE_IVB)
1310 intel_opregion_asle_intr(dev);
1311
1312 for (i = 0; i < 3; i++) {
1313 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1314 drm_handle_vblank(dev, i);
1315 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1316 intel_prepare_page_flip(dev, i);
1317 intel_finish_page_flip_plane(dev, i);
1318 }
1319 }
1320
1321 /* check event from PCH */
1322 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1323 u32 pch_iir = I915_READ(SDEIIR);
1324
1325 cpt_irq_handler(dev, pch_iir);
1326
1327 /* clear PCH hotplug event before clear CPU irq */
1328 I915_WRITE(SDEIIR, pch_iir);
1329 }
1330}
1331
f1af8fc1 1332static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1333{
1334 struct drm_device *dev = (struct drm_device *) arg;
1335 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1336 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1337 irqreturn_t ret = IRQ_NONE;
b1f14ad0
JB		 1338
1339 atomic_inc(&dev_priv->irq_received);
1340
8664281b
PZ		 1341 /* We get interrupts on unclaimed registers, so check for this before we
1342 * do any I915_{READ,WRITE}. */
907b28c5 1343 intel_uncore_check_errors(dev);
8664281b 1344
b1f14ad0
JB		 1345 /* disable master interrupt before clearing iir */
1346 de_ier = I915_READ(DEIER);
1347 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1348 POSTING_READ(DEIER);
b1f14ad0 1349
44498aea
PZ		 1350 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1351 * interrupts will will be stored on its back queue, and then we'll be
1352 * able to process them after we restore SDEIER (as soon as we restore
1353 * it, we'll get an interrupt if SDEIIR still has something to process
1354 * due to its back queue). */
ab5c608b
BW		 1355 if (!HAS_PCH_NOP(dev)) {
1356 sde_ier = I915_READ(SDEIER);
1357 I915_WRITE(SDEIER, 0);
1358 POSTING_READ(SDEIER);
1359 }
44498aea 1360
8664281b
PZ		 1361 /* On Haswell, also mask ERR_INT because we don't want to risk
1362 * generating "unclaimed register" interrupts from inside the interrupt
1363 * handler. */
4bc9d430
DV		 1364 if (IS_HASWELL(dev)) {
1365 spin_lock(&dev_priv->irq_lock);
8664281b 1366 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1367 spin_unlock(&dev_priv->irq_lock);
1368 }
8664281b 1369
b1f14ad0 1370 gt_iir = I915_READ(GTIIR);
0e43406b 1371 if (gt_iir) {
d8fc8a47 1372 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1373 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1374 else
1375 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1376 I915_WRITE(GTIIR, gt_iir);
1377 ret = IRQ_HANDLED;
b1f14ad0
JB		 1378 }
1379
0e43406b
CW		 1380 de_iir = I915_READ(DEIIR);
1381 if (de_iir) {
f1af8fc1
PZ		 1382 if (INTEL_INFO(dev)->gen >= 7)
1383 ivb_display_irq_handler(dev, de_iir);
1384 else
1385 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1386 I915_WRITE(DEIIR, de_iir);
1387 ret = IRQ_HANDLED;
b1f14ad0
JB		 1388 }
1389
f1af8fc1
PZ		 1390 if (INTEL_INFO(dev)->gen >= 6) {
1391 u32 pm_iir = I915_READ(GEN6_PMIIR);
1392 if (pm_iir) {
1393 if (IS_HASWELL(dev))
1394 hsw_pm_irq_handler(dev_priv, pm_iir);
1395 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1396 gen6_rps_irq_handler(dev_priv, pm_iir);
1397 I915_WRITE(GEN6_PMIIR, pm_iir);
1398 ret = IRQ_HANDLED;
1399 }
0e43406b 1400 }
b1f14ad0 1401
4bc9d430
DV		 1402 if (IS_HASWELL(dev)) {
1403 spin_lock(&dev_priv->irq_lock);
1404 if (ivb_can_enable_err_int(dev))
1405 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1406 spin_unlock(&dev_priv->irq_lock);
1407 }
8664281b 1408
b1f14ad0
JB		 1409 I915_WRITE(DEIER, de_ier);
1410 POSTING_READ(DEIER);
ab5c608b
BW		 1411 if (!HAS_PCH_NOP(dev)) {
1412 I915_WRITE(SDEIER, sde_ier);
1413 POSTING_READ(SDEIER);
1414 }
b1f14ad0
JB		 1415
1416 return ret;
1417}
1418
8a905236
JB		 1419/**
1420 * i915_error_work_func - do process context error handling work
1421 * @work: work struct
1422 *
1423 * Fire an error uevent so userspace can see that a hang or error
1424 * was detected.
1425 */
1426static void i915_error_work_func(struct work_struct *work)
1427{
1f83fee0
DV		 1428 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1429 work);
1430 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1431 gpu_error);
8a905236 1432 struct drm_device *dev = dev_priv->dev;
f69061be 1433 struct intel_ring_buffer *ring;
cce723ed
BW		 1434 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1435 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1436 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
f69061be 1437 int i, ret;
8a905236 1438
f316a42c
BG		 1439 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1440
7db0ba24
DV		 1441 /*
1442 * Note that there's only one work item which does gpu resets, so we
1443 * need not worry about concurrent gpu resets potentially incrementing
1444 * error->reset_counter twice. We only need to take care of another
1445 * racing irq/hangcheck declaring the gpu dead for a second time. A
1446 * quick check for that is good enough: schedule_work ensures the
1447 * correct ordering between hang detection and this work item, and since
1448 * the reset in-progress bit is only ever set by code outside of this
1449 * work we don't need to worry about any other races.
1450 */
1451 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1452 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1453 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1454 reset_event);
1f83fee0 1455
f69061be
DV		 1456 ret = i915_reset(dev);
1457
1458 if (ret == 0) {
1459 /*
1460 * After all the gem state is reset, increment the reset
1461 * counter and wake up everyone waiting for the reset to
1462 * complete.
1463 *
1464 * Since unlock operations are a one-sided barrier only,
1465 * we need to insert a barrier here to order any seqno
1466 * updates before
1467 * the counter increment.
1468 */
1469 smp_mb__before_atomic_inc();
1470 atomic_inc(&dev_priv->gpu_error.reset_counter);
1471
1472 kobject_uevent_env(&dev->primary->kdev.kobj,
1473 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1474 } else {
1475 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1476 }
1f83fee0 1477
f69061be
DV		 1478 for_each_ring(ring, dev_priv, i)
1479 wake_up_all(&ring->irq_queue);
1480
96a02917
VS		 1481 intel_display_handle_reset(dev);
1482
1f83fee0 1483 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1484 }
8a905236
JB		 1485}
1486
35aed2e6 1487static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1490 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1491 u32 eir = I915_READ(EIR);
050ee91f 1492 int pipe, i;
8a905236 1493
35aed2e6
CW		 1494 if (!eir)
1495 return;
8a905236 1496
a70491cc 1497 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1498
bd9854f9
BW		 1499 i915_get_extra_instdone(dev, instdone);
1500
8a905236
JB		 1501 if (IS_G4X(dev)) {
1502 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1503 u32 ipeir = I915_READ(IPEIR_I965);
1504
a70491cc
JP		 1505 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1506 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1507 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1508 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1509 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1510 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1511 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1512 POSTING_READ(IPEIR_I965);
8a905236
JB		 1513 }
1514 if (eir & GM45_ERROR_PAGE_TABLE) {
1515 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1516 pr_err("page table error\n");
1517 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1518 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1519 POSTING_READ(PGTBL_ER);
8a905236
JB		 1520 }
1521 }
1522
a6c45cf0 1523 if (!IS_GEN2(dev)) {
8a905236
JB		 1524 if (eir & I915_ERROR_PAGE_TABLE) {
1525 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1526 pr_err("page table error\n");
1527 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1528 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1529 POSTING_READ(PGTBL_ER);
8a905236
JB		 1530 }
1531 }
1532
1533 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1534 pr_err("memory refresh error:\n");
9db4a9c7 1535 for_each_pipe(pipe)
a70491cc 1536 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1537 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1538 /* pipestat has already been acked */
1539 }
1540 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1541 pr_err("instruction error\n");
1542 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1543 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1544 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1545 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1546 u32 ipeir = I915_READ(IPEIR);
1547
a70491cc
JP		 1548 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1549 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1550 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1551 I915_WRITE(IPEIR, ipeir);
3143a2bf 1552 POSTING_READ(IPEIR);
8a905236
JB		 1553 } else {
1554 u32 ipeir = I915_READ(IPEIR_I965);
1555
a70491cc
JP		 1556 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1557 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1558 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1559 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1560 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1561 POSTING_READ(IPEIR_I965);
8a905236
JB		 1562 }
1563 }
1564
1565 I915_WRITE(EIR, eir);
3143a2bf 1566 POSTING_READ(EIR);
8a905236
JB		 1567 eir = I915_READ(EIR);
1568 if (eir) {
1569 /*
1570 * some errors might have become stuck,
1571 * mask them.
1572 */
1573 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1574 I915_WRITE(EMR, I915_READ(EMR) | eir);
1575 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1576 }
35aed2e6
CW		 1577}
1578
1579/**
1580 * i915_handle_error - handle an error interrupt
1581 * @dev: drm device
1582 *
1583 * Do some basic checking of regsiter state at error interrupt time and
1584 * dump it to the syslog. Also call i915_capture_error_state() to make
1585 * sure we get a record and make it available in debugfs. Fire a uevent
1586 * so userspace knows something bad happened (should trigger collection
1587 * of a ring dump etc.).
1588 */
527f9e90 1589void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1590{
1591 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1592 struct intel_ring_buffer *ring;
1593 int i;
35aed2e6
CW		 1594
1595 i915_capture_error_state(dev);
1596 i915_report_and_clear_eir(dev);
8a905236 1597
ba1234d1 1598 if (wedged) {
f69061be
DV		 1599 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1600 &dev_priv->gpu_error.reset_counter);
ba1234d1 1601
11ed50ec 1602 /*
1f83fee0
DV		 1603 * Wakeup waiting processes so that the reset work item
1604 * doesn't deadlock trying to grab various locks.
11ed50ec 1605 */
b4519513
CW		 1606 for_each_ring(ring, dev_priv, i)
1607 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1608 }
1609
99584db3 1610 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1611}
1612
21ad8330 1613static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1614{
1615 drm_i915_private_t *dev_priv = dev->dev_private;
1616 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1618 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1619 struct intel_unpin_work *work;
1620 unsigned long flags;
1621 bool stall_detected;
1622
1623 /* Ignore early vblank irqs */
1624 if (intel_crtc == NULL)
1625 return;
1626
1627 spin_lock_irqsave(&dev->event_lock, flags);
1628 work = intel_crtc->unpin_work;
1629
e7d841ca
CW		 1630 if (work == NULL ||
1631 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1632 !work->enable_stall_check) {
4e5359cd
SF		 1633 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1634 spin_unlock_irqrestore(&dev->event_lock, flags);
1635 return;
1636 }
1637
1638 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1639 obj = work->pending_flip_obj;
a6c45cf0 1640 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1641 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1642 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1643 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1644 } else {
9db4a9c7 1645 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1646 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1647 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1648 crtc->x * crtc->fb->bits_per_pixel/8);
1649 }
1650
1651 spin_unlock_irqrestore(&dev->event_lock, flags);
1652
1653 if (stall_detected) {
1654 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1655 intel_prepare_page_flip(dev, intel_crtc->plane);
1656 }
1657}
1658
42f52ef8
KP		 1659/* Called from drm generic code, passed 'crtc' which
1660 * we use as a pipe index
1661 */
f71d4af4 1662static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1663{
1664 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1665 unsigned long irqflags;
71e0ffa5 1666
5eddb70b 1667 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1668 return -EINVAL;
0a3e67a4 1669
1ec14ad3 1670 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1671 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1672 i915_enable_pipestat(dev_priv, pipe,
1673 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1674 else
7c463586
KP		 1675 i915_enable_pipestat(dev_priv, pipe,
1676 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1677
1678 /* maintain vblank delivery even in deep C-states */
1679 if (dev_priv->info->gen == 3)
6b26c86d 1680 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1681 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1682
0a3e67a4
JB		 1683 return 0;
1684}
1685
f71d4af4 1686static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1687{
1688 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1689 unsigned long irqflags;
b518421f
PZ		 1690 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1691 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1692
1693 if (!i915_pipe_enabled(dev, pipe))
1694 return -EINVAL;
1695
1696 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1697 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1698 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1699
1700 return 0;
1701}
1702
7e231dbe
JB		 1703static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1704{
1705 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1706 unsigned long irqflags;
31acc7f5 1707 u32 imr;
7e231dbe
JB		 1708
1709 if (!i915_pipe_enabled(dev, pipe))
1710 return -EINVAL;
1711
1712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1713 imr = I915_READ(VLV_IMR);
31acc7f5 1714 if (pipe == 0)
7e231dbe 1715 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1716 else
7e231dbe 1717 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1718 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1719 i915_enable_pipestat(dev_priv, pipe,
1720 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1721 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1722
1723 return 0;
1724}
1725
42f52ef8
KP		 1726/* Called from drm generic code, passed 'crtc' which
1727 * we use as a pipe index
1728 */
f71d4af4 1729static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1730{
1731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1732 unsigned long irqflags;
0a3e67a4 1733
1ec14ad3 1734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1735 if (dev_priv->info->gen == 3)
6b26c86d 1736 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1737
f796cf8f
JB		 1738 i915_disable_pipestat(dev_priv, pipe,
1739 PIPE_VBLANK_INTERRUPT_ENABLE |
1740 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1741 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1742}
1743
f71d4af4 1744static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1745{
1746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1747 unsigned long irqflags;
b518421f
PZ		 1748 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1749 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1750
1751 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1752 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1753 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1754}
1755
7e231dbe
JB		 1756static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1757{
1758 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1759 unsigned long irqflags;
31acc7f5 1760 u32 imr;
7e231dbe
JB		 1761
1762 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1763 i915_disable_pipestat(dev_priv, pipe,
1764 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1765 imr = I915_READ(VLV_IMR);
31acc7f5 1766 if (pipe == 0)
7e231dbe 1767 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1768 else
7e231dbe 1769 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1770 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1771 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1772}
1773
893eead0
CW		 1774static u32
1775ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1776{
893eead0
CW		 1777 return list_entry(ring->request_list.prev,
1778 struct drm_i915_gem_request, list)->seqno;
1779}
1780
9107e9d2
CW		 1781static bool
1782ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1783{
1784 return (list_empty(&ring->request_list) ||
1785 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 1786}
1787
6274f212
CW		 1788static struct intel_ring_buffer *
1789semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 1790{
1791 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 1792 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 1793
1794 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1795 if ((ipehr & ~(0x3 << 16)) !=
1796 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 1797 return NULL;
a24a11e6
CW		 1798
1799 /* ACTHD is likely pointing to the dword after the actual command,
1800 * so scan backwards until we find the MBOX.
1801 */
6274f212 1802 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 1803 acthd_min = max((int)acthd - 3 * 4, 0);
1804 do {
1805 cmd = ioread32(ring->virtual_start + acthd);
1806 if (cmd == ipehr)
1807 break;
1808
1809 acthd -= 4;
1810 if (acthd < acthd_min)
6274f212 1811 return NULL;
a24a11e6
CW		 1812 } while (1);
1813
6274f212
CW		 1814 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1815 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 1816}
1817
6274f212
CW		 1818static int semaphore_passed(struct intel_ring_buffer *ring)
1819{
1820 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1821 struct intel_ring_buffer *signaller;
1822 u32 seqno, ctl;
1823
1824 ring->hangcheck.deadlock = true;
1825
1826 signaller = semaphore_waits_for(ring, &seqno);
1827 if (signaller == NULL || signaller->hangcheck.deadlock)
1828 return -1;
1829
1830 /* cursory check for an unkickable deadlock */
1831 ctl = I915_READ_CTL(signaller);
1832 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1833 return -1;
1834
1835 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1836}
1837
1838static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1839{
1840 struct intel_ring_buffer *ring;
1841 int i;
1842
1843 for_each_ring(ring, dev_priv, i)
1844 ring->hangcheck.deadlock = false;
1845}
1846
ad8beaea
MK		 1847static enum intel_ring_hangcheck_action
1848ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 1849{
1850 struct drm_device *dev = ring->dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 1852 u32 tmp;
1853
6274f212 1854 if (ring->hangcheck.acthd != acthd)
f2f4d82f 1855 return HANGCHECK_ACTIVE;
6274f212 1856
9107e9d2 1857 if (IS_GEN2(dev))
f2f4d82f 1858 return HANGCHECK_HUNG;
9107e9d2
CW		 1859
1860 /* Is the chip hanging on a WAIT_FOR_EVENT?
1861 * If so we can simply poke the RB_WAIT bit
1862 * and break the hang. This should work on
1863 * all but the second generation chipsets.
1864 */
1865 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 1866 if (tmp & RING_WAIT) {
1867 DRM_ERROR("Kicking stuck wait on %s\n",
1868 ring->name);
1869 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1870 return HANGCHECK_KICK;
6274f212
CW		 1871 }
1872
1873 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1874 switch (semaphore_passed(ring)) {
1875 default:
f2f4d82f 1876 return HANGCHECK_HUNG;
6274f212
CW		 1877 case 1:
1878 DRM_ERROR("Kicking stuck semaphore on %s\n",
1879 ring->name);
1880 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1881 return HANGCHECK_KICK;
6274f212 1882 case 0:
f2f4d82f 1883 return HANGCHECK_WAIT;
6274f212 1884 }
9107e9d2 1885 }
ed5cbb03 1886
f2f4d82f 1887 return HANGCHECK_HUNG;
ed5cbb03
MK		 1888}
1889
f65d9421
BG		 1890/**
1891 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 1892 * batchbuffers in a long time. We keep track per ring seqno progress and
1893 * if there are no progress, hangcheck score for that ring is increased.
1894 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1895 * we kick the ring. If we see no progress on three subsequent calls
1896 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 1897 */
a658b5d2 1898static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 1899{
1900 struct drm_device *dev = (struct drm_device *)data;
1901 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 1902 struct intel_ring_buffer *ring;
b4519513 1903 int i;
05407ff8 1904 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 1905 bool stuck[I915_NUM_RINGS] = { 0 };
1906#define BUSY 1
1907#define KICK 5
1908#define HUNG 20
1909#define FIRE 30
893eead0 1910
3e0dc6b0
BW		 1911 if (!i915_enable_hangcheck)
1912 return;
1913
b4519513 1914 for_each_ring(ring, dev_priv, i) {
05407ff8 1915 u32 seqno, acthd;
9107e9d2 1916 bool busy = true;
05407ff8 1917
6274f212
CW		 1918 semaphore_clear_deadlocks(dev_priv);
1919
05407ff8
MK		 1920 seqno = ring->get_seqno(ring, false);
1921 acthd = intel_ring_get_active_head(ring);
b4519513 1922
9107e9d2
CW		 1923 if (ring->hangcheck.seqno == seqno) {
1924 if (ring_idle(ring, seqno)) {
1925 if (waitqueue_active(&ring->irq_queue)) {
1926 /* Issue a wake-up to catch stuck h/w. */
1927 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1928 ring->name);
1929 wake_up_all(&ring->irq_queue);
1930 ring->hangcheck.score += HUNG;
1931 } else
1932 busy = false;
05407ff8 1933 } else {
6274f212
CW		 1934 /* We always increment the hangcheck score
1935 * if the ring is busy and still processing
1936 * the same request, so that no single request
1937 * can run indefinitely (such as a chain of
1938 * batches). The only time we do not increment
1939 * the hangcheck score on this ring, if this
1940 * ring is in a legitimate wait for another
1941 * ring. In that case the waiting ring is a
1942 * victim and we want to be sure we catch the
1943 * right culprit. Then every time we do kick
1944 * the ring, add a small increment to the
1945 * score so that we can catch a batch that is
1946 * being repeatedly kicked and so responsible
1947 * for stalling the machine.
1948 */
ad8beaea
MK		 1949 ring->hangcheck.action = ring_stuck(ring,
1950 acthd);
1951
1952 switch (ring->hangcheck.action) {
f2f4d82f 1953 case HANGCHECK_WAIT:
6274f212 1954 break;
f2f4d82f 1955 case HANGCHECK_ACTIVE:
ea04cb31 1956 ring->hangcheck.score += BUSY;
6274f212 1957 break;
f2f4d82f 1958 case HANGCHECK_KICK:
ea04cb31 1959 ring->hangcheck.score += KICK;
6274f212 1960 break;
f2f4d82f 1961 case HANGCHECK_HUNG:
ea04cb31 1962 ring->hangcheck.score += HUNG;
6274f212
CW		 1963 stuck[i] = true;
1964 break;
1965 }
05407ff8 1966 }
9107e9d2
CW		 1967 } else {
1968 /* Gradually reduce the count so that we catch DoS
1969 * attempts across multiple batches.
1970 */
1971 if (ring->hangcheck.score > 0)
1972 ring->hangcheck.score--;
d1e61e7f
CW		 1973 }
1974
05407ff8
MK		 1975 ring->hangcheck.seqno = seqno;
1976 ring->hangcheck.acthd = acthd;
9107e9d2 1977 busy_count += busy;
893eead0 1978 }
b9201c14 1979
92cab734 1980 for_each_ring(ring, dev_priv, i) {
9107e9d2 1981 if (ring->hangcheck.score > FIRE) {
acd78c11 1982 DRM_ERROR("%s on %s\n",
05407ff8 1983 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 1984 ring->name);
1985 rings_hung++;
92cab734
MK		 1986 }
1987 }
1988
05407ff8
MK		 1989 if (rings_hung)
1990 return i915_handle_error(dev, true);
f65d9421 1991
05407ff8
MK		 1992 if (busy_count)
1993 /* Reset timer case chip hangs without another request
1994 * being added */
10cd45b6
MK		 1995 i915_queue_hangcheck(dev);
1996}
1997
1998void i915_queue_hangcheck(struct drm_device *dev)
1999{
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 if (!i915_enable_hangcheck)
2002 return;
2003
2004 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2005 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2006}
2007
91738a95
PZ		 2008static void ibx_irq_preinstall(struct drm_device *dev)
2009{
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011
2012 if (HAS_PCH_NOP(dev))
2013 return;
2014
2015 /* south display irq */
2016 I915_WRITE(SDEIMR, 0xffffffff);
2017 /*
2018 * SDEIER is also touched by the interrupt handler to work around missed
2019 * PCH interrupts. Hence we can't update it after the interrupt handler
2020 * is enabled - instead we unconditionally enable all PCH interrupt
2021 * sources here, but then only unmask them as needed with SDEIMR.
2022 */
2023 I915_WRITE(SDEIER, 0xffffffff);
2024 POSTING_READ(SDEIER);
2025}
2026
d18ea1b5
DV		 2027static void gen5_gt_irq_preinstall(struct drm_device *dev)
2028{
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030
2031 /* and GT */
2032 I915_WRITE(GTIMR, 0xffffffff);
2033 I915_WRITE(GTIER, 0x0);
2034 POSTING_READ(GTIER);
2035
2036 if (INTEL_INFO(dev)->gen >= 6) {
2037 /* and PM */
2038 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2039 I915_WRITE(GEN6_PMIER, 0x0);
2040 POSTING_READ(GEN6_PMIER);
2041 }
2042}
2043
1da177e4
LT		 2044/* drm_dma.h hooks
2045*/
f71d4af4 2046static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2047{
2048 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2049
4697995b
JB		 2050 atomic_set(&dev_priv->irq_received, 0);
2051
036a4a7d 2052 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2053
036a4a7d
ZW		 2054 I915_WRITE(DEIMR, 0xffffffff);
2055 I915_WRITE(DEIER, 0x0);
3143a2bf 2056 POSTING_READ(DEIER);
036a4a7d 2057
d18ea1b5 2058 gen5_gt_irq_preinstall(dev);
c650156a 2059
91738a95 2060 ibx_irq_preinstall(dev);
7d99163d
BW		 2061}
2062
7e231dbe
JB		 2063static void valleyview_irq_preinstall(struct drm_device *dev)
2064{
2065 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2066 int pipe;
2067
2068 atomic_set(&dev_priv->irq_received, 0);
2069
7e231dbe
JB		 2070 /* VLV magic */
2071 I915_WRITE(VLV_IMR, 0);
2072 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2073 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2074 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2075
7e231dbe
JB		 2076 /* and GT */
2077 I915_WRITE(GTIIR, I915_READ(GTIIR));
2078 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2079
2080 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2081
2082 I915_WRITE(DPINVGTT, 0xff);
2083
2084 I915_WRITE(PORT_HOTPLUG_EN, 0);
2085 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2086 for_each_pipe(pipe)
2087 I915_WRITE(PIPESTAT(pipe), 0xffff);
2088 I915_WRITE(VLV_IIR, 0xffffffff);
2089 I915_WRITE(VLV_IMR, 0xffffffff);
2090 I915_WRITE(VLV_IER, 0x0);
2091 POSTING_READ(VLV_IER);
2092}
2093
82a28bcf 2094static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2095{
2096 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2097 struct drm_mode_config *mode_config = &dev->mode_config;
2098 struct intel_encoder *intel_encoder;
fee884ed 2099 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2100
2101 if (HAS_PCH_IBX(dev)) {
fee884ed 2102 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2103 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2104 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2105 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2106 } else {
fee884ed 2107 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2108 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2109 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2110 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2111 }
7fe0b973 2112
fee884ed 2113 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2114
2115 /*
2116 * Enable digital hotplug on the PCH, and configure the DP short pulse
2117 * duration to 2ms (which is the minimum in the Display Port spec)
2118 *
2119 * This register is the same on all known PCH chips.
2120 */
7fe0b973
KP		 2121 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2122 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2123 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2124 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2125 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2126 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2127}
2128
d46da437
PZ		 2129static void ibx_irq_postinstall(struct drm_device *dev)
2130{
2131 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2132 u32 mask;
e5868a31 2133
692a04cf
DV		 2134 if (HAS_PCH_NOP(dev))
2135 return;
2136
8664281b
PZ		 2137 if (HAS_PCH_IBX(dev)) {
2138 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2139 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2140 } else {
2141 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2142
2143 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2144 }
ab5c608b 2145
d46da437
PZ		 2146 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2147 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2148}
2149
0a9a8c91
DV		 2150static void gen5_gt_irq_postinstall(struct drm_device *dev)
2151{
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2153 u32 pm_irqs, gt_irqs;
2154
2155 pm_irqs = gt_irqs = 0;
2156
2157 dev_priv->gt_irq_mask = ~0;
2158 if (HAS_L3_GPU_CACHE(dev)) {
2159 /* L3 parity interrupt is always unmasked. */
2160 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2161 gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2162 }
2163
2164 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2165 if (IS_GEN5(dev)) {
2166 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2167 ILK_BSD_USER_INTERRUPT;
2168 } else {
2169 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2170 }
2171
2172 I915_WRITE(GTIIR, I915_READ(GTIIR));
2173 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2174 I915_WRITE(GTIER, gt_irqs);
2175 POSTING_READ(GTIER);
2176
2177 if (INTEL_INFO(dev)->gen >= 6) {
2178 pm_irqs |= GEN6_PM_RPS_EVENTS;
2179
2180 if (HAS_VEBOX(dev))
2181 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2182
2183 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2184 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2185 I915_WRITE(GEN6_PMIER, pm_irqs);
2186 POSTING_READ(GEN6_PMIER);
2187 }
2188}
2189
f71d4af4 2190static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2191{
4bc9d430 2192 unsigned long irqflags;
036a4a7d 2193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2194 u32 display_mask, extra_mask;
2195
2196 if (INTEL_INFO(dev)->gen >= 7) {
2197 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2198 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2199 DE_PLANEB_FLIP_DONE_IVB |
2200 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2201 DE_ERR_INT_IVB);
2202 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2203 DE_PIPEA_VBLANK_IVB);
2204
2205 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2206 } else {
2207 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2208 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2209 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2210 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2211 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2212 }
036a4a7d 2213
1ec14ad3 2214 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2215
2216 /* should always can generate irq */
2217 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2218 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2219 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2220 POSTING_READ(DEIER);
036a4a7d 2221
0a9a8c91 2222 gen5_gt_irq_postinstall(dev);
036a4a7d 2223
d46da437 2224 ibx_irq_postinstall(dev);
7fe0b973 2225
f97108d1 2226 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2227 /* Enable PCU event interrupts
2228 *
2229 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2230 * setup is guaranteed to run in single-threaded context. But we
2231 * need it to make the assert_spin_locked happy. */
2232 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2233 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2234 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2235 }
2236
036a4a7d
ZW		 2237 return 0;
2238}
2239
7e231dbe
JB		 2240static int valleyview_irq_postinstall(struct drm_device *dev)
2241{
2242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2243 u32 enable_mask;
31acc7f5 2244 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2245 unsigned long irqflags;
7e231dbe
JB		 2246
2247 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2248 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2249 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2250 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2251 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2252
31acc7f5
JB		 2253 /*
2254 *Leave vblank interrupts masked initially. enable/disable will
2255 * toggle them based on usage.
2256 */
2257 dev_priv->irq_mask = (~enable_mask) |
2258 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2259 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2260
20afbda2
DV		 2261 I915_WRITE(PORT_HOTPLUG_EN, 0);
2262 POSTING_READ(PORT_HOTPLUG_EN);
2263
7e231dbe
JB		 2264 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2265 I915_WRITE(VLV_IER, enable_mask);
2266 I915_WRITE(VLV_IIR, 0xffffffff);
2267 I915_WRITE(PIPESTAT(0), 0xffff);
2268 I915_WRITE(PIPESTAT(1), 0xffff);
2269 POSTING_READ(VLV_IER);
2270
b79480ba
DV		 2271 /* Interrupt setup is already guaranteed to be single-threaded, this is
2272 * just to make the assert_spin_locked check happy. */
2273 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2274 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2275 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2276 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2277 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2278
7e231dbe
JB		 2279 I915_WRITE(VLV_IIR, 0xffffffff);
2280 I915_WRITE(VLV_IIR, 0xffffffff);
2281
0a9a8c91 2282 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2283
2284 /* ack & enable invalid PTE error interrupts */
2285#if 0 /* FIXME: add support to irq handler for checking these bits */
2286 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2287 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2288#endif
2289
2290 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2291
2292 return 0;
2293}
2294
7e231dbe
JB		 2295static void valleyview_irq_uninstall(struct drm_device *dev)
2296{
2297 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2298 int pipe;
2299
2300 if (!dev_priv)
2301 return;
2302
ac4c16c5
EE		 2303 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2304
7e231dbe
JB		 2305 for_each_pipe(pipe)
2306 I915_WRITE(PIPESTAT(pipe), 0xffff);
2307
2308 I915_WRITE(HWSTAM, 0xffffffff);
2309 I915_WRITE(PORT_HOTPLUG_EN, 0);
2310 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2311 for_each_pipe(pipe)
2312 I915_WRITE(PIPESTAT(pipe), 0xffff);
2313 I915_WRITE(VLV_IIR, 0xffffffff);
2314 I915_WRITE(VLV_IMR, 0xffffffff);
2315 I915_WRITE(VLV_IER, 0x0);
2316 POSTING_READ(VLV_IER);
2317}
2318
f71d4af4 2319static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2320{
2321 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2322
2323 if (!dev_priv)
2324 return;
2325
ac4c16c5
EE		 2326 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2327
036a4a7d
ZW		 2328 I915_WRITE(HWSTAM, 0xffffffff);
2329
2330 I915_WRITE(DEIMR, 0xffffffff);
2331 I915_WRITE(DEIER, 0x0);
2332 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2333 if (IS_GEN7(dev))
2334 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2335
2336 I915_WRITE(GTIMR, 0xffffffff);
2337 I915_WRITE(GTIER, 0x0);
2338 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2339
ab5c608b
BW		 2340 if (HAS_PCH_NOP(dev))
2341 return;
2342
192aac1f
KP		 2343 I915_WRITE(SDEIMR, 0xffffffff);
2344 I915_WRITE(SDEIER, 0x0);
2345 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2346 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2347 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2348}
2349
a266c7d5 2350static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2351{
2352 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2353 int pipe;
91e3738e 2354
a266c7d5 2355 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2356
9db4a9c7
JB		 2357 for_each_pipe(pipe)
2358 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2359 I915_WRITE16(IMR, 0xffff);
2360 I915_WRITE16(IER, 0x0);
2361 POSTING_READ16(IER);
c2798b19
CW		 2362}
2363
2364static int i8xx_irq_postinstall(struct drm_device *dev)
2365{
2366 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2367
c2798b19
CW		 2368 I915_WRITE16(EMR,
2369 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2370
2371 /* Unmask the interrupts that we always want on. */
2372 dev_priv->irq_mask =
2373 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2374 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2375 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2376 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2377 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2378 I915_WRITE16(IMR, dev_priv->irq_mask);
2379
2380 I915_WRITE16(IER,
2381 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2382 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2383 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2384 I915_USER_INTERRUPT);
2385 POSTING_READ16(IER);
2386
2387 return 0;
2388}
2389
90a72f87
VS		 2390/*
2391 * Returns true when a page flip has completed.
2392 */
2393static bool i8xx_handle_vblank(struct drm_device *dev,
2394 int pipe, u16 iir)
2395{
2396 drm_i915_private_t *dev_priv = dev->dev_private;
2397 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2398
2399 if (!drm_handle_vblank(dev, pipe))
2400 return false;
2401
2402 if ((iir & flip_pending) == 0)
2403 return false;
2404
2405 intel_prepare_page_flip(dev, pipe);
2406
2407 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2408 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2409 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2410 * the flip is completed (no longer pending). Since this doesn't raise
2411 * an interrupt per se, we watch for the change at vblank.
2412 */
2413 if (I915_READ16(ISR) & flip_pending)
2414 return false;
2415
2416 intel_finish_page_flip(dev, pipe);
2417
2418 return true;
2419}
2420
ff1f525e 2421static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2422{
2423 struct drm_device *dev = (struct drm_device *) arg;
2424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2425 u16 iir, new_iir;
2426 u32 pipe_stats[2];
2427 unsigned long irqflags;
c2798b19
CW		 2428 int pipe;
2429 u16 flip_mask =
2430 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2431 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2432
2433 atomic_inc(&dev_priv->irq_received);
2434
2435 iir = I915_READ16(IIR);
2436 if (iir == 0)
2437 return IRQ_NONE;
2438
2439 while (iir & ~flip_mask) {
2440 /* Can't rely on pipestat interrupt bit in iir as it might
2441 * have been cleared after the pipestat interrupt was received.
2442 * It doesn't set the bit in iir again, but it still produces
2443 * interrupts (for non-MSI).
2444 */
2445 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2446 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2447 i915_handle_error(dev, false);
2448
2449 for_each_pipe(pipe) {
2450 int reg = PIPESTAT(pipe);
2451 pipe_stats[pipe] = I915_READ(reg);
2452
2453 /*
2454 * Clear the PIPE*STAT regs before the IIR
2455 */
2456 if (pipe_stats[pipe] & 0x8000ffff) {
2457 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2458 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2459 pipe_name(pipe));
2460 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2461 }
2462 }
2463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2464
2465 I915_WRITE16(IIR, iir & ~flip_mask);
2466 new_iir = I915_READ16(IIR); /* Flush posted writes */
2467
d05c617e 2468 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2469
2470 if (iir & I915_USER_INTERRUPT)
2471 notify_ring(dev, &dev_priv->ring[RCS]);
2472
2473 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2474 i8xx_handle_vblank(dev, 0, iir))
2475 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2476
2477 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2478 i8xx_handle_vblank(dev, 1, iir))
2479 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2480
2481 iir = new_iir;
2482 }
2483
2484 return IRQ_HANDLED;
2485}
2486
2487static void i8xx_irq_uninstall(struct drm_device * dev)
2488{
2489 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2490 int pipe;
2491
c2798b19
CW		 2492 for_each_pipe(pipe) {
2493 /* Clear enable bits; then clear status bits */
2494 I915_WRITE(PIPESTAT(pipe), 0);
2495 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2496 }
2497 I915_WRITE16(IMR, 0xffff);
2498 I915_WRITE16(IER, 0x0);
2499 I915_WRITE16(IIR, I915_READ16(IIR));
2500}
2501
a266c7d5
CW		 2502static void i915_irq_preinstall(struct drm_device * dev)
2503{
2504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2505 int pipe;
2506
2507 atomic_set(&dev_priv->irq_received, 0);
2508
2509 if (I915_HAS_HOTPLUG(dev)) {
2510 I915_WRITE(PORT_HOTPLUG_EN, 0);
2511 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2512 }
2513
00d98ebd 2514 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2515 for_each_pipe(pipe)
2516 I915_WRITE(PIPESTAT(pipe), 0);
2517 I915_WRITE(IMR, 0xffffffff);
2518 I915_WRITE(IER, 0x0);
2519 POSTING_READ(IER);
2520}
2521
2522static int i915_irq_postinstall(struct drm_device *dev)
2523{
2524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2525 u32 enable_mask;
a266c7d5 2526
38bde180
CW		 2527 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2528
2529 /* Unmask the interrupts that we always want on. */
2530 dev_priv->irq_mask =
2531 ~(I915_ASLE_INTERRUPT |
2532 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2533 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2534 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2535 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2536 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2537
2538 enable_mask =
2539 I915_ASLE_INTERRUPT |
2540 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2541 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2542 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2543 I915_USER_INTERRUPT;
2544
a266c7d5 2545 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2546 I915_WRITE(PORT_HOTPLUG_EN, 0);
2547 POSTING_READ(PORT_HOTPLUG_EN);
2548
a266c7d5
CW		 2549 /* Enable in IER... */
2550 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2551 /* and unmask in IMR */
2552 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2553 }
2554
a266c7d5
CW		 2555 I915_WRITE(IMR, dev_priv->irq_mask);
2556 I915_WRITE(IER, enable_mask);
2557 POSTING_READ(IER);
2558
f49e38dd 2559 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2560
2561 return 0;
2562}
2563
90a72f87
VS		 2564/*
2565 * Returns true when a page flip has completed.
2566 */
2567static bool i915_handle_vblank(struct drm_device *dev,
2568 int plane, int pipe, u32 iir)
2569{
2570 drm_i915_private_t *dev_priv = dev->dev_private;
2571 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2572
2573 if (!drm_handle_vblank(dev, pipe))
2574 return false;
2575
2576 if ((iir & flip_pending) == 0)
2577 return false;
2578
2579 intel_prepare_page_flip(dev, plane);
2580
2581 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2582 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2583 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2584 * the flip is completed (no longer pending). Since this doesn't raise
2585 * an interrupt per se, we watch for the change at vblank.
2586 */
2587 if (I915_READ(ISR) & flip_pending)
2588 return false;
2589
2590 intel_finish_page_flip(dev, pipe);
2591
2592 return true;
2593}
2594
ff1f525e 2595static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2596{
2597 struct drm_device *dev = (struct drm_device *) arg;
2598 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2599 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2600 unsigned long irqflags;
38bde180
CW		 2601 u32 flip_mask =
2602 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2603 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2604 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2605
2606 atomic_inc(&dev_priv->irq_received);
2607
2608 iir = I915_READ(IIR);
38bde180
CW		 2609 do {
2610 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2611 bool blc_event = false;
a266c7d5
CW		 2612
2613 /* Can't rely on pipestat interrupt bit in iir as it might
2614 * have been cleared after the pipestat interrupt was received.
2615 * It doesn't set the bit in iir again, but it still produces
2616 * interrupts (for non-MSI).
2617 */
2618 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2619 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2620 i915_handle_error(dev, false);
2621
2622 for_each_pipe(pipe) {
2623 int reg = PIPESTAT(pipe);
2624 pipe_stats[pipe] = I915_READ(reg);
2625
38bde180 2626 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2627 if (pipe_stats[pipe] & 0x8000ffff) {
2628 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2629 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2630 pipe_name(pipe));
2631 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2632 irq_received = true;
a266c7d5
CW		 2633 }
2634 }
2635 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2636
2637 if (!irq_received)
2638 break;
2639
a266c7d5
CW		 2640 /* Consume port. Then clear IIR or we'll miss events */
2641 if ((I915_HAS_HOTPLUG(dev)) &&
2642 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2643 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2644 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2645
2646 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2647 hotplug_status);
91d131d2
DV		 2648
2649 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2650
a266c7d5 2651 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2652 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2653 }
2654
38bde180 2655 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2656 new_iir = I915_READ(IIR); /* Flush posted writes */
2657
a266c7d5
CW		 2658 if (iir & I915_USER_INTERRUPT)
2659 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2660
a266c7d5 2661 for_each_pipe(pipe) {
38bde180
CW		 2662 int plane = pipe;
2663 if (IS_MOBILE(dev))
2664 plane = !plane;
90a72f87 2665
8291ee90 2666 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2667 i915_handle_vblank(dev, plane, pipe, iir))
2668 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2669
2670 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2671 blc_event = true;
2672 }
2673
a266c7d5
CW		 2674 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2675 intel_opregion_asle_intr(dev);
2676
2677 /* With MSI, interrupts are only generated when iir
2678 * transitions from zero to nonzero. If another bit got
2679 * set while we were handling the existing iir bits, then
2680 * we would never get another interrupt.
2681 *
2682 * This is fine on non-MSI as well, as if we hit this path
2683 * we avoid exiting the interrupt handler only to generate
2684 * another one.
2685 *
2686 * Note that for MSI this could cause a stray interrupt report
2687 * if an interrupt landed in the time between writing IIR and
2688 * the posting read. This should be rare enough to never
2689 * trigger the 99% of 100,000 interrupts test for disabling
2690 * stray interrupts.
2691 */
38bde180 2692 ret = IRQ_HANDLED;
a266c7d5 2693 iir = new_iir;
38bde180 2694 } while (iir & ~flip_mask);
a266c7d5 2695
d05c617e 2696 i915_update_dri1_breadcrumb(dev);
8291ee90 2697
a266c7d5
CW		 2698 return ret;
2699}
2700
2701static void i915_irq_uninstall(struct drm_device * dev)
2702{
2703 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2704 int pipe;
2705
ac4c16c5
EE		 2706 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2707
a266c7d5
CW		 2708 if (I915_HAS_HOTPLUG(dev)) {
2709 I915_WRITE(PORT_HOTPLUG_EN, 0);
2710 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2711 }
2712
00d98ebd 2713 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2714 for_each_pipe(pipe) {
2715 /* Clear enable bits; then clear status bits */
a266c7d5 2716 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2717 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2718 }
a266c7d5
CW		 2719 I915_WRITE(IMR, 0xffffffff);
2720 I915_WRITE(IER, 0x0);
2721
a266c7d5
CW		 2722 I915_WRITE(IIR, I915_READ(IIR));
2723}
2724
2725static void i965_irq_preinstall(struct drm_device * dev)
2726{
2727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2728 int pipe;
2729
2730 atomic_set(&dev_priv->irq_received, 0);
2731
adca4730
CW		 2732 I915_WRITE(PORT_HOTPLUG_EN, 0);
2733 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2734
2735 I915_WRITE(HWSTAM, 0xeffe);
2736 for_each_pipe(pipe)
2737 I915_WRITE(PIPESTAT(pipe), 0);
2738 I915_WRITE(IMR, 0xffffffff);
2739 I915_WRITE(IER, 0x0);
2740 POSTING_READ(IER);
2741}
2742
2743static int i965_irq_postinstall(struct drm_device *dev)
2744{
2745 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2746 u32 enable_mask;
a266c7d5 2747 u32 error_mask;
b79480ba 2748 unsigned long irqflags;
a266c7d5 2749
a266c7d5 2750 /* Unmask the interrupts that we always want on. */
bbba0a97 2751 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2752 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2753 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2754 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2755 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2756 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2757 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2758
2759 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2760 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2761 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2762 enable_mask |= I915_USER_INTERRUPT;
2763
2764 if (IS_G4X(dev))
2765 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2766
b79480ba
DV		 2767 /* Interrupt setup is already guaranteed to be single-threaded, this is
2768 * just to make the assert_spin_locked check happy. */
2769 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 2770 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 2771 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 2772
a266c7d5
CW		 2773 /*
2774 * Enable some error detection, note the instruction error mask
2775 * bit is reserved, so we leave it masked.
2776 */
2777 if (IS_G4X(dev)) {
2778 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2779 GM45_ERROR_MEM_PRIV |
2780 GM45_ERROR_CP_PRIV |
2781 I915_ERROR_MEMORY_REFRESH);
2782 } else {
2783 error_mask = ~(I915_ERROR_PAGE_TABLE |
2784 I915_ERROR_MEMORY_REFRESH);
2785 }
2786 I915_WRITE(EMR, error_mask);
2787
2788 I915_WRITE(IMR, dev_priv->irq_mask);
2789 I915_WRITE(IER, enable_mask);
2790 POSTING_READ(IER);
2791
20afbda2
DV		 2792 I915_WRITE(PORT_HOTPLUG_EN, 0);
2793 POSTING_READ(PORT_HOTPLUG_EN);
2794
f49e38dd 2795 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2796
2797 return 0;
2798}
2799
bac56d5b 2800static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 2801{
2802 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 2803 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 2804 struct intel_encoder *intel_encoder;
20afbda2
DV		 2805 u32 hotplug_en;
2806
b5ea2d56
DV		 2807 assert_spin_locked(&dev_priv->irq_lock);
2808
bac56d5b
EE		 2809 if (I915_HAS_HOTPLUG(dev)) {
2810 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2811 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2812 /* Note HDMI and DP share hotplug bits */
e5868a31 2813 /* enable bits are the same for all generations */
cd569aed
EE		 2814 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2815 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2816 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 2817 /* Programming the CRT detection parameters tends
2818 to generate a spurious hotplug event about three
2819 seconds later. So just do it once.
2820 */
2821 if (IS_G4X(dev))
2822 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 2823 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 2824 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 2825
bac56d5b
EE		 2826 /* Ignore TV since it's buggy */
2827 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2828 }
a266c7d5
CW		 2829}
2830
ff1f525e 2831static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2832{
2833 struct drm_device *dev = (struct drm_device *) arg;
2834 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2835 u32 iir, new_iir;
2836 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2837 unsigned long irqflags;
2838 int irq_received;
2839 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2840 u32 flip_mask =
2841 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2842 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2843
2844 atomic_inc(&dev_priv->irq_received);
2845
2846 iir = I915_READ(IIR);
2847
a266c7d5 2848 for (;;) {
2c8ba29f
CW		 2849 bool blc_event = false;
2850
21ad8330 2851 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2852
2853 /* Can't rely on pipestat interrupt bit in iir as it might
2854 * have been cleared after the pipestat interrupt was received.
2855 * It doesn't set the bit in iir again, but it still produces
2856 * interrupts (for non-MSI).
2857 */
2858 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2859 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2860 i915_handle_error(dev, false);
2861
2862 for_each_pipe(pipe) {
2863 int reg = PIPESTAT(pipe);
2864 pipe_stats[pipe] = I915_READ(reg);
2865
2866 /*
2867 * Clear the PIPE*STAT regs before the IIR
2868 */
2869 if (pipe_stats[pipe] & 0x8000ffff) {
2870 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2871 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2872 pipe_name(pipe));
2873 I915_WRITE(reg, pipe_stats[pipe]);
2874 irq_received = 1;
2875 }
2876 }
2877 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2878
2879 if (!irq_received)
2880 break;
2881
2882 ret = IRQ_HANDLED;
2883
2884 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2885 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 2886 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 2887 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2888 HOTPLUG_INT_STATUS_G4X :
4f7fd709 2889 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 2890
2891 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2892 hotplug_status);
91d131d2
DV		 2893
2894 intel_hpd_irq_handler(dev, hotplug_trigger,
2895 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
2896
a266c7d5
CW		 2897 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2898 I915_READ(PORT_HOTPLUG_STAT);
2899 }
2900
21ad8330 2901 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2902 new_iir = I915_READ(IIR); /* Flush posted writes */
2903
a266c7d5
CW		 2904 if (iir & I915_USER_INTERRUPT)
2905 notify_ring(dev, &dev_priv->ring[RCS]);
2906 if (iir & I915_BSD_USER_INTERRUPT)
2907 notify_ring(dev, &dev_priv->ring[VCS]);
2908
a266c7d5 2909 for_each_pipe(pipe) {
2c8ba29f 2910 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2911 i915_handle_vblank(dev, pipe, pipe, iir))
2912 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2913
2914 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2915 blc_event = true;
2916 }
2917
2918
2919 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2920 intel_opregion_asle_intr(dev);
2921
515ac2bb
DV		 2922 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2923 gmbus_irq_handler(dev);
2924
a266c7d5
CW		 2925 /* With MSI, interrupts are only generated when iir
2926 * transitions from zero to nonzero. If another bit got
2927 * set while we were handling the existing iir bits, then
2928 * we would never get another interrupt.
2929 *
2930 * This is fine on non-MSI as well, as if we hit this path
2931 * we avoid exiting the interrupt handler only to generate
2932 * another one.
2933 *
2934 * Note that for MSI this could cause a stray interrupt report
2935 * if an interrupt landed in the time between writing IIR and
2936 * the posting read. This should be rare enough to never
2937 * trigger the 99% of 100,000 interrupts test for disabling
2938 * stray interrupts.
2939 */
2940 iir = new_iir;
2941 }
2942
d05c617e 2943 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2944
a266c7d5
CW		 2945 return ret;
2946}
2947
2948static void i965_irq_uninstall(struct drm_device * dev)
2949{
2950 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2951 int pipe;
2952
2953 if (!dev_priv)
2954 return;
2955
ac4c16c5
EE		 2956 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2957
adca4730
CW		 2958 I915_WRITE(PORT_HOTPLUG_EN, 0);
2959 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2960
2961 I915_WRITE(HWSTAM, 0xffffffff);
2962 for_each_pipe(pipe)
2963 I915_WRITE(PIPESTAT(pipe), 0);
2964 I915_WRITE(IMR, 0xffffffff);
2965 I915_WRITE(IER, 0x0);
2966
2967 for_each_pipe(pipe)
2968 I915_WRITE(PIPESTAT(pipe),
2969 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2970 I915_WRITE(IIR, I915_READ(IIR));
2971}
2972
ac4c16c5
EE		 2973static void i915_reenable_hotplug_timer_func(unsigned long data)
2974{
2975 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
2976 struct drm_device *dev = dev_priv->dev;
2977 struct drm_mode_config *mode_config = &dev->mode_config;
2978 unsigned long irqflags;
2979 int i;
2980
2981 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2982 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
2983 struct drm_connector *connector;
2984
2985 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
2986 continue;
2987
2988 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
2989
2990 list_for_each_entry(connector, &mode_config->connector_list, head) {
2991 struct intel_connector *intel_connector = to_intel_connector(connector);
2992
2993 if (intel_connector->encoder->hpd_pin == i) {
2994 if (connector->polled != intel_connector->polled)
2995 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
2996 drm_get_connector_name(connector));
2997 connector->polled = intel_connector->polled;
2998 if (!connector->polled)
2999 connector->polled = DRM_CONNECTOR_POLL_HPD;
3000 }
3001 }
3002 }
3003 if (dev_priv->display.hpd_irq_setup)
3004 dev_priv->display.hpd_irq_setup(dev);
3005 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3006}
3007
f71d4af4
JB		 3008void intel_irq_init(struct drm_device *dev)
3009{
8b2e326d
CW		 3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3013 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3014 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3015 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3016
99584db3
DV		 3017 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3018 i915_hangcheck_elapsed,
61bac78e 3019 (unsigned long) dev);
ac4c16c5
EE		 3020 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3021 (unsigned long) dev_priv);
61bac78e 3022
97a19a24 3023 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3024
f71d4af4
JB		 3025 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3026 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3027 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3028 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3029 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3030 }
3031
c3613de9
KP		 3032 if (drm_core_check_feature(dev, DRIVER_MODESET))
3033 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3034 else
3035 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3036 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3037
7e231dbe
JB		 3038 if (IS_VALLEYVIEW(dev)) {
3039 dev->driver->irq_handler = valleyview_irq_handler;
3040 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3041 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3042 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3043 dev->driver->enable_vblank = valleyview_enable_vblank;
3044 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3045 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3046 } else if (HAS_PCH_SPLIT(dev)) {
3047 dev->driver->irq_handler = ironlake_irq_handler;
3048 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3049 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3050 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3051 dev->driver->enable_vblank = ironlake_enable_vblank;
3052 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3053 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3054 } else {
c2798b19
CW		 3055 if (INTEL_INFO(dev)->gen == 2) {
3056 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3057 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3058 dev->driver->irq_handler = i8xx_irq_handler;
3059 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3060 } else if (INTEL_INFO(dev)->gen == 3) {
3061 dev->driver->irq_preinstall = i915_irq_preinstall;
3062 dev->driver->irq_postinstall = i915_irq_postinstall;
3063 dev->driver->irq_uninstall = i915_irq_uninstall;
3064 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3065 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3066 } else {
a266c7d5
CW		 3067 dev->driver->irq_preinstall = i965_irq_preinstall;
3068 dev->driver->irq_postinstall = i965_irq_postinstall;
3069 dev->driver->irq_uninstall = i965_irq_uninstall;
3070 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3071 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3072 }
f71d4af4
JB		 3073 dev->driver->enable_vblank = i915_enable_vblank;
3074 dev->driver->disable_vblank = i915_disable_vblank;
3075 }
3076}
20afbda2
DV		 3077
3078void intel_hpd_init(struct drm_device *dev)
3079{
3080 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3081 struct drm_mode_config *mode_config = &dev->mode_config;
3082 struct drm_connector *connector;
b5ea2d56 3083 unsigned long irqflags;
821450c6 3084 int i;
20afbda2 3085
821450c6
EE		 3086 for (i = 1; i < HPD_NUM_PINS; i++) {
3087 dev_priv->hpd_stats[i].hpd_cnt = 0;
3088 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3089 }
3090 list_for_each_entry(connector, &mode_config->connector_list, head) {
3091 struct intel_connector *intel_connector = to_intel_connector(connector);
3092 connector->polled = intel_connector->polled;
3093 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3094 connector->polled = DRM_CONNECTOR_POLL_HPD;
3095 }
b5ea2d56
DV		 3096
3097 /* Interrupt setup is already guaranteed to be single-threaded, this is
3098 * just to make the assert_spin_locked checks happy. */
3099 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3100 if (dev_priv->display.hpd_irq_setup)
3101 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3102 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3103}
Linux kernel - Deliverables
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