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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
704cfb87 | 65 | static const u32 hpd_status_g4x[] = { |
e5868a31 EE |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
036a4a7d | 83 | /* For display hotplug interrupt */ |
995b6762 | 84 | static void |
2d1013dd | 85 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 86 | { |
4bc9d430 DV |
87 | assert_spin_locked(&dev_priv->irq_lock); |
88 | ||
5d584b2e | 89 | if (dev_priv->pm.irqs_disabled) { |
c67a470b | 90 | WARN(1, "IRQs disabled\n"); |
5d584b2e | 91 | dev_priv->pm.regsave.deimr &= ~mask; |
c67a470b PZ |
92 | return; |
93 | } | |
94 | ||
1ec14ad3 CW |
95 | if ((dev_priv->irq_mask & mask) != 0) { |
96 | dev_priv->irq_mask &= ~mask; | |
97 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 98 | POSTING_READ(DEIMR); |
036a4a7d ZW |
99 | } |
100 | } | |
101 | ||
0ff9800a | 102 | static void |
2d1013dd | 103 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 104 | { |
4bc9d430 DV |
105 | assert_spin_locked(&dev_priv->irq_lock); |
106 | ||
5d584b2e | 107 | if (dev_priv->pm.irqs_disabled) { |
c67a470b | 108 | WARN(1, "IRQs disabled\n"); |
5d584b2e | 109 | dev_priv->pm.regsave.deimr |= mask; |
c67a470b PZ |
110 | return; |
111 | } | |
112 | ||
1ec14ad3 CW |
113 | if ((dev_priv->irq_mask & mask) != mask) { |
114 | dev_priv->irq_mask |= mask; | |
115 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 116 | POSTING_READ(DEIMR); |
036a4a7d ZW |
117 | } |
118 | } | |
119 | ||
43eaea13 PZ |
120 | /** |
121 | * ilk_update_gt_irq - update GTIMR | |
122 | * @dev_priv: driver private | |
123 | * @interrupt_mask: mask of interrupt bits to update | |
124 | * @enabled_irq_mask: mask of interrupt bits to enable | |
125 | */ | |
126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
127 | uint32_t interrupt_mask, | |
128 | uint32_t enabled_irq_mask) | |
129 | { | |
130 | assert_spin_locked(&dev_priv->irq_lock); | |
131 | ||
5d584b2e | 132 | if (dev_priv->pm.irqs_disabled) { |
c67a470b | 133 | WARN(1, "IRQs disabled\n"); |
5d584b2e PZ |
134 | dev_priv->pm.regsave.gtimr &= ~interrupt_mask; |
135 | dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask & | |
c67a470b PZ |
136 | interrupt_mask); |
137 | return; | |
138 | } | |
139 | ||
43eaea13 PZ |
140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
143 | POSTING_READ(GTIMR); | |
144 | } | |
145 | ||
146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
147 | { | |
148 | ilk_update_gt_irq(dev_priv, mask, mask); | |
149 | } | |
150 | ||
151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
152 | { | |
153 | ilk_update_gt_irq(dev_priv, mask, 0); | |
154 | } | |
155 | ||
edbfdb45 PZ |
156 | /** |
157 | * snb_update_pm_irq - update GEN6_PMIMR | |
158 | * @dev_priv: driver private | |
159 | * @interrupt_mask: mask of interrupt bits to update | |
160 | * @enabled_irq_mask: mask of interrupt bits to enable | |
161 | */ | |
162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
163 | uint32_t interrupt_mask, | |
164 | uint32_t enabled_irq_mask) | |
165 | { | |
605cd25b | 166 | uint32_t new_val; |
edbfdb45 PZ |
167 | |
168 | assert_spin_locked(&dev_priv->irq_lock); | |
169 | ||
5d584b2e | 170 | if (dev_priv->pm.irqs_disabled) { |
c67a470b | 171 | WARN(1, "IRQs disabled\n"); |
5d584b2e PZ |
172 | dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask; |
173 | dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
c67a470b PZ |
174 | interrupt_mask); |
175 | return; | |
176 | } | |
177 | ||
605cd25b | 178 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
179 | new_val &= ~interrupt_mask; |
180 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
181 | ||
605cd25b PZ |
182 | if (new_val != dev_priv->pm_irq_mask) { |
183 | dev_priv->pm_irq_mask = new_val; | |
184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
185 | POSTING_READ(GEN6_PMIMR); |
186 | } | |
edbfdb45 PZ |
187 | } |
188 | ||
189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
190 | { | |
191 | snb_update_pm_irq(dev_priv, mask, mask); | |
192 | } | |
193 | ||
194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
195 | { | |
196 | snb_update_pm_irq(dev_priv, mask, 0); | |
197 | } | |
198 | ||
8664281b PZ |
199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
200 | { | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
202 | struct intel_crtc *crtc; | |
203 | enum pipe pipe; | |
204 | ||
4bc9d430 DV |
205 | assert_spin_locked(&dev_priv->irq_lock); |
206 | ||
8664281b PZ |
207 | for_each_pipe(pipe) { |
208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
209 | ||
210 | if (crtc->cpu_fifo_underrun_disabled) | |
211 | return false; | |
212 | } | |
213 | ||
214 | return true; | |
215 | } | |
216 | ||
217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | enum pipe pipe; | |
221 | struct intel_crtc *crtc; | |
222 | ||
fee884ed DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
8664281b PZ |
225 | for_each_pipe(pipe) { |
226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
227 | ||
228 | if (crtc->pch_fifo_underrun_disabled) | |
229 | return false; | |
230 | } | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
2d9d2b0b VS |
235 | static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe) |
236 | { | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u32 reg = PIPESTAT(pipe); | |
239 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
240 | ||
241 | assert_spin_locked(&dev_priv->irq_lock); | |
242 | ||
243 | I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS); | |
244 | POSTING_READ(reg); | |
245 | } | |
246 | ||
8664281b PZ |
247 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, |
248 | enum pipe pipe, bool enable) | |
249 | { | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
251 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
252 | DE_PIPEB_FIFO_UNDERRUN; | |
253 | ||
254 | if (enable) | |
255 | ironlake_enable_display_irq(dev_priv, bit); | |
256 | else | |
257 | ironlake_disable_display_irq(dev_priv, bit); | |
258 | } | |
259 | ||
260 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 261 | enum pipe pipe, bool enable) |
8664281b PZ |
262 | { |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 264 | if (enable) { |
7336df65 DV |
265 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
266 | ||
8664281b PZ |
267 | if (!ivb_can_enable_err_int(dev)) |
268 | return; | |
269 | ||
8664281b PZ |
270 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
271 | } else { | |
7336df65 DV |
272 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
273 | ||
274 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 275 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
276 | |
277 | if (!was_enabled && | |
278 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
279 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
280 | pipe_name(pipe)); | |
281 | } | |
8664281b PZ |
282 | } |
283 | } | |
284 | ||
38d83c96 DV |
285 | static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, |
286 | enum pipe pipe, bool enable) | |
287 | { | |
288 | struct drm_i915_private *dev_priv = dev->dev_private; | |
289 | ||
290 | assert_spin_locked(&dev_priv->irq_lock); | |
291 | ||
292 | if (enable) | |
293 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; | |
294 | else | |
295 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; | |
296 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
297 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
298 | } | |
299 | ||
fee884ed DV |
300 | /** |
301 | * ibx_display_interrupt_update - update SDEIMR | |
302 | * @dev_priv: driver private | |
303 | * @interrupt_mask: mask of interrupt bits to update | |
304 | * @enabled_irq_mask: mask of interrupt bits to enable | |
305 | */ | |
306 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
307 | uint32_t interrupt_mask, | |
308 | uint32_t enabled_irq_mask) | |
309 | { | |
310 | uint32_t sdeimr = I915_READ(SDEIMR); | |
311 | sdeimr &= ~interrupt_mask; | |
312 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
313 | ||
314 | assert_spin_locked(&dev_priv->irq_lock); | |
315 | ||
5d584b2e | 316 | if (dev_priv->pm.irqs_disabled && |
c67a470b PZ |
317 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { |
318 | WARN(1, "IRQs disabled\n"); | |
5d584b2e PZ |
319 | dev_priv->pm.regsave.sdeimr &= ~interrupt_mask; |
320 | dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask & | |
c67a470b PZ |
321 | interrupt_mask); |
322 | return; | |
323 | } | |
324 | ||
fee884ed DV |
325 | I915_WRITE(SDEIMR, sdeimr); |
326 | POSTING_READ(SDEIMR); | |
327 | } | |
328 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
329 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
330 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
331 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
332 | ||
de28075d DV |
333 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
334 | enum transcoder pch_transcoder, | |
8664281b PZ |
335 | bool enable) |
336 | { | |
8664281b | 337 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
338 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
339 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
340 | |
341 | if (enable) | |
fee884ed | 342 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 343 | else |
fee884ed | 344 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
345 | } |
346 | ||
347 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
348 | enum transcoder pch_transcoder, | |
349 | bool enable) | |
350 | { | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
352 | ||
353 | if (enable) { | |
1dd246fb DV |
354 | I915_WRITE(SERR_INT, |
355 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
356 | ||
8664281b PZ |
357 | if (!cpt_can_enable_serr_int(dev)) |
358 | return; | |
359 | ||
fee884ed | 360 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 361 | } else { |
1dd246fb DV |
362 | uint32_t tmp = I915_READ(SERR_INT); |
363 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
364 | ||
365 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 366 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
367 | |
368 | if (!was_enabled && | |
369 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
370 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
371 | transcoder_name(pch_transcoder)); | |
372 | } | |
8664281b | 373 | } |
8664281b PZ |
374 | } |
375 | ||
376 | /** | |
377 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
378 | * @dev: drm device | |
379 | * @pipe: pipe | |
380 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
381 | * | |
382 | * This function makes us disable or enable CPU fifo underruns for a specific | |
383 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
384 | * reporting for one pipe may also disable all the other CPU error interruts for | |
385 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
386 | * bit for all the pipes. | |
387 | * | |
388 | * Returns the previous state of underrun reporting. | |
389 | */ | |
f88d42f1 ID |
390 | bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
391 | enum pipe pipe, bool enable) | |
8664281b PZ |
392 | { |
393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
394 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
395 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
396 | bool ret; |
397 | ||
77961eb9 ID |
398 | assert_spin_locked(&dev_priv->irq_lock); |
399 | ||
8664281b PZ |
400 | ret = !intel_crtc->cpu_fifo_underrun_disabled; |
401 | ||
402 | if (enable == ret) | |
403 | goto done; | |
404 | ||
405 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
406 | ||
2d9d2b0b VS |
407 | if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))) |
408 | i9xx_clear_fifo_underrun(dev, pipe); | |
409 | else if (IS_GEN5(dev) || IS_GEN6(dev)) | |
8664281b PZ |
410 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); |
411 | else if (IS_GEN7(dev)) | |
7336df65 | 412 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
38d83c96 DV |
413 | else if (IS_GEN8(dev)) |
414 | broadwell_set_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b PZ |
415 | |
416 | done: | |
f88d42f1 ID |
417 | return ret; |
418 | } | |
419 | ||
420 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
421 | enum pipe pipe, bool enable) | |
422 | { | |
423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
424 | unsigned long flags; | |
425 | bool ret; | |
426 | ||
427 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
428 | ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); | |
8664281b | 429 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
f88d42f1 | 430 | |
8664281b PZ |
431 | return ret; |
432 | } | |
433 | ||
91d181dd ID |
434 | static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, |
435 | enum pipe pipe) | |
436 | { | |
437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
438 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
439 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
440 | ||
441 | return !intel_crtc->cpu_fifo_underrun_disabled; | |
442 | } | |
443 | ||
8664281b PZ |
444 | /** |
445 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
446 | * @dev: drm device | |
447 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
448 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
449 | * | |
450 | * This function makes us disable or enable PCH fifo underruns for a specific | |
451 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
452 | * underrun reporting for one transcoder may also disable all the other PCH | |
453 | * error interruts for the other transcoders, due to the fact that there's just | |
454 | * one interrupt mask/enable bit for all the transcoders. | |
455 | * | |
456 | * Returns the previous state of underrun reporting. | |
457 | */ | |
458 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
459 | enum transcoder pch_transcoder, | |
460 | bool enable) | |
461 | { | |
462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
463 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
465 | unsigned long flags; |
466 | bool ret; | |
467 | ||
de28075d DV |
468 | /* |
469 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
470 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
471 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
472 | * underrun statistics in crtc A. Since we never expose this anywhere | |
473 | * nor use it outside of the fifo underrun code here using the "wrong" | |
474 | * crtc on LPT won't cause issues. | |
475 | */ | |
8664281b PZ |
476 | |
477 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
478 | ||
479 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
480 | ||
481 | if (enable == ret) | |
482 | goto done; | |
483 | ||
484 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
485 | ||
486 | if (HAS_PCH_IBX(dev)) | |
de28075d | 487 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
488 | else |
489 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
490 | ||
491 | done: | |
492 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
493 | return ret; | |
494 | } | |
495 | ||
496 | ||
b5ea642a | 497 | static void |
755e9019 ID |
498 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
499 | u32 enable_mask, u32 status_mask) | |
7c463586 | 500 | { |
46c06a30 | 501 | u32 reg = PIPESTAT(pipe); |
755e9019 | 502 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 503 | |
b79480ba DV |
504 | assert_spin_locked(&dev_priv->irq_lock); |
505 | ||
755e9019 ID |
506 | if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
507 | status_mask & ~PIPESTAT_INT_STATUS_MASK)) | |
508 | return; | |
509 | ||
510 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
511 | return; |
512 | ||
91d181dd ID |
513 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
514 | ||
46c06a30 | 515 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 516 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
517 | I915_WRITE(reg, pipestat); |
518 | POSTING_READ(reg); | |
7c463586 KP |
519 | } |
520 | ||
b5ea642a | 521 | static void |
755e9019 ID |
522 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
523 | u32 enable_mask, u32 status_mask) | |
7c463586 | 524 | { |
46c06a30 | 525 | u32 reg = PIPESTAT(pipe); |
755e9019 | 526 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 527 | |
b79480ba DV |
528 | assert_spin_locked(&dev_priv->irq_lock); |
529 | ||
755e9019 ID |
530 | if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
531 | status_mask & ~PIPESTAT_INT_STATUS_MASK)) | |
46c06a30 VS |
532 | return; |
533 | ||
755e9019 ID |
534 | if ((pipestat & enable_mask) == 0) |
535 | return; | |
536 | ||
91d181dd ID |
537 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
538 | ||
755e9019 | 539 | pipestat &= ~enable_mask; |
46c06a30 VS |
540 | I915_WRITE(reg, pipestat); |
541 | POSTING_READ(reg); | |
7c463586 KP |
542 | } |
543 | ||
10c59c51 ID |
544 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
545 | { | |
546 | u32 enable_mask = status_mask << 16; | |
547 | ||
548 | /* | |
549 | * On pipe A we don't support the PSR interrupt yet, on pipe B the | |
550 | * same bit MBZ. | |
551 | */ | |
552 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
553 | return 0; | |
554 | ||
555 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
556 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
557 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
558 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
559 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
560 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
561 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
562 | ||
563 | return enable_mask; | |
564 | } | |
565 | ||
755e9019 ID |
566 | void |
567 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
568 | u32 status_mask) | |
569 | { | |
570 | u32 enable_mask; | |
571 | ||
10c59c51 ID |
572 | if (IS_VALLEYVIEW(dev_priv->dev)) |
573 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
574 | status_mask); | |
575 | else | |
576 | enable_mask = status_mask << 16; | |
755e9019 ID |
577 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
578 | } | |
579 | ||
580 | void | |
581 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
582 | u32 status_mask) | |
583 | { | |
584 | u32 enable_mask; | |
585 | ||
10c59c51 ID |
586 | if (IS_VALLEYVIEW(dev_priv->dev)) |
587 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
588 | status_mask); | |
589 | else | |
590 | enable_mask = status_mask << 16; | |
755e9019 ID |
591 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
592 | } | |
593 | ||
01c66889 | 594 | /** |
f49e38dd | 595 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 596 | */ |
f49e38dd | 597 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 598 | { |
2d1013dd | 599 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 CW |
600 | unsigned long irqflags; |
601 | ||
f49e38dd JN |
602 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
603 | return; | |
604 | ||
1ec14ad3 | 605 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 606 | |
755e9019 | 607 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 608 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 609 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 610 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 CW |
611 | |
612 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
613 | } |
614 | ||
0a3e67a4 JB |
615 | /** |
616 | * i915_pipe_enabled - check if a pipe is enabled | |
617 | * @dev: DRM device | |
618 | * @pipe: pipe to check | |
619 | * | |
620 | * Reading certain registers when the pipe is disabled can hang the chip. | |
621 | * Use this routine to make sure the PLL is running and the pipe is active | |
622 | * before reading such registers if unsure. | |
623 | */ | |
624 | static int | |
625 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
626 | { | |
2d1013dd | 627 | struct drm_i915_private *dev_priv = dev->dev_private; |
702e7a56 | 628 | |
a01025af DV |
629 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
630 | /* Locking is horribly broken here, but whatever. */ | |
631 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 633 | |
a01025af DV |
634 | return intel_crtc->active; |
635 | } else { | |
636 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
637 | } | |
0a3e67a4 JB |
638 | } |
639 | ||
4cdb83ec VS |
640 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
641 | { | |
642 | /* Gen2 doesn't have a hardware frame counter */ | |
643 | return 0; | |
644 | } | |
645 | ||
42f52ef8 KP |
646 | /* Called from drm generic code, passed a 'crtc', which |
647 | * we use as a pipe index | |
648 | */ | |
f71d4af4 | 649 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 650 | { |
2d1013dd | 651 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
652 | unsigned long high_frame; |
653 | unsigned long low_frame; | |
391f75e2 | 654 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
655 | |
656 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 657 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 658 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
659 | return 0; |
660 | } | |
661 | ||
391f75e2 VS |
662 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
663 | struct intel_crtc *intel_crtc = | |
664 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
665 | const struct drm_display_mode *mode = | |
666 | &intel_crtc->config.adjusted_mode; | |
667 | ||
668 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
669 | } else { | |
a2d213dd | 670 | enum transcoder cpu_transcoder = (enum transcoder) pipe; |
391f75e2 VS |
671 | u32 htotal; |
672 | ||
673 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
674 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
675 | ||
676 | vbl_start *= htotal; | |
677 | } | |
678 | ||
9db4a9c7 JB |
679 | high_frame = PIPEFRAME(pipe); |
680 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 681 | |
0a3e67a4 JB |
682 | /* |
683 | * High & low register fields aren't synchronized, so make sure | |
684 | * we get a low value that's stable across two reads of the high | |
685 | * register. | |
686 | */ | |
687 | do { | |
5eddb70b | 688 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 689 | low = I915_READ(low_frame); |
5eddb70b | 690 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
691 | } while (high1 != high2); |
692 | ||
5eddb70b | 693 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 694 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 695 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
696 | |
697 | /* | |
698 | * The frame counter increments at beginning of active. | |
699 | * Cook up a vblank counter by also checking the pixel | |
700 | * counter against vblank start. | |
701 | */ | |
edc08d0a | 702 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
703 | } |
704 | ||
f71d4af4 | 705 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 706 | { |
2d1013dd | 707 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 708 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
709 | |
710 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 711 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 712 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
713 | return 0; |
714 | } | |
715 | ||
716 | return I915_READ(reg); | |
717 | } | |
718 | ||
ad3543ed MK |
719 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
720 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 721 | |
095163ba | 722 | static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe) |
54ddcbd2 VS |
723 | { |
724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
725 | uint32_t status; | |
24302624 VS |
726 | int reg; |
727 | ||
728 | if (INTEL_INFO(dev)->gen >= 8) { | |
729 | status = GEN8_PIPE_VBLANK; | |
730 | reg = GEN8_DE_PIPE_ISR(pipe); | |
731 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
732 | status = DE_PIPE_VBLANK_IVB(pipe); | |
733 | reg = DEISR; | |
54ddcbd2 | 734 | } else { |
24302624 VS |
735 | status = DE_PIPE_VBLANK(pipe); |
736 | reg = DEISR; | |
54ddcbd2 | 737 | } |
ad3543ed | 738 | |
24302624 | 739 | return __raw_i915_read32(dev_priv, reg) & status; |
54ddcbd2 VS |
740 | } |
741 | ||
f71d4af4 | 742 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
743 | unsigned int flags, int *vpos, int *hpos, |
744 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 745 | { |
c2baf4b7 VS |
746 | struct drm_i915_private *dev_priv = dev->dev_private; |
747 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
749 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 750 | int position; |
0af7e4df MK |
751 | int vbl_start, vbl_end, htotal, vtotal; |
752 | bool in_vbl = true; | |
753 | int ret = 0; | |
ad3543ed | 754 | unsigned long irqflags; |
0af7e4df | 755 | |
c2baf4b7 | 756 | if (!intel_crtc->active) { |
0af7e4df | 757 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 758 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
759 | return 0; |
760 | } | |
761 | ||
c2baf4b7 VS |
762 | htotal = mode->crtc_htotal; |
763 | vtotal = mode->crtc_vtotal; | |
764 | vbl_start = mode->crtc_vblank_start; | |
765 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 766 | |
d31faf65 VS |
767 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
768 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
769 | vbl_end /= 2; | |
770 | vtotal /= 2; | |
771 | } | |
772 | ||
c2baf4b7 VS |
773 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
774 | ||
ad3543ed MK |
775 | /* |
776 | * Lock uncore.lock, as we will do multiple timing critical raw | |
777 | * register reads, potentially with preemption disabled, so the | |
778 | * following code must not block on uncore.lock. | |
779 | */ | |
780 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
781 | ||
782 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ | |
783 | ||
784 | /* Get optional system timestamp before query. */ | |
785 | if (stime) | |
786 | *stime = ktime_get(); | |
787 | ||
7c06b08a | 788 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
789 | /* No obvious pixelcount register. Only query vertical |
790 | * scanout position from Display scan line register. | |
791 | */ | |
7c06b08a | 792 | if (IS_GEN2(dev)) |
ad3543ed | 793 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; |
7c06b08a | 794 | else |
ad3543ed | 795 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; |
54ddcbd2 | 796 | |
fcb81823 VS |
797 | if (HAS_DDI(dev)) { |
798 | /* | |
799 | * On HSW HDMI outputs there seems to be a 2 line | |
800 | * difference, whereas eDP has the normal 1 line | |
801 | * difference that earlier platforms have. External | |
802 | * DP is unknown. For now just check for the 2 line | |
803 | * difference case on all output types on HSW+. | |
804 | * | |
805 | * This might misinterpret the scanline counter being | |
806 | * one line too far along on eDP, but that's less | |
807 | * dangerous than the alternative since that would lead | |
808 | * the vblank timestamp code astray when it sees a | |
809 | * scanline count before vblank_start during a vblank | |
810 | * interrupt. | |
811 | */ | |
812 | in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); | |
813 | if ((in_vbl && (position == vbl_start - 2 || | |
814 | position == vbl_start - 1)) || | |
815 | (!in_vbl && (position == vbl_end - 2 || | |
816 | position == vbl_end - 1))) | |
817 | position = (position + 2) % vtotal; | |
818 | } else if (HAS_PCH_SPLIT(dev)) { | |
095163ba VS |
819 | /* |
820 | * The scanline counter increments at the leading edge | |
821 | * of hsync, ie. it completely misses the active portion | |
822 | * of the line. Fix up the counter at both edges of vblank | |
823 | * to get a more accurate picture whether we're in vblank | |
824 | * or not. | |
825 | */ | |
826 | in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); | |
827 | if ((in_vbl && position == vbl_start - 1) || | |
828 | (!in_vbl && position == vbl_end - 1)) | |
829 | position = (position + 1) % vtotal; | |
830 | } else { | |
831 | /* | |
832 | * ISR vblank status bits don't work the way we'd want | |
833 | * them to work on non-PCH platforms (for | |
834 | * ilk_pipe_in_vblank_locked()), and there doesn't | |
835 | * appear any other way to determine if we're currently | |
836 | * in vblank. | |
837 | * | |
838 | * Instead let's assume that we're already in vblank if | |
839 | * we got called from the vblank interrupt and the | |
840 | * scanline counter value indicates that we're on the | |
841 | * line just prior to vblank start. This should result | |
842 | * in the correct answer, unless the vblank interrupt | |
843 | * delivery really got delayed for almost exactly one | |
844 | * full frame/field. | |
845 | */ | |
846 | if (flags & DRM_CALLED_FROM_VBLIRQ && | |
847 | position == vbl_start - 1) { | |
848 | position = (position + 1) % vtotal; | |
849 | ||
850 | /* Signal this correction as "applied". */ | |
851 | ret |= 0x8; | |
852 | } | |
853 | } | |
0af7e4df MK |
854 | } else { |
855 | /* Have access to pixelcount since start of frame. | |
856 | * We can split this into vertical and horizontal | |
857 | * scanout position. | |
858 | */ | |
ad3543ed | 859 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 860 | |
3aa18df8 VS |
861 | /* convert to pixel counts */ |
862 | vbl_start *= htotal; | |
863 | vbl_end *= htotal; | |
864 | vtotal *= htotal; | |
0af7e4df MK |
865 | } |
866 | ||
ad3543ed MK |
867 | /* Get optional system timestamp after query. */ |
868 | if (etime) | |
869 | *etime = ktime_get(); | |
870 | ||
871 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
872 | ||
873 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
874 | ||
3aa18df8 VS |
875 | in_vbl = position >= vbl_start && position < vbl_end; |
876 | ||
877 | /* | |
878 | * While in vblank, position will be negative | |
879 | * counting up towards 0 at vbl_end. And outside | |
880 | * vblank, position will be positive counting | |
881 | * up since vbl_end. | |
882 | */ | |
883 | if (position >= vbl_start) | |
884 | position -= vbl_end; | |
885 | else | |
886 | position += vtotal - vbl_end; | |
0af7e4df | 887 | |
7c06b08a | 888 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
889 | *vpos = position; |
890 | *hpos = 0; | |
891 | } else { | |
892 | *vpos = position / htotal; | |
893 | *hpos = position - (*vpos * htotal); | |
894 | } | |
0af7e4df | 895 | |
0af7e4df MK |
896 | /* In vblank? */ |
897 | if (in_vbl) | |
898 | ret |= DRM_SCANOUTPOS_INVBL; | |
899 | ||
900 | return ret; | |
901 | } | |
902 | ||
f71d4af4 | 903 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
904 | int *max_error, |
905 | struct timeval *vblank_time, | |
906 | unsigned flags) | |
907 | { | |
4041b853 | 908 | struct drm_crtc *crtc; |
0af7e4df | 909 | |
7eb552ae | 910 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 911 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
912 | return -EINVAL; |
913 | } | |
914 | ||
915 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
916 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
917 | if (crtc == NULL) { | |
918 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
919 | return -EINVAL; | |
920 | } | |
921 | ||
922 | if (!crtc->enabled) { | |
923 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
924 | return -EBUSY; | |
925 | } | |
0af7e4df MK |
926 | |
927 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
928 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
929 | vblank_time, flags, | |
7da903ef VS |
930 | crtc, |
931 | &to_intel_crtc(crtc)->config.adjusted_mode); | |
0af7e4df MK |
932 | } |
933 | ||
67c347ff JN |
934 | static bool intel_hpd_irq_event(struct drm_device *dev, |
935 | struct drm_connector *connector) | |
321a1b30 EE |
936 | { |
937 | enum drm_connector_status old_status; | |
938 | ||
939 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
940 | old_status = connector->status; | |
941 | ||
942 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
943 | if (old_status == connector->status) |
944 | return false; | |
945 | ||
946 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
947 | connector->base.id, |
948 | drm_get_connector_name(connector), | |
67c347ff JN |
949 | drm_get_connector_status_name(old_status), |
950 | drm_get_connector_status_name(connector->status)); | |
951 | ||
952 | return true; | |
321a1b30 EE |
953 | } |
954 | ||
5ca58282 JB |
955 | /* |
956 | * Handle hotplug events outside the interrupt handler proper. | |
957 | */ | |
ac4c16c5 EE |
958 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
959 | ||
5ca58282 JB |
960 | static void i915_hotplug_work_func(struct work_struct *work) |
961 | { | |
2d1013dd JN |
962 | struct drm_i915_private *dev_priv = |
963 | container_of(work, struct drm_i915_private, hotplug_work); | |
5ca58282 | 964 | struct drm_device *dev = dev_priv->dev; |
c31c4ba3 | 965 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
966 | struct intel_connector *intel_connector; |
967 | struct intel_encoder *intel_encoder; | |
968 | struct drm_connector *connector; | |
969 | unsigned long irqflags; | |
970 | bool hpd_disabled = false; | |
321a1b30 | 971 | bool changed = false; |
142e2398 | 972 | u32 hpd_event_bits; |
4ef69c7a | 973 | |
52d7eced DV |
974 | /* HPD irq before everything is fully set up. */ |
975 | if (!dev_priv->enable_hotplug_processing) | |
976 | return; | |
977 | ||
a65e34c7 | 978 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
979 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
980 | ||
cd569aed | 981 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
982 | |
983 | hpd_event_bits = dev_priv->hpd_event_bits; | |
984 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
985 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
986 | intel_connector = to_intel_connector(connector); | |
987 | intel_encoder = intel_connector->encoder; | |
988 | if (intel_encoder->hpd_pin > HPD_NONE && | |
989 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
990 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
991 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
992 | "switching from hotplug detection to polling\n", | |
993 | drm_get_connector_name(connector)); | |
994 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
995 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
996 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
997 | hpd_disabled = true; | |
998 | } | |
142e2398 EE |
999 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
1000 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
1001 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
1002 | } | |
cd569aed EE |
1003 | } |
1004 | /* if there were no outputs to poll, poll was disabled, | |
1005 | * therefore make sure it's enabled when disabling HPD on | |
1006 | * some connectors */ | |
ac4c16c5 | 1007 | if (hpd_disabled) { |
cd569aed | 1008 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
1009 | mod_timer(&dev_priv->hotplug_reenable_timer, |
1010 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
1011 | } | |
cd569aed EE |
1012 | |
1013 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1014 | ||
321a1b30 EE |
1015 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
1016 | intel_connector = to_intel_connector(connector); | |
1017 | intel_encoder = intel_connector->encoder; | |
1018 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
1019 | if (intel_encoder->hot_plug) | |
1020 | intel_encoder->hot_plug(intel_encoder); | |
1021 | if (intel_hpd_irq_event(dev, connector)) | |
1022 | changed = true; | |
1023 | } | |
1024 | } | |
40ee3381 KP |
1025 | mutex_unlock(&mode_config->mutex); |
1026 | ||
321a1b30 EE |
1027 | if (changed) |
1028 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
1029 | } |
1030 | ||
3ca1cced VS |
1031 | static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv) |
1032 | { | |
1033 | del_timer_sync(&dev_priv->hotplug_reenable_timer); | |
1034 | } | |
1035 | ||
d0ecd7e2 | 1036 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 1037 | { |
2d1013dd | 1038 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 1039 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 1040 | u8 new_delay; |
9270388e | 1041 | |
d0ecd7e2 | 1042 | spin_lock(&mchdev_lock); |
f97108d1 | 1043 | |
73edd18f DV |
1044 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
1045 | ||
20e4d407 | 1046 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 1047 | |
7648fa99 | 1048 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
1049 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
1050 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
1051 | max_avg = I915_READ(RCBMAXAVG); |
1052 | min_avg = I915_READ(RCBMINAVG); | |
1053 | ||
1054 | /* Handle RCS change request from hw */ | |
b5b72e89 | 1055 | if (busy_up > max_avg) { |
20e4d407 DV |
1056 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
1057 | new_delay = dev_priv->ips.cur_delay - 1; | |
1058 | if (new_delay < dev_priv->ips.max_delay) | |
1059 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 1060 | } else if (busy_down < min_avg) { |
20e4d407 DV |
1061 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
1062 | new_delay = dev_priv->ips.cur_delay + 1; | |
1063 | if (new_delay > dev_priv->ips.min_delay) | |
1064 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
1065 | } |
1066 | ||
7648fa99 | 1067 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 1068 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 1069 | |
d0ecd7e2 | 1070 | spin_unlock(&mchdev_lock); |
9270388e | 1071 | |
f97108d1 JB |
1072 | return; |
1073 | } | |
1074 | ||
549f7365 CW |
1075 | static void notify_ring(struct drm_device *dev, |
1076 | struct intel_ring_buffer *ring) | |
1077 | { | |
475553de CW |
1078 | if (ring->obj == NULL) |
1079 | return; | |
1080 | ||
814e9b57 | 1081 | trace_i915_gem_request_complete(ring); |
9862e600 | 1082 | |
549f7365 | 1083 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 1084 | i915_queue_hangcheck(dev); |
549f7365 CW |
1085 | } |
1086 | ||
4912d041 | 1087 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1088 | { |
2d1013dd JN |
1089 | struct drm_i915_private *dev_priv = |
1090 | container_of(work, struct drm_i915_private, rps.work); | |
edbfdb45 | 1091 | u32 pm_iir; |
dd75fdc8 | 1092 | int new_delay, adj; |
4912d041 | 1093 | |
59cdb63d | 1094 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
1095 | pm_iir = dev_priv->rps.pm_iir; |
1096 | dev_priv->rps.pm_iir = 0; | |
4848405c | 1097 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
a6706b45 | 1098 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
59cdb63d | 1099 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1100 | |
60611c13 | 1101 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1102 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1103 | |
a6706b45 | 1104 | if ((pm_iir & dev_priv->pm_rps_events) == 0) |
3b8d8d91 JB |
1105 | return; |
1106 | ||
4fc688ce | 1107 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1108 | |
dd75fdc8 | 1109 | adj = dev_priv->rps.last_adj; |
7425034a | 1110 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
1111 | if (adj > 0) |
1112 | adj *= 2; | |
1113 | else | |
1114 | adj = 1; | |
b39fb297 | 1115 | new_delay = dev_priv->rps.cur_freq + adj; |
7425034a VS |
1116 | |
1117 | /* | |
1118 | * For better performance, jump directly | |
1119 | * to RPe if we're below it. | |
1120 | */ | |
b39fb297 BW |
1121 | if (new_delay < dev_priv->rps.efficient_freq) |
1122 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1123 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1124 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1125 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1126 | else |
b39fb297 | 1127 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1128 | adj = 0; |
1129 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1130 | if (adj < 0) | |
1131 | adj *= 2; | |
1132 | else | |
1133 | adj = -1; | |
b39fb297 | 1134 | new_delay = dev_priv->rps.cur_freq + adj; |
dd75fdc8 | 1135 | } else { /* unknown event */ |
b39fb297 | 1136 | new_delay = dev_priv->rps.cur_freq; |
dd75fdc8 | 1137 | } |
3b8d8d91 | 1138 | |
79249636 BW |
1139 | /* sysfs frequency interfaces may have snuck in while servicing the |
1140 | * interrupt | |
1141 | */ | |
1272e7b8 | 1142 | new_delay = clamp_t(int, new_delay, |
b39fb297 BW |
1143 | dev_priv->rps.min_freq_softlimit, |
1144 | dev_priv->rps.max_freq_softlimit); | |
27544369 | 1145 | |
b39fb297 | 1146 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; |
dd75fdc8 CW |
1147 | |
1148 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
1149 | valleyview_set_rps(dev_priv->dev, new_delay); | |
1150 | else | |
1151 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 1152 | |
4fc688ce | 1153 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1154 | } |
1155 | ||
e3689190 BW |
1156 | |
1157 | /** | |
1158 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1159 | * occurred. | |
1160 | * @work: workqueue struct | |
1161 | * | |
1162 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1163 | * this event, userspace should try to remap the bad rows since statistically | |
1164 | * it is likely the same row is more likely to go bad again. | |
1165 | */ | |
1166 | static void ivybridge_parity_work(struct work_struct *work) | |
1167 | { | |
2d1013dd JN |
1168 | struct drm_i915_private *dev_priv = |
1169 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1170 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1171 | char *parity_event[6]; |
e3689190 BW |
1172 | uint32_t misccpctl; |
1173 | unsigned long flags; | |
35a85ac6 | 1174 | uint8_t slice = 0; |
e3689190 BW |
1175 | |
1176 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1177 | * In order to prevent a get/put style interface, acquire struct mutex | |
1178 | * any time we access those registers. | |
1179 | */ | |
1180 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1181 | ||
35a85ac6 BW |
1182 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1183 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1184 | goto out; | |
1185 | ||
e3689190 BW |
1186 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1187 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1188 | POSTING_READ(GEN7_MISCCPCTL); | |
1189 | ||
35a85ac6 BW |
1190 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1191 | u32 reg; | |
e3689190 | 1192 | |
35a85ac6 BW |
1193 | slice--; |
1194 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1195 | break; | |
e3689190 | 1196 | |
35a85ac6 | 1197 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1198 | |
35a85ac6 | 1199 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1200 | |
35a85ac6 BW |
1201 | error_status = I915_READ(reg); |
1202 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1203 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1204 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1205 | ||
1206 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1207 | POSTING_READ(reg); | |
1208 | ||
1209 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1210 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1211 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1212 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1213 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1214 | parity_event[5] = NULL; | |
1215 | ||
5bdebb18 | 1216 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1217 | KOBJ_CHANGE, parity_event); |
e3689190 | 1218 | |
35a85ac6 BW |
1219 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1220 | slice, row, bank, subbank); | |
e3689190 | 1221 | |
35a85ac6 BW |
1222 | kfree(parity_event[4]); |
1223 | kfree(parity_event[3]); | |
1224 | kfree(parity_event[2]); | |
1225 | kfree(parity_event[1]); | |
1226 | } | |
e3689190 | 1227 | |
35a85ac6 | 1228 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1229 | |
35a85ac6 BW |
1230 | out: |
1231 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1232 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1233 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1234 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1235 | ||
1236 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1237 | } |
1238 | ||
35a85ac6 | 1239 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1240 | { |
2d1013dd | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1242 | |
040d2baa | 1243 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1244 | return; |
1245 | ||
d0ecd7e2 | 1246 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1247 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1248 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1249 | |
35a85ac6 BW |
1250 | iir &= GT_PARITY_ERROR(dev); |
1251 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1252 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1253 | ||
1254 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1255 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1256 | ||
a4da4fa4 | 1257 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1258 | } |
1259 | ||
f1af8fc1 PZ |
1260 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1261 | struct drm_i915_private *dev_priv, | |
1262 | u32 gt_iir) | |
1263 | { | |
1264 | if (gt_iir & | |
1265 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1266 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1267 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1268 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1269 | } | |
1270 | ||
e7b4c6b1 DV |
1271 | static void snb_gt_irq_handler(struct drm_device *dev, |
1272 | struct drm_i915_private *dev_priv, | |
1273 | u32 gt_iir) | |
1274 | { | |
1275 | ||
cc609d5d BW |
1276 | if (gt_iir & |
1277 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1278 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1279 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1280 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1281 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1282 | notify_ring(dev, &dev_priv->ring[BCS]); |
1283 | ||
cc609d5d BW |
1284 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1285 | GT_BSD_CS_ERROR_INTERRUPT | | |
1286 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
58174462 MK |
1287 | i915_handle_error(dev, false, "GT error interrupt 0x%08x", |
1288 | gt_iir); | |
e7b4c6b1 | 1289 | } |
e3689190 | 1290 | |
35a85ac6 BW |
1291 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1292 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1293 | } |
1294 | ||
abd58f01 BW |
1295 | static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, |
1296 | struct drm_i915_private *dev_priv, | |
1297 | u32 master_ctl) | |
1298 | { | |
1299 | u32 rcs, bcs, vcs; | |
1300 | uint32_t tmp = 0; | |
1301 | irqreturn_t ret = IRQ_NONE; | |
1302 | ||
1303 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
1304 | tmp = I915_READ(GEN8_GT_IIR(0)); | |
1305 | if (tmp) { | |
1306 | ret = IRQ_HANDLED; | |
1307 | rcs = tmp >> GEN8_RCS_IRQ_SHIFT; | |
1308 | bcs = tmp >> GEN8_BCS_IRQ_SHIFT; | |
1309 | if (rcs & GT_RENDER_USER_INTERRUPT) | |
1310 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1311 | if (bcs & GT_RENDER_USER_INTERRUPT) | |
1312 | notify_ring(dev, &dev_priv->ring[BCS]); | |
1313 | I915_WRITE(GEN8_GT_IIR(0), tmp); | |
1314 | } else | |
1315 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1316 | } | |
1317 | ||
1318 | if (master_ctl & GEN8_GT_VCS1_IRQ) { | |
1319 | tmp = I915_READ(GEN8_GT_IIR(1)); | |
1320 | if (tmp) { | |
1321 | ret = IRQ_HANDLED; | |
1322 | vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; | |
1323 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1324 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1325 | I915_WRITE(GEN8_GT_IIR(1), tmp); | |
1326 | } else | |
1327 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); | |
1328 | } | |
1329 | ||
1330 | if (master_ctl & GEN8_GT_VECS_IRQ) { | |
1331 | tmp = I915_READ(GEN8_GT_IIR(3)); | |
1332 | if (tmp) { | |
1333 | ret = IRQ_HANDLED; | |
1334 | vcs = tmp >> GEN8_VECS_IRQ_SHIFT; | |
1335 | if (vcs & GT_RENDER_USER_INTERRUPT) | |
1336 | notify_ring(dev, &dev_priv->ring[VECS]); | |
1337 | I915_WRITE(GEN8_GT_IIR(3), tmp); | |
1338 | } else | |
1339 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1340 | } | |
1341 | ||
1342 | return ret; | |
1343 | } | |
1344 | ||
b543fb04 EE |
1345 | #define HPD_STORM_DETECT_PERIOD 1000 |
1346 | #define HPD_STORM_THRESHOLD 5 | |
1347 | ||
10a504de | 1348 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1349 | u32 hotplug_trigger, |
1350 | const u32 *hpd) | |
b543fb04 | 1351 | { |
2d1013dd | 1352 | struct drm_i915_private *dev_priv = dev->dev_private; |
b543fb04 | 1353 | int i; |
10a504de | 1354 | bool storm_detected = false; |
b543fb04 | 1355 | |
91d131d2 DV |
1356 | if (!hotplug_trigger) |
1357 | return; | |
1358 | ||
cc9bd499 ID |
1359 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
1360 | hotplug_trigger); | |
1361 | ||
b5ea2d56 | 1362 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1363 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1364 | |
3432087e | 1365 | WARN_ONCE(hpd[i] & hotplug_trigger && |
8b5565b8 | 1366 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, |
cba1c073 CW |
1367 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", |
1368 | hotplug_trigger, i, hpd[i]); | |
b8f102e8 | 1369 | |
b543fb04 EE |
1370 | if (!(hpd[i] & hotplug_trigger) || |
1371 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1372 | continue; | |
1373 | ||
bc5ead8c | 1374 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1375 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1376 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1377 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1378 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1379 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1380 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1381 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1382 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1383 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1384 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1385 | storm_detected = true; |
b543fb04 EE |
1386 | } else { |
1387 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1388 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1389 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1390 | } |
1391 | } | |
1392 | ||
10a504de DV |
1393 | if (storm_detected) |
1394 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1395 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1396 | |
645416f5 DV |
1397 | /* |
1398 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1399 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1400 | * queue for otherwise the flush_work in the pageflip code will | |
1401 | * deadlock. | |
1402 | */ | |
1403 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1404 | } |
1405 | ||
515ac2bb DV |
1406 | static void gmbus_irq_handler(struct drm_device *dev) |
1407 | { | |
2d1013dd | 1408 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1409 | |
28c70f16 | 1410 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1411 | } |
1412 | ||
ce99c256 DV |
1413 | static void dp_aux_irq_handler(struct drm_device *dev) |
1414 | { | |
2d1013dd | 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1416 | |
9ee32fea | 1417 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1418 | } |
1419 | ||
8bf1e9f1 | 1420 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1421 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1422 | uint32_t crc0, uint32_t crc1, | |
1423 | uint32_t crc2, uint32_t crc3, | |
1424 | uint32_t crc4) | |
8bf1e9f1 SH |
1425 | { |
1426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1427 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1428 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1429 | int head, tail; |
b2c88f5b | 1430 | |
d538bbdf DL |
1431 | spin_lock(&pipe_crc->lock); |
1432 | ||
0c912c79 | 1433 | if (!pipe_crc->entries) { |
d538bbdf | 1434 | spin_unlock(&pipe_crc->lock); |
0c912c79 DL |
1435 | DRM_ERROR("spurious interrupt\n"); |
1436 | return; | |
1437 | } | |
1438 | ||
d538bbdf DL |
1439 | head = pipe_crc->head; |
1440 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1441 | |
1442 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1443 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1444 | DRM_ERROR("CRC buffer overflowing\n"); |
1445 | return; | |
1446 | } | |
1447 | ||
1448 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1449 | |
8bc5e955 | 1450 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1451 | entry->crc[0] = crc0; |
1452 | entry->crc[1] = crc1; | |
1453 | entry->crc[2] = crc2; | |
1454 | entry->crc[3] = crc3; | |
1455 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1456 | |
1457 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1458 | pipe_crc->head = head; |
1459 | ||
1460 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1461 | |
1462 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1463 | } |
277de95e DV |
1464 | #else |
1465 | static inline void | |
1466 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1467 | uint32_t crc0, uint32_t crc1, | |
1468 | uint32_t crc2, uint32_t crc3, | |
1469 | uint32_t crc4) {} | |
1470 | #endif | |
1471 | ||
eba94eb9 | 1472 | |
277de95e | 1473 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1474 | { |
1475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1476 | ||
277de95e DV |
1477 | display_pipe_crc_irq_handler(dev, pipe, |
1478 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1479 | 0, 0, 0, 0); | |
5a69b89f DV |
1480 | } |
1481 | ||
277de95e | 1482 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1483 | { |
1484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1485 | ||
277de95e DV |
1486 | display_pipe_crc_irq_handler(dev, pipe, |
1487 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1488 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1489 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1490 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1491 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1492 | } |
5b3a856b | 1493 | |
277de95e | 1494 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1495 | { |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1497 | uint32_t res1, res2; |
1498 | ||
1499 | if (INTEL_INFO(dev)->gen >= 3) | |
1500 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1501 | else | |
1502 | res1 = 0; | |
1503 | ||
1504 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1505 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1506 | else | |
1507 | res2 = 0; | |
5b3a856b | 1508 | |
277de95e DV |
1509 | display_pipe_crc_irq_handler(dev, pipe, |
1510 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1511 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1512 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1513 | res1, res2); | |
5b3a856b | 1514 | } |
8bf1e9f1 | 1515 | |
1403c0d4 PZ |
1516 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1517 | * IMR bits until the work is done. Other interrupts can be processed without | |
1518 | * the work queue. */ | |
1519 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1520 | { |
a6706b45 | 1521 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1522 | spin_lock(&dev_priv->irq_lock); |
a6706b45 D |
1523 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; |
1524 | snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); | |
59cdb63d | 1525 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1526 | |
1527 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1528 | } |
baf02a1f | 1529 | |
1403c0d4 PZ |
1530 | if (HAS_VEBOX(dev_priv->dev)) { |
1531 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1532 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1533 | |
1403c0d4 | 1534 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
58174462 MK |
1535 | i915_handle_error(dev_priv->dev, false, |
1536 | "VEBOX CS error interrupt 0x%08x", | |
1537 | pm_iir); | |
1403c0d4 | 1538 | } |
12638c57 | 1539 | } |
baf02a1f BW |
1540 | } |
1541 | ||
c1874ed7 ID |
1542 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1543 | { | |
1544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1545 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1546 | int pipe; |
1547 | ||
58ead0d7 | 1548 | spin_lock(&dev_priv->irq_lock); |
c1874ed7 | 1549 | for_each_pipe(pipe) { |
91d181dd | 1550 | int reg; |
bbb5eebf | 1551 | u32 mask, iir_bit = 0; |
91d181dd | 1552 | |
bbb5eebf DV |
1553 | /* |
1554 | * PIPESTAT bits get signalled even when the interrupt is | |
1555 | * disabled with the mask bits, and some of the status bits do | |
1556 | * not generate interrupts at all (like the underrun bit). Hence | |
1557 | * we need to be careful that we only handle what we want to | |
1558 | * handle. | |
1559 | */ | |
1560 | mask = 0; | |
1561 | if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) | |
1562 | mask |= PIPE_FIFO_UNDERRUN_STATUS; | |
1563 | ||
1564 | switch (pipe) { | |
1565 | case PIPE_A: | |
1566 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1567 | break; | |
1568 | case PIPE_B: | |
1569 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1570 | break; | |
1571 | } | |
1572 | if (iir & iir_bit) | |
1573 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1574 | ||
1575 | if (!mask) | |
91d181dd ID |
1576 | continue; |
1577 | ||
1578 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1579 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1580 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1581 | |
1582 | /* | |
1583 | * Clear the PIPE*STAT regs before the IIR | |
1584 | */ | |
91d181dd ID |
1585 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1586 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1587 | I915_WRITE(reg, pipe_stats[pipe]); |
1588 | } | |
58ead0d7 | 1589 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 ID |
1590 | |
1591 | for_each_pipe(pipe) { | |
1592 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) | |
1593 | drm_handle_vblank(dev, pipe); | |
1594 | ||
579a9b0e | 1595 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1596 | intel_prepare_page_flip(dev, pipe); |
1597 | intel_finish_page_flip(dev, pipe); | |
1598 | } | |
1599 | ||
1600 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1601 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1602 | ||
1603 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
1604 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
1605 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); | |
1606 | } | |
1607 | ||
1608 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1609 | gmbus_irq_handler(dev); | |
1610 | } | |
1611 | ||
ff1f525e | 1612 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1613 | { |
1614 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1615 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1616 | u32 iir, gt_iir, pm_iir; |
1617 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1618 | |
7e231dbe JB |
1619 | while (true) { |
1620 | iir = I915_READ(VLV_IIR); | |
1621 | gt_iir = I915_READ(GTIIR); | |
1622 | pm_iir = I915_READ(GEN6_PMIIR); | |
1623 | ||
1624 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1625 | goto out; | |
1626 | ||
1627 | ret = IRQ_HANDLED; | |
1628 | ||
e7b4c6b1 | 1629 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe | 1630 | |
c1874ed7 | 1631 | valleyview_pipestat_irq_handler(dev, iir); |
31acc7f5 | 1632 | |
7e231dbe JB |
1633 | /* Consume port. Then clear IIR or we'll miss events */ |
1634 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1635 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1636 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe | 1637 | |
91d131d2 DV |
1638 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
1639 | ||
4aeebd74 DV |
1640 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) |
1641 | dp_aux_irq_handler(dev); | |
1642 | ||
7e231dbe JB |
1643 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1644 | I915_READ(PORT_HOTPLUG_STAT); | |
1645 | } | |
1646 | ||
7e231dbe | 1647 | |
60611c13 | 1648 | if (pm_iir) |
d0ecd7e2 | 1649 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1650 | |
1651 | I915_WRITE(GTIIR, gt_iir); | |
1652 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1653 | I915_WRITE(VLV_IIR, iir); | |
1654 | } | |
1655 | ||
1656 | out: | |
1657 | return ret; | |
1658 | } | |
1659 | ||
23e81d69 | 1660 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1661 | { |
2d1013dd | 1662 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1663 | int pipe; |
b543fb04 | 1664 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1665 | |
91d131d2 DV |
1666 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1667 | ||
cfc33bf7 VS |
1668 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1669 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1670 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1671 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1672 | port_name(port)); |
1673 | } | |
776ad806 | 1674 | |
ce99c256 DV |
1675 | if (pch_iir & SDE_AUX_MASK) |
1676 | dp_aux_irq_handler(dev); | |
1677 | ||
776ad806 | 1678 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1679 | gmbus_irq_handler(dev); |
776ad806 JB |
1680 | |
1681 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1682 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1683 | ||
1684 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1685 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1686 | ||
1687 | if (pch_iir & SDE_POISON) | |
1688 | DRM_ERROR("PCH poison interrupt\n"); | |
1689 | ||
9db4a9c7 JB |
1690 | if (pch_iir & SDE_FDI_MASK) |
1691 | for_each_pipe(pipe) | |
1692 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1693 | pipe_name(pipe), | |
1694 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1695 | |
1696 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1697 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1698 | ||
1699 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1700 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1701 | ||
776ad806 | 1702 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1703 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1704 | false)) | |
fc2c807b | 1705 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1706 | |
1707 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1708 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1709 | false)) | |
fc2c807b | 1710 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1711 | } |
1712 | ||
1713 | static void ivb_err_int_handler(struct drm_device *dev) | |
1714 | { | |
1715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1716 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1717 | enum pipe pipe; |
8664281b | 1718 | |
de032bf4 PZ |
1719 | if (err_int & ERR_INT_POISON) |
1720 | DRM_ERROR("Poison interrupt\n"); | |
1721 | ||
5a69b89f DV |
1722 | for_each_pipe(pipe) { |
1723 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { | |
1724 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
1725 | false)) | |
fc2c807b VS |
1726 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1727 | pipe_name(pipe)); | |
5a69b89f | 1728 | } |
8bf1e9f1 | 1729 | |
5a69b89f DV |
1730 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1731 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1732 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1733 | else |
277de95e | 1734 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1735 | } |
1736 | } | |
8bf1e9f1 | 1737 | |
8664281b PZ |
1738 | I915_WRITE(GEN7_ERR_INT, err_int); |
1739 | } | |
1740 | ||
1741 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1742 | { | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | u32 serr_int = I915_READ(SERR_INT); | |
1745 | ||
de032bf4 PZ |
1746 | if (serr_int & SERR_INT_POISON) |
1747 | DRM_ERROR("PCH poison interrupt\n"); | |
1748 | ||
8664281b PZ |
1749 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1750 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1751 | false)) | |
fc2c807b | 1752 | DRM_ERROR("PCH transcoder A FIFO underrun\n"); |
8664281b PZ |
1753 | |
1754 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1755 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1756 | false)) | |
fc2c807b | 1757 | DRM_ERROR("PCH transcoder B FIFO underrun\n"); |
8664281b PZ |
1758 | |
1759 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1760 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1761 | false)) | |
fc2c807b | 1762 | DRM_ERROR("PCH transcoder C FIFO underrun\n"); |
8664281b PZ |
1763 | |
1764 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1765 | } |
1766 | ||
23e81d69 AJ |
1767 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1768 | { | |
2d1013dd | 1769 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1770 | int pipe; |
b543fb04 | 1771 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1772 | |
91d131d2 DV |
1773 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1774 | ||
cfc33bf7 VS |
1775 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1776 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1777 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1778 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1779 | port_name(port)); | |
1780 | } | |
23e81d69 AJ |
1781 | |
1782 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1783 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1784 | |
1785 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1786 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1787 | |
1788 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1789 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1790 | ||
1791 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1792 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1793 | ||
1794 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1795 | for_each_pipe(pipe) | |
1796 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1797 | pipe_name(pipe), | |
1798 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1799 | |
1800 | if (pch_iir & SDE_ERROR_CPT) | |
1801 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1802 | } |
1803 | ||
c008bc6e PZ |
1804 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1805 | { | |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1807 | enum pipe pipe; |
c008bc6e PZ |
1808 | |
1809 | if (de_iir & DE_AUX_CHANNEL_A) | |
1810 | dp_aux_irq_handler(dev); | |
1811 | ||
1812 | if (de_iir & DE_GSE) | |
1813 | intel_opregion_asle_intr(dev); | |
1814 | ||
c008bc6e PZ |
1815 | if (de_iir & DE_POISON) |
1816 | DRM_ERROR("Poison interrupt\n"); | |
1817 | ||
40da17c2 DV |
1818 | for_each_pipe(pipe) { |
1819 | if (de_iir & DE_PIPE_VBLANK(pipe)) | |
1820 | drm_handle_vblank(dev, pipe); | |
5b3a856b | 1821 | |
40da17c2 DV |
1822 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1823 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b VS |
1824 | DRM_ERROR("Pipe %c FIFO underrun\n", |
1825 | pipe_name(pipe)); | |
5b3a856b | 1826 | |
40da17c2 DV |
1827 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
1828 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 1829 | |
40da17c2 DV |
1830 | /* plane/pipes map 1:1 on ilk+ */ |
1831 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
1832 | intel_prepare_page_flip(dev, pipe); | |
1833 | intel_finish_page_flip_plane(dev, pipe); | |
1834 | } | |
c008bc6e PZ |
1835 | } |
1836 | ||
1837 | /* check event from PCH */ | |
1838 | if (de_iir & DE_PCH_EVENT) { | |
1839 | u32 pch_iir = I915_READ(SDEIIR); | |
1840 | ||
1841 | if (HAS_PCH_CPT(dev)) | |
1842 | cpt_irq_handler(dev, pch_iir); | |
1843 | else | |
1844 | ibx_irq_handler(dev, pch_iir); | |
1845 | ||
1846 | /* should clear PCH hotplug event before clear CPU irq */ | |
1847 | I915_WRITE(SDEIIR, pch_iir); | |
1848 | } | |
1849 | ||
1850 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1851 | ironlake_rps_change_irq_handler(dev); | |
1852 | } | |
1853 | ||
9719fb98 PZ |
1854 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1855 | { | |
1856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 1857 | enum pipe pipe; |
9719fb98 PZ |
1858 | |
1859 | if (de_iir & DE_ERR_INT_IVB) | |
1860 | ivb_err_int_handler(dev); | |
1861 | ||
1862 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1863 | dp_aux_irq_handler(dev); | |
1864 | ||
1865 | if (de_iir & DE_GSE_IVB) | |
1866 | intel_opregion_asle_intr(dev); | |
1867 | ||
07d27e20 DL |
1868 | for_each_pipe(pipe) { |
1869 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) | |
1870 | drm_handle_vblank(dev, pipe); | |
40da17c2 DV |
1871 | |
1872 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
1873 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
1874 | intel_prepare_page_flip(dev, pipe); | |
1875 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
1876 | } |
1877 | } | |
1878 | ||
1879 | /* check event from PCH */ | |
1880 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1881 | u32 pch_iir = I915_READ(SDEIIR); | |
1882 | ||
1883 | cpt_irq_handler(dev, pch_iir); | |
1884 | ||
1885 | /* clear PCH hotplug event before clear CPU irq */ | |
1886 | I915_WRITE(SDEIIR, pch_iir); | |
1887 | } | |
1888 | } | |
1889 | ||
f1af8fc1 | 1890 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1891 | { |
1892 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 1893 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 1894 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1895 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 1896 | |
8664281b PZ |
1897 | /* We get interrupts on unclaimed registers, so check for this before we |
1898 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1899 | intel_uncore_check_errors(dev); |
8664281b | 1900 | |
b1f14ad0 JB |
1901 | /* disable master interrupt before clearing iir */ |
1902 | de_ier = I915_READ(DEIER); | |
1903 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1904 | POSTING_READ(DEIER); |
b1f14ad0 | 1905 | |
44498aea PZ |
1906 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1907 | * interrupts will will be stored on its back queue, and then we'll be | |
1908 | * able to process them after we restore SDEIER (as soon as we restore | |
1909 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1910 | * due to its back queue). */ | |
ab5c608b BW |
1911 | if (!HAS_PCH_NOP(dev)) { |
1912 | sde_ier = I915_READ(SDEIER); | |
1913 | I915_WRITE(SDEIER, 0); | |
1914 | POSTING_READ(SDEIER); | |
1915 | } | |
44498aea | 1916 | |
b1f14ad0 | 1917 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1918 | if (gt_iir) { |
d8fc8a47 | 1919 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1920 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1921 | else |
1922 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1923 | I915_WRITE(GTIIR, gt_iir); |
1924 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1925 | } |
1926 | ||
0e43406b CW |
1927 | de_iir = I915_READ(DEIIR); |
1928 | if (de_iir) { | |
f1af8fc1 PZ |
1929 | if (INTEL_INFO(dev)->gen >= 7) |
1930 | ivb_display_irq_handler(dev, de_iir); | |
1931 | else | |
1932 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1933 | I915_WRITE(DEIIR, de_iir); |
1934 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1935 | } |
1936 | ||
f1af8fc1 PZ |
1937 | if (INTEL_INFO(dev)->gen >= 6) { |
1938 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1939 | if (pm_iir) { | |
1403c0d4 | 1940 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1941 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1942 | ret = IRQ_HANDLED; | |
1943 | } | |
0e43406b | 1944 | } |
b1f14ad0 | 1945 | |
b1f14ad0 JB |
1946 | I915_WRITE(DEIER, de_ier); |
1947 | POSTING_READ(DEIER); | |
ab5c608b BW |
1948 | if (!HAS_PCH_NOP(dev)) { |
1949 | I915_WRITE(SDEIER, sde_ier); | |
1950 | POSTING_READ(SDEIER); | |
1951 | } | |
b1f14ad0 JB |
1952 | |
1953 | return ret; | |
1954 | } | |
1955 | ||
abd58f01 BW |
1956 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
1957 | { | |
1958 | struct drm_device *dev = arg; | |
1959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1960 | u32 master_ctl; | |
1961 | irqreturn_t ret = IRQ_NONE; | |
1962 | uint32_t tmp = 0; | |
c42664cc | 1963 | enum pipe pipe; |
abd58f01 | 1964 | |
abd58f01 BW |
1965 | master_ctl = I915_READ(GEN8_MASTER_IRQ); |
1966 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; | |
1967 | if (!master_ctl) | |
1968 | return IRQ_NONE; | |
1969 | ||
1970 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
1971 | POSTING_READ(GEN8_MASTER_IRQ); | |
1972 | ||
1973 | ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); | |
1974 | ||
1975 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
1976 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
1977 | if (tmp & GEN8_DE_MISC_GSE) | |
1978 | intel_opregion_asle_intr(dev); | |
1979 | else if (tmp) | |
1980 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
1981 | else | |
1982 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
1983 | ||
1984 | if (tmp) { | |
1985 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
1986 | ret = IRQ_HANDLED; | |
1987 | } | |
1988 | } | |
1989 | ||
6d766f02 DV |
1990 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
1991 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
1992 | if (tmp & GEN8_AUX_CHANNEL_A) | |
1993 | dp_aux_irq_handler(dev); | |
1994 | else if (tmp) | |
1995 | DRM_ERROR("Unexpected DE Port interrupt\n"); | |
1996 | else | |
1997 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
1998 | ||
1999 | if (tmp) { | |
2000 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); | |
2001 | ret = IRQ_HANDLED; | |
2002 | } | |
2003 | } | |
2004 | ||
c42664cc DV |
2005 | for_each_pipe(pipe) { |
2006 | uint32_t pipe_iir; | |
abd58f01 | 2007 | |
c42664cc DV |
2008 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2009 | continue; | |
abd58f01 | 2010 | |
c42664cc DV |
2011 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
2012 | if (pipe_iir & GEN8_PIPE_VBLANK) | |
2013 | drm_handle_vblank(dev, pipe); | |
abd58f01 | 2014 | |
c42664cc DV |
2015 | if (pipe_iir & GEN8_PIPE_FLIP_DONE) { |
2016 | intel_prepare_page_flip(dev, pipe); | |
2017 | intel_finish_page_flip_plane(dev, pipe); | |
abd58f01 | 2018 | } |
c42664cc | 2019 | |
0fbe7870 DV |
2020 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) |
2021 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2022 | ||
38d83c96 DV |
2023 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { |
2024 | if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, | |
2025 | false)) | |
fc2c807b VS |
2026 | DRM_ERROR("Pipe %c FIFO underrun\n", |
2027 | pipe_name(pipe)); | |
38d83c96 DV |
2028 | } |
2029 | ||
30100f2b DV |
2030 | if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { |
2031 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", | |
2032 | pipe_name(pipe), | |
2033 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
2034 | } | |
c42664cc DV |
2035 | |
2036 | if (pipe_iir) { | |
2037 | ret = IRQ_HANDLED; | |
2038 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
2039 | } else | |
abd58f01 BW |
2040 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2041 | } | |
2042 | ||
92d03a80 DV |
2043 | if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { |
2044 | /* | |
2045 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2046 | * scheme also closed the SDE interrupt handling race we've seen | |
2047 | * on older pch-split platforms. But this needs testing. | |
2048 | */ | |
2049 | u32 pch_iir = I915_READ(SDEIIR); | |
2050 | ||
2051 | cpt_irq_handler(dev, pch_iir); | |
2052 | ||
2053 | if (pch_iir) { | |
2054 | I915_WRITE(SDEIIR, pch_iir); | |
2055 | ret = IRQ_HANDLED; | |
2056 | } | |
2057 | } | |
2058 | ||
abd58f01 BW |
2059 | I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2060 | POSTING_READ(GEN8_MASTER_IRQ); | |
2061 | ||
2062 | return ret; | |
2063 | } | |
2064 | ||
17e1df07 DV |
2065 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2066 | bool reset_completed) | |
2067 | { | |
2068 | struct intel_ring_buffer *ring; | |
2069 | int i; | |
2070 | ||
2071 | /* | |
2072 | * Notify all waiters for GPU completion events that reset state has | |
2073 | * been changed, and that they need to restart their wait after | |
2074 | * checking for potential errors (and bail out to drop locks if there is | |
2075 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2076 | */ | |
2077 | ||
2078 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2079 | for_each_ring(ring, dev_priv, i) | |
2080 | wake_up_all(&ring->irq_queue); | |
2081 | ||
2082 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2083 | wake_up_all(&dev_priv->pending_flip_queue); | |
2084 | ||
2085 | /* | |
2086 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2087 | * reset state is cleared. | |
2088 | */ | |
2089 | if (reset_completed) | |
2090 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2091 | } | |
2092 | ||
8a905236 JB |
2093 | /** |
2094 | * i915_error_work_func - do process context error handling work | |
2095 | * @work: work struct | |
2096 | * | |
2097 | * Fire an error uevent so userspace can see that a hang or error | |
2098 | * was detected. | |
2099 | */ | |
2100 | static void i915_error_work_func(struct work_struct *work) | |
2101 | { | |
1f83fee0 DV |
2102 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
2103 | work); | |
2d1013dd JN |
2104 | struct drm_i915_private *dev_priv = |
2105 | container_of(error, struct drm_i915_private, gpu_error); | |
8a905236 | 2106 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
2107 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2108 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2109 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2110 | int ret; |
8a905236 | 2111 | |
5bdebb18 | 2112 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2113 | |
7db0ba24 DV |
2114 | /* |
2115 | * Note that there's only one work item which does gpu resets, so we | |
2116 | * need not worry about concurrent gpu resets potentially incrementing | |
2117 | * error->reset_counter twice. We only need to take care of another | |
2118 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2119 | * quick check for that is good enough: schedule_work ensures the | |
2120 | * correct ordering between hang detection and this work item, and since | |
2121 | * the reset in-progress bit is only ever set by code outside of this | |
2122 | * work we don't need to worry about any other races. | |
2123 | */ | |
2124 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2125 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2126 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2127 | reset_event); |
1f83fee0 | 2128 | |
17e1df07 DV |
2129 | /* |
2130 | * All state reset _must_ be completed before we update the | |
2131 | * reset counter, for otherwise waiters might miss the reset | |
2132 | * pending state and not properly drop locks, resulting in | |
2133 | * deadlocks with the reset work. | |
2134 | */ | |
f69061be DV |
2135 | ret = i915_reset(dev); |
2136 | ||
17e1df07 DV |
2137 | intel_display_handle_reset(dev); |
2138 | ||
f69061be DV |
2139 | if (ret == 0) { |
2140 | /* | |
2141 | * After all the gem state is reset, increment the reset | |
2142 | * counter and wake up everyone waiting for the reset to | |
2143 | * complete. | |
2144 | * | |
2145 | * Since unlock operations are a one-sided barrier only, | |
2146 | * we need to insert a barrier here to order any seqno | |
2147 | * updates before | |
2148 | * the counter increment. | |
2149 | */ | |
4e857c58 | 2150 | smp_mb__before_atomic(); |
f69061be DV |
2151 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2152 | ||
5bdebb18 | 2153 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2154 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2155 | } else { |
2ac0f450 | 2156 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2157 | } |
1f83fee0 | 2158 | |
17e1df07 DV |
2159 | /* |
2160 | * Note: The wake_up also serves as a memory barrier so that | |
2161 | * waiters see the update value of the reset counter atomic_t. | |
2162 | */ | |
2163 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2164 | } |
8a905236 JB |
2165 | } |
2166 | ||
35aed2e6 | 2167 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2168 | { |
2169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2170 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2171 | u32 eir = I915_READ(EIR); |
050ee91f | 2172 | int pipe, i; |
8a905236 | 2173 | |
35aed2e6 CW |
2174 | if (!eir) |
2175 | return; | |
8a905236 | 2176 | |
a70491cc | 2177 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2178 | |
bd9854f9 BW |
2179 | i915_get_extra_instdone(dev, instdone); |
2180 | ||
8a905236 JB |
2181 | if (IS_G4X(dev)) { |
2182 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2183 | u32 ipeir = I915_READ(IPEIR_I965); | |
2184 | ||
a70491cc JP |
2185 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2186 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2187 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2188 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2189 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2190 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2191 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2192 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2193 | } |
2194 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2195 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2196 | pr_err("page table error\n"); |
2197 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2198 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2199 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2200 | } |
2201 | } | |
2202 | ||
a6c45cf0 | 2203 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2204 | if (eir & I915_ERROR_PAGE_TABLE) { |
2205 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2206 | pr_err("page table error\n"); |
2207 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2208 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2209 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2210 | } |
2211 | } | |
2212 | ||
2213 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2214 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 2215 | for_each_pipe(pipe) |
a70491cc | 2216 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2217 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2218 | /* pipestat has already been acked */ |
2219 | } | |
2220 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2221 | pr_err("instruction error\n"); |
2222 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2223 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2224 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2225 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2226 | u32 ipeir = I915_READ(IPEIR); |
2227 | ||
a70491cc JP |
2228 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2229 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2230 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2231 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2232 | POSTING_READ(IPEIR); |
8a905236 JB |
2233 | } else { |
2234 | u32 ipeir = I915_READ(IPEIR_I965); | |
2235 | ||
a70491cc JP |
2236 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2237 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2238 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2239 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2240 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2241 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2242 | } |
2243 | } | |
2244 | ||
2245 | I915_WRITE(EIR, eir); | |
3143a2bf | 2246 | POSTING_READ(EIR); |
8a905236 JB |
2247 | eir = I915_READ(EIR); |
2248 | if (eir) { | |
2249 | /* | |
2250 | * some errors might have become stuck, | |
2251 | * mask them. | |
2252 | */ | |
2253 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2254 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2255 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2256 | } | |
35aed2e6 CW |
2257 | } |
2258 | ||
2259 | /** | |
2260 | * i915_handle_error - handle an error interrupt | |
2261 | * @dev: drm device | |
2262 | * | |
2263 | * Do some basic checking of regsiter state at error interrupt time and | |
2264 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
2265 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2266 | * so userspace knows something bad happened (should trigger collection | |
2267 | * of a ring dump etc.). | |
2268 | */ | |
58174462 MK |
2269 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2270 | const char *fmt, ...) | |
35aed2e6 CW |
2271 | { |
2272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2273 | va_list args; |
2274 | char error_msg[80]; | |
35aed2e6 | 2275 | |
58174462 MK |
2276 | va_start(args, fmt); |
2277 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2278 | va_end(args); | |
2279 | ||
2280 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2281 | i915_report_and_clear_eir(dev); |
8a905236 | 2282 | |
ba1234d1 | 2283 | if (wedged) { |
f69061be DV |
2284 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2285 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2286 | |
11ed50ec | 2287 | /* |
17e1df07 DV |
2288 | * Wakeup waiting processes so that the reset work function |
2289 | * i915_error_work_func doesn't deadlock trying to grab various | |
2290 | * locks. By bumping the reset counter first, the woken | |
2291 | * processes will see a reset in progress and back off, | |
2292 | * releasing their locks and then wait for the reset completion. | |
2293 | * We must do this for _all_ gpu waiters that might hold locks | |
2294 | * that the reset work needs to acquire. | |
2295 | * | |
2296 | * Note: The wake_up serves as the required memory barrier to | |
2297 | * ensure that the waiters see the updated value of the reset | |
2298 | * counter atomic_t. | |
11ed50ec | 2299 | */ |
17e1df07 | 2300 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2301 | } |
2302 | ||
122f46ba DV |
2303 | /* |
2304 | * Our reset work can grab modeset locks (since it needs to reset the | |
2305 | * state of outstanding pagelips). Hence it must not be run on our own | |
2306 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
2307 | * code will deadlock. | |
2308 | */ | |
2309 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
2310 | } |
2311 | ||
21ad8330 | 2312 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd | 2313 | { |
2d1013dd | 2314 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd SF |
2315 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
2316 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 2317 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
2318 | struct intel_unpin_work *work; |
2319 | unsigned long flags; | |
2320 | bool stall_detected; | |
2321 | ||
2322 | /* Ignore early vblank irqs */ | |
2323 | if (intel_crtc == NULL) | |
2324 | return; | |
2325 | ||
2326 | spin_lock_irqsave(&dev->event_lock, flags); | |
2327 | work = intel_crtc->unpin_work; | |
2328 | ||
e7d841ca CW |
2329 | if (work == NULL || |
2330 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
2331 | !work->enable_stall_check) { | |
4e5359cd SF |
2332 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
2333 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2334 | return; | |
2335 | } | |
2336 | ||
2337 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 2338 | obj = work->pending_flip_obj; |
a6c45cf0 | 2339 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 2340 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 2341 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 2342 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 2343 | } else { |
9db4a9c7 | 2344 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 2345 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
f4510a27 MR |
2346 | crtc->y * crtc->primary->fb->pitches[0] + |
2347 | crtc->x * crtc->primary->fb->bits_per_pixel/8); | |
4e5359cd SF |
2348 | } |
2349 | ||
2350 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2351 | ||
2352 | if (stall_detected) { | |
2353 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
2354 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
2355 | } | |
2356 | } | |
2357 | ||
42f52ef8 KP |
2358 | /* Called from drm generic code, passed 'crtc' which |
2359 | * we use as a pipe index | |
2360 | */ | |
f71d4af4 | 2361 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2362 | { |
2d1013dd | 2363 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2364 | unsigned long irqflags; |
71e0ffa5 | 2365 | |
5eddb70b | 2366 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 2367 | return -EINVAL; |
0a3e67a4 | 2368 | |
1ec14ad3 | 2369 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2370 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2371 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2372 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2373 | else |
7c463586 | 2374 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2375 | PIPE_VBLANK_INTERRUPT_STATUS); |
8692d00e CW |
2376 | |
2377 | /* maintain vblank delivery even in deep C-states */ | |
3d13ef2e | 2378 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2379 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 2380 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2381 | |
0a3e67a4 JB |
2382 | return 0; |
2383 | } | |
2384 | ||
f71d4af4 | 2385 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2386 | { |
2d1013dd | 2387 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2388 | unsigned long irqflags; |
b518421f | 2389 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2390 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2391 | |
2392 | if (!i915_pipe_enabled(dev, pipe)) | |
2393 | return -EINVAL; | |
2394 | ||
2395 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2396 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2397 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2398 | ||
2399 | return 0; | |
2400 | } | |
2401 | ||
7e231dbe JB |
2402 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2403 | { | |
2d1013dd | 2404 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2405 | unsigned long irqflags; |
7e231dbe JB |
2406 | |
2407 | if (!i915_pipe_enabled(dev, pipe)) | |
2408 | return -EINVAL; | |
2409 | ||
2410 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2411 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2412 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2413 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2414 | ||
2415 | return 0; | |
2416 | } | |
2417 | ||
abd58f01 BW |
2418 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2419 | { | |
2420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2421 | unsigned long irqflags; | |
abd58f01 BW |
2422 | |
2423 | if (!i915_pipe_enabled(dev, pipe)) | |
2424 | return -EINVAL; | |
2425 | ||
2426 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2427 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2428 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2429 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2430 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2431 | return 0; | |
2432 | } | |
2433 | ||
42f52ef8 KP |
2434 | /* Called from drm generic code, passed 'crtc' which |
2435 | * we use as a pipe index | |
2436 | */ | |
f71d4af4 | 2437 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2438 | { |
2d1013dd | 2439 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2440 | unsigned long irqflags; |
0a3e67a4 | 2441 | |
1ec14ad3 | 2442 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
3d13ef2e | 2443 | if (INTEL_INFO(dev)->gen == 3) |
6b26c86d | 2444 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2445 | |
f796cf8f | 2446 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2447 | PIPE_VBLANK_INTERRUPT_STATUS | |
2448 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2449 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2450 | } | |
2451 | ||
f71d4af4 | 2452 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2453 | { |
2d1013dd | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2455 | unsigned long irqflags; |
b518421f | 2456 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2457 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2458 | |
2459 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2460 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2461 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2462 | } | |
2463 | ||
7e231dbe JB |
2464 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2465 | { | |
2d1013dd | 2466 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2467 | unsigned long irqflags; |
7e231dbe JB |
2468 | |
2469 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2470 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2471 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2472 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2473 | } | |
2474 | ||
abd58f01 BW |
2475 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2476 | { | |
2477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2478 | unsigned long irqflags; | |
abd58f01 BW |
2479 | |
2480 | if (!i915_pipe_enabled(dev, pipe)) | |
2481 | return; | |
2482 | ||
2483 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7167d7c6 DV |
2484 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2485 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2486 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2487 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2488 | } | |
2489 | ||
893eead0 CW |
2490 | static u32 |
2491 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2492 | { |
893eead0 CW |
2493 | return list_entry(ring->request_list.prev, |
2494 | struct drm_i915_gem_request, list)->seqno; | |
2495 | } | |
2496 | ||
9107e9d2 CW |
2497 | static bool |
2498 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2499 | { | |
2500 | return (list_empty(&ring->request_list) || | |
2501 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2502 | } |
2503 | ||
6274f212 CW |
2504 | static struct intel_ring_buffer * |
2505 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2506 | { |
2507 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d DV |
2508 | u32 cmd, ipehr, head; |
2509 | int i; | |
a24a11e6 CW |
2510 | |
2511 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2512 | if ((ipehr & ~(0x3 << 16)) != | |
2513 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2514 | return NULL; |
a24a11e6 | 2515 | |
88fe429d DV |
2516 | /* |
2517 | * HEAD is likely pointing to the dword after the actual command, | |
2518 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
2519 | * dwords. Note that we don't care about ACTHD here since that might | |
2520 | * point at at batch, and semaphores are always emitted into the | |
2521 | * ringbuffer itself. | |
a24a11e6 | 2522 | */ |
88fe429d DV |
2523 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
2524 | ||
2525 | for (i = 4; i; --i) { | |
2526 | /* | |
2527 | * Be paranoid and presume the hw has gone off into the wild - | |
2528 | * our ring is smaller than what the hardware (and hence | |
2529 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2530 | */ | |
2531 | head &= ring->size - 1; | |
2532 | ||
2533 | /* This here seems to blow up */ | |
2534 | cmd = ioread32(ring->virtual_start + head); | |
a24a11e6 CW |
2535 | if (cmd == ipehr) |
2536 | break; | |
2537 | ||
88fe429d DV |
2538 | head -= 4; |
2539 | } | |
a24a11e6 | 2540 | |
88fe429d DV |
2541 | if (!i) |
2542 | return NULL; | |
a24a11e6 | 2543 | |
88fe429d | 2544 | *seqno = ioread32(ring->virtual_start + head + 4) + 1; |
6274f212 | 2545 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; |
a24a11e6 CW |
2546 | } |
2547 | ||
6274f212 CW |
2548 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2549 | { | |
2550 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2551 | struct intel_ring_buffer *signaller; | |
2552 | u32 seqno, ctl; | |
2553 | ||
2554 | ring->hangcheck.deadlock = true; | |
2555 | ||
2556 | signaller = semaphore_waits_for(ring, &seqno); | |
2557 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2558 | return -1; | |
2559 | ||
2560 | /* cursory check for an unkickable deadlock */ | |
2561 | ctl = I915_READ_CTL(signaller); | |
2562 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2563 | return -1; | |
2564 | ||
2565 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2566 | } | |
2567 | ||
2568 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2569 | { | |
2570 | struct intel_ring_buffer *ring; | |
2571 | int i; | |
2572 | ||
2573 | for_each_ring(ring, dev_priv, i) | |
2574 | ring->hangcheck.deadlock = false; | |
2575 | } | |
2576 | ||
ad8beaea | 2577 | static enum intel_ring_hangcheck_action |
50877445 | 2578 | ring_stuck(struct intel_ring_buffer *ring, u64 acthd) |
1ec14ad3 CW |
2579 | { |
2580 | struct drm_device *dev = ring->dev; | |
2581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2582 | u32 tmp; |
2583 | ||
6274f212 | 2584 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2585 | return HANGCHECK_ACTIVE; |
6274f212 | 2586 | |
9107e9d2 | 2587 | if (IS_GEN2(dev)) |
f2f4d82f | 2588 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2589 | |
2590 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2591 | * If so we can simply poke the RB_WAIT bit | |
2592 | * and break the hang. This should work on | |
2593 | * all but the second generation chipsets. | |
2594 | */ | |
2595 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2596 | if (tmp & RING_WAIT) { |
58174462 MK |
2597 | i915_handle_error(dev, false, |
2598 | "Kicking stuck wait on %s", | |
2599 | ring->name); | |
1ec14ad3 | 2600 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2601 | return HANGCHECK_KICK; |
6274f212 CW |
2602 | } |
2603 | ||
2604 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2605 | switch (semaphore_passed(ring)) { | |
2606 | default: | |
f2f4d82f | 2607 | return HANGCHECK_HUNG; |
6274f212 | 2608 | case 1: |
58174462 MK |
2609 | i915_handle_error(dev, false, |
2610 | "Kicking stuck semaphore on %s", | |
2611 | ring->name); | |
6274f212 | 2612 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2613 | return HANGCHECK_KICK; |
6274f212 | 2614 | case 0: |
f2f4d82f | 2615 | return HANGCHECK_WAIT; |
6274f212 | 2616 | } |
9107e9d2 | 2617 | } |
ed5cbb03 | 2618 | |
f2f4d82f | 2619 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2620 | } |
2621 | ||
f65d9421 BG |
2622 | /** |
2623 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2624 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2625 | * if there are no progress, hangcheck score for that ring is increased. | |
2626 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2627 | * we kick the ring. If we see no progress on three subsequent calls | |
2628 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2629 | */ |
a658b5d2 | 2630 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2631 | { |
2632 | struct drm_device *dev = (struct drm_device *)data; | |
2d1013dd | 2633 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2634 | struct intel_ring_buffer *ring; |
b4519513 | 2635 | int i; |
05407ff8 | 2636 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2637 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2638 | #define BUSY 1 | |
2639 | #define KICK 5 | |
2640 | #define HUNG 20 | |
893eead0 | 2641 | |
d330a953 | 2642 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2643 | return; |
2644 | ||
b4519513 | 2645 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2646 | u64 acthd; |
2647 | u32 seqno; | |
9107e9d2 | 2648 | bool busy = true; |
05407ff8 | 2649 | |
6274f212 CW |
2650 | semaphore_clear_deadlocks(dev_priv); |
2651 | ||
05407ff8 MK |
2652 | seqno = ring->get_seqno(ring, false); |
2653 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2654 | |
9107e9d2 CW |
2655 | if (ring->hangcheck.seqno == seqno) { |
2656 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2657 | ring->hangcheck.action = HANGCHECK_IDLE; |
2658 | ||
9107e9d2 CW |
2659 | if (waitqueue_active(&ring->irq_queue)) { |
2660 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2661 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2662 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2663 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2664 | ring->name); | |
2665 | else | |
2666 | DRM_INFO("Fake missed irq on %s\n", | |
2667 | ring->name); | |
094f9a54 CW |
2668 | wake_up_all(&ring->irq_queue); |
2669 | } | |
2670 | /* Safeguard against driver failure */ | |
2671 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2672 | } else |
2673 | busy = false; | |
05407ff8 | 2674 | } else { |
6274f212 CW |
2675 | /* We always increment the hangcheck score |
2676 | * if the ring is busy and still processing | |
2677 | * the same request, so that no single request | |
2678 | * can run indefinitely (such as a chain of | |
2679 | * batches). The only time we do not increment | |
2680 | * the hangcheck score on this ring, if this | |
2681 | * ring is in a legitimate wait for another | |
2682 | * ring. In that case the waiting ring is a | |
2683 | * victim and we want to be sure we catch the | |
2684 | * right culprit. Then every time we do kick | |
2685 | * the ring, add a small increment to the | |
2686 | * score so that we can catch a batch that is | |
2687 | * being repeatedly kicked and so responsible | |
2688 | * for stalling the machine. | |
2689 | */ | |
ad8beaea MK |
2690 | ring->hangcheck.action = ring_stuck(ring, |
2691 | acthd); | |
2692 | ||
2693 | switch (ring->hangcheck.action) { | |
da661464 | 2694 | case HANGCHECK_IDLE: |
f2f4d82f | 2695 | case HANGCHECK_WAIT: |
6274f212 | 2696 | break; |
f2f4d82f | 2697 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2698 | ring->hangcheck.score += BUSY; |
6274f212 | 2699 | break; |
f2f4d82f | 2700 | case HANGCHECK_KICK: |
ea04cb31 | 2701 | ring->hangcheck.score += KICK; |
6274f212 | 2702 | break; |
f2f4d82f | 2703 | case HANGCHECK_HUNG: |
ea04cb31 | 2704 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2705 | stuck[i] = true; |
2706 | break; | |
2707 | } | |
05407ff8 | 2708 | } |
9107e9d2 | 2709 | } else { |
da661464 MK |
2710 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2711 | ||
9107e9d2 CW |
2712 | /* Gradually reduce the count so that we catch DoS |
2713 | * attempts across multiple batches. | |
2714 | */ | |
2715 | if (ring->hangcheck.score > 0) | |
2716 | ring->hangcheck.score--; | |
d1e61e7f CW |
2717 | } |
2718 | ||
05407ff8 MK |
2719 | ring->hangcheck.seqno = seqno; |
2720 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2721 | busy_count += busy; |
893eead0 | 2722 | } |
b9201c14 | 2723 | |
92cab734 | 2724 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2725 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2726 | DRM_INFO("%s on %s\n", |
2727 | stuck[i] ? "stuck" : "no progress", | |
2728 | ring->name); | |
a43adf07 | 2729 | rings_hung++; |
92cab734 MK |
2730 | } |
2731 | } | |
2732 | ||
05407ff8 | 2733 | if (rings_hung) |
58174462 | 2734 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 2735 | |
05407ff8 MK |
2736 | if (busy_count) |
2737 | /* Reset timer case chip hangs without another request | |
2738 | * being added */ | |
10cd45b6 MK |
2739 | i915_queue_hangcheck(dev); |
2740 | } | |
2741 | ||
2742 | void i915_queue_hangcheck(struct drm_device *dev) | |
2743 | { | |
2744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d330a953 | 2745 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
2746 | return; |
2747 | ||
2748 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2749 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2750 | } |
2751 | ||
91738a95 PZ |
2752 | static void ibx_irq_preinstall(struct drm_device *dev) |
2753 | { | |
2754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2755 | ||
2756 | if (HAS_PCH_NOP(dev)) | |
2757 | return; | |
2758 | ||
2759 | /* south display irq */ | |
2760 | I915_WRITE(SDEIMR, 0xffffffff); | |
2761 | /* | |
2762 | * SDEIER is also touched by the interrupt handler to work around missed | |
2763 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2764 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2765 | * sources here, but then only unmask them as needed with SDEIMR. | |
2766 | */ | |
2767 | I915_WRITE(SDEIER, 0xffffffff); | |
2768 | POSTING_READ(SDEIER); | |
2769 | } | |
2770 | ||
d18ea1b5 DV |
2771 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2772 | { | |
2773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2774 | ||
2775 | /* and GT */ | |
2776 | I915_WRITE(GTIMR, 0xffffffff); | |
2777 | I915_WRITE(GTIER, 0x0); | |
2778 | POSTING_READ(GTIER); | |
2779 | ||
2780 | if (INTEL_INFO(dev)->gen >= 6) { | |
2781 | /* and PM */ | |
2782 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2783 | I915_WRITE(GEN6_PMIER, 0x0); | |
2784 | POSTING_READ(GEN6_PMIER); | |
2785 | } | |
2786 | } | |
2787 | ||
1da177e4 LT |
2788 | /* drm_dma.h hooks |
2789 | */ | |
f71d4af4 | 2790 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d | 2791 | { |
2d1013dd | 2792 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d ZW |
2793 | |
2794 | I915_WRITE(HWSTAM, 0xeffe); | |
bdfcdb63 | 2795 | |
036a4a7d ZW |
2796 | I915_WRITE(DEIMR, 0xffffffff); |
2797 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2798 | POSTING_READ(DEIER); |
036a4a7d | 2799 | |
d18ea1b5 | 2800 | gen5_gt_irq_preinstall(dev); |
c650156a | 2801 | |
91738a95 | 2802 | ibx_irq_preinstall(dev); |
7d99163d BW |
2803 | } |
2804 | ||
7e231dbe JB |
2805 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2806 | { | |
2d1013dd | 2807 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
2808 | int pipe; |
2809 | ||
7e231dbe JB |
2810 | /* VLV magic */ |
2811 | I915_WRITE(VLV_IMR, 0); | |
2812 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2813 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2814 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2815 | ||
7e231dbe JB |
2816 | /* and GT */ |
2817 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2818 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2819 | |
2820 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2821 | |
2822 | I915_WRITE(DPINVGTT, 0xff); | |
2823 | ||
2824 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2825 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2826 | for_each_pipe(pipe) | |
2827 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2828 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2829 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2830 | I915_WRITE(VLV_IER, 0x0); | |
2831 | POSTING_READ(VLV_IER); | |
2832 | } | |
2833 | ||
abd58f01 BW |
2834 | static void gen8_irq_preinstall(struct drm_device *dev) |
2835 | { | |
2836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2837 | int pipe; | |
2838 | ||
abd58f01 BW |
2839 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
2840 | POSTING_READ(GEN8_MASTER_IRQ); | |
2841 | ||
2842 | /* IIR can theoretically queue up two events. Be paranoid */ | |
2843 | #define GEN8_IRQ_INIT_NDX(type, which) do { \ | |
2844 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
2845 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
2846 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
2847 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2848 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
2849 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
2850 | } while (0) | |
2851 | ||
2852 | #define GEN8_IRQ_INIT(type) do { \ | |
2853 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
2854 | POSTING_READ(GEN8_##type##_IMR); \ | |
2855 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
2856 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2857 | POSTING_READ(GEN8_##type##_IIR); \ | |
2858 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
2859 | } while (0) | |
2860 | ||
2861 | GEN8_IRQ_INIT_NDX(GT, 0); | |
2862 | GEN8_IRQ_INIT_NDX(GT, 1); | |
2863 | GEN8_IRQ_INIT_NDX(GT, 2); | |
2864 | GEN8_IRQ_INIT_NDX(GT, 3); | |
2865 | ||
2866 | for_each_pipe(pipe) { | |
2867 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); | |
2868 | } | |
2869 | ||
2870 | GEN8_IRQ_INIT(DE_PORT); | |
2871 | GEN8_IRQ_INIT(DE_MISC); | |
2872 | GEN8_IRQ_INIT(PCU); | |
2873 | #undef GEN8_IRQ_INIT | |
2874 | #undef GEN8_IRQ_INIT_NDX | |
2875 | ||
2876 | POSTING_READ(GEN8_PCU_IIR); | |
09f2344d JB |
2877 | |
2878 | ibx_irq_preinstall(dev); | |
abd58f01 BW |
2879 | } |
2880 | ||
82a28bcf | 2881 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 2882 | { |
2d1013dd | 2883 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf DV |
2884 | struct drm_mode_config *mode_config = &dev->mode_config; |
2885 | struct intel_encoder *intel_encoder; | |
fee884ed | 2886 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2887 | |
2888 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2889 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2890 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2891 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2892 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2893 | } else { |
fee884ed | 2894 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2895 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2896 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2897 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2898 | } |
7fe0b973 | 2899 | |
fee884ed | 2900 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2901 | |
2902 | /* | |
2903 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2904 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2905 | * | |
2906 | * This register is the same on all known PCH chips. | |
2907 | */ | |
7fe0b973 KP |
2908 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2909 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2910 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2911 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2912 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2913 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2914 | } | |
2915 | ||
d46da437 PZ |
2916 | static void ibx_irq_postinstall(struct drm_device *dev) |
2917 | { | |
2d1013dd | 2918 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 2919 | u32 mask; |
e5868a31 | 2920 | |
692a04cf DV |
2921 | if (HAS_PCH_NOP(dev)) |
2922 | return; | |
2923 | ||
8664281b | 2924 | if (HAS_PCH_IBX(dev)) { |
5c673b60 | 2925 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
8664281b | 2926 | } else { |
5c673b60 | 2927 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b PZ |
2928 | |
2929 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2930 | } | |
ab5c608b | 2931 | |
d46da437 PZ |
2932 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2933 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2934 | } |
2935 | ||
0a9a8c91 DV |
2936 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2937 | { | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2939 | u32 pm_irqs, gt_irqs; | |
2940 | ||
2941 | pm_irqs = gt_irqs = 0; | |
2942 | ||
2943 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2944 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2945 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2946 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2947 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2948 | } |
2949 | ||
2950 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2951 | if (IS_GEN5(dev)) { | |
2952 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2953 | ILK_BSD_USER_INTERRUPT; | |
2954 | } else { | |
2955 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2956 | } | |
2957 | ||
2958 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2959 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2960 | I915_WRITE(GTIER, gt_irqs); | |
2961 | POSTING_READ(GTIER); | |
2962 | ||
2963 | if (INTEL_INFO(dev)->gen >= 6) { | |
a6706b45 | 2964 | pm_irqs |= dev_priv->pm_rps_events; |
0a9a8c91 DV |
2965 | |
2966 | if (HAS_VEBOX(dev)) | |
2967 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2968 | ||
605cd25b | 2969 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2970 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2971 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2972 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2973 | POSTING_READ(GEN6_PMIER); | |
2974 | } | |
2975 | } | |
2976 | ||
f71d4af4 | 2977 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2978 | { |
4bc9d430 | 2979 | unsigned long irqflags; |
2d1013dd | 2980 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
2981 | u32 display_mask, extra_mask; |
2982 | ||
2983 | if (INTEL_INFO(dev)->gen >= 7) { | |
2984 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2985 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2986 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 2987 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 2988 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
5c673b60 | 2989 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); |
8e76f8dc PZ |
2990 | |
2991 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2992 | } else { | |
2993 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2994 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 2995 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
2996 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
2997 | DE_POISON); | |
5c673b60 DV |
2998 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
2999 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; | |
8e76f8dc | 3000 | } |
036a4a7d | 3001 | |
1ec14ad3 | 3002 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
3003 | |
3004 | /* should always can generate irq */ | |
3005 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 3006 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 3007 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 3008 | POSTING_READ(DEIER); |
036a4a7d | 3009 | |
0a9a8c91 | 3010 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3011 | |
d46da437 | 3012 | ibx_irq_postinstall(dev); |
7fe0b973 | 3013 | |
f97108d1 | 3014 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3015 | /* Enable PCU event interrupts |
3016 | * | |
3017 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3018 | * setup is guaranteed to run in single-threaded context. But we |
3019 | * need it to make the assert_spin_locked happy. */ | |
3020 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 3021 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 3022 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
3023 | } |
3024 | ||
036a4a7d ZW |
3025 | return 0; |
3026 | } | |
3027 | ||
f8b79e58 ID |
3028 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3029 | { | |
3030 | u32 pipestat_mask; | |
3031 | u32 iir_mask; | |
3032 | ||
3033 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3034 | PIPE_FIFO_UNDERRUN_STATUS; | |
3035 | ||
3036 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3037 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3038 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3039 | ||
3040 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3041 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3042 | ||
3043 | i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3044 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3045 | i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3046 | ||
3047 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3048 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3049 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
3050 | dev_priv->irq_mask &= ~iir_mask; | |
3051 | ||
3052 | I915_WRITE(VLV_IIR, iir_mask); | |
3053 | I915_WRITE(VLV_IIR, iir_mask); | |
3054 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3055 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3056 | POSTING_READ(VLV_IER); | |
3057 | } | |
3058 | ||
3059 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3060 | { | |
3061 | u32 pipestat_mask; | |
3062 | u32 iir_mask; | |
3063 | ||
3064 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3065 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3066 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
f8b79e58 ID |
3067 | |
3068 | dev_priv->irq_mask |= iir_mask; | |
3069 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3070 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3071 | I915_WRITE(VLV_IIR, iir_mask); | |
3072 | I915_WRITE(VLV_IIR, iir_mask); | |
3073 | POSTING_READ(VLV_IIR); | |
3074 | ||
3075 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3076 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3077 | ||
3078 | i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask | | |
3079 | PIPE_GMBUS_INTERRUPT_STATUS); | |
3080 | i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask); | |
3081 | ||
3082 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3083 | PIPE_FIFO_UNDERRUN_STATUS; | |
3084 | I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask); | |
3085 | I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask); | |
3086 | POSTING_READ(PIPESTAT(PIPE_A)); | |
3087 | } | |
3088 | ||
3089 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3090 | { | |
3091 | assert_spin_locked(&dev_priv->irq_lock); | |
3092 | ||
3093 | if (dev_priv->display_irqs_enabled) | |
3094 | return; | |
3095 | ||
3096 | dev_priv->display_irqs_enabled = true; | |
3097 | ||
3098 | if (dev_priv->dev->irq_enabled) | |
3099 | valleyview_display_irqs_install(dev_priv); | |
3100 | } | |
3101 | ||
3102 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3103 | { | |
3104 | assert_spin_locked(&dev_priv->irq_lock); | |
3105 | ||
3106 | if (!dev_priv->display_irqs_enabled) | |
3107 | return; | |
3108 | ||
3109 | dev_priv->display_irqs_enabled = false; | |
3110 | ||
3111 | if (dev_priv->dev->irq_enabled) | |
3112 | valleyview_display_irqs_uninstall(dev_priv); | |
3113 | } | |
3114 | ||
7e231dbe JB |
3115 | static int valleyview_irq_postinstall(struct drm_device *dev) |
3116 | { | |
2d1013dd | 3117 | struct drm_i915_private *dev_priv = dev->dev_private; |
b79480ba | 3118 | unsigned long irqflags; |
7e231dbe | 3119 | |
f8b79e58 | 3120 | dev_priv->irq_mask = ~0; |
7e231dbe | 3121 | |
20afbda2 DV |
3122 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3123 | POSTING_READ(PORT_HOTPLUG_EN); | |
3124 | ||
7e231dbe | 3125 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
f8b79e58 | 3126 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
7e231dbe | 3127 | I915_WRITE(VLV_IIR, 0xffffffff); |
7e231dbe JB |
3128 | POSTING_READ(VLV_IER); |
3129 | ||
b79480ba DV |
3130 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3131 | * just to make the assert_spin_locked check happy. */ | |
3132 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f8b79e58 ID |
3133 | if (dev_priv->display_irqs_enabled) |
3134 | valleyview_display_irqs_install(dev_priv); | |
b79480ba | 3135 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 3136 | |
7e231dbe JB |
3137 | I915_WRITE(VLV_IIR, 0xffffffff); |
3138 | I915_WRITE(VLV_IIR, 0xffffffff); | |
3139 | ||
0a9a8c91 | 3140 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3141 | |
3142 | /* ack & enable invalid PTE error interrupts */ | |
3143 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3144 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3145 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3146 | #endif | |
3147 | ||
3148 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3149 | |
3150 | return 0; | |
3151 | } | |
3152 | ||
abd58f01 BW |
3153 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3154 | { | |
3155 | int i; | |
3156 | ||
3157 | /* These are interrupts we'll toggle with the ring mask register */ | |
3158 | uint32_t gt_interrupts[] = { | |
3159 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
3160 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | | |
3161 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
3162 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | | |
3163 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
3164 | 0, | |
3165 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3166 | }; | |
3167 | ||
3168 | for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { | |
3169 | u32 tmp = I915_READ(GEN8_GT_IIR(i)); | |
3170 | if (tmp) | |
3171 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
3172 | i, tmp); | |
3173 | I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); | |
3174 | I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); | |
3175 | } | |
3176 | POSTING_READ(GEN8_GT_IER(0)); | |
3177 | } | |
3178 | ||
3179 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3180 | { | |
3181 | struct drm_device *dev = dev_priv->dev; | |
13b3a0a7 DV |
3182 | uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | |
3183 | GEN8_PIPE_CDCLK_CRC_DONE | | |
13b3a0a7 | 3184 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; |
5c673b60 DV |
3185 | uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | |
3186 | GEN8_PIPE_FIFO_UNDERRUN; | |
abd58f01 | 3187 | int pipe; |
13b3a0a7 DV |
3188 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3189 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3190 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 BW |
3191 | |
3192 | for_each_pipe(pipe) { | |
3193 | u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); | |
3194 | if (tmp) | |
3195 | DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", | |
3196 | pipe, tmp); | |
3197 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
3198 | I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); | |
3199 | } | |
3200 | POSTING_READ(GEN8_DE_PIPE_ISR(0)); | |
3201 | ||
6d766f02 DV |
3202 | I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); |
3203 | I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); | |
abd58f01 BW |
3204 | POSTING_READ(GEN8_DE_PORT_IER); |
3205 | } | |
3206 | ||
3207 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3208 | { | |
3209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3210 | ||
3211 | gen8_gt_irq_postinstall(dev_priv); | |
3212 | gen8_de_irq_postinstall(dev_priv); | |
3213 | ||
3214 | ibx_irq_postinstall(dev); | |
3215 | ||
3216 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3217 | POSTING_READ(GEN8_MASTER_IRQ); | |
3218 | ||
3219 | return 0; | |
3220 | } | |
3221 | ||
3222 | static void gen8_irq_uninstall(struct drm_device *dev) | |
3223 | { | |
3224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3225 | int pipe; | |
3226 | ||
3227 | if (!dev_priv) | |
3228 | return; | |
3229 | ||
abd58f01 BW |
3230 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3231 | ||
3232 | #define GEN8_IRQ_FINI_NDX(type, which) do { \ | |
3233 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ | |
3234 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
3235 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
3236 | } while (0) | |
3237 | ||
3238 | #define GEN8_IRQ_FINI(type) do { \ | |
3239 | I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ | |
3240 | I915_WRITE(GEN8_##type##_IER, 0); \ | |
3241 | I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ | |
3242 | } while (0) | |
3243 | ||
3244 | GEN8_IRQ_FINI_NDX(GT, 0); | |
3245 | GEN8_IRQ_FINI_NDX(GT, 1); | |
3246 | GEN8_IRQ_FINI_NDX(GT, 2); | |
3247 | GEN8_IRQ_FINI_NDX(GT, 3); | |
3248 | ||
3249 | for_each_pipe(pipe) { | |
3250 | GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); | |
3251 | } | |
3252 | ||
3253 | GEN8_IRQ_FINI(DE_PORT); | |
3254 | GEN8_IRQ_FINI(DE_MISC); | |
3255 | GEN8_IRQ_FINI(PCU); | |
3256 | #undef GEN8_IRQ_FINI | |
3257 | #undef GEN8_IRQ_FINI_NDX | |
3258 | ||
3259 | POSTING_READ(GEN8_PCU_IIR); | |
3260 | } | |
3261 | ||
7e231dbe JB |
3262 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3263 | { | |
2d1013dd | 3264 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8b79e58 | 3265 | unsigned long irqflags; |
7e231dbe JB |
3266 | int pipe; |
3267 | ||
3268 | if (!dev_priv) | |
3269 | return; | |
3270 | ||
3ca1cced | 3271 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3272 | |
7e231dbe JB |
3273 | for_each_pipe(pipe) |
3274 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3275 | ||
3276 | I915_WRITE(HWSTAM, 0xffffffff); | |
3277 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3278 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
f8b79e58 ID |
3279 | |
3280 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3281 | if (dev_priv->display_irqs_enabled) | |
3282 | valleyview_display_irqs_uninstall(dev_priv); | |
3283 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3284 | ||
3285 | dev_priv->irq_mask = 0; | |
3286 | ||
7e231dbe JB |
3287 | I915_WRITE(VLV_IIR, 0xffffffff); |
3288 | I915_WRITE(VLV_IMR, 0xffffffff); | |
3289 | I915_WRITE(VLV_IER, 0x0); | |
3290 | POSTING_READ(VLV_IER); | |
3291 | } | |
3292 | ||
f71d4af4 | 3293 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3294 | { |
2d1013dd | 3295 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3296 | |
3297 | if (!dev_priv) | |
3298 | return; | |
3299 | ||
3ca1cced | 3300 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3301 | |
036a4a7d ZW |
3302 | I915_WRITE(HWSTAM, 0xffffffff); |
3303 | ||
3304 | I915_WRITE(DEIMR, 0xffffffff); | |
3305 | I915_WRITE(DEIER, 0x0); | |
3306 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
3307 | if (IS_GEN7(dev)) |
3308 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
3309 | |
3310 | I915_WRITE(GTIMR, 0xffffffff); | |
3311 | I915_WRITE(GTIER, 0x0); | |
3312 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 3313 | |
ab5c608b BW |
3314 | if (HAS_PCH_NOP(dev)) |
3315 | return; | |
3316 | ||
192aac1f KP |
3317 | I915_WRITE(SDEIMR, 0xffffffff); |
3318 | I915_WRITE(SDEIER, 0x0); | |
3319 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
3320 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
3321 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
3322 | } |
3323 | ||
a266c7d5 | 3324 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3325 | { |
2d1013dd | 3326 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3327 | int pipe; |
91e3738e | 3328 | |
9db4a9c7 JB |
3329 | for_each_pipe(pipe) |
3330 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
3331 | I915_WRITE16(IMR, 0xffff); |
3332 | I915_WRITE16(IER, 0x0); | |
3333 | POSTING_READ16(IER); | |
c2798b19 CW |
3334 | } |
3335 | ||
3336 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3337 | { | |
2d1013dd | 3338 | struct drm_i915_private *dev_priv = dev->dev_private; |
379ef82d | 3339 | unsigned long irqflags; |
c2798b19 | 3340 | |
c2798b19 CW |
3341 | I915_WRITE16(EMR, |
3342 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3343 | ||
3344 | /* Unmask the interrupts that we always want on. */ | |
3345 | dev_priv->irq_mask = | |
3346 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3347 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3348 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3349 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3350 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3351 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
3352 | ||
3353 | I915_WRITE16(IER, | |
3354 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3355 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3356 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3357 | I915_USER_INTERRUPT); | |
3358 | POSTING_READ16(IER); | |
3359 | ||
379ef82d DV |
3360 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3361 | * just to make the assert_spin_locked check happy. */ | |
3362 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3363 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3364 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3365 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3366 | ||
c2798b19 CW |
3367 | return 0; |
3368 | } | |
3369 | ||
90a72f87 VS |
3370 | /* |
3371 | * Returns true when a page flip has completed. | |
3372 | */ | |
3373 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3374 | int plane, int pipe, u32 iir) |
90a72f87 | 3375 | { |
2d1013dd | 3376 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3377 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 VS |
3378 | |
3379 | if (!drm_handle_vblank(dev, pipe)) | |
3380 | return false; | |
3381 | ||
3382 | if ((iir & flip_pending) == 0) | |
3383 | return false; | |
3384 | ||
1f1c2e24 | 3385 | intel_prepare_page_flip(dev, plane); |
90a72f87 VS |
3386 | |
3387 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3388 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3389 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3390 | * the flip is completed (no longer pending). Since this doesn't raise | |
3391 | * an interrupt per se, we watch for the change at vblank. | |
3392 | */ | |
3393 | if (I915_READ16(ISR) & flip_pending) | |
3394 | return false; | |
3395 | ||
3396 | intel_finish_page_flip(dev, pipe); | |
3397 | ||
3398 | return true; | |
3399 | } | |
3400 | ||
ff1f525e | 3401 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
3402 | { |
3403 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3404 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3405 | u16 iir, new_iir; |
3406 | u32 pipe_stats[2]; | |
3407 | unsigned long irqflags; | |
c2798b19 CW |
3408 | int pipe; |
3409 | u16 flip_mask = | |
3410 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3411 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3412 | ||
c2798b19 CW |
3413 | iir = I915_READ16(IIR); |
3414 | if (iir == 0) | |
3415 | return IRQ_NONE; | |
3416 | ||
3417 | while (iir & ~flip_mask) { | |
3418 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3419 | * have been cleared after the pipestat interrupt was received. | |
3420 | * It doesn't set the bit in iir again, but it still produces | |
3421 | * interrupts (for non-MSI). | |
3422 | */ | |
3423 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3424 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3425 | i915_handle_error(dev, false, |
3426 | "Command parser error, iir 0x%08x", | |
3427 | iir); | |
c2798b19 CW |
3428 | |
3429 | for_each_pipe(pipe) { | |
3430 | int reg = PIPESTAT(pipe); | |
3431 | pipe_stats[pipe] = I915_READ(reg); | |
3432 | ||
3433 | /* | |
3434 | * Clear the PIPE*STAT regs before the IIR | |
3435 | */ | |
2d9d2b0b | 3436 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3437 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 CW |
3438 | } |
3439 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3440 | ||
3441 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3442 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3443 | ||
d05c617e | 3444 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
3445 | |
3446 | if (iir & I915_USER_INTERRUPT) | |
3447 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3448 | ||
4356d586 | 3449 | for_each_pipe(pipe) { |
1f1c2e24 | 3450 | int plane = pipe; |
3a77c4c4 | 3451 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3452 | plane = !plane; |
3453 | ||
4356d586 | 3454 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3455 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3456 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3457 | |
4356d586 | 3458 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3459 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3460 | |
3461 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3462 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3463 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
4356d586 | 3464 | } |
c2798b19 CW |
3465 | |
3466 | iir = new_iir; | |
3467 | } | |
3468 | ||
3469 | return IRQ_HANDLED; | |
3470 | } | |
3471 | ||
3472 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3473 | { | |
2d1013dd | 3474 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3475 | int pipe; |
3476 | ||
c2798b19 CW |
3477 | for_each_pipe(pipe) { |
3478 | /* Clear enable bits; then clear status bits */ | |
3479 | I915_WRITE(PIPESTAT(pipe), 0); | |
3480 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3481 | } | |
3482 | I915_WRITE16(IMR, 0xffff); | |
3483 | I915_WRITE16(IER, 0x0); | |
3484 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3485 | } | |
3486 | ||
a266c7d5 CW |
3487 | static void i915_irq_preinstall(struct drm_device * dev) |
3488 | { | |
2d1013dd | 3489 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3490 | int pipe; |
3491 | ||
a266c7d5 CW |
3492 | if (I915_HAS_HOTPLUG(dev)) { |
3493 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3494 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3495 | } | |
3496 | ||
00d98ebd | 3497 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
3498 | for_each_pipe(pipe) |
3499 | I915_WRITE(PIPESTAT(pipe), 0); | |
3500 | I915_WRITE(IMR, 0xffffffff); | |
3501 | I915_WRITE(IER, 0x0); | |
3502 | POSTING_READ(IER); | |
3503 | } | |
3504 | ||
3505 | static int i915_irq_postinstall(struct drm_device *dev) | |
3506 | { | |
2d1013dd | 3507 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3508 | u32 enable_mask; |
379ef82d | 3509 | unsigned long irqflags; |
a266c7d5 | 3510 | |
38bde180 CW |
3511 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3512 | ||
3513 | /* Unmask the interrupts that we always want on. */ | |
3514 | dev_priv->irq_mask = | |
3515 | ~(I915_ASLE_INTERRUPT | | |
3516 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3517 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3518 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3519 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3520 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3521 | ||
3522 | enable_mask = | |
3523 | I915_ASLE_INTERRUPT | | |
3524 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3525 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3526 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
3527 | I915_USER_INTERRUPT; | |
3528 | ||
a266c7d5 | 3529 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
3530 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3531 | POSTING_READ(PORT_HOTPLUG_EN); | |
3532 | ||
a266c7d5 CW |
3533 | /* Enable in IER... */ |
3534 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3535 | /* and unmask in IMR */ | |
3536 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3537 | } | |
3538 | ||
a266c7d5 CW |
3539 | I915_WRITE(IMR, dev_priv->irq_mask); |
3540 | I915_WRITE(IER, enable_mask); | |
3541 | POSTING_READ(IER); | |
3542 | ||
f49e38dd | 3543 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3544 | |
379ef82d DV |
3545 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3546 | * just to make the assert_spin_locked check happy. */ | |
3547 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3548 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3549 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
379ef82d DV |
3550 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
3551 | ||
20afbda2 DV |
3552 | return 0; |
3553 | } | |
3554 | ||
90a72f87 VS |
3555 | /* |
3556 | * Returns true when a page flip has completed. | |
3557 | */ | |
3558 | static bool i915_handle_vblank(struct drm_device *dev, | |
3559 | int plane, int pipe, u32 iir) | |
3560 | { | |
2d1013dd | 3561 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3562 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3563 | ||
3564 | if (!drm_handle_vblank(dev, pipe)) | |
3565 | return false; | |
3566 | ||
3567 | if ((iir & flip_pending) == 0) | |
3568 | return false; | |
3569 | ||
3570 | intel_prepare_page_flip(dev, plane); | |
3571 | ||
3572 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
3573 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3574 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3575 | * the flip is completed (no longer pending). Since this doesn't raise | |
3576 | * an interrupt per se, we watch for the change at vblank. | |
3577 | */ | |
3578 | if (I915_READ(ISR) & flip_pending) | |
3579 | return false; | |
3580 | ||
3581 | intel_finish_page_flip(dev, pipe); | |
3582 | ||
3583 | return true; | |
3584 | } | |
3585 | ||
ff1f525e | 3586 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3587 | { |
3588 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3589 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3590 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 3591 | unsigned long irqflags; |
38bde180 CW |
3592 | u32 flip_mask = |
3593 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3594 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3595 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3596 | |
a266c7d5 | 3597 | iir = I915_READ(IIR); |
38bde180 CW |
3598 | do { |
3599 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3600 | bool blc_event = false; |
a266c7d5 CW |
3601 | |
3602 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3603 | * have been cleared after the pipestat interrupt was received. | |
3604 | * It doesn't set the bit in iir again, but it still produces | |
3605 | * interrupts (for non-MSI). | |
3606 | */ | |
3607 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3608 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3609 | i915_handle_error(dev, false, |
3610 | "Command parser error, iir 0x%08x", | |
3611 | iir); | |
a266c7d5 CW |
3612 | |
3613 | for_each_pipe(pipe) { | |
3614 | int reg = PIPESTAT(pipe); | |
3615 | pipe_stats[pipe] = I915_READ(reg); | |
3616 | ||
38bde180 | 3617 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 3618 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 3619 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 3620 | irq_received = true; |
a266c7d5 CW |
3621 | } |
3622 | } | |
3623 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3624 | ||
3625 | if (!irq_received) | |
3626 | break; | |
3627 | ||
a266c7d5 CW |
3628 | /* Consume port. Then clear IIR or we'll miss events */ |
3629 | if ((I915_HAS_HOTPLUG(dev)) && | |
3630 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
3631 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 3632 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 | 3633 | |
91d131d2 DV |
3634 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); |
3635 | ||
a266c7d5 | 3636 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 3637 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
3638 | } |
3639 | ||
38bde180 | 3640 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3641 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3642 | ||
a266c7d5 CW |
3643 | if (iir & I915_USER_INTERRUPT) |
3644 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 3645 | |
a266c7d5 | 3646 | for_each_pipe(pipe) { |
38bde180 | 3647 | int plane = pipe; |
3a77c4c4 | 3648 | if (HAS_FBC(dev)) |
38bde180 | 3649 | plane = !plane; |
90a72f87 | 3650 | |
8291ee90 | 3651 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3652 | i915_handle_vblank(dev, plane, pipe, iir)) |
3653 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
3654 | |
3655 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3656 | blc_event = true; | |
4356d586 DV |
3657 | |
3658 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3659 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b VS |
3660 | |
3661 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && | |
3662 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3663 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
a266c7d5 CW |
3664 | } |
3665 | ||
a266c7d5 CW |
3666 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
3667 | intel_opregion_asle_intr(dev); | |
3668 | ||
3669 | /* With MSI, interrupts are only generated when iir | |
3670 | * transitions from zero to nonzero. If another bit got | |
3671 | * set while we were handling the existing iir bits, then | |
3672 | * we would never get another interrupt. | |
3673 | * | |
3674 | * This is fine on non-MSI as well, as if we hit this path | |
3675 | * we avoid exiting the interrupt handler only to generate | |
3676 | * another one. | |
3677 | * | |
3678 | * Note that for MSI this could cause a stray interrupt report | |
3679 | * if an interrupt landed in the time between writing IIR and | |
3680 | * the posting read. This should be rare enough to never | |
3681 | * trigger the 99% of 100,000 interrupts test for disabling | |
3682 | * stray interrupts. | |
3683 | */ | |
38bde180 | 3684 | ret = IRQ_HANDLED; |
a266c7d5 | 3685 | iir = new_iir; |
38bde180 | 3686 | } while (iir & ~flip_mask); |
a266c7d5 | 3687 | |
d05c617e | 3688 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 3689 | |
a266c7d5 CW |
3690 | return ret; |
3691 | } | |
3692 | ||
3693 | static void i915_irq_uninstall(struct drm_device * dev) | |
3694 | { | |
2d1013dd | 3695 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3696 | int pipe; |
3697 | ||
3ca1cced | 3698 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3699 | |
a266c7d5 CW |
3700 | if (I915_HAS_HOTPLUG(dev)) { |
3701 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3702 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3703 | } | |
3704 | ||
00d98ebd | 3705 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3706 | for_each_pipe(pipe) { |
3707 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3708 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3709 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3710 | } | |
a266c7d5 CW |
3711 | I915_WRITE(IMR, 0xffffffff); |
3712 | I915_WRITE(IER, 0x0); | |
3713 | ||
a266c7d5 CW |
3714 | I915_WRITE(IIR, I915_READ(IIR)); |
3715 | } | |
3716 | ||
3717 | static void i965_irq_preinstall(struct drm_device * dev) | |
3718 | { | |
2d1013dd | 3719 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3720 | int pipe; |
3721 | ||
adca4730 CW |
3722 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3723 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3724 | |
3725 | I915_WRITE(HWSTAM, 0xeffe); | |
3726 | for_each_pipe(pipe) | |
3727 | I915_WRITE(PIPESTAT(pipe), 0); | |
3728 | I915_WRITE(IMR, 0xffffffff); | |
3729 | I915_WRITE(IER, 0x0); | |
3730 | POSTING_READ(IER); | |
3731 | } | |
3732 | ||
3733 | static int i965_irq_postinstall(struct drm_device *dev) | |
3734 | { | |
2d1013dd | 3735 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 3736 | u32 enable_mask; |
a266c7d5 | 3737 | u32 error_mask; |
b79480ba | 3738 | unsigned long irqflags; |
a266c7d5 | 3739 | |
a266c7d5 | 3740 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3741 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3742 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3743 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3744 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3745 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3746 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3747 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3748 | ||
3749 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3750 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3751 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3752 | enable_mask |= I915_USER_INTERRUPT; |
3753 | ||
3754 | if (IS_G4X(dev)) | |
3755 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3756 | |
b79480ba DV |
3757 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3758 | * just to make the assert_spin_locked check happy. */ | |
3759 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
755e9019 ID |
3760 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3761 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
3762 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
b79480ba | 3763 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3764 | |
a266c7d5 CW |
3765 | /* |
3766 | * Enable some error detection, note the instruction error mask | |
3767 | * bit is reserved, so we leave it masked. | |
3768 | */ | |
3769 | if (IS_G4X(dev)) { | |
3770 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3771 | GM45_ERROR_MEM_PRIV | | |
3772 | GM45_ERROR_CP_PRIV | | |
3773 | I915_ERROR_MEMORY_REFRESH); | |
3774 | } else { | |
3775 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3776 | I915_ERROR_MEMORY_REFRESH); | |
3777 | } | |
3778 | I915_WRITE(EMR, error_mask); | |
3779 | ||
3780 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3781 | I915_WRITE(IER, enable_mask); | |
3782 | POSTING_READ(IER); | |
3783 | ||
20afbda2 DV |
3784 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3785 | POSTING_READ(PORT_HOTPLUG_EN); | |
3786 | ||
f49e38dd | 3787 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3788 | |
3789 | return 0; | |
3790 | } | |
3791 | ||
bac56d5b | 3792 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 3793 | { |
2d1013dd | 3794 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5868a31 | 3795 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3796 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3797 | u32 hotplug_en; |
3798 | ||
b5ea2d56 DV |
3799 | assert_spin_locked(&dev_priv->irq_lock); |
3800 | ||
bac56d5b EE |
3801 | if (I915_HAS_HOTPLUG(dev)) { |
3802 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3803 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3804 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3805 | /* enable bits are the same for all generations */ |
cd569aed EE |
3806 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3807 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3808 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3809 | /* Programming the CRT detection parameters tends |
3810 | to generate a spurious hotplug event about three | |
3811 | seconds later. So just do it once. | |
3812 | */ | |
3813 | if (IS_G4X(dev)) | |
3814 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3815 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3816 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3817 | |
bac56d5b EE |
3818 | /* Ignore TV since it's buggy */ |
3819 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3820 | } | |
a266c7d5 CW |
3821 | } |
3822 | ||
ff1f525e | 3823 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3824 | { |
3825 | struct drm_device *dev = (struct drm_device *) arg; | |
2d1013dd | 3826 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3827 | u32 iir, new_iir; |
3828 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 3829 | unsigned long irqflags; |
a266c7d5 | 3830 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
3831 | u32 flip_mask = |
3832 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3833 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 3834 | |
a266c7d5 CW |
3835 | iir = I915_READ(IIR); |
3836 | ||
a266c7d5 | 3837 | for (;;) { |
501e01d7 | 3838 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
3839 | bool blc_event = false; |
3840 | ||
a266c7d5 CW |
3841 | /* Can't rely on pipestat interrupt bit in iir as it might |
3842 | * have been cleared after the pipestat interrupt was received. | |
3843 | * It doesn't set the bit in iir again, but it still produces | |
3844 | * interrupts (for non-MSI). | |
3845 | */ | |
3846 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3847 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
58174462 MK |
3848 | i915_handle_error(dev, false, |
3849 | "Command parser error, iir 0x%08x", | |
3850 | iir); | |
a266c7d5 CW |
3851 | |
3852 | for_each_pipe(pipe) { | |
3853 | int reg = PIPESTAT(pipe); | |
3854 | pipe_stats[pipe] = I915_READ(reg); | |
3855 | ||
3856 | /* | |
3857 | * Clear the PIPE*STAT regs before the IIR | |
3858 | */ | |
3859 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 3860 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 3861 | irq_received = true; |
a266c7d5 CW |
3862 | } |
3863 | } | |
3864 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3865 | ||
3866 | if (!irq_received) | |
3867 | break; | |
3868 | ||
3869 | ret = IRQ_HANDLED; | |
3870 | ||
3871 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3872 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3873 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3874 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3875 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3876 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 | 3877 | |
91d131d2 | 3878 | intel_hpd_irq_handler(dev, hotplug_trigger, |
704cfb87 | 3879 | IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); |
91d131d2 | 3880 | |
4aeebd74 DV |
3881 | if (IS_G4X(dev) && |
3882 | (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) | |
3883 | dp_aux_irq_handler(dev); | |
3884 | ||
a266c7d5 CW |
3885 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3886 | I915_READ(PORT_HOTPLUG_STAT); | |
3887 | } | |
3888 | ||
21ad8330 | 3889 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3890 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3891 | ||
a266c7d5 CW |
3892 | if (iir & I915_USER_INTERRUPT) |
3893 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3894 | if (iir & I915_BSD_USER_INTERRUPT) | |
3895 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3896 | ||
a266c7d5 | 3897 | for_each_pipe(pipe) { |
2c8ba29f | 3898 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3899 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3900 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3901 | |
3902 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3903 | blc_event = true; | |
4356d586 DV |
3904 | |
3905 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 3906 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 3907 | |
2d9d2b0b VS |
3908 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && |
3909 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) | |
fc2c807b | 3910 | DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); |
2d9d2b0b | 3911 | } |
a266c7d5 CW |
3912 | |
3913 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3914 | intel_opregion_asle_intr(dev); | |
3915 | ||
515ac2bb DV |
3916 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3917 | gmbus_irq_handler(dev); | |
3918 | ||
a266c7d5 CW |
3919 | /* With MSI, interrupts are only generated when iir |
3920 | * transitions from zero to nonzero. If another bit got | |
3921 | * set while we were handling the existing iir bits, then | |
3922 | * we would never get another interrupt. | |
3923 | * | |
3924 | * This is fine on non-MSI as well, as if we hit this path | |
3925 | * we avoid exiting the interrupt handler only to generate | |
3926 | * another one. | |
3927 | * | |
3928 | * Note that for MSI this could cause a stray interrupt report | |
3929 | * if an interrupt landed in the time between writing IIR and | |
3930 | * the posting read. This should be rare enough to never | |
3931 | * trigger the 99% of 100,000 interrupts test for disabling | |
3932 | * stray interrupts. | |
3933 | */ | |
3934 | iir = new_iir; | |
3935 | } | |
3936 | ||
d05c617e | 3937 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3938 | |
a266c7d5 CW |
3939 | return ret; |
3940 | } | |
3941 | ||
3942 | static void i965_irq_uninstall(struct drm_device * dev) | |
3943 | { | |
2d1013dd | 3944 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3945 | int pipe; |
3946 | ||
3947 | if (!dev_priv) | |
3948 | return; | |
3949 | ||
3ca1cced | 3950 | intel_hpd_irq_uninstall(dev_priv); |
ac4c16c5 | 3951 | |
adca4730 CW |
3952 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3953 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3954 | |
3955 | I915_WRITE(HWSTAM, 0xffffffff); | |
3956 | for_each_pipe(pipe) | |
3957 | I915_WRITE(PIPESTAT(pipe), 0); | |
3958 | I915_WRITE(IMR, 0xffffffff); | |
3959 | I915_WRITE(IER, 0x0); | |
3960 | ||
3961 | for_each_pipe(pipe) | |
3962 | I915_WRITE(PIPESTAT(pipe), | |
3963 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3964 | I915_WRITE(IIR, I915_READ(IIR)); | |
3965 | } | |
3966 | ||
3ca1cced | 3967 | static void intel_hpd_irq_reenable(unsigned long data) |
ac4c16c5 | 3968 | { |
2d1013dd | 3969 | struct drm_i915_private *dev_priv = (struct drm_i915_private *)data; |
ac4c16c5 EE |
3970 | struct drm_device *dev = dev_priv->dev; |
3971 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3972 | unsigned long irqflags; | |
3973 | int i; | |
3974 | ||
3975 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3976 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3977 | struct drm_connector *connector; | |
3978 | ||
3979 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3980 | continue; | |
3981 | ||
3982 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3983 | ||
3984 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3985 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3986 | ||
3987 | if (intel_connector->encoder->hpd_pin == i) { | |
3988 | if (connector->polled != intel_connector->polled) | |
3989 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3990 | drm_get_connector_name(connector)); | |
3991 | connector->polled = intel_connector->polled; | |
3992 | if (!connector->polled) | |
3993 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3994 | } | |
3995 | } | |
3996 | } | |
3997 | if (dev_priv->display.hpd_irq_setup) | |
3998 | dev_priv->display.hpd_irq_setup(dev); | |
3999 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4000 | } | |
4001 | ||
f71d4af4 JB |
4002 | void intel_irq_init(struct drm_device *dev) |
4003 | { | |
8b2e326d CW |
4004 | struct drm_i915_private *dev_priv = dev->dev_private; |
4005 | ||
4006 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 4007 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 4008 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4009 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4010 | |
a6706b45 D |
4011 | /* Let's track the enabled rps events */ |
4012 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
4013 | ||
99584db3 DV |
4014 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
4015 | i915_hangcheck_elapsed, | |
61bac78e | 4016 | (unsigned long) dev); |
3ca1cced | 4017 | setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable, |
ac4c16c5 | 4018 | (unsigned long) dev_priv); |
61bac78e | 4019 | |
97a19a24 | 4020 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4021 | |
4cdb83ec VS |
4022 | if (IS_GEN2(dev)) { |
4023 | dev->max_vblank_count = 0; | |
4024 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
4025 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
4026 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4027 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4028 | } else { |
4029 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4030 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4031 | } |
4032 | ||
c2baf4b7 | 4033 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 4034 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
4035 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
4036 | } | |
f71d4af4 | 4037 | |
7e231dbe JB |
4038 | if (IS_VALLEYVIEW(dev)) { |
4039 | dev->driver->irq_handler = valleyview_irq_handler; | |
4040 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4041 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4042 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4043 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4044 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4045 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
abd58f01 BW |
4046 | } else if (IS_GEN8(dev)) { |
4047 | dev->driver->irq_handler = gen8_irq_handler; | |
4048 | dev->driver->irq_preinstall = gen8_irq_preinstall; | |
4049 | dev->driver->irq_postinstall = gen8_irq_postinstall; | |
4050 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4051 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4052 | dev->driver->disable_vblank = gen8_disable_vblank; | |
4053 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; | |
f71d4af4 JB |
4054 | } else if (HAS_PCH_SPLIT(dev)) { |
4055 | dev->driver->irq_handler = ironlake_irq_handler; | |
4056 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
4057 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
4058 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4059 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4060 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 4061 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 4062 | } else { |
c2798b19 CW |
4063 | if (INTEL_INFO(dev)->gen == 2) { |
4064 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
4065 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4066 | dev->driver->irq_handler = i8xx_irq_handler; | |
4067 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
4068 | } else if (INTEL_INFO(dev)->gen == 3) { |
4069 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
4070 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4071 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4072 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 4073 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4074 | } else { |
a266c7d5 CW |
4075 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4076 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4077 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4078 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 4079 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 4080 | } |
f71d4af4 JB |
4081 | dev->driver->enable_vblank = i915_enable_vblank; |
4082 | dev->driver->disable_vblank = i915_disable_vblank; | |
4083 | } | |
4084 | } | |
20afbda2 DV |
4085 | |
4086 | void intel_hpd_init(struct drm_device *dev) | |
4087 | { | |
4088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
4089 | struct drm_mode_config *mode_config = &dev->mode_config; |
4090 | struct drm_connector *connector; | |
b5ea2d56 | 4091 | unsigned long irqflags; |
821450c6 | 4092 | int i; |
20afbda2 | 4093 | |
821450c6 EE |
4094 | for (i = 1; i < HPD_NUM_PINS; i++) { |
4095 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
4096 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
4097 | } | |
4098 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
4099 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4100 | connector->polled = intel_connector->polled; | |
4101 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
4102 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
4103 | } | |
b5ea2d56 DV |
4104 | |
4105 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
4106 | * just to make the assert_spin_locked checks happy. */ | |
4107 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
4108 | if (dev_priv->display.hpd_irq_setup) |
4109 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 4110 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 4111 | } |
c67a470b | 4112 | |
5d584b2e PZ |
4113 | /* Disable interrupts so we can allow runtime PM. */ |
4114 | void hsw_runtime_pm_disable_interrupts(struct drm_device *dev) | |
c67a470b PZ |
4115 | { |
4116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4117 | unsigned long irqflags; | |
4118 | ||
4119 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4120 | ||
5d584b2e PZ |
4121 | dev_priv->pm.regsave.deimr = I915_READ(DEIMR); |
4122 | dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR); | |
4123 | dev_priv->pm.regsave.gtimr = I915_READ(GTIMR); | |
4124 | dev_priv->pm.regsave.gtier = I915_READ(GTIER); | |
4125 | dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
c67a470b | 4126 | |
1f2d4531 PZ |
4127 | ironlake_disable_display_irq(dev_priv, 0xffffffff); |
4128 | ibx_disable_display_interrupt(dev_priv, 0xffffffff); | |
c67a470b PZ |
4129 | ilk_disable_gt_irq(dev_priv, 0xffffffff); |
4130 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
4131 | ||
5d584b2e | 4132 | dev_priv->pm.irqs_disabled = true; |
c67a470b PZ |
4133 | |
4134 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4135 | } | |
4136 | ||
5d584b2e PZ |
4137 | /* Restore interrupts so we can recover from runtime PM. */ |
4138 | void hsw_runtime_pm_restore_interrupts(struct drm_device *dev) | |
c67a470b PZ |
4139 | { |
4140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4141 | unsigned long irqflags; | |
1f2d4531 | 4142 | uint32_t val; |
c67a470b PZ |
4143 | |
4144 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
4145 | ||
4146 | val = I915_READ(DEIMR); | |
1f2d4531 | 4147 | WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); |
c67a470b | 4148 | |
1f2d4531 PZ |
4149 | val = I915_READ(SDEIMR); |
4150 | WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); | |
c67a470b PZ |
4151 | |
4152 | val = I915_READ(GTIMR); | |
1f2d4531 | 4153 | WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); |
c67a470b PZ |
4154 | |
4155 | val = I915_READ(GEN6_PMIMR); | |
1f2d4531 | 4156 | WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); |
c67a470b | 4157 | |
5d584b2e | 4158 | dev_priv->pm.irqs_disabled = false; |
c67a470b | 4159 | |
5d584b2e PZ |
4160 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr); |
4161 | ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr); | |
4162 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr); | |
4163 | snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr); | |
4164 | I915_WRITE(GTIER, dev_priv->pm.regsave.gtier); | |
c67a470b PZ |
4165 | |
4166 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
4167 | } |