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drm/i915: add haswell_update_sprite_wm
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
73static const u32 hpd_status_i965[] = {
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
82static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
83 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
cd569aed
EE		 91static void ibx_hpd_irq_setup(struct drm_device *dev);
92static void i915_hpd_irq_setup(struct drm_device *dev);
e5868a31 93
036a4a7d 94/* For display hotplug interrupt */
995b6762 95static void
f2b115e6 96ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
1ec14ad3
CW		 98 if ((dev_priv->irq_mask & mask) != 0) {
99 dev_priv->irq_mask &= ~mask;
100 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 101 POSTING_READ(DEIMR);
036a4a7d
ZW		 102 }
103}
104
0ff9800a 105static void
f2b115e6 106ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 107{
1ec14ad3
CW		 108 if ((dev_priv->irq_mask & mask) != mask) {
109 dev_priv->irq_mask |= mask;
110 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 111 POSTING_READ(DEIMR);
036a4a7d
ZW		 112 }
113}
114
8664281b
PZ		 115static bool ivb_can_enable_err_int(struct drm_device *dev)
116{
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct intel_crtc *crtc;
119 enum pipe pipe;
120
121 for_each_pipe(pipe) {
122 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
123
124 if (crtc->cpu_fifo_underrun_disabled)
125 return false;
126 }
127
128 return true;
129}
130
131static bool cpt_can_enable_serr_int(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 enum pipe pipe;
135 struct intel_crtc *crtc;
136
137 for_each_pipe(pipe) {
138 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
139
140 if (crtc->pch_fifo_underrun_disabled)
141 return false;
142 }
143
144 return true;
145}
146
147static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
148 enum pipe pipe, bool enable)
149{
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
152 DE_PIPEB_FIFO_UNDERRUN;
153
154 if (enable)
155 ironlake_enable_display_irq(dev_priv, bit);
156 else
157 ironlake_disable_display_irq(dev_priv, bit);
158}
159
160static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
161 bool enable)
162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 if (enable) {
166 if (!ivb_can_enable_err_int(dev))
167 return;
168
169 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
170 ERR_INT_FIFO_UNDERRUN_B |
171 ERR_INT_FIFO_UNDERRUN_C);
172
173 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
174 } else {
175 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
176 }
177}
178
179static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
180 bool enable)
181{
182 struct drm_device *dev = crtc->base.dev;
183 struct drm_i915_private *dev_priv = dev->dev_private;
184 uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
185 SDE_TRANSB_FIFO_UNDER;
186
187 if (enable)
188 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
189 else
190 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
191
192 POSTING_READ(SDEIMR);
193}
194
195static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
196 enum transcoder pch_transcoder,
197 bool enable)
198{
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
201 if (enable) {
202 if (!cpt_can_enable_serr_int(dev))
203 return;
204
205 I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
206 SERR_INT_TRANS_B_FIFO_UNDERRUN |
207 SERR_INT_TRANS_C_FIFO_UNDERRUN);
208
209 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
210 } else {
211 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
212 }
213
214 POSTING_READ(SDEIMR);
215}
216
217/**
218 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
219 * @dev: drm device
220 * @pipe: pipe
221 * @enable: true if we want to report FIFO underrun errors, false otherwise
222 *
223 * This function makes us disable or enable CPU fifo underruns for a specific
224 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
225 * reporting for one pipe may also disable all the other CPU error interruts for
226 * the other pipes, due to the fact that there's just one interrupt mask/enable
227 * bit for all the pipes.
228 *
229 * Returns the previous state of underrun reporting.
230 */
231bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
232 enum pipe pipe, bool enable)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
237 unsigned long flags;
238 bool ret;
239
240 spin_lock_irqsave(&dev_priv->irq_lock, flags);
241
242 ret = !intel_crtc->cpu_fifo_underrun_disabled;
243
244 if (enable == ret)
245 goto done;
246
247 intel_crtc->cpu_fifo_underrun_disabled = !enable;
248
249 if (IS_GEN5(dev) || IS_GEN6(dev))
250 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
251 else if (IS_GEN7(dev))
252 ivybridge_set_fifo_underrun_reporting(dev, enable);
253
254done:
255 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
256 return ret;
257}
258
259/**
260 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
261 * @dev: drm device
262 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
263 * @enable: true if we want to report FIFO underrun errors, false otherwise
264 *
265 * This function makes us disable or enable PCH fifo underruns for a specific
266 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
267 * underrun reporting for one transcoder may also disable all the other PCH
268 * error interruts for the other transcoders, due to the fact that there's just
269 * one interrupt mask/enable bit for all the transcoders.
270 *
271 * Returns the previous state of underrun reporting.
272 */
273bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
275 bool enable)
276{
277 struct drm_i915_private *dev_priv = dev->dev_private;
278 enum pipe p;
279 struct drm_crtc *crtc;
280 struct intel_crtc *intel_crtc;
281 unsigned long flags;
282 bool ret;
283
284 if (HAS_PCH_LPT(dev)) {
285 crtc = NULL;
286 for_each_pipe(p) {
287 struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
288 if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
289 crtc = c;
290 break;
291 }
292 }
293 if (!crtc) {
294 DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
295 return false;
296 }
297 } else {
298 crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
299 }
300 intel_crtc = to_intel_crtc(crtc);
301
302 spin_lock_irqsave(&dev_priv->irq_lock, flags);
303
304 ret = !intel_crtc->pch_fifo_underrun_disabled;
305
306 if (enable == ret)
307 goto done;
308
309 intel_crtc->pch_fifo_underrun_disabled = !enable;
310
311 if (HAS_PCH_IBX(dev))
312 ibx_set_fifo_underrun_reporting(intel_crtc, enable);
313 else
314 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
315
316done:
317 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
318 return ret;
319}
320
321
7c463586
KP		 322void
323i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
324{
46c06a30
VS		 325 u32 reg = PIPESTAT(pipe);
326 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 327
46c06a30
VS		 328 if ((pipestat & mask) == mask)
329 return;
330
331 /* Enable the interrupt, clear any pending status */
332 pipestat |= mask | (mask >> 16);
333 I915_WRITE(reg, pipestat);
334 POSTING_READ(reg);
7c463586
KP		 335}
336
337void
338i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
339{
46c06a30
VS		 340 u32 reg = PIPESTAT(pipe);
341 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 342
46c06a30
VS		 343 if ((pipestat & mask) == 0)
344 return;
345
346 pipestat &= ~mask;
347 I915_WRITE(reg, pipestat);
348 POSTING_READ(reg);
7c463586
KP		 349}
350
01c66889 351/**
f49e38dd 352 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 353 */
f49e38dd 354static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 355{
1ec14ad3
CW		 356 drm_i915_private_t *dev_priv = dev->dev_private;
357 unsigned long irqflags;
358
f49e38dd
JN		 359 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
360 return;
361
1ec14ad3 362 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 363
f898780b
JN		 364 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
365 if (INTEL_INFO(dev)->gen >= 4)
366 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 367
368 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 369}
370
0a3e67a4
JB		 371/**
372 * i915_pipe_enabled - check if a pipe is enabled
373 * @dev: DRM device
374 * @pipe: pipe to check
375 *
376 * Reading certain registers when the pipe is disabled can hang the chip.
377 * Use this routine to make sure the PLL is running and the pipe is active
378 * before reading such registers if unsure.
379 */
380static int
381i915_pipe_enabled(struct drm_device *dev, int pipe)
382{
383 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 384 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
385 pipe);
386
71f8ba6b
PZ		 387 if (!intel_display_power_enabled(dev,
388 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
389 return false;
390
702e7a56 391 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 392}
393
42f52ef8
KP		 394/* Called from drm generic code, passed a 'crtc', which
395 * we use as a pipe index
396 */
f71d4af4 397static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 398{
399 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
400 unsigned long high_frame;
401 unsigned long low_frame;
5eddb70b 402 u32 high1, high2, low;
0a3e67a4
JB		 403
404 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 405 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 406 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 407 return 0;
408 }
409
9db4a9c7
JB		 410 high_frame = PIPEFRAME(pipe);
411 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 412
0a3e67a4
JB		 413 /*
414 * High & low register fields aren't synchronized, so make sure
415 * we get a low value that's stable across two reads of the high
416 * register.
417 */
418 do {
5eddb70b
CW		 419 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
420 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
421 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 422 } while (high1 != high2);
423
5eddb70b
CW		 424 high1 >>= PIPE_FRAME_HIGH_SHIFT;
425 low >>= PIPE_FRAME_LOW_SHIFT;
426 return (high1 << 8) | low;
0a3e67a4
JB		 427}
428
f71d4af4 429static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 430{
431 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 432 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 433
434 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 435 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 436 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 437 return 0;
438 }
439
440 return I915_READ(reg);
441}
442
f71d4af4 443static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 444 int *vpos, int *hpos)
445{
446 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
447 u32 vbl = 0, position = 0;
448 int vbl_start, vbl_end, htotal, vtotal;
449 bool in_vbl = true;
450 int ret = 0;
fe2b8f9d
PZ		 451 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
452 pipe);
0af7e4df
MK		 453
454 if (!i915_pipe_enabled(dev, pipe)) {
455 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 456 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 457 return 0;
458 }
459
460 /* Get vtotal. */
fe2b8f9d 461 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 462
463 if (INTEL_INFO(dev)->gen >= 4) {
464 /* No obvious pixelcount register. Only query vertical
465 * scanout position from Display scan line register.
466 */
467 position = I915_READ(PIPEDSL(pipe));
468
469 /* Decode into vertical scanout position. Don't have
470 * horizontal scanout position.
471 */
472 *vpos = position & 0x1fff;
473 *hpos = 0;
474 } else {
475 /* Have access to pixelcount since start of frame.
476 * We can split this into vertical and horizontal
477 * scanout position.
478 */
479 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
480
fe2b8f9d 481 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 482 *vpos = position / htotal;
483 *hpos = position - (*vpos * htotal);
484 }
485
486 /* Query vblank area. */
fe2b8f9d 487 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 488
489 /* Test position against vblank region. */
490 vbl_start = vbl & 0x1fff;
491 vbl_end = (vbl >> 16) & 0x1fff;
492
493 if ((*vpos < vbl_start) || (*vpos > vbl_end))
494 in_vbl = false;
495
496 /* Inside "upper part" of vblank area? Apply corrective offset: */
497 if (in_vbl && (*vpos >= vbl_start))
498 *vpos = *vpos - vtotal;
499
500 /* Readouts valid? */
501 if (vbl > 0)
502 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
503
504 /* In vblank? */
505 if (in_vbl)
506 ret |= DRM_SCANOUTPOS_INVBL;
507
508 return ret;
509}
510
f71d4af4 511static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 512 int *max_error,
513 struct timeval *vblank_time,
514 unsigned flags)
515{
4041b853 516 struct drm_crtc *crtc;
0af7e4df 517
7eb552ae 518 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 519 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 520 return -EINVAL;
521 }
522
523 /* Get drm_crtc to timestamp: */
4041b853
CW		 524 crtc = intel_get_crtc_for_pipe(dev, pipe);
525 if (crtc == NULL) {
526 DRM_ERROR("Invalid crtc %d\n", pipe);
527 return -EINVAL;
528 }
529
530 if (!crtc->enabled) {
531 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
532 return -EBUSY;
533 }
0af7e4df
MK		 534
535 /* Helper routine in DRM core does all the work: */
4041b853
CW		 536 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
537 vblank_time, flags,
538 crtc);
0af7e4df
MK		 539}
540
321a1b30
EE		 541static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
542{
543 enum drm_connector_status old_status;
544
545 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
546 old_status = connector->status;
547
548 connector->status = connector->funcs->detect(connector, false);
549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
550 connector->base.id,
551 drm_get_connector_name(connector),
552 old_status, connector->status);
553 return (old_status != connector->status);
554}
555
5ca58282
JB		 556/*
557 * Handle hotplug events outside the interrupt handler proper.
558 */
ac4c16c5
EE		 559#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
560
5ca58282
JB		 561static void i915_hotplug_work_func(struct work_struct *work)
562{
563 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
564 hotplug_work);
565 struct drm_device *dev = dev_priv->dev;
c31c4ba3 566 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 567 struct intel_connector *intel_connector;
568 struct intel_encoder *intel_encoder;
569 struct drm_connector *connector;
570 unsigned long irqflags;
571 bool hpd_disabled = false;
321a1b30 572 bool changed = false;
142e2398 573 u32 hpd_event_bits;
4ef69c7a 574
52d7eced
DV		 575 /* HPD irq before everything is fully set up. */
576 if (!dev_priv->enable_hotplug_processing)
577 return;
578
a65e34c7 579 mutex_lock(&mode_config->mutex);
e67189ab
JB		 580 DRM_DEBUG_KMS("running encoder hotplug functions\n");
581
cd569aed 582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 583
584 hpd_event_bits = dev_priv->hpd_event_bits;
585 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 586 list_for_each_entry(connector, &mode_config->connector_list, head) {
587 intel_connector = to_intel_connector(connector);
588 intel_encoder = intel_connector->encoder;
589 if (intel_encoder->hpd_pin > HPD_NONE &&
590 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
591 connector->polled == DRM_CONNECTOR_POLL_HPD) {
592 DRM_INFO("HPD interrupt storm detected on connector %s: "
593 "switching from hotplug detection to polling\n",
594 drm_get_connector_name(connector));
595 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
596 connector->polled = DRM_CONNECTOR_POLL_CONNECT
597 | DRM_CONNECTOR_POLL_DISCONNECT;
598 hpd_disabled = true;
599 }
142e2398
EE		 600 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
601 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
602 drm_get_connector_name(connector), intel_encoder->hpd_pin);
603 }
cd569aed
EE		 604 }
605 /* if there were no outputs to poll, poll was disabled,
606 * therefore make sure it's enabled when disabling HPD on
607 * some connectors */
ac4c16c5 608 if (hpd_disabled) {
cd569aed 609 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 610 mod_timer(&dev_priv->hotplug_reenable_timer,
611 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
612 }
cd569aed
EE		 613
614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
615
321a1b30
EE		 616 list_for_each_entry(connector, &mode_config->connector_list, head) {
617 intel_connector = to_intel_connector(connector);
618 intel_encoder = intel_connector->encoder;
619 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
620 if (intel_encoder->hot_plug)
621 intel_encoder->hot_plug(intel_encoder);
622 if (intel_hpd_irq_event(dev, connector))
623 changed = true;
624 }
625 }
40ee3381
KP		 626 mutex_unlock(&mode_config->mutex);
627
321a1b30
EE		 628 if (changed)
629 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 630}
631
73edd18f 632static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 633{
634 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 635 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 636 u8 new_delay;
637 unsigned long flags;
638
639 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 640
73edd18f
DV		 641 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
642
20e4d407 643 new_delay = dev_priv->ips.cur_delay;
9270388e 644
7648fa99 645 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 646 busy_up = I915_READ(RCPREVBSYTUPAVG);
647 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 648 max_avg = I915_READ(RCBMAXAVG);
649 min_avg = I915_READ(RCBMINAVG);
650
651 /* Handle RCS change request from hw */
b5b72e89 652 if (busy_up > max_avg) {
20e4d407
DV		 653 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
654 new_delay = dev_priv->ips.cur_delay - 1;
655 if (new_delay < dev_priv->ips.max_delay)
656 new_delay = dev_priv->ips.max_delay;
b5b72e89 657 } else if (busy_down < min_avg) {
20e4d407
DV		 658 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
659 new_delay = dev_priv->ips.cur_delay + 1;
660 if (new_delay > dev_priv->ips.min_delay)
661 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 662 }
663
7648fa99 664 if (ironlake_set_drps(dev, new_delay))
20e4d407 665 dev_priv->ips.cur_delay = new_delay;
f97108d1 666
9270388e
DV		 667 spin_unlock_irqrestore(&mchdev_lock, flags);
668
f97108d1
JB		 669 return;
670}
671
549f7365
CW		 672static void notify_ring(struct drm_device *dev,
673 struct intel_ring_buffer *ring)
674{
675 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 676
475553de
CW		 677 if (ring->obj == NULL)
678 return;
679
b2eadbc8 680 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 681
549f7365 682 wake_up_all(&ring->irq_queue);
3e0dc6b0 683 if (i915_enable_hangcheck) {
99584db3
DV		 684 dev_priv->gpu_error.hangcheck_count = 0;
685 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 686 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 687 }
549f7365
CW		 688}
689
4912d041 690static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 691{
4912d041 692 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 693 rps.work);
4912d041 694 u32 pm_iir, pm_imr;
7b9e0ae6 695 u8 new_delay;
4912d041 696
c6a828d3
DV		 697 spin_lock_irq(&dev_priv->rps.lock);
698 pm_iir = dev_priv->rps.pm_iir;
699 dev_priv->rps.pm_iir = 0;
4912d041 700 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 701 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 702 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 703
7b9e0ae6 704 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 705 return;
706
4fc688ce 707 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 708
709 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 710 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 711 else
c6a828d3 712 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 713
79249636
BW		 714 /* sysfs frequency interfaces may have snuck in while servicing the
715 * interrupt
716 */
717 if (!(new_delay > dev_priv->rps.max_delay ||
718 new_delay < dev_priv->rps.min_delay)) {
0a073b84
JB		 719 if (IS_VALLEYVIEW(dev_priv->dev))
720 valleyview_set_rps(dev_priv->dev, new_delay);
721 else
722 gen6_set_rps(dev_priv->dev, new_delay);
79249636 723 }
3b8d8d91 724
52ceb908
JB		 725 if (IS_VALLEYVIEW(dev_priv->dev)) {
726 /*
727 * On VLV, when we enter RC6 we may not be at the minimum
728 * voltage level, so arm a timer to check. It should only
729 * fire when there's activity or once after we've entered
730 * RC6, and then won't be re-armed until the next RPS interrupt.
731 */
732 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
733 msecs_to_jiffies(100));
734 }
735
4fc688ce 736 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 737}
738
e3689190
BW		 739
740/**
741 * ivybridge_parity_work - Workqueue called when a parity error interrupt
742 * occurred.
743 * @work: workqueue struct
744 *
745 * Doesn't actually do anything except notify userspace. As a consequence of
746 * this event, userspace should try to remap the bad rows since statistically
747 * it is likely the same row is more likely to go bad again.
748 */
749static void ivybridge_parity_work(struct work_struct *work)
750{
751 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 752 l3_parity.error_work);
e3689190
BW		 753 u32 error_status, row, bank, subbank;
754 char *parity_event[5];
755 uint32_t misccpctl;
756 unsigned long flags;
757
758 /* We must turn off DOP level clock gating to access the L3 registers.
759 * In order to prevent a get/put style interface, acquire struct mutex
760 * any time we access those registers.
761 */
762 mutex_lock(&dev_priv->dev->struct_mutex);
763
764 misccpctl = I915_READ(GEN7_MISCCPCTL);
765 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
766 POSTING_READ(GEN7_MISCCPCTL);
767
768 error_status = I915_READ(GEN7_L3CDERRST1);
769 row = GEN7_PARITY_ERROR_ROW(error_status);
770 bank = GEN7_PARITY_ERROR_BANK(error_status);
771 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
772
773 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
774 GEN7_L3CDERRST1_ENABLE);
775 POSTING_READ(GEN7_L3CDERRST1);
776
777 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
778
779 spin_lock_irqsave(&dev_priv->irq_lock, flags);
780 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
781 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
782 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
783
784 mutex_unlock(&dev_priv->dev->struct_mutex);
785
786 parity_event[0] = "L3_PARITY_ERROR=1";
787 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
788 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
789 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
790 parity_event[4] = NULL;
791
792 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
793 KOBJ_CHANGE, parity_event);
794
795 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
796 row, bank, subbank);
797
798 kfree(parity_event[3]);
799 kfree(parity_event[2]);
800 kfree(parity_event[1]);
801}
802
d2ba8470 803static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 804{
805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
806 unsigned long flags;
807
e1ef7cc2 808 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 809 return;
810
811 spin_lock_irqsave(&dev_priv->irq_lock, flags);
812 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
813 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
814 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
815
a4da4fa4 816 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 817}
818
e7b4c6b1
DV		 819static void snb_gt_irq_handler(struct drm_device *dev,
820 struct drm_i915_private *dev_priv,
821 u32 gt_iir)
822{
823
824 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
825 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
826 notify_ring(dev, &dev_priv->ring[RCS]);
827 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
828 notify_ring(dev, &dev_priv->ring[VCS]);
829 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
830 notify_ring(dev, &dev_priv->ring[BCS]);
831
832 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
833 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
834 GT_RENDER_CS_ERROR_INTERRUPT)) {
835 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
836 i915_handle_error(dev, false);
837 }
e3689190
BW		 838
839 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
840 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 841}
842
fc6826d1
CW		 843static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
844 u32 pm_iir)
845{
846 unsigned long flags;
847
848 /*
849 * IIR bits should never already be set because IMR should
850 * prevent an interrupt from being shown in IIR. The warning
851 * displays a case where we've unsafely cleared
c6a828d3 852 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 853 * type is not a problem, it displays a problem in the logic.
854 *
c6a828d3 855 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 856 */
857
c6a828d3 858 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 859 dev_priv->rps.pm_iir |= pm_iir;
860 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 861 POSTING_READ(GEN6_PMIMR);
c6a828d3 862 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 863
c6a828d3 864 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 865}
866
b543fb04
EE		 867#define HPD_STORM_DETECT_PERIOD 1000
868#define HPD_STORM_THRESHOLD 5
869
cd569aed 870static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
b543fb04
EE		 871 u32 hotplug_trigger,
872 const u32 *hpd)
873{
874 drm_i915_private_t *dev_priv = dev->dev_private;
875 unsigned long irqflags;
876 int i;
cd569aed 877 bool ret = false;
b543fb04
EE		 878
879 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
880
881 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 882
b543fb04
EE		 883 if (!(hpd[i] & hotplug_trigger) ||
884 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
885 continue;
886
bc5ead8c 887 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 888 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
889 dev_priv->hpd_stats[i].hpd_last_jiffies
890 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
891 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
892 dev_priv->hpd_stats[i].hpd_cnt = 0;
893 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
894 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 895 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 896 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
cd569aed 897 ret = true;
b543fb04
EE		 898 } else {
899 dev_priv->hpd_stats[i].hpd_cnt++;
900 }
901 }
902
903 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
cd569aed
EE		 904
905 return ret;
b543fb04
EE		 906}
907
515ac2bb
DV		 908static void gmbus_irq_handler(struct drm_device *dev)
909{
28c70f16
DV		 910 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
911
28c70f16 912 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 913}
914
ce99c256
DV		 915static void dp_aux_irq_handler(struct drm_device *dev)
916{
9ee32fea
DV		 917 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
918
9ee32fea 919 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 920}
921
ff1f525e 922static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 923{
924 struct drm_device *dev = (struct drm_device *) arg;
925 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
926 u32 iir, gt_iir, pm_iir;
927 irqreturn_t ret = IRQ_NONE;
928 unsigned long irqflags;
929 int pipe;
930 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 931
932 atomic_inc(&dev_priv->irq_received);
933
7e231dbe
JB		 934 while (true) {
935 iir = I915_READ(VLV_IIR);
936 gt_iir = I915_READ(GTIIR);
937 pm_iir = I915_READ(GEN6_PMIIR);
938
939 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
940 goto out;
941
942 ret = IRQ_HANDLED;
943
e7b4c6b1 944 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 945
946 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
947 for_each_pipe(pipe) {
948 int reg = PIPESTAT(pipe);
949 pipe_stats[pipe] = I915_READ(reg);
950
951 /*
952 * Clear the PIPE*STAT regs before the IIR
953 */
954 if (pipe_stats[pipe] & 0x8000ffff) {
955 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
956 DRM_DEBUG_DRIVER("pipe %c underrun\n",
957 pipe_name(pipe));
958 I915_WRITE(reg, pipe_stats[pipe]);
959 }
960 }
961 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
962
31acc7f5
JB		 963 for_each_pipe(pipe) {
964 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
965 drm_handle_vblank(dev, pipe);
966
967 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
968 intel_prepare_page_flip(dev, pipe);
969 intel_finish_page_flip(dev, pipe);
970 }
971 }
972
7e231dbe
JB		 973 /* Consume port. Then clear IIR or we'll miss events */
974 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
975 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 976 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 977
978 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
979 hotplug_status);
b543fb04 980 if (hotplug_trigger) {
cd569aed
EE		 981 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
982 i915_hpd_irq_setup(dev);
7e231dbe
JB		 983 queue_work(dev_priv->wq,
984 &dev_priv->hotplug_work);
b543fb04 985 }
7e231dbe
JB		 986 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
987 I915_READ(PORT_HOTPLUG_STAT);
988 }
989
515ac2bb
DV		 990 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
991 gmbus_irq_handler(dev);
7e231dbe 992
fc6826d1
CW		 993 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
994 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 995
996 I915_WRITE(GTIIR, gt_iir);
997 I915_WRITE(GEN6_PMIIR, pm_iir);
998 I915_WRITE(VLV_IIR, iir);
999 }
1000
1001out:
1002 return ret;
1003}
1004
23e81d69 1005static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1006{
1007 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1008 int pipe;
b543fb04 1009 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1010
b543fb04 1011 if (hotplug_trigger) {
cd569aed
EE		 1012 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
1013 ibx_hpd_irq_setup(dev);
76e43830 1014 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1015 }
cfc33bf7
VS		 1016 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1017 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1018 SDE_AUDIO_POWER_SHIFT);
776ad806 1019 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1020 port_name(port));
1021 }
776ad806 1022
ce99c256
DV		 1023 if (pch_iir & SDE_AUX_MASK)
1024 dp_aux_irq_handler(dev);
1025
776ad806 1026 if (pch_iir & SDE_GMBUS)
515ac2bb 1027 gmbus_irq_handler(dev);
776ad806
JB		 1028
1029 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1030 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1031
1032 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1033 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1034
1035 if (pch_iir & SDE_POISON)
1036 DRM_ERROR("PCH poison interrupt\n");
1037
9db4a9c7
JB		 1038 if (pch_iir & SDE_FDI_MASK)
1039 for_each_pipe(pipe)
1040 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1041 pipe_name(pipe),
1042 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1043
1044 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1045 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1046
1047 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1048 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1049
776ad806 1050 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1051 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1052 false))
1053 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1054
1055 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1056 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1057 false))
1058 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1059}
1060
1061static void ivb_err_int_handler(struct drm_device *dev)
1062{
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 u32 err_int = I915_READ(GEN7_ERR_INT);
1065
de032bf4
PZ		 1066 if (err_int & ERR_INT_POISON)
1067 DRM_ERROR("Poison interrupt\n");
1068
8664281b
PZ		 1069 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1070 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1071 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1072
1073 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1074 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1075 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1076
1077 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1078 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1079 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1080
1081 I915_WRITE(GEN7_ERR_INT, err_int);
1082}
1083
1084static void cpt_serr_int_handler(struct drm_device *dev)
1085{
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 u32 serr_int = I915_READ(SERR_INT);
1088
de032bf4
PZ		 1089 if (serr_int & SERR_INT_POISON)
1090 DRM_ERROR("PCH poison interrupt\n");
1091
8664281b
PZ		 1092 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1093 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1094 false))
1095 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1096
1097 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1098 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1099 false))
1100 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1101
1102 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1103 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1104 false))
1105 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1106
1107 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1108}
1109
23e81d69
AJ		 1110static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1111{
1112 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1113 int pipe;
b543fb04 1114 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1115
b543fb04 1116 if (hotplug_trigger) {
cd569aed
EE		 1117 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
1118 ibx_hpd_irq_setup(dev);
76e43830 1119 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
b543fb04 1120 }
cfc33bf7
VS		 1121 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1122 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1123 SDE_AUDIO_POWER_SHIFT_CPT);
1124 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1125 port_name(port));
1126 }
23e81d69
AJ		 1127
1128 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1129 dp_aux_irq_handler(dev);
23e81d69
AJ		 1130
1131 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1132 gmbus_irq_handler(dev);
23e81d69
AJ		 1133
1134 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1135 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1136
1137 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1138 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1139
1140 if (pch_iir & SDE_FDI_MASK_CPT)
1141 for_each_pipe(pipe)
1142 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1143 pipe_name(pipe),
1144 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1145
1146 if (pch_iir & SDE_ERROR_CPT)
1147 cpt_serr_int_handler(dev);
23e81d69
AJ		 1148}
1149
ff1f525e 1150static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1151{
1152 struct drm_device *dev = (struct drm_device *) arg;
1153 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1154 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1155 irqreturn_t ret = IRQ_NONE;
1156 int i;
b1f14ad0
JB		 1157
1158 atomic_inc(&dev_priv->irq_received);
1159
8664281b
PZ		 1160 /* We get interrupts on unclaimed registers, so check for this before we
1161 * do any I915_{READ,WRITE}. */
1162 if (IS_HASWELL(dev) &&
1163 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1164 DRM_ERROR("Unclaimed register before interrupt\n");
1165 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1166 }
1167
b1f14ad0
JB		 1168 /* disable master interrupt before clearing iir */
1169 de_ier = I915_READ(DEIER);
1170 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1171
44498aea
PZ		 1172 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1173 * interrupts will will be stored on its back queue, and then we'll be
1174 * able to process them after we restore SDEIER (as soon as we restore
1175 * it, we'll get an interrupt if SDEIIR still has something to process
1176 * due to its back queue). */
ab5c608b
BW		 1177 if (!HAS_PCH_NOP(dev)) {
1178 sde_ier = I915_READ(SDEIER);
1179 I915_WRITE(SDEIER, 0);
1180 POSTING_READ(SDEIER);
1181 }
44498aea 1182
8664281b
PZ		 1183 /* On Haswell, also mask ERR_INT because we don't want to risk
1184 * generating "unclaimed register" interrupts from inside the interrupt
1185 * handler. */
1186 if (IS_HASWELL(dev))
1187 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
1188
b1f14ad0 1189 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1190 if (gt_iir) {
1191 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1192 I915_WRITE(GTIIR, gt_iir);
1193 ret = IRQ_HANDLED;
b1f14ad0
JB		 1194 }
1195
0e43406b
CW		 1196 de_iir = I915_READ(DEIIR);
1197 if (de_iir) {
8664281b
PZ		 1198 if (de_iir & DE_ERR_INT_IVB)
1199 ivb_err_int_handler(dev);
1200
ce99c256
DV		 1201 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1202 dp_aux_irq_handler(dev);
1203
0e43406b 1204 if (de_iir & DE_GSE_IVB)
81a07809 1205 intel_opregion_asle_intr(dev);
0e43406b
CW		 1206
1207 for (i = 0; i < 3; i++) {
74d44445
DV		 1208 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1209 drm_handle_vblank(dev, i);
0e43406b
CW		 1210 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1211 intel_prepare_page_flip(dev, i);
1212 intel_finish_page_flip_plane(dev, i);
1213 }
0e43406b 1214 }
b615b57a 1215
0e43406b 1216 /* check event from PCH */
ab5c608b 1217 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1218 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1219
23e81d69 1220 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1221
0e43406b
CW		 1222 /* clear PCH hotplug event before clear CPU irq */
1223 I915_WRITE(SDEIIR, pch_iir);
1224 }
b615b57a 1225
0e43406b
CW		 1226 I915_WRITE(DEIIR, de_iir);
1227 ret = IRQ_HANDLED;
b1f14ad0
JB		 1228 }
1229
0e43406b
CW		 1230 pm_iir = I915_READ(GEN6_PMIIR);
1231 if (pm_iir) {
1232 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
1233 gen6_queue_rps_work(dev_priv, pm_iir);
1234 I915_WRITE(GEN6_PMIIR, pm_iir);
1235 ret = IRQ_HANDLED;
1236 }
b1f14ad0 1237
8664281b
PZ		 1238 if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
1239 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1240
b1f14ad0
JB		 1241 I915_WRITE(DEIER, de_ier);
1242 POSTING_READ(DEIER);
ab5c608b
BW		 1243 if (!HAS_PCH_NOP(dev)) {
1244 I915_WRITE(SDEIER, sde_ier);
1245 POSTING_READ(SDEIER);
1246 }
b1f14ad0
JB		 1247
1248 return ret;
1249}
1250
e7b4c6b1
DV		 1251static void ilk_gt_irq_handler(struct drm_device *dev,
1252 struct drm_i915_private *dev_priv,
1253 u32 gt_iir)
1254{
1255 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
1256 notify_ring(dev, &dev_priv->ring[RCS]);
1257 if (gt_iir & GT_BSD_USER_INTERRUPT)
1258 notify_ring(dev, &dev_priv->ring[VCS]);
1259}
1260
ff1f525e 1261static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1262{
4697995b 1263 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1264 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1265 int ret = IRQ_NONE;
44498aea 1266 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1267
4697995b
JB		 1268 atomic_inc(&dev_priv->irq_received);
1269
2d109a84
ZN		 1270 /* disable master interrupt before clearing iir */
1271 de_ier = I915_READ(DEIER);
1272 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1273 POSTING_READ(DEIER);
2d109a84 1274
44498aea
PZ		 1275 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1276 * interrupts will will be stored on its back queue, and then we'll be
1277 * able to process them after we restore SDEIER (as soon as we restore
1278 * it, we'll get an interrupt if SDEIIR still has something to process
1279 * due to its back queue). */
1280 sde_ier = I915_READ(SDEIER);
1281 I915_WRITE(SDEIER, 0);
1282 POSTING_READ(SDEIER);
1283
036a4a7d
ZW		 1284 de_iir = I915_READ(DEIIR);
1285 gt_iir = I915_READ(GTIIR);
3b8d8d91 1286 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1287
acd15b6c 1288 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1289 goto done;
036a4a7d 1290
c7c85101 1291 ret = IRQ_HANDLED;
036a4a7d 1292
e7b4c6b1
DV		 1293 if (IS_GEN5(dev))
1294 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1295 else
1296 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1297
ce99c256
DV		 1298 if (de_iir & DE_AUX_CHANNEL_A)
1299 dp_aux_irq_handler(dev);
1300
c7c85101 1301 if (de_iir & DE_GSE)
81a07809 1302 intel_opregion_asle_intr(dev);
c650156a 1303
74d44445
DV		 1304 if (de_iir & DE_PIPEA_VBLANK)
1305 drm_handle_vblank(dev, 0);
1306
1307 if (de_iir & DE_PIPEB_VBLANK)
1308 drm_handle_vblank(dev, 1);
1309
de032bf4
PZ		 1310 if (de_iir & DE_POISON)
1311 DRM_ERROR("Poison interrupt\n");
1312
8664281b
PZ		 1313 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1314 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1315 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1316
1317 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1318 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1319 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1320
f072d2e7 1321 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1322 intel_prepare_page_flip(dev, 0);
2bbda389 1323 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1324 }
013d5aa2 1325
f072d2e7 1326 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1327 intel_prepare_page_flip(dev, 1);
2bbda389 1328 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1329 }
013d5aa2 1330
c7c85101 1331 /* check event from PCH */
776ad806 1332 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1333 u32 pch_iir = I915_READ(SDEIIR);
1334
23e81d69
AJ		 1335 if (HAS_PCH_CPT(dev))
1336 cpt_irq_handler(dev, pch_iir);
1337 else
1338 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1339
1340 /* should clear PCH hotplug event before clear CPU irq */
1341 I915_WRITE(SDEIIR, pch_iir);
776ad806 1342 }
036a4a7d 1343
73edd18f
DV		 1344 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1345 ironlake_handle_rps_change(dev);
f97108d1 1346
fc6826d1
CW		 1347 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
1348 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 1349
c7c85101
ZN		 1350 I915_WRITE(GTIIR, gt_iir);
1351 I915_WRITE(DEIIR, de_iir);
4912d041 1352 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1353
1354done:
2d109a84 1355 I915_WRITE(DEIER, de_ier);
3143a2bf 1356 POSTING_READ(DEIER);
44498aea
PZ		 1357 I915_WRITE(SDEIER, sde_ier);
1358 POSTING_READ(SDEIER);
2d109a84 1359
036a4a7d
ZW		 1360 return ret;
1361}
1362
8a905236
JB		 1363/**
1364 * i915_error_work_func - do process context error handling work
1365 * @work: work struct
1366 *
1367 * Fire an error uevent so userspace can see that a hang or error
1368 * was detected.
1369 */
1370static void i915_error_work_func(struct work_struct *work)
1371{
1f83fee0
DV		 1372 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1373 work);
1374 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1375 gpu_error);
8a905236 1376 struct drm_device *dev = dev_priv->dev;
f69061be 1377 struct intel_ring_buffer *ring;
f316a42c
BG		 1378 char *error_event[] = { "ERROR=1", NULL };
1379 char *reset_event[] = { "RESET=1", NULL };
1380 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1381 int i, ret;
8a905236 1382
f316a42c
BG		 1383 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1384
7db0ba24
DV		 1385 /*
1386 * Note that there's only one work item which does gpu resets, so we
1387 * need not worry about concurrent gpu resets potentially incrementing
1388 * error->reset_counter twice. We only need to take care of another
1389 * racing irq/hangcheck declaring the gpu dead for a second time. A
1390 * quick check for that is good enough: schedule_work ensures the
1391 * correct ordering between hang detection and this work item, and since
1392 * the reset in-progress bit is only ever set by code outside of this
1393 * work we don't need to worry about any other races.
1394 */
1395 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1396 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1397 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1398 reset_event);
1f83fee0 1399
f69061be
DV		 1400 ret = i915_reset(dev);
1401
1402 if (ret == 0) {
1403 /*
1404 * After all the gem state is reset, increment the reset
1405 * counter and wake up everyone waiting for the reset to
1406 * complete.
1407 *
1408 * Since unlock operations are a one-sided barrier only,
1409 * we need to insert a barrier here to order any seqno
1410 * updates before
1411 * the counter increment.
1412 */
1413 smp_mb__before_atomic_inc();
1414 atomic_inc(&dev_priv->gpu_error.reset_counter);
1415
1416 kobject_uevent_env(&dev->primary->kdev.kobj,
1417 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1418 } else {
1419 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1420 }
1f83fee0 1421
f69061be
DV		 1422 for_each_ring(ring, dev_priv, i)
1423 wake_up_all(&ring->irq_queue);
1424
96a02917
VS		 1425 intel_display_handle_reset(dev);
1426
1f83fee0 1427 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1428 }
8a905236
JB		 1429}
1430
85f9e50d
DV		 1431/* NB: please notice the memset */
1432static void i915_get_extra_instdone(struct drm_device *dev,
1433 uint32_t *instdone)
1434{
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1437
1438 switch(INTEL_INFO(dev)->gen) {
1439 case 2:
1440 case 3:
1441 instdone[0] = I915_READ(INSTDONE);
1442 break;
1443 case 4:
1444 case 5:
1445 case 6:
1446 instdone[0] = I915_READ(INSTDONE_I965);
1447 instdone[1] = I915_READ(INSTDONE1);
1448 break;
1449 default:
1450 WARN_ONCE(1, "Unsupported platform\n");
1451 case 7:
1452 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1453 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1454 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1455 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1456 break;
1457 }
1458}
1459
3bd3c932 1460#ifdef CONFIG_DEBUG_FS
9df30794 1461static struct drm_i915_error_object *
d0d045e8
BW		 1462i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1463 struct drm_i915_gem_object *src,
1464 const int num_pages)
9df30794
CW		 1465{
1466 struct drm_i915_error_object *dst;
d0d045e8 1467 int i;
e56660dd 1468 u32 reloc_offset;
9df30794 1469
05394f39 1470 if (src == NULL || src->pages == NULL)
9df30794
CW		 1471 return NULL;
1472
d0d045e8 1473 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1474 if (dst == NULL)
1475 return NULL;
1476
05394f39 1477 reloc_offset = src->gtt_offset;
d0d045e8 1478 for (i = 0; i < num_pages; i++) {
788885ae 1479 unsigned long flags;
e56660dd 1480 void *d;
788885ae 1481
e56660dd 1482 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1483 if (d == NULL)
1484 goto unwind;
e56660dd 1485
788885ae 1486 local_irq_save(flags);
5d4545ae 1487 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1488 src->has_global_gtt_mapping) {
172975aa
CW		 1489 void __iomem *s;
1490
1491 /* Simply ignore tiling or any overlapping fence.
1492 * It's part of the error state, and this hopefully
1493 * captures what the GPU read.
1494 */
1495
5d4545ae 1496 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1497 reloc_offset);
1498 memcpy_fromio(d, s, PAGE_SIZE);
1499 io_mapping_unmap_atomic(s);
960e3564
CW		 1500 } else if (src->stolen) {
1501 unsigned long offset;
1502
1503 offset = dev_priv->mm.stolen_base;
1504 offset += src->stolen->start;
1505 offset += i << PAGE_SHIFT;
1506
1a240d4d 1507 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1508 } else {
9da3da66 1509 struct page *page;
172975aa
CW		 1510 void *s;
1511
9da3da66 1512 page = i915_gem_object_get_page(src, i);
172975aa 1513
9da3da66
CW		 1514 drm_clflush_pages(&page, 1);
1515
1516 s = kmap_atomic(page);
172975aa
CW		 1517 memcpy(d, s, PAGE_SIZE);
1518 kunmap_atomic(s);
1519
9da3da66 1520 drm_clflush_pages(&page, 1);
172975aa 1521 }
788885ae 1522 local_irq_restore(flags);
e56660dd 1523
9da3da66 1524 dst->pages[i] = d;
e56660dd
CW		 1525
1526 reloc_offset += PAGE_SIZE;
9df30794 1527 }
d0d045e8 1528 dst->page_count = num_pages;
05394f39 1529 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1530
1531 return dst;
1532
1533unwind:
9da3da66
CW		 1534 while (i--)
1535 kfree(dst->pages[i]);
9df30794
CW		 1536 kfree(dst);
1537 return NULL;
1538}
d0d045e8
BW		 1539#define i915_error_object_create(dev_priv, src) \
1540 i915_error_object_create_sized((dev_priv), (src), \
1541 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1542
1543static void
1544i915_error_object_free(struct drm_i915_error_object *obj)
1545{
1546 int page;
1547
1548 if (obj == NULL)
1549 return;
1550
1551 for (page = 0; page < obj->page_count; page++)
1552 kfree(obj->pages[page]);
1553
1554 kfree(obj);
1555}
1556
742cbee8
DV		 1557void
1558i915_error_state_free(struct kref *error_ref)
9df30794 1559{
742cbee8
DV		 1560 struct drm_i915_error_state *error = container_of(error_ref,
1561 typeof(*error), ref);
e2f973d5
CW		 1562 int i;
1563
52d39a21
CW		 1564 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1565 i915_error_object_free(error->ring[i].batchbuffer);
1566 i915_error_object_free(error->ring[i].ringbuffer);
1567 kfree(error->ring[i].requests);
1568 }
e2f973d5 1569
9df30794 1570 kfree(error->active_bo);
6ef3d427 1571 kfree(error->overlay);
9df30794
CW		 1572 kfree(error);
1573}
1b50247a
CW		 1574static void capture_bo(struct drm_i915_error_buffer *err,
1575 struct drm_i915_gem_object *obj)
1576{
1577 err->size = obj->base.size;
1578 err->name = obj->base.name;
0201f1ec
CW		 1579 err->rseqno = obj->last_read_seqno;
1580 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1581 err->gtt_offset = obj->gtt_offset;
1582 err->read_domains = obj->base.read_domains;
1583 err->write_domain = obj->base.write_domain;
1584 err->fence_reg = obj->fence_reg;
1585 err->pinned = 0;
1586 if (obj->pin_count > 0)
1587 err->pinned = 1;
1588 if (obj->user_pin_count > 0)
1589 err->pinned = -1;
1590 err->tiling = obj->tiling_mode;
1591 err->dirty = obj->dirty;
1592 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1593 err->ring = obj->ring ? obj->ring->id : -1;
1594 err->cache_level = obj->cache_level;
1595}
9df30794 1596
1b50247a
CW		 1597static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1598 int count, struct list_head *head)
c724e8a9
CW		 1599{
1600 struct drm_i915_gem_object *obj;
1601 int i = 0;
1602
1603 list_for_each_entry(obj, head, mm_list) {
1b50247a 1604 capture_bo(err++, obj);
c724e8a9
CW		 1605 if (++i == count)
1606 break;
1b50247a
CW		 1607 }
1608
1609 return i;
1610}
1611
1612static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1613 int count, struct list_head *head)
1614{
1615 struct drm_i915_gem_object *obj;
1616 int i = 0;
1617
1618 list_for_each_entry(obj, head, gtt_list) {
1619 if (obj->pin_count == 0)
1620 continue;
c724e8a9 1621
1b50247a
CW		 1622 capture_bo(err++, obj);
1623 if (++i == count)
1624 break;
c724e8a9
CW		 1625 }
1626
1627 return i;
1628}
1629
748ebc60
CW		 1630static void i915_gem_record_fences(struct drm_device *dev,
1631 struct drm_i915_error_state *error)
1632{
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int i;
1635
1636 /* Fences */
1637 switch (INTEL_INFO(dev)->gen) {
775d17b6 1638 case 7:
748ebc60 1639 case 6:
42b5aeab 1640 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1641 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1642 break;
1643 case 5:
1644 case 4:
1645 for (i = 0; i < 16; i++)
1646 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1647 break;
1648 case 3:
1649 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1650 for (i = 0; i < 8; i++)
1651 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1652 case 2:
1653 for (i = 0; i < 8; i++)
1654 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1655 break;
1656
7dbf9d6e
BW		 1657 default:
1658 BUG();
748ebc60
CW		 1659 }
1660}
1661
bcfb2e28
CW		 1662static struct drm_i915_error_object *
1663i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1664 struct intel_ring_buffer *ring)
1665{
1666 struct drm_i915_gem_object *obj;
1667 u32 seqno;
1668
1669 if (!ring->get_seqno)
1670 return NULL;
1671
b45305fc
DV		 1672 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1673 u32 acthd = I915_READ(ACTHD);
1674
1675 if (WARN_ON(ring->id != RCS))
1676 return NULL;
1677
1678 obj = ring->private;
1679 if (acthd >= obj->gtt_offset &&
1680 acthd < obj->gtt_offset + obj->base.size)
1681 return i915_error_object_create(dev_priv, obj);
1682 }
1683
b2eadbc8 1684 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1685 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1686 if (obj->ring != ring)
1687 continue;
1688
0201f1ec 1689 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1690 continue;
1691
1692 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1693 continue;
1694
1695 /* We need to copy these to an anonymous buffer as the simplest
1696 * method to avoid being overwritten by userspace.
1697 */
1698 return i915_error_object_create(dev_priv, obj);
1699 }
1700
1701 return NULL;
1702}
1703
d27b1e0e
DV		 1704static void i915_record_ring_state(struct drm_device *dev,
1705 struct drm_i915_error_state *error,
1706 struct intel_ring_buffer *ring)
1707{
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709
33f3f518 1710 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1711 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1712 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1713 error->semaphore_mboxes[ring->id][0]
1714 = I915_READ(RING_SYNC_0(ring->mmio_base));
1715 error->semaphore_mboxes[ring->id][1]
1716 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1717 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1718 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1719 }
c1cd90ed 1720
d27b1e0e 1721 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1722 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1723 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1724 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1725 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1726 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1727 if (ring->id == RCS)
d27b1e0e 1728 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1729 } else {
9d2f41fa 1730 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1731 error->ipeir[ring->id] = I915_READ(IPEIR);
1732 error->ipehr[ring->id] = I915_READ(IPEHR);
1733 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1734 }
1735
9574b3fe 1736 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1737 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1738 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1739 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1740 error->head[ring->id] = I915_READ_HEAD(ring);
1741 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1742 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1743
1744 error->cpu_ring_head[ring->id] = ring->head;
1745 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1746}
1747
8c123e54
BW		 1748
1749static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1750 struct drm_i915_error_state *error,
1751 struct drm_i915_error_ring *ering)
1752{
1753 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1754 struct drm_i915_gem_object *obj;
1755
1756 /* Currently render ring is the only HW context user */
1757 if (ring->id != RCS || !error->ccid)
1758 return;
1759
1760 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1761 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1762 ering->ctx = i915_error_object_create_sized(dev_priv,
1763 obj, 1);
1764 }
1765 }
1766}
1767
52d39a21
CW		 1768static void i915_gem_record_rings(struct drm_device *dev,
1769 struct drm_i915_error_state *error)
1770{
1771 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1772 struct intel_ring_buffer *ring;
52d39a21
CW		 1773 struct drm_i915_gem_request *request;
1774 int i, count;
1775
b4519513 1776 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1777 i915_record_ring_state(dev, error, ring);
1778
1779 error->ring[i].batchbuffer =
1780 i915_error_first_batchbuffer(dev_priv, ring);
1781
1782 error->ring[i].ringbuffer =
1783 i915_error_object_create(dev_priv, ring->obj);
1784
8c123e54
BW		 1785
1786 i915_gem_record_active_context(ring, error, &error->ring[i]);
1787
52d39a21
CW		 1788 count = 0;
1789 list_for_each_entry(request, &ring->request_list, list)
1790 count++;
1791
1792 error->ring[i].num_requests = count;
1793 error->ring[i].requests =
1794 kmalloc(count*sizeof(struct drm_i915_error_request),
1795 GFP_ATOMIC);
1796 if (error->ring[i].requests == NULL) {
1797 error->ring[i].num_requests = 0;
1798 continue;
1799 }
1800
1801 count = 0;
1802 list_for_each_entry(request, &ring->request_list, list) {
1803 struct drm_i915_error_request *erq;
1804
1805 erq = &error->ring[i].requests[count++];
1806 erq->seqno = request->seqno;
1807 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1808 erq->tail = request->tail;
52d39a21
CW		 1809 }
1810 }
1811}
1812
8a905236
JB		 1813/**
1814 * i915_capture_error_state - capture an error record for later analysis
1815 * @dev: drm device
1816 *
1817 * Should be called when an error is detected (either a hang or an error
1818 * interrupt) to capture error state from the time of the error. Fills
1819 * out a structure which becomes available in debugfs for user level tools
1820 * to pick up.
1821 */
63eeaf38
JB		 1822static void i915_capture_error_state(struct drm_device *dev)
1823{
1824 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1825 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1826 struct drm_i915_error_state *error;
1827 unsigned long flags;
9db4a9c7 1828 int i, pipe;
63eeaf38 1829
99584db3
DV		 1830 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1831 error = dev_priv->gpu_error.first_error;
1832 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1833 if (error)
1834 return;
63eeaf38 1835
9db4a9c7 1836 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1837 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1838 if (!error) {
9df30794
CW		 1839 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1840 return;
63eeaf38
JB		 1841 }
1842
5d83d294 1843 DRM_INFO("capturing error event; look for more information in "
2f86f191 1844 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1845 dev->primary->index);
2fa772f3 1846
742cbee8 1847 kref_init(&error->ref);
63eeaf38
JB		 1848 error->eir = I915_READ(EIR);
1849 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1850 if (HAS_HW_CONTEXTS(dev))
1851 error->ccid = I915_READ(CCID);
be998e2e
BW		 1852
1853 if (HAS_PCH_SPLIT(dev))
1854 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1855 else if (IS_VALLEYVIEW(dev))
1856 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1857 else if (IS_GEN2(dev))
1858 error->ier = I915_READ16(IER);
1859 else
1860 error->ier = I915_READ(IER);
1861
0f3b6849
CW		 1862 if (INTEL_INFO(dev)->gen >= 6)
1863 error->derrmr = I915_READ(DERRMR);
1864
1865 if (IS_VALLEYVIEW(dev))
1866 error->forcewake = I915_READ(FORCEWAKE_VLV);
1867 else if (INTEL_INFO(dev)->gen >= 7)
1868 error->forcewake = I915_READ(FORCEWAKE_MT);
1869 else if (INTEL_INFO(dev)->gen == 6)
1870 error->forcewake = I915_READ(FORCEWAKE);
1871
4f3308b9
PZ		 1872 if (!HAS_PCH_SPLIT(dev))
1873 for_each_pipe(pipe)
1874 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1875
33f3f518 1876 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1877 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1878 error->done_reg = I915_READ(DONE_REG);
1879 }
d27b1e0e 1880
71e172e8
BW		 1881 if (INTEL_INFO(dev)->gen == 7)
1882 error->err_int = I915_READ(GEN7_ERR_INT);
1883
050ee91f
BW		 1884 i915_get_extra_instdone(dev, error->extra_instdone);
1885
748ebc60 1886 i915_gem_record_fences(dev, error);
52d39a21 1887 i915_gem_record_rings(dev, error);
9df30794 1888
c724e8a9 1889 /* Record buffers on the active and pinned lists. */
9df30794 1890 error->active_bo = NULL;
c724e8a9 1891 error->pinned_bo = NULL;
9df30794 1892
bcfb2e28
CW		 1893 i = 0;
1894 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1895 i++;
1896 error->active_bo_count = i;
6c085a72 1897 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1898 if (obj->pin_count)
1899 i++;
bcfb2e28 1900 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1901
8e934dbf
CW		 1902 error->active_bo = NULL;
1903 error->pinned_bo = NULL;
bcfb2e28
CW		 1904 if (i) {
1905 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1906 GFP_ATOMIC);
c724e8a9
CW		 1907 if (error->active_bo)
1908 error->pinned_bo =
1909 error->active_bo + error->active_bo_count;
9df30794
CW		 1910 }
1911
c724e8a9
CW		 1912 if (error->active_bo)
1913 error->active_bo_count =
1b50247a
CW		 1914 capture_active_bo(error->active_bo,
1915 error->active_bo_count,
1916 &dev_priv->mm.active_list);
c724e8a9
CW		 1917
1918 if (error->pinned_bo)
1919 error->pinned_bo_count =
1b50247a
CW		 1920 capture_pinned_bo(error->pinned_bo,
1921 error->pinned_bo_count,
6c085a72 1922 &dev_priv->mm.bound_list);
c724e8a9 1923
9df30794
CW		 1924 do_gettimeofday(&error->time);
1925
6ef3d427 1926 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1927 error->display = intel_display_capture_error_state(dev);
6ef3d427 1928
99584db3
DV		 1929 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1930 if (dev_priv->gpu_error.first_error == NULL) {
1931 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1932 error = NULL;
1933 }
99584db3 1934 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1935
1936 if (error)
742cbee8 1937 i915_error_state_free(&error->ref);
9df30794
CW		 1938}
1939
1940void i915_destroy_error_state(struct drm_device *dev)
1941{
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943 struct drm_i915_error_state *error;
6dc0e816 1944 unsigned long flags;
9df30794 1945
99584db3
DV		 1946 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1947 error = dev_priv->gpu_error.first_error;
1948 dev_priv->gpu_error.first_error = NULL;
1949 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1950
1951 if (error)
742cbee8 1952 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1953}
3bd3c932
CW		 1954#else
1955#define i915_capture_error_state(x)
1956#endif
63eeaf38 1957
35aed2e6 1958static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1959{
1960 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1961 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1962 u32 eir = I915_READ(EIR);
050ee91f 1963 int pipe, i;
8a905236 1964
35aed2e6
CW		 1965 if (!eir)
1966 return;
8a905236 1967
a70491cc 1968 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1969
bd9854f9
BW		 1970 i915_get_extra_instdone(dev, instdone);
1971
8a905236
JB		 1972 if (IS_G4X(dev)) {
1973 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1974 u32 ipeir = I915_READ(IPEIR_I965);
1975
a70491cc
JP		 1976 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1977 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1978 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1979 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1980 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1981 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1982 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1983 POSTING_READ(IPEIR_I965);
8a905236
JB		 1984 }
1985 if (eir & GM45_ERROR_PAGE_TABLE) {
1986 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1987 pr_err("page table error\n");
1988 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1989 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1990 POSTING_READ(PGTBL_ER);
8a905236
JB		 1991 }
1992 }
1993
a6c45cf0 1994 if (!IS_GEN2(dev)) {
8a905236
JB		 1995 if (eir & I915_ERROR_PAGE_TABLE) {
1996 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1997 pr_err("page table error\n");
1998 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1999 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2000 POSTING_READ(PGTBL_ER);
8a905236
JB		 2001 }
2002 }
2003
2004 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2005 pr_err("memory refresh error:\n");
9db4a9c7 2006 for_each_pipe(pipe)
a70491cc 2007 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2008 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2009 /* pipestat has already been acked */
2010 }
2011 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2012 pr_err("instruction error\n");
2013 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2014 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2015 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2016 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2017 u32 ipeir = I915_READ(IPEIR);
2018
a70491cc
JP		 2019 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2020 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2021 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2022 I915_WRITE(IPEIR, ipeir);
3143a2bf 2023 POSTING_READ(IPEIR);
8a905236
JB		 2024 } else {
2025 u32 ipeir = I915_READ(IPEIR_I965);
2026
a70491cc
JP		 2027 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2028 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2029 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2030 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2031 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2032 POSTING_READ(IPEIR_I965);
8a905236
JB		 2033 }
2034 }
2035
2036 I915_WRITE(EIR, eir);
3143a2bf 2037 POSTING_READ(EIR);
8a905236
JB		 2038 eir = I915_READ(EIR);
2039 if (eir) {
2040 /*
2041 * some errors might have become stuck,
2042 * mask them.
2043 */
2044 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2045 I915_WRITE(EMR, I915_READ(EMR) | eir);
2046 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2047 }
35aed2e6
CW		 2048}
2049
2050/**
2051 * i915_handle_error - handle an error interrupt
2052 * @dev: drm device
2053 *
2054 * Do some basic checking of regsiter state at error interrupt time and
2055 * dump it to the syslog. Also call i915_capture_error_state() to make
2056 * sure we get a record and make it available in debugfs. Fire a uevent
2057 * so userspace knows something bad happened (should trigger collection
2058 * of a ring dump etc.).
2059 */
527f9e90 2060void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2061{
2062 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2063 struct intel_ring_buffer *ring;
2064 int i;
35aed2e6
CW		 2065
2066 i915_capture_error_state(dev);
2067 i915_report_and_clear_eir(dev);
8a905236 2068
ba1234d1 2069 if (wedged) {
f69061be
DV		 2070 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2071 &dev_priv->gpu_error.reset_counter);
ba1234d1 2072
11ed50ec 2073 /*
1f83fee0
DV		 2074 * Wakeup waiting processes so that the reset work item
2075 * doesn't deadlock trying to grab various locks.
11ed50ec 2076 */
b4519513
CW		 2077 for_each_ring(ring, dev_priv, i)
2078 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2079 }
2080
99584db3 2081 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2082}
2083
21ad8330 2084static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2085{
2086 drm_i915_private_t *dev_priv = dev->dev_private;
2087 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2089 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2090 struct intel_unpin_work *work;
2091 unsigned long flags;
2092 bool stall_detected;
2093
2094 /* Ignore early vblank irqs */
2095 if (intel_crtc == NULL)
2096 return;
2097
2098 spin_lock_irqsave(&dev->event_lock, flags);
2099 work = intel_crtc->unpin_work;
2100
e7d841ca
CW		 2101 if (work == NULL ||
2102 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2103 !work->enable_stall_check) {
4e5359cd
SF		 2104 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2105 spin_unlock_irqrestore(&dev->event_lock, flags);
2106 return;
2107 }
2108
2109 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2110 obj = work->pending_flip_obj;
a6c45cf0 2111 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2112 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 2113 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2114 obj->gtt_offset;
4e5359cd 2115 } else {
9db4a9c7 2116 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 2117 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 2118 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2119 crtc->x * crtc->fb->bits_per_pixel/8);
2120 }
2121
2122 spin_unlock_irqrestore(&dev->event_lock, flags);
2123
2124 if (stall_detected) {
2125 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2126 intel_prepare_page_flip(dev, intel_crtc->plane);
2127 }
2128}
2129
42f52ef8
KP		 2130/* Called from drm generic code, passed 'crtc' which
2131 * we use as a pipe index
2132 */
f71d4af4 2133static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2134{
2135 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2136 unsigned long irqflags;
71e0ffa5 2137
5eddb70b 2138 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2139 return -EINVAL;
0a3e67a4 2140
1ec14ad3 2141 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2142 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2143 i915_enable_pipestat(dev_priv, pipe,
2144 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2145 else
7c463586
KP		 2146 i915_enable_pipestat(dev_priv, pipe,
2147 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2148
2149 /* maintain vblank delivery even in deep C-states */
2150 if (dev_priv->info->gen == 3)
6b26c86d 2151 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2152 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2153
0a3e67a4
JB		 2154 return 0;
2155}
2156
f71d4af4 2157static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2158{
2159 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2160 unsigned long irqflags;
2161
2162 if (!i915_pipe_enabled(dev, pipe))
2163 return -EINVAL;
2164
2165 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2166 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2167 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2168 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2169
2170 return 0;
2171}
2172
f71d4af4 2173static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2174{
2175 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2176 unsigned long irqflags;
2177
2178 if (!i915_pipe_enabled(dev, pipe))
2179 return -EINVAL;
2180
2181 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2182 ironlake_enable_display_irq(dev_priv,
2183 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2184 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2185
2186 return 0;
2187}
2188
7e231dbe
JB		 2189static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2190{
2191 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2192 unsigned long irqflags;
31acc7f5 2193 u32 imr;
7e231dbe
JB		 2194
2195 if (!i915_pipe_enabled(dev, pipe))
2196 return -EINVAL;
2197
2198 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2199 imr = I915_READ(VLV_IMR);
31acc7f5 2200 if (pipe == 0)
7e231dbe 2201 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2202 else
7e231dbe 2203 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2204 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2205 i915_enable_pipestat(dev_priv, pipe,
2206 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2207 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2208
2209 return 0;
2210}
2211
42f52ef8
KP		 2212/* Called from drm generic code, passed 'crtc' which
2213 * we use as a pipe index
2214 */
f71d4af4 2215static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2216{
2217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2218 unsigned long irqflags;
0a3e67a4 2219
1ec14ad3 2220 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2221 if (dev_priv->info->gen == 3)
6b26c86d 2222 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2223
f796cf8f
JB		 2224 i915_disable_pipestat(dev_priv, pipe,
2225 PIPE_VBLANK_INTERRUPT_ENABLE |
2226 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2227 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2228}
2229
f71d4af4 2230static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2231{
2232 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2233 unsigned long irqflags;
2234
2235 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2236 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2237 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2238 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2239}
2240
f71d4af4 2241static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2242{
2243 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2244 unsigned long irqflags;
2245
2246 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2247 ironlake_disable_display_irq(dev_priv,
2248 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2249 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2250}
2251
7e231dbe
JB		 2252static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2253{
2254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2255 unsigned long irqflags;
31acc7f5 2256 u32 imr;
7e231dbe
JB		 2257
2258 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2259 i915_disable_pipestat(dev_priv, pipe,
2260 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2261 imr = I915_READ(VLV_IMR);
31acc7f5 2262 if (pipe == 0)
7e231dbe 2263 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2264 else
7e231dbe 2265 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2266 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2267 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2268}
2269
893eead0
CW		 2270static u32
2271ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2272{
893eead0
CW		 2273 return list_entry(ring->request_list.prev,
2274 struct drm_i915_gem_request, list)->seqno;
2275}
2276
2277static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
2278{
2279 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 2280 i915_seqno_passed(ring->get_seqno(ring, false),
2281 ring_last_seqno(ring))) {
893eead0 2282 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 2283 if (waitqueue_active(&ring->irq_queue)) {
2284 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2285 ring->name);
893eead0
CW		 2286 wake_up_all(&ring->irq_queue);
2287 *err = true;
2288 }
2289 return true;
2290 }
2291 return false;
f65d9421
BG		 2292}
2293
a24a11e6
CW		 2294static bool semaphore_passed(struct intel_ring_buffer *ring)
2295{
2296 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2297 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2298 struct intel_ring_buffer *signaller;
2299 u32 cmd, ipehr, acthd_min;
2300
2301 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2302 if ((ipehr & ~(0x3 << 16)) !=
2303 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2304 return false;
2305
2306 /* ACTHD is likely pointing to the dword after the actual command,
2307 * so scan backwards until we find the MBOX.
2308 */
2309 acthd_min = max((int)acthd - 3 * 4, 0);
2310 do {
2311 cmd = ioread32(ring->virtual_start + acthd);
2312 if (cmd == ipehr)
2313 break;
2314
2315 acthd -= 4;
2316 if (acthd < acthd_min)
2317 return false;
2318 } while (1);
2319
2320 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2321 return i915_seqno_passed(signaller->get_seqno(signaller, false),
2322 ioread32(ring->virtual_start+acthd+4)+1);
2323}
2324
1ec14ad3
CW		 2325static bool kick_ring(struct intel_ring_buffer *ring)
2326{
2327 struct drm_device *dev = ring->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 u32 tmp = I915_READ_CTL(ring);
2330 if (tmp & RING_WAIT) {
2331 DRM_ERROR("Kicking stuck wait on %s\n",
2332 ring->name);
2333 I915_WRITE_CTL(ring, tmp);
2334 return true;
2335 }
a24a11e6
CW		 2336
2337 if (INTEL_INFO(dev)->gen >= 6 &&
2338 tmp & RING_WAIT_SEMAPHORE &&
2339 semaphore_passed(ring)) {
2340 DRM_ERROR("Kicking stuck semaphore on %s\n",
2341 ring->name);
2342 I915_WRITE_CTL(ring, tmp);
2343 return true;
2344 }
1ec14ad3
CW		 2345 return false;
2346}
2347
d1e61e7f
CW		 2348static bool i915_hangcheck_hung(struct drm_device *dev)
2349{
2350 drm_i915_private_t *dev_priv = dev->dev_private;
2351
99584db3 2352 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 2353 bool hung = true;
2354
d1e61e7f
CW		 2355 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2356 i915_handle_error(dev, true);
2357
2358 if (!IS_GEN2(dev)) {
b4519513
CW		 2359 struct intel_ring_buffer *ring;
2360 int i;
2361
d1e61e7f
CW		 2362 /* Is the chip hanging on a WAIT_FOR_EVENT?
2363 * If so we can simply poke the RB_WAIT bit
2364 * and break the hang. This should work on
2365 * all but the second generation chipsets.
2366 */
b4519513
CW		 2367 for_each_ring(ring, dev_priv, i)
2368 hung &= !kick_ring(ring);
d1e61e7f
CW		 2369 }
2370
b4519513 2371 return hung;
d1e61e7f
CW		 2372 }
2373
2374 return false;
2375}
2376
f65d9421
BG		 2377/**
2378 * This is called when the chip hasn't reported back with completed
2379 * batchbuffers in a long time. The first time this is called we simply record
2380 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2381 * again, we assume the chip is wedged and try to fix it.
2382 */
2383void i915_hangcheck_elapsed(unsigned long data)
2384{
2385 struct drm_device *dev = (struct drm_device *)data;
2386 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 2387 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 2388 struct intel_ring_buffer *ring;
2389 bool err = false, idle;
2390 int i;
893eead0 2391
3e0dc6b0
BW		 2392 if (!i915_enable_hangcheck)
2393 return;
2394
b4519513
CW		 2395 memset(acthd, 0, sizeof(acthd));
2396 idle = true;
2397 for_each_ring(ring, dev_priv, i) {
2398 idle &= i915_hangcheck_ring_idle(ring, &err);
2399 acthd[i] = intel_ring_get_active_head(ring);
2400 }
2401
893eead0 2402 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 2403 if (idle) {
d1e61e7f
CW		 2404 if (err) {
2405 if (i915_hangcheck_hung(dev))
2406 return;
2407
893eead0 2408 goto repeat;
d1e61e7f
CW		 2409 }
2410
99584db3 2411 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 2412 return;
2413 }
b9201c14 2414
bd9854f9 2415 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 2416 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
2417 sizeof(acthd)) == 0 &&
2418 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
2419 sizeof(instdone)) == 0) {
d1e61e7f 2420 if (i915_hangcheck_hung(dev))
cbb465e7 2421 return;
cbb465e7 2422 } else {
99584db3 2423 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 2424
99584db3
DV		 2425 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2426 sizeof(acthd));
2427 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2428 sizeof(instdone));
cbb465e7 2429 }
f65d9421 2430
893eead0 2431repeat:
f65d9421 2432 /* Reset timer case chip hangs without another request being added */
99584db3 2433 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 2434 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2435}
2436
1da177e4
LT		 2437/* drm_dma.h hooks
2438*/
f71d4af4 2439static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2440{
2441 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2442
4697995b
JB		 2443 atomic_set(&dev_priv->irq_received, 0);
2444
036a4a7d 2445 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2446
036a4a7d
ZW		 2447 /* XXX hotplug from PCH */
2448
2449 I915_WRITE(DEIMR, 0xffffffff);
2450 I915_WRITE(DEIER, 0x0);
3143a2bf 2451 POSTING_READ(DEIER);
036a4a7d
ZW		 2452
2453 /* and GT */
2454 I915_WRITE(GTIMR, 0xffffffff);
2455 I915_WRITE(GTIER, 0x0);
3143a2bf 2456 POSTING_READ(GTIER);
c650156a 2457
ab5c608b
BW		 2458 if (HAS_PCH_NOP(dev))
2459 return;
2460
c650156a
ZW		 2461 /* south display irq */
2462 I915_WRITE(SDEIMR, 0xffffffff);
82a28bcf
DV		 2463 /*
2464 * SDEIER is also touched by the interrupt handler to work around missed
2465 * PCH interrupts. Hence we can't update it after the interrupt handler
2466 * is enabled - instead we unconditionally enable all PCH interrupt
2467 * sources here, but then only unmask them as needed with SDEIMR.
2468 */
2469 I915_WRITE(SDEIER, 0xffffffff);
3143a2bf 2470 POSTING_READ(SDEIER);
036a4a7d
ZW		 2471}
2472
7e231dbe
JB		 2473static void valleyview_irq_preinstall(struct drm_device *dev)
2474{
2475 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2476 int pipe;
2477
2478 atomic_set(&dev_priv->irq_received, 0);
2479
7e231dbe
JB		 2480 /* VLV magic */
2481 I915_WRITE(VLV_IMR, 0);
2482 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2483 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2484 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2485
7e231dbe
JB		 2486 /* and GT */
2487 I915_WRITE(GTIIR, I915_READ(GTIIR));
2488 I915_WRITE(GTIIR, I915_READ(GTIIR));
2489 I915_WRITE(GTIMR, 0xffffffff);
2490 I915_WRITE(GTIER, 0x0);
2491 POSTING_READ(GTIER);
2492
2493 I915_WRITE(DPINVGTT, 0xff);
2494
2495 I915_WRITE(PORT_HOTPLUG_EN, 0);
2496 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2497 for_each_pipe(pipe)
2498 I915_WRITE(PIPESTAT(pipe), 0xffff);
2499 I915_WRITE(VLV_IIR, 0xffffffff);
2500 I915_WRITE(VLV_IMR, 0xffffffff);
2501 I915_WRITE(VLV_IER, 0x0);
2502 POSTING_READ(VLV_IER);
2503}
2504
82a28bcf 2505static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2506{
2507 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2508 struct drm_mode_config *mode_config = &dev->mode_config;
2509 struct intel_encoder *intel_encoder;
2510 u32 mask = ~I915_READ(SDEIMR);
2511 u32 hotplug;
2512
2513 if (HAS_PCH_IBX(dev)) {
995e6b3d 2514 mask &= ~SDE_HOTPLUG_MASK;
82a28bcf 2515 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2516 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2517 mask |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2518 } else {
995e6b3d 2519 mask &= ~SDE_HOTPLUG_MASK_CPT;
82a28bcf 2520 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed
EE		 2521 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2522 mask |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2523 }
7fe0b973 2524
82a28bcf
DV		 2525 I915_WRITE(SDEIMR, ~mask);
2526
2527 /*
2528 * Enable digital hotplug on the PCH, and configure the DP short pulse
2529 * duration to 2ms (which is the minimum in the Display Port spec)
2530 *
2531 * This register is the same on all known PCH chips.
2532 */
7fe0b973
KP		 2533 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2534 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2535 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2536 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2537 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2538 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2539}
2540
d46da437
PZ		 2541static void ibx_irq_postinstall(struct drm_device *dev)
2542{
2543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2544 u32 mask;
e5868a31 2545
8664281b
PZ		 2546 if (HAS_PCH_IBX(dev)) {
2547 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2548 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2549 } else {
2550 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2551
2552 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2553 }
ab5c608b
BW		 2554
2555 if (HAS_PCH_NOP(dev))
2556 return;
2557
d46da437
PZ		 2558 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2559 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2560}
2561
f71d4af4 2562static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 2563{
2564 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2565 /* enable kind of interrupts always enabled */
013d5aa2 2566 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2567 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2568 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2569 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
1ec14ad3 2570 u32 render_irqs;
036a4a7d 2571
1ec14ad3 2572 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2573
2574 /* should always can generate irq */
2575 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 2576 I915_WRITE(DEIMR, dev_priv->irq_mask);
2577 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 2578 POSTING_READ(DEIER);
036a4a7d 2579
1ec14ad3 2580 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2581
2582 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2583 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2584
1ec14ad3
CW		 2585 if (IS_GEN6(dev))
2586 render_irqs =
2587 GT_USER_INTERRUPT |
e2a1e2f0
BW		 2588 GEN6_BSD_USER_INTERRUPT |
2589 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 2590 else
2591 render_irqs =
88f23b8f 2592 GT_USER_INTERRUPT |
c6df541c 2593 GT_PIPE_NOTIFY |
1ec14ad3
CW		 2594 GT_BSD_USER_INTERRUPT;
2595 I915_WRITE(GTIER, render_irqs);
3143a2bf 2596 POSTING_READ(GTIER);
036a4a7d 2597
d46da437 2598 ibx_irq_postinstall(dev);
7fe0b973 2599
f97108d1
JB		 2600 if (IS_IRONLAKE_M(dev)) {
2601 /* Clear & enable PCU event interrupts */
2602 I915_WRITE(DEIIR, DE_PCU_EVENT);
2603 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2604 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2605 }
2606
036a4a7d
ZW		 2607 return 0;
2608}
2609
f71d4af4 2610static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2611{
2612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2613 /* enable kind of interrupts always enabled */
b615b57a
CW		 2614 u32 display_mask =
2615 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2616 DE_PLANEC_FLIP_DONE_IVB |
2617 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2618 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2619 DE_AUX_CHANNEL_A_IVB |
2620 DE_ERR_INT_IVB;
b1f14ad0 2621 u32 render_irqs;
b1f14ad0 2622
b1f14ad0
JB		 2623 dev_priv->irq_mask = ~display_mask;
2624
2625 /* should always can generate irq */
8664281b 2626 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2627 I915_WRITE(DEIIR, I915_READ(DEIIR));
2628 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2629 I915_WRITE(DEIER,
2630 display_mask |
2631 DE_PIPEC_VBLANK_IVB |
2632 DE_PIPEB_VBLANK_IVB |
2633 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2634 POSTING_READ(DEIER);
2635
15b9f80e 2636 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2637
2638 I915_WRITE(GTIIR, I915_READ(GTIIR));
2639 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2640
e2a1e2f0 2641 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2642 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2643 I915_WRITE(GTIER, render_irqs);
2644 POSTING_READ(GTIER);
2645
d46da437 2646 ibx_irq_postinstall(dev);
7fe0b973 2647
b1f14ad0
JB		 2648 return 0;
2649}
2650
7e231dbe
JB		 2651static int valleyview_irq_postinstall(struct drm_device *dev)
2652{
2653 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2654 u32 enable_mask;
31acc7f5 2655 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2656 u32 render_irqs;
7e231dbe
JB		 2657
2658 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2659 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2660 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2661 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2662 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2663
31acc7f5
JB		 2664 /*
2665 *Leave vblank interrupts masked initially. enable/disable will
2666 * toggle them based on usage.
2667 */
2668 dev_priv->irq_mask = (~enable_mask) |
2669 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2670 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2671
20afbda2
DV		 2672 I915_WRITE(PORT_HOTPLUG_EN, 0);
2673 POSTING_READ(PORT_HOTPLUG_EN);
2674
7e231dbe
JB		 2675 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2676 I915_WRITE(VLV_IER, enable_mask);
2677 I915_WRITE(VLV_IIR, 0xffffffff);
2678 I915_WRITE(PIPESTAT(0), 0xffff);
2679 I915_WRITE(PIPESTAT(1), 0xffff);
2680 POSTING_READ(VLV_IER);
2681
31acc7f5 2682 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2683 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2684 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2685
7e231dbe
JB		 2686 I915_WRITE(VLV_IIR, 0xffffffff);
2687 I915_WRITE(VLV_IIR, 0xffffffff);
2688
7e231dbe 2689 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2690 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2691
2692 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2693 GEN6_BLITTER_USER_INTERRUPT;
2694 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2695 POSTING_READ(GTIER);
2696
2697 /* ack & enable invalid PTE error interrupts */
2698#if 0 /* FIXME: add support to irq handler for checking these bits */
2699 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2700 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2701#endif
2702
2703 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2704
2705 return 0;
2706}
2707
7e231dbe
JB		 2708static void valleyview_irq_uninstall(struct drm_device *dev)
2709{
2710 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2711 int pipe;
2712
2713 if (!dev_priv)
2714 return;
2715
ac4c16c5
EE		 2716 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2717
7e231dbe
JB		 2718 for_each_pipe(pipe)
2719 I915_WRITE(PIPESTAT(pipe), 0xffff);
2720
2721 I915_WRITE(HWSTAM, 0xffffffff);
2722 I915_WRITE(PORT_HOTPLUG_EN, 0);
2723 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2724 for_each_pipe(pipe)
2725 I915_WRITE(PIPESTAT(pipe), 0xffff);
2726 I915_WRITE(VLV_IIR, 0xffffffff);
2727 I915_WRITE(VLV_IMR, 0xffffffff);
2728 I915_WRITE(VLV_IER, 0x0);
2729 POSTING_READ(VLV_IER);
2730}
2731
f71d4af4 2732static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2733{
2734 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2735
2736 if (!dev_priv)
2737 return;
2738
ac4c16c5
EE		 2739 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2740
036a4a7d
ZW		 2741 I915_WRITE(HWSTAM, 0xffffffff);
2742
2743 I915_WRITE(DEIMR, 0xffffffff);
2744 I915_WRITE(DEIER, 0x0);
2745 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2746 if (IS_GEN7(dev))
2747 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2748
2749 I915_WRITE(GTIMR, 0xffffffff);
2750 I915_WRITE(GTIER, 0x0);
2751 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2752
ab5c608b
BW		 2753 if (HAS_PCH_NOP(dev))
2754 return;
2755
192aac1f
KP		 2756 I915_WRITE(SDEIMR, 0xffffffff);
2757 I915_WRITE(SDEIER, 0x0);
2758 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2759 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2760 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2761}
2762
a266c7d5 2763static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2764{
2765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2766 int pipe;
91e3738e 2767
a266c7d5 2768 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2769
9db4a9c7
JB		 2770 for_each_pipe(pipe)
2771 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2772 I915_WRITE16(IMR, 0xffff);
2773 I915_WRITE16(IER, 0x0);
2774 POSTING_READ16(IER);
c2798b19
CW		 2775}
2776
2777static int i8xx_irq_postinstall(struct drm_device *dev)
2778{
2779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2780
c2798b19
CW		 2781 I915_WRITE16(EMR,
2782 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2783
2784 /* Unmask the interrupts that we always want on. */
2785 dev_priv->irq_mask =
2786 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2787 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2788 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2789 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2790 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2791 I915_WRITE16(IMR, dev_priv->irq_mask);
2792
2793 I915_WRITE16(IER,
2794 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2795 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2796 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2797 I915_USER_INTERRUPT);
2798 POSTING_READ16(IER);
2799
2800 return 0;
2801}
2802
90a72f87
VS		 2803/*
2804 * Returns true when a page flip has completed.
2805 */
2806static bool i8xx_handle_vblank(struct drm_device *dev,
2807 int pipe, u16 iir)
2808{
2809 drm_i915_private_t *dev_priv = dev->dev_private;
2810 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2811
2812 if (!drm_handle_vblank(dev, pipe))
2813 return false;
2814
2815 if ((iir & flip_pending) == 0)
2816 return false;
2817
2818 intel_prepare_page_flip(dev, pipe);
2819
2820 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2821 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2822 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2823 * the flip is completed (no longer pending). Since this doesn't raise
2824 * an interrupt per se, we watch for the change at vblank.
2825 */
2826 if (I915_READ16(ISR) & flip_pending)
2827 return false;
2828
2829 intel_finish_page_flip(dev, pipe);
2830
2831 return true;
2832}
2833
ff1f525e 2834static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2835{
2836 struct drm_device *dev = (struct drm_device *) arg;
2837 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2838 u16 iir, new_iir;
2839 u32 pipe_stats[2];
2840 unsigned long irqflags;
2841 int irq_received;
2842 int pipe;
2843 u16 flip_mask =
2844 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2845 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2846
2847 atomic_inc(&dev_priv->irq_received);
2848
2849 iir = I915_READ16(IIR);
2850 if (iir == 0)
2851 return IRQ_NONE;
2852
2853 while (iir & ~flip_mask) {
2854 /* Can't rely on pipestat interrupt bit in iir as it might
2855 * have been cleared after the pipestat interrupt was received.
2856 * It doesn't set the bit in iir again, but it still produces
2857 * interrupts (for non-MSI).
2858 */
2859 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2860 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2861 i915_handle_error(dev, false);
2862
2863 for_each_pipe(pipe) {
2864 int reg = PIPESTAT(pipe);
2865 pipe_stats[pipe] = I915_READ(reg);
2866
2867 /*
2868 * Clear the PIPE*STAT regs before the IIR
2869 */
2870 if (pipe_stats[pipe] & 0x8000ffff) {
2871 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2872 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2873 pipe_name(pipe));
2874 I915_WRITE(reg, pipe_stats[pipe]);
2875 irq_received = 1;
2876 }
2877 }
2878 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2879
2880 I915_WRITE16(IIR, iir & ~flip_mask);
2881 new_iir = I915_READ16(IIR); /* Flush posted writes */
2882
d05c617e 2883 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2884
2885 if (iir & I915_USER_INTERRUPT)
2886 notify_ring(dev, &dev_priv->ring[RCS]);
2887
2888 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2889 i8xx_handle_vblank(dev, 0, iir))
2890 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2891
2892 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2893 i8xx_handle_vblank(dev, 1, iir))
2894 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2895
2896 iir = new_iir;
2897 }
2898
2899 return IRQ_HANDLED;
2900}
2901
2902static void i8xx_irq_uninstall(struct drm_device * dev)
2903{
2904 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2905 int pipe;
2906
c2798b19
CW		 2907 for_each_pipe(pipe) {
2908 /* Clear enable bits; then clear status bits */
2909 I915_WRITE(PIPESTAT(pipe), 0);
2910 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2911 }
2912 I915_WRITE16(IMR, 0xffff);
2913 I915_WRITE16(IER, 0x0);
2914 I915_WRITE16(IIR, I915_READ16(IIR));
2915}
2916
a266c7d5
CW		 2917static void i915_irq_preinstall(struct drm_device * dev)
2918{
2919 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2920 int pipe;
2921
2922 atomic_set(&dev_priv->irq_received, 0);
2923
2924 if (I915_HAS_HOTPLUG(dev)) {
2925 I915_WRITE(PORT_HOTPLUG_EN, 0);
2926 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2927 }
2928
00d98ebd 2929 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2930 for_each_pipe(pipe)
2931 I915_WRITE(PIPESTAT(pipe), 0);
2932 I915_WRITE(IMR, 0xffffffff);
2933 I915_WRITE(IER, 0x0);
2934 POSTING_READ(IER);
2935}
2936
2937static int i915_irq_postinstall(struct drm_device *dev)
2938{
2939 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2940 u32 enable_mask;
a266c7d5 2941
38bde180
CW		 2942 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2943
2944 /* Unmask the interrupts that we always want on. */
2945 dev_priv->irq_mask =
2946 ~(I915_ASLE_INTERRUPT |
2947 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2948 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2949 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2950 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2951 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2952
2953 enable_mask =
2954 I915_ASLE_INTERRUPT |
2955 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2956 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2957 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2958 I915_USER_INTERRUPT;
2959
a266c7d5 2960 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2961 I915_WRITE(PORT_HOTPLUG_EN, 0);
2962 POSTING_READ(PORT_HOTPLUG_EN);
2963
a266c7d5
CW		 2964 /* Enable in IER... */
2965 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2966 /* and unmask in IMR */
2967 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2968 }
2969
a266c7d5
CW		 2970 I915_WRITE(IMR, dev_priv->irq_mask);
2971 I915_WRITE(IER, enable_mask);
2972 POSTING_READ(IER);
2973
f49e38dd 2974 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2975
2976 return 0;
2977}
2978
90a72f87
VS		 2979/*
2980 * Returns true when a page flip has completed.
2981 */
2982static bool i915_handle_vblank(struct drm_device *dev,
2983 int plane, int pipe, u32 iir)
2984{
2985 drm_i915_private_t *dev_priv = dev->dev_private;
2986 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2987
2988 if (!drm_handle_vblank(dev, pipe))
2989 return false;
2990
2991 if ((iir & flip_pending) == 0)
2992 return false;
2993
2994 intel_prepare_page_flip(dev, plane);
2995
2996 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2997 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2998 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2999 * the flip is completed (no longer pending). Since this doesn't raise
3000 * an interrupt per se, we watch for the change at vblank.
3001 */
3002 if (I915_READ(ISR) & flip_pending)
3003 return false;
3004
3005 intel_finish_page_flip(dev, pipe);
3006
3007 return true;
3008}
3009
ff1f525e 3010static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3011{
3012 struct drm_device *dev = (struct drm_device *) arg;
3013 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3014 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3015 unsigned long irqflags;
38bde180
CW		 3016 u32 flip_mask =
3017 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3018 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3019 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3020
3021 atomic_inc(&dev_priv->irq_received);
3022
3023 iir = I915_READ(IIR);
38bde180
CW		 3024 do {
3025 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3026 bool blc_event = false;
a266c7d5
CW		 3027
3028 /* Can't rely on pipestat interrupt bit in iir as it might
3029 * have been cleared after the pipestat interrupt was received.
3030 * It doesn't set the bit in iir again, but it still produces
3031 * interrupts (for non-MSI).
3032 */
3033 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3034 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3035 i915_handle_error(dev, false);
3036
3037 for_each_pipe(pipe) {
3038 int reg = PIPESTAT(pipe);
3039 pipe_stats[pipe] = I915_READ(reg);
3040
38bde180 3041 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3042 if (pipe_stats[pipe] & 0x8000ffff) {
3043 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3044 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3045 pipe_name(pipe));
3046 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3047 irq_received = true;
a266c7d5
CW		 3048 }
3049 }
3050 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3051
3052 if (!irq_received)
3053 break;
3054
a266c7d5
CW		 3055 /* Consume port. Then clear IIR or we'll miss events */
3056 if ((I915_HAS_HOTPLUG(dev)) &&
3057 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3058 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3059 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3060
3061 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3062 hotplug_status);
b543fb04 3063 if (hotplug_trigger) {
cd569aed
EE		 3064 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
3065 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3066 queue_work(dev_priv->wq,
3067 &dev_priv->hotplug_work);
b543fb04 3068 }
a266c7d5 3069 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3070 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3071 }
3072
38bde180 3073 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3074 new_iir = I915_READ(IIR); /* Flush posted writes */
3075
a266c7d5
CW		 3076 if (iir & I915_USER_INTERRUPT)
3077 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3078
a266c7d5 3079 for_each_pipe(pipe) {
38bde180
CW		 3080 int plane = pipe;
3081 if (IS_MOBILE(dev))
3082 plane = !plane;
90a72f87 3083
8291ee90 3084 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3085 i915_handle_vblank(dev, plane, pipe, iir))
3086 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3087
3088 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3089 blc_event = true;
3090 }
3091
a266c7d5
CW		 3092 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3093 intel_opregion_asle_intr(dev);
3094
3095 /* With MSI, interrupts are only generated when iir
3096 * transitions from zero to nonzero. If another bit got
3097 * set while we were handling the existing iir bits, then
3098 * we would never get another interrupt.
3099 *
3100 * This is fine on non-MSI as well, as if we hit this path
3101 * we avoid exiting the interrupt handler only to generate
3102 * another one.
3103 *
3104 * Note that for MSI this could cause a stray interrupt report
3105 * if an interrupt landed in the time between writing IIR and
3106 * the posting read. This should be rare enough to never
3107 * trigger the 99% of 100,000 interrupts test for disabling
3108 * stray interrupts.
3109 */
38bde180 3110 ret = IRQ_HANDLED;
a266c7d5 3111 iir = new_iir;
38bde180 3112 } while (iir & ~flip_mask);
a266c7d5 3113
d05c617e 3114 i915_update_dri1_breadcrumb(dev);
8291ee90 3115
a266c7d5
CW		 3116 return ret;
3117}
3118
3119static void i915_irq_uninstall(struct drm_device * dev)
3120{
3121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3122 int pipe;
3123
ac4c16c5
EE		 3124 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3125
a266c7d5
CW		 3126 if (I915_HAS_HOTPLUG(dev)) {
3127 I915_WRITE(PORT_HOTPLUG_EN, 0);
3128 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3129 }
3130
00d98ebd 3131 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3132 for_each_pipe(pipe) {
3133 /* Clear enable bits; then clear status bits */
a266c7d5 3134 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3135 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3136 }
a266c7d5
CW		 3137 I915_WRITE(IMR, 0xffffffff);
3138 I915_WRITE(IER, 0x0);
3139
a266c7d5
CW		 3140 I915_WRITE(IIR, I915_READ(IIR));
3141}
3142
3143static void i965_irq_preinstall(struct drm_device * dev)
3144{
3145 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3146 int pipe;
3147
3148 atomic_set(&dev_priv->irq_received, 0);
3149
adca4730
CW		 3150 I915_WRITE(PORT_HOTPLUG_EN, 0);
3151 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3152
3153 I915_WRITE(HWSTAM, 0xeffe);
3154 for_each_pipe(pipe)
3155 I915_WRITE(PIPESTAT(pipe), 0);
3156 I915_WRITE(IMR, 0xffffffff);
3157 I915_WRITE(IER, 0x0);
3158 POSTING_READ(IER);
3159}
3160
3161static int i965_irq_postinstall(struct drm_device *dev)
3162{
3163 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3164 u32 enable_mask;
a266c7d5
CW		 3165 u32 error_mask;
3166
a266c7d5 3167 /* Unmask the interrupts that we always want on. */
bbba0a97 3168 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3169 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3170 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3171 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3172 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3173 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3174 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3175
3176 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3177 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3178 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3179 enable_mask |= I915_USER_INTERRUPT;
3180
3181 if (IS_G4X(dev))
3182 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3183
515ac2bb 3184 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 3185
a266c7d5
CW		 3186 /*
3187 * Enable some error detection, note the instruction error mask
3188 * bit is reserved, so we leave it masked.
3189 */
3190 if (IS_G4X(dev)) {
3191 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3192 GM45_ERROR_MEM_PRIV |
3193 GM45_ERROR_CP_PRIV |
3194 I915_ERROR_MEMORY_REFRESH);
3195 } else {
3196 error_mask = ~(I915_ERROR_PAGE_TABLE |
3197 I915_ERROR_MEMORY_REFRESH);
3198 }
3199 I915_WRITE(EMR, error_mask);
3200
3201 I915_WRITE(IMR, dev_priv->irq_mask);
3202 I915_WRITE(IER, enable_mask);
3203 POSTING_READ(IER);
3204
20afbda2
DV		 3205 I915_WRITE(PORT_HOTPLUG_EN, 0);
3206 POSTING_READ(PORT_HOTPLUG_EN);
3207
f49e38dd 3208 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3209
3210 return 0;
3211}
3212
bac56d5b 3213static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3214{
3215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3216 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3217 struct intel_encoder *intel_encoder;
20afbda2
DV		 3218 u32 hotplug_en;
3219
bac56d5b
EE		 3220 if (I915_HAS_HOTPLUG(dev)) {
3221 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3222 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3223 /* Note HDMI and DP share hotplug bits */
e5868a31 3224 /* enable bits are the same for all generations */
cd569aed
EE		 3225 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3226 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3227 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3228 /* Programming the CRT detection parameters tends
3229 to generate a spurious hotplug event about three
3230 seconds later. So just do it once.
3231 */
3232 if (IS_G4X(dev))
3233 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3234 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3235 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3236
bac56d5b
EE		 3237 /* Ignore TV since it's buggy */
3238 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3239 }
a266c7d5
CW		 3240}
3241
ff1f525e 3242static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3243{
3244 struct drm_device *dev = (struct drm_device *) arg;
3245 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3246 u32 iir, new_iir;
3247 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3248 unsigned long irqflags;
3249 int irq_received;
3250 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3251 u32 flip_mask =
3252 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3253 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3254
3255 atomic_inc(&dev_priv->irq_received);
3256
3257 iir = I915_READ(IIR);
3258
a266c7d5 3259 for (;;) {
2c8ba29f
CW		 3260 bool blc_event = false;
3261
21ad8330 3262 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3263
3264 /* Can't rely on pipestat interrupt bit in iir as it might
3265 * have been cleared after the pipestat interrupt was received.
3266 * It doesn't set the bit in iir again, but it still produces
3267 * interrupts (for non-MSI).
3268 */
3269 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3270 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3271 i915_handle_error(dev, false);
3272
3273 for_each_pipe(pipe) {
3274 int reg = PIPESTAT(pipe);
3275 pipe_stats[pipe] = I915_READ(reg);
3276
3277 /*
3278 * Clear the PIPE*STAT regs before the IIR
3279 */
3280 if (pipe_stats[pipe] & 0x8000ffff) {
3281 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3282 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3283 pipe_name(pipe));
3284 I915_WRITE(reg, pipe_stats[pipe]);
3285 irq_received = 1;
3286 }
3287 }
3288 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3289
3290 if (!irq_received)
3291 break;
3292
3293 ret = IRQ_HANDLED;
3294
3295 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3296 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3297 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3298 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3299 HOTPLUG_INT_STATUS_G4X :
3300 HOTPLUG_INT_STATUS_I965);
a266c7d5
CW		 3301
3302 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3303 hotplug_status);
b543fb04 3304 if (hotplug_trigger) {
cd569aed
EE		 3305 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
3306 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
3307 i915_hpd_irq_setup(dev);
a266c7d5
CW		 3308 queue_work(dev_priv->wq,
3309 &dev_priv->hotplug_work);
b543fb04 3310 }
a266c7d5
CW		 3311 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3312 I915_READ(PORT_HOTPLUG_STAT);
3313 }
3314
21ad8330 3315 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3316 new_iir = I915_READ(IIR); /* Flush posted writes */
3317
a266c7d5
CW		 3318 if (iir & I915_USER_INTERRUPT)
3319 notify_ring(dev, &dev_priv->ring[RCS]);
3320 if (iir & I915_BSD_USER_INTERRUPT)
3321 notify_ring(dev, &dev_priv->ring[VCS]);
3322
a266c7d5 3323 for_each_pipe(pipe) {
2c8ba29f 3324 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3325 i915_handle_vblank(dev, pipe, pipe, iir))
3326 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3327
3328 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3329 blc_event = true;
3330 }
3331
3332
3333 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3334 intel_opregion_asle_intr(dev);
3335
515ac2bb
DV		 3336 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3337 gmbus_irq_handler(dev);
3338
a266c7d5
CW		 3339 /* With MSI, interrupts are only generated when iir
3340 * transitions from zero to nonzero. If another bit got
3341 * set while we were handling the existing iir bits, then
3342 * we would never get another interrupt.
3343 *
3344 * This is fine on non-MSI as well, as if we hit this path
3345 * we avoid exiting the interrupt handler only to generate
3346 * another one.
3347 *
3348 * Note that for MSI this could cause a stray interrupt report
3349 * if an interrupt landed in the time between writing IIR and
3350 * the posting read. This should be rare enough to never
3351 * trigger the 99% of 100,000 interrupts test for disabling
3352 * stray interrupts.
3353 */
3354 iir = new_iir;
3355 }
3356
d05c617e 3357 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3358
a266c7d5
CW		 3359 return ret;
3360}
3361
3362static void i965_irq_uninstall(struct drm_device * dev)
3363{
3364 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3365 int pipe;
3366
3367 if (!dev_priv)
3368 return;
3369
ac4c16c5
EE		 3370 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3371
adca4730
CW		 3372 I915_WRITE(PORT_HOTPLUG_EN, 0);
3373 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3374
3375 I915_WRITE(HWSTAM, 0xffffffff);
3376 for_each_pipe(pipe)
3377 I915_WRITE(PIPESTAT(pipe), 0);
3378 I915_WRITE(IMR, 0xffffffff);
3379 I915_WRITE(IER, 0x0);
3380
3381 for_each_pipe(pipe)
3382 I915_WRITE(PIPESTAT(pipe),
3383 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3384 I915_WRITE(IIR, I915_READ(IIR));
3385}
3386
ac4c16c5
EE		 3387static void i915_reenable_hotplug_timer_func(unsigned long data)
3388{
3389 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3390 struct drm_device *dev = dev_priv->dev;
3391 struct drm_mode_config *mode_config = &dev->mode_config;
3392 unsigned long irqflags;
3393 int i;
3394
3395 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3396 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3397 struct drm_connector *connector;
3398
3399 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3400 continue;
3401
3402 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3403
3404 list_for_each_entry(connector, &mode_config->connector_list, head) {
3405 struct intel_connector *intel_connector = to_intel_connector(connector);
3406
3407 if (intel_connector->encoder->hpd_pin == i) {
3408 if (connector->polled != intel_connector->polled)
3409 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3410 drm_get_connector_name(connector));
3411 connector->polled = intel_connector->polled;
3412 if (!connector->polled)
3413 connector->polled = DRM_CONNECTOR_POLL_HPD;
3414 }
3415 }
3416 }
3417 if (dev_priv->display.hpd_irq_setup)
3418 dev_priv->display.hpd_irq_setup(dev);
3419 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3420}
3421
f71d4af4
JB		 3422void intel_irq_init(struct drm_device *dev)
3423{
8b2e326d
CW		 3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425
3426 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3427 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3428 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3429 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3430
99584db3
DV		 3431 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3432 i915_hangcheck_elapsed,
61bac78e 3433 (unsigned long) dev);
ac4c16c5
EE		 3434 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3435 (unsigned long) dev_priv);
61bac78e 3436
97a19a24 3437 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3438
f71d4af4
JB		 3439 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3440 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3441 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3442 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3443 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3444 }
3445
c3613de9
KP		 3446 if (drm_core_check_feature(dev, DRIVER_MODESET))
3447 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3448 else
3449 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3450 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3451
7e231dbe
JB		 3452 if (IS_VALLEYVIEW(dev)) {
3453 dev->driver->irq_handler = valleyview_irq_handler;
3454 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3455 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3456 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3457 dev->driver->enable_vblank = valleyview_enable_vblank;
3458 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3459 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3460 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 3461 /* Share pre & uninstall handlers with ILK/SNB */
3462 dev->driver->irq_handler = ivybridge_irq_handler;
3463 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3464 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3465 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3466 dev->driver->enable_vblank = ivybridge_enable_vblank;
3467 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3468 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3469 } else if (HAS_PCH_SPLIT(dev)) {
3470 dev->driver->irq_handler = ironlake_irq_handler;
3471 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3472 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3473 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3474 dev->driver->enable_vblank = ironlake_enable_vblank;
3475 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3476 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3477 } else {
c2798b19
CW		 3478 if (INTEL_INFO(dev)->gen == 2) {
3479 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3480 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3481 dev->driver->irq_handler = i8xx_irq_handler;
3482 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3483 } else if (INTEL_INFO(dev)->gen == 3) {
3484 dev->driver->irq_preinstall = i915_irq_preinstall;
3485 dev->driver->irq_postinstall = i915_irq_postinstall;
3486 dev->driver->irq_uninstall = i915_irq_uninstall;
3487 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3488 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3489 } else {
a266c7d5
CW		 3490 dev->driver->irq_preinstall = i965_irq_preinstall;
3491 dev->driver->irq_postinstall = i965_irq_postinstall;
3492 dev->driver->irq_uninstall = i965_irq_uninstall;
3493 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3494 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3495 }
f71d4af4
JB		 3496 dev->driver->enable_vblank = i915_enable_vblank;
3497 dev->driver->disable_vblank = i915_disable_vblank;
3498 }
3499}
20afbda2
DV		 3500
3501void intel_hpd_init(struct drm_device *dev)
3502{
3503 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3504 struct drm_mode_config *mode_config = &dev->mode_config;
3505 struct drm_connector *connector;
3506 int i;
20afbda2 3507
821450c6
EE		 3508 for (i = 1; i < HPD_NUM_PINS; i++) {
3509 dev_priv->hpd_stats[i].hpd_cnt = 0;
3510 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3511 }
3512 list_for_each_entry(connector, &mode_config->connector_list, head) {
3513 struct intel_connector *intel_connector = to_intel_connector(connector);
3514 connector->polled = intel_connector->polled;
3515 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3516 connector->polled = DRM_CONNECTOR_POLL_HPD;
3517 }
20afbda2
DV		 3518 if (dev_priv->display.hpd_irq_setup)
3519 dev_priv->display.hpd_irq_setup(dev);
3520}
Linux kernel - Deliverables
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