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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
e5868a31 EE |
40 | static const u32 hpd_ibx[] = { |
41 | [HPD_CRT] = SDE_CRT_HOTPLUG, | |
42 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
43 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
44 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
45 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
46 | }; | |
47 | ||
48 | static const u32 hpd_cpt[] = { | |
49 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, | |
73c352a2 | 50 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
51 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
52 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
53 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
54 | }; | |
55 | ||
56 | static const u32 hpd_mask_i915[] = { | |
57 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, | |
58 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
59 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
60 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
61 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
62 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
63 | }; | |
64 | ||
65 | static const u32 hpd_status_gen4[] = { | |
66 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
67 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
68 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
69 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
70 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
71 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
72 | }; | |
73 | ||
e5868a31 EE |
74 | static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ |
75 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, | |
76 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
77 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
78 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
79 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
80 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
81 | }; | |
82 | ||
036a4a7d | 83 | /* For display hotplug interrupt */ |
995b6762 | 84 | static void |
f2b115e6 | 85 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 86 | { |
4bc9d430 DV |
87 | assert_spin_locked(&dev_priv->irq_lock); |
88 | ||
c67a470b PZ |
89 | if (dev_priv->pc8.irqs_disabled) { |
90 | WARN(1, "IRQs disabled\n"); | |
91 | dev_priv->pc8.regsave.deimr &= ~mask; | |
92 | return; | |
93 | } | |
94 | ||
1ec14ad3 CW |
95 | if ((dev_priv->irq_mask & mask) != 0) { |
96 | dev_priv->irq_mask &= ~mask; | |
97 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 98 | POSTING_READ(DEIMR); |
036a4a7d ZW |
99 | } |
100 | } | |
101 | ||
0ff9800a | 102 | static void |
f2b115e6 | 103 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 104 | { |
4bc9d430 DV |
105 | assert_spin_locked(&dev_priv->irq_lock); |
106 | ||
c67a470b PZ |
107 | if (dev_priv->pc8.irqs_disabled) { |
108 | WARN(1, "IRQs disabled\n"); | |
109 | dev_priv->pc8.regsave.deimr |= mask; | |
110 | return; | |
111 | } | |
112 | ||
1ec14ad3 CW |
113 | if ((dev_priv->irq_mask & mask) != mask) { |
114 | dev_priv->irq_mask |= mask; | |
115 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 116 | POSTING_READ(DEIMR); |
036a4a7d ZW |
117 | } |
118 | } | |
119 | ||
43eaea13 PZ |
120 | /** |
121 | * ilk_update_gt_irq - update GTIMR | |
122 | * @dev_priv: driver private | |
123 | * @interrupt_mask: mask of interrupt bits to update | |
124 | * @enabled_irq_mask: mask of interrupt bits to enable | |
125 | */ | |
126 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
127 | uint32_t interrupt_mask, | |
128 | uint32_t enabled_irq_mask) | |
129 | { | |
130 | assert_spin_locked(&dev_priv->irq_lock); | |
131 | ||
c67a470b PZ |
132 | if (dev_priv->pc8.irqs_disabled) { |
133 | WARN(1, "IRQs disabled\n"); | |
134 | dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; | |
135 | dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & | |
136 | interrupt_mask); | |
137 | return; | |
138 | } | |
139 | ||
43eaea13 PZ |
140 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
141 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
142 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
143 | POSTING_READ(GTIMR); | |
144 | } | |
145 | ||
146 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
147 | { | |
148 | ilk_update_gt_irq(dev_priv, mask, mask); | |
149 | } | |
150 | ||
151 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
152 | { | |
153 | ilk_update_gt_irq(dev_priv, mask, 0); | |
154 | } | |
155 | ||
edbfdb45 PZ |
156 | /** |
157 | * snb_update_pm_irq - update GEN6_PMIMR | |
158 | * @dev_priv: driver private | |
159 | * @interrupt_mask: mask of interrupt bits to update | |
160 | * @enabled_irq_mask: mask of interrupt bits to enable | |
161 | */ | |
162 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
163 | uint32_t interrupt_mask, | |
164 | uint32_t enabled_irq_mask) | |
165 | { | |
605cd25b | 166 | uint32_t new_val; |
edbfdb45 PZ |
167 | |
168 | assert_spin_locked(&dev_priv->irq_lock); | |
169 | ||
c67a470b PZ |
170 | if (dev_priv->pc8.irqs_disabled) { |
171 | WARN(1, "IRQs disabled\n"); | |
172 | dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; | |
173 | dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & | |
174 | interrupt_mask); | |
175 | return; | |
176 | } | |
177 | ||
605cd25b | 178 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
179 | new_val &= ~interrupt_mask; |
180 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
181 | ||
605cd25b PZ |
182 | if (new_val != dev_priv->pm_irq_mask) { |
183 | dev_priv->pm_irq_mask = new_val; | |
184 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); | |
f52ecbcf PZ |
185 | POSTING_READ(GEN6_PMIMR); |
186 | } | |
edbfdb45 PZ |
187 | } |
188 | ||
189 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
190 | { | |
191 | snb_update_pm_irq(dev_priv, mask, mask); | |
192 | } | |
193 | ||
194 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) | |
195 | { | |
196 | snb_update_pm_irq(dev_priv, mask, 0); | |
197 | } | |
198 | ||
8664281b PZ |
199 | static bool ivb_can_enable_err_int(struct drm_device *dev) |
200 | { | |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
202 | struct intel_crtc *crtc; | |
203 | enum pipe pipe; | |
204 | ||
4bc9d430 DV |
205 | assert_spin_locked(&dev_priv->irq_lock); |
206 | ||
8664281b PZ |
207 | for_each_pipe(pipe) { |
208 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
209 | ||
210 | if (crtc->cpu_fifo_underrun_disabled) | |
211 | return false; | |
212 | } | |
213 | ||
214 | return true; | |
215 | } | |
216 | ||
217 | static bool cpt_can_enable_serr_int(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | enum pipe pipe; | |
221 | struct intel_crtc *crtc; | |
222 | ||
fee884ed DV |
223 | assert_spin_locked(&dev_priv->irq_lock); |
224 | ||
8664281b PZ |
225 | for_each_pipe(pipe) { |
226 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
227 | ||
228 | if (crtc->pch_fifo_underrun_disabled) | |
229 | return false; | |
230 | } | |
231 | ||
232 | return true; | |
233 | } | |
234 | ||
235 | static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, | |
236 | enum pipe pipe, bool enable) | |
237 | { | |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
239 | uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : | |
240 | DE_PIPEB_FIFO_UNDERRUN; | |
241 | ||
242 | if (enable) | |
243 | ironlake_enable_display_irq(dev_priv, bit); | |
244 | else | |
245 | ironlake_disable_display_irq(dev_priv, bit); | |
246 | } | |
247 | ||
248 | static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, | |
7336df65 | 249 | enum pipe pipe, bool enable) |
8664281b PZ |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8664281b | 252 | if (enable) { |
7336df65 DV |
253 | I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); |
254 | ||
8664281b PZ |
255 | if (!ivb_can_enable_err_int(dev)) |
256 | return; | |
257 | ||
8664281b PZ |
258 | ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); |
259 | } else { | |
7336df65 DV |
260 | bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); |
261 | ||
262 | /* Change the state _after_ we've read out the current one. */ | |
8664281b | 263 | ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
7336df65 DV |
264 | |
265 | if (!was_enabled && | |
266 | (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { | |
267 | DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", | |
268 | pipe_name(pipe)); | |
269 | } | |
8664281b PZ |
270 | } |
271 | } | |
272 | ||
fee884ed DV |
273 | /** |
274 | * ibx_display_interrupt_update - update SDEIMR | |
275 | * @dev_priv: driver private | |
276 | * @interrupt_mask: mask of interrupt bits to update | |
277 | * @enabled_irq_mask: mask of interrupt bits to enable | |
278 | */ | |
279 | static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
280 | uint32_t interrupt_mask, | |
281 | uint32_t enabled_irq_mask) | |
282 | { | |
283 | uint32_t sdeimr = I915_READ(SDEIMR); | |
284 | sdeimr &= ~interrupt_mask; | |
285 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
286 | ||
287 | assert_spin_locked(&dev_priv->irq_lock); | |
288 | ||
c67a470b PZ |
289 | if (dev_priv->pc8.irqs_disabled && |
290 | (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { | |
291 | WARN(1, "IRQs disabled\n"); | |
292 | dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; | |
293 | dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & | |
294 | interrupt_mask); | |
295 | return; | |
296 | } | |
297 | ||
fee884ed DV |
298 | I915_WRITE(SDEIMR, sdeimr); |
299 | POSTING_READ(SDEIMR); | |
300 | } | |
301 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
302 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
303 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
304 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
305 | ||
de28075d DV |
306 | static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, |
307 | enum transcoder pch_transcoder, | |
8664281b PZ |
308 | bool enable) |
309 | { | |
8664281b | 310 | struct drm_i915_private *dev_priv = dev->dev_private; |
de28075d DV |
311 | uint32_t bit = (pch_transcoder == TRANSCODER_A) ? |
312 | SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; | |
8664281b PZ |
313 | |
314 | if (enable) | |
fee884ed | 315 | ibx_enable_display_interrupt(dev_priv, bit); |
8664281b | 316 | else |
fee884ed | 317 | ibx_disable_display_interrupt(dev_priv, bit); |
8664281b PZ |
318 | } |
319 | ||
320 | static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, | |
321 | enum transcoder pch_transcoder, | |
322 | bool enable) | |
323 | { | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | ||
326 | if (enable) { | |
1dd246fb DV |
327 | I915_WRITE(SERR_INT, |
328 | SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); | |
329 | ||
8664281b PZ |
330 | if (!cpt_can_enable_serr_int(dev)) |
331 | return; | |
332 | ||
fee884ed | 333 | ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
8664281b | 334 | } else { |
1dd246fb DV |
335 | uint32_t tmp = I915_READ(SERR_INT); |
336 | bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); | |
337 | ||
338 | /* Change the state _after_ we've read out the current one. */ | |
fee884ed | 339 | ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); |
1dd246fb DV |
340 | |
341 | if (!was_enabled && | |
342 | (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { | |
343 | DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", | |
344 | transcoder_name(pch_transcoder)); | |
345 | } | |
8664281b | 346 | } |
8664281b PZ |
347 | } |
348 | ||
349 | /** | |
350 | * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
351 | * @dev: drm device | |
352 | * @pipe: pipe | |
353 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
354 | * | |
355 | * This function makes us disable or enable CPU fifo underruns for a specific | |
356 | * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun | |
357 | * reporting for one pipe may also disable all the other CPU error interruts for | |
358 | * the other pipes, due to the fact that there's just one interrupt mask/enable | |
359 | * bit for all the pipes. | |
360 | * | |
361 | * Returns the previous state of underrun reporting. | |
362 | */ | |
363 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, | |
364 | enum pipe pipe, bool enable) | |
365 | { | |
366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
367 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
369 | unsigned long flags; | |
370 | bool ret; | |
371 | ||
372 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
373 | ||
374 | ret = !intel_crtc->cpu_fifo_underrun_disabled; | |
375 | ||
376 | if (enable == ret) | |
377 | goto done; | |
378 | ||
379 | intel_crtc->cpu_fifo_underrun_disabled = !enable; | |
380 | ||
381 | if (IS_GEN5(dev) || IS_GEN6(dev)) | |
382 | ironlake_set_fifo_underrun_reporting(dev, pipe, enable); | |
383 | else if (IS_GEN7(dev)) | |
7336df65 | 384 | ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); |
8664281b PZ |
385 | |
386 | done: | |
387 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
388 | return ret; | |
389 | } | |
390 | ||
391 | /** | |
392 | * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages | |
393 | * @dev: drm device | |
394 | * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) | |
395 | * @enable: true if we want to report FIFO underrun errors, false otherwise | |
396 | * | |
397 | * This function makes us disable or enable PCH fifo underruns for a specific | |
398 | * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO | |
399 | * underrun reporting for one transcoder may also disable all the other PCH | |
400 | * error interruts for the other transcoders, due to the fact that there's just | |
401 | * one interrupt mask/enable bit for all the transcoders. | |
402 | * | |
403 | * Returns the previous state of underrun reporting. | |
404 | */ | |
405 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
406 | enum transcoder pch_transcoder, | |
407 | bool enable) | |
408 | { | |
409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de28075d DV |
410 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; |
411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8664281b PZ |
412 | unsigned long flags; |
413 | bool ret; | |
414 | ||
de28075d DV |
415 | /* |
416 | * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT | |
417 | * has only one pch transcoder A that all pipes can use. To avoid racy | |
418 | * pch transcoder -> pipe lookups from interrupt code simply store the | |
419 | * underrun statistics in crtc A. Since we never expose this anywhere | |
420 | * nor use it outside of the fifo underrun code here using the "wrong" | |
421 | * crtc on LPT won't cause issues. | |
422 | */ | |
8664281b PZ |
423 | |
424 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
425 | ||
426 | ret = !intel_crtc->pch_fifo_underrun_disabled; | |
427 | ||
428 | if (enable == ret) | |
429 | goto done; | |
430 | ||
431 | intel_crtc->pch_fifo_underrun_disabled = !enable; | |
432 | ||
433 | if (HAS_PCH_IBX(dev)) | |
de28075d | 434 | ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); |
8664281b PZ |
435 | else |
436 | cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); | |
437 | ||
438 | done: | |
439 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
440 | return ret; | |
441 | } | |
442 | ||
443 | ||
7c463586 KP |
444 | void |
445 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
446 | { | |
46c06a30 VS |
447 | u32 reg = PIPESTAT(pipe); |
448 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 449 | |
b79480ba DV |
450 | assert_spin_locked(&dev_priv->irq_lock); |
451 | ||
46c06a30 VS |
452 | if ((pipestat & mask) == mask) |
453 | return; | |
454 | ||
455 | /* Enable the interrupt, clear any pending status */ | |
456 | pipestat |= mask | (mask >> 16); | |
457 | I915_WRITE(reg, pipestat); | |
458 | POSTING_READ(reg); | |
7c463586 KP |
459 | } |
460 | ||
461 | void | |
462 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
463 | { | |
46c06a30 VS |
464 | u32 reg = PIPESTAT(pipe); |
465 | u32 pipestat = I915_READ(reg) & 0x7fff0000; | |
7c463586 | 466 | |
b79480ba DV |
467 | assert_spin_locked(&dev_priv->irq_lock); |
468 | ||
46c06a30 VS |
469 | if ((pipestat & mask) == 0) |
470 | return; | |
471 | ||
472 | pipestat &= ~mask; | |
473 | I915_WRITE(reg, pipestat); | |
474 | POSTING_READ(reg); | |
7c463586 KP |
475 | } |
476 | ||
01c66889 | 477 | /** |
f49e38dd | 478 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 479 | */ |
f49e38dd | 480 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 481 | { |
1ec14ad3 CW |
482 | drm_i915_private_t *dev_priv = dev->dev_private; |
483 | unsigned long irqflags; | |
484 | ||
f49e38dd JN |
485 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
486 | return; | |
487 | ||
1ec14ad3 | 488 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
01c66889 | 489 | |
f898780b JN |
490 | i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE); |
491 | if (INTEL_INFO(dev)->gen >= 4) | |
492 | i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); | |
1ec14ad3 CW |
493 | |
494 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
495 | } |
496 | ||
0a3e67a4 JB |
497 | /** |
498 | * i915_pipe_enabled - check if a pipe is enabled | |
499 | * @dev: DRM device | |
500 | * @pipe: pipe to check | |
501 | * | |
502 | * Reading certain registers when the pipe is disabled can hang the chip. | |
503 | * Use this routine to make sure the PLL is running and the pipe is active | |
504 | * before reading such registers if unsure. | |
505 | */ | |
506 | static int | |
507 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
508 | { | |
509 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
702e7a56 | 510 | |
a01025af DV |
511 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
512 | /* Locking is horribly broken here, but whatever. */ | |
513 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
71f8ba6b | 515 | |
a01025af DV |
516 | return intel_crtc->active; |
517 | } else { | |
518 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; | |
519 | } | |
0a3e67a4 JB |
520 | } |
521 | ||
4cdb83ec VS |
522 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
523 | { | |
524 | /* Gen2 doesn't have a hardware frame counter */ | |
525 | return 0; | |
526 | } | |
527 | ||
42f52ef8 KP |
528 | /* Called from drm generic code, passed a 'crtc', which |
529 | * we use as a pipe index | |
530 | */ | |
f71d4af4 | 531 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
532 | { |
533 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
534 | unsigned long high_frame; | |
535 | unsigned long low_frame; | |
391f75e2 | 536 | u32 high1, high2, low, pixel, vbl_start; |
0a3e67a4 JB |
537 | |
538 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 539 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 540 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
541 | return 0; |
542 | } | |
543 | ||
391f75e2 VS |
544 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
545 | struct intel_crtc *intel_crtc = | |
546 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
547 | const struct drm_display_mode *mode = | |
548 | &intel_crtc->config.adjusted_mode; | |
549 | ||
550 | vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; | |
551 | } else { | |
552 | enum transcoder cpu_transcoder = | |
553 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
554 | u32 htotal; | |
555 | ||
556 | htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; | |
557 | vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; | |
558 | ||
559 | vbl_start *= htotal; | |
560 | } | |
561 | ||
9db4a9c7 JB |
562 | high_frame = PIPEFRAME(pipe); |
563 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 564 | |
0a3e67a4 JB |
565 | /* |
566 | * High & low register fields aren't synchronized, so make sure | |
567 | * we get a low value that's stable across two reads of the high | |
568 | * register. | |
569 | */ | |
570 | do { | |
5eddb70b | 571 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 572 | low = I915_READ(low_frame); |
5eddb70b | 573 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
574 | } while (high1 != high2); |
575 | ||
5eddb70b | 576 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 577 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 578 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
579 | |
580 | /* | |
581 | * The frame counter increments at beginning of active. | |
582 | * Cook up a vblank counter by also checking the pixel | |
583 | * counter against vblank start. | |
584 | */ | |
585 | return ((high1 << 8) | low) + (pixel >= vbl_start); | |
0a3e67a4 JB |
586 | } |
587 | ||
f71d4af4 | 588 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
589 | { |
590 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 591 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
592 | |
593 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 594 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 595 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
596 | return 0; |
597 | } | |
598 | ||
599 | return I915_READ(reg); | |
600 | } | |
601 | ||
7c06b08a | 602 | static bool intel_pipe_in_vblank(struct drm_device *dev, enum pipe pipe) |
54ddcbd2 VS |
603 | { |
604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
605 | uint32_t status; | |
606 | ||
607 | if (IS_VALLEYVIEW(dev)) { | |
608 | status = pipe == PIPE_A ? | |
609 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
610 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
611 | ||
612 | return I915_READ(VLV_ISR) & status; | |
7c06b08a VS |
613 | } else if (IS_GEN2(dev)) { |
614 | status = pipe == PIPE_A ? | |
615 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
616 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
617 | ||
618 | return I915_READ16(ISR) & status; | |
619 | } else if (INTEL_INFO(dev)->gen < 5) { | |
54ddcbd2 VS |
620 | status = pipe == PIPE_A ? |
621 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT : | |
622 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
623 | ||
624 | return I915_READ(ISR) & status; | |
625 | } else if (INTEL_INFO(dev)->gen < 7) { | |
626 | status = pipe == PIPE_A ? | |
627 | DE_PIPEA_VBLANK : | |
628 | DE_PIPEB_VBLANK; | |
629 | ||
630 | return I915_READ(DEISR) & status; | |
631 | } else { | |
632 | switch (pipe) { | |
633 | default: | |
634 | case PIPE_A: | |
635 | status = DE_PIPEA_VBLANK_IVB; | |
636 | break; | |
637 | case PIPE_B: | |
638 | status = DE_PIPEB_VBLANK_IVB; | |
639 | break; | |
640 | case PIPE_C: | |
641 | status = DE_PIPEC_VBLANK_IVB; | |
642 | break; | |
643 | } | |
644 | ||
645 | return I915_READ(DEISR) & status; | |
646 | } | |
647 | } | |
648 | ||
f71d4af4 | 649 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
650 | int *vpos, int *hpos) |
651 | { | |
c2baf4b7 VS |
652 | struct drm_i915_private *dev_priv = dev->dev_private; |
653 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
655 | const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; | |
3aa18df8 | 656 | int position; |
0af7e4df MK |
657 | int vbl_start, vbl_end, htotal, vtotal; |
658 | bool in_vbl = true; | |
659 | int ret = 0; | |
660 | ||
c2baf4b7 | 661 | if (!intel_crtc->active) { |
0af7e4df | 662 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 663 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
664 | return 0; |
665 | } | |
666 | ||
c2baf4b7 VS |
667 | htotal = mode->crtc_htotal; |
668 | vtotal = mode->crtc_vtotal; | |
669 | vbl_start = mode->crtc_vblank_start; | |
670 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 671 | |
c2baf4b7 VS |
672 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
673 | ||
7c06b08a | 674 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
675 | /* No obvious pixelcount register. Only query vertical |
676 | * scanout position from Display scan line register. | |
677 | */ | |
7c06b08a VS |
678 | if (IS_GEN2(dev)) |
679 | position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
680 | else | |
681 | position = I915_READ(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
54ddcbd2 VS |
682 | |
683 | /* | |
684 | * The scanline counter increments at the leading edge | |
685 | * of hsync, ie. it completely misses the active portion | |
686 | * of the line. Fix up the counter at both edges of vblank | |
687 | * to get a more accurate picture whether we're in vblank | |
688 | * or not. | |
689 | */ | |
7c06b08a | 690 | in_vbl = intel_pipe_in_vblank(dev, pipe); |
54ddcbd2 VS |
691 | if ((in_vbl && position == vbl_start - 1) || |
692 | (!in_vbl && position == vbl_end - 1)) | |
693 | position = (position + 1) % vtotal; | |
0af7e4df MK |
694 | } else { |
695 | /* Have access to pixelcount since start of frame. | |
696 | * We can split this into vertical and horizontal | |
697 | * scanout position. | |
698 | */ | |
699 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
700 | ||
3aa18df8 VS |
701 | /* convert to pixel counts */ |
702 | vbl_start *= htotal; | |
703 | vbl_end *= htotal; | |
704 | vtotal *= htotal; | |
0af7e4df MK |
705 | } |
706 | ||
3aa18df8 VS |
707 | in_vbl = position >= vbl_start && position < vbl_end; |
708 | ||
709 | /* | |
710 | * While in vblank, position will be negative | |
711 | * counting up towards 0 at vbl_end. And outside | |
712 | * vblank, position will be positive counting | |
713 | * up since vbl_end. | |
714 | */ | |
715 | if (position >= vbl_start) | |
716 | position -= vbl_end; | |
717 | else | |
718 | position += vtotal - vbl_end; | |
0af7e4df | 719 | |
7c06b08a | 720 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
721 | *vpos = position; |
722 | *hpos = 0; | |
723 | } else { | |
724 | *vpos = position / htotal; | |
725 | *hpos = position - (*vpos * htotal); | |
726 | } | |
0af7e4df | 727 | |
0af7e4df MK |
728 | /* In vblank? */ |
729 | if (in_vbl) | |
730 | ret |= DRM_SCANOUTPOS_INVBL; | |
731 | ||
732 | return ret; | |
733 | } | |
734 | ||
f71d4af4 | 735 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
736 | int *max_error, |
737 | struct timeval *vblank_time, | |
738 | unsigned flags) | |
739 | { | |
4041b853 | 740 | struct drm_crtc *crtc; |
0af7e4df | 741 | |
7eb552ae | 742 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 743 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
744 | return -EINVAL; |
745 | } | |
746 | ||
747 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
748 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
749 | if (crtc == NULL) { | |
750 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
751 | return -EINVAL; | |
752 | } | |
753 | ||
754 | if (!crtc->enabled) { | |
755 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
756 | return -EBUSY; | |
757 | } | |
0af7e4df MK |
758 | |
759 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
760 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
761 | vblank_time, flags, | |
762 | crtc); | |
0af7e4df MK |
763 | } |
764 | ||
67c347ff JN |
765 | static bool intel_hpd_irq_event(struct drm_device *dev, |
766 | struct drm_connector *connector) | |
321a1b30 EE |
767 | { |
768 | enum drm_connector_status old_status; | |
769 | ||
770 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); | |
771 | old_status = connector->status; | |
772 | ||
773 | connector->status = connector->funcs->detect(connector, false); | |
67c347ff JN |
774 | if (old_status == connector->status) |
775 | return false; | |
776 | ||
777 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", | |
321a1b30 EE |
778 | connector->base.id, |
779 | drm_get_connector_name(connector), | |
67c347ff JN |
780 | drm_get_connector_status_name(old_status), |
781 | drm_get_connector_status_name(connector->status)); | |
782 | ||
783 | return true; | |
321a1b30 EE |
784 | } |
785 | ||
5ca58282 JB |
786 | /* |
787 | * Handle hotplug events outside the interrupt handler proper. | |
788 | */ | |
ac4c16c5 EE |
789 | #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) |
790 | ||
5ca58282 JB |
791 | static void i915_hotplug_work_func(struct work_struct *work) |
792 | { | |
793 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
794 | hotplug_work); | |
795 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 796 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed EE |
797 | struct intel_connector *intel_connector; |
798 | struct intel_encoder *intel_encoder; | |
799 | struct drm_connector *connector; | |
800 | unsigned long irqflags; | |
801 | bool hpd_disabled = false; | |
321a1b30 | 802 | bool changed = false; |
142e2398 | 803 | u32 hpd_event_bits; |
4ef69c7a | 804 | |
52d7eced DV |
805 | /* HPD irq before everything is fully set up. */ |
806 | if (!dev_priv->enable_hotplug_processing) | |
807 | return; | |
808 | ||
a65e34c7 | 809 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
810 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
811 | ||
cd569aed | 812 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
142e2398 EE |
813 | |
814 | hpd_event_bits = dev_priv->hpd_event_bits; | |
815 | dev_priv->hpd_event_bits = 0; | |
cd569aed EE |
816 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
817 | intel_connector = to_intel_connector(connector); | |
818 | intel_encoder = intel_connector->encoder; | |
819 | if (intel_encoder->hpd_pin > HPD_NONE && | |
820 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && | |
821 | connector->polled == DRM_CONNECTOR_POLL_HPD) { | |
822 | DRM_INFO("HPD interrupt storm detected on connector %s: " | |
823 | "switching from hotplug detection to polling\n", | |
824 | drm_get_connector_name(connector)); | |
825 | dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; | |
826 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
827 | | DRM_CONNECTOR_POLL_DISCONNECT; | |
828 | hpd_disabled = true; | |
829 | } | |
142e2398 EE |
830 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { |
831 | DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", | |
832 | drm_get_connector_name(connector), intel_encoder->hpd_pin); | |
833 | } | |
cd569aed EE |
834 | } |
835 | /* if there were no outputs to poll, poll was disabled, | |
836 | * therefore make sure it's enabled when disabling HPD on | |
837 | * some connectors */ | |
ac4c16c5 | 838 | if (hpd_disabled) { |
cd569aed | 839 | drm_kms_helper_poll_enable(dev); |
ac4c16c5 EE |
840 | mod_timer(&dev_priv->hotplug_reenable_timer, |
841 | jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); | |
842 | } | |
cd569aed EE |
843 | |
844 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
845 | ||
321a1b30 EE |
846 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
847 | intel_connector = to_intel_connector(connector); | |
848 | intel_encoder = intel_connector->encoder; | |
849 | if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { | |
850 | if (intel_encoder->hot_plug) | |
851 | intel_encoder->hot_plug(intel_encoder); | |
852 | if (intel_hpd_irq_event(dev, connector)) | |
853 | changed = true; | |
854 | } | |
855 | } | |
40ee3381 KP |
856 | mutex_unlock(&mode_config->mutex); |
857 | ||
321a1b30 EE |
858 | if (changed) |
859 | drm_kms_helper_hotplug_event(dev); | |
5ca58282 JB |
860 | } |
861 | ||
d0ecd7e2 | 862 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 JB |
863 | { |
864 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 865 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 866 | u8 new_delay; |
9270388e | 867 | |
d0ecd7e2 | 868 | spin_lock(&mchdev_lock); |
f97108d1 | 869 | |
73edd18f DV |
870 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
871 | ||
20e4d407 | 872 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 873 | |
7648fa99 | 874 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
875 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
876 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
877 | max_avg = I915_READ(RCBMAXAVG); |
878 | min_avg = I915_READ(RCBMINAVG); | |
879 | ||
880 | /* Handle RCS change request from hw */ | |
b5b72e89 | 881 | if (busy_up > max_avg) { |
20e4d407 DV |
882 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
883 | new_delay = dev_priv->ips.cur_delay - 1; | |
884 | if (new_delay < dev_priv->ips.max_delay) | |
885 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 886 | } else if (busy_down < min_avg) { |
20e4d407 DV |
887 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
888 | new_delay = dev_priv->ips.cur_delay + 1; | |
889 | if (new_delay > dev_priv->ips.min_delay) | |
890 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
891 | } |
892 | ||
7648fa99 | 893 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 894 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 895 | |
d0ecd7e2 | 896 | spin_unlock(&mchdev_lock); |
9270388e | 897 | |
f97108d1 JB |
898 | return; |
899 | } | |
900 | ||
549f7365 CW |
901 | static void notify_ring(struct drm_device *dev, |
902 | struct intel_ring_buffer *ring) | |
903 | { | |
475553de CW |
904 | if (ring->obj == NULL) |
905 | return; | |
906 | ||
814e9b57 | 907 | trace_i915_gem_request_complete(ring); |
9862e600 | 908 | |
549f7365 | 909 | wake_up_all(&ring->irq_queue); |
10cd45b6 | 910 | i915_queue_hangcheck(dev); |
549f7365 CW |
911 | } |
912 | ||
4912d041 | 913 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 914 | { |
4912d041 | 915 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
c6a828d3 | 916 | rps.work); |
edbfdb45 | 917 | u32 pm_iir; |
dd75fdc8 | 918 | int new_delay, adj; |
4912d041 | 919 | |
59cdb63d | 920 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 DV |
921 | pm_iir = dev_priv->rps.pm_iir; |
922 | dev_priv->rps.pm_iir = 0; | |
4848405c | 923 | /* Make sure not to corrupt PMIMR state used by ringbuffer code */ |
edbfdb45 | 924 | snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); |
59cdb63d | 925 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 926 | |
60611c13 PZ |
927 | /* Make sure we didn't queue anything we're not going to process. */ |
928 | WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); | |
929 | ||
4848405c | 930 | if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) |
3b8d8d91 JB |
931 | return; |
932 | ||
4fc688ce | 933 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 934 | |
dd75fdc8 | 935 | adj = dev_priv->rps.last_adj; |
7425034a | 936 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
dd75fdc8 CW |
937 | if (adj > 0) |
938 | adj *= 2; | |
939 | else | |
940 | adj = 1; | |
941 | new_delay = dev_priv->rps.cur_delay + adj; | |
7425034a VS |
942 | |
943 | /* | |
944 | * For better performance, jump directly | |
945 | * to RPe if we're below it. | |
946 | */ | |
dd75fdc8 CW |
947 | if (new_delay < dev_priv->rps.rpe_delay) |
948 | new_delay = dev_priv->rps.rpe_delay; | |
949 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { | |
950 | if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) | |
7425034a | 951 | new_delay = dev_priv->rps.rpe_delay; |
dd75fdc8 CW |
952 | else |
953 | new_delay = dev_priv->rps.min_delay; | |
954 | adj = 0; | |
955 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
956 | if (adj < 0) | |
957 | adj *= 2; | |
958 | else | |
959 | adj = -1; | |
960 | new_delay = dev_priv->rps.cur_delay + adj; | |
961 | } else { /* unknown event */ | |
962 | new_delay = dev_priv->rps.cur_delay; | |
963 | } | |
3b8d8d91 | 964 | |
79249636 BW |
965 | /* sysfs frequency interfaces may have snuck in while servicing the |
966 | * interrupt | |
967 | */ | |
dd75fdc8 CW |
968 | if (new_delay < (int)dev_priv->rps.min_delay) |
969 | new_delay = dev_priv->rps.min_delay; | |
970 | if (new_delay > (int)dev_priv->rps.max_delay) | |
971 | new_delay = dev_priv->rps.max_delay; | |
972 | dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; | |
973 | ||
974 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
975 | valleyview_set_rps(dev_priv->dev, new_delay); | |
976 | else | |
977 | gen6_set_rps(dev_priv->dev, new_delay); | |
3b8d8d91 | 978 | |
4fc688ce | 979 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
980 | } |
981 | ||
e3689190 BW |
982 | |
983 | /** | |
984 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
985 | * occurred. | |
986 | * @work: workqueue struct | |
987 | * | |
988 | * Doesn't actually do anything except notify userspace. As a consequence of | |
989 | * this event, userspace should try to remap the bad rows since statistically | |
990 | * it is likely the same row is more likely to go bad again. | |
991 | */ | |
992 | static void ivybridge_parity_work(struct work_struct *work) | |
993 | { | |
994 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
a4da4fa4 | 995 | l3_parity.error_work); |
e3689190 | 996 | u32 error_status, row, bank, subbank; |
35a85ac6 | 997 | char *parity_event[6]; |
e3689190 BW |
998 | uint32_t misccpctl; |
999 | unsigned long flags; | |
35a85ac6 | 1000 | uint8_t slice = 0; |
e3689190 BW |
1001 | |
1002 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1003 | * In order to prevent a get/put style interface, acquire struct mutex | |
1004 | * any time we access those registers. | |
1005 | */ | |
1006 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1007 | ||
35a85ac6 BW |
1008 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1009 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1010 | goto out; | |
1011 | ||
e3689190 BW |
1012 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1013 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1014 | POSTING_READ(GEN7_MISCCPCTL); | |
1015 | ||
35a85ac6 BW |
1016 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1017 | u32 reg; | |
e3689190 | 1018 | |
35a85ac6 BW |
1019 | slice--; |
1020 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1021 | break; | |
e3689190 | 1022 | |
35a85ac6 | 1023 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1024 | |
35a85ac6 | 1025 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1026 | |
35a85ac6 BW |
1027 | error_status = I915_READ(reg); |
1028 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1029 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1030 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1031 | ||
1032 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1033 | POSTING_READ(reg); | |
1034 | ||
1035 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1036 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1037 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1038 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1039 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1040 | parity_event[5] = NULL; | |
1041 | ||
1042 | kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, | |
1043 | KOBJ_CHANGE, parity_event); | |
e3689190 | 1044 | |
35a85ac6 BW |
1045 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1046 | slice, row, bank, subbank); | |
e3689190 | 1047 | |
35a85ac6 BW |
1048 | kfree(parity_event[4]); |
1049 | kfree(parity_event[3]); | |
1050 | kfree(parity_event[2]); | |
1051 | kfree(parity_event[1]); | |
1052 | } | |
e3689190 | 1053 | |
35a85ac6 | 1054 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1055 | |
35a85ac6 BW |
1056 | out: |
1057 | WARN_ON(dev_priv->l3_parity.which_slice); | |
1058 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1059 | ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); | |
1060 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1061 | ||
1062 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1063 | } |
1064 | ||
35a85ac6 | 1065 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 BW |
1066 | { |
1067 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e3689190 | 1068 | |
040d2baa | 1069 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1070 | return; |
1071 | ||
d0ecd7e2 | 1072 | spin_lock(&dev_priv->irq_lock); |
35a85ac6 | 1073 | ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1074 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1075 | |
35a85ac6 BW |
1076 | iir &= GT_PARITY_ERROR(dev); |
1077 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1078 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1079 | ||
1080 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1081 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1082 | ||
a4da4fa4 | 1083 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1084 | } |
1085 | ||
f1af8fc1 PZ |
1086 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1087 | struct drm_i915_private *dev_priv, | |
1088 | u32 gt_iir) | |
1089 | { | |
1090 | if (gt_iir & | |
1091 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
1092 | notify_ring(dev, &dev_priv->ring[RCS]); | |
1093 | if (gt_iir & ILK_BSD_USER_INTERRUPT) | |
1094 | notify_ring(dev, &dev_priv->ring[VCS]); | |
1095 | } | |
1096 | ||
e7b4c6b1 DV |
1097 | static void snb_gt_irq_handler(struct drm_device *dev, |
1098 | struct drm_i915_private *dev_priv, | |
1099 | u32 gt_iir) | |
1100 | { | |
1101 | ||
cc609d5d BW |
1102 | if (gt_iir & |
1103 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
e7b4c6b1 | 1104 | notify_ring(dev, &dev_priv->ring[RCS]); |
cc609d5d | 1105 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
e7b4c6b1 | 1106 | notify_ring(dev, &dev_priv->ring[VCS]); |
cc609d5d | 1107 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
e7b4c6b1 DV |
1108 | notify_ring(dev, &dev_priv->ring[BCS]); |
1109 | ||
cc609d5d BW |
1110 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1111 | GT_BSD_CS_ERROR_INTERRUPT | | |
1112 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { | |
e7b4c6b1 DV |
1113 | DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); |
1114 | i915_handle_error(dev, false); | |
1115 | } | |
e3689190 | 1116 | |
35a85ac6 BW |
1117 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1118 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1119 | } |
1120 | ||
b543fb04 EE |
1121 | #define HPD_STORM_DETECT_PERIOD 1000 |
1122 | #define HPD_STORM_THRESHOLD 5 | |
1123 | ||
10a504de | 1124 | static inline void intel_hpd_irq_handler(struct drm_device *dev, |
22062dba DV |
1125 | u32 hotplug_trigger, |
1126 | const u32 *hpd) | |
b543fb04 EE |
1127 | { |
1128 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b543fb04 | 1129 | int i; |
10a504de | 1130 | bool storm_detected = false; |
b543fb04 | 1131 | |
91d131d2 DV |
1132 | if (!hotplug_trigger) |
1133 | return; | |
1134 | ||
b5ea2d56 | 1135 | spin_lock(&dev_priv->irq_lock); |
b543fb04 | 1136 | for (i = 1; i < HPD_NUM_PINS; i++) { |
821450c6 | 1137 | |
b8f102e8 EE |
1138 | WARN(((hpd[i] & hotplug_trigger) && |
1139 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED), | |
1140 | "Received HPD interrupt although disabled\n"); | |
1141 | ||
b543fb04 EE |
1142 | if (!(hpd[i] & hotplug_trigger) || |
1143 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | |
1144 | continue; | |
1145 | ||
bc5ead8c | 1146 | dev_priv->hpd_event_bits |= (1 << i); |
b543fb04 EE |
1147 | if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, |
1148 | dev_priv->hpd_stats[i].hpd_last_jiffies | |
1149 | + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { | |
1150 | dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; | |
1151 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
b8f102e8 | 1152 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); |
b543fb04 EE |
1153 | } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { |
1154 | dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; | |
142e2398 | 1155 | dev_priv->hpd_event_bits &= ~(1 << i); |
b543fb04 | 1156 | DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); |
10a504de | 1157 | storm_detected = true; |
b543fb04 EE |
1158 | } else { |
1159 | dev_priv->hpd_stats[i].hpd_cnt++; | |
b8f102e8 EE |
1160 | DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, |
1161 | dev_priv->hpd_stats[i].hpd_cnt); | |
b543fb04 EE |
1162 | } |
1163 | } | |
1164 | ||
10a504de DV |
1165 | if (storm_detected) |
1166 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 1167 | spin_unlock(&dev_priv->irq_lock); |
5876fa0d | 1168 | |
645416f5 DV |
1169 | /* |
1170 | * Our hotplug handler can grab modeset locks (by calling down into the | |
1171 | * fb helpers). Hence it must not be run on our own dev-priv->wq work | |
1172 | * queue for otherwise the flush_work in the pageflip code will | |
1173 | * deadlock. | |
1174 | */ | |
1175 | schedule_work(&dev_priv->hotplug_work); | |
b543fb04 EE |
1176 | } |
1177 | ||
515ac2bb DV |
1178 | static void gmbus_irq_handler(struct drm_device *dev) |
1179 | { | |
28c70f16 DV |
1180 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1181 | ||
28c70f16 | 1182 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1183 | } |
1184 | ||
ce99c256 DV |
1185 | static void dp_aux_irq_handler(struct drm_device *dev) |
1186 | { | |
9ee32fea DV |
1187 | struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1188 | ||
9ee32fea | 1189 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1190 | } |
1191 | ||
8bf1e9f1 | 1192 | #if defined(CONFIG_DEBUG_FS) |
eba94eb9 DV |
1193 | static void display_pipe_crc_update(struct drm_device *dev, enum pipe pipe, |
1194 | uint32_t crc0, uint32_t crc1, | |
1195 | uint32_t crc2, uint32_t crc3, | |
1196 | uint32_t crc4, uint32_t frame) | |
8bf1e9f1 SH |
1197 | { |
1198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1199 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1200 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1201 | int head, tail; |
b2c88f5b | 1202 | |
0c912c79 DL |
1203 | if (!pipe_crc->entries) { |
1204 | DRM_ERROR("spurious interrupt\n"); | |
1205 | return; | |
1206 | } | |
1207 | ||
b2c88f5b DL |
1208 | head = atomic_read(&pipe_crc->head); |
1209 | tail = atomic_read(&pipe_crc->tail); | |
1210 | ||
1211 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
1212 | DRM_ERROR("CRC buffer overflowing\n"); | |
1213 | return; | |
1214 | } | |
1215 | ||
1216 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1217 | |
eba94eb9 DV |
1218 | entry->frame = frame; |
1219 | entry->crc[0] = crc0; | |
1220 | entry->crc[1] = crc1; | |
1221 | entry->crc[2] = crc2; | |
1222 | entry->crc[3] = crc3; | |
1223 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1224 | |
1225 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
1226 | atomic_set(&pipe_crc->head, head); | |
07144428 DL |
1227 | |
1228 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1229 | } |
eba94eb9 DV |
1230 | |
1231 | static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe) | |
1232 | { | |
1233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1234 | ||
1235 | display_pipe_crc_update(dev, pipe, | |
1236 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1237 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1238 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1239 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1240 | I915_READ(PIPE_CRC_RES_5_IVB(pipe)), | |
1241 | I915_READ(PIPEFRAME(pipe))); | |
1242 | } | |
8bf1e9f1 | 1243 | #else |
f8c168fa | 1244 | static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {} |
8bf1e9f1 SH |
1245 | #endif |
1246 | ||
1403c0d4 PZ |
1247 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1248 | * IMR bits until the work is done. Other interrupts can be processed without | |
1249 | * the work queue. */ | |
1250 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1251 | { |
41a05a3a | 1252 | if (pm_iir & GEN6_PM_RPS_EVENTS) { |
59cdb63d | 1253 | spin_lock(&dev_priv->irq_lock); |
41a05a3a | 1254 | dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; |
4d3b3d5f | 1255 | snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); |
59cdb63d | 1256 | spin_unlock(&dev_priv->irq_lock); |
2adbee62 DV |
1257 | |
1258 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
baf02a1f | 1259 | } |
baf02a1f | 1260 | |
1403c0d4 PZ |
1261 | if (HAS_VEBOX(dev_priv->dev)) { |
1262 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
1263 | notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); | |
12638c57 | 1264 | |
1403c0d4 PZ |
1265 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { |
1266 | DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); | |
1267 | i915_handle_error(dev_priv->dev, false); | |
1268 | } | |
12638c57 | 1269 | } |
baf02a1f BW |
1270 | } |
1271 | ||
ff1f525e | 1272 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe JB |
1273 | { |
1274 | struct drm_device *dev = (struct drm_device *) arg; | |
1275 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1276 | u32 iir, gt_iir, pm_iir; | |
1277 | irqreturn_t ret = IRQ_NONE; | |
1278 | unsigned long irqflags; | |
1279 | int pipe; | |
1280 | u32 pipe_stats[I915_MAX_PIPES]; | |
7e231dbe JB |
1281 | |
1282 | atomic_inc(&dev_priv->irq_received); | |
1283 | ||
7e231dbe JB |
1284 | while (true) { |
1285 | iir = I915_READ(VLV_IIR); | |
1286 | gt_iir = I915_READ(GTIIR); | |
1287 | pm_iir = I915_READ(GEN6_PMIIR); | |
1288 | ||
1289 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1290 | goto out; | |
1291 | ||
1292 | ret = IRQ_HANDLED; | |
1293 | ||
e7b4c6b1 | 1294 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
7e231dbe JB |
1295 | |
1296 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1297 | for_each_pipe(pipe) { | |
1298 | int reg = PIPESTAT(pipe); | |
1299 | pipe_stats[pipe] = I915_READ(reg); | |
1300 | ||
1301 | /* | |
1302 | * Clear the PIPE*STAT regs before the IIR | |
1303 | */ | |
1304 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1305 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1306 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1307 | pipe_name(pipe)); | |
1308 | I915_WRITE(reg, pipe_stats[pipe]); | |
1309 | } | |
1310 | } | |
1311 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1312 | ||
31acc7f5 JB |
1313 | for_each_pipe(pipe) { |
1314 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) | |
1315 | drm_handle_vblank(dev, pipe); | |
1316 | ||
1317 | if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { | |
1318 | intel_prepare_page_flip(dev, pipe); | |
1319 | intel_finish_page_flip(dev, pipe); | |
1320 | } | |
1321 | } | |
1322 | ||
7e231dbe JB |
1323 | /* Consume port. Then clear IIR or we'll miss events */ |
1324 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { | |
1325 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 1326 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
7e231dbe JB |
1327 | |
1328 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
1329 | hotplug_status); | |
91d131d2 DV |
1330 | |
1331 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
1332 | ||
7e231dbe JB |
1333 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1334 | I915_READ(PORT_HOTPLUG_STAT); | |
1335 | } | |
1336 | ||
515ac2bb DV |
1337 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
1338 | gmbus_irq_handler(dev); | |
7e231dbe | 1339 | |
60611c13 | 1340 | if (pm_iir) |
d0ecd7e2 | 1341 | gen6_rps_irq_handler(dev_priv, pm_iir); |
7e231dbe JB |
1342 | |
1343 | I915_WRITE(GTIIR, gt_iir); | |
1344 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1345 | I915_WRITE(VLV_IIR, iir); | |
1346 | } | |
1347 | ||
1348 | out: | |
1349 | return ret; | |
1350 | } | |
1351 | ||
23e81d69 | 1352 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 JB |
1353 | { |
1354 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1355 | int pipe; |
b543fb04 | 1356 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
776ad806 | 1357 | |
91d131d2 DV |
1358 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); |
1359 | ||
cfc33bf7 VS |
1360 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1361 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1362 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1363 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1364 | port_name(port)); |
1365 | } | |
776ad806 | 1366 | |
ce99c256 DV |
1367 | if (pch_iir & SDE_AUX_MASK) |
1368 | dp_aux_irq_handler(dev); | |
1369 | ||
776ad806 | 1370 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1371 | gmbus_irq_handler(dev); |
776ad806 JB |
1372 | |
1373 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1374 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1375 | ||
1376 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1377 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1378 | ||
1379 | if (pch_iir & SDE_POISON) | |
1380 | DRM_ERROR("PCH poison interrupt\n"); | |
1381 | ||
9db4a9c7 JB |
1382 | if (pch_iir & SDE_FDI_MASK) |
1383 | for_each_pipe(pipe) | |
1384 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1385 | pipe_name(pipe), | |
1386 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1387 | |
1388 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1389 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1390 | ||
1391 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1392 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1393 | ||
776ad806 | 1394 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
8664281b PZ |
1395 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, |
1396 | false)) | |
1397 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1398 | ||
1399 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1400 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1401 | false)) | |
1402 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1403 | } | |
1404 | ||
1405 | static void ivb_err_int_handler(struct drm_device *dev) | |
1406 | { | |
1407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1408 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
1409 | ||
de032bf4 PZ |
1410 | if (err_int & ERR_INT_POISON) |
1411 | DRM_ERROR("Poison interrupt\n"); | |
1412 | ||
8664281b PZ |
1413 | if (err_int & ERR_INT_FIFO_UNDERRUN_A) |
1414 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1415 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1416 | ||
1417 | if (err_int & ERR_INT_FIFO_UNDERRUN_B) | |
1418 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1419 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1420 | ||
1421 | if (err_int & ERR_INT_FIFO_UNDERRUN_C) | |
1422 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false)) | |
1423 | DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n"); | |
1424 | ||
8bf1e9f1 SH |
1425 | if (err_int & ERR_INT_PIPE_CRC_DONE_A) |
1426 | ivb_pipe_crc_update(dev, PIPE_A); | |
1427 | ||
1428 | if (err_int & ERR_INT_PIPE_CRC_DONE_B) | |
1429 | ivb_pipe_crc_update(dev, PIPE_B); | |
1430 | ||
1431 | if (err_int & ERR_INT_PIPE_CRC_DONE_C) | |
1432 | ivb_pipe_crc_update(dev, PIPE_C); | |
1433 | ||
8664281b PZ |
1434 | I915_WRITE(GEN7_ERR_INT, err_int); |
1435 | } | |
1436 | ||
1437 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1438 | { | |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | u32 serr_int = I915_READ(SERR_INT); | |
1441 | ||
de032bf4 PZ |
1442 | if (serr_int & SERR_INT_POISON) |
1443 | DRM_ERROR("PCH poison interrupt\n"); | |
1444 | ||
8664281b PZ |
1445 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1446 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, | |
1447 | false)) | |
1448 | DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); | |
1449 | ||
1450 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1451 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, | |
1452 | false)) | |
1453 | DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); | |
1454 | ||
1455 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1456 | if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, | |
1457 | false)) | |
1458 | DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); | |
1459 | ||
1460 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1461 | } |
1462 | ||
23e81d69 AJ |
1463 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1464 | { | |
1465 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1466 | int pipe; | |
b543fb04 | 1467 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
23e81d69 | 1468 | |
91d131d2 DV |
1469 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); |
1470 | ||
cfc33bf7 VS |
1471 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1472 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1473 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1474 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1475 | port_name(port)); | |
1476 | } | |
23e81d69 AJ |
1477 | |
1478 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1479 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1480 | |
1481 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1482 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1483 | |
1484 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1485 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1486 | ||
1487 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1488 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1489 | ||
1490 | if (pch_iir & SDE_FDI_MASK_CPT) | |
1491 | for_each_pipe(pipe) | |
1492 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
1493 | pipe_name(pipe), | |
1494 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1495 | |
1496 | if (pch_iir & SDE_ERROR_CPT) | |
1497 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1498 | } |
1499 | ||
c008bc6e PZ |
1500 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1501 | { | |
1502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1503 | ||
1504 | if (de_iir & DE_AUX_CHANNEL_A) | |
1505 | dp_aux_irq_handler(dev); | |
1506 | ||
1507 | if (de_iir & DE_GSE) | |
1508 | intel_opregion_asle_intr(dev); | |
1509 | ||
1510 | if (de_iir & DE_PIPEA_VBLANK) | |
1511 | drm_handle_vblank(dev, 0); | |
1512 | ||
1513 | if (de_iir & DE_PIPEB_VBLANK) | |
1514 | drm_handle_vblank(dev, 1); | |
1515 | ||
1516 | if (de_iir & DE_POISON) | |
1517 | DRM_ERROR("Poison interrupt\n"); | |
1518 | ||
1519 | if (de_iir & DE_PIPEA_FIFO_UNDERRUN) | |
1520 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false)) | |
1521 | DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n"); | |
1522 | ||
1523 | if (de_iir & DE_PIPEB_FIFO_UNDERRUN) | |
1524 | if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) | |
1525 | DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n"); | |
1526 | ||
1527 | if (de_iir & DE_PLANEA_FLIP_DONE) { | |
1528 | intel_prepare_page_flip(dev, 0); | |
1529 | intel_finish_page_flip_plane(dev, 0); | |
1530 | } | |
1531 | ||
1532 | if (de_iir & DE_PLANEB_FLIP_DONE) { | |
1533 | intel_prepare_page_flip(dev, 1); | |
1534 | intel_finish_page_flip_plane(dev, 1); | |
1535 | } | |
1536 | ||
1537 | /* check event from PCH */ | |
1538 | if (de_iir & DE_PCH_EVENT) { | |
1539 | u32 pch_iir = I915_READ(SDEIIR); | |
1540 | ||
1541 | if (HAS_PCH_CPT(dev)) | |
1542 | cpt_irq_handler(dev, pch_iir); | |
1543 | else | |
1544 | ibx_irq_handler(dev, pch_iir); | |
1545 | ||
1546 | /* should clear PCH hotplug event before clear CPU irq */ | |
1547 | I915_WRITE(SDEIIR, pch_iir); | |
1548 | } | |
1549 | ||
1550 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
1551 | ironlake_rps_change_irq_handler(dev); | |
1552 | } | |
1553 | ||
9719fb98 PZ |
1554 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1555 | { | |
1556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1557 | int i; | |
1558 | ||
1559 | if (de_iir & DE_ERR_INT_IVB) | |
1560 | ivb_err_int_handler(dev); | |
1561 | ||
1562 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
1563 | dp_aux_irq_handler(dev); | |
1564 | ||
1565 | if (de_iir & DE_GSE_IVB) | |
1566 | intel_opregion_asle_intr(dev); | |
1567 | ||
1568 | for (i = 0; i < 3; i++) { | |
1569 | if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) | |
1570 | drm_handle_vblank(dev, i); | |
1571 | if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { | |
1572 | intel_prepare_page_flip(dev, i); | |
1573 | intel_finish_page_flip_plane(dev, i); | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | /* check event from PCH */ | |
1578 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
1579 | u32 pch_iir = I915_READ(SDEIIR); | |
1580 | ||
1581 | cpt_irq_handler(dev, pch_iir); | |
1582 | ||
1583 | /* clear PCH hotplug event before clear CPU irq */ | |
1584 | I915_WRITE(SDEIIR, pch_iir); | |
1585 | } | |
1586 | } | |
1587 | ||
f1af8fc1 | 1588 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 JB |
1589 | { |
1590 | struct drm_device *dev = (struct drm_device *) arg; | |
1591 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
f1af8fc1 | 1592 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 1593 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 JB |
1594 | |
1595 | atomic_inc(&dev_priv->irq_received); | |
1596 | ||
8664281b PZ |
1597 | /* We get interrupts on unclaimed registers, so check for this before we |
1598 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 1599 | intel_uncore_check_errors(dev); |
8664281b | 1600 | |
b1f14ad0 JB |
1601 | /* disable master interrupt before clearing iir */ |
1602 | de_ier = I915_READ(DEIER); | |
1603 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 1604 | POSTING_READ(DEIER); |
b1f14ad0 | 1605 | |
44498aea PZ |
1606 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
1607 | * interrupts will will be stored on its back queue, and then we'll be | |
1608 | * able to process them after we restore SDEIER (as soon as we restore | |
1609 | * it, we'll get an interrupt if SDEIIR still has something to process | |
1610 | * due to its back queue). */ | |
ab5c608b BW |
1611 | if (!HAS_PCH_NOP(dev)) { |
1612 | sde_ier = I915_READ(SDEIER); | |
1613 | I915_WRITE(SDEIER, 0); | |
1614 | POSTING_READ(SDEIER); | |
1615 | } | |
44498aea | 1616 | |
b1f14ad0 | 1617 | gt_iir = I915_READ(GTIIR); |
0e43406b | 1618 | if (gt_iir) { |
d8fc8a47 | 1619 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 1620 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
1621 | else |
1622 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
0e43406b CW |
1623 | I915_WRITE(GTIIR, gt_iir); |
1624 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1625 | } |
1626 | ||
0e43406b CW |
1627 | de_iir = I915_READ(DEIIR); |
1628 | if (de_iir) { | |
f1af8fc1 PZ |
1629 | if (INTEL_INFO(dev)->gen >= 7) |
1630 | ivb_display_irq_handler(dev, de_iir); | |
1631 | else | |
1632 | ilk_display_irq_handler(dev, de_iir); | |
0e43406b CW |
1633 | I915_WRITE(DEIIR, de_iir); |
1634 | ret = IRQ_HANDLED; | |
b1f14ad0 JB |
1635 | } |
1636 | ||
f1af8fc1 PZ |
1637 | if (INTEL_INFO(dev)->gen >= 6) { |
1638 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
1639 | if (pm_iir) { | |
1403c0d4 | 1640 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 PZ |
1641 | I915_WRITE(GEN6_PMIIR, pm_iir); |
1642 | ret = IRQ_HANDLED; | |
1643 | } | |
0e43406b | 1644 | } |
b1f14ad0 | 1645 | |
b1f14ad0 JB |
1646 | I915_WRITE(DEIER, de_ier); |
1647 | POSTING_READ(DEIER); | |
ab5c608b BW |
1648 | if (!HAS_PCH_NOP(dev)) { |
1649 | I915_WRITE(SDEIER, sde_ier); | |
1650 | POSTING_READ(SDEIER); | |
1651 | } | |
b1f14ad0 JB |
1652 | |
1653 | return ret; | |
1654 | } | |
1655 | ||
17e1df07 DV |
1656 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
1657 | bool reset_completed) | |
1658 | { | |
1659 | struct intel_ring_buffer *ring; | |
1660 | int i; | |
1661 | ||
1662 | /* | |
1663 | * Notify all waiters for GPU completion events that reset state has | |
1664 | * been changed, and that they need to restart their wait after | |
1665 | * checking for potential errors (and bail out to drop locks if there is | |
1666 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
1667 | */ | |
1668 | ||
1669 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
1670 | for_each_ring(ring, dev_priv, i) | |
1671 | wake_up_all(&ring->irq_queue); | |
1672 | ||
1673 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
1674 | wake_up_all(&dev_priv->pending_flip_queue); | |
1675 | ||
1676 | /* | |
1677 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
1678 | * reset state is cleared. | |
1679 | */ | |
1680 | if (reset_completed) | |
1681 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
1682 | } | |
1683 | ||
8a905236 JB |
1684 | /** |
1685 | * i915_error_work_func - do process context error handling work | |
1686 | * @work: work struct | |
1687 | * | |
1688 | * Fire an error uevent so userspace can see that a hang or error | |
1689 | * was detected. | |
1690 | */ | |
1691 | static void i915_error_work_func(struct work_struct *work) | |
1692 | { | |
1f83fee0 DV |
1693 | struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, |
1694 | work); | |
1695 | drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, | |
1696 | gpu_error); | |
8a905236 | 1697 | struct drm_device *dev = dev_priv->dev; |
cce723ed BW |
1698 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
1699 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
1700 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 1701 | int ret; |
8a905236 | 1702 | |
f316a42c BG |
1703 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
1704 | ||
7db0ba24 DV |
1705 | /* |
1706 | * Note that there's only one work item which does gpu resets, so we | |
1707 | * need not worry about concurrent gpu resets potentially incrementing | |
1708 | * error->reset_counter twice. We only need to take care of another | |
1709 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
1710 | * quick check for that is good enough: schedule_work ensures the | |
1711 | * correct ordering between hang detection and this work item, and since | |
1712 | * the reset in-progress bit is only ever set by code outside of this | |
1713 | * work we don't need to worry about any other races. | |
1714 | */ | |
1715 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 1716 | DRM_DEBUG_DRIVER("resetting chip\n"); |
7db0ba24 DV |
1717 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, |
1718 | reset_event); | |
1f83fee0 | 1719 | |
17e1df07 DV |
1720 | /* |
1721 | * All state reset _must_ be completed before we update the | |
1722 | * reset counter, for otherwise waiters might miss the reset | |
1723 | * pending state and not properly drop locks, resulting in | |
1724 | * deadlocks with the reset work. | |
1725 | */ | |
f69061be DV |
1726 | ret = i915_reset(dev); |
1727 | ||
17e1df07 DV |
1728 | intel_display_handle_reset(dev); |
1729 | ||
f69061be DV |
1730 | if (ret == 0) { |
1731 | /* | |
1732 | * After all the gem state is reset, increment the reset | |
1733 | * counter and wake up everyone waiting for the reset to | |
1734 | * complete. | |
1735 | * | |
1736 | * Since unlock operations are a one-sided barrier only, | |
1737 | * we need to insert a barrier here to order any seqno | |
1738 | * updates before | |
1739 | * the counter increment. | |
1740 | */ | |
1741 | smp_mb__before_atomic_inc(); | |
1742 | atomic_inc(&dev_priv->gpu_error.reset_counter); | |
1743 | ||
1744 | kobject_uevent_env(&dev->primary->kdev.kobj, | |
1745 | KOBJ_CHANGE, reset_done_event); | |
1f83fee0 DV |
1746 | } else { |
1747 | atomic_set(&error->reset_counter, I915_WEDGED); | |
f316a42c | 1748 | } |
1f83fee0 | 1749 | |
17e1df07 DV |
1750 | /* |
1751 | * Note: The wake_up also serves as a memory barrier so that | |
1752 | * waiters see the update value of the reset counter atomic_t. | |
1753 | */ | |
1754 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 1755 | } |
8a905236 JB |
1756 | } |
1757 | ||
35aed2e6 | 1758 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1759 | { |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 1761 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 1762 | u32 eir = I915_READ(EIR); |
050ee91f | 1763 | int pipe, i; |
8a905236 | 1764 | |
35aed2e6 CW |
1765 | if (!eir) |
1766 | return; | |
8a905236 | 1767 | |
a70491cc | 1768 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 1769 | |
bd9854f9 BW |
1770 | i915_get_extra_instdone(dev, instdone); |
1771 | ||
8a905236 JB |
1772 | if (IS_G4X(dev)) { |
1773 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1774 | u32 ipeir = I915_READ(IPEIR_I965); | |
1775 | ||
a70491cc JP |
1776 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1777 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
1778 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1779 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 1780 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1781 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1782 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1783 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1784 | } |
1785 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1786 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1787 | pr_err("page table error\n"); |
1788 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1789 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1790 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1791 | } |
1792 | } | |
1793 | ||
a6c45cf0 | 1794 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1795 | if (eir & I915_ERROR_PAGE_TABLE) { |
1796 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
1797 | pr_err("page table error\n"); |
1798 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 1799 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 1800 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1801 | } |
1802 | } | |
1803 | ||
1804 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 1805 | pr_err("memory refresh error:\n"); |
9db4a9c7 | 1806 | for_each_pipe(pipe) |
a70491cc | 1807 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 1808 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
1809 | /* pipestat has already been acked */ |
1810 | } | |
1811 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
1812 | pr_err("instruction error\n"); |
1813 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
1814 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
1815 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 1816 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1817 | u32 ipeir = I915_READ(IPEIR); |
1818 | ||
a70491cc JP |
1819 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
1820 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 1821 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 1822 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 1823 | POSTING_READ(IPEIR); |
8a905236 JB |
1824 | } else { |
1825 | u32 ipeir = I915_READ(IPEIR_I965); | |
1826 | ||
a70491cc JP |
1827 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
1828 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 1829 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 1830 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 1831 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 1832 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1833 | } |
1834 | } | |
1835 | ||
1836 | I915_WRITE(EIR, eir); | |
3143a2bf | 1837 | POSTING_READ(EIR); |
8a905236 JB |
1838 | eir = I915_READ(EIR); |
1839 | if (eir) { | |
1840 | /* | |
1841 | * some errors might have become stuck, | |
1842 | * mask them. | |
1843 | */ | |
1844 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1845 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1846 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1847 | } | |
35aed2e6 CW |
1848 | } |
1849 | ||
1850 | /** | |
1851 | * i915_handle_error - handle an error interrupt | |
1852 | * @dev: drm device | |
1853 | * | |
1854 | * Do some basic checking of regsiter state at error interrupt time and | |
1855 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1856 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1857 | * so userspace knows something bad happened (should trigger collection | |
1858 | * of a ring dump etc.). | |
1859 | */ | |
527f9e90 | 1860 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1861 | { |
1862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1863 | ||
1864 | i915_capture_error_state(dev); | |
1865 | i915_report_and_clear_eir(dev); | |
8a905236 | 1866 | |
ba1234d1 | 1867 | if (wedged) { |
f69061be DV |
1868 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
1869 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 1870 | |
11ed50ec | 1871 | /* |
17e1df07 DV |
1872 | * Wakeup waiting processes so that the reset work function |
1873 | * i915_error_work_func doesn't deadlock trying to grab various | |
1874 | * locks. By bumping the reset counter first, the woken | |
1875 | * processes will see a reset in progress and back off, | |
1876 | * releasing their locks and then wait for the reset completion. | |
1877 | * We must do this for _all_ gpu waiters that might hold locks | |
1878 | * that the reset work needs to acquire. | |
1879 | * | |
1880 | * Note: The wake_up serves as the required memory barrier to | |
1881 | * ensure that the waiters see the updated value of the reset | |
1882 | * counter atomic_t. | |
11ed50ec | 1883 | */ |
17e1df07 | 1884 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
1885 | } |
1886 | ||
122f46ba DV |
1887 | /* |
1888 | * Our reset work can grab modeset locks (since it needs to reset the | |
1889 | * state of outstanding pagelips). Hence it must not be run on our own | |
1890 | * dev-priv->wq work queue for otherwise the flush_work in the pageflip | |
1891 | * code will deadlock. | |
1892 | */ | |
1893 | schedule_work(&dev_priv->gpu_error.work); | |
8a905236 JB |
1894 | } |
1895 | ||
21ad8330 | 1896 | static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
4e5359cd SF |
1897 | { |
1898 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1899 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1901 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1902 | struct intel_unpin_work *work; |
1903 | unsigned long flags; | |
1904 | bool stall_detected; | |
1905 | ||
1906 | /* Ignore early vblank irqs */ | |
1907 | if (intel_crtc == NULL) | |
1908 | return; | |
1909 | ||
1910 | spin_lock_irqsave(&dev->event_lock, flags); | |
1911 | work = intel_crtc->unpin_work; | |
1912 | ||
e7d841ca CW |
1913 | if (work == NULL || |
1914 | atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || | |
1915 | !work->enable_stall_check) { | |
4e5359cd SF |
1916 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ |
1917 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1918 | return; | |
1919 | } | |
1920 | ||
1921 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1922 | obj = work->pending_flip_obj; |
a6c45cf0 | 1923 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1924 | int dspsurf = DSPSURF(intel_crtc->plane); |
446f2545 | 1925 | stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == |
f343c5f6 | 1926 | i915_gem_obj_ggtt_offset(obj); |
4e5359cd | 1927 | } else { |
9db4a9c7 | 1928 | int dspaddr = DSPADDR(intel_crtc->plane); |
f343c5f6 | 1929 | stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + |
01f2c773 | 1930 | crtc->y * crtc->fb->pitches[0] + |
4e5359cd SF |
1931 | crtc->x * crtc->fb->bits_per_pixel/8); |
1932 | } | |
1933 | ||
1934 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1935 | ||
1936 | if (stall_detected) { | |
1937 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1938 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1939 | } | |
1940 | } | |
1941 | ||
42f52ef8 KP |
1942 | /* Called from drm generic code, passed 'crtc' which |
1943 | * we use as a pipe index | |
1944 | */ | |
f71d4af4 | 1945 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1946 | { |
1947 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1948 | unsigned long irqflags; |
71e0ffa5 | 1949 | |
5eddb70b | 1950 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1951 | return -EINVAL; |
0a3e67a4 | 1952 | |
1ec14ad3 | 1953 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1954 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1955 | i915_enable_pipestat(dev_priv, pipe, |
1956 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1957 | else |
7c463586 KP |
1958 | i915_enable_pipestat(dev_priv, pipe, |
1959 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1960 | |
1961 | /* maintain vblank delivery even in deep C-states */ | |
1962 | if (dev_priv->info->gen == 3) | |
6b26c86d | 1963 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); |
1ec14ad3 | 1964 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1965 | |
0a3e67a4 JB |
1966 | return 0; |
1967 | } | |
1968 | ||
f71d4af4 | 1969 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1970 | { |
1971 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1972 | unsigned long irqflags; | |
b518421f PZ |
1973 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
1974 | DE_PIPE_VBLANK_ILK(pipe); | |
f796cf8f JB |
1975 | |
1976 | if (!i915_pipe_enabled(dev, pipe)) | |
1977 | return -EINVAL; | |
1978 | ||
1979 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 1980 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
1981 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
7e231dbe JB |
1986 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
1987 | { | |
1988 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1989 | unsigned long irqflags; | |
31acc7f5 | 1990 | u32 imr; |
7e231dbe JB |
1991 | |
1992 | if (!i915_pipe_enabled(dev, pipe)) | |
1993 | return -EINVAL; | |
1994 | ||
1995 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
7e231dbe | 1996 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 1997 | if (pipe == 0) |
7e231dbe | 1998 | imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 1999 | else |
7e231dbe | 2000 | imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2001 | I915_WRITE(VLV_IMR, imr); |
31acc7f5 JB |
2002 | i915_enable_pipestat(dev_priv, pipe, |
2003 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe JB |
2004 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2005 | ||
2006 | return 0; | |
2007 | } | |
2008 | ||
42f52ef8 KP |
2009 | /* Called from drm generic code, passed 'crtc' which |
2010 | * we use as a pipe index | |
2011 | */ | |
f71d4af4 | 2012 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
2013 | { |
2014 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 2015 | unsigned long irqflags; |
0a3e67a4 | 2016 | |
1ec14ad3 | 2017 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e | 2018 | if (dev_priv->info->gen == 3) |
6b26c86d | 2019 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); |
8692d00e | 2020 | |
f796cf8f JB |
2021 | i915_disable_pipestat(dev_priv, pipe, |
2022 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
2023 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
2024 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2025 | } | |
2026 | ||
f71d4af4 | 2027 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
2028 | { |
2029 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2030 | unsigned long irqflags; | |
b518421f PZ |
2031 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
2032 | DE_PIPE_VBLANK_ILK(pipe); | |
f796cf8f JB |
2033 | |
2034 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2035 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2036 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2037 | } | |
2038 | ||
7e231dbe JB |
2039 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2040 | { | |
2041 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2042 | unsigned long irqflags; | |
31acc7f5 | 2043 | u32 imr; |
7e231dbe JB |
2044 | |
2045 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 JB |
2046 | i915_disable_pipestat(dev_priv, pipe, |
2047 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
7e231dbe | 2048 | imr = I915_READ(VLV_IMR); |
31acc7f5 | 2049 | if (pipe == 0) |
7e231dbe | 2050 | imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; |
31acc7f5 | 2051 | else |
7e231dbe | 2052 | imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
7e231dbe | 2053 | I915_WRITE(VLV_IMR, imr); |
7e231dbe JB |
2054 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2055 | } | |
2056 | ||
893eead0 CW |
2057 | static u32 |
2058 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 2059 | { |
893eead0 CW |
2060 | return list_entry(ring->request_list.prev, |
2061 | struct drm_i915_gem_request, list)->seqno; | |
2062 | } | |
2063 | ||
9107e9d2 CW |
2064 | static bool |
2065 | ring_idle(struct intel_ring_buffer *ring, u32 seqno) | |
2066 | { | |
2067 | return (list_empty(&ring->request_list) || | |
2068 | i915_seqno_passed(seqno, ring_last_seqno(ring))); | |
f65d9421 BG |
2069 | } |
2070 | ||
6274f212 CW |
2071 | static struct intel_ring_buffer * |
2072 | semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) | |
a24a11e6 CW |
2073 | { |
2074 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6274f212 | 2075 | u32 cmd, ipehr, acthd, acthd_min; |
a24a11e6 CW |
2076 | |
2077 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
2078 | if ((ipehr & ~(0x3 << 16)) != | |
2079 | (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) | |
6274f212 | 2080 | return NULL; |
a24a11e6 CW |
2081 | |
2082 | /* ACTHD is likely pointing to the dword after the actual command, | |
2083 | * so scan backwards until we find the MBOX. | |
2084 | */ | |
6274f212 | 2085 | acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; |
a24a11e6 CW |
2086 | acthd_min = max((int)acthd - 3 * 4, 0); |
2087 | do { | |
2088 | cmd = ioread32(ring->virtual_start + acthd); | |
2089 | if (cmd == ipehr) | |
2090 | break; | |
2091 | ||
2092 | acthd -= 4; | |
2093 | if (acthd < acthd_min) | |
6274f212 | 2094 | return NULL; |
a24a11e6 CW |
2095 | } while (1); |
2096 | ||
6274f212 CW |
2097 | *seqno = ioread32(ring->virtual_start+acthd+4)+1; |
2098 | return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; | |
a24a11e6 CW |
2099 | } |
2100 | ||
6274f212 CW |
2101 | static int semaphore_passed(struct intel_ring_buffer *ring) |
2102 | { | |
2103 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2104 | struct intel_ring_buffer *signaller; | |
2105 | u32 seqno, ctl; | |
2106 | ||
2107 | ring->hangcheck.deadlock = true; | |
2108 | ||
2109 | signaller = semaphore_waits_for(ring, &seqno); | |
2110 | if (signaller == NULL || signaller->hangcheck.deadlock) | |
2111 | return -1; | |
2112 | ||
2113 | /* cursory check for an unkickable deadlock */ | |
2114 | ctl = I915_READ_CTL(signaller); | |
2115 | if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) | |
2116 | return -1; | |
2117 | ||
2118 | return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); | |
2119 | } | |
2120 | ||
2121 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2122 | { | |
2123 | struct intel_ring_buffer *ring; | |
2124 | int i; | |
2125 | ||
2126 | for_each_ring(ring, dev_priv, i) | |
2127 | ring->hangcheck.deadlock = false; | |
2128 | } | |
2129 | ||
ad8beaea MK |
2130 | static enum intel_ring_hangcheck_action |
2131 | ring_stuck(struct intel_ring_buffer *ring, u32 acthd) | |
1ec14ad3 CW |
2132 | { |
2133 | struct drm_device *dev = ring->dev; | |
2134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2135 | u32 tmp; |
2136 | ||
6274f212 | 2137 | if (ring->hangcheck.acthd != acthd) |
f2f4d82f | 2138 | return HANGCHECK_ACTIVE; |
6274f212 | 2139 | |
9107e9d2 | 2140 | if (IS_GEN2(dev)) |
f2f4d82f | 2141 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2142 | |
2143 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2144 | * If so we can simply poke the RB_WAIT bit | |
2145 | * and break the hang. This should work on | |
2146 | * all but the second generation chipsets. | |
2147 | */ | |
2148 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 CW |
2149 | if (tmp & RING_WAIT) { |
2150 | DRM_ERROR("Kicking stuck wait on %s\n", | |
2151 | ring->name); | |
09e14bf3 | 2152 | i915_handle_error(dev, false); |
1ec14ad3 | 2153 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2154 | return HANGCHECK_KICK; |
6274f212 CW |
2155 | } |
2156 | ||
2157 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2158 | switch (semaphore_passed(ring)) { | |
2159 | default: | |
f2f4d82f | 2160 | return HANGCHECK_HUNG; |
6274f212 CW |
2161 | case 1: |
2162 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
2163 | ring->name); | |
09e14bf3 | 2164 | i915_handle_error(dev, false); |
6274f212 | 2165 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2166 | return HANGCHECK_KICK; |
6274f212 | 2167 | case 0: |
f2f4d82f | 2168 | return HANGCHECK_WAIT; |
6274f212 | 2169 | } |
9107e9d2 | 2170 | } |
ed5cbb03 | 2171 | |
f2f4d82f | 2172 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2173 | } |
2174 | ||
f65d9421 BG |
2175 | /** |
2176 | * This is called when the chip hasn't reported back with completed | |
05407ff8 MK |
2177 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2178 | * if there are no progress, hangcheck score for that ring is increased. | |
2179 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2180 | * we kick the ring. If we see no progress on three subsequent calls | |
2181 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2182 | */ |
a658b5d2 | 2183 | static void i915_hangcheck_elapsed(unsigned long data) |
f65d9421 BG |
2184 | { |
2185 | struct drm_device *dev = (struct drm_device *)data; | |
2186 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2187 | struct intel_ring_buffer *ring; |
b4519513 | 2188 | int i; |
05407ff8 | 2189 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2190 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2191 | #define BUSY 1 | |
2192 | #define KICK 5 | |
2193 | #define HUNG 20 | |
2194 | #define FIRE 30 | |
893eead0 | 2195 | |
3e0dc6b0 BW |
2196 | if (!i915_enable_hangcheck) |
2197 | return; | |
2198 | ||
b4519513 | 2199 | for_each_ring(ring, dev_priv, i) { |
05407ff8 | 2200 | u32 seqno, acthd; |
9107e9d2 | 2201 | bool busy = true; |
05407ff8 | 2202 | |
6274f212 CW |
2203 | semaphore_clear_deadlocks(dev_priv); |
2204 | ||
05407ff8 MK |
2205 | seqno = ring->get_seqno(ring, false); |
2206 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2207 | |
9107e9d2 CW |
2208 | if (ring->hangcheck.seqno == seqno) { |
2209 | if (ring_idle(ring, seqno)) { | |
da661464 MK |
2210 | ring->hangcheck.action = HANGCHECK_IDLE; |
2211 | ||
9107e9d2 CW |
2212 | if (waitqueue_active(&ring->irq_queue)) { |
2213 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 CW |
2214 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
2215 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2216 | ring->name); | |
2217 | wake_up_all(&ring->irq_queue); | |
2218 | } | |
2219 | /* Safeguard against driver failure */ | |
2220 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2221 | } else |
2222 | busy = false; | |
05407ff8 | 2223 | } else { |
6274f212 CW |
2224 | /* We always increment the hangcheck score |
2225 | * if the ring is busy and still processing | |
2226 | * the same request, so that no single request | |
2227 | * can run indefinitely (such as a chain of | |
2228 | * batches). The only time we do not increment | |
2229 | * the hangcheck score on this ring, if this | |
2230 | * ring is in a legitimate wait for another | |
2231 | * ring. In that case the waiting ring is a | |
2232 | * victim and we want to be sure we catch the | |
2233 | * right culprit. Then every time we do kick | |
2234 | * the ring, add a small increment to the | |
2235 | * score so that we can catch a batch that is | |
2236 | * being repeatedly kicked and so responsible | |
2237 | * for stalling the machine. | |
2238 | */ | |
ad8beaea MK |
2239 | ring->hangcheck.action = ring_stuck(ring, |
2240 | acthd); | |
2241 | ||
2242 | switch (ring->hangcheck.action) { | |
da661464 | 2243 | case HANGCHECK_IDLE: |
f2f4d82f | 2244 | case HANGCHECK_WAIT: |
6274f212 | 2245 | break; |
f2f4d82f | 2246 | case HANGCHECK_ACTIVE: |
ea04cb31 | 2247 | ring->hangcheck.score += BUSY; |
6274f212 | 2248 | break; |
f2f4d82f | 2249 | case HANGCHECK_KICK: |
ea04cb31 | 2250 | ring->hangcheck.score += KICK; |
6274f212 | 2251 | break; |
f2f4d82f | 2252 | case HANGCHECK_HUNG: |
ea04cb31 | 2253 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2254 | stuck[i] = true; |
2255 | break; | |
2256 | } | |
05407ff8 | 2257 | } |
9107e9d2 | 2258 | } else { |
da661464 MK |
2259 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2260 | ||
9107e9d2 CW |
2261 | /* Gradually reduce the count so that we catch DoS |
2262 | * attempts across multiple batches. | |
2263 | */ | |
2264 | if (ring->hangcheck.score > 0) | |
2265 | ring->hangcheck.score--; | |
d1e61e7f CW |
2266 | } |
2267 | ||
05407ff8 MK |
2268 | ring->hangcheck.seqno = seqno; |
2269 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2270 | busy_count += busy; |
893eead0 | 2271 | } |
b9201c14 | 2272 | |
92cab734 | 2273 | for_each_ring(ring, dev_priv, i) { |
9107e9d2 | 2274 | if (ring->hangcheck.score > FIRE) { |
b8d88d1d DV |
2275 | DRM_INFO("%s on %s\n", |
2276 | stuck[i] ? "stuck" : "no progress", | |
2277 | ring->name); | |
a43adf07 | 2278 | rings_hung++; |
92cab734 MK |
2279 | } |
2280 | } | |
2281 | ||
05407ff8 MK |
2282 | if (rings_hung) |
2283 | return i915_handle_error(dev, true); | |
f65d9421 | 2284 | |
05407ff8 MK |
2285 | if (busy_count) |
2286 | /* Reset timer case chip hangs without another request | |
2287 | * being added */ | |
10cd45b6 MK |
2288 | i915_queue_hangcheck(dev); |
2289 | } | |
2290 | ||
2291 | void i915_queue_hangcheck(struct drm_device *dev) | |
2292 | { | |
2293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2294 | if (!i915_enable_hangcheck) | |
2295 | return; | |
2296 | ||
2297 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, | |
2298 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
2299 | } |
2300 | ||
91738a95 PZ |
2301 | static void ibx_irq_preinstall(struct drm_device *dev) |
2302 | { | |
2303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2304 | ||
2305 | if (HAS_PCH_NOP(dev)) | |
2306 | return; | |
2307 | ||
2308 | /* south display irq */ | |
2309 | I915_WRITE(SDEIMR, 0xffffffff); | |
2310 | /* | |
2311 | * SDEIER is also touched by the interrupt handler to work around missed | |
2312 | * PCH interrupts. Hence we can't update it after the interrupt handler | |
2313 | * is enabled - instead we unconditionally enable all PCH interrupt | |
2314 | * sources here, but then only unmask them as needed with SDEIMR. | |
2315 | */ | |
2316 | I915_WRITE(SDEIER, 0xffffffff); | |
2317 | POSTING_READ(SDEIER); | |
2318 | } | |
2319 | ||
d18ea1b5 DV |
2320 | static void gen5_gt_irq_preinstall(struct drm_device *dev) |
2321 | { | |
2322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2323 | ||
2324 | /* and GT */ | |
2325 | I915_WRITE(GTIMR, 0xffffffff); | |
2326 | I915_WRITE(GTIER, 0x0); | |
2327 | POSTING_READ(GTIER); | |
2328 | ||
2329 | if (INTEL_INFO(dev)->gen >= 6) { | |
2330 | /* and PM */ | |
2331 | I915_WRITE(GEN6_PMIMR, 0xffffffff); | |
2332 | I915_WRITE(GEN6_PMIER, 0x0); | |
2333 | POSTING_READ(GEN6_PMIER); | |
2334 | } | |
2335 | } | |
2336 | ||
1da177e4 LT |
2337 | /* drm_dma.h hooks |
2338 | */ | |
f71d4af4 | 2339 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
2340 | { |
2341 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2342 | ||
4697995b JB |
2343 | atomic_set(&dev_priv->irq_received, 0); |
2344 | ||
036a4a7d | 2345 | I915_WRITE(HWSTAM, 0xeffe); |
bdfcdb63 | 2346 | |
036a4a7d ZW |
2347 | I915_WRITE(DEIMR, 0xffffffff); |
2348 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 2349 | POSTING_READ(DEIER); |
036a4a7d | 2350 | |
d18ea1b5 | 2351 | gen5_gt_irq_preinstall(dev); |
c650156a | 2352 | |
91738a95 | 2353 | ibx_irq_preinstall(dev); |
7d99163d BW |
2354 | } |
2355 | ||
7e231dbe JB |
2356 | static void valleyview_irq_preinstall(struct drm_device *dev) |
2357 | { | |
2358 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2359 | int pipe; | |
2360 | ||
2361 | atomic_set(&dev_priv->irq_received, 0); | |
2362 | ||
7e231dbe JB |
2363 | /* VLV magic */ |
2364 | I915_WRITE(VLV_IMR, 0); | |
2365 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
2366 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
2367 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
2368 | ||
7e231dbe JB |
2369 | /* and GT */ |
2370 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2371 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
d18ea1b5 DV |
2372 | |
2373 | gen5_gt_irq_preinstall(dev); | |
7e231dbe JB |
2374 | |
2375 | I915_WRITE(DPINVGTT, 0xff); | |
2376 | ||
2377 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2378 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2379 | for_each_pipe(pipe) | |
2380 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2381 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2382 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2383 | I915_WRITE(VLV_IER, 0x0); | |
2384 | POSTING_READ(VLV_IER); | |
2385 | } | |
2386 | ||
82a28bcf | 2387 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 KP |
2388 | { |
2389 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf DV |
2390 | struct drm_mode_config *mode_config = &dev->mode_config; |
2391 | struct intel_encoder *intel_encoder; | |
fee884ed | 2392 | u32 hotplug_irqs, hotplug, enabled_irqs = 0; |
82a28bcf DV |
2393 | |
2394 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 2395 | hotplug_irqs = SDE_HOTPLUG_MASK; |
82a28bcf | 2396 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2397 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2398 | enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; |
82a28bcf | 2399 | } else { |
fee884ed | 2400 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
82a28bcf | 2401 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
cd569aed | 2402 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) |
fee884ed | 2403 | enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; |
82a28bcf | 2404 | } |
7fe0b973 | 2405 | |
fee884ed | 2406 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
2407 | |
2408 | /* | |
2409 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
2410 | * duration to 2ms (which is the minimum in the Display Port spec) | |
2411 | * | |
2412 | * This register is the same on all known PCH chips. | |
2413 | */ | |
7fe0b973 KP |
2414 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
2415 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
2416 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
2417 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
2418 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
2419 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
2420 | } | |
2421 | ||
d46da437 PZ |
2422 | static void ibx_irq_postinstall(struct drm_device *dev) |
2423 | { | |
2424 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
82a28bcf | 2425 | u32 mask; |
e5868a31 | 2426 | |
692a04cf DV |
2427 | if (HAS_PCH_NOP(dev)) |
2428 | return; | |
2429 | ||
8664281b PZ |
2430 | if (HAS_PCH_IBX(dev)) { |
2431 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER | | |
de032bf4 | 2432 | SDE_TRANSA_FIFO_UNDER | SDE_POISON; |
8664281b PZ |
2433 | } else { |
2434 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; | |
2435 | ||
2436 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
2437 | } | |
ab5c608b | 2438 | |
d46da437 PZ |
2439 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
2440 | I915_WRITE(SDEIMR, ~mask); | |
d46da437 PZ |
2441 | } |
2442 | ||
0a9a8c91 DV |
2443 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
2444 | { | |
2445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2446 | u32 pm_irqs, gt_irqs; | |
2447 | ||
2448 | pm_irqs = gt_irqs = 0; | |
2449 | ||
2450 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 2451 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 2452 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
2453 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
2454 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
2455 | } |
2456 | ||
2457 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
2458 | if (IS_GEN5(dev)) { | |
2459 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
2460 | ILK_BSD_USER_INTERRUPT; | |
2461 | } else { | |
2462 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
2463 | } | |
2464 | ||
2465 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2466 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
2467 | I915_WRITE(GTIER, gt_irqs); | |
2468 | POSTING_READ(GTIER); | |
2469 | ||
2470 | if (INTEL_INFO(dev)->gen >= 6) { | |
2471 | pm_irqs |= GEN6_PM_RPS_EVENTS; | |
2472 | ||
2473 | if (HAS_VEBOX(dev)) | |
2474 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
2475 | ||
605cd25b | 2476 | dev_priv->pm_irq_mask = 0xffffffff; |
0a9a8c91 | 2477 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
605cd25b | 2478 | I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); |
0a9a8c91 DV |
2479 | I915_WRITE(GEN6_PMIER, pm_irqs); |
2480 | POSTING_READ(GEN6_PMIER); | |
2481 | } | |
2482 | } | |
2483 | ||
f71d4af4 | 2484 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 2485 | { |
4bc9d430 | 2486 | unsigned long irqflags; |
036a4a7d | 2487 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
8e76f8dc PZ |
2488 | u32 display_mask, extra_mask; |
2489 | ||
2490 | if (INTEL_INFO(dev)->gen >= 7) { | |
2491 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
2492 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
2493 | DE_PLANEB_FLIP_DONE_IVB | | |
2494 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB | | |
2495 | DE_ERR_INT_IVB); | |
2496 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | | |
2497 | DE_PIPEA_VBLANK_IVB); | |
2498 | ||
2499 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
2500 | } else { | |
2501 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
2502 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
2503 | DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN | | |
2504 | DE_PIPEA_FIFO_UNDERRUN | DE_POISON); | |
2505 | extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT; | |
2506 | } | |
036a4a7d | 2507 | |
1ec14ad3 | 2508 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
2509 | |
2510 | /* should always can generate irq */ | |
2511 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 | 2512 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
8e76f8dc | 2513 | I915_WRITE(DEIER, display_mask | extra_mask); |
3143a2bf | 2514 | POSTING_READ(DEIER); |
036a4a7d | 2515 | |
0a9a8c91 | 2516 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 2517 | |
d46da437 | 2518 | ibx_irq_postinstall(dev); |
7fe0b973 | 2519 | |
f97108d1 | 2520 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
2521 | /* Enable PCU event interrupts |
2522 | * | |
2523 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
2524 | * setup is guaranteed to run in single-threaded context. But we |
2525 | * need it to make the assert_spin_locked happy. */ | |
2526 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
f97108d1 | 2527 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
4bc9d430 | 2528 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
f97108d1 JB |
2529 | } |
2530 | ||
036a4a7d ZW |
2531 | return 0; |
2532 | } | |
2533 | ||
7e231dbe JB |
2534 | static int valleyview_irq_postinstall(struct drm_device *dev) |
2535 | { | |
2536 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7e231dbe | 2537 | u32 enable_mask; |
31acc7f5 | 2538 | u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; |
b79480ba | 2539 | unsigned long irqflags; |
7e231dbe JB |
2540 | |
2541 | enable_mask = I915_DISPLAY_PORT_INTERRUPT; | |
31acc7f5 JB |
2542 | enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
2543 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2544 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
7e231dbe JB |
2545 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; |
2546 | ||
31acc7f5 JB |
2547 | /* |
2548 | *Leave vblank interrupts masked initially. enable/disable will | |
2549 | * toggle them based on usage. | |
2550 | */ | |
2551 | dev_priv->irq_mask = (~enable_mask) | | |
2552 | I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | | |
2553 | I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; | |
7e231dbe | 2554 | |
20afbda2 DV |
2555 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2556 | POSTING_READ(PORT_HOTPLUG_EN); | |
2557 | ||
7e231dbe JB |
2558 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
2559 | I915_WRITE(VLV_IER, enable_mask); | |
2560 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2561 | I915_WRITE(PIPESTAT(0), 0xffff); | |
2562 | I915_WRITE(PIPESTAT(1), 0xffff); | |
2563 | POSTING_READ(VLV_IER); | |
2564 | ||
b79480ba DV |
2565 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
2566 | * just to make the assert_spin_locked check happy. */ | |
2567 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2568 | i915_enable_pipestat(dev_priv, 0, pipestat_enable); |
515ac2bb | 2569 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
31acc7f5 | 2570 | i915_enable_pipestat(dev_priv, 1, pipestat_enable); |
b79480ba | 2571 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2572 | |
7e231dbe JB |
2573 | I915_WRITE(VLV_IIR, 0xffffffff); |
2574 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2575 | ||
0a9a8c91 | 2576 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
2577 | |
2578 | /* ack & enable invalid PTE error interrupts */ | |
2579 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
2580 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
2581 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
2582 | #endif | |
2583 | ||
2584 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
2585 | |
2586 | return 0; | |
2587 | } | |
2588 | ||
7e231dbe JB |
2589 | static void valleyview_irq_uninstall(struct drm_device *dev) |
2590 | { | |
2591 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2592 | int pipe; | |
2593 | ||
2594 | if (!dev_priv) | |
2595 | return; | |
2596 | ||
ac4c16c5 EE |
2597 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2598 | ||
7e231dbe JB |
2599 | for_each_pipe(pipe) |
2600 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2601 | ||
2602 | I915_WRITE(HWSTAM, 0xffffffff); | |
2603 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2604 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2605 | for_each_pipe(pipe) | |
2606 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
2607 | I915_WRITE(VLV_IIR, 0xffffffff); | |
2608 | I915_WRITE(VLV_IMR, 0xffffffff); | |
2609 | I915_WRITE(VLV_IER, 0x0); | |
2610 | POSTING_READ(VLV_IER); | |
2611 | } | |
2612 | ||
f71d4af4 | 2613 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2614 | { |
2615 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2616 | |
2617 | if (!dev_priv) | |
2618 | return; | |
2619 | ||
ac4c16c5 EE |
2620 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
2621 | ||
036a4a7d ZW |
2622 | I915_WRITE(HWSTAM, 0xffffffff); |
2623 | ||
2624 | I915_WRITE(DEIMR, 0xffffffff); | |
2625 | I915_WRITE(DEIER, 0x0); | |
2626 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
8664281b PZ |
2627 | if (IS_GEN7(dev)) |
2628 | I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); | |
036a4a7d ZW |
2629 | |
2630 | I915_WRITE(GTIMR, 0xffffffff); | |
2631 | I915_WRITE(GTIER, 0x0); | |
2632 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
192aac1f | 2633 | |
ab5c608b BW |
2634 | if (HAS_PCH_NOP(dev)) |
2635 | return; | |
2636 | ||
192aac1f KP |
2637 | I915_WRITE(SDEIMR, 0xffffffff); |
2638 | I915_WRITE(SDEIER, 0x0); | |
2639 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
8664281b PZ |
2640 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) |
2641 | I915_WRITE(SERR_INT, I915_READ(SERR_INT)); | |
036a4a7d ZW |
2642 | } |
2643 | ||
a266c7d5 | 2644 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
2645 | { |
2646 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2647 | int pipe; |
91e3738e | 2648 | |
a266c7d5 | 2649 | atomic_set(&dev_priv->irq_received, 0); |
5ca58282 | 2650 | |
9db4a9c7 JB |
2651 | for_each_pipe(pipe) |
2652 | I915_WRITE(PIPESTAT(pipe), 0); | |
a266c7d5 CW |
2653 | I915_WRITE16(IMR, 0xffff); |
2654 | I915_WRITE16(IER, 0x0); | |
2655 | POSTING_READ16(IER); | |
c2798b19 CW |
2656 | } |
2657 | ||
2658 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
2659 | { | |
2660 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2661 | ||
c2798b19 CW |
2662 | I915_WRITE16(EMR, |
2663 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
2664 | ||
2665 | /* Unmask the interrupts that we always want on. */ | |
2666 | dev_priv->irq_mask = | |
2667 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2668 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2669 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2670 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2671 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2672 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
2673 | ||
2674 | I915_WRITE16(IER, | |
2675 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2676 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2677 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2678 | I915_USER_INTERRUPT); | |
2679 | POSTING_READ16(IER); | |
2680 | ||
2681 | return 0; | |
2682 | } | |
2683 | ||
90a72f87 VS |
2684 | /* |
2685 | * Returns true when a page flip has completed. | |
2686 | */ | |
2687 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
2688 | int pipe, u16 iir) | |
2689 | { | |
2690 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2691 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe); | |
2692 | ||
2693 | if (!drm_handle_vblank(dev, pipe)) | |
2694 | return false; | |
2695 | ||
2696 | if ((iir & flip_pending) == 0) | |
2697 | return false; | |
2698 | ||
2699 | intel_prepare_page_flip(dev, pipe); | |
2700 | ||
2701 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2702 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2703 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2704 | * the flip is completed (no longer pending). Since this doesn't raise | |
2705 | * an interrupt per se, we watch for the change at vblank. | |
2706 | */ | |
2707 | if (I915_READ16(ISR) & flip_pending) | |
2708 | return false; | |
2709 | ||
2710 | intel_finish_page_flip(dev, pipe); | |
2711 | ||
2712 | return true; | |
2713 | } | |
2714 | ||
ff1f525e | 2715 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 CW |
2716 | { |
2717 | struct drm_device *dev = (struct drm_device *) arg; | |
2718 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
c2798b19 CW |
2719 | u16 iir, new_iir; |
2720 | u32 pipe_stats[2]; | |
2721 | unsigned long irqflags; | |
c2798b19 CW |
2722 | int pipe; |
2723 | u16 flip_mask = | |
2724 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2725 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
2726 | ||
2727 | atomic_inc(&dev_priv->irq_received); | |
2728 | ||
2729 | iir = I915_READ16(IIR); | |
2730 | if (iir == 0) | |
2731 | return IRQ_NONE; | |
2732 | ||
2733 | while (iir & ~flip_mask) { | |
2734 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2735 | * have been cleared after the pipestat interrupt was received. | |
2736 | * It doesn't set the bit in iir again, but it still produces | |
2737 | * interrupts (for non-MSI). | |
2738 | */ | |
2739 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2740 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2741 | i915_handle_error(dev, false); | |
2742 | ||
2743 | for_each_pipe(pipe) { | |
2744 | int reg = PIPESTAT(pipe); | |
2745 | pipe_stats[pipe] = I915_READ(reg); | |
2746 | ||
2747 | /* | |
2748 | * Clear the PIPE*STAT regs before the IIR | |
2749 | */ | |
2750 | if (pipe_stats[pipe] & 0x8000ffff) { | |
2751 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2752 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2753 | pipe_name(pipe)); | |
2754 | I915_WRITE(reg, pipe_stats[pipe]); | |
c2798b19 CW |
2755 | } |
2756 | } | |
2757 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2758 | ||
2759 | I915_WRITE16(IIR, iir & ~flip_mask); | |
2760 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
2761 | ||
d05c617e | 2762 | i915_update_dri1_breadcrumb(dev); |
c2798b19 CW |
2763 | |
2764 | if (iir & I915_USER_INTERRUPT) | |
2765 | notify_ring(dev, &dev_priv->ring[RCS]); | |
2766 | ||
2767 | if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2768 | i8xx_handle_vblank(dev, 0, iir)) |
2769 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0); | |
c2798b19 CW |
2770 | |
2771 | if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && | |
90a72f87 VS |
2772 | i8xx_handle_vblank(dev, 1, iir)) |
2773 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1); | |
c2798b19 CW |
2774 | |
2775 | iir = new_iir; | |
2776 | } | |
2777 | ||
2778 | return IRQ_HANDLED; | |
2779 | } | |
2780 | ||
2781 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
2782 | { | |
2783 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2784 | int pipe; | |
2785 | ||
c2798b19 CW |
2786 | for_each_pipe(pipe) { |
2787 | /* Clear enable bits; then clear status bits */ | |
2788 | I915_WRITE(PIPESTAT(pipe), 0); | |
2789 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
2790 | } | |
2791 | I915_WRITE16(IMR, 0xffff); | |
2792 | I915_WRITE16(IER, 0x0); | |
2793 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
2794 | } | |
2795 | ||
a266c7d5 CW |
2796 | static void i915_irq_preinstall(struct drm_device * dev) |
2797 | { | |
2798 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2799 | int pipe; | |
2800 | ||
2801 | atomic_set(&dev_priv->irq_received, 0); | |
2802 | ||
2803 | if (I915_HAS_HOTPLUG(dev)) { | |
2804 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2805 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2806 | } | |
2807 | ||
00d98ebd | 2808 | I915_WRITE16(HWSTAM, 0xeffe); |
a266c7d5 CW |
2809 | for_each_pipe(pipe) |
2810 | I915_WRITE(PIPESTAT(pipe), 0); | |
2811 | I915_WRITE(IMR, 0xffffffff); | |
2812 | I915_WRITE(IER, 0x0); | |
2813 | POSTING_READ(IER); | |
2814 | } | |
2815 | ||
2816 | static int i915_irq_postinstall(struct drm_device *dev) | |
2817 | { | |
2818 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
38bde180 | 2819 | u32 enable_mask; |
a266c7d5 | 2820 | |
38bde180 CW |
2821 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
2822 | ||
2823 | /* Unmask the interrupts that we always want on. */ | |
2824 | dev_priv->irq_mask = | |
2825 | ~(I915_ASLE_INTERRUPT | | |
2826 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2827 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2828 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2829 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
2830 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2831 | ||
2832 | enable_mask = | |
2833 | I915_ASLE_INTERRUPT | | |
2834 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
2835 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
2836 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | | |
2837 | I915_USER_INTERRUPT; | |
2838 | ||
a266c7d5 | 2839 | if (I915_HAS_HOTPLUG(dev)) { |
20afbda2 DV |
2840 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
2841 | POSTING_READ(PORT_HOTPLUG_EN); | |
2842 | ||
a266c7d5 CW |
2843 | /* Enable in IER... */ |
2844 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
2845 | /* and unmask in IMR */ | |
2846 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
2847 | } | |
2848 | ||
a266c7d5 CW |
2849 | I915_WRITE(IMR, dev_priv->irq_mask); |
2850 | I915_WRITE(IER, enable_mask); | |
2851 | POSTING_READ(IER); | |
2852 | ||
f49e38dd | 2853 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
2854 | |
2855 | return 0; | |
2856 | } | |
2857 | ||
90a72f87 VS |
2858 | /* |
2859 | * Returns true when a page flip has completed. | |
2860 | */ | |
2861 | static bool i915_handle_vblank(struct drm_device *dev, | |
2862 | int plane, int pipe, u32 iir) | |
2863 | { | |
2864 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2865 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); | |
2866 | ||
2867 | if (!drm_handle_vblank(dev, pipe)) | |
2868 | return false; | |
2869 | ||
2870 | if ((iir & flip_pending) == 0) | |
2871 | return false; | |
2872 | ||
2873 | intel_prepare_page_flip(dev, plane); | |
2874 | ||
2875 | /* We detect FlipDone by looking for the change in PendingFlip from '1' | |
2876 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
2877 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
2878 | * the flip is completed (no longer pending). Since this doesn't raise | |
2879 | * an interrupt per se, we watch for the change at vblank. | |
2880 | */ | |
2881 | if (I915_READ(ISR) & flip_pending) | |
2882 | return false; | |
2883 | ||
2884 | intel_finish_page_flip(dev, pipe); | |
2885 | ||
2886 | return true; | |
2887 | } | |
2888 | ||
ff1f525e | 2889 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 CW |
2890 | { |
2891 | struct drm_device *dev = (struct drm_device *) arg; | |
2892 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8291ee90 | 2893 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
a266c7d5 | 2894 | unsigned long irqflags; |
38bde180 CW |
2895 | u32 flip_mask = |
2896 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
2897 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 2898 | int pipe, ret = IRQ_NONE; |
a266c7d5 CW |
2899 | |
2900 | atomic_inc(&dev_priv->irq_received); | |
2901 | ||
2902 | iir = I915_READ(IIR); | |
38bde180 CW |
2903 | do { |
2904 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 2905 | bool blc_event = false; |
a266c7d5 CW |
2906 | |
2907 | /* Can't rely on pipestat interrupt bit in iir as it might | |
2908 | * have been cleared after the pipestat interrupt was received. | |
2909 | * It doesn't set the bit in iir again, but it still produces | |
2910 | * interrupts (for non-MSI). | |
2911 | */ | |
2912 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
2913 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
2914 | i915_handle_error(dev, false); | |
2915 | ||
2916 | for_each_pipe(pipe) { | |
2917 | int reg = PIPESTAT(pipe); | |
2918 | pipe_stats[pipe] = I915_READ(reg); | |
2919 | ||
38bde180 | 2920 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 CW |
2921 | if (pipe_stats[pipe] & 0x8000ffff) { |
2922 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
2923 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
2924 | pipe_name(pipe)); | |
2925 | I915_WRITE(reg, pipe_stats[pipe]); | |
38bde180 | 2926 | irq_received = true; |
a266c7d5 CW |
2927 | } |
2928 | } | |
2929 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
2930 | ||
2931 | if (!irq_received) | |
2932 | break; | |
2933 | ||
a266c7d5 CW |
2934 | /* Consume port. Then clear IIR or we'll miss events */ |
2935 | if ((I915_HAS_HOTPLUG(dev)) && | |
2936 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
2937 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
b543fb04 | 2938 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; |
a266c7d5 CW |
2939 | |
2940 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
2941 | hotplug_status); | |
91d131d2 DV |
2942 | |
2943 | intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); | |
2944 | ||
a266c7d5 | 2945 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
38bde180 | 2946 | POSTING_READ(PORT_HOTPLUG_STAT); |
a266c7d5 CW |
2947 | } |
2948 | ||
38bde180 | 2949 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
2950 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
2951 | ||
a266c7d5 CW |
2952 | if (iir & I915_USER_INTERRUPT) |
2953 | notify_ring(dev, &dev_priv->ring[RCS]); | |
a266c7d5 | 2954 | |
a266c7d5 | 2955 | for_each_pipe(pipe) { |
38bde180 CW |
2956 | int plane = pipe; |
2957 | if (IS_MOBILE(dev)) | |
2958 | plane = !plane; | |
90a72f87 | 2959 | |
8291ee90 | 2960 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
2961 | i915_handle_vblank(dev, plane, pipe, iir)) |
2962 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
2963 | |
2964 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
2965 | blc_event = true; | |
2966 | } | |
2967 | ||
a266c7d5 CW |
2968 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
2969 | intel_opregion_asle_intr(dev); | |
2970 | ||
2971 | /* With MSI, interrupts are only generated when iir | |
2972 | * transitions from zero to nonzero. If another bit got | |
2973 | * set while we were handling the existing iir bits, then | |
2974 | * we would never get another interrupt. | |
2975 | * | |
2976 | * This is fine on non-MSI as well, as if we hit this path | |
2977 | * we avoid exiting the interrupt handler only to generate | |
2978 | * another one. | |
2979 | * | |
2980 | * Note that for MSI this could cause a stray interrupt report | |
2981 | * if an interrupt landed in the time between writing IIR and | |
2982 | * the posting read. This should be rare enough to never | |
2983 | * trigger the 99% of 100,000 interrupts test for disabling | |
2984 | * stray interrupts. | |
2985 | */ | |
38bde180 | 2986 | ret = IRQ_HANDLED; |
a266c7d5 | 2987 | iir = new_iir; |
38bde180 | 2988 | } while (iir & ~flip_mask); |
a266c7d5 | 2989 | |
d05c617e | 2990 | i915_update_dri1_breadcrumb(dev); |
8291ee90 | 2991 | |
a266c7d5 CW |
2992 | return ret; |
2993 | } | |
2994 | ||
2995 | static void i915_irq_uninstall(struct drm_device * dev) | |
2996 | { | |
2997 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
2998 | int pipe; | |
2999 | ||
ac4c16c5 EE |
3000 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3001 | ||
a266c7d5 CW |
3002 | if (I915_HAS_HOTPLUG(dev)) { |
3003 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
3004 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
3005 | } | |
3006 | ||
00d98ebd | 3007 | I915_WRITE16(HWSTAM, 0xffff); |
55b39755 CW |
3008 | for_each_pipe(pipe) { |
3009 | /* Clear enable bits; then clear status bits */ | |
a266c7d5 | 3010 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
3011 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
3012 | } | |
a266c7d5 CW |
3013 | I915_WRITE(IMR, 0xffffffff); |
3014 | I915_WRITE(IER, 0x0); | |
3015 | ||
a266c7d5 CW |
3016 | I915_WRITE(IIR, I915_READ(IIR)); |
3017 | } | |
3018 | ||
3019 | static void i965_irq_preinstall(struct drm_device * dev) | |
3020 | { | |
3021 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3022 | int pipe; | |
3023 | ||
3024 | atomic_set(&dev_priv->irq_received, 0); | |
3025 | ||
adca4730 CW |
3026 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3027 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3028 | |
3029 | I915_WRITE(HWSTAM, 0xeffe); | |
3030 | for_each_pipe(pipe) | |
3031 | I915_WRITE(PIPESTAT(pipe), 0); | |
3032 | I915_WRITE(IMR, 0xffffffff); | |
3033 | I915_WRITE(IER, 0x0); | |
3034 | POSTING_READ(IER); | |
3035 | } | |
3036 | ||
3037 | static int i965_irq_postinstall(struct drm_device *dev) | |
3038 | { | |
3039 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
bbba0a97 | 3040 | u32 enable_mask; |
a266c7d5 | 3041 | u32 error_mask; |
b79480ba | 3042 | unsigned long irqflags; |
a266c7d5 | 3043 | |
a266c7d5 | 3044 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 3045 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 3046 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
3047 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
3048 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3049 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3050 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
3051 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
3052 | ||
3053 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
3054 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
3055 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
3056 | enable_mask |= I915_USER_INTERRUPT; |
3057 | ||
3058 | if (IS_G4X(dev)) | |
3059 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 3060 | |
b79480ba DV |
3061 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3062 | * just to make the assert_spin_locked check happy. */ | |
3063 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
515ac2bb | 3064 | i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); |
b79480ba | 3065 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
a266c7d5 | 3066 | |
a266c7d5 CW |
3067 | /* |
3068 | * Enable some error detection, note the instruction error mask | |
3069 | * bit is reserved, so we leave it masked. | |
3070 | */ | |
3071 | if (IS_G4X(dev)) { | |
3072 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
3073 | GM45_ERROR_MEM_PRIV | | |
3074 | GM45_ERROR_CP_PRIV | | |
3075 | I915_ERROR_MEMORY_REFRESH); | |
3076 | } else { | |
3077 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
3078 | I915_ERROR_MEMORY_REFRESH); | |
3079 | } | |
3080 | I915_WRITE(EMR, error_mask); | |
3081 | ||
3082 | I915_WRITE(IMR, dev_priv->irq_mask); | |
3083 | I915_WRITE(IER, enable_mask); | |
3084 | POSTING_READ(IER); | |
3085 | ||
20afbda2 DV |
3086 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3087 | POSTING_READ(PORT_HOTPLUG_EN); | |
3088 | ||
f49e38dd | 3089 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
3090 | |
3091 | return 0; | |
3092 | } | |
3093 | ||
bac56d5b | 3094 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 DV |
3095 | { |
3096 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e5868a31 | 3097 | struct drm_mode_config *mode_config = &dev->mode_config; |
cd569aed | 3098 | struct intel_encoder *intel_encoder; |
20afbda2 DV |
3099 | u32 hotplug_en; |
3100 | ||
b5ea2d56 DV |
3101 | assert_spin_locked(&dev_priv->irq_lock); |
3102 | ||
bac56d5b EE |
3103 | if (I915_HAS_HOTPLUG(dev)) { |
3104 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
3105 | hotplug_en &= ~HOTPLUG_INT_EN_MASK; | |
3106 | /* Note HDMI and DP share hotplug bits */ | |
e5868a31 | 3107 | /* enable bits are the same for all generations */ |
cd569aed EE |
3108 | list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) |
3109 | if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) | |
3110 | hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; | |
bac56d5b EE |
3111 | /* Programming the CRT detection parameters tends |
3112 | to generate a spurious hotplug event about three | |
3113 | seconds later. So just do it once. | |
3114 | */ | |
3115 | if (IS_G4X(dev)) | |
3116 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
85fc95ba | 3117 | hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; |
bac56d5b | 3118 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
a266c7d5 | 3119 | |
bac56d5b EE |
3120 | /* Ignore TV since it's buggy */ |
3121 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
3122 | } | |
a266c7d5 CW |
3123 | } |
3124 | ||
ff1f525e | 3125 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 CW |
3126 | { |
3127 | struct drm_device *dev = (struct drm_device *) arg; | |
3128 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
a266c7d5 CW |
3129 | u32 iir, new_iir; |
3130 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 CW |
3131 | unsigned long irqflags; |
3132 | int irq_received; | |
3133 | int ret = IRQ_NONE, pipe; | |
21ad8330 VS |
3134 | u32 flip_mask = |
3135 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3136 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 CW |
3137 | |
3138 | atomic_inc(&dev_priv->irq_received); | |
3139 | ||
3140 | iir = I915_READ(IIR); | |
3141 | ||
a266c7d5 | 3142 | for (;;) { |
2c8ba29f CW |
3143 | bool blc_event = false; |
3144 | ||
21ad8330 | 3145 | irq_received = (iir & ~flip_mask) != 0; |
a266c7d5 CW |
3146 | |
3147 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3148 | * have been cleared after the pipestat interrupt was received. | |
3149 | * It doesn't set the bit in iir again, but it still produces | |
3150 | * interrupts (for non-MSI). | |
3151 | */ | |
3152 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3153 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
3154 | i915_handle_error(dev, false); | |
3155 | ||
3156 | for_each_pipe(pipe) { | |
3157 | int reg = PIPESTAT(pipe); | |
3158 | pipe_stats[pipe] = I915_READ(reg); | |
3159 | ||
3160 | /* | |
3161 | * Clear the PIPE*STAT regs before the IIR | |
3162 | */ | |
3163 | if (pipe_stats[pipe] & 0x8000ffff) { | |
3164 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
3165 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
3166 | pipe_name(pipe)); | |
3167 | I915_WRITE(reg, pipe_stats[pipe]); | |
3168 | irq_received = 1; | |
3169 | } | |
3170 | } | |
3171 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3172 | ||
3173 | if (!irq_received) | |
3174 | break; | |
3175 | ||
3176 | ret = IRQ_HANDLED; | |
3177 | ||
3178 | /* Consume port. Then clear IIR or we'll miss events */ | |
adca4730 | 3179 | if (iir & I915_DISPLAY_PORT_INTERRUPT) { |
a266c7d5 | 3180 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
b543fb04 EE |
3181 | u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? |
3182 | HOTPLUG_INT_STATUS_G4X : | |
4f7fd709 | 3183 | HOTPLUG_INT_STATUS_I915); |
a266c7d5 CW |
3184 | |
3185 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", | |
3186 | hotplug_status); | |
91d131d2 DV |
3187 | |
3188 | intel_hpd_irq_handler(dev, hotplug_trigger, | |
3189 | IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); | |
3190 | ||
a266c7d5 CW |
3191 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
3192 | I915_READ(PORT_HOTPLUG_STAT); | |
3193 | } | |
3194 | ||
21ad8330 | 3195 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
3196 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
3197 | ||
a266c7d5 CW |
3198 | if (iir & I915_USER_INTERRUPT) |
3199 | notify_ring(dev, &dev_priv->ring[RCS]); | |
3200 | if (iir & I915_BSD_USER_INTERRUPT) | |
3201 | notify_ring(dev, &dev_priv->ring[VCS]); | |
3202 | ||
a266c7d5 | 3203 | for_each_pipe(pipe) { |
2c8ba29f | 3204 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
3205 | i915_handle_vblank(dev, pipe, pipe, iir)) |
3206 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
3207 | |
3208 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
3209 | blc_event = true; | |
3210 | } | |
3211 | ||
3212 | ||
3213 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3214 | intel_opregion_asle_intr(dev); | |
3215 | ||
515ac2bb DV |
3216 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
3217 | gmbus_irq_handler(dev); | |
3218 | ||
a266c7d5 CW |
3219 | /* With MSI, interrupts are only generated when iir |
3220 | * transitions from zero to nonzero. If another bit got | |
3221 | * set while we were handling the existing iir bits, then | |
3222 | * we would never get another interrupt. | |
3223 | * | |
3224 | * This is fine on non-MSI as well, as if we hit this path | |
3225 | * we avoid exiting the interrupt handler only to generate | |
3226 | * another one. | |
3227 | * | |
3228 | * Note that for MSI this could cause a stray interrupt report | |
3229 | * if an interrupt landed in the time between writing IIR and | |
3230 | * the posting read. This should be rare enough to never | |
3231 | * trigger the 99% of 100,000 interrupts test for disabling | |
3232 | * stray interrupts. | |
3233 | */ | |
3234 | iir = new_iir; | |
3235 | } | |
3236 | ||
d05c617e | 3237 | i915_update_dri1_breadcrumb(dev); |
2c8ba29f | 3238 | |
a266c7d5 CW |
3239 | return ret; |
3240 | } | |
3241 | ||
3242 | static void i965_irq_uninstall(struct drm_device * dev) | |
3243 | { | |
3244 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
3245 | int pipe; | |
3246 | ||
3247 | if (!dev_priv) | |
3248 | return; | |
3249 | ||
ac4c16c5 EE |
3250 | del_timer_sync(&dev_priv->hotplug_reenable_timer); |
3251 | ||
adca4730 CW |
3252 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
3253 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
a266c7d5 CW |
3254 | |
3255 | I915_WRITE(HWSTAM, 0xffffffff); | |
3256 | for_each_pipe(pipe) | |
3257 | I915_WRITE(PIPESTAT(pipe), 0); | |
3258 | I915_WRITE(IMR, 0xffffffff); | |
3259 | I915_WRITE(IER, 0x0); | |
3260 | ||
3261 | for_each_pipe(pipe) | |
3262 | I915_WRITE(PIPESTAT(pipe), | |
3263 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
3264 | I915_WRITE(IIR, I915_READ(IIR)); | |
3265 | } | |
3266 | ||
ac4c16c5 EE |
3267 | static void i915_reenable_hotplug_timer_func(unsigned long data) |
3268 | { | |
3269 | drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; | |
3270 | struct drm_device *dev = dev_priv->dev; | |
3271 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3272 | unsigned long irqflags; | |
3273 | int i; | |
3274 | ||
3275 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3276 | for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { | |
3277 | struct drm_connector *connector; | |
3278 | ||
3279 | if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) | |
3280 | continue; | |
3281 | ||
3282 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3283 | ||
3284 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3285 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3286 | ||
3287 | if (intel_connector->encoder->hpd_pin == i) { | |
3288 | if (connector->polled != intel_connector->polled) | |
3289 | DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", | |
3290 | drm_get_connector_name(connector)); | |
3291 | connector->polled = intel_connector->polled; | |
3292 | if (!connector->polled) | |
3293 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3294 | } | |
3295 | } | |
3296 | } | |
3297 | if (dev_priv->display.hpd_irq_setup) | |
3298 | dev_priv->display.hpd_irq_setup(dev); | |
3299 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3300 | } | |
3301 | ||
f71d4af4 JB |
3302 | void intel_irq_init(struct drm_device *dev) |
3303 | { | |
8b2e326d CW |
3304 | struct drm_i915_private *dev_priv = dev->dev_private; |
3305 | ||
3306 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
99584db3 | 3307 | INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); |
c6a828d3 | 3308 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 3309 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 3310 | |
99584db3 DV |
3311 | setup_timer(&dev_priv->gpu_error.hangcheck_timer, |
3312 | i915_hangcheck_elapsed, | |
61bac78e | 3313 | (unsigned long) dev); |
ac4c16c5 EE |
3314 | setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, |
3315 | (unsigned long) dev_priv); | |
61bac78e | 3316 | |
97a19a24 | 3317 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 3318 | |
4cdb83ec VS |
3319 | if (IS_GEN2(dev)) { |
3320 | dev->max_vblank_count = 0; | |
3321 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
3322 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
f71d4af4 JB |
3323 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
3324 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
3325 | } else { |
3326 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
3327 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
3328 | } |
3329 | ||
c2baf4b7 | 3330 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
c3613de9 | 3331 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
c2baf4b7 VS |
3332 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
3333 | } | |
f71d4af4 | 3334 | |
7e231dbe JB |
3335 | if (IS_VALLEYVIEW(dev)) { |
3336 | dev->driver->irq_handler = valleyview_irq_handler; | |
3337 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
3338 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
3339 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
3340 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
3341 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 3342 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
f71d4af4 JB |
3343 | } else if (HAS_PCH_SPLIT(dev)) { |
3344 | dev->driver->irq_handler = ironlake_irq_handler; | |
3345 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
3346 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
3347 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
3348 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
3349 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
82a28bcf | 3350 | dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; |
f71d4af4 | 3351 | } else { |
c2798b19 CW |
3352 | if (INTEL_INFO(dev)->gen == 2) { |
3353 | dev->driver->irq_preinstall = i8xx_irq_preinstall; | |
3354 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
3355 | dev->driver->irq_handler = i8xx_irq_handler; | |
3356 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
a266c7d5 CW |
3357 | } else if (INTEL_INFO(dev)->gen == 3) { |
3358 | dev->driver->irq_preinstall = i915_irq_preinstall; | |
3359 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
3360 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
3361 | dev->driver->irq_handler = i915_irq_handler; | |
20afbda2 | 3362 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3363 | } else { |
a266c7d5 CW |
3364 | dev->driver->irq_preinstall = i965_irq_preinstall; |
3365 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
3366 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
3367 | dev->driver->irq_handler = i965_irq_handler; | |
bac56d5b | 3368 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
c2798b19 | 3369 | } |
f71d4af4 JB |
3370 | dev->driver->enable_vblank = i915_enable_vblank; |
3371 | dev->driver->disable_vblank = i915_disable_vblank; | |
3372 | } | |
3373 | } | |
20afbda2 DV |
3374 | |
3375 | void intel_hpd_init(struct drm_device *dev) | |
3376 | { | |
3377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821450c6 EE |
3378 | struct drm_mode_config *mode_config = &dev->mode_config; |
3379 | struct drm_connector *connector; | |
b5ea2d56 | 3380 | unsigned long irqflags; |
821450c6 | 3381 | int i; |
20afbda2 | 3382 | |
821450c6 EE |
3383 | for (i = 1; i < HPD_NUM_PINS; i++) { |
3384 | dev_priv->hpd_stats[i].hpd_cnt = 0; | |
3385 | dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; | |
3386 | } | |
3387 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
3388 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
3389 | connector->polled = intel_connector->polled; | |
3390 | if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) | |
3391 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
3392 | } | |
b5ea2d56 DV |
3393 | |
3394 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3395 | * just to make the assert_spin_locked checks happy. */ | |
3396 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
20afbda2 DV |
3397 | if (dev_priv->display.hpd_irq_setup) |
3398 | dev_priv->display.hpd_irq_setup(dev); | |
b5ea2d56 | 3399 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
20afbda2 | 3400 | } |
c67a470b PZ |
3401 | |
3402 | /* Disable interrupts so we can allow Package C8+. */ | |
3403 | void hsw_pc8_disable_interrupts(struct drm_device *dev) | |
3404 | { | |
3405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3406 | unsigned long irqflags; | |
3407 | ||
3408 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3409 | ||
3410 | dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); | |
3411 | dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); | |
3412 | dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); | |
3413 | dev_priv->pc8.regsave.gtier = I915_READ(GTIER); | |
3414 | dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); | |
3415 | ||
3416 | ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB); | |
3417 | ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT); | |
3418 | ilk_disable_gt_irq(dev_priv, 0xffffffff); | |
3419 | snb_disable_pm_irq(dev_priv, 0xffffffff); | |
3420 | ||
3421 | dev_priv->pc8.irqs_disabled = true; | |
3422 | ||
3423 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3424 | } | |
3425 | ||
3426 | /* Restore interrupts so we can recover from Package C8+. */ | |
3427 | void hsw_pc8_restore_interrupts(struct drm_device *dev) | |
3428 | { | |
3429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3430 | unsigned long irqflags; | |
3431 | uint32_t val, expected; | |
3432 | ||
3433 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
3434 | ||
3435 | val = I915_READ(DEIMR); | |
3436 | expected = ~DE_PCH_EVENT_IVB; | |
3437 | WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected); | |
3438 | ||
3439 | val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT; | |
3440 | expected = ~SDE_HOTPLUG_MASK_CPT; | |
3441 | WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n", | |
3442 | val, expected); | |
3443 | ||
3444 | val = I915_READ(GTIMR); | |
3445 | expected = 0xffffffff; | |
3446 | WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected); | |
3447 | ||
3448 | val = I915_READ(GEN6_PMIMR); | |
3449 | expected = 0xffffffff; | |
3450 | WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val, | |
3451 | expected); | |
3452 | ||
3453 | dev_priv->pc8.irqs_disabled = false; | |
3454 | ||
3455 | ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); | |
3456 | ibx_enable_display_interrupt(dev_priv, | |
3457 | ~dev_priv->pc8.regsave.sdeimr & | |
3458 | ~SDE_HOTPLUG_MASK_CPT); | |
3459 | ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); | |
3460 | snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); | |
3461 | I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); | |
3462 | ||
3463 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
3464 | } |