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drm/i915: fix gen4 gpu reset
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
776ad806
JB		 536static void pch_irq_handler(struct drm_device *dev)
537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
539 u32 pch_iir;
9db4a9c7 540 int pipe;
776ad806
JB		 541
542 pch_iir = I915_READ(SDEIIR);
543
544 if (pch_iir & SDE_AUDIO_POWER_MASK)
545 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
546 (pch_iir & SDE_AUDIO_POWER_MASK) >>
547 SDE_AUDIO_POWER_SHIFT);
548
549 if (pch_iir & SDE_GMBUS)
550 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_HDCP_MASK)
553 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
554
555 if (pch_iir & SDE_AUDIO_TRANS_MASK)
556 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
557
558 if (pch_iir & SDE_POISON)
559 DRM_ERROR("PCH poison interrupt\n");
560
9db4a9c7
JB		 561 if (pch_iir & SDE_FDI_MASK)
562 for_each_pipe(pipe)
563 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
564 pipe_name(pipe),
565 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 566
567 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
569
570 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
572
573 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
574 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
575 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
576 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
577}
578
f71d4af4 579static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 580{
581 struct drm_device *dev = (struct drm_device *) arg;
582 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
583 int ret = IRQ_NONE;
584 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
b1f14ad0
JB		 585
586 atomic_inc(&dev_priv->irq_received);
587
588 /* disable master interrupt before clearing iir */
589 de_ier = I915_READ(DEIER);
590 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
591 POSTING_READ(DEIER);
592
593 de_iir = I915_READ(DEIIR);
594 gt_iir = I915_READ(GTIIR);
595 pch_iir = I915_READ(SDEIIR);
596 pm_iir = I915_READ(GEN6_PMIIR);
597
598 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
599 goto done;
600
601 ret = IRQ_HANDLED;
602
e7b4c6b1 603 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 604
605 if (de_iir & DE_GSE_IVB)
606 intel_opregion_gse_intr(dev);
607
608 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
609 intel_prepare_page_flip(dev, 0);
610 intel_finish_page_flip_plane(dev, 0);
611 }
612
613 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
614 intel_prepare_page_flip(dev, 1);
615 intel_finish_page_flip_plane(dev, 1);
616 }
617
618 if (de_iir & DE_PIPEA_VBLANK_IVB)
619 drm_handle_vblank(dev, 0);
620
f6b07f45 621 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 622 drm_handle_vblank(dev, 1);
623
624 /* check event from PCH */
625 if (de_iir & DE_PCH_EVENT_IVB) {
626 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
627 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
628 pch_irq_handler(dev);
629 }
630
fc6826d1
CW		 631 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
632 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 633
634 /* should clear PCH hotplug event before clear CPU irq */
635 I915_WRITE(SDEIIR, pch_iir);
636 I915_WRITE(GTIIR, gt_iir);
637 I915_WRITE(DEIIR, de_iir);
638 I915_WRITE(GEN6_PMIIR, pm_iir);
639
640done:
641 I915_WRITE(DEIER, de_ier);
642 POSTING_READ(DEIER);
643
644 return ret;
645}
646
e7b4c6b1
DV		 647static void ilk_gt_irq_handler(struct drm_device *dev,
648 struct drm_i915_private *dev_priv,
649 u32 gt_iir)
650{
651 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
652 notify_ring(dev, &dev_priv->ring[RCS]);
653 if (gt_iir & GT_BSD_USER_INTERRUPT)
654 notify_ring(dev, &dev_priv->ring[VCS]);
655}
656
f71d4af4 657static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 658{
4697995b 659 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
661 int ret = IRQ_NONE;
3b8d8d91 662 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 663 u32 hotplug_mask;
881f47b6 664
4697995b
JB		 665 atomic_inc(&dev_priv->irq_received);
666
2d109a84
ZN		 667 /* disable master interrupt before clearing iir */
668 de_ier = I915_READ(DEIER);
669 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 670 POSTING_READ(DEIER);
2d109a84 671
036a4a7d
ZW		 672 de_iir = I915_READ(DEIIR);
673 gt_iir = I915_READ(GTIIR);
c650156a 674 pch_iir = I915_READ(SDEIIR);
3b8d8d91 675 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 676
3b8d8d91
JB		 677 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
678 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 679 goto done;
036a4a7d 680
2d7b8366
YL		 681 if (HAS_PCH_CPT(dev))
682 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
683 else
684 hotplug_mask = SDE_HOTPLUG_MASK;
685
c7c85101 686 ret = IRQ_HANDLED;
036a4a7d 687
e7b4c6b1
DV		 688 if (IS_GEN5(dev))
689 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
690 else
691 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 692
c7c85101 693 if (de_iir & DE_GSE)
3b617967 694 intel_opregion_gse_intr(dev);
c650156a 695
f072d2e7 696 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 697 intel_prepare_page_flip(dev, 0);
2bbda389 698 intel_finish_page_flip_plane(dev, 0);
f072d2e7 699 }
013d5aa2 700
f072d2e7 701 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 702 intel_prepare_page_flip(dev, 1);
2bbda389 703 intel_finish_page_flip_plane(dev, 1);
f072d2e7 704 }
013d5aa2 705
f072d2e7 706 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 707 drm_handle_vblank(dev, 0);
708
f072d2e7 709 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 710 drm_handle_vblank(dev, 1);
711
c7c85101 712 /* check event from PCH */
776ad806
JB		 713 if (de_iir & DE_PCH_EVENT) {
714 if (pch_iir & hotplug_mask)
715 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
716 pch_irq_handler(dev);
717 }
036a4a7d 718
f97108d1 719 if (de_iir & DE_PCU_EVENT) {
7648fa99 720 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 721 i915_handle_rps_change(dev);
722 }
723
fc6826d1
CW		 724 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
725 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 726
c7c85101
ZN		 727 /* should clear PCH hotplug event before clear CPU irq */
728 I915_WRITE(SDEIIR, pch_iir);
729 I915_WRITE(GTIIR, gt_iir);
730 I915_WRITE(DEIIR, de_iir);
4912d041 731 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 732
733done:
2d109a84 734 I915_WRITE(DEIER, de_ier);
3143a2bf 735 POSTING_READ(DEIER);
2d109a84 736
036a4a7d
ZW		 737 return ret;
738}
739
8a905236
JB		 740/**
741 * i915_error_work_func - do process context error handling work
742 * @work: work struct
743 *
744 * Fire an error uevent so userspace can see that a hang or error
745 * was detected.
746 */
747static void i915_error_work_func(struct work_struct *work)
748{
749 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
750 error_work);
751 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 752 char *error_event[] = { "ERROR=1", NULL };
753 char *reset_event[] = { "RESET=1", NULL };
754 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 755
f316a42c
BG		 756 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
757
ba1234d1 758 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 759 DRM_DEBUG_DRIVER("resetting chip\n");
760 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 761 if (!i915_reset(dev)) {
f803aa55
CW		 762 atomic_set(&dev_priv->mm.wedged, 0);
763 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 764 }
30dbf0c0 765 complete_all(&dev_priv->error_completion);
f316a42c 766 }
8a905236
JB		 767}
768
3bd3c932 769#ifdef CONFIG_DEBUG_FS
9df30794 770static struct drm_i915_error_object *
bcfb2e28 771i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 772 struct drm_i915_gem_object *src)
9df30794
CW		 773{
774 struct drm_i915_error_object *dst;
9df30794 775 int page, page_count;
e56660dd 776 u32 reloc_offset;
9df30794 777
05394f39 778 if (src == NULL || src->pages == NULL)
9df30794
CW		 779 return NULL;
780
05394f39 781 page_count = src->base.size / PAGE_SIZE;
9df30794 782
0206e353 783 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 784 if (dst == NULL)
785 return NULL;
786
05394f39 787 reloc_offset = src->gtt_offset;
9df30794 788 for (page = 0; page < page_count; page++) {
788885ae 789 unsigned long flags;
e56660dd 790 void *d;
788885ae 791
e56660dd 792 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 793 if (d == NULL)
794 goto unwind;
e56660dd 795
788885ae 796 local_irq_save(flags);
74898d7e
DV		 797 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
798 src->has_global_gtt_mapping) {
172975aa
CW		 799 void __iomem *s;
800
801 /* Simply ignore tiling or any overlapping fence.
802 * It's part of the error state, and this hopefully
803 * captures what the GPU read.
804 */
805
806 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
807 reloc_offset);
808 memcpy_fromio(d, s, PAGE_SIZE);
809 io_mapping_unmap_atomic(s);
810 } else {
811 void *s;
812
813 drm_clflush_pages(&src->pages[page], 1);
814
815 s = kmap_atomic(src->pages[page]);
816 memcpy(d, s, PAGE_SIZE);
817 kunmap_atomic(s);
818
819 drm_clflush_pages(&src->pages[page], 1);
820 }
788885ae 821 local_irq_restore(flags);
e56660dd 822
9df30794 823 dst->pages[page] = d;
e56660dd
CW		 824
825 reloc_offset += PAGE_SIZE;
9df30794
CW		 826 }
827 dst->page_count = page_count;
05394f39 828 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 829
830 return dst;
831
832unwind:
833 while (page--)
834 kfree(dst->pages[page]);
835 kfree(dst);
836 return NULL;
837}
838
839static void
840i915_error_object_free(struct drm_i915_error_object *obj)
841{
842 int page;
843
844 if (obj == NULL)
845 return;
846
847 for (page = 0; page < obj->page_count; page++)
848 kfree(obj->pages[page]);
849
850 kfree(obj);
851}
852
742cbee8
DV		 853void
854i915_error_state_free(struct kref *error_ref)
9df30794 855{
742cbee8
DV		 856 struct drm_i915_error_state *error = container_of(error_ref,
857 typeof(*error), ref);
e2f973d5
CW		 858 int i;
859
52d39a21
CW		 860 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
861 i915_error_object_free(error->ring[i].batchbuffer);
862 i915_error_object_free(error->ring[i].ringbuffer);
863 kfree(error->ring[i].requests);
864 }
e2f973d5 865
9df30794 866 kfree(error->active_bo);
6ef3d427 867 kfree(error->overlay);
9df30794
CW		 868 kfree(error);
869}
1b50247a
CW		 870static void capture_bo(struct drm_i915_error_buffer *err,
871 struct drm_i915_gem_object *obj)
872{
873 err->size = obj->base.size;
874 err->name = obj->base.name;
875 err->seqno = obj->last_rendering_seqno;
876 err->gtt_offset = obj->gtt_offset;
877 err->read_domains = obj->base.read_domains;
878 err->write_domain = obj->base.write_domain;
879 err->fence_reg = obj->fence_reg;
880 err->pinned = 0;
881 if (obj->pin_count > 0)
882 err->pinned = 1;
883 if (obj->user_pin_count > 0)
884 err->pinned = -1;
885 err->tiling = obj->tiling_mode;
886 err->dirty = obj->dirty;
887 err->purgeable = obj->madv != I915_MADV_WILLNEED;
888 err->ring = obj->ring ? obj->ring->id : -1;
889 err->cache_level = obj->cache_level;
890}
9df30794 891
1b50247a
CW		 892static u32 capture_active_bo(struct drm_i915_error_buffer *err,
893 int count, struct list_head *head)
c724e8a9
CW		 894{
895 struct drm_i915_gem_object *obj;
896 int i = 0;
897
898 list_for_each_entry(obj, head, mm_list) {
1b50247a 899 capture_bo(err++, obj);
c724e8a9
CW		 900 if (++i == count)
901 break;
1b50247a
CW		 902 }
903
904 return i;
905}
906
907static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
908 int count, struct list_head *head)
909{
910 struct drm_i915_gem_object *obj;
911 int i = 0;
912
913 list_for_each_entry(obj, head, gtt_list) {
914 if (obj->pin_count == 0)
915 continue;
c724e8a9 916
1b50247a
CW		 917 capture_bo(err++, obj);
918 if (++i == count)
919 break;
c724e8a9
CW		 920 }
921
922 return i;
923}
924
748ebc60
CW		 925static void i915_gem_record_fences(struct drm_device *dev,
926 struct drm_i915_error_state *error)
927{
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 int i;
930
931 /* Fences */
932 switch (INTEL_INFO(dev)->gen) {
775d17b6 933 case 7:
748ebc60
CW		 934 case 6:
935 for (i = 0; i < 16; i++)
936 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
937 break;
938 case 5:
939 case 4:
940 for (i = 0; i < 16; i++)
941 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
942 break;
943 case 3:
944 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
945 for (i = 0; i < 8; i++)
946 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
947 case 2:
948 for (i = 0; i < 8; i++)
949 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
950 break;
951
952 }
953}
954
bcfb2e28
CW		 955static struct drm_i915_error_object *
956i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
957 struct intel_ring_buffer *ring)
958{
959 struct drm_i915_gem_object *obj;
960 u32 seqno;
961
962 if (!ring->get_seqno)
963 return NULL;
964
965 seqno = ring->get_seqno(ring);
966 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
967 if (obj->ring != ring)
968 continue;
969
c37d9a5d 970 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 971 continue;
972
973 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
974 continue;
975
976 /* We need to copy these to an anonymous buffer as the simplest
977 * method to avoid being overwritten by userspace.
978 */
979 return i915_error_object_create(dev_priv, obj);
980 }
981
982 return NULL;
983}
984
d27b1e0e
DV		 985static void i915_record_ring_state(struct drm_device *dev,
986 struct drm_i915_error_state *error,
987 struct intel_ring_buffer *ring)
988{
989 struct drm_i915_private *dev_priv = dev->dev_private;
990
33f3f518 991 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 992 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 993 error->semaphore_mboxes[ring->id][0]
994 = I915_READ(RING_SYNC_0(ring->mmio_base));
995 error->semaphore_mboxes[ring->id][1]
996 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 997 }
c1cd90ed 998
d27b1e0e 999 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1000 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1001 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1002 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1003 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1004 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1005 if (ring->id == RCS) {
d27b1e0e
DV		 1006 error->instdone1 = I915_READ(INSTDONE1);
1007 error->bbaddr = I915_READ64(BB_ADDR);
1008 }
1009 } else {
9d2f41fa 1010 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1011 error->ipeir[ring->id] = I915_READ(IPEIR);
1012 error->ipehr[ring->id] = I915_READ(IPEHR);
1013 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1014 }
1015
9574b3fe 1016 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1017 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1018 error->seqno[ring->id] = ring->get_seqno(ring);
1019 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1020 error->head[ring->id] = I915_READ_HEAD(ring);
1021 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1022
1023 error->cpu_ring_head[ring->id] = ring->head;
1024 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1025}
1026
52d39a21
CW		 1027static void i915_gem_record_rings(struct drm_device *dev,
1028 struct drm_i915_error_state *error)
1029{
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 struct drm_i915_gem_request *request;
1032 int i, count;
1033
1034 for (i = 0; i < I915_NUM_RINGS; i++) {
1035 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1036
1037 if (ring->obj == NULL)
1038 continue;
1039
1040 i915_record_ring_state(dev, error, ring);
1041
1042 error->ring[i].batchbuffer =
1043 i915_error_first_batchbuffer(dev_priv, ring);
1044
1045 error->ring[i].ringbuffer =
1046 i915_error_object_create(dev_priv, ring->obj);
1047
1048 count = 0;
1049 list_for_each_entry(request, &ring->request_list, list)
1050 count++;
1051
1052 error->ring[i].num_requests = count;
1053 error->ring[i].requests =
1054 kmalloc(count*sizeof(struct drm_i915_error_request),
1055 GFP_ATOMIC);
1056 if (error->ring[i].requests == NULL) {
1057 error->ring[i].num_requests = 0;
1058 continue;
1059 }
1060
1061 count = 0;
1062 list_for_each_entry(request, &ring->request_list, list) {
1063 struct drm_i915_error_request *erq;
1064
1065 erq = &error->ring[i].requests[count++];
1066 erq->seqno = request->seqno;
1067 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1068 erq->tail = request->tail;
52d39a21
CW		 1069 }
1070 }
1071}
1072
8a905236
JB		 1073/**
1074 * i915_capture_error_state - capture an error record for later analysis
1075 * @dev: drm device
1076 *
1077 * Should be called when an error is detected (either a hang or an error
1078 * interrupt) to capture error state from the time of the error. Fills
1079 * out a structure which becomes available in debugfs for user level tools
1080 * to pick up.
1081 */
63eeaf38
JB		 1082static void i915_capture_error_state(struct drm_device *dev)
1083{
1084 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1085 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1086 struct drm_i915_error_state *error;
1087 unsigned long flags;
9db4a9c7 1088 int i, pipe;
63eeaf38
JB		 1089
1090 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1091 error = dev_priv->first_error;
1092 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1093 if (error)
1094 return;
63eeaf38 1095
9db4a9c7 1096 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1097 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1098 if (!error) {
9df30794
CW		 1099 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1100 return;
63eeaf38
JB		 1101 }
1102
b6f7833b
CW		 1103 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1104 dev->primary->index);
2fa772f3 1105
742cbee8 1106 kref_init(&error->ref);
63eeaf38
JB		 1107 error->eir = I915_READ(EIR);
1108 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1109
1110 if (HAS_PCH_SPLIT(dev))
1111 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1112 else if (IS_VALLEYVIEW(dev))
1113 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1114 else if (IS_GEN2(dev))
1115 error->ier = I915_READ16(IER);
1116 else
1117 error->ier = I915_READ(IER);
1118
9db4a9c7
JB		 1119 for_each_pipe(pipe)
1120 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1121
33f3f518 1122 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1123 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1124 error->done_reg = I915_READ(DONE_REG);
1125 }
d27b1e0e 1126
748ebc60 1127 i915_gem_record_fences(dev, error);
52d39a21 1128 i915_gem_record_rings(dev, error);
9df30794 1129
c724e8a9 1130 /* Record buffers on the active and pinned lists. */
9df30794 1131 error->active_bo = NULL;
c724e8a9 1132 error->pinned_bo = NULL;
9df30794 1133
bcfb2e28
CW		 1134 i = 0;
1135 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1136 i++;
1137 error->active_bo_count = i;
1b50247a
CW		 1138 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1139 if (obj->pin_count)
1140 i++;
bcfb2e28 1141 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1142
8e934dbf
CW		 1143 error->active_bo = NULL;
1144 error->pinned_bo = NULL;
bcfb2e28
CW		 1145 if (i) {
1146 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1147 GFP_ATOMIC);
c724e8a9
CW		 1148 if (error->active_bo)
1149 error->pinned_bo =
1150 error->active_bo + error->active_bo_count;
9df30794
CW		 1151 }
1152
c724e8a9
CW		 1153 if (error->active_bo)
1154 error->active_bo_count =
1b50247a
CW		 1155 capture_active_bo(error->active_bo,
1156 error->active_bo_count,
1157 &dev_priv->mm.active_list);
c724e8a9
CW		 1158
1159 if (error->pinned_bo)
1160 error->pinned_bo_count =
1b50247a
CW		 1161 capture_pinned_bo(error->pinned_bo,
1162 error->pinned_bo_count,
1163 &dev_priv->mm.gtt_list);
c724e8a9 1164
9df30794
CW		 1165 do_gettimeofday(&error->time);
1166
6ef3d427 1167 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1168 error->display = intel_display_capture_error_state(dev);
6ef3d427 1169
9df30794
CW		 1170 spin_lock_irqsave(&dev_priv->error_lock, flags);
1171 if (dev_priv->first_error == NULL) {
1172 dev_priv->first_error = error;
1173 error = NULL;
1174 }
63eeaf38 1175 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1176
1177 if (error)
742cbee8 1178 i915_error_state_free(&error->ref);
9df30794
CW		 1179}
1180
1181void i915_destroy_error_state(struct drm_device *dev)
1182{
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 struct drm_i915_error_state *error;
6dc0e816 1185 unsigned long flags;
9df30794 1186
6dc0e816 1187 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1188 error = dev_priv->first_error;
1189 dev_priv->first_error = NULL;
6dc0e816 1190 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1191
1192 if (error)
742cbee8 1193 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1194}
3bd3c932
CW		 1195#else
1196#define i915_capture_error_state(x)
1197#endif
63eeaf38 1198
35aed2e6 1199static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1200{
1201 struct drm_i915_private *dev_priv = dev->dev_private;
1202 u32 eir = I915_READ(EIR);
9db4a9c7 1203 int pipe;
8a905236 1204
35aed2e6
CW		 1205 if (!eir)
1206 return;
8a905236 1207
a70491cc 1208 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1209
1210 if (IS_G4X(dev)) {
1211 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1212 u32 ipeir = I915_READ(IPEIR_I965);
1213
a70491cc
JP		 1214 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1215 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1216 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1217 I915_READ(INSTDONE_I965));
a70491cc
JP		 1218 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1219 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1220 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1221 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1222 POSTING_READ(IPEIR_I965);
8a905236
JB		 1223 }
1224 if (eir & GM45_ERROR_PAGE_TABLE) {
1225 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1226 pr_err("page table error\n");
1227 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1228 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1229 POSTING_READ(PGTBL_ER);
8a905236
JB		 1230 }
1231 }
1232
a6c45cf0 1233 if (!IS_GEN2(dev)) {
8a905236
JB		 1234 if (eir & I915_ERROR_PAGE_TABLE) {
1235 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1236 pr_err("page table error\n");
1237 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1238 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1239 POSTING_READ(PGTBL_ER);
8a905236
JB		 1240 }
1241 }
1242
1243 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1244 pr_err("memory refresh error:\n");
9db4a9c7 1245 for_each_pipe(pipe)
a70491cc 1246 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1247 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1248 /* pipestat has already been acked */
1249 }
1250 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1251 pr_err("instruction error\n");
1252 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1253 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1254 u32 ipeir = I915_READ(IPEIR);
1255
a70491cc
JP		 1256 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1257 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1258 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1259 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1260 I915_WRITE(IPEIR, ipeir);
3143a2bf 1261 POSTING_READ(IPEIR);
8a905236
JB		 1262 } else {
1263 u32 ipeir = I915_READ(IPEIR_I965);
1264
a70491cc
JP		 1265 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1266 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1267 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1268 I915_READ(INSTDONE_I965));
a70491cc
JP		 1269 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1270 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1271 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1272 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1273 POSTING_READ(IPEIR_I965);
8a905236
JB		 1274 }
1275 }
1276
1277 I915_WRITE(EIR, eir);
3143a2bf 1278 POSTING_READ(EIR);
8a905236
JB		 1279 eir = I915_READ(EIR);
1280 if (eir) {
1281 /*
1282 * some errors might have become stuck,
1283 * mask them.
1284 */
1285 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1286 I915_WRITE(EMR, I915_READ(EMR) | eir);
1287 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1288 }
35aed2e6
CW		 1289}
1290
1291/**
1292 * i915_handle_error - handle an error interrupt
1293 * @dev: drm device
1294 *
1295 * Do some basic checking of regsiter state at error interrupt time and
1296 * dump it to the syslog. Also call i915_capture_error_state() to make
1297 * sure we get a record and make it available in debugfs. Fire a uevent
1298 * so userspace knows something bad happened (should trigger collection
1299 * of a ring dump etc.).
1300 */
527f9e90 1301void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1302{
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304
1305 i915_capture_error_state(dev);
1306 i915_report_and_clear_eir(dev);
8a905236 1307
ba1234d1 1308 if (wedged) {
30dbf0c0 1309 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1310 atomic_set(&dev_priv->mm.wedged, 1);
1311
11ed50ec
BG		 1312 /*
1313 * Wakeup waiting processes so they don't hang
1314 */
1ec14ad3 1315 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1316 if (HAS_BSD(dev))
1ec14ad3 1317 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1318 if (HAS_BLT(dev))
1ec14ad3 1319 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1320 }
1321
9c9fe1f8 1322 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1323}
1324
4e5359cd
SF		 1325static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1326{
1327 drm_i915_private_t *dev_priv = dev->dev_private;
1328 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1330 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1331 struct intel_unpin_work *work;
1332 unsigned long flags;
1333 bool stall_detected;
1334
1335 /* Ignore early vblank irqs */
1336 if (intel_crtc == NULL)
1337 return;
1338
1339 spin_lock_irqsave(&dev->event_lock, flags);
1340 work = intel_crtc->unpin_work;
1341
1342 if (work == NULL || work->pending || !work->enable_stall_check) {
1343 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1344 spin_unlock_irqrestore(&dev->event_lock, flags);
1345 return;
1346 }
1347
1348 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1349 obj = work->pending_flip_obj;
a6c45cf0 1350 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1351 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1352 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1353 obj->gtt_offset;
4e5359cd 1354 } else {
9db4a9c7 1355 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1356 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1357 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1358 crtc->x * crtc->fb->bits_per_pixel/8);
1359 }
1360
1361 spin_unlock_irqrestore(&dev->event_lock, flags);
1362
1363 if (stall_detected) {
1364 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1365 intel_prepare_page_flip(dev, intel_crtc->plane);
1366 }
1367}
1368
42f52ef8
KP		 1369/* Called from drm generic code, passed 'crtc' which
1370 * we use as a pipe index
1371 */
f71d4af4 1372static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1373{
1374 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1375 unsigned long irqflags;
71e0ffa5 1376
5eddb70b 1377 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1378 return -EINVAL;
0a3e67a4 1379
1ec14ad3 1380 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1381 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1382 i915_enable_pipestat(dev_priv, pipe,
1383 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1384 else
7c463586
KP		 1385 i915_enable_pipestat(dev_priv, pipe,
1386 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1387
1388 /* maintain vblank delivery even in deep C-states */
1389 if (dev_priv->info->gen == 3)
6b26c86d 1390 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1391 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1392
0a3e67a4
JB		 1393 return 0;
1394}
1395
f71d4af4 1396static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1397{
1398 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1399 unsigned long irqflags;
1400
1401 if (!i915_pipe_enabled(dev, pipe))
1402 return -EINVAL;
1403
1404 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1405 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1406 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1407 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1408
1409 return 0;
1410}
1411
f71d4af4 1412static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1413{
1414 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1415 unsigned long irqflags;
1416
1417 if (!i915_pipe_enabled(dev, pipe))
1418 return -EINVAL;
1419
1420 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1421 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1422 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1423 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1424
1425 return 0;
1426}
1427
7e231dbe
JB		 1428static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1429{
1430 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1431 unsigned long irqflags;
1432 u32 dpfl, imr;
1433
1434 if (!i915_pipe_enabled(dev, pipe))
1435 return -EINVAL;
1436
1437 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1438 dpfl = I915_READ(VLV_DPFLIPSTAT);
1439 imr = I915_READ(VLV_IMR);
1440 if (pipe == 0) {
1441 dpfl |= PIPEA_VBLANK_INT_EN;
1442 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1443 } else {
1444 dpfl |= PIPEA_VBLANK_INT_EN;
1445 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1446 }
1447 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1448 I915_WRITE(VLV_IMR, imr);
1449 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1450
1451 return 0;
1452}
1453
42f52ef8
KP		 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index
1456 */
f71d4af4 1457static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1460 unsigned long irqflags;
0a3e67a4 1461
1ec14ad3 1462 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1463 if (dev_priv->info->gen == 3)
6b26c86d 1464 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1465
f796cf8f
JB		 1466 i915_disable_pipestat(dev_priv, pipe,
1467 PIPE_VBLANK_INTERRUPT_ENABLE |
1468 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1469 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1470}
1471
f71d4af4 1472static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1473{
1474 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1475 unsigned long irqflags;
1476
1477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1478 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1479 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1480 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1481}
1482
f71d4af4 1483static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1484{
1485 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1486 unsigned long irqflags;
1487
1488 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1489 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1490 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1491 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1492}
1493
7e231dbe
JB		 1494static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1495{
1496 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1497 unsigned long irqflags;
1498 u32 dpfl, imr;
1499
1500 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1501 dpfl = I915_READ(VLV_DPFLIPSTAT);
1502 imr = I915_READ(VLV_IMR);
1503 if (pipe == 0) {
1504 dpfl &= ~PIPEA_VBLANK_INT_EN;
1505 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1506 } else {
1507 dpfl &= ~PIPEB_VBLANK_INT_EN;
1508 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1509 }
1510 I915_WRITE(VLV_IMR, imr);
1511 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1512 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1513}
1514
893eead0
CW		 1515static u32
1516ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1517{
893eead0
CW		 1518 return list_entry(ring->request_list.prev,
1519 struct drm_i915_gem_request, list)->seqno;
1520}
1521
1522static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1523{
9574b3fe
BW		 1524 /* We don't check whether the ring even exists before calling this
1525 * function. Hence check whether it's initialized. */
1526 if (ring->obj == NULL)
1527 return true;
1528
893eead0
CW		 1529 if (list_empty(&ring->request_list) ||
1530 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1531 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1532 if (waitqueue_active(&ring->irq_queue)) {
1533 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1534 ring->name);
893eead0
CW		 1535 wake_up_all(&ring->irq_queue);
1536 *err = true;
1537 }
1538 return true;
1539 }
1540 return false;
f65d9421
BG		 1541}
1542
1ec14ad3
CW		 1543static bool kick_ring(struct intel_ring_buffer *ring)
1544{
1545 struct drm_device *dev = ring->dev;
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 u32 tmp = I915_READ_CTL(ring);
1548 if (tmp & RING_WAIT) {
1549 DRM_ERROR("Kicking stuck wait on %s\n",
1550 ring->name);
1551 I915_WRITE_CTL(ring, tmp);
1552 return true;
1553 }
1ec14ad3
CW		 1554 return false;
1555}
1556
d1e61e7f
CW		 1557static bool i915_hangcheck_hung(struct drm_device *dev)
1558{
1559 drm_i915_private_t *dev_priv = dev->dev_private;
1560
1561 if (dev_priv->hangcheck_count++ > 1) {
1562 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1563 i915_handle_error(dev, true);
1564
1565 if (!IS_GEN2(dev)) {
1566 /* Is the chip hanging on a WAIT_FOR_EVENT?
1567 * If so we can simply poke the RB_WAIT bit
1568 * and break the hang. This should work on
1569 * all but the second generation chipsets.
1570 */
1571 if (kick_ring(&dev_priv->ring[RCS]))
1572 return false;
1573
1574 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1575 return false;
1576
1577 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1578 return false;
1579 }
1580
1581 return true;
1582 }
1583
1584 return false;
1585}
1586
f65d9421
BG		 1587/**
1588 * This is called when the chip hasn't reported back with completed
1589 * batchbuffers in a long time. The first time this is called we simply record
1590 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1591 * again, we assume the chip is wedged and try to fix it.
1592 */
1593void i915_hangcheck_elapsed(unsigned long data)
1594{
1595 struct drm_device *dev = (struct drm_device *)data;
1596 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1597 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1598 bool err = false;
1599
3e0dc6b0
BW		 1600 if (!i915_enable_hangcheck)
1601 return;
1602
893eead0 1603 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1604 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1605 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1606 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1607 if (err) {
1608 if (i915_hangcheck_hung(dev))
1609 return;
1610
893eead0 1611 goto repeat;
d1e61e7f
CW		 1612 }
1613
1614 dev_priv->hangcheck_count = 0;
893eead0
CW		 1615 return;
1616 }
b9201c14 1617
a6c45cf0 1618 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1619 instdone = I915_READ(INSTDONE);
1620 instdone1 = 0;
1621 } else {
cbb465e7
CW		 1622 instdone = I915_READ(INSTDONE_I965);
1623 instdone1 = I915_READ(INSTDONE1);
1624 }
097354eb
DV		 1625 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1626 acthd_bsd = HAS_BSD(dev) ?
1627 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1628 acthd_blt = HAS_BLT(dev) ?
1629 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1630
cbb465e7 1631 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1632 dev_priv->last_acthd_bsd == acthd_bsd &&
1633 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1634 dev_priv->last_instdone == instdone &&
1635 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1636 if (i915_hangcheck_hung(dev))
cbb465e7 1637 return;
cbb465e7
CW		 1638 } else {
1639 dev_priv->hangcheck_count = 0;
1640
1641 dev_priv->last_acthd = acthd;
097354eb
DV		 1642 dev_priv->last_acthd_bsd = acthd_bsd;
1643 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1644 dev_priv->last_instdone = instdone;
1645 dev_priv->last_instdone1 = instdone1;
1646 }
f65d9421 1647
893eead0 1648repeat:
f65d9421 1649 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1650 mod_timer(&dev_priv->hangcheck_timer,
1651 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1652}
1653
1da177e4
LT		 1654/* drm_dma.h hooks
1655*/
f71d4af4 1656static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1657{
1658 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1659
4697995b
JB		 1660 atomic_set(&dev_priv->irq_received, 0);
1661
4697995b 1662
036a4a7d 1663 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1664
036a4a7d
ZW		 1665 /* XXX hotplug from PCH */
1666
1667 I915_WRITE(DEIMR, 0xffffffff);
1668 I915_WRITE(DEIER, 0x0);
3143a2bf 1669 POSTING_READ(DEIER);
036a4a7d
ZW		 1670
1671 /* and GT */
1672 I915_WRITE(GTIMR, 0xffffffff);
1673 I915_WRITE(GTIER, 0x0);
3143a2bf 1674 POSTING_READ(GTIER);
c650156a
ZW		 1675
1676 /* south display irq */
1677 I915_WRITE(SDEIMR, 0xffffffff);
1678 I915_WRITE(SDEIER, 0x0);
3143a2bf 1679 POSTING_READ(SDEIER);
036a4a7d
ZW		 1680}
1681
7e231dbe
JB		 1682static void valleyview_irq_preinstall(struct drm_device *dev)
1683{
1684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1685 int pipe;
1686
1687 atomic_set(&dev_priv->irq_received, 0);
1688
7e231dbe
JB		 1689 /* VLV magic */
1690 I915_WRITE(VLV_IMR, 0);
1691 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1692 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1693 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1694
7e231dbe
JB		 1695 /* and GT */
1696 I915_WRITE(GTIIR, I915_READ(GTIIR));
1697 I915_WRITE(GTIIR, I915_READ(GTIIR));
1698 I915_WRITE(GTIMR, 0xffffffff);
1699 I915_WRITE(GTIER, 0x0);
1700 POSTING_READ(GTIER);
1701
1702 I915_WRITE(DPINVGTT, 0xff);
1703
1704 I915_WRITE(PORT_HOTPLUG_EN, 0);
1705 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1706 for_each_pipe(pipe)
1707 I915_WRITE(PIPESTAT(pipe), 0xffff);
1708 I915_WRITE(VLV_IIR, 0xffffffff);
1709 I915_WRITE(VLV_IMR, 0xffffffff);
1710 I915_WRITE(VLV_IER, 0x0);
1711 POSTING_READ(VLV_IER);
1712}
1713
7fe0b973
KP		 1714/*
1715 * Enable digital hotplug on the PCH, and configure the DP short pulse
1716 * duration to 2ms (which is the minimum in the Display Port spec)
1717 *
1718 * This register is the same on all known PCH chips.
1719 */
1720
1721static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1722{
1723 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1724 u32 hotplug;
1725
1726 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1727 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1728 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1729 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1730 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1731 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1732}
1733
f71d4af4 1734static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1735{
1736 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1737 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1738 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1739 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1740 u32 render_irqs;
2d7b8366 1741 u32 hotplug_mask;
036a4a7d 1742
1ec14ad3 1743 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1744
1745 /* should always can generate irq */
1746 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1747 I915_WRITE(DEIMR, dev_priv->irq_mask);
1748 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1749 POSTING_READ(DEIER);
036a4a7d 1750
1ec14ad3 1751 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1752
1753 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1754 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1755
1ec14ad3
CW		 1756 if (IS_GEN6(dev))
1757 render_irqs =
1758 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1759 GEN6_BSD_USER_INTERRUPT |
1760 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1761 else
1762 render_irqs =
88f23b8f 1763 GT_USER_INTERRUPT |
c6df541c 1764 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1765 GT_BSD_USER_INTERRUPT;
1766 I915_WRITE(GTIER, render_irqs);
3143a2bf 1767 POSTING_READ(GTIER);
036a4a7d 1768
2d7b8366 1769 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1770 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1771 SDE_PORTB_HOTPLUG_CPT |
1772 SDE_PORTC_HOTPLUG_CPT |
1773 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1774 } else {
9035a97a
CW		 1775 hotplug_mask = (SDE_CRT_HOTPLUG |
1776 SDE_PORTB_HOTPLUG |
1777 SDE_PORTC_HOTPLUG |
1778 SDE_PORTD_HOTPLUG |
1779 SDE_AUX_MASK);
2d7b8366
YL		 1780 }
1781
1ec14ad3 1782 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1783
1784 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1785 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1786 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1787 POSTING_READ(SDEIER);
c650156a 1788
7fe0b973
KP		 1789 ironlake_enable_pch_hotplug(dev);
1790
f97108d1
JB		 1791 if (IS_IRONLAKE_M(dev)) {
1792 /* Clear & enable PCU event interrupts */
1793 I915_WRITE(DEIIR, DE_PCU_EVENT);
1794 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1795 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1796 }
1797
036a4a7d
ZW		 1798 return 0;
1799}
1800
f71d4af4 1801static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1802{
1803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1804 /* enable kind of interrupts always enabled */
1805 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1806 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1807 DE_PLANEB_FLIP_DONE_IVB;
1808 u32 render_irqs;
1809 u32 hotplug_mask;
1810
b1f14ad0
JB		 1811 dev_priv->irq_mask = ~display_mask;
1812
1813 /* should always can generate irq */
1814 I915_WRITE(DEIIR, I915_READ(DEIIR));
1815 I915_WRITE(DEIMR, dev_priv->irq_mask);
1816 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1817 DE_PIPEB_VBLANK_IVB);
1818 POSTING_READ(DEIER);
1819
1820 dev_priv->gt_irq_mask = ~0;
1821
1822 I915_WRITE(GTIIR, I915_READ(GTIIR));
1823 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1824
e2a1e2f0
BW		 1825 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1826 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1827 I915_WRITE(GTIER, render_irqs);
1828 POSTING_READ(GTIER);
1829
1830 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1831 SDE_PORTB_HOTPLUG_CPT |
1832 SDE_PORTC_HOTPLUG_CPT |
1833 SDE_PORTD_HOTPLUG_CPT);
1834 dev_priv->pch_irq_mask = ~hotplug_mask;
1835
1836 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1837 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1838 I915_WRITE(SDEIER, hotplug_mask);
1839 POSTING_READ(SDEIER);
1840
7fe0b973
KP		 1841 ironlake_enable_pch_hotplug(dev);
1842
b1f14ad0
JB		 1843 return 0;
1844}
1845
7e231dbe
JB		 1846static int valleyview_irq_postinstall(struct drm_device *dev)
1847{
1848 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1849 u32 render_irqs;
1850 u32 enable_mask;
1851 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1852 u16 msid;
1853
1854 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1855 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1856 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1857
1858 dev_priv->irq_mask = ~enable_mask;
1859
7e231dbe
JB		 1860 dev_priv->pipestat[0] = 0;
1861 dev_priv->pipestat[1] = 0;
1862
7e231dbe
JB		 1863 /* Hack for broken MSIs on VLV */
1864 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1865 pci_read_config_word(dev->pdev, 0x98, &msid);
1866 msid &= 0xff; /* mask out delivery bits */
1867 msid |= (1<<14);
1868 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1869
1870 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1871 I915_WRITE(VLV_IER, enable_mask);
1872 I915_WRITE(VLV_IIR, 0xffffffff);
1873 I915_WRITE(PIPESTAT(0), 0xffff);
1874 I915_WRITE(PIPESTAT(1), 0xffff);
1875 POSTING_READ(VLV_IER);
1876
1877 I915_WRITE(VLV_IIR, 0xffffffff);
1878 I915_WRITE(VLV_IIR, 0xffffffff);
1879
1880 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1881 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1882 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1883 GT_GEN6_BSD_USER_INTERRUPT |
1884 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1885 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1886 GT_PIPE_NOTIFY |
1887 GT_RENDER_CS_ERROR_INTERRUPT |
1888 GT_SYNC_STATUS |
1889 GT_USER_INTERRUPT;
1890
1891 dev_priv->gt_irq_mask = ~render_irqs;
1892
1893 I915_WRITE(GTIIR, I915_READ(GTIIR));
1894 I915_WRITE(GTIIR, I915_READ(GTIIR));
1895 I915_WRITE(GTIMR, 0);
1896 I915_WRITE(GTIER, render_irqs);
1897 POSTING_READ(GTIER);
1898
1899 /* ack & enable invalid PTE error interrupts */
1900#if 0 /* FIXME: add support to irq handler for checking these bits */
1901 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1902 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1903#endif
1904
1905 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1906#if 0 /* FIXME: check register definitions; some have moved */
1907 /* Note HDMI and DP share bits */
1908 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1909 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1910 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1911 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1912 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1913 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1914 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1915 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1916 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1917 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1918 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1919 hotplug_en |= CRT_HOTPLUG_INT_EN;
1920 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1921 }
1922#endif
1923
1924 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1925
1926 return 0;
1927}
1928
7e231dbe
JB		 1929static void valleyview_irq_uninstall(struct drm_device *dev)
1930{
1931 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1932 int pipe;
1933
1934 if (!dev_priv)
1935 return;
1936
7e231dbe
JB		 1937 for_each_pipe(pipe)
1938 I915_WRITE(PIPESTAT(pipe), 0xffff);
1939
1940 I915_WRITE(HWSTAM, 0xffffffff);
1941 I915_WRITE(PORT_HOTPLUG_EN, 0);
1942 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1943 for_each_pipe(pipe)
1944 I915_WRITE(PIPESTAT(pipe), 0xffff);
1945 I915_WRITE(VLV_IIR, 0xffffffff);
1946 I915_WRITE(VLV_IMR, 0xffffffff);
1947 I915_WRITE(VLV_IER, 0x0);
1948 POSTING_READ(VLV_IER);
1949}
1950
f71d4af4 1951static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1952{
1953 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1954
1955 if (!dev_priv)
1956 return;
1957
036a4a7d
ZW		 1958 I915_WRITE(HWSTAM, 0xffffffff);
1959
1960 I915_WRITE(DEIMR, 0xffffffff);
1961 I915_WRITE(DEIER, 0x0);
1962 I915_WRITE(DEIIR, I915_READ(DEIIR));
1963
1964 I915_WRITE(GTIMR, 0xffffffff);
1965 I915_WRITE(GTIER, 0x0);
1966 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1967
1968 I915_WRITE(SDEIMR, 0xffffffff);
1969 I915_WRITE(SDEIER, 0x0);
1970 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1971}
1972
a266c7d5 1973static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1974{
1975 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1976 int pipe;
91e3738e 1977
a266c7d5 1978 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1979
9db4a9c7
JB		 1980 for_each_pipe(pipe)
1981 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1982 I915_WRITE16(IMR, 0xffff);
1983 I915_WRITE16(IER, 0x0);
1984 POSTING_READ16(IER);
c2798b19
CW		 1985}
1986
1987static int i8xx_irq_postinstall(struct drm_device *dev)
1988{
1989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1990
c2798b19
CW		 1991 dev_priv->pipestat[0] = 0;
1992 dev_priv->pipestat[1] = 0;
1993
1994 I915_WRITE16(EMR,
1995 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1996
1997 /* Unmask the interrupts that we always want on. */
1998 dev_priv->irq_mask =
1999 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2000 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2001 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2002 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2003 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2004 I915_WRITE16(IMR, dev_priv->irq_mask);
2005
2006 I915_WRITE16(IER,
2007 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2008 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2009 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2010 I915_USER_INTERRUPT);
2011 POSTING_READ16(IER);
2012
2013 return 0;
2014}
2015
2016static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2017{
2018 struct drm_device *dev = (struct drm_device *) arg;
2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2020 u16 iir, new_iir;
2021 u32 pipe_stats[2];
2022 unsigned long irqflags;
2023 int irq_received;
2024 int pipe;
2025 u16 flip_mask =
2026 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2027 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2028
2029 atomic_inc(&dev_priv->irq_received);
2030
2031 iir = I915_READ16(IIR);
2032 if (iir == 0)
2033 return IRQ_NONE;
2034
2035 while (iir & ~flip_mask) {
2036 /* Can't rely on pipestat interrupt bit in iir as it might
2037 * have been cleared after the pipestat interrupt was received.
2038 * It doesn't set the bit in iir again, but it still produces
2039 * interrupts (for non-MSI).
2040 */
2041 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2042 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2043 i915_handle_error(dev, false);
2044
2045 for_each_pipe(pipe) {
2046 int reg = PIPESTAT(pipe);
2047 pipe_stats[pipe] = I915_READ(reg);
2048
2049 /*
2050 * Clear the PIPE*STAT regs before the IIR
2051 */
2052 if (pipe_stats[pipe] & 0x8000ffff) {
2053 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2054 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2055 pipe_name(pipe));
2056 I915_WRITE(reg, pipe_stats[pipe]);
2057 irq_received = 1;
2058 }
2059 }
2060 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2061
2062 I915_WRITE16(IIR, iir & ~flip_mask);
2063 new_iir = I915_READ16(IIR); /* Flush posted writes */
2064
d05c617e 2065 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2066
2067 if (iir & I915_USER_INTERRUPT)
2068 notify_ring(dev, &dev_priv->ring[RCS]);
2069
2070 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2071 drm_handle_vblank(dev, 0)) {
2072 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2073 intel_prepare_page_flip(dev, 0);
2074 intel_finish_page_flip(dev, 0);
2075 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2076 }
2077 }
2078
2079 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2080 drm_handle_vblank(dev, 1)) {
2081 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2082 intel_prepare_page_flip(dev, 1);
2083 intel_finish_page_flip(dev, 1);
2084 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2085 }
2086 }
2087
2088 iir = new_iir;
2089 }
2090
2091 return IRQ_HANDLED;
2092}
2093
2094static void i8xx_irq_uninstall(struct drm_device * dev)
2095{
2096 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2097 int pipe;
2098
c2798b19
CW		 2099 for_each_pipe(pipe) {
2100 /* Clear enable bits; then clear status bits */
2101 I915_WRITE(PIPESTAT(pipe), 0);
2102 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2103 }
2104 I915_WRITE16(IMR, 0xffff);
2105 I915_WRITE16(IER, 0x0);
2106 I915_WRITE16(IIR, I915_READ16(IIR));
2107}
2108
a266c7d5
CW		 2109static void i915_irq_preinstall(struct drm_device * dev)
2110{
2111 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2112 int pipe;
2113
2114 atomic_set(&dev_priv->irq_received, 0);
2115
2116 if (I915_HAS_HOTPLUG(dev)) {
2117 I915_WRITE(PORT_HOTPLUG_EN, 0);
2118 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2119 }
2120
00d98ebd 2121 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2122 for_each_pipe(pipe)
2123 I915_WRITE(PIPESTAT(pipe), 0);
2124 I915_WRITE(IMR, 0xffffffff);
2125 I915_WRITE(IER, 0x0);
2126 POSTING_READ(IER);
2127}
2128
2129static int i915_irq_postinstall(struct drm_device *dev)
2130{
2131 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2132 u32 enable_mask;
a266c7d5 2133
a266c7d5
CW		 2134 dev_priv->pipestat[0] = 0;
2135 dev_priv->pipestat[1] = 0;
2136
38bde180
CW		 2137 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2138
2139 /* Unmask the interrupts that we always want on. */
2140 dev_priv->irq_mask =
2141 ~(I915_ASLE_INTERRUPT |
2142 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2143 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2144 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2145 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2146 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2147
2148 enable_mask =
2149 I915_ASLE_INTERRUPT |
2150 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2151 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2152 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2153 I915_USER_INTERRUPT;
2154
a266c7d5
CW		 2155 if (I915_HAS_HOTPLUG(dev)) {
2156 /* Enable in IER... */
2157 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2158 /* and unmask in IMR */
2159 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2160 }
2161
a266c7d5
CW		 2162 I915_WRITE(IMR, dev_priv->irq_mask);
2163 I915_WRITE(IER, enable_mask);
2164 POSTING_READ(IER);
2165
2166 if (I915_HAS_HOTPLUG(dev)) {
2167 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2168
a266c7d5
CW		 2169 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2170 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2171 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2172 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2173 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2174 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2175 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2176 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2177 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2178 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2179 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2180 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2181 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2182 }
2183
2184 /* Ignore TV since it's buggy */
2185
2186 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2187 }
2188
2189 intel_opregion_enable_asle(dev);
2190
2191 return 0;
2192}
2193
2194static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2195{
2196 struct drm_device *dev = (struct drm_device *) arg;
2197 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2198 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2199 unsigned long irqflags;
38bde180
CW		 2200 u32 flip_mask =
2201 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2202 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2203 u32 flip[2] = {
2204 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2205 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2206 };
2207 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2208
2209 atomic_inc(&dev_priv->irq_received);
2210
2211 iir = I915_READ(IIR);
38bde180
CW		 2212 do {
2213 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2214 bool blc_event = false;
a266c7d5
CW		 2215
2216 /* Can't rely on pipestat interrupt bit in iir as it might
2217 * have been cleared after the pipestat interrupt was received.
2218 * It doesn't set the bit in iir again, but it still produces
2219 * interrupts (for non-MSI).
2220 */
2221 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2222 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2223 i915_handle_error(dev, false);
2224
2225 for_each_pipe(pipe) {
2226 int reg = PIPESTAT(pipe);
2227 pipe_stats[pipe] = I915_READ(reg);
2228
38bde180 2229 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2230 if (pipe_stats[pipe] & 0x8000ffff) {
2231 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2232 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2233 pipe_name(pipe));
2234 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2235 irq_received = true;
a266c7d5
CW		 2236 }
2237 }
2238 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2239
2240 if (!irq_received)
2241 break;
2242
a266c7d5
CW		 2243 /* Consume port. Then clear IIR or we'll miss events */
2244 if ((I915_HAS_HOTPLUG(dev)) &&
2245 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2246 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2247
2248 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2249 hotplug_status);
2250 if (hotplug_status & dev_priv->hotplug_supported_mask)
2251 queue_work(dev_priv->wq,
2252 &dev_priv->hotplug_work);
2253
2254 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2255 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2256 }
2257
38bde180 2258 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2259 new_iir = I915_READ(IIR); /* Flush posted writes */
2260
a266c7d5
CW		 2261 if (iir & I915_USER_INTERRUPT)
2262 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2263
a266c7d5 2264 for_each_pipe(pipe) {
38bde180
CW		 2265 int plane = pipe;
2266 if (IS_MOBILE(dev))
2267 plane = !plane;
8291ee90 2268 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2269 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2270 if (iir & flip[plane]) {
2271 intel_prepare_page_flip(dev, plane);
2272 intel_finish_page_flip(dev, pipe);
2273 flip_mask &= ~flip[plane];
2274 }
a266c7d5
CW		 2275 }
2276
2277 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2278 blc_event = true;
2279 }
2280
a266c7d5
CW		 2281 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2282 intel_opregion_asle_intr(dev);
2283
2284 /* With MSI, interrupts are only generated when iir
2285 * transitions from zero to nonzero. If another bit got
2286 * set while we were handling the existing iir bits, then
2287 * we would never get another interrupt.
2288 *
2289 * This is fine on non-MSI as well, as if we hit this path
2290 * we avoid exiting the interrupt handler only to generate
2291 * another one.
2292 *
2293 * Note that for MSI this could cause a stray interrupt report
2294 * if an interrupt landed in the time between writing IIR and
2295 * the posting read. This should be rare enough to never
2296 * trigger the 99% of 100,000 interrupts test for disabling
2297 * stray interrupts.
2298 */
38bde180 2299 ret = IRQ_HANDLED;
a266c7d5 2300 iir = new_iir;
38bde180 2301 } while (iir & ~flip_mask);
a266c7d5 2302
d05c617e 2303 i915_update_dri1_breadcrumb(dev);
8291ee90 2304
a266c7d5
CW		 2305 return ret;
2306}
2307
2308static void i915_irq_uninstall(struct drm_device * dev)
2309{
2310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2311 int pipe;
2312
a266c7d5
CW		 2313 if (I915_HAS_HOTPLUG(dev)) {
2314 I915_WRITE(PORT_HOTPLUG_EN, 0);
2315 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2316 }
2317
00d98ebd 2318 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2319 for_each_pipe(pipe) {
2320 /* Clear enable bits; then clear status bits */
a266c7d5 2321 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2322 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2323 }
a266c7d5
CW		 2324 I915_WRITE(IMR, 0xffffffff);
2325 I915_WRITE(IER, 0x0);
2326
a266c7d5
CW		 2327 I915_WRITE(IIR, I915_READ(IIR));
2328}
2329
2330static void i965_irq_preinstall(struct drm_device * dev)
2331{
2332 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2333 int pipe;
2334
2335 atomic_set(&dev_priv->irq_received, 0);
2336
2337 if (I915_HAS_HOTPLUG(dev)) {
2338 I915_WRITE(PORT_HOTPLUG_EN, 0);
2339 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2340 }
2341
2342 I915_WRITE(HWSTAM, 0xeffe);
2343 for_each_pipe(pipe)
2344 I915_WRITE(PIPESTAT(pipe), 0);
2345 I915_WRITE(IMR, 0xffffffff);
2346 I915_WRITE(IER, 0x0);
2347 POSTING_READ(IER);
2348}
2349
2350static int i965_irq_postinstall(struct drm_device *dev)
2351{
2352 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2353 u32 enable_mask;
a266c7d5
CW		 2354 u32 error_mask;
2355
a266c7d5 2356 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2357 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2358 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2359 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2360 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2361 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2362 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2363
2364 enable_mask = ~dev_priv->irq_mask;
2365 enable_mask |= I915_USER_INTERRUPT;
2366
2367 if (IS_G4X(dev))
2368 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2369
2370 dev_priv->pipestat[0] = 0;
2371 dev_priv->pipestat[1] = 0;
2372
2373 if (I915_HAS_HOTPLUG(dev)) {
2374 /* Enable in IER... */
2375 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2376 /* and unmask in IMR */
2377 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2378 }
2379
2380 /*
2381 * Enable some error detection, note the instruction error mask
2382 * bit is reserved, so we leave it masked.
2383 */
2384 if (IS_G4X(dev)) {
2385 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2386 GM45_ERROR_MEM_PRIV |
2387 GM45_ERROR_CP_PRIV |
2388 I915_ERROR_MEMORY_REFRESH);
2389 } else {
2390 error_mask = ~(I915_ERROR_PAGE_TABLE |
2391 I915_ERROR_MEMORY_REFRESH);
2392 }
2393 I915_WRITE(EMR, error_mask);
2394
2395 I915_WRITE(IMR, dev_priv->irq_mask);
2396 I915_WRITE(IER, enable_mask);
2397 POSTING_READ(IER);
2398
2399 if (I915_HAS_HOTPLUG(dev)) {
2400 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2401
2402 /* Note HDMI and DP share bits */
2403 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2404 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2405 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2406 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2407 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2408 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2409 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2410 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2411 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2412 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2413 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2414 hotplug_en |= CRT_HOTPLUG_INT_EN;
2415
2416 /* Programming the CRT detection parameters tends
2417 to generate a spurious hotplug event about three
2418 seconds later. So just do it once.
2419 */
2420 if (IS_G4X(dev))
2421 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2422 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2423 }
2424
2425 /* Ignore TV since it's buggy */
2426
2427 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2428 }
2429
2430 intel_opregion_enable_asle(dev);
2431
2432 return 0;
2433}
2434
2435static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2436{
2437 struct drm_device *dev = (struct drm_device *) arg;
2438 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2439 u32 iir, new_iir;
2440 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2441 unsigned long irqflags;
2442 int irq_received;
2443 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2444
2445 atomic_inc(&dev_priv->irq_received);
2446
2447 iir = I915_READ(IIR);
2448
a266c7d5 2449 for (;;) {
2c8ba29f
CW		 2450 bool blc_event = false;
2451
a266c7d5
CW		 2452 irq_received = iir != 0;
2453
2454 /* Can't rely on pipestat interrupt bit in iir as it might
2455 * have been cleared after the pipestat interrupt was received.
2456 * It doesn't set the bit in iir again, but it still produces
2457 * interrupts (for non-MSI).
2458 */
2459 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2460 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2461 i915_handle_error(dev, false);
2462
2463 for_each_pipe(pipe) {
2464 int reg = PIPESTAT(pipe);
2465 pipe_stats[pipe] = I915_READ(reg);
2466
2467 /*
2468 * Clear the PIPE*STAT regs before the IIR
2469 */
2470 if (pipe_stats[pipe] & 0x8000ffff) {
2471 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2472 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2473 pipe_name(pipe));
2474 I915_WRITE(reg, pipe_stats[pipe]);
2475 irq_received = 1;
2476 }
2477 }
2478 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2479
2480 if (!irq_received)
2481 break;
2482
2483 ret = IRQ_HANDLED;
2484
2485 /* Consume port. Then clear IIR or we'll miss events */
2486 if ((I915_HAS_HOTPLUG(dev)) &&
2487 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2488 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2489
2490 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2491 hotplug_status);
2492 if (hotplug_status & dev_priv->hotplug_supported_mask)
2493 queue_work(dev_priv->wq,
2494 &dev_priv->hotplug_work);
2495
2496 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2497 I915_READ(PORT_HOTPLUG_STAT);
2498 }
2499
2500 I915_WRITE(IIR, iir);
2501 new_iir = I915_READ(IIR); /* Flush posted writes */
2502
a266c7d5
CW		 2503 if (iir & I915_USER_INTERRUPT)
2504 notify_ring(dev, &dev_priv->ring[RCS]);
2505 if (iir & I915_BSD_USER_INTERRUPT)
2506 notify_ring(dev, &dev_priv->ring[VCS]);
2507
4f7d1e79 2508 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2509 intel_prepare_page_flip(dev, 0);
a266c7d5 2510
4f7d1e79 2511 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2512 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2513
2514 for_each_pipe(pipe) {
2c8ba29f 2515 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2516 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2517 i915_pageflip_stall_check(dev, pipe);
2518 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2519 }
2520
2521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2522 blc_event = true;
2523 }
2524
2525
2526 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2527 intel_opregion_asle_intr(dev);
2528
2529 /* With MSI, interrupts are only generated when iir
2530 * transitions from zero to nonzero. If another bit got
2531 * set while we were handling the existing iir bits, then
2532 * we would never get another interrupt.
2533 *
2534 * This is fine on non-MSI as well, as if we hit this path
2535 * we avoid exiting the interrupt handler only to generate
2536 * another one.
2537 *
2538 * Note that for MSI this could cause a stray interrupt report
2539 * if an interrupt landed in the time between writing IIR and
2540 * the posting read. This should be rare enough to never
2541 * trigger the 99% of 100,000 interrupts test for disabling
2542 * stray interrupts.
2543 */
2544 iir = new_iir;
2545 }
2546
d05c617e 2547 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2548
a266c7d5
CW		 2549 return ret;
2550}
2551
2552static void i965_irq_uninstall(struct drm_device * dev)
2553{
2554 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2555 int pipe;
2556
2557 if (!dev_priv)
2558 return;
2559
a266c7d5
CW		 2560 if (I915_HAS_HOTPLUG(dev)) {
2561 I915_WRITE(PORT_HOTPLUG_EN, 0);
2562 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2563 }
2564
2565 I915_WRITE(HWSTAM, 0xffffffff);
2566 for_each_pipe(pipe)
2567 I915_WRITE(PIPESTAT(pipe), 0);
2568 I915_WRITE(IMR, 0xffffffff);
2569 I915_WRITE(IER, 0x0);
2570
2571 for_each_pipe(pipe)
2572 I915_WRITE(PIPESTAT(pipe),
2573 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2574 I915_WRITE(IIR, I915_READ(IIR));
2575}
2576
f71d4af4
JB		 2577void intel_irq_init(struct drm_device *dev)
2578{
8b2e326d
CW		 2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580
2581 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2582 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2583 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2584
f71d4af4
JB		 2585 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2586 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2587 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2588 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2589 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2590 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2591 }
2592
c3613de9
KP		 2593 if (drm_core_check_feature(dev, DRIVER_MODESET))
2594 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2595 else
2596 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2597 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2598
7e231dbe
JB		 2599 if (IS_VALLEYVIEW(dev)) {
2600 dev->driver->irq_handler = valleyview_irq_handler;
2601 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2602 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2603 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2604 dev->driver->enable_vblank = valleyview_enable_vblank;
2605 dev->driver->disable_vblank = valleyview_disable_vblank;
2606 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2607 /* Share pre & uninstall handlers with ILK/SNB */
2608 dev->driver->irq_handler = ivybridge_irq_handler;
2609 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2610 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2611 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2612 dev->driver->enable_vblank = ivybridge_enable_vblank;
2613 dev->driver->disable_vblank = ivybridge_disable_vblank;
2614 } else if (HAS_PCH_SPLIT(dev)) {
2615 dev->driver->irq_handler = ironlake_irq_handler;
2616 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2617 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2618 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2619 dev->driver->enable_vblank = ironlake_enable_vblank;
2620 dev->driver->disable_vblank = ironlake_disable_vblank;
2621 } else {
c2798b19
CW		 2622 if (INTEL_INFO(dev)->gen == 2) {
2623 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2624 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2625 dev->driver->irq_handler = i8xx_irq_handler;
2626 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2627 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2628 /* IIR "flip pending" means done if this bit is set */
2629 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2630
a266c7d5
CW		 2631 dev->driver->irq_preinstall = i915_irq_preinstall;
2632 dev->driver->irq_postinstall = i915_irq_postinstall;
2633 dev->driver->irq_uninstall = i915_irq_uninstall;
2634 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2635 } else {
a266c7d5
CW		 2636 dev->driver->irq_preinstall = i965_irq_preinstall;
2637 dev->driver->irq_postinstall = i965_irq_postinstall;
2638 dev->driver->irq_uninstall = i965_irq_uninstall;
2639 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2640 }
f71d4af4
JB		 2641 dev->driver->enable_vblank = i915_enable_vblank;
2642 dev->driver->disable_vblank = i915_disable_vblank;
2643 }
2644}
Linux kernel - Deliverables
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