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drm/i915: add dev_priv->pm_irq_mask
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
43eaea13
PZ		 107/**
108 * ilk_update_gt_irq - update GTIMR
109 * @dev_priv: driver private
110 * @interrupt_mask: mask of interrupt bits to update
111 * @enabled_irq_mask: mask of interrupt bits to enable
112 */
113static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
114 uint32_t interrupt_mask,
115 uint32_t enabled_irq_mask)
116{
117 assert_spin_locked(&dev_priv->irq_lock);
118
119 dev_priv->gt_irq_mask &= ~interrupt_mask;
120 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
121 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
122 POSTING_READ(GTIMR);
123}
124
125void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
126{
127 ilk_update_gt_irq(dev_priv, mask, mask);
128}
129
130void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
131{
132 ilk_update_gt_irq(dev_priv, mask, 0);
133}
134
edbfdb45
PZ		 135/**
136 * snb_update_pm_irq - update GEN6_PMIMR
137 * @dev_priv: driver private
138 * @interrupt_mask: mask of interrupt bits to update
139 * @enabled_irq_mask: mask of interrupt bits to enable
140 */
141static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
142 uint32_t interrupt_mask,
143 uint32_t enabled_irq_mask)
144{
605cd25b 145 uint32_t new_val;
edbfdb45
PZ		 146
147 assert_spin_locked(&dev_priv->irq_lock);
148
605cd25b 149 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 150 new_val &= ~interrupt_mask;
151 new_val |= (~enabled_irq_mask & interrupt_mask);
152
605cd25b
PZ		 153 if (new_val != dev_priv->pm_irq_mask) {
154 dev_priv->pm_irq_mask = new_val;
155 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 156 POSTING_READ(GEN6_PMIMR);
157 }
edbfdb45
PZ		 158}
159
160void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
161{
162 snb_update_pm_irq(dev_priv, mask, mask);
163}
164
165void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
166{
167 snb_update_pm_irq(dev_priv, mask, 0);
168}
169
170static void snb_set_pm_irq(struct drm_i915_private *dev_priv, uint32_t val)
171{
172 snb_update_pm_irq(dev_priv, 0xffffffff, ~val);
173}
174
8664281b
PZ		 175static bool ivb_can_enable_err_int(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct intel_crtc *crtc;
179 enum pipe pipe;
180
4bc9d430
DV		 181 assert_spin_locked(&dev_priv->irq_lock);
182
8664281b
PZ		 183 for_each_pipe(pipe) {
184 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
185
186 if (crtc->cpu_fifo_underrun_disabled)
187 return false;
188 }
189
190 return true;
191}
192
193static bool cpt_can_enable_serr_int(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 enum pipe pipe;
197 struct intel_crtc *crtc;
198
fee884ed
DV		 199 assert_spin_locked(&dev_priv->irq_lock);
200
8664281b
PZ		 201 for_each_pipe(pipe) {
202 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
203
204 if (crtc->pch_fifo_underrun_disabled)
205 return false;
206 }
207
208 return true;
209}
210
211static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
212 enum pipe pipe, bool enable)
213{
214 struct drm_i915_private *dev_priv = dev->dev_private;
215 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
216 DE_PIPEB_FIFO_UNDERRUN;
217
218 if (enable)
219 ironlake_enable_display_irq(dev_priv, bit);
220 else
221 ironlake_disable_display_irq(dev_priv, bit);
222}
223
224static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 225 enum pipe pipe, bool enable)
8664281b
PZ		 226{
227 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 228 if (enable) {
7336df65
DV		 229 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
230
8664281b
PZ		 231 if (!ivb_can_enable_err_int(dev))
232 return;
233
8664281b
PZ		 234 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
235 } else {
7336df65
DV		 236 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
237
238 /* Change the state _after_ we've read out the current one. */
8664281b 239 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 240
241 if (!was_enabled &&
242 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
243 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
244 pipe_name(pipe));
245 }
8664281b
PZ		 246 }
247}
248
fee884ed
DV		 249/**
250 * ibx_display_interrupt_update - update SDEIMR
251 * @dev_priv: driver private
252 * @interrupt_mask: mask of interrupt bits to update
253 * @enabled_irq_mask: mask of interrupt bits to enable
254 */
255static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
256 uint32_t interrupt_mask,
257 uint32_t enabled_irq_mask)
258{
259 uint32_t sdeimr = I915_READ(SDEIMR);
260 sdeimr &= ~interrupt_mask;
261 sdeimr |= (~enabled_irq_mask & interrupt_mask);
262
263 assert_spin_locked(&dev_priv->irq_lock);
264
265 I915_WRITE(SDEIMR, sdeimr);
266 POSTING_READ(SDEIMR);
267}
268#define ibx_enable_display_interrupt(dev_priv, bits) \
269 ibx_display_interrupt_update((dev_priv), (bits), (bits))
270#define ibx_disable_display_interrupt(dev_priv, bits) \
271 ibx_display_interrupt_update((dev_priv), (bits), 0)
272
de28075d
DV		 273static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
274 enum transcoder pch_transcoder,
8664281b
PZ		 275 bool enable)
276{
8664281b 277 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 278 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
279 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 280
281 if (enable)
fee884ed 282 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 283 else
fee884ed 284 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 285}
286
287static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
288 enum transcoder pch_transcoder,
289 bool enable)
290{
291 struct drm_i915_private *dev_priv = dev->dev_private;
292
293 if (enable) {
1dd246fb
DV		 294 I915_WRITE(SERR_INT,
295 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
296
8664281b
PZ		 297 if (!cpt_can_enable_serr_int(dev))
298 return;
299
fee884ed 300 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 301 } else {
1dd246fb
DV		 302 uint32_t tmp = I915_READ(SERR_INT);
303 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
304
305 /* Change the state _after_ we've read out the current one. */
fee884ed 306 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 307
308 if (!was_enabled &&
309 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
310 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
311 transcoder_name(pch_transcoder));
312 }
8664281b 313 }
8664281b
PZ		 314}
315
316/**
317 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
318 * @dev: drm device
319 * @pipe: pipe
320 * @enable: true if we want to report FIFO underrun errors, false otherwise
321 *
322 * This function makes us disable or enable CPU fifo underruns for a specific
323 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
324 * reporting for one pipe may also disable all the other CPU error interruts for
325 * the other pipes, due to the fact that there's just one interrupt mask/enable
326 * bit for all the pipes.
327 *
328 * Returns the previous state of underrun reporting.
329 */
330bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
331 enum pipe pipe, bool enable)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
334 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
336 unsigned long flags;
337 bool ret;
338
339 spin_lock_irqsave(&dev_priv->irq_lock, flags);
340
341 ret = !intel_crtc->cpu_fifo_underrun_disabled;
342
343 if (enable == ret)
344 goto done;
345
346 intel_crtc->cpu_fifo_underrun_disabled = !enable;
347
348 if (IS_GEN5(dev) || IS_GEN6(dev))
349 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
350 else if (IS_GEN7(dev))
7336df65 351 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 352
353done:
354 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
355 return ret;
356}
357
358/**
359 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
360 * @dev: drm device
361 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
362 * @enable: true if we want to report FIFO underrun errors, false otherwise
363 *
364 * This function makes us disable or enable PCH fifo underruns for a specific
365 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
366 * underrun reporting for one transcoder may also disable all the other PCH
367 * error interruts for the other transcoders, due to the fact that there's just
368 * one interrupt mask/enable bit for all the transcoders.
369 *
370 * Returns the previous state of underrun reporting.
371 */
372bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
373 enum transcoder pch_transcoder,
374 bool enable)
375{
376 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 377 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 379 unsigned long flags;
380 bool ret;
381
de28075d
DV		 382 /*
383 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
384 * has only one pch transcoder A that all pipes can use. To avoid racy
385 * pch transcoder -> pipe lookups from interrupt code simply store the
386 * underrun statistics in crtc A. Since we never expose this anywhere
387 * nor use it outside of the fifo underrun code here using the "wrong"
388 * crtc on LPT won't cause issues.
389 */
8664281b
PZ		 390
391 spin_lock_irqsave(&dev_priv->irq_lock, flags);
392
393 ret = !intel_crtc->pch_fifo_underrun_disabled;
394
395 if (enable == ret)
396 goto done;
397
398 intel_crtc->pch_fifo_underrun_disabled = !enable;
399
400 if (HAS_PCH_IBX(dev))
de28075d 401 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 402 else
403 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
404
405done:
406 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
407 return ret;
408}
409
410
7c463586
KP		 411void
412i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
413{
46c06a30
VS		 414 u32 reg = PIPESTAT(pipe);
415 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 416
b79480ba
DV		 417 assert_spin_locked(&dev_priv->irq_lock);
418
46c06a30
VS		 419 if ((pipestat & mask) == mask)
420 return;
421
422 /* Enable the interrupt, clear any pending status */
423 pipestat |= mask | (mask >> 16);
424 I915_WRITE(reg, pipestat);
425 POSTING_READ(reg);
7c463586
KP		 426}
427
428void
429i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
430{
46c06a30
VS		 431 u32 reg = PIPESTAT(pipe);
432 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 433
b79480ba
DV		 434 assert_spin_locked(&dev_priv->irq_lock);
435
46c06a30
VS		 436 if ((pipestat & mask) == 0)
437 return;
438
439 pipestat &= ~mask;
440 I915_WRITE(reg, pipestat);
441 POSTING_READ(reg);
7c463586
KP		 442}
443
01c66889 444/**
f49e38dd 445 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 446 */
f49e38dd 447static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 448{
1ec14ad3
CW		 449 drm_i915_private_t *dev_priv = dev->dev_private;
450 unsigned long irqflags;
451
f49e38dd
JN		 452 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
453 return;
454
1ec14ad3 455 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 456
f898780b
JN		 457 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
458 if (INTEL_INFO(dev)->gen >= 4)
459 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 460
461 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 462}
463
0a3e67a4
JB		 464/**
465 * i915_pipe_enabled - check if a pipe is enabled
466 * @dev: DRM device
467 * @pipe: pipe to check
468 *
469 * Reading certain registers when the pipe is disabled can hang the chip.
470 * Use this routine to make sure the PLL is running and the pipe is active
471 * before reading such registers if unsure.
472 */
473static int
474i915_pipe_enabled(struct drm_device *dev, int pipe)
475{
476 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 477
a01025af
DV		 478 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
479 /* Locking is horribly broken here, but whatever. */
480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 482
a01025af
DV		 483 return intel_crtc->active;
484 } else {
485 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
486 }
0a3e67a4
JB		 487}
488
42f52ef8
KP		 489/* Called from drm generic code, passed a 'crtc', which
490 * we use as a pipe index
491 */
f71d4af4 492static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 493{
494 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
495 unsigned long high_frame;
496 unsigned long low_frame;
5eddb70b 497 u32 high1, high2, low;
0a3e67a4
JB		 498
499 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 500 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 501 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 502 return 0;
503 }
504
9db4a9c7
JB		 505 high_frame = PIPEFRAME(pipe);
506 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 507
0a3e67a4
JB		 508 /*
509 * High & low register fields aren't synchronized, so make sure
510 * we get a low value that's stable across two reads of the high
511 * register.
512 */
513 do {
5eddb70b
CW		 514 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
515 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
516 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 517 } while (high1 != high2);
518
5eddb70b
CW		 519 high1 >>= PIPE_FRAME_HIGH_SHIFT;
520 low >>= PIPE_FRAME_LOW_SHIFT;
521 return (high1 << 8) | low;
0a3e67a4
JB		 522}
523
f71d4af4 524static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 525{
526 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 527 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 528
529 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 530 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 531 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 532 return 0;
533 }
534
535 return I915_READ(reg);
536}
537
f71d4af4 538static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 539 int *vpos, int *hpos)
540{
541 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
542 u32 vbl = 0, position = 0;
543 int vbl_start, vbl_end, htotal, vtotal;
544 bool in_vbl = true;
545 int ret = 0;
fe2b8f9d
PZ		 546 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
547 pipe);
0af7e4df
MK		 548
549 if (!i915_pipe_enabled(dev, pipe)) {
550 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 551 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 552 return 0;
553 }
554
555 /* Get vtotal. */
fe2b8f9d 556 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 557
558 if (INTEL_INFO(dev)->gen >= 4) {
559 /* No obvious pixelcount register. Only query vertical
560 * scanout position from Display scan line register.
561 */
562 position = I915_READ(PIPEDSL(pipe));
563
564 /* Decode into vertical scanout position. Don't have
565 * horizontal scanout position.
566 */
567 *vpos = position & 0x1fff;
568 *hpos = 0;
569 } else {
570 /* Have access to pixelcount since start of frame.
571 * We can split this into vertical and horizontal
572 * scanout position.
573 */
574 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
575
fe2b8f9d 576 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 577 *vpos = position / htotal;
578 *hpos = position - (*vpos * htotal);
579 }
580
581 /* Query vblank area. */
fe2b8f9d 582 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 583
584 /* Test position against vblank region. */
585 vbl_start = vbl & 0x1fff;
586 vbl_end = (vbl >> 16) & 0x1fff;
587
588 if ((*vpos < vbl_start) || (*vpos > vbl_end))
589 in_vbl = false;
590
591 /* Inside "upper part" of vblank area? Apply corrective offset: */
592 if (in_vbl && (*vpos >= vbl_start))
593 *vpos = *vpos - vtotal;
594
595 /* Readouts valid? */
596 if (vbl > 0)
597 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
598
599 /* In vblank? */
600 if (in_vbl)
601 ret |= DRM_SCANOUTPOS_INVBL;
602
603 return ret;
604}
605
f71d4af4 606static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 607 int *max_error,
608 struct timeval *vblank_time,
609 unsigned flags)
610{
4041b853 611 struct drm_crtc *crtc;
0af7e4df 612
7eb552ae 613 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 614 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 615 return -EINVAL;
616 }
617
618 /* Get drm_crtc to timestamp: */
4041b853
CW		 619 crtc = intel_get_crtc_for_pipe(dev, pipe);
620 if (crtc == NULL) {
621 DRM_ERROR("Invalid crtc %d\n", pipe);
622 return -EINVAL;
623 }
624
625 if (!crtc->enabled) {
626 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
627 return -EBUSY;
628 }
0af7e4df
MK		 629
630 /* Helper routine in DRM core does all the work: */
4041b853
CW		 631 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
632 vblank_time, flags,
633 crtc);
0af7e4df
MK		 634}
635
321a1b30
EE		 636static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
637{
638 enum drm_connector_status old_status;
639
640 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
641 old_status = connector->status;
642
643 connector->status = connector->funcs->detect(connector, false);
644 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
645 connector->base.id,
646 drm_get_connector_name(connector),
647 old_status, connector->status);
648 return (old_status != connector->status);
649}
650
5ca58282
JB		 651/*
652 * Handle hotplug events outside the interrupt handler proper.
653 */
ac4c16c5
EE		 654#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
655
5ca58282
JB		 656static void i915_hotplug_work_func(struct work_struct *work)
657{
658 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
659 hotplug_work);
660 struct drm_device *dev = dev_priv->dev;
c31c4ba3 661 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 662 struct intel_connector *intel_connector;
663 struct intel_encoder *intel_encoder;
664 struct drm_connector *connector;
665 unsigned long irqflags;
666 bool hpd_disabled = false;
321a1b30 667 bool changed = false;
142e2398 668 u32 hpd_event_bits;
4ef69c7a 669
52d7eced
DV		 670 /* HPD irq before everything is fully set up. */
671 if (!dev_priv->enable_hotplug_processing)
672 return;
673
a65e34c7 674 mutex_lock(&mode_config->mutex);
e67189ab
JB		 675 DRM_DEBUG_KMS("running encoder hotplug functions\n");
676
cd569aed 677 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 678
679 hpd_event_bits = dev_priv->hpd_event_bits;
680 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 681 list_for_each_entry(connector, &mode_config->connector_list, head) {
682 intel_connector = to_intel_connector(connector);
683 intel_encoder = intel_connector->encoder;
684 if (intel_encoder->hpd_pin > HPD_NONE &&
685 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
686 connector->polled == DRM_CONNECTOR_POLL_HPD) {
687 DRM_INFO("HPD interrupt storm detected on connector %s: "
688 "switching from hotplug detection to polling\n",
689 drm_get_connector_name(connector));
690 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
691 connector->polled = DRM_CONNECTOR_POLL_CONNECT
692 | DRM_CONNECTOR_POLL_DISCONNECT;
693 hpd_disabled = true;
694 }
142e2398
EE		 695 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
696 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
697 drm_get_connector_name(connector), intel_encoder->hpd_pin);
698 }
cd569aed
EE		 699 }
700 /* if there were no outputs to poll, poll was disabled,
701 * therefore make sure it's enabled when disabling HPD on
702 * some connectors */
ac4c16c5 703 if (hpd_disabled) {
cd569aed 704 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 705 mod_timer(&dev_priv->hotplug_reenable_timer,
706 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
707 }
cd569aed
EE		 708
709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
710
321a1b30
EE		 711 list_for_each_entry(connector, &mode_config->connector_list, head) {
712 intel_connector = to_intel_connector(connector);
713 intel_encoder = intel_connector->encoder;
714 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
715 if (intel_encoder->hot_plug)
716 intel_encoder->hot_plug(intel_encoder);
717 if (intel_hpd_irq_event(dev, connector))
718 changed = true;
719 }
720 }
40ee3381
KP		 721 mutex_unlock(&mode_config->mutex);
722
321a1b30
EE		 723 if (changed)
724 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 725}
726
d0ecd7e2 727static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 728{
729 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 730 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 731 u8 new_delay;
9270388e 732
d0ecd7e2 733 spin_lock(&mchdev_lock);
f97108d1 734
73edd18f
DV		 735 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
736
20e4d407 737 new_delay = dev_priv->ips.cur_delay;
9270388e 738
7648fa99 739 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 740 busy_up = I915_READ(RCPREVBSYTUPAVG);
741 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 742 max_avg = I915_READ(RCBMAXAVG);
743 min_avg = I915_READ(RCBMINAVG);
744
745 /* Handle RCS change request from hw */
b5b72e89 746 if (busy_up > max_avg) {
20e4d407
DV		 747 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
748 new_delay = dev_priv->ips.cur_delay - 1;
749 if (new_delay < dev_priv->ips.max_delay)
750 new_delay = dev_priv->ips.max_delay;
b5b72e89 751 } else if (busy_down < min_avg) {
20e4d407
DV		 752 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
753 new_delay = dev_priv->ips.cur_delay + 1;
754 if (new_delay > dev_priv->ips.min_delay)
755 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 756 }
757
7648fa99 758 if (ironlake_set_drps(dev, new_delay))
20e4d407 759 dev_priv->ips.cur_delay = new_delay;
f97108d1 760
d0ecd7e2 761 spin_unlock(&mchdev_lock);
9270388e 762
f97108d1
JB		 763 return;
764}
765
549f7365
CW		 766static void notify_ring(struct drm_device *dev,
767 struct intel_ring_buffer *ring)
768{
475553de
CW		 769 if (ring->obj == NULL)
770 return;
771
b2eadbc8 772 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 773
549f7365 774 wake_up_all(&ring->irq_queue);
10cd45b6 775 i915_queue_hangcheck(dev);
549f7365
CW		 776}
777
4912d041 778static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 779{
4912d041 780 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 781 rps.work);
edbfdb45 782 u32 pm_iir;
7b9e0ae6 783 u8 new_delay;
4912d041 784
59cdb63d 785 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 786 pm_iir = dev_priv->rps.pm_iir;
787 dev_priv->rps.pm_iir = 0;
4848405c 788 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
edbfdb45 789 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
59cdb63d 790 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 791
4848405c 792 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 793 return;
794
4fc688ce 795 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 796
7425034a 797 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 798 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 799
800 /*
801 * For better performance, jump directly
802 * to RPe if we're below it.
803 */
804 if (IS_VALLEYVIEW(dev_priv->dev) &&
805 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
806 new_delay = dev_priv->rps.rpe_delay;
807 } else
c6a828d3 808 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 809
79249636
BW		 810 /* sysfs frequency interfaces may have snuck in while servicing the
811 * interrupt
812 */
d8289c9e
VS		 813 if (new_delay >= dev_priv->rps.min_delay &&
814 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 815 if (IS_VALLEYVIEW(dev_priv->dev))
816 valleyview_set_rps(dev_priv->dev, new_delay);
817 else
818 gen6_set_rps(dev_priv->dev, new_delay);
79249636 819 }
3b8d8d91 820
52ceb908
JB		 821 if (IS_VALLEYVIEW(dev_priv->dev)) {
822 /*
823 * On VLV, when we enter RC6 we may not be at the minimum
824 * voltage level, so arm a timer to check. It should only
825 * fire when there's activity or once after we've entered
826 * RC6, and then won't be re-armed until the next RPS interrupt.
827 */
828 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
829 msecs_to_jiffies(100));
830 }
831
4fc688ce 832 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 833}
834
e3689190
BW		 835
836/**
837 * ivybridge_parity_work - Workqueue called when a parity error interrupt
838 * occurred.
839 * @work: workqueue struct
840 *
841 * Doesn't actually do anything except notify userspace. As a consequence of
842 * this event, userspace should try to remap the bad rows since statistically
843 * it is likely the same row is more likely to go bad again.
844 */
845static void ivybridge_parity_work(struct work_struct *work)
846{
847 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 848 l3_parity.error_work);
e3689190
BW		 849 u32 error_status, row, bank, subbank;
850 char *parity_event[5];
851 uint32_t misccpctl;
852 unsigned long flags;
853
854 /* We must turn off DOP level clock gating to access the L3 registers.
855 * In order to prevent a get/put style interface, acquire struct mutex
856 * any time we access those registers.
857 */
858 mutex_lock(&dev_priv->dev->struct_mutex);
859
860 misccpctl = I915_READ(GEN7_MISCCPCTL);
861 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
862 POSTING_READ(GEN7_MISCCPCTL);
863
864 error_status = I915_READ(GEN7_L3CDERRST1);
865 row = GEN7_PARITY_ERROR_ROW(error_status);
866 bank = GEN7_PARITY_ERROR_BANK(error_status);
867 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
868
869 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
870 GEN7_L3CDERRST1_ENABLE);
871 POSTING_READ(GEN7_L3CDERRST1);
872
873 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
874
875 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 876 ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
e3689190
BW		 877 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
878
879 mutex_unlock(&dev_priv->dev->struct_mutex);
880
cce723ed 881 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
e3689190
BW		 882 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
883 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
884 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
885 parity_event[4] = NULL;
886
887 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
888 KOBJ_CHANGE, parity_event);
889
890 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
891 row, bank, subbank);
892
893 kfree(parity_event[3]);
894 kfree(parity_event[2]);
895 kfree(parity_event[1]);
896}
897
d0ecd7e2 898static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
e3689190
BW		 899{
900 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 901
e1ef7cc2 902 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 903 return;
904
d0ecd7e2 905 spin_lock(&dev_priv->irq_lock);
43eaea13 906 ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
d0ecd7e2 907 spin_unlock(&dev_priv->irq_lock);
e3689190 908
a4da4fa4 909 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 910}
911
f1af8fc1
PZ		 912static void ilk_gt_irq_handler(struct drm_device *dev,
913 struct drm_i915_private *dev_priv,
914 u32 gt_iir)
915{
916 if (gt_iir &
917 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
918 notify_ring(dev, &dev_priv->ring[RCS]);
919 if (gt_iir & ILK_BSD_USER_INTERRUPT)
920 notify_ring(dev, &dev_priv->ring[VCS]);
921}
922
e7b4c6b1
DV		 923static void snb_gt_irq_handler(struct drm_device *dev,
924 struct drm_i915_private *dev_priv,
925 u32 gt_iir)
926{
927
cc609d5d
BW		 928 if (gt_iir &
929 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 930 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 931 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 932 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 933 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 934 notify_ring(dev, &dev_priv->ring[BCS]);
935
cc609d5d
BW		 936 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
937 GT_BSD_CS_ERROR_INTERRUPT |
938 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 939 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
940 i915_handle_error(dev, false);
941 }
e3689190 942
cc609d5d 943 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
d0ecd7e2 944 ivybridge_parity_error_irq_handler(dev);
e7b4c6b1
DV		 945}
946
baf02a1f 947/* Legacy way of handling PM interrupts */
d0ecd7e2
DV		 948static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
949 u32 pm_iir)
fc6826d1 950{
fc6826d1
CW		 951 /*
952 * IIR bits should never already be set because IMR should
953 * prevent an interrupt from being shown in IIR. The warning
954 * displays a case where we've unsafely cleared
c6a828d3 955 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 956 * type is not a problem, it displays a problem in the logic.
957 *
c6a828d3 958 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 959 */
960
59cdb63d 961 spin_lock(&dev_priv->irq_lock);
c6a828d3 962 dev_priv->rps.pm_iir |= pm_iir;
edbfdb45 963 snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir);
59cdb63d 964 spin_unlock(&dev_priv->irq_lock);
fc6826d1 965
c6a828d3 966 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 967}
968
b543fb04
EE		 969#define HPD_STORM_DETECT_PERIOD 1000
970#define HPD_STORM_THRESHOLD 5
971
10a504de 972static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 973 u32 hotplug_trigger,
974 const u32 *hpd)
b543fb04
EE		 975{
976 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 977 int i;
10a504de 978 bool storm_detected = false;
b543fb04 979
91d131d2
DV		 980 if (!hotplug_trigger)
981 return;
982
b5ea2d56 983 spin_lock(&dev_priv->irq_lock);
b543fb04 984 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 985
b8f102e8
EE		 986 WARN(((hpd[i] & hotplug_trigger) &&
987 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
988 "Received HPD interrupt although disabled\n");
989
b543fb04
EE		 990 if (!(hpd[i] & hotplug_trigger) ||
991 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
992 continue;
993
bc5ead8c 994 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 995 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
996 dev_priv->hpd_stats[i].hpd_last_jiffies
997 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
998 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
999 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1000 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1001 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1002 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1003 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1004 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1005 storm_detected = true;
b543fb04
EE		 1006 } else {
1007 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1008 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1009 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1010 }
1011 }
1012
10a504de
DV		 1013 if (storm_detected)
1014 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1015 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 1016
1017 queue_work(dev_priv->wq,
1018 &dev_priv->hotplug_work);
b543fb04
EE		 1019}
1020
515ac2bb
DV		 1021static void gmbus_irq_handler(struct drm_device *dev)
1022{
28c70f16
DV		 1023 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1024
28c70f16 1025 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1026}
1027
ce99c256
DV		 1028static void dp_aux_irq_handler(struct drm_device *dev)
1029{
9ee32fea
DV		 1030 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1031
9ee32fea 1032 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1033}
1034
d0ecd7e2 1035/* Unlike gen6_rps_irq_handler() from which this function is originally derived,
baf02a1f
BW		 1036 * we must be able to deal with other PM interrupts. This is complicated because
1037 * of the way in which we use the masks to defer the RPS work (which for
1038 * posterity is necessary because of forcewake).
1039 */
1040static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
1041 u32 pm_iir)
1042{
41a05a3a 1043 if (pm_iir & GEN6_PM_RPS_EVENTS) {
59cdb63d 1044 spin_lock(&dev_priv->irq_lock);
41a05a3a 1045 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
edbfdb45
PZ		 1046 snb_set_pm_irq(dev_priv, dev_priv->rps.pm_iir);
1047 /* never want to mask useful interrupts. */
4848405c 1048 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
59cdb63d 1049 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1050
1051 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1052 }
baf02a1f 1053
41a05a3a
DV		 1054 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1055 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1056
41a05a3a
DV		 1057 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1058 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1059 i915_handle_error(dev_priv->dev, false);
12638c57 1060 }
baf02a1f
BW		 1061}
1062
ff1f525e 1063static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1064{
1065 struct drm_device *dev = (struct drm_device *) arg;
1066 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1067 u32 iir, gt_iir, pm_iir;
1068 irqreturn_t ret = IRQ_NONE;
1069 unsigned long irqflags;
1070 int pipe;
1071 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 1072
1073 atomic_inc(&dev_priv->irq_received);
1074
7e231dbe
JB		 1075 while (true) {
1076 iir = I915_READ(VLV_IIR);
1077 gt_iir = I915_READ(GTIIR);
1078 pm_iir = I915_READ(GEN6_PMIIR);
1079
1080 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1081 goto out;
1082
1083 ret = IRQ_HANDLED;
1084
e7b4c6b1 1085 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1086
1087 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1088 for_each_pipe(pipe) {
1089 int reg = PIPESTAT(pipe);
1090 pipe_stats[pipe] = I915_READ(reg);
1091
1092 /*
1093 * Clear the PIPE*STAT regs before the IIR
1094 */
1095 if (pipe_stats[pipe] & 0x8000ffff) {
1096 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1097 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1098 pipe_name(pipe));
1099 I915_WRITE(reg, pipe_stats[pipe]);
1100 }
1101 }
1102 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1103
31acc7f5
JB		 1104 for_each_pipe(pipe) {
1105 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1106 drm_handle_vblank(dev, pipe);
1107
1108 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1109 intel_prepare_page_flip(dev, pipe);
1110 intel_finish_page_flip(dev, pipe);
1111 }
1112 }
1113
7e231dbe
JB		 1114 /* Consume port. Then clear IIR or we'll miss events */
1115 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1116 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1117 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1118
1119 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1120 hotplug_status);
91d131d2
DV		 1121
1122 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1123
7e231dbe
JB		 1124 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1125 I915_READ(PORT_HOTPLUG_STAT);
1126 }
1127
515ac2bb
DV		 1128 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1129 gmbus_irq_handler(dev);
7e231dbe 1130
4848405c 1131 if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1132 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1133
1134 I915_WRITE(GTIIR, gt_iir);
1135 I915_WRITE(GEN6_PMIIR, pm_iir);
1136 I915_WRITE(VLV_IIR, iir);
1137 }
1138
1139out:
1140 return ret;
1141}
1142
23e81d69 1143static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1144{
1145 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1146 int pipe;
b543fb04 1147 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1148
91d131d2
DV		 1149 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1150
cfc33bf7
VS		 1151 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1152 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1153 SDE_AUDIO_POWER_SHIFT);
776ad806 1154 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1155 port_name(port));
1156 }
776ad806 1157
ce99c256
DV		 1158 if (pch_iir & SDE_AUX_MASK)
1159 dp_aux_irq_handler(dev);
1160
776ad806 1161 if (pch_iir & SDE_GMBUS)
515ac2bb 1162 gmbus_irq_handler(dev);
776ad806
JB		 1163
1164 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1165 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1166
1167 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1168 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1169
1170 if (pch_iir & SDE_POISON)
1171 DRM_ERROR("PCH poison interrupt\n");
1172
9db4a9c7
JB		 1173 if (pch_iir & SDE_FDI_MASK)
1174 for_each_pipe(pipe)
1175 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1176 pipe_name(pipe),
1177 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1178
1179 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1180 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1181
1182 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1183 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1184
776ad806 1185 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1186 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1187 false))
1188 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1189
1190 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1191 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1192 false))
1193 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1194}
1195
1196static void ivb_err_int_handler(struct drm_device *dev)
1197{
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 err_int = I915_READ(GEN7_ERR_INT);
1200
de032bf4
PZ		 1201 if (err_int & ERR_INT_POISON)
1202 DRM_ERROR("Poison interrupt\n");
1203
8664281b
PZ		 1204 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1205 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1206 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1207
1208 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1209 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1210 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1211
1212 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1213 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1214 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1215
1216 I915_WRITE(GEN7_ERR_INT, err_int);
1217}
1218
1219static void cpt_serr_int_handler(struct drm_device *dev)
1220{
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 u32 serr_int = I915_READ(SERR_INT);
1223
de032bf4
PZ		 1224 if (serr_int & SERR_INT_POISON)
1225 DRM_ERROR("PCH poison interrupt\n");
1226
8664281b
PZ		 1227 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1228 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1229 false))
1230 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1231
1232 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1233 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1234 false))
1235 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1236
1237 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1238 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1239 false))
1240 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1241
1242 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1243}
1244
23e81d69
AJ		 1245static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1246{
1247 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1248 int pipe;
b543fb04 1249 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1250
91d131d2
DV		 1251 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1252
cfc33bf7
VS		 1253 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1254 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1255 SDE_AUDIO_POWER_SHIFT_CPT);
1256 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1257 port_name(port));
1258 }
23e81d69
AJ		 1259
1260 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1261 dp_aux_irq_handler(dev);
23e81d69
AJ		 1262
1263 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1264 gmbus_irq_handler(dev);
23e81d69
AJ		 1265
1266 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1267 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1268
1269 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1270 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1271
1272 if (pch_iir & SDE_FDI_MASK_CPT)
1273 for_each_pipe(pipe)
1274 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1275 pipe_name(pipe),
1276 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1277
1278 if (pch_iir & SDE_ERROR_CPT)
1279 cpt_serr_int_handler(dev);
23e81d69
AJ		 1280}
1281
c008bc6e
PZ		 1282static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1283{
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285
1286 if (de_iir & DE_AUX_CHANNEL_A)
1287 dp_aux_irq_handler(dev);
1288
1289 if (de_iir & DE_GSE)
1290 intel_opregion_asle_intr(dev);
1291
1292 if (de_iir & DE_PIPEA_VBLANK)
1293 drm_handle_vblank(dev, 0);
1294
1295 if (de_iir & DE_PIPEB_VBLANK)
1296 drm_handle_vblank(dev, 1);
1297
1298 if (de_iir & DE_POISON)
1299 DRM_ERROR("Poison interrupt\n");
1300
1301 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1302 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1303 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1304
1305 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1306 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1307 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1308
1309 if (de_iir & DE_PLANEA_FLIP_DONE) {
1310 intel_prepare_page_flip(dev, 0);
1311 intel_finish_page_flip_plane(dev, 0);
1312 }
1313
1314 if (de_iir & DE_PLANEB_FLIP_DONE) {
1315 intel_prepare_page_flip(dev, 1);
1316 intel_finish_page_flip_plane(dev, 1);
1317 }
1318
1319 /* check event from PCH */
1320 if (de_iir & DE_PCH_EVENT) {
1321 u32 pch_iir = I915_READ(SDEIIR);
1322
1323 if (HAS_PCH_CPT(dev))
1324 cpt_irq_handler(dev, pch_iir);
1325 else
1326 ibx_irq_handler(dev, pch_iir);
1327
1328 /* should clear PCH hotplug event before clear CPU irq */
1329 I915_WRITE(SDEIIR, pch_iir);
1330 }
1331
1332 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1333 ironlake_rps_change_irq_handler(dev);
1334}
1335
9719fb98
PZ		 1336static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1337{
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 int i;
1340
1341 if (de_iir & DE_ERR_INT_IVB)
1342 ivb_err_int_handler(dev);
1343
1344 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1345 dp_aux_irq_handler(dev);
1346
1347 if (de_iir & DE_GSE_IVB)
1348 intel_opregion_asle_intr(dev);
1349
1350 for (i = 0; i < 3; i++) {
1351 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1352 drm_handle_vblank(dev, i);
1353 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1354 intel_prepare_page_flip(dev, i);
1355 intel_finish_page_flip_plane(dev, i);
1356 }
1357 }
1358
1359 /* check event from PCH */
1360 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1361 u32 pch_iir = I915_READ(SDEIIR);
1362
1363 cpt_irq_handler(dev, pch_iir);
1364
1365 /* clear PCH hotplug event before clear CPU irq */
1366 I915_WRITE(SDEIIR, pch_iir);
1367 }
1368}
1369
f1af8fc1 1370static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1371{
1372 struct drm_device *dev = (struct drm_device *) arg;
1373 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
f1af8fc1 1374 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1375 irqreturn_t ret = IRQ_NONE;
b1f14ad0
JB		 1376
1377 atomic_inc(&dev_priv->irq_received);
1378
8664281b
PZ		 1379 /* We get interrupts on unclaimed registers, so check for this before we
1380 * do any I915_{READ,WRITE}. */
907b28c5 1381 intel_uncore_check_errors(dev);
8664281b 1382
b1f14ad0
JB		 1383 /* disable master interrupt before clearing iir */
1384 de_ier = I915_READ(DEIER);
1385 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1386 POSTING_READ(DEIER);
b1f14ad0 1387
44498aea
PZ		 1388 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1389 * interrupts will will be stored on its back queue, and then we'll be
1390 * able to process them after we restore SDEIER (as soon as we restore
1391 * it, we'll get an interrupt if SDEIIR still has something to process
1392 * due to its back queue). */
ab5c608b
BW		 1393 if (!HAS_PCH_NOP(dev)) {
1394 sde_ier = I915_READ(SDEIER);
1395 I915_WRITE(SDEIER, 0);
1396 POSTING_READ(SDEIER);
1397 }
44498aea 1398
8664281b
PZ		 1399 /* On Haswell, also mask ERR_INT because we don't want to risk
1400 * generating "unclaimed register" interrupts from inside the interrupt
1401 * handler. */
4bc9d430
DV		 1402 if (IS_HASWELL(dev)) {
1403 spin_lock(&dev_priv->irq_lock);
8664281b 1404 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1405 spin_unlock(&dev_priv->irq_lock);
1406 }
8664281b 1407
b1f14ad0 1408 gt_iir = I915_READ(GTIIR);
0e43406b 1409 if (gt_iir) {
d8fc8a47 1410 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1411 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1412 else
1413 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1414 I915_WRITE(GTIIR, gt_iir);
1415 ret = IRQ_HANDLED;
b1f14ad0
JB		 1416 }
1417
0e43406b
CW		 1418 de_iir = I915_READ(DEIIR);
1419 if (de_iir) {
f1af8fc1
PZ		 1420 if (INTEL_INFO(dev)->gen >= 7)
1421 ivb_display_irq_handler(dev, de_iir);
1422 else
1423 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1424 I915_WRITE(DEIIR, de_iir);
1425 ret = IRQ_HANDLED;
b1f14ad0
JB		 1426 }
1427
f1af8fc1
PZ		 1428 if (INTEL_INFO(dev)->gen >= 6) {
1429 u32 pm_iir = I915_READ(GEN6_PMIIR);
1430 if (pm_iir) {
1431 if (IS_HASWELL(dev))
1432 hsw_pm_irq_handler(dev_priv, pm_iir);
1433 else if (pm_iir & GEN6_PM_RPS_EVENTS)
1434 gen6_rps_irq_handler(dev_priv, pm_iir);
1435 I915_WRITE(GEN6_PMIIR, pm_iir);
1436 ret = IRQ_HANDLED;
1437 }
0e43406b 1438 }
b1f14ad0 1439
4bc9d430
DV		 1440 if (IS_HASWELL(dev)) {
1441 spin_lock(&dev_priv->irq_lock);
1442 if (ivb_can_enable_err_int(dev))
1443 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1444 spin_unlock(&dev_priv->irq_lock);
1445 }
8664281b 1446
b1f14ad0
JB		 1447 I915_WRITE(DEIER, de_ier);
1448 POSTING_READ(DEIER);
ab5c608b
BW		 1449 if (!HAS_PCH_NOP(dev)) {
1450 I915_WRITE(SDEIER, sde_ier);
1451 POSTING_READ(SDEIER);
1452 }
b1f14ad0
JB		 1453
1454 return ret;
1455}
1456
8a905236
JB		 1457/**
1458 * i915_error_work_func - do process context error handling work
1459 * @work: work struct
1460 *
1461 * Fire an error uevent so userspace can see that a hang or error
1462 * was detected.
1463 */
1464static void i915_error_work_func(struct work_struct *work)
1465{
1f83fee0
DV		 1466 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1467 work);
1468 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1469 gpu_error);
8a905236 1470 struct drm_device *dev = dev_priv->dev;
f69061be 1471 struct intel_ring_buffer *ring;
cce723ed
BW		 1472 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1473 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1474 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
f69061be 1475 int i, ret;
8a905236 1476
f316a42c
BG		 1477 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1478
7db0ba24
DV		 1479 /*
1480 * Note that there's only one work item which does gpu resets, so we
1481 * need not worry about concurrent gpu resets potentially incrementing
1482 * error->reset_counter twice. We only need to take care of another
1483 * racing irq/hangcheck declaring the gpu dead for a second time. A
1484 * quick check for that is good enough: schedule_work ensures the
1485 * correct ordering between hang detection and this work item, and since
1486 * the reset in-progress bit is only ever set by code outside of this
1487 * work we don't need to worry about any other races.
1488 */
1489 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1490 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1491 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1492 reset_event);
1f83fee0 1493
f69061be
DV		 1494 ret = i915_reset(dev);
1495
1496 if (ret == 0) {
1497 /*
1498 * After all the gem state is reset, increment the reset
1499 * counter and wake up everyone waiting for the reset to
1500 * complete.
1501 *
1502 * Since unlock operations are a one-sided barrier only,
1503 * we need to insert a barrier here to order any seqno
1504 * updates before
1505 * the counter increment.
1506 */
1507 smp_mb__before_atomic_inc();
1508 atomic_inc(&dev_priv->gpu_error.reset_counter);
1509
1510 kobject_uevent_env(&dev->primary->kdev.kobj,
1511 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1512 } else {
1513 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1514 }
1f83fee0 1515
f69061be
DV		 1516 for_each_ring(ring, dev_priv, i)
1517 wake_up_all(&ring->irq_queue);
1518
96a02917
VS		 1519 intel_display_handle_reset(dev);
1520
1f83fee0 1521 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1522 }
8a905236
JB		 1523}
1524
35aed2e6 1525static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1526{
1527 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1528 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1529 u32 eir = I915_READ(EIR);
050ee91f 1530 int pipe, i;
8a905236 1531
35aed2e6
CW		 1532 if (!eir)
1533 return;
8a905236 1534
a70491cc 1535 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1536
bd9854f9
BW		 1537 i915_get_extra_instdone(dev, instdone);
1538
8a905236
JB		 1539 if (IS_G4X(dev)) {
1540 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1541 u32 ipeir = I915_READ(IPEIR_I965);
1542
a70491cc
JP		 1543 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1544 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1545 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1546 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1547 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1548 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1549 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1550 POSTING_READ(IPEIR_I965);
8a905236
JB		 1551 }
1552 if (eir & GM45_ERROR_PAGE_TABLE) {
1553 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1554 pr_err("page table error\n");
1555 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1556 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1557 POSTING_READ(PGTBL_ER);
8a905236
JB		 1558 }
1559 }
1560
a6c45cf0 1561 if (!IS_GEN2(dev)) {
8a905236
JB		 1562 if (eir & I915_ERROR_PAGE_TABLE) {
1563 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1564 pr_err("page table error\n");
1565 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1566 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1567 POSTING_READ(PGTBL_ER);
8a905236
JB		 1568 }
1569 }
1570
1571 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1572 pr_err("memory refresh error:\n");
9db4a9c7 1573 for_each_pipe(pipe)
a70491cc 1574 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1575 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1576 /* pipestat has already been acked */
1577 }
1578 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1579 pr_err("instruction error\n");
1580 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1581 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1582 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1583 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1584 u32 ipeir = I915_READ(IPEIR);
1585
a70491cc
JP		 1586 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1587 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1588 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1589 I915_WRITE(IPEIR, ipeir);
3143a2bf 1590 POSTING_READ(IPEIR);
8a905236
JB		 1591 } else {
1592 u32 ipeir = I915_READ(IPEIR_I965);
1593
a70491cc
JP		 1594 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1595 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1596 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1597 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1598 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1599 POSTING_READ(IPEIR_I965);
8a905236
JB		 1600 }
1601 }
1602
1603 I915_WRITE(EIR, eir);
3143a2bf 1604 POSTING_READ(EIR);
8a905236
JB		 1605 eir = I915_READ(EIR);
1606 if (eir) {
1607 /*
1608 * some errors might have become stuck,
1609 * mask them.
1610 */
1611 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1612 I915_WRITE(EMR, I915_READ(EMR) | eir);
1613 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1614 }
35aed2e6
CW		 1615}
1616
1617/**
1618 * i915_handle_error - handle an error interrupt
1619 * @dev: drm device
1620 *
1621 * Do some basic checking of regsiter state at error interrupt time and
1622 * dump it to the syslog. Also call i915_capture_error_state() to make
1623 * sure we get a record and make it available in debugfs. Fire a uevent
1624 * so userspace knows something bad happened (should trigger collection
1625 * of a ring dump etc.).
1626 */
527f9e90 1627void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1628{
1629 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1630 struct intel_ring_buffer *ring;
1631 int i;
35aed2e6
CW		 1632
1633 i915_capture_error_state(dev);
1634 i915_report_and_clear_eir(dev);
8a905236 1635
ba1234d1 1636 if (wedged) {
f69061be
DV		 1637 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1638 &dev_priv->gpu_error.reset_counter);
ba1234d1 1639
11ed50ec 1640 /*
1f83fee0
DV		 1641 * Wakeup waiting processes so that the reset work item
1642 * doesn't deadlock trying to grab various locks.
11ed50ec 1643 */
b4519513
CW		 1644 for_each_ring(ring, dev_priv, i)
1645 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1646 }
1647
99584db3 1648 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1649}
1650
21ad8330 1651static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1652{
1653 drm_i915_private_t *dev_priv = dev->dev_private;
1654 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1656 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1657 struct intel_unpin_work *work;
1658 unsigned long flags;
1659 bool stall_detected;
1660
1661 /* Ignore early vblank irqs */
1662 if (intel_crtc == NULL)
1663 return;
1664
1665 spin_lock_irqsave(&dev->event_lock, flags);
1666 work = intel_crtc->unpin_work;
1667
e7d841ca
CW		 1668 if (work == NULL ||
1669 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1670 !work->enable_stall_check) {
4e5359cd
SF		 1671 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1672 spin_unlock_irqrestore(&dev->event_lock, flags);
1673 return;
1674 }
1675
1676 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1677 obj = work->pending_flip_obj;
a6c45cf0 1678 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1679 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 1680 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 1681 i915_gem_obj_ggtt_offset(obj);
4e5359cd 1682 } else {
9db4a9c7 1683 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 1684 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 1685 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1686 crtc->x * crtc->fb->bits_per_pixel/8);
1687 }
1688
1689 spin_unlock_irqrestore(&dev->event_lock, flags);
1690
1691 if (stall_detected) {
1692 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1693 intel_prepare_page_flip(dev, intel_crtc->plane);
1694 }
1695}
1696
42f52ef8
KP		 1697/* Called from drm generic code, passed 'crtc' which
1698 * we use as a pipe index
1699 */
f71d4af4 1700static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1701{
1702 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1703 unsigned long irqflags;
71e0ffa5 1704
5eddb70b 1705 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1706 return -EINVAL;
0a3e67a4 1707
1ec14ad3 1708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1709 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1710 i915_enable_pipestat(dev_priv, pipe,
1711 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1712 else
7c463586
KP		 1713 i915_enable_pipestat(dev_priv, pipe,
1714 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1715
1716 /* maintain vblank delivery even in deep C-states */
1717 if (dev_priv->info->gen == 3)
6b26c86d 1718 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1719 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1720
0a3e67a4
JB		 1721 return 0;
1722}
1723
f71d4af4 1724static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1725{
1726 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1727 unsigned long irqflags;
b518421f
PZ		 1728 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1729 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1730
1731 if (!i915_pipe_enabled(dev, pipe))
1732 return -EINVAL;
1733
1734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1735 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1737
1738 return 0;
1739}
1740
7e231dbe
JB		 1741static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1742{
1743 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1744 unsigned long irqflags;
31acc7f5 1745 u32 imr;
7e231dbe
JB		 1746
1747 if (!i915_pipe_enabled(dev, pipe))
1748 return -EINVAL;
1749
1750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1751 imr = I915_READ(VLV_IMR);
31acc7f5 1752 if (pipe == 0)
7e231dbe 1753 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1754 else
7e231dbe 1755 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1756 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1757 i915_enable_pipestat(dev_priv, pipe,
1758 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1759 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1760
1761 return 0;
1762}
1763
42f52ef8
KP		 1764/* Called from drm generic code, passed 'crtc' which
1765 * we use as a pipe index
1766 */
f71d4af4 1767static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1768{
1769 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1770 unsigned long irqflags;
0a3e67a4 1771
1ec14ad3 1772 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1773 if (dev_priv->info->gen == 3)
6b26c86d 1774 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1775
f796cf8f
JB		 1776 i915_disable_pipestat(dev_priv, pipe,
1777 PIPE_VBLANK_INTERRUPT_ENABLE |
1778 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1779 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1780}
1781
f71d4af4 1782static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1783{
1784 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1785 unsigned long irqflags;
b518421f
PZ		 1786 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1787 DE_PIPE_VBLANK_ILK(pipe);
f796cf8f
JB		 1788
1789 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 1790 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 1791 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1792}
1793
7e231dbe
JB		 1794static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1795{
1796 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1797 unsigned long irqflags;
31acc7f5 1798 u32 imr;
7e231dbe
JB		 1799
1800 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1801 i915_disable_pipestat(dev_priv, pipe,
1802 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1803 imr = I915_READ(VLV_IMR);
31acc7f5 1804 if (pipe == 0)
7e231dbe 1805 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1806 else
7e231dbe 1807 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1808 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1809 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1810}
1811
893eead0
CW		 1812static u32
1813ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1814{
893eead0
CW		 1815 return list_entry(ring->request_list.prev,
1816 struct drm_i915_gem_request, list)->seqno;
1817}
1818
9107e9d2
CW		 1819static bool
1820ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1821{
1822 return (list_empty(&ring->request_list) ||
1823 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 1824}
1825
6274f212
CW		 1826static struct intel_ring_buffer *
1827semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 1828{
1829 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 1830 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 1831
1832 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1833 if ((ipehr & ~(0x3 << 16)) !=
1834 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 1835 return NULL;
a24a11e6
CW		 1836
1837 /* ACTHD is likely pointing to the dword after the actual command,
1838 * so scan backwards until we find the MBOX.
1839 */
6274f212 1840 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 1841 acthd_min = max((int)acthd - 3 * 4, 0);
1842 do {
1843 cmd = ioread32(ring->virtual_start + acthd);
1844 if (cmd == ipehr)
1845 break;
1846
1847 acthd -= 4;
1848 if (acthd < acthd_min)
6274f212 1849 return NULL;
a24a11e6
CW		 1850 } while (1);
1851
6274f212
CW		 1852 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1853 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 1854}
1855
6274f212
CW		 1856static int semaphore_passed(struct intel_ring_buffer *ring)
1857{
1858 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1859 struct intel_ring_buffer *signaller;
1860 u32 seqno, ctl;
1861
1862 ring->hangcheck.deadlock = true;
1863
1864 signaller = semaphore_waits_for(ring, &seqno);
1865 if (signaller == NULL || signaller->hangcheck.deadlock)
1866 return -1;
1867
1868 /* cursory check for an unkickable deadlock */
1869 ctl = I915_READ_CTL(signaller);
1870 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1871 return -1;
1872
1873 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1874}
1875
1876static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1877{
1878 struct intel_ring_buffer *ring;
1879 int i;
1880
1881 for_each_ring(ring, dev_priv, i)
1882 ring->hangcheck.deadlock = false;
1883}
1884
ad8beaea
MK		 1885static enum intel_ring_hangcheck_action
1886ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 1887{
1888 struct drm_device *dev = ring->dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 1890 u32 tmp;
1891
6274f212 1892 if (ring->hangcheck.acthd != acthd)
f2f4d82f 1893 return HANGCHECK_ACTIVE;
6274f212 1894
9107e9d2 1895 if (IS_GEN2(dev))
f2f4d82f 1896 return HANGCHECK_HUNG;
9107e9d2
CW		 1897
1898 /* Is the chip hanging on a WAIT_FOR_EVENT?
1899 * If so we can simply poke the RB_WAIT bit
1900 * and break the hang. This should work on
1901 * all but the second generation chipsets.
1902 */
1903 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 1904 if (tmp & RING_WAIT) {
1905 DRM_ERROR("Kicking stuck wait on %s\n",
1906 ring->name);
1907 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1908 return HANGCHECK_KICK;
6274f212
CW		 1909 }
1910
1911 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1912 switch (semaphore_passed(ring)) {
1913 default:
f2f4d82f 1914 return HANGCHECK_HUNG;
6274f212
CW		 1915 case 1:
1916 DRM_ERROR("Kicking stuck semaphore on %s\n",
1917 ring->name);
1918 I915_WRITE_CTL(ring, tmp);
f2f4d82f 1919 return HANGCHECK_KICK;
6274f212 1920 case 0:
f2f4d82f 1921 return HANGCHECK_WAIT;
6274f212 1922 }
9107e9d2 1923 }
ed5cbb03 1924
f2f4d82f 1925 return HANGCHECK_HUNG;
ed5cbb03
MK		 1926}
1927
f65d9421
BG		 1928/**
1929 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 1930 * batchbuffers in a long time. We keep track per ring seqno progress and
1931 * if there are no progress, hangcheck score for that ring is increased.
1932 * Further, acthd is inspected to see if the ring is stuck. On stuck case
1933 * we kick the ring. If we see no progress on three subsequent calls
1934 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 1935 */
a658b5d2 1936static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 1937{
1938 struct drm_device *dev = (struct drm_device *)data;
1939 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 1940 struct intel_ring_buffer *ring;
b4519513 1941 int i;
05407ff8 1942 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 1943 bool stuck[I915_NUM_RINGS] = { 0 };
1944#define BUSY 1
1945#define KICK 5
1946#define HUNG 20
1947#define FIRE 30
893eead0 1948
3e0dc6b0
BW		 1949 if (!i915_enable_hangcheck)
1950 return;
1951
b4519513 1952 for_each_ring(ring, dev_priv, i) {
05407ff8 1953 u32 seqno, acthd;
9107e9d2 1954 bool busy = true;
05407ff8 1955
6274f212
CW		 1956 semaphore_clear_deadlocks(dev_priv);
1957
05407ff8
MK		 1958 seqno = ring->get_seqno(ring, false);
1959 acthd = intel_ring_get_active_head(ring);
b4519513 1960
9107e9d2
CW		 1961 if (ring->hangcheck.seqno == seqno) {
1962 if (ring_idle(ring, seqno)) {
1963 if (waitqueue_active(&ring->irq_queue)) {
1964 /* Issue a wake-up to catch stuck h/w. */
1965 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1966 ring->name);
1967 wake_up_all(&ring->irq_queue);
1968 ring->hangcheck.score += HUNG;
1969 } else
1970 busy = false;
05407ff8 1971 } else {
6274f212
CW		 1972 /* We always increment the hangcheck score
1973 * if the ring is busy and still processing
1974 * the same request, so that no single request
1975 * can run indefinitely (such as a chain of
1976 * batches). The only time we do not increment
1977 * the hangcheck score on this ring, if this
1978 * ring is in a legitimate wait for another
1979 * ring. In that case the waiting ring is a
1980 * victim and we want to be sure we catch the
1981 * right culprit. Then every time we do kick
1982 * the ring, add a small increment to the
1983 * score so that we can catch a batch that is
1984 * being repeatedly kicked and so responsible
1985 * for stalling the machine.
1986 */
ad8beaea
MK		 1987 ring->hangcheck.action = ring_stuck(ring,
1988 acthd);
1989
1990 switch (ring->hangcheck.action) {
f2f4d82f 1991 case HANGCHECK_WAIT:
6274f212 1992 break;
f2f4d82f 1993 case HANGCHECK_ACTIVE:
ea04cb31 1994 ring->hangcheck.score += BUSY;
6274f212 1995 break;
f2f4d82f 1996 case HANGCHECK_KICK:
ea04cb31 1997 ring->hangcheck.score += KICK;
6274f212 1998 break;
f2f4d82f 1999 case HANGCHECK_HUNG:
ea04cb31 2000 ring->hangcheck.score += HUNG;
6274f212
CW		 2001 stuck[i] = true;
2002 break;
2003 }
05407ff8 2004 }
9107e9d2
CW		 2005 } else {
2006 /* Gradually reduce the count so that we catch DoS
2007 * attempts across multiple batches.
2008 */
2009 if (ring->hangcheck.score > 0)
2010 ring->hangcheck.score--;
d1e61e7f
CW		 2011 }
2012
05407ff8
MK		 2013 ring->hangcheck.seqno = seqno;
2014 ring->hangcheck.acthd = acthd;
9107e9d2 2015 busy_count += busy;
893eead0 2016 }
b9201c14 2017
92cab734 2018 for_each_ring(ring, dev_priv, i) {
9107e9d2 2019 if (ring->hangcheck.score > FIRE) {
acd78c11 2020 DRM_ERROR("%s on %s\n",
05407ff8 2021 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2022 ring->name);
2023 rings_hung++;
92cab734
MK		 2024 }
2025 }
2026
05407ff8
MK		 2027 if (rings_hung)
2028 return i915_handle_error(dev, true);
f65d9421 2029
05407ff8
MK		 2030 if (busy_count)
2031 /* Reset timer case chip hangs without another request
2032 * being added */
10cd45b6
MK		 2033 i915_queue_hangcheck(dev);
2034}
2035
2036void i915_queue_hangcheck(struct drm_device *dev)
2037{
2038 struct drm_i915_private *dev_priv = dev->dev_private;
2039 if (!i915_enable_hangcheck)
2040 return;
2041
2042 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2043 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2044}
2045
91738a95
PZ		 2046static void ibx_irq_preinstall(struct drm_device *dev)
2047{
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2049
2050 if (HAS_PCH_NOP(dev))
2051 return;
2052
2053 /* south display irq */
2054 I915_WRITE(SDEIMR, 0xffffffff);
2055 /*
2056 * SDEIER is also touched by the interrupt handler to work around missed
2057 * PCH interrupts. Hence we can't update it after the interrupt handler
2058 * is enabled - instead we unconditionally enable all PCH interrupt
2059 * sources here, but then only unmask them as needed with SDEIMR.
2060 */
2061 I915_WRITE(SDEIER, 0xffffffff);
2062 POSTING_READ(SDEIER);
2063}
2064
d18ea1b5
DV		 2065static void gen5_gt_irq_preinstall(struct drm_device *dev)
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068
2069 /* and GT */
2070 I915_WRITE(GTIMR, 0xffffffff);
2071 I915_WRITE(GTIER, 0x0);
2072 POSTING_READ(GTIER);
2073
2074 if (INTEL_INFO(dev)->gen >= 6) {
2075 /* and PM */
2076 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2077 I915_WRITE(GEN6_PMIER, 0x0);
2078 POSTING_READ(GEN6_PMIER);
2079 }
2080}
2081
1da177e4
LT		 2082/* drm_dma.h hooks
2083*/
f71d4af4 2084static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2085{
2086 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2087
4697995b
JB		 2088 atomic_set(&dev_priv->irq_received, 0);
2089
036a4a7d 2090 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2091
036a4a7d
ZW		 2092 I915_WRITE(DEIMR, 0xffffffff);
2093 I915_WRITE(DEIER, 0x0);
3143a2bf 2094 POSTING_READ(DEIER);
036a4a7d 2095
d18ea1b5 2096 gen5_gt_irq_preinstall(dev);
c650156a 2097
91738a95 2098 ibx_irq_preinstall(dev);
7d99163d
BW		 2099}
2100
7e231dbe
JB		 2101static void valleyview_irq_preinstall(struct drm_device *dev)
2102{
2103 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2104 int pipe;
2105
2106 atomic_set(&dev_priv->irq_received, 0);
2107
7e231dbe
JB		 2108 /* VLV magic */
2109 I915_WRITE(VLV_IMR, 0);
2110 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2111 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2112 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2113
7e231dbe
JB		 2114 /* and GT */
2115 I915_WRITE(GTIIR, I915_READ(GTIIR));
2116 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5
DV		 2117
2118 gen5_gt_irq_preinstall(dev);
7e231dbe
JB		 2119
2120 I915_WRITE(DPINVGTT, 0xff);
2121
2122 I915_WRITE(PORT_HOTPLUG_EN, 0);
2123 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2124 for_each_pipe(pipe)
2125 I915_WRITE(PIPESTAT(pipe), 0xffff);
2126 I915_WRITE(VLV_IIR, 0xffffffff);
2127 I915_WRITE(VLV_IMR, 0xffffffff);
2128 I915_WRITE(VLV_IER, 0x0);
2129 POSTING_READ(VLV_IER);
2130}
2131
82a28bcf 2132static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2133{
2134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2135 struct drm_mode_config *mode_config = &dev->mode_config;
2136 struct intel_encoder *intel_encoder;
fee884ed 2137 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2138
2139 if (HAS_PCH_IBX(dev)) {
fee884ed 2140 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2141 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2142 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2143 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2144 } else {
fee884ed 2145 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2146 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2147 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2148 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2149 }
7fe0b973 2150
fee884ed 2151 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2152
2153 /*
2154 * Enable digital hotplug on the PCH, and configure the DP short pulse
2155 * duration to 2ms (which is the minimum in the Display Port spec)
2156 *
2157 * This register is the same on all known PCH chips.
2158 */
7fe0b973
KP		 2159 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2160 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2161 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2162 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2163 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2164 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2165}
2166
d46da437
PZ		 2167static void ibx_irq_postinstall(struct drm_device *dev)
2168{
2169 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2170 u32 mask;
e5868a31 2171
692a04cf
DV		 2172 if (HAS_PCH_NOP(dev))
2173 return;
2174
8664281b
PZ		 2175 if (HAS_PCH_IBX(dev)) {
2176 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2177 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2178 } else {
2179 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2180
2181 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2182 }
ab5c608b 2183
d46da437
PZ		 2184 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2185 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2186}
2187
0a9a8c91
DV		 2188static void gen5_gt_irq_postinstall(struct drm_device *dev)
2189{
2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191 u32 pm_irqs, gt_irqs;
2192
2193 pm_irqs = gt_irqs = 0;
2194
2195 dev_priv->gt_irq_mask = ~0;
2196 if (HAS_L3_GPU_CACHE(dev)) {
2197 /* L3 parity interrupt is always unmasked. */
2198 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2199 gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2200 }
2201
2202 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2203 if (IS_GEN5(dev)) {
2204 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2205 ILK_BSD_USER_INTERRUPT;
2206 } else {
2207 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2208 }
2209
2210 I915_WRITE(GTIIR, I915_READ(GTIIR));
2211 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2212 I915_WRITE(GTIER, gt_irqs);
2213 POSTING_READ(GTIER);
2214
2215 if (INTEL_INFO(dev)->gen >= 6) {
2216 pm_irqs |= GEN6_PM_RPS_EVENTS;
2217
2218 if (HAS_VEBOX(dev))
2219 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2220
605cd25b 2221 dev_priv->pm_irq_mask = 0xffffffff;
0a9a8c91 2222 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
605cd25b 2223 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
0a9a8c91
DV		 2224 I915_WRITE(GEN6_PMIER, pm_irqs);
2225 POSTING_READ(GEN6_PMIER);
2226 }
2227}
2228
f71d4af4 2229static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2230{
4bc9d430 2231 unsigned long irqflags;
036a4a7d 2232 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8e76f8dc
PZ		 2233 u32 display_mask, extra_mask;
2234
2235 if (INTEL_INFO(dev)->gen >= 7) {
2236 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2237 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2238 DE_PLANEB_FLIP_DONE_IVB |
2239 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2240 DE_ERR_INT_IVB);
2241 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2242 DE_PIPEA_VBLANK_IVB);
2243
2244 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2245 } else {
2246 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2247 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2248 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2249 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2250 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2251 }
036a4a7d 2252
1ec14ad3 2253 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2254
2255 /* should always can generate irq */
2256 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2257 I915_WRITE(DEIMR, dev_priv->irq_mask);
8e76f8dc 2258 I915_WRITE(DEIER, display_mask | extra_mask);
3143a2bf 2259 POSTING_READ(DEIER);
036a4a7d 2260
0a9a8c91 2261 gen5_gt_irq_postinstall(dev);
036a4a7d 2262
d46da437 2263 ibx_irq_postinstall(dev);
7fe0b973 2264
f97108d1 2265 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2266 /* Enable PCU event interrupts
2267 *
2268 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2269 * setup is guaranteed to run in single-threaded context. But we
2270 * need it to make the assert_spin_locked happy. */
2271 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2272 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2273 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2274 }
2275
036a4a7d
ZW		 2276 return 0;
2277}
2278
7e231dbe
JB		 2279static int valleyview_irq_postinstall(struct drm_device *dev)
2280{
2281 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2282 u32 enable_mask;
31acc7f5 2283 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2284 unsigned long irqflags;
7e231dbe
JB		 2285
2286 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2287 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2288 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2289 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2290 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2291
31acc7f5
JB		 2292 /*
2293 *Leave vblank interrupts masked initially. enable/disable will
2294 * toggle them based on usage.
2295 */
2296 dev_priv->irq_mask = (~enable_mask) |
2297 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2298 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2299
20afbda2
DV		 2300 I915_WRITE(PORT_HOTPLUG_EN, 0);
2301 POSTING_READ(PORT_HOTPLUG_EN);
2302
7e231dbe
JB		 2303 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2304 I915_WRITE(VLV_IER, enable_mask);
2305 I915_WRITE(VLV_IIR, 0xffffffff);
2306 I915_WRITE(PIPESTAT(0), 0xffff);
2307 I915_WRITE(PIPESTAT(1), 0xffff);
2308 POSTING_READ(VLV_IER);
2309
b79480ba
DV		 2310 /* Interrupt setup is already guaranteed to be single-threaded, this is
2311 * just to make the assert_spin_locked check happy. */
2312 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2313 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2314 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2315 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2316 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2317
7e231dbe
JB		 2318 I915_WRITE(VLV_IIR, 0xffffffff);
2319 I915_WRITE(VLV_IIR, 0xffffffff);
2320
0a9a8c91 2321 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 2322
2323 /* ack & enable invalid PTE error interrupts */
2324#if 0 /* FIXME: add support to irq handler for checking these bits */
2325 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2326 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2327#endif
2328
2329 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2330
2331 return 0;
2332}
2333
7e231dbe
JB		 2334static void valleyview_irq_uninstall(struct drm_device *dev)
2335{
2336 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2337 int pipe;
2338
2339 if (!dev_priv)
2340 return;
2341
ac4c16c5
EE		 2342 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2343
7e231dbe
JB		 2344 for_each_pipe(pipe)
2345 I915_WRITE(PIPESTAT(pipe), 0xffff);
2346
2347 I915_WRITE(HWSTAM, 0xffffffff);
2348 I915_WRITE(PORT_HOTPLUG_EN, 0);
2349 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2350 for_each_pipe(pipe)
2351 I915_WRITE(PIPESTAT(pipe), 0xffff);
2352 I915_WRITE(VLV_IIR, 0xffffffff);
2353 I915_WRITE(VLV_IMR, 0xffffffff);
2354 I915_WRITE(VLV_IER, 0x0);
2355 POSTING_READ(VLV_IER);
2356}
2357
f71d4af4 2358static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2359{
2360 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2361
2362 if (!dev_priv)
2363 return;
2364
ac4c16c5
EE		 2365 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2366
036a4a7d
ZW		 2367 I915_WRITE(HWSTAM, 0xffffffff);
2368
2369 I915_WRITE(DEIMR, 0xffffffff);
2370 I915_WRITE(DEIER, 0x0);
2371 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2372 if (IS_GEN7(dev))
2373 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2374
2375 I915_WRITE(GTIMR, 0xffffffff);
2376 I915_WRITE(GTIER, 0x0);
2377 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2378
ab5c608b
BW		 2379 if (HAS_PCH_NOP(dev))
2380 return;
2381
192aac1f
KP		 2382 I915_WRITE(SDEIMR, 0xffffffff);
2383 I915_WRITE(SDEIER, 0x0);
2384 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2385 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2386 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2387}
2388
a266c7d5 2389static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2390{
2391 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2392 int pipe;
91e3738e 2393
a266c7d5 2394 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2395
9db4a9c7
JB		 2396 for_each_pipe(pipe)
2397 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2398 I915_WRITE16(IMR, 0xffff);
2399 I915_WRITE16(IER, 0x0);
2400 POSTING_READ16(IER);
c2798b19
CW		 2401}
2402
2403static int i8xx_irq_postinstall(struct drm_device *dev)
2404{
2405 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2406
c2798b19
CW		 2407 I915_WRITE16(EMR,
2408 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2409
2410 /* Unmask the interrupts that we always want on. */
2411 dev_priv->irq_mask =
2412 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2413 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2414 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2415 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2416 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2417 I915_WRITE16(IMR, dev_priv->irq_mask);
2418
2419 I915_WRITE16(IER,
2420 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2421 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2422 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2423 I915_USER_INTERRUPT);
2424 POSTING_READ16(IER);
2425
2426 return 0;
2427}
2428
90a72f87
VS		 2429/*
2430 * Returns true when a page flip has completed.
2431 */
2432static bool i8xx_handle_vblank(struct drm_device *dev,
2433 int pipe, u16 iir)
2434{
2435 drm_i915_private_t *dev_priv = dev->dev_private;
2436 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2437
2438 if (!drm_handle_vblank(dev, pipe))
2439 return false;
2440
2441 if ((iir & flip_pending) == 0)
2442 return false;
2443
2444 intel_prepare_page_flip(dev, pipe);
2445
2446 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2447 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2448 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2449 * the flip is completed (no longer pending). Since this doesn't raise
2450 * an interrupt per se, we watch for the change at vblank.
2451 */
2452 if (I915_READ16(ISR) & flip_pending)
2453 return false;
2454
2455 intel_finish_page_flip(dev, pipe);
2456
2457 return true;
2458}
2459
ff1f525e 2460static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2461{
2462 struct drm_device *dev = (struct drm_device *) arg;
2463 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2464 u16 iir, new_iir;
2465 u32 pipe_stats[2];
2466 unsigned long irqflags;
c2798b19
CW		 2467 int pipe;
2468 u16 flip_mask =
2469 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2470 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2471
2472 atomic_inc(&dev_priv->irq_received);
2473
2474 iir = I915_READ16(IIR);
2475 if (iir == 0)
2476 return IRQ_NONE;
2477
2478 while (iir & ~flip_mask) {
2479 /* Can't rely on pipestat interrupt bit in iir as it might
2480 * have been cleared after the pipestat interrupt was received.
2481 * It doesn't set the bit in iir again, but it still produces
2482 * interrupts (for non-MSI).
2483 */
2484 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2485 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2486 i915_handle_error(dev, false);
2487
2488 for_each_pipe(pipe) {
2489 int reg = PIPESTAT(pipe);
2490 pipe_stats[pipe] = I915_READ(reg);
2491
2492 /*
2493 * Clear the PIPE*STAT regs before the IIR
2494 */
2495 if (pipe_stats[pipe] & 0x8000ffff) {
2496 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2497 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2498 pipe_name(pipe));
2499 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 2500 }
2501 }
2502 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2503
2504 I915_WRITE16(IIR, iir & ~flip_mask);
2505 new_iir = I915_READ16(IIR); /* Flush posted writes */
2506
d05c617e 2507 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2508
2509 if (iir & I915_USER_INTERRUPT)
2510 notify_ring(dev, &dev_priv->ring[RCS]);
2511
2512 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2513 i8xx_handle_vblank(dev, 0, iir))
2514 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2515
2516 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2517 i8xx_handle_vblank(dev, 1, iir))
2518 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2519
2520 iir = new_iir;
2521 }
2522
2523 return IRQ_HANDLED;
2524}
2525
2526static void i8xx_irq_uninstall(struct drm_device * dev)
2527{
2528 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2529 int pipe;
2530
c2798b19
CW		 2531 for_each_pipe(pipe) {
2532 /* Clear enable bits; then clear status bits */
2533 I915_WRITE(PIPESTAT(pipe), 0);
2534 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2535 }
2536 I915_WRITE16(IMR, 0xffff);
2537 I915_WRITE16(IER, 0x0);
2538 I915_WRITE16(IIR, I915_READ16(IIR));
2539}
2540
a266c7d5
CW		 2541static void i915_irq_preinstall(struct drm_device * dev)
2542{
2543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2544 int pipe;
2545
2546 atomic_set(&dev_priv->irq_received, 0);
2547
2548 if (I915_HAS_HOTPLUG(dev)) {
2549 I915_WRITE(PORT_HOTPLUG_EN, 0);
2550 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2551 }
2552
00d98ebd 2553 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2554 for_each_pipe(pipe)
2555 I915_WRITE(PIPESTAT(pipe), 0);
2556 I915_WRITE(IMR, 0xffffffff);
2557 I915_WRITE(IER, 0x0);
2558 POSTING_READ(IER);
2559}
2560
2561static int i915_irq_postinstall(struct drm_device *dev)
2562{
2563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2564 u32 enable_mask;
a266c7d5 2565
38bde180
CW		 2566 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2567
2568 /* Unmask the interrupts that we always want on. */
2569 dev_priv->irq_mask =
2570 ~(I915_ASLE_INTERRUPT |
2571 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2572 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2573 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2574 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2575 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2576
2577 enable_mask =
2578 I915_ASLE_INTERRUPT |
2579 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2580 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2581 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2582 I915_USER_INTERRUPT;
2583
a266c7d5 2584 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2585 I915_WRITE(PORT_HOTPLUG_EN, 0);
2586 POSTING_READ(PORT_HOTPLUG_EN);
2587
a266c7d5
CW		 2588 /* Enable in IER... */
2589 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2590 /* and unmask in IMR */
2591 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2592 }
2593
a266c7d5
CW		 2594 I915_WRITE(IMR, dev_priv->irq_mask);
2595 I915_WRITE(IER, enable_mask);
2596 POSTING_READ(IER);
2597
f49e38dd 2598 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2599
2600 return 0;
2601}
2602
90a72f87
VS		 2603/*
2604 * Returns true when a page flip has completed.
2605 */
2606static bool i915_handle_vblank(struct drm_device *dev,
2607 int plane, int pipe, u32 iir)
2608{
2609 drm_i915_private_t *dev_priv = dev->dev_private;
2610 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2611
2612 if (!drm_handle_vblank(dev, pipe))
2613 return false;
2614
2615 if ((iir & flip_pending) == 0)
2616 return false;
2617
2618 intel_prepare_page_flip(dev, plane);
2619
2620 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2621 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2622 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2623 * the flip is completed (no longer pending). Since this doesn't raise
2624 * an interrupt per se, we watch for the change at vblank.
2625 */
2626 if (I915_READ(ISR) & flip_pending)
2627 return false;
2628
2629 intel_finish_page_flip(dev, pipe);
2630
2631 return true;
2632}
2633
ff1f525e 2634static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2635{
2636 struct drm_device *dev = (struct drm_device *) arg;
2637 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2638 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2639 unsigned long irqflags;
38bde180
CW		 2640 u32 flip_mask =
2641 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2642 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2643 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2644
2645 atomic_inc(&dev_priv->irq_received);
2646
2647 iir = I915_READ(IIR);
38bde180
CW		 2648 do {
2649 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2650 bool blc_event = false;
a266c7d5
CW		 2651
2652 /* Can't rely on pipestat interrupt bit in iir as it might
2653 * have been cleared after the pipestat interrupt was received.
2654 * It doesn't set the bit in iir again, but it still produces
2655 * interrupts (for non-MSI).
2656 */
2657 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2658 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2659 i915_handle_error(dev, false);
2660
2661 for_each_pipe(pipe) {
2662 int reg = PIPESTAT(pipe);
2663 pipe_stats[pipe] = I915_READ(reg);
2664
38bde180 2665 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2666 if (pipe_stats[pipe] & 0x8000ffff) {
2667 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2668 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2669 pipe_name(pipe));
2670 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2671 irq_received = true;
a266c7d5
CW		 2672 }
2673 }
2674 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2675
2676 if (!irq_received)
2677 break;
2678
a266c7d5
CW		 2679 /* Consume port. Then clear IIR or we'll miss events */
2680 if ((I915_HAS_HOTPLUG(dev)) &&
2681 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2682 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 2683 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 2684
2685 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2686 hotplug_status);
91d131d2
DV		 2687
2688 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2689
a266c7d5 2690 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2691 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2692 }
2693
38bde180 2694 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2695 new_iir = I915_READ(IIR); /* Flush posted writes */
2696
a266c7d5
CW		 2697 if (iir & I915_USER_INTERRUPT)
2698 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2699
a266c7d5 2700 for_each_pipe(pipe) {
38bde180
CW		 2701 int plane = pipe;
2702 if (IS_MOBILE(dev))
2703 plane = !plane;
90a72f87 2704
8291ee90 2705 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2706 i915_handle_vblank(dev, plane, pipe, iir))
2707 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2708
2709 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2710 blc_event = true;
2711 }
2712
a266c7d5
CW		 2713 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2714 intel_opregion_asle_intr(dev);
2715
2716 /* With MSI, interrupts are only generated when iir
2717 * transitions from zero to nonzero. If another bit got
2718 * set while we were handling the existing iir bits, then
2719 * we would never get another interrupt.
2720 *
2721 * This is fine on non-MSI as well, as if we hit this path
2722 * we avoid exiting the interrupt handler only to generate
2723 * another one.
2724 *
2725 * Note that for MSI this could cause a stray interrupt report
2726 * if an interrupt landed in the time between writing IIR and
2727 * the posting read. This should be rare enough to never
2728 * trigger the 99% of 100,000 interrupts test for disabling
2729 * stray interrupts.
2730 */
38bde180 2731 ret = IRQ_HANDLED;
a266c7d5 2732 iir = new_iir;
38bde180 2733 } while (iir & ~flip_mask);
a266c7d5 2734
d05c617e 2735 i915_update_dri1_breadcrumb(dev);
8291ee90 2736
a266c7d5
CW		 2737 return ret;
2738}
2739
2740static void i915_irq_uninstall(struct drm_device * dev)
2741{
2742 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2743 int pipe;
2744
ac4c16c5
EE		 2745 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2746
a266c7d5
CW		 2747 if (I915_HAS_HOTPLUG(dev)) {
2748 I915_WRITE(PORT_HOTPLUG_EN, 0);
2749 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2750 }
2751
00d98ebd 2752 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2753 for_each_pipe(pipe) {
2754 /* Clear enable bits; then clear status bits */
a266c7d5 2755 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2756 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2757 }
a266c7d5
CW		 2758 I915_WRITE(IMR, 0xffffffff);
2759 I915_WRITE(IER, 0x0);
2760
a266c7d5
CW		 2761 I915_WRITE(IIR, I915_READ(IIR));
2762}
2763
2764static void i965_irq_preinstall(struct drm_device * dev)
2765{
2766 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2767 int pipe;
2768
2769 atomic_set(&dev_priv->irq_received, 0);
2770
adca4730
CW		 2771 I915_WRITE(PORT_HOTPLUG_EN, 0);
2772 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2773
2774 I915_WRITE(HWSTAM, 0xeffe);
2775 for_each_pipe(pipe)
2776 I915_WRITE(PIPESTAT(pipe), 0);
2777 I915_WRITE(IMR, 0xffffffff);
2778 I915_WRITE(IER, 0x0);
2779 POSTING_READ(IER);
2780}
2781
2782static int i965_irq_postinstall(struct drm_device *dev)
2783{
2784 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2785 u32 enable_mask;
a266c7d5 2786 u32 error_mask;
b79480ba 2787 unsigned long irqflags;
a266c7d5 2788
a266c7d5 2789 /* Unmask the interrupts that we always want on. */
bbba0a97 2790 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2791 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2792 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2793 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2794 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2795 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2796 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2797
2798 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2799 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2800 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2801 enable_mask |= I915_USER_INTERRUPT;
2802
2803 if (IS_G4X(dev))
2804 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2805
b79480ba
DV		 2806 /* Interrupt setup is already guaranteed to be single-threaded, this is
2807 * just to make the assert_spin_locked check happy. */
2808 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 2809 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 2810 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 2811
a266c7d5
CW		 2812 /*
2813 * Enable some error detection, note the instruction error mask
2814 * bit is reserved, so we leave it masked.
2815 */
2816 if (IS_G4X(dev)) {
2817 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2818 GM45_ERROR_MEM_PRIV |
2819 GM45_ERROR_CP_PRIV |
2820 I915_ERROR_MEMORY_REFRESH);
2821 } else {
2822 error_mask = ~(I915_ERROR_PAGE_TABLE |
2823 I915_ERROR_MEMORY_REFRESH);
2824 }
2825 I915_WRITE(EMR, error_mask);
2826
2827 I915_WRITE(IMR, dev_priv->irq_mask);
2828 I915_WRITE(IER, enable_mask);
2829 POSTING_READ(IER);
2830
20afbda2
DV		 2831 I915_WRITE(PORT_HOTPLUG_EN, 0);
2832 POSTING_READ(PORT_HOTPLUG_EN);
2833
f49e38dd 2834 i915_enable_asle_pipestat(dev);
20afbda2
DV		 2835
2836 return 0;
2837}
2838
bac56d5b 2839static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 2840{
2841 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 2842 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 2843 struct intel_encoder *intel_encoder;
20afbda2
DV		 2844 u32 hotplug_en;
2845
b5ea2d56
DV		 2846 assert_spin_locked(&dev_priv->irq_lock);
2847
bac56d5b
EE		 2848 if (I915_HAS_HOTPLUG(dev)) {
2849 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2850 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2851 /* Note HDMI and DP share hotplug bits */
e5868a31 2852 /* enable bits are the same for all generations */
cd569aed
EE		 2853 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2854 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2855 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 2856 /* Programming the CRT detection parameters tends
2857 to generate a spurious hotplug event about three
2858 seconds later. So just do it once.
2859 */
2860 if (IS_G4X(dev))
2861 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 2862 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 2863 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 2864
bac56d5b
EE		 2865 /* Ignore TV since it's buggy */
2866 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2867 }
a266c7d5
CW		 2868}
2869
ff1f525e 2870static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2871{
2872 struct drm_device *dev = (struct drm_device *) arg;
2873 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2874 u32 iir, new_iir;
2875 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2876 unsigned long irqflags;
2877 int irq_received;
2878 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2879 u32 flip_mask =
2880 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2881 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2882
2883 atomic_inc(&dev_priv->irq_received);
2884
2885 iir = I915_READ(IIR);
2886
a266c7d5 2887 for (;;) {
2c8ba29f
CW		 2888 bool blc_event = false;
2889
21ad8330 2890 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2891
2892 /* Can't rely on pipestat interrupt bit in iir as it might
2893 * have been cleared after the pipestat interrupt was received.
2894 * It doesn't set the bit in iir again, but it still produces
2895 * interrupts (for non-MSI).
2896 */
2897 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2898 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2899 i915_handle_error(dev, false);
2900
2901 for_each_pipe(pipe) {
2902 int reg = PIPESTAT(pipe);
2903 pipe_stats[pipe] = I915_READ(reg);
2904
2905 /*
2906 * Clear the PIPE*STAT regs before the IIR
2907 */
2908 if (pipe_stats[pipe] & 0x8000ffff) {
2909 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2910 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2911 pipe_name(pipe));
2912 I915_WRITE(reg, pipe_stats[pipe]);
2913 irq_received = 1;
2914 }
2915 }
2916 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2917
2918 if (!irq_received)
2919 break;
2920
2921 ret = IRQ_HANDLED;
2922
2923 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2924 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 2925 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 2926 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2927 HOTPLUG_INT_STATUS_G4X :
4f7fd709 2928 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 2929
2930 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2931 hotplug_status);
91d131d2
DV		 2932
2933 intel_hpd_irq_handler(dev, hotplug_trigger,
2934 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
2935
a266c7d5
CW		 2936 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2937 I915_READ(PORT_HOTPLUG_STAT);
2938 }
2939
21ad8330 2940 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2941 new_iir = I915_READ(IIR); /* Flush posted writes */
2942
a266c7d5
CW		 2943 if (iir & I915_USER_INTERRUPT)
2944 notify_ring(dev, &dev_priv->ring[RCS]);
2945 if (iir & I915_BSD_USER_INTERRUPT)
2946 notify_ring(dev, &dev_priv->ring[VCS]);
2947
a266c7d5 2948 for_each_pipe(pipe) {
2c8ba29f 2949 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2950 i915_handle_vblank(dev, pipe, pipe, iir))
2951 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2952
2953 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2954 blc_event = true;
2955 }
2956
2957
2958 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2959 intel_opregion_asle_intr(dev);
2960
515ac2bb
DV		 2961 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2962 gmbus_irq_handler(dev);
2963
a266c7d5
CW		 2964 /* With MSI, interrupts are only generated when iir
2965 * transitions from zero to nonzero. If another bit got
2966 * set while we were handling the existing iir bits, then
2967 * we would never get another interrupt.
2968 *
2969 * This is fine on non-MSI as well, as if we hit this path
2970 * we avoid exiting the interrupt handler only to generate
2971 * another one.
2972 *
2973 * Note that for MSI this could cause a stray interrupt report
2974 * if an interrupt landed in the time between writing IIR and
2975 * the posting read. This should be rare enough to never
2976 * trigger the 99% of 100,000 interrupts test for disabling
2977 * stray interrupts.
2978 */
2979 iir = new_iir;
2980 }
2981
d05c617e 2982 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2983
a266c7d5
CW		 2984 return ret;
2985}
2986
2987static void i965_irq_uninstall(struct drm_device * dev)
2988{
2989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2990 int pipe;
2991
2992 if (!dev_priv)
2993 return;
2994
ac4c16c5
EE		 2995 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2996
adca4730
CW		 2997 I915_WRITE(PORT_HOTPLUG_EN, 0);
2998 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2999
3000 I915_WRITE(HWSTAM, 0xffffffff);
3001 for_each_pipe(pipe)
3002 I915_WRITE(PIPESTAT(pipe), 0);
3003 I915_WRITE(IMR, 0xffffffff);
3004 I915_WRITE(IER, 0x0);
3005
3006 for_each_pipe(pipe)
3007 I915_WRITE(PIPESTAT(pipe),
3008 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3009 I915_WRITE(IIR, I915_READ(IIR));
3010}
3011
ac4c16c5
EE		 3012static void i915_reenable_hotplug_timer_func(unsigned long data)
3013{
3014 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3015 struct drm_device *dev = dev_priv->dev;
3016 struct drm_mode_config *mode_config = &dev->mode_config;
3017 unsigned long irqflags;
3018 int i;
3019
3020 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3021 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3022 struct drm_connector *connector;
3023
3024 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3025 continue;
3026
3027 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3028
3029 list_for_each_entry(connector, &mode_config->connector_list, head) {
3030 struct intel_connector *intel_connector = to_intel_connector(connector);
3031
3032 if (intel_connector->encoder->hpd_pin == i) {
3033 if (connector->polled != intel_connector->polled)
3034 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3035 drm_get_connector_name(connector));
3036 connector->polled = intel_connector->polled;
3037 if (!connector->polled)
3038 connector->polled = DRM_CONNECTOR_POLL_HPD;
3039 }
3040 }
3041 }
3042 if (dev_priv->display.hpd_irq_setup)
3043 dev_priv->display.hpd_irq_setup(dev);
3044 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3045}
3046
f71d4af4
JB		 3047void intel_irq_init(struct drm_device *dev)
3048{
8b2e326d
CW		 3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050
3051 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3052 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3053 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3054 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3055
99584db3
DV		 3056 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3057 i915_hangcheck_elapsed,
61bac78e 3058 (unsigned long) dev);
ac4c16c5
EE		 3059 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3060 (unsigned long) dev_priv);
61bac78e 3061
97a19a24 3062 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3063
f71d4af4
JB		 3064 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3065 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3066 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3067 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3068 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3069 }
3070
c3613de9
KP		 3071 if (drm_core_check_feature(dev, DRIVER_MODESET))
3072 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3073 else
3074 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3075 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3076
7e231dbe
JB		 3077 if (IS_VALLEYVIEW(dev)) {
3078 dev->driver->irq_handler = valleyview_irq_handler;
3079 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3080 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3081 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3082 dev->driver->enable_vblank = valleyview_enable_vblank;
3083 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3084 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 3085 } else if (HAS_PCH_SPLIT(dev)) {
3086 dev->driver->irq_handler = ironlake_irq_handler;
3087 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3088 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3089 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3090 dev->driver->enable_vblank = ironlake_enable_vblank;
3091 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3092 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3093 } else {
c2798b19
CW		 3094 if (INTEL_INFO(dev)->gen == 2) {
3095 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3096 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3097 dev->driver->irq_handler = i8xx_irq_handler;
3098 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3099 } else if (INTEL_INFO(dev)->gen == 3) {
3100 dev->driver->irq_preinstall = i915_irq_preinstall;
3101 dev->driver->irq_postinstall = i915_irq_postinstall;
3102 dev->driver->irq_uninstall = i915_irq_uninstall;
3103 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3104 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3105 } else {
a266c7d5
CW		 3106 dev->driver->irq_preinstall = i965_irq_preinstall;
3107 dev->driver->irq_postinstall = i965_irq_postinstall;
3108 dev->driver->irq_uninstall = i965_irq_uninstall;
3109 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3110 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3111 }
f71d4af4
JB		 3112 dev->driver->enable_vblank = i915_enable_vblank;
3113 dev->driver->disable_vblank = i915_disable_vblank;
3114 }
3115}
20afbda2
DV		 3116
3117void intel_hpd_init(struct drm_device *dev)
3118{
3119 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3120 struct drm_mode_config *mode_config = &dev->mode_config;
3121 struct drm_connector *connector;
b5ea2d56 3122 unsigned long irqflags;
821450c6 3123 int i;
20afbda2 3124
821450c6
EE		 3125 for (i = 1; i < HPD_NUM_PINS; i++) {
3126 dev_priv->hpd_stats[i].hpd_cnt = 0;
3127 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3128 }
3129 list_for_each_entry(connector, &mode_config->connector_list, head) {
3130 struct intel_connector *intel_connector = to_intel_connector(connector);
3131 connector->polled = intel_connector->polled;
3132 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3133 connector->polled = DRM_CONNECTOR_POLL_HPD;
3134 }
b5ea2d56
DV		 3135
3136 /* Interrupt setup is already guaranteed to be single-threaded, this is
3137 * just to make the assert_spin_locked checks happy. */
3138 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3139 if (dev_priv->display.hpd_irq_setup)
3140 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3141 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3142}
Linux kernel - Deliverables
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